DSDT - Vanilla Speedstep - Generic Scope (_PR)

Brett Whinnen · September 9, 2009

Hi Guys

Please see post 71 here in ab__73's bootloader thread - regarding finding correct memory addresses for _cst. It involves some messing around with voodoo kernel but c-states wont load unless this is correct.

D.

Are you still injecting via DSDT.aml or are you using mutliple SSDT.aml files?

Next question, has anyone seen a voodoo kernel for SL? Otherwise I'll have to resurrect my 10.5.7 installation

Cheers

Brett

FKA · September 9, 2009

Are you still injecting via DSDT.aml or are you using mutliple SSDT.aml files?

Next question, has anyone seen a voodoo kernel for SL? Otherwise I'll have to resurrect my 10.5.7 installation

Cheers

Brett

too busy with work, haven't had any time to play around with this recently so sill using SSDT appended to DSDT.

D.

goodbye losers · September 9, 2009

hi,

my specs

snow leopard Chameleon-2.0-r431+10.1 bootloader

ga-965p-dq6

c2d 6700@2660MHz

i have a boot error - kernel ACPI_SMC_PlatformPlugin:PushCPU_CSTData - _CST evaluation failed. my problem is native speedstep...please can you look inside my dsdt.aml for options like speedstep?

Master Chief · September 9, 2009

Thanks for the pointers. I'll run through the SSDT from the MBP5,1 I have and compare them to mine for the OST and PDC fields.

The following lines from yours:

Processor (CPU1, 0x01, 0x00000810, 0x06)

{

OperationRegion (STBL, SystemMemory, 0xCFF8E0D0, 0x01D2)

What memory addresses are they referring to from your SSDT tables? The CST or IST?

In this case it is referring to my computers IST table, but OperationRegion can be used for anything, including yours below, but there is no need to replace them.

I did put in my own PDC and OST but that made no difference (been playing with wireless routers all day and this is the first sit down I've had). As mentioned I'll look through the SSDT-1 from an MBP5,1 and see what they are doing to load the CST and IST from SSDT...

OperationRegion (IST0, SystemMemory, DerefOf (Index (SSDT, 0x01)), DerefOf (Index (SSDT, 0x02)))

OperationRegion (CST0, SystemMemory, DerefOf (Index (SSDT, 0x07)), DerefOf (Index (SSDT, 0x08)))

(for CPU0 from mine).

Actually those are identical, and IST0 is loaded to HI0 and CST0 to HC0...

The second argument in a Load() statement is a handle (see ACPI programmers manual) which can be used to release the table. Actually, you can see that yourself by reading the second argument like this: HI0 refers to Handle IST 0 and HC0 refers to Handle CAP 0

Code snippet -> from _OST for the Dell
Store (0x06, STS0)

Store (0x0A, STS0)

For the MBP5,1

Store (0x06, Index (STS0, 0x00))

Store (0x0A, Index (STS0, 0x00))

Just the way the Store is done is different between the two SSDT's... Not sure if that is significant at all or not, thoughts?

Yes, that is different. The first call simply replaced STS0 with 0x06 while the second call replaces only the nth argument – in this case 0 – with 0x06/0x0a.

p.s. If you do happen to have SSDT tables, then by all means use that and don't go looking for anything else. Assuming that you don't have to change anything in it of course

And like I said before, that table is your key to success. Here's an example:

To anyone wondering about why there are two tables in _PSS, one called SPSS and the other NPSS; Take a look at this example:

		Method (_PSS, 0, NotSerialized)
	{
		If (LEqual (And (TYPE, 0x01), 0x01)) 
		{
			Return (NPSS)
		}
		Else
		{
			Return (SPSS)
		}
	}

Now check the table I proved to in post #71 to find this: If set, the OSPM supports the C1 "I/O then Halt" FFH sequence for multi-processor configurations. And you'll find other use of it throughout the DSDT/SSDT.

n.b. TYPE in this example is probably called differently in yours, like PDC0 for example.

You should see a similar check in method _PCT() in your SSDT – which is one of the three Performance Control objects (_PCT, _PSS and _PPC) – to differentiate between FFixedHW and SystemIO et all.

Beerkex'd · September 9, 2009

Just attaching my ACPI dump for reference. It was dumped with Lavalys Everest under Windows, and seems to be complete. The FACP is there too.

This could be interesting for anyone using a Core 2 Duo E8500 who has difficulties getting a complete dump.

I only just started looking at it, haven't tried doing anything with it yet.

P5QE_C2D8500_ACPIDUMP.zip

Of course if someone wants to take a look and help me get speedstepping working I wouldn't mind

Here's my current DSDT.

(removed)

/EDIT 09-12

Both archives updated.

/EDIT 09-19

Old attached DSDT removed - and we have liftoff - see this post:

http://www.insanelymac.com/forum/index.php...t&p=1272462

SA22C · September 9, 2009

I booted into Ubuntu and to my surprise, it was able to retrieve two ssdt tables for my system.

The thing is, they don't contain any references to c-states that I can see and if I use them in my DSDT (by adding the relevant methods to the PR scope,) I still do not see any stepping.

I've attached the tables below:

Name (NPCT, Package (0x02)
       {
           ResourceTemplate ()
           {
               Register (FFixedHW, 
                   0x40,               // Bit Width
                   0x00,               // Bit Offset
                   0x0000000000000199, // Address
                   ,)
           }, 

           ResourceTemplate ()
           {
               Register (FFixedHW, 
                   0x10,               // Bit Width
                   0x00,               // Bit Offset
                   0x0000000000000198, // Address
                   ,)
           }
       })
       Name (SPCT, Package (0x02)
       {
           ResourceTemplate ()
           {
               Register (SystemIO, 
                   0x10,               // Bit Width
                   0x00,               // Bit Offset
                   0x0000000000000900, // Address
                   ,)
           }, 

           ResourceTemplate ()
           {
               Register (SystemIO, 
                   0x10,               // Bit Width
                   0x00,               // Bit Offset
                   0x0000000000000902, // Address
                   ,)
           }
       })
       Method (_PCT, 0, NotSerialized)
       {
           If (LEqual (And (TYPE, 0x01), 0x01))
           {
               Return (NPCT)
           }
           Else
           {
               Return (SPCT)
           }
       }

       Name (XPSS, 0x02)
       Name (_PPC, 0x00)
       Name (SPSS, Package (0x02)
       {
           Package (0x06)
           {
               0x00000850, 
               0x000157C0, 
               0x0000006E, 
               0x0000000A, 
               0x00000086, 
               0x00000000
           }, 

           Package (0x06)
           {
               0x0000063C, 
               0x0000E700, 
               0x0000006E, 
               0x0000000A, 
               0x00000186, 
               0x00000001
           }
       })
       Name (NPSS, Package (0x02)
       {
           Package (0x06)
           {
               0x00000850, 
               0x000157C0, 
               0x0000000A, 
               0x0000000A, 
               0x00000828, 
               0x00000828
           }, 

           Package (0x06)
           {
               0x0000063C, 
               0x0000E700, 
               0x0000000A, 
               0x0000000A, 
               0x0000061B, 
               0x0000061B
           }
       })
       Method (_PSS, 0, NotSerialized)
       {
           If (LEqual (And (TYPE, 0x01), 0x01))
           {
               Return (NPSS)
           }
           Else
           {
               Return (SPSS)
           }
       }

       Method (_PSD, 0, NotSerialized)
       {
           If (And (CFGD, 0x01000000))
           {
               If (And (TYPE, 0x0800))
               {
                   Return (Package (0x01)
                   {
                       Package (0x05)
                       {
                           0x05, 
                           0x00, 
                           0x00, 
                           0xFE, 
                           NCPU
                       }
                   })
               }

               Return (Package (0x01)
               {
                   Package (0x05)
                   {
                       0x05, 
                       0x00, 
                       0x00, 
                       0xFC, 
                       NCPU
                   }
               })
           }

           Return (Package (0x01)
           {
               Package (0x05)
               {
                   0x05, 
                   0x00, 
                   0x00, 
                   0xFC, 
                   NCPU
               }
           })
       }

The table for CPU2 is the same.

FKA · September 9, 2009

Just attaching my SSDT dump for reference. It was dumped with Lavalys Everest under Windows, and seems to be complete.

This could be interesting for anyone using a Core 2 Duo E8500 who has difficulties getting a complete dump.

Thanks Beerkex'd

I booted into Ubuntu and to my surprise, it was able to retrieve two ssdt tables for my system.

The thing is, they don't contain any references to c-states that I can see and if I use them in my DSDT (by adding the relevant methods to the PR scope,) I still do not see any stepping.

I've attached the tables below:

Name (NPCT, Package (0x02)
       {
           ResourceTemplate ()
           {
               Register (FFixedHW, 
                   0x40,               // Bit Width
                   0x00,               // Bit Offset
                   0x0000000000000199, // Address
                   ,)
           }, 

           ResourceTemplate ()
           {
               Register (FFixedHW, 
                   0x10,               // Bit Width
                   0x00,               // Bit Offset
                   0x0000000000000198, // Address
                   ,)
           }
       })
       Name (SPCT, Package (0x02)
       {
           ResourceTemplate ()
           {
               Register (SystemIO, 
                   0x10,               // Bit Width
                   0x00,               // Bit Offset
                   0x0000000000000900, // Address
                   ,)
           }, 

           ResourceTemplate ()
           {
               Register (SystemIO, 
                   0x10,               // Bit Width
                   0x00,               // Bit Offset
                   0x0000000000000902, // Address
                   ,)
           }
       })
       Method (_PCT, 0, NotSerialized)
       {
           If (LEqual (And (TYPE, 0x01), 0x01))
           {
               Return (NPCT)
           }
           Else
           {
               Return (SPCT)
           }
       }

       Name (XPSS, 0x02)
       Name (_PPC, 0x00)
       Name (SPSS, Package (0x02)
       {
           Package (0x06)
           {
               0x00000850, 
               0x000157C0, 
               0x0000006E, 
               0x0000000A, 
               0x00000086, 
               0x00000000
           }, 

           Package (0x06)
           {
               0x0000063C, 
               0x0000E700, 
               0x0000006E, 
               0x0000000A, 
               0x00000186, 
               0x00000001
           }
       })
       Name (NPSS, Package (0x02)
       {
           Package (0x06)
           {
               0x00000850, 
               0x000157C0, 
               0x0000000A, 
               0x0000000A, 
               0x00000828, 
               0x00000828
           }, 

           Package (0x06)
           {
               0x0000063C, 
               0x0000E700, 
               0x0000000A, 
               0x0000000A, 
               0x0000061B, 
               0x0000061B
           }
       })
       Method (_PSS, 0, NotSerialized)
       {
           If (LEqual (And (TYPE, 0x01), 0x01))
           {
               Return (NPSS)
           }
           Else
           {
               Return (SPSS)
           }
       }

       Method (_PSD, 0, NotSerialized)
       {
           If (And (CFGD, 0x01000000))
           {
               If (And (TYPE, 0x0800))
               {
                   Return (Package (0x01)
                   {
                       Package (0x05)
                       {
                           0x05, 
                           0x00, 
                           0x00, 
                           0xFE, 
                           NCPU
                       }
                   })
               }

               Return (Package (0x01)
               {
                   Package (0x05)
                   {
                       0x05, 
                       0x00, 
                       0x00, 
                       0xFC, 
                       NCPU
                   }
               })
           }

           Return (Package (0x01)
           {
               Package (0x05)
               {
                   0x05, 
                   0x00, 
                   0x00, 
                   0xFC, 
                   NCPU
               }
           })
       }

The table for CPU2 is the same.

Quite likely you MB doesn't support c-states. I've not managed to find any for my GA EP35 DS4 either.

Is this from your Desktop of Portable rig??

I presume you have amended to suit your CPU, the data for the 2 p-states listed under SPSS and NPSS?

D

Master Chief · September 9, 2009

Quite likely you MB doesn't support c-states. I've not managed to find any for my GA EP35 DS4 either.

He could check this by dumping the FACP table from his ACPI output. Below you'll find a dump of my previous P5K PRO BIOS (1002):

/*
* Intel ACPI Component Architecture
* AML Disassembler version 20080926
*
* Disassembly of FACP.dat, Wed Sep  9 20:09:40 2009
*
* ACPI Data Table [FACP]
*
* Format: [HexOffset DecimalOffset ByteLength]  FieldName : FieldValue
*/

[000h 000  4]                    Signature : "FACP"    /* Fixed ACPI Description Table */
[004h 004  4]                 Table Length : 000000F4
[008h 008  1]                     Revision : 03
[009h 009  1]                     Checksum : 6D
[00Ah 010  6]                       Oem ID : "A_M_I_"
[010h 016  8]                 Oem Table ID : "OEMFACP "
[018h 024  4]                 Oem Revision : 12000816
[01Ch 028  4]              Asl Compiler ID : "MSFT"
[020h 032  4]        Asl Compiler Revision : 00000097

[024h 036  4]                 FACS Address : CFF8E000
[028h 040  4]                 DSDT Address : 00DDE000
[02Ch 044  1]                        Model : 01
[02Dh 045  1]                   PM Profile : 01
[02Eh 046  2]                SCI Interrupt : 0009
[030h 048  4]             SMI Command Port : 000000B2
[034h 052  1]            ACPI Enable Value : E1
[035h 053  1]           ACPI Disable Value : 1E
[036h 054  1]               S4BIOS Command : 00
[037h 055  1]              P-State Control : E2
[038h 056  4]     PM1A Event Block Address : 00000800
[03Ch 060  4]     PM1B Event Block Address : 00000000
[040h 064  4]   PM1A Control Block Address : 00000804
[044h 068  4]   PM1B Control Block Address : 00000000
[048h 072  4]    PM2 Control Block Address : 00000000
[04Ch 076  4]       PM Timer Block Address : 00000808
[050h 080  4]           GPE0 Block Address : 00000820
[054h 084  4]           GPE1 Block Address : 00000000
[058h 088  1]       PM1 Event Block Length : 04
[059h 089  1]     PM1 Control Block Length : 02
[05Ah 090  1]     PM2 Control Block Length : 00
[05Bh 091  1]        PM Timer Block Length : 04
[05Ch 092  1]            GPE0 Block Length : 10
[05Dh 093  1]            GPE1 Block Length : 00
[05Eh 094  1]             GPE1 Base Offset : 00
[05Fh 095  1]                 _CST Support : E3
[060h 096  2]                   C2 Latency : 0065
[062h 098  2]                   C3 Latency : 03E9
[064h 100  2]               CPU Cache Size : 0400
[066h 102  2]           Cache Flush Stride : 0010
[068h 104  1]            Duty Cycle Offset : 01
[069h 105  1]             Duty Cycle Width : 00
[06Ah 106  1]          RTC Day Alarm Index : 0D
[06Bh 107  1]        RTC Month Alarm Index : 00
[06Ch 108  1]            RTC Century Index : 32
[06Dh 109  2]      Boot Architecture Flags : 0003
[06Fh 111  1]                     Reserved : 00
[070h 112  4]        Flags (decoded below) : 000000A5
                    WBINVD is operational : 1
               WBINVD does not invalidate : 0
                      All CPUs support C1 : 1
                    C2 works on MP system : 0
                  Power button is generic : 0
                  Sleep button is generic : 1
                     RTC wakeup not fixed : 0
               RTC wakeup/S4 not possible : 1
                          32-bit PM Timer : 0
                        Docking Supported : 0
                 Reset Register Supported : 0
                              Sealed Case : 0
                      Headless - No Video : 0
               Native instr after SLP_TYP : 0
                     PCIEXP_WAK Supported : 0
                       Use Platform Timer : 0
                   RTC_STS valid after S4 : 0
                  Remote Power-on capable : 0
                       APIC Cluster Model : 0
                  APIC Physical Dest Mode : 0

[074h 116 12]               Reset Register : <Generic Address Structure>
[074h 116  1]                     Space ID : 01 (SystemIO)
[075h 117  1]                    Bit Width : 08
[076h 118  1]                   Bit Offset : 00
[077h 119  1]                 Access Width : 00
[078h 120  8]                      Address : 0000000000000CF9
Invalid zero length subtable

[080h 128  1]         Value to cause reset : 06
[081h 129  3]                     Reserved : 000000
[084h 132  8]                 FACS Address : 00000000CFF8E000
[08Ch 140  8]                 DSDT Address : 0000000000DDE000
[094h 148 12]             PM1A Event Block : <Generic Address Structure>
[094h 148  1]                     Space ID : 01 (SystemIO)
[095h 149  1]                    Bit Width : 20
[096h 150  1]                   Bit Offset : 00
[097h 151  1]                 Access Width : 00
[098h 152  8]                      Address : 0000000000000800
Invalid zero length subtable

[0A0h 160 12]             PM1B Event Block : <Generic Address Structure>
[0A0h 160  1]                     Space ID : 01 (SystemIO)
[0A1h 161  1]                    Bit Width : 20
[0A2h 162  1]                   Bit Offset : 00
[0A3h 163  1]                 Access Width : 00
[0A4h 164  8]                      Address : 0000000000000000
Invalid zero length subtable

[0ACh 172 12]           PM1A Control Block : <Generic Address Structure>
[0ACh 172  1]                     Space ID : 01 (SystemIO)
[0ADh 173  1]                    Bit Width : 10
[0AEh 174  1]                   Bit Offset : 00
[0AFh 175  1]                 Access Width : 00
[0B0h 176  8]                      Address : 0000000000000804
Invalid zero length subtable

[0B8h 184 12]           PM1B Control Block : <Generic Address Structure>
[0B8h 184  1]                     Space ID : 00 (SystemMemory)
[0B9h 185  1]                    Bit Width : 00
[0BAh 186  1]                   Bit Offset : 00
[0BBh 187  1]                 Access Width : 00
[0BCh 188  8]                      Address : 0000000000000000
Invalid zero length subtable

[0C4h 196 12]            PM2 Control Block : <Generic Address Structure>
[0C4h 196  1]                     Space ID : 00 (SystemMemory)
[0C5h 197  1]                    Bit Width : 00
[0C6h 198  1]                   Bit Offset : 00
[0C7h 199  1]                 Access Width : 00
[0C8h 200  8]                      Address : 0000000000000000
Invalid zero length subtable

[0D0h 208 12]               PM Timer Block : <Generic Address Structure>
[0D0h 208  1]                     Space ID : 01 (SystemIO)
[0D1h 209  1]                    Bit Width : 20
[0D2h 210  1]                   Bit Offset : 00
[0D3h 211  1]                 Access Width : 00
[0D4h 212  8]                      Address : 0000000000000808
Invalid zero length subtable

[0DCh 220 12]                   GPE0 Block : <Generic Address Structure>
[0DCh 220  1]                     Space ID : 01 (SystemIO)
[0DDh 221  1]                    Bit Width : 80
[0DEh 222  1]                   Bit Offset : 00
[0DFh 223  1]                 Access Width : 00
[0E0h 224  8]                      Address : 0000000000000820
Invalid zero length subtable

[0E8h 232 12]                   GPE1 Block : <Generic Address Structure>
[0E8h 232  1]                     Space ID : 01 (SystemIO)
[0E9h 233  1]                    Bit Width : 20
[0EAh 234  1]                   Bit Offset : 00
[0EBh 235  1]                 Access Width : 00
[0ECh 236  8]                      Address : 0000000000000000
Invalid zero length subtable


Raw Table Data

 0000: 46 41 43 50 F4 00 00 00 03 6D 41 5F 4D 5F 49 5F  FACP.....mA_M_I_
 0010: 4F 45 4D 46 41 43 50 20 16 08 00 12 4D 53 46 54  OEMFACP ....MSFT
 0020: 97 00 00 00 00 E0 F8 CF 00 E0 DD 00 01 01 09 00  ................
 0030: B2 00 00 00 E1 1E 00 E2 00 08 00 00 00 00 00 00  ................
 0040: 04 08 00 00 00 00 00 00 00 00 00 00 08 08 00 00  ................
 0050: 20 08 00 00 00 00 00 00 04 02 00 04 10 00 00 E3   ...............
 0060: 65 00 E9 03 00 04 10 00 01 00 0D 00 32 03 00 00  e...........2...
 0070: A5 00 00 00 01 08 00 00 F9 0C 00 00 00 00 00 00  ................
 0080: 06 00 00 00 00 E0 F8 CF 00 00 00 00 00 E0 DD 00  ................
 0090: 00 00 00 00 01 20 00 00 00 08 00 00 00 00 00 00  ..... ..........
 00A0: 01 20 00 00 00 00 00 00 00 00 00 00 01 10 00 00  . ..............
 00B0: 04 08 00 00 00 00 00 00 00 00 00 00 00 00 00 00  ................
 00C0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00  ................
 00D0: 01 20 00 00 08 08 00 00 00 00 00 00 01 80 00 00  . ..............
 00E0: 20 08 00 00 00 00 00 00 01 20 00 00 00 00 00 00   ........ ......
 00F0: 00 00 00 00                                      ....

Which also gives you the required C-State latency for C2 and C3 (which you need to get C-States going).

Note: The most significant change in BIOS 1303 was a changed DSDT address (00DDE000 -> CFF80440).

WinstonAce · September 9, 2009

Hello

attached are my dsdt.dsl (which compile and work fine) and the ssdt tables (in dsl format with // where needed).

my ssdt table have 2 CPUIST 8 CPUCST and 1 CPUPM

no matter what I tried I can't compile the dsdt after merging the ssdt table into it

I always get the same error:

^ syntax error, unexpected PARSEOP_SCOPE, expecting $end

can someone help with that?

the motherboard is EP45-UD3R with bios F-11

dsdt_ssdt.zip

FKA · September 9, 2009

Hello
attached are my dsdt.dsl (which compile and work fine) and the ssdt tables (in dsl format with // where needed).

my ssdt table have 2 CPUIST 8 CPUCST and 1 CPUPM

no matter what I tried I can't compile the dsdt after merging the ssdt table into it

I always get the same error:

can someone help with that?

the motherboard is EP45-UD3R with bios F-11

what line is the error on?

##EDIT ##

might help if you post the merged dsdt

WinstonAce · September 9, 2009

- Simple GUI for ASL Optimizing Compiler -
-- iasl Me --

v1.0 © cVad 2009.

www.applelife.ru

Task:

Compile

"/Users/omri/Desktop/untitled folder/dsdt.dsl"

to

"/Users/omri/Desktop/untitled folder/Sessions/2009-09-09-221315/dsdt.aml"

Start working...

Compiling ... Done.

Intel ACPI Component Architecture

ASL Optimizing Compiler version 20080926 [Oct 4 2008]

Copyright © 2000 - 2008 Intel Corporation

Supports ACPI Specification Revision 3.0a

/Users/omri/Desktop/untitled folder/dsdt.dsl 599: CreateDWordField (BUF0, \_SB.PCI0._CRS._Y00._MIN, TCMM)

Optimize 6057 - NamePath optimized ^ (_Y00._MIN)

/Users/omri/Desktop/untitled folder/dsdt.dsl 600: CreateDWordField (BUF0, \_SB.PCI0._CRS._Y00._LEN, TOMM)

Optimize 6057 - NamePath optimized ^ (_Y00._LEN)

/Users/omri/Desktop/untitled folder/dsdt.dsl 3550: CreateByteField (BUF0, \_SB.PCI0.PX40.FDC0._CRS._Y01._MIN, IOLO)

Optimize 6057 - NamePath optimized ^ (_Y01._MIN)

/Users/omri/Desktop/untitled folder/dsdt.dsl 3552: CreateByteField (BUF0, \_SB.PCI0.PX40.FDC0._CRS._Y01._MAX, IORL)

Optimize 6057 - NamePath optimized ^ (_Y01._MAX)

/Users/omri/Desktop/untitled folder/dsdt.dsl 3650: CreateByteField (BUF1, \_SB.PCI0.PX40.UAR1._CRS._Y02._MIN, IOLO)

Optimize 6057 - NamePath optimized ^ (_Y02._MIN)

/Users/omri/Desktop/untitled folder/dsdt.dsl 3652: CreateByteField (BUF1, \_SB.PCI0.PX40.UAR1._CRS._Y02._MAX, IORL)

Optimize 6057 - NamePath optimized ^ (_Y02._MAX)

/Users/omri/Desktop/untitled folder/dsdt.dsl 3654: CreateWordField (BUF1, \_SB.PCI0.PX40.UAR1._CRS._Y03._INT, IRQW)

Optimize 6057 - NamePath optimized ^ (_Y03._INT)

/Users/omri/Desktop/untitled folder/dsdt.dsl 3823: CreateByteField (BUF5, \_SB.PCI0.PX40.LPT1._CRS._Y04._MIN, IOLO)

Optimize 6057 - NamePath optimized ^ (_Y04._MIN)

/Users/omri/Desktop/untitled folder/dsdt.dsl 3825: CreateByteField (BUF5, \_SB.PCI0.PX40.LPT1._CRS._Y04._MAX, IORL)

Optimize 6057 - NamePath optimized ^ (_Y04._MAX)

/Users/omri/Desktop/untitled folder/dsdt.dsl 3827: CreateByteField (BUF5, \_SB.PCI0.PX40.LPT1._CRS._Y04._LEN, IOLE)

Optimize 6057 - NamePath optimized ^ (_Y04._LEN)

/Users/omri/Desktop/untitled folder/dsdt.dsl 3828: CreateWordField (BUF5, \_SB.PCI0.PX40.LPT1._CRS._Y05._INT, IRQW)

Optimize 6057 - NamePath optimized ^ (_Y05._INT)

/Users/omri/Desktop/untitled folder/dsdt.dsl 3976: CreateByteField (BUF6, \_SB.PCI0.PX40.ECP1._CRS._Y06._MIN, IOLO)

Optimize 6057 - NamePath optimized ^ (_Y06._MIN)

/Users/omri/Desktop/untitled folder/dsdt.dsl 3978: CreateByteField (BUF6, \_SB.PCI0.PX40.ECP1._CRS._Y06._MAX, IORL)

Optimize 6057 - NamePath optimized ^ (_Y06._MAX)

/Users/omri/Desktop/untitled folder/dsdt.dsl 3980: CreateByteField (BUF6, \_SB.PCI0.PX40.ECP1._CRS._Y06._LEN, IOLE)

Optimize 6057 - NamePath optimized ^ (_Y06._LEN)

/Users/omri/Desktop/untitled folder/dsdt.dsl 3981: CreateByteField (BUF6, \_SB.PCI0.PX40.ECP1._CRS._Y07._MIN, IOEL)

Optimize 6057 - NamePath optimized ^ (_Y07._MIN)

/Users/omri/Desktop/untitled folder/dsdt.dsl 3983: CreateByteField (BUF6, \_SB.PCI0.PX40.ECP1._CRS._Y07._MAX, IOML)

Optimize 6057 - NamePath optimized ^ (_Y07._MAX)

/Users/omri/Desktop/untitled folder/dsdt.dsl 3985: CreateWordField (BUF6, \_SB.PCI0.PX40.ECP1._CRS._Y08._INT, IRQW)

Optimize 6057 - NamePath optimized ^ (_Y08._INT)

/Users/omri/Desktop/untitled folder/dsdt.dsl 3986: CreateByteField (BUF6, \_SB.PCI0.PX40.ECP1._CRS._Y09._DMA, DMAC)

Optimize 6057 - NamePath optimized ^ (_Y09._DMA)

/Users/omri/Desktop/untitled folder/dsdt.dsl 5781: CreateDWordField (BUF0, \_SB.MEM._CRS._Y0A._BAS, ACMM)

Optimize 6057 - NamePath optimized ^ (_Y0A._BAS)

/Users/omri/Desktop/untitled folder/dsdt.dsl 5782: CreateDWordField (BUF0, \_SB.MEM._CRS._Y0A._LEN, ASSM)

Optimize 6057 - NamePath optimized ^ (_Y0A._LEN)

/Users/omri/Desktop/untitled folder/dsdt.dsl 5783: CreateDWordField (BUF0, \_SB.MEM._CRS._Y0B._BAS, RMA1)

Optimize 6057 - NamePath optimized ^ (_Y0B._BAS)

/Users/omri/Desktop/untitled folder/dsdt.dsl 5784: CreateDWordField (BUF0, \_SB.MEM._CRS._Y0B._LEN, RSS1)

Optimize 6057 - NamePath optimized ^ (_Y0B._LEN)

/Users/omri/Desktop/untitled folder/dsdt.dsl 5785: CreateDWordField (BUF0, \_SB.MEM._CRS._Y0C._BAS, RMA2)

Optimize 6057 - NamePath optimized ^ (_Y0C._BAS)

/Users/omri/Desktop/untitled folder/dsdt.dsl 5786: CreateDWordField (BUF0, \_SB.MEM._CRS._Y0C._LEN, RSS2)

Optimize 6057 - NamePath optimized ^ (_Y0C._LEN)

/Users/omri/Desktop/untitled folder/dsdt.dsl 5787: CreateDWordField (BUF0, \_SB.MEM._CRS._Y0D._BAS, RMA3)

Optimize 6057 - NamePath optimized ^ (_Y0D._BAS)

/Users/omri/Desktop/untitled folder/dsdt.dsl 5788: CreateDWordField (BUF0, \_SB.MEM._CRS._Y0D._LEN, RSS3)

Optimize 6057 - NamePath optimized ^ (_Y0D._LEN)

/Users/omri/Desktop/untitled folder/dsdt.dsl 5789: CreateDWordField (BUF0, \_SB.MEM._CRS._Y0E._BAS, RMA4)

Optimize 6057 - NamePath optimized ^ (_Y0E._BAS)

/Users/omri/Desktop/untitled folder/dsdt.dsl 5790: CreateDWordField (BUF0, \_SB.MEM._CRS._Y0E._LEN, RSS4)

Optimize 6057 - NamePath optimized ^ (_Y0E._LEN)

/Users/omri/Desktop/untitled folder/dsdt.dsl 5791: CreateDWordField (BUF0, \_SB.MEM._CRS._Y0F._BAS, ERMA)

Optimize 6057 - NamePath optimized ^ (_Y0F._BAS)

/Users/omri/Desktop/untitled folder/dsdt.dsl 5792: CreateDWordField (BUF0, \_SB.MEM._CRS._Y0F._LEN, ERMS)

Optimize 6057 - NamePath optimized ^ (_Y0F._LEN)

/Users/omri/Desktop/untitled folder/dsdt.dsl 5793: CreateDWordField (BUF0, \_SB.MEM._CRS._Y10._LEN, EXTM)

Optimize 6057 - NamePath optimized ^ (_Y10._LEN)

/Users/omri/Desktop/untitled folder/dsdt.dsl 5946: Scope {

Error 4095 - ^ syntax error, unexpected PARSEOP_SCOPE, expecting $end

ASL Input: /Users/omri/Desktop/untitled folder/dsdt.dsl - 7776 lines, 254284 bytes, 2367 keywords

Compilation complete. 1 Errors, 0 Warnings, 0 Remarks, 31 Optimizations

All done.

Enjoy ...

dsdt.dsl.zip

SA22C · September 9, 2009

The data for the P-states listed in the NPSS and SPSS methods appeared to match up with my processor's capabilities, so I left it alone. As for the C-State latency, that's pretty neat but I don't have any IST tables or c-states from my motherboard. How would I go about adapting the tables from the Mac Pro to work with my system?

Brett Whinnen · September 9, 2009

Check your brackets. I would say you've inserted one too many '}' when you've pasted in and are closing off a method or similar early...

Chrysaor · September 9, 2009

Modified MSR Tools to run on Snow Leopard. You can see the steppings if you have P-states support.

MSR_Tools.app.zip

FKA · September 9, 2009

Hello
attached are my dsdt.dsl (which compile and work fine) and the ssdt tables (in dsl format with // where needed).

my ssdt table have 2 CPUIST 8 CPUCST and 1 CPUPM

no matter what I tried I can't compile the dsdt after merging the ssdt table into it

I always get the same error:

can someone help with that?

the motherboard is EP45-UD3R with bios F-11

Hi Winston Ace

You've forgotten to comment out the last line of your DSDT

D.

WinstonAce · September 9, 2009

Thanks

I fixed the brackets and i have 4 errors due to duplicate values (two of each CPUCST)

I've tried to leave only one of each and I ended with cpu with constant multiplier of 6 (instead of 9 in "stress")

what's next?

FKA · September 9, 2009

Modified MSR Tools to run on Snow Leopard. You can see the steppings if you have P-states support.

MSR_Tools.app.zip

Fantastic - Many thanks!

Brett Whinnen · September 9, 2009

Modified MSR Tools to run on Snow Leopard. You can see the steppings if you have P-states support.

MSR_Tools.app.zip

Damn 32bit only Time for a reboot

FKA · September 9, 2009

Thanks
I fixed the brackets and i have 4 errors due to duplicate values (two of each CPUCST)

I've tried to leave only one of each and I ended with cpu with constant multiplier of 6 (instead of 9 in "stress")

what's next?

You've got a few duplicates in there - I'm sure you'll be able to work through it!

Tip:- your SSDT's seem to be broken up. i.e

Scope (\_PR.CPU1)

Method (_CST, 0, NotSerialized) is spread over 2 entries !

Rather than removing one of them try to bring the 2 together - all under the same Method (_CST, 0, NotSerialized)

D.

Brett Whinnen · September 9, 2009

Modified MSR Tools to run on Snow Leopard. You can see the steppings if you have P-states support.

MSR_Tools.app.zip

Booted into 32bit mode and can definitely see the stepping working as expected. Nice!

WinstonAce · September 10, 2009

You've got a few duplicates in there - I'm sure you'll be able to work through it!

Tip:- your SSDT's seem to be broken up. i.e

Scope (\_PR.CPU1)

Method (_CST, 0, NotSerialized) is spread over 2 entries !

Rather than removing one of them try to bring the 2 together - all under the same Method (_CST, 0, NotSerialized)

D.

I tried your suggestions but it didn't work

whatever I tried led me to the same result -->multiplier X6 and stock voltage (1.25) not changing.

William Parker · September 10, 2009

Hi,

Really stumped here. DSDT.aml fixed everything LAN, Video, Audio, CMOS reset, USBEHCI and power button on GA-EP45-DS3R+Q9550. In Leopard 10.5.7 the same DSDT.aml allows AppleIntelCPUPowerManagement to initialize correctly and I do see temps higher by 10 deg. Centigrade. But the same DSDT.aml in SnowLeopard 10.6 causes kernel panic on boot. I have to put back the NullCPUPowermanagement.kext to get booted. everything Else is working.

Can anyone please shed some light on this.

On my way to DSDT Vanilla Speedstep, so need help please.

Thank you.

FKA · September 10, 2009

The data for the P-states listed in the NPSS and SPSS methods appeared to match up with my processor's capabilities, so I left it alone. As for the C-State latency, that's pretty neat but I don't have any IST tables or c-states from my motherboard. How would I go about adapting the tables from the Mac Pro to work with my system?

Have a look at your p-states again -

Name (SPSS, Package (0x02)
{
Package (0x06)
{
0x00000850,
0x000157C0,
0x0000006E,
0x0000000A,
0x00000086, [color="#ff0000"]//<here[/color]
0x00000000   [color="#ff0000"]// <<< here[/color]
},

Package (0x06)
{
0x0000063C,
0x0000E700,
0x0000006E,
0x0000000A,
0x00000186, [color="#ff0000"]//here[/color]
0x00000001  [color="#ff0000"]//here[/color]
}
})

These are desired and achived p-states (fid)(vid) . they're wrong.

As for c-states I got somewhere with this last night - I've actually borrowed _cst tables from a lap top that has C1, C2 and C3. The Mac Pro3,1 cst, I've used, only had C1 and C2.

I've got this to compile but managed to brick my install cocking around with the voodoo kernel to get correct cst memory addreses. Currently carbon copying back-up

I'm away on holiday tomorrow so I'll post what I've got tonight.

D.

He could check this by dumping the FACP table from his ACPI output. Below you'll find a dump of my previous P5K PRO BIOS (1002):

/*
* Intel ACPI Component Architecture
* AML Disassembler version 20080926
*
* Disassembly of FACP.dat, Wed Sep  9 20:09:40 2009
*
* ACPI Data Table [FACP]
*
* Format: [HexOffset DecimalOffset ByteLength]  FieldName : FieldValue
*/

[000h 000  4]                    Signature : "FACP"    /* Fixed ACPI Description Table */
[004h 004  4]                 Table Length : 000000F4
[008h 008  1]                     Revision : 03
[009h 009  1]                     Checksum : 6D
[00Ah 010  6]                       Oem ID : "A_M_I_"
[010h 016  8]                 Oem Table ID : "OEMFACP "
[018h 024  4]                 Oem Revision : 12000816
[01Ch 028  4]              Asl Compiler ID : "MSFT"
[020h 032  4]        Asl Compiler Revision : 00000097

[024h 036  4]                 FACS Address : CFF8E000
[028h 040  4]                 DSDT Address : 00DDE000
[02Ch 044  1]                        Model : 01
[02Dh 045  1]                   PM Profile : 01
[02Eh 046  2]                SCI Interrupt : 0009
[030h 048  4]             SMI Command Port : 000000B2
[034h 052  1]            ACPI Enable Value : E1
[035h 053  1]           ACPI Disable Value : 1E
[036h 054  1]               S4BIOS Command : 00
[037h 055  1]              P-State Control : E2
[038h 056  4]     PM1A Event Block Address : 00000800
[03Ch 060  4]     PM1B Event Block Address : 00000000
[040h 064  4]   PM1A Control Block Address : 00000804
[044h 068  4]   PM1B Control Block Address : 00000000
[048h 072  4]    PM2 Control Block Address : 00000000
[04Ch 076  4]       PM Timer Block Address : 00000808
[050h 080  4]           GPE0 Block Address : 00000820
[054h 084  4]           GPE1 Block Address : 00000000
[058h 088  1]       PM1 Event Block Length : 04
[059h 089  1]     PM1 Control Block Length : 02
[05Ah 090  1]     PM2 Control Block Length : 00
[05Bh 091  1]        PM Timer Block Length : 04
[05Ch 092  1]            GPE0 Block Length : 10
[05Dh 093  1]            GPE1 Block Length : 00
[05Eh 094  1]             GPE1 Base Offset : 00
[05Fh 095  1]                 _CST Support : E3
[060h 096  2]                   C2 Latency : 0065
[062h 098  2]                   C3 Latency : 03E9
[064h 100  2]               CPU Cache Size : 0400
[066h 102  2]           Cache Flush Stride : 0010
[068h 104  1]            Duty Cycle Offset : 01
[069h 105  1]             Duty Cycle Width : 00
[06Ah 106  1]          RTC Day Alarm Index : 0D
[06Bh 107  1]        RTC Month Alarm Index : 00
[06Ch 108  1]            RTC Century Index : 32
[06Dh 109  2]      Boot Architecture Flags : 0003
[06Fh 111  1]                     Reserved : 00
[070h 112  4]        Flags (decoded below) : 000000A5
                    WBINVD is operational : 1
               WBINVD does not invalidate : 0
                      All CPUs support C1 : 1
                    C2 works on MP system : 0
                  Power button is generic : 0
                  Sleep button is generic : 1
                     RTC wakeup not fixed : 0
               RTC wakeup/S4 not possible : 1
                          32-bit PM Timer : 0
                        Docking Supported : 0
                 Reset Register Supported : 0
                              Sealed Case : 0
                      Headless - No Video : 0
               Native instr after SLP_TYP : 0
                     PCIEXP_WAK Supported : 0
                       Use Platform Timer : 0
                   RTC_STS valid after S4 : 0
                  Remote Power-on capable : 0
                       APIC Cluster Model : 0
                  APIC Physical Dest Mode : 0

[074h 116 12]               Reset Register : <Generic Address Structure>
[074h 116  1]                     Space ID : 01 (SystemIO)
[075h 117  1]                    Bit Width : 08
[076h 118  1]                   Bit Offset : 00
[077h 119  1]                 Access Width : 00
[078h 120  8]                      Address : 0000000000000CF9
Invalid zero length subtable

[080h 128  1]         Value to cause reset : 06
[081h 129  3]                     Reserved : 000000
[084h 132  8]                 FACS Address : 00000000CFF8E000
[08Ch 140  8]                 DSDT Address : 0000000000DDE000
[094h 148 12]             PM1A Event Block : <Generic Address Structure>
[094h 148  1]                     Space ID : 01 (SystemIO)
[095h 149  1]                    Bit Width : 20
[096h 150  1]                   Bit Offset : 00
[097h 151  1]                 Access Width : 00
[098h 152  8]                      Address : 0000000000000800
Invalid zero length subtable

[0A0h 160 12]             PM1B Event Block : <Generic Address Structure>
[0A0h 160  1]                     Space ID : 01 (SystemIO)
[0A1h 161  1]                    Bit Width : 20
[0A2h 162  1]                   Bit Offset : 00
[0A3h 163  1]                 Access Width : 00
[0A4h 164  8]                      Address : 0000000000000000
Invalid zero length subtable

[0ACh 172 12]           PM1A Control Block : <Generic Address Structure>
[0ACh 172  1]                     Space ID : 01 (SystemIO)
[0ADh 173  1]                    Bit Width : 10
[0AEh 174  1]                   Bit Offset : 00
[0AFh 175  1]                 Access Width : 00
[0B0h 176  8]                      Address : 0000000000000804
Invalid zero length subtable

[0B8h 184 12]           PM1B Control Block : <Generic Address Structure>
[0B8h 184  1]                     Space ID : 00 (SystemMemory)
[0B9h 185  1]                    Bit Width : 00
[0BAh 186  1]                   Bit Offset : 00
[0BBh 187  1]                 Access Width : 00
[0BCh 188  8]                      Address : 0000000000000000
Invalid zero length subtable

[0C4h 196 12]            PM2 Control Block : <Generic Address Structure>
[0C4h 196  1]                     Space ID : 00 (SystemMemory)
[0C5h 197  1]                    Bit Width : 00
[0C6h 198  1]                   Bit Offset : 00
[0C7h 199  1]                 Access Width : 00
[0C8h 200  8]                      Address : 0000000000000000
Invalid zero length subtable

[0D0h 208 12]               PM Timer Block : <Generic Address Structure>
[0D0h 208  1]                     Space ID : 01 (SystemIO)
[0D1h 209  1]                    Bit Width : 20
[0D2h 210  1]                   Bit Offset : 00
[0D3h 211  1]                 Access Width : 00
[0D4h 212  8]                      Address : 0000000000000808
Invalid zero length subtable

[0DCh 220 12]                   GPE0 Block : <Generic Address Structure>
[0DCh 220  1]                     Space ID : 01 (SystemIO)
[0DDh 221  1]                    Bit Width : 80
[0DEh 222  1]                   Bit Offset : 00
[0DFh 223  1]                 Access Width : 00
[0E0h 224  8]                      Address : 0000000000000820
Invalid zero length subtable

[0E8h 232 12]                   GPE1 Block : <Generic Address Structure>
[0E8h 232  1]                     Space ID : 01 (SystemIO)
[0E9h 233  1]                    Bit Width : 20
[0EAh 234  1]                   Bit Offset : 00
[0EBh 235  1]                 Access Width : 00
[0ECh 236  8]                      Address : 0000000000000000
Invalid zero length subtable


Raw Table Data

 0000: 46 41 43 50 F4 00 00 00 03 6D 41 5F 4D 5F 49 5F  FACP.....mA_M_I_
 0010: 4F 45 4D 46 41 43 50 20 16 08 00 12 4D 53 46 54  OEMFACP ....MSFT
 0020: 97 00 00 00 00 E0 F8 CF 00 E0 DD 00 01 01 09 00  ................
 0030: B2 00 00 00 E1 1E 00 E2 00 08 00 00 00 00 00 00  ................
 0040: 04 08 00 00 00 00 00 00 00 00 00 00 08 08 00 00  ................
 0050: 20 08 00 00 00 00 00 00 04 02 00 04 10 00 00 E3   ...............
 0060: 65 00 E9 03 00 04 10 00 01 00 0D 00 32 03 00 00  e...........2...
 0070: A5 00 00 00 01 08 00 00 F9 0C 00 00 00 00 00 00  ................
 0080: 06 00 00 00 00 E0 F8 CF 00 00 00 00 00 E0 DD 00  ................
 0090: 00 00 00 00 01 20 00 00 00 08 00 00 00 00 00 00  ..... ..........
 00A0: 01 20 00 00 00 00 00 00 00 00 00 00 01 10 00 00  . ..............
 00B0: 04 08 00 00 00 00 00 00 00 00 00 00 00 00 00 00  ................
 00C0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00  ................
 00D0: 01 20 00 00 08 08 00 00 00 00 00 00 01 80 00 00  . ..............
 00E0: 20 08 00 00 00 00 00 00 01 20 00 00 00 00 00 00   ........ ......
 00F0: 00 00 00 00                                      ....

Which also gives you the required C-State latency for C2 and C3 (which you need to get C-States going).

Note: The most significant change in BIOS 1303 was a changed DSDT address (00DDE000 -> CFF80440).

Note if you get (as I do.) -

[**** *** *] _CST Support : 0

Your MB ACPI does not support _cst

The question is if we add _cst to the DSDT correctly - will it work?!!

D.

Master Chief · September 10, 2009

Note if you get (as I do.) -
[**** *** *] _CST Support : 0
Your MB ACPI does not support _cst

The question is if we add _cst to the DSDT correctly - will it work?!!

D.

Exactly!

BTW: The version of CPU-i that I compiled for Snow Leopard (32-bit) works here – unlike that ugly MSRTools tools thing. Even for my computer, which still shows up as: "P5K PRO" in System Profiler (I changed the ACPI plugin Info.plist). And not only that. because the 7.5 multiplier (0x4720 in my _PSS) works too!!! I am however still looking for the value for the 6.5 multiplier; the reported value in CPU-i (0x461C) doesn't seem to work here (no 6.5 showing up in CPU-i).

Hi,
Really stumped here. DSDT.aml fixed everything LAN, Video, Audio, CMOS reset, USBEHCI and power button on GA-EP45-DS3R+Q9550. In Leopard 10.5.7 the same DSDT.aml allows AppleIntelCPUPowerManagement to initialize correctly and I do see temps higher by 10 deg. Centigrade. But the same DSDT.aml in SnowLeopard 10.6 causes kernel panic on boot. I have to put back the NullCPUPowermanagement.kext to get booted. everything Else is working.

Can anyone please shed some light on this.

On my way to DSDT Vanilla Speedstep, so need help please.

Thank you.

I take it that the unmodified dsdt.dsl works with Snow Leopard? As in it fails after your changed it? Then attach both the original (working) and modified dsdt.dsl because how else should anyone here help you?

I tried your suggestions but it didn't work
whatever I tried led me to the same result -->multiplier X6 and stock voltage (1.25) not changing.

What kind of "Model Identifier:" do you see in System Profiler?

Mine still reports: "P5K PRO" and thus I modified ACPI_SMC_PlatformPlugin.kext (I simply replaced MacPro3,1" and "MacPro4,1" with "P5K PRO" in the Info.plist) to get P-stepping working.

WinstonAce · September 10, 2009

What kind of "Model Identifier:" do you see in System Profiler?

Mine still reports: "P5K PRO" and thus I modified ACPI_SMC_PlatformPlugin.kext (I simply replaced MacPro3,1" and "MacPro4,1" with "P5K PRO" in the Info.plist) to get P-stepping working.

MacPro2,1

DSDT - Vanilla Speedstep - Generic Scope (_PR)

Recommended Posts

Link to comment

Share on other sites

Link to comment

Share on other sites

Link to comment

Share on other sites

Link to comment

Share on other sites

Link to comment

Share on other sites

Link to comment

Share on other sites

Link to comment

Share on other sites

Link to comment

Share on other sites

Link to comment

Share on other sites

Link to comment

Share on other sites

Link to comment

Share on other sites

Link to comment

Share on other sites

Link to comment

Share on other sites

Link to comment

Share on other sites

Link to comment

Share on other sites

Link to comment

Share on other sites

Link to comment

Share on other sites

Link to comment

Share on other sites

Link to comment

Share on other sites

Link to comment

Share on other sites

Link to comment

Share on other sites

Link to comment

Share on other sites

Link to comment

Share on other sites

Link to comment

Share on other sites

Link to comment

Share on other sites