jalavoui Posted May 4 Share Posted May 4 (edited) guys only use -allow3d if you wanna test something or see some crashes nblue updates benmacfreak can ypu post your ioreg ? i cant find card id with 0x9a68 /* TGL */ #define INTEL_TGL_12_GT1_IDS(info) \ INTEL_VGA_DEVICE(0x9A60, info), \ INTEL_VGA_DEVICE(0x9A68, info), \ INTEL_VGA_DEVICE(0x9A70, info) #define INTEL_TGL_12_GT2_IDS(info) \ INTEL_VGA_DEVICE(0x9A40, info), \ INTEL_VGA_DEVICE(0x9A49, info), \ INTEL_VGA_DEVICE(0x9A59, info), \ INTEL_VGA_DEVICE(0x9A78, info), \ INTEL_VGA_DEVICE(0x9AC0, info), \ INTEL_VGA_DEVICE(0x9AC9, info), \ INTEL_VGA_DEVICE(0x9AD9, info), \ INTEL_VGA_DEVICE(0x9AF8, info) Edited May 9 by jalavoui 1 Link to comment Share on other sites More sharing options...
benmacfreak Posted May 4 Share Posted May 4 (edited) 8 hours ago, Mastachief said: I just tried your modified WhenverGreen without the -allow3d flag and it allows me to boot without the blackscreen issue on 14.4.1, framebuffer is enabled, if using 8a71, you get 2048MB, commands below -v keepsyms=1 debug=0x100 -wegdbg igfxfw=2 The Blackscreen after Sleep issue is still there, i have my correct efis configs on usb's, so i use the internal ssd efi for testing, it doesnt actually enter sleep i tried the same idk what to add for device property 8a71 my device ID is 9a68 and idk how to make it work tbh without someone downloading my config off me, or teamviewering into me. I'm tbh that lost. Edited May 4 by benmacfreak 1 Link to comment Share on other sites More sharing options...
benmacfreak Posted May 4 Share Posted May 4 7 hours ago, jalavoui said: guys only use -allow3d if you wanna test something or see some crashes nblue updates NootedBlue.kext.zip 29.1 kB · 3 downloads NootedBlue-master.zip 358.08 kB · 0 downloads benmacfreak can ypu post your ioreg ? i cant find card id with 0x9a68 i just tried to boot in without weg or nblue enabled, no luck. i tried adding -igfxvesa, no luck. i did a lspci -nn | grep VGA from within arch linux it does show 9A688086 as my pci dev id for my igpu Link to comment Share on other sites More sharing options...
Mastachief Posted May 4 Share Posted May 4 According to https://dgpu-docs.intel.com/devices/hardware-table.html9a68 is intel UHD under the XE Architecture, however, even googling it brings up little results only that it is TigerLake-H GT1 [uHD Graphics]benmac, please post your full lspci -nn, meaning with all the other items on it, I k ow you may not have ioreg now, but are you able to install using -igfxvesa, if so, do it and then post the ioreg, you can do a search and remove your serial before doing so. Link to comment Share on other sites More sharing options...
benmacfreak Posted May 4 Share Posted May 4 2 minutes ago, Mastachief said: According to https://dgpu-docs.intel.com/devices/hardware-table.html 9a68 is intel UHD under the XE Architecture, however, even googling it brings up no result, benmac, please post your full lspci -nn, meaning with all the other items on it, I k ow you may not have ioreg now, but are you able to install using -igfxvesa, if so, do it and then post the ioreg, you can do a search and remove your serial before doing so. Sent from my SM-N970U using Tapatalk ok should i install ventura or sonoma Link to comment Share on other sites More sharing options...
Mastachief Posted May 4 Share Posted May 4 It is a good idea to try either, Ventura would be better for testing though because you have access to even more symbios options Link to comment Share on other sites More sharing options...
benmacfreak Posted May 4 Share Posted May 4 ill try sonoma Link to comment Share on other sites More sharing options...
Mastachief Posted May 5 Share Posted May 5 It's in the GT1 tglINTEL_VGA_DEVICE(0x9A68, info), \ Link to comment Share on other sites More sharing options...
benmacfreak Posted May 5 Share Posted May 5 Just now, Mastachief said: It's in the GT1 tgl INTEL_VGA_DEVICE(0x9A68, info), \ well i just tried sonoma and ventura, no luck, installer nor installed os loads with -igfxvesa nblue on or off Link to comment Share on other sites More sharing options...
Mastachief Posted May 5 Share Posted May 5 Maybe try the whenvergreen instead of nblue? Use the last one by shl628 Link to comment Share on other sites More sharing options...
benmacfreak Posted May 5 Share Posted May 5 37 minutes ago, Mastachief said: Maybe try the whenvergreen instead of nblue? Use the last one by shl628 i did and i wasnt sure what device properties to try. what should i do for that please? Link to comment Share on other sites More sharing options...
cankiulascmnfye Posted May 5 Share Posted May 5 18 hours ago, jalavoui said: guys only use -allow3d if you wanna test something or see some crashes nblue updates NootedBlue.kext.zip 29.1 kB · 8 downloads NootedBlue-master.zip 358.08 kB · 6 downloads benmacfreak can ypu post your ioreg ? i cant find card id with 0x9a68 /* TGL */ #define INTEL_TGL_12_GT1_IDS(info) \ INTEL_VGA_DEVICE(0x9A60, info), \ INTEL_VGA_DEVICE(0x9A68, info), \ INTEL_VGA_DEVICE(0x9A70, info) #define INTEL_TGL_12_GT2_IDS(info) \ INTEL_VGA_DEVICE(0x9A40, info), \ INTEL_VGA_DEVICE(0x9A49, info), \ INTEL_VGA_DEVICE(0x9A59, info), \ INTEL_VGA_DEVICE(0x9A78, info), \ INTEL_VGA_DEVICE(0x9AC0, info), \ INTEL_VGA_DEVICE(0x9AC9, info), \ INTEL_VGA_DEVICE(0x9AD9, info), \ INTEL_VGA_DEVICE(0x9AF8, info) Great job. Do you have a repo for "Nooted Blue" which I can link to in OC-Little Translated? Link to comment Share on other sites More sharing options...
Mastachief Posted May 5 Share Posted May 5 Maybe try the device properties page from his github? The device should be 8A71 Link to comment Share on other sites More sharing options...
Shimijda Posted May 5 Share Posted May 5 Hello, I wanted to contribute to your work as tester as well. But I guess I'm mising correct SMBIOS which throws me "support.apple.com/mac/startup" error. Which SMBIOS are you all using? Greetings, -Shimijda. Link to comment Share on other sites More sharing options...
benmacfreak Posted May 6 Share Posted May 6 well guys i tried ALL day till now to get weg and nblue working on my laptop, i cant do it. I tried all versions listed here, none worked, no device property numbers listed have worked, nothing. Im beyond frustrated, i've done ALL options here, im just beyond frustrated and ready to admit defeat and grab my win11 usb and forget it without one of us facetiming me and helping me. I've reached that lvl of difficulty. Link to comment Share on other sites More sharing options...
jalavoui Posted May 6 Share Posted May 6 (edited) why no ioreg or logs ? without them we can't help there's no such code in icl gen11 int... static irq_handler_t intel_irq_handler(struct drm_i915_private *dev_priv) { if (HAS_GMCH(dev_priv)) { if (IS_CHERRYVIEW(dev_priv)) return cherryview_irq_handler; else if (IS_VALLEYVIEW(dev_priv)) return valleyview_irq_handler; else if (GRAPHICS_VER(dev_priv) == 4) return i965_irq_handler; else if (GRAPHICS_VER(dev_priv) == 3) return i915_irq_handler; else return i8xx_irq_handler; } else { if (GRAPHICS_VER_FULL(dev_priv) >= IP_VER(12, 10)) return dg1_irq_handler; else if (GRAPHICS_VER(dev_priv) >= 11) return gen11_irq_handler; else if (GRAPHICS_VER(dev_priv) >= 😎 return gen8_irq_handler; else return ilk_irq_handler; } } if icl is gen8 then static inline void gen8_master_intr_enable(void __iomem * const regs) { raw_reg_write(regs, GEN8_MASTER_IRQ, GEN8_MASTER_IRQ_CONTROL); } and we need static inline void gen11_master_intr_enable(void __iomem * const regs) { raw_reg_write(regs, GEN11_GFX_MSTR_IRQ, GEN11_MASTER_IRQ); } confirmed icl frame uses GEN8_MASTER_IRQ a lot in apple code undefined8 AppleIntelFramebufferController::hwDisableInterrupts(void) { uint uVar1; AppleIntelFramebufferController *in_RDI; _DAT_0010dd28 = _DAT_0010dd28 + 1; interruptLock(); if ((in_RDI->m_AppleIntelFramebufferController).field_0xfcc != '\0') { _DAT_0010dd30 = _DAT_0010dd30 + 1; (in_RDI->m_AppleIntelFramebufferController).field_0xfcc = 0; WriteRegister32(in_RDI,0x44200,0); DAT_0010d338 = DAT_0010d338 + 1; uVar1 = ReadRegister32(in_RDI,0xc2000); WriteRegister32(in_RDI,0xc2000,uVar1 | 0x80); WriteRegister32(in_RDI,0xc4004,0xffffffff); WriteRegister32(in_RDI,0xc400c,0); WriteRegister32(in_RDI,0xc4008,0xffffffff); WriteRegister32(in_RDI,0xc4008,0xffffffff); uVar1 = ReadRegister32(in_RDI,0xc2000); WriteRegister32(in_RDI,0xc2000,uVar1 & 0xffffff7f); WriteRegister32(in_RDI,0x44474,0xffffffff); WriteRegister32(in_RDI,0x4447c,0); WriteRegister32(in_RDI,0x44478,0xffffffff); WriteRegister32(in_RDI,0x44478,0xffffffff); WriteRegister32(in_RDI,0x44464,0xffffffff); WriteRegister32(in_RDI,0x4446c,0); WriteRegister32(in_RDI,0x44468,0xffffffff); WriteRegister32(in_RDI,0x44468,0xffffffff); WriteRegister32(in_RDI,0x44404,0xffffffff); WriteRegister32(in_RDI,0x4440c,0); WriteRegister32(in_RDI,0x44408,0xffffffff); WriteRegister32(in_RDI,0x44408,0xffffffff); WriteRegister32(in_RDI,0x44414,0xffffffff); WriteRegister32(in_RDI,0x4441c,0); WriteRegister32(in_RDI,0x44418,0xffffffff); WriteRegister32(in_RDI,0x44418,0xffffffff); WriteRegister32(in_RDI,0x44424,0xffffffff); WriteRegister32(in_RDI,0x4442c,0); WriteRegister32(in_RDI,0x44428,0xffffffff); WriteRegister32(in_RDI,0x44428,0xffffffff); } interruptUnlock(); return 0; } so... #define SOUTH_CHICKEN1 (0xc2000) #define GEN8_MASTER_IRQ (0x44200) #define SDEIMR (0xc4004) #define SDEIIR (0xc4008) #define SDEIER (0xc400c) #define GEN11_DE_HPD_ISR (0x44470) #define GEN11_DE_HPD_IMR (0x44474) #define GEN11_DE_HPD_IIR (0x44478) #define GEN11_DE_HPD_IER (0x4447c) #define GEN8_DE_MISC_ISR (0x44460) #define GEN8_DE_MISC_IMR (0x44464) #define GEN8_DE_MISC_IIR (0x44468) #define GEN8_DE_MISC_IER (0x4446c) #define GEN8_DE_PIPE_ISR_A (0x44400) #define GEN8_DE_PIPE_IMR_A (0x44404) #define GEN8_DE_PIPE_IIR_A (0x44408) #define GEN8_DE_PIPE_IER_A (0x4440c) #define GEN8_DE_PIPE_ISR_B (0x44410) #define GEN8_DE_PIPE_IMR_B (0x44414) #define GEN8_DE_PIPE_IIR_B (0x44418) #define GEN8_DE_PIPE_IER_B (0x4441c) #define GEN8_DE_PIPE_ISR_C (0x44420) #define GEN8_DE_PIPE_IMR_C (0x44424) #define GEN8_DE_PIPE_IIR_C (0x44428) #define GEN8_DE_PIPE_IER_C (0x4442c) and them undefined8 AppleIntelFramebufferController::hwDisableInterrupts(void) { uint regValue; AppleIntelFramebufferController *thisPointer; interruptCounter = interruptCounter + 1; interruptLock(); if (thisPointer->interruptEnabledFlag != '\0') { disableInterruptCounter = disableInterruptCounter + 1; thisPointer->interruptEnabledFlag = 0; WriteRegister32(thisPointer, GEN8_MASTER_IRQ, 0); miscInterruptCounter = miscInterruptCounter + 1; regValue = ReadRegister32(thisPointer, SOUTH_CHICKEN1); WriteRegister32(thisPointer, SOUTH_CHICKEN1, regValue | 0x80); WriteRegister32(thisPointer, SDEIMR, 0xffffffff); WriteRegister32(thisPointer, SDEIER, 0); WriteRegister32(thisPointer, SDEIIR, 0xffffffff); WriteRegister32(thisPointer, SDEIIR, 0xffffffff); regValue = ReadRegister32(thisPointer, SOUTH_CHICKEN1); WriteRegister32(thisPointer, SOUTH_CHICKEN1, regValue & 0xffffff7f); WriteRegister32(thisPointer, GEN11_DE_HPD_IMR, 0xffffffff); WriteRegister32(thisPointer, GEN11_DE_HPD_IER, 0); WriteRegister32(thisPointer, GEN11_DE_HPD_IIR, 0xffffffff); WriteRegister32(thisPointer, GEN11_DE_HPD_IIR, 0xffffffff); WriteRegister32(thisPointer, GEN8_DE_MISC_IMR, 0xffffffff); WriteRegister32(thisPointer, GEN8_DE_MISC_IER, 0); WriteRegister32(thisPointer, GEN8_DE_MISC_IIR, 0xffffffff); WriteRegister32(thisPointer, GEN8_DE_MISC_IIR, 0xffffffff); WriteRegister32(thisPointer, GEN8_DE_PIPE_IMR_A, 0xffffffff); WriteRegister32(thisPointer, GEN8_DE_PIPE_IER_A, 0); WriteRegister32(thisPointer, GEN8_DE_PIPE_IIR_A, 0xffffffff); WriteRegister32(thisPointer, GEN8_DE_PIPE_IIR_A, 0xffffffff); WriteRegister32(thisPointer, GEN8_DE_PIPE_IMR_B, 0xffffffff); WriteRegister32(thisPointer, GEN8_DE_PIPE_IER_B, 0); WriteRegister32(thisPointer, GEN8_DE_PIPE_IIR_B, 0xffffffff); WriteRegister32(thisPointer, GEN8_DE_PIPE_IIR_B, 0xffffffff); WriteRegister32(thisPointer, GEN8_DE_PIPE_IMR_C, 0xffffffff); WriteRegister32(thisPointer, GEN8_DE_PIPE_IER_C, 0); WriteRegister32(thisPointer, GEN8_DE_PIPE_IIR_C, 0xffffffff); WriteRegister32(thisPointer, GEN8_DE_PIPE_IIR_C, 0xffffffff); } interruptUnlock(); return 0; } Edited May 6 by jalavoui 1 Link to comment Share on other sites More sharing options...
Slice Posted May 6 Share Posted May 6 Also no signature. Link to comment Share on other sites More sharing options...
jalavoui Posted May 6 Share Posted May 6 (edited) now the undefined8 AppleIntelFramebufferController::hwEnableInterrupts(void) as this defs + some i can't find in recent linux sources this are the defs for both #define GEN11_GFX_MSTR_IRQ (0x190010) #define SOUTH_CHICKEN1 (0xc2000) #define GEN8_MASTER_IRQ (0x44200) #define PCH_PORT_HOTPLUG (0xc4030) #define SHOTPLUG_CTL_DDI (0xc4030) #define SHOTPLUG_CTL_TC (0xc4034) #define SHPD_FILTER_CNT (0xc4038) #define SDEIMR (0xc4004) #define SDEIIR (0xc4008) #define SDEIER (0xc400c) #define GEN11_DE_HPD_ISR (0x44470) #define GEN11_DE_HPD_IMR (0x44474) #define GEN11_DE_HPD_IIR (0x44478) #define GEN11_DE_HPD_IER (0x4447c) #define GEN8_DE_MISC_ISR (0x44460) #define GEN8_DE_MISC_IMR (0x44464) #define GEN8_DE_MISC_IIR (0x44468) #define GEN8_DE_MISC_IER (0x4446c) #define GEN8_DE_PIPE_ISR_A (0x44400) #define GEN8_DE_PIPE_IMR_A (0x44404) #define GEN8_DE_PIPE_IIR_A (0x44408) #define GEN8_DE_PIPE_IER_A (0x4440c) #define GEN8_DE_PIPE_ISR_B (0x44410) #define GEN8_DE_PIPE_IMR_B (0x44414) #define GEN8_DE_PIPE_IIR_B (0x44418) #define GEN8_DE_PIPE_IER_B (0x4441c) #define GEN8_DE_PIPE_ISR_C (0x44420) #define GEN8_DE_PIPE_IMR_C (0x44424) #define GEN8_DE_PIPE_IIR_C (0x44428) #define GEN8_DE_PIPE_IER_C (0x4442c) WriteRegister32(in_RDI,0x190010,0x80000000); = static inline void gen11_master_intr_enable(void __iomem * const regs) { raw_reg_write(regs, GEN11_GFX_MSTR_IRQ, GEN11_MASTER_IRQ); } this function is in apple code undefined8 AppleIntelFramebufferController::ProcessInterrupt(void) void gen11_display_irq_handler(struct drm_i915_private *i915) { void __iomem * const regs = intel_uncore_regs(&i915->uncore); const u32 disp_ctl = raw_reg_read(regs, GEN11_DISPLAY_INT_CTL); disable_rpm_wakeref_asserts(&i915->runtime_pm); /* * GEN11_DISPLAY_INT_CTL has same format as GEN8_MASTER_IRQ * for the display related bits. */ raw_reg_write(regs, GEN11_DISPLAY_INT_CTL, 0x0); gen8_de_irq_handler(i915, disp_ctl); raw_reg_write(regs, GEN11_DISPLAY_INT_CTL, GEN11_DISPLAY_IRQ_ENABLE); enable_rpm_wakeref_asserts(&i915->runtime_pm); } dam irqs https://elixir.bootlin.com/linux/latest/source/drivers/gpu/drm/i915/gt/intel_gt_irq.c Edited May 6 by jalavoui Link to comment Share on other sites More sharing options...
benmacfreak Posted May 7 Share Posted May 7 8 hours ago, jalavoui said: why no ioreg or logs ? without them we can't help there's no such code in icl gen11 int... static irq_handler_t intel_irq_handler(struct drm_i915_private *dev_priv) { if (HAS_GMCH(dev_priv)) { if (IS_CHERRYVIEW(dev_priv)) return cherryview_irq_handler; else if (IS_VALLEYVIEW(dev_priv)) return valleyview_irq_handler; else if (GRAPHICS_VER(dev_priv) == 4) return i965_irq_handler; else if (GRAPHICS_VER(dev_priv) == 3) return i915_irq_handler; else return i8xx_irq_handler; } else { if (GRAPHICS_VER_FULL(dev_priv) >= IP_VER(12, 10)) return dg1_irq_handler; else if (GRAPHICS_VER(dev_priv) >= 11) return gen11_irq_handler; else if (GRAPHICS_VER(dev_priv) >= 😎 return gen8_irq_handler; else return ilk_irq_handler; } } if icl is gen8 then static inline void gen8_master_intr_enable(void __iomem * const regs) { raw_reg_write(regs, GEN8_MASTER_IRQ, GEN8_MASTER_IRQ_CONTROL); } and we need static inline void gen11_master_intr_enable(void __iomem * const regs) { raw_reg_write(regs, GEN11_GFX_MSTR_IRQ, GEN11_MASTER_IRQ); } confirmed icl frame uses GEN8_MASTER_IRQ a lot in apple code undefined8 AppleIntelFramebufferController::hwDisableInterrupts(void) { uint uVar1; AppleIntelFramebufferController *in_RDI; _DAT_0010dd28 = _DAT_0010dd28 + 1; interruptLock(); if ((in_RDI->m_AppleIntelFramebufferController).field_0xfcc != '\0') { _DAT_0010dd30 = _DAT_0010dd30 + 1; (in_RDI->m_AppleIntelFramebufferController).field_0xfcc = 0; WriteRegister32(in_RDI,0x44200,0); DAT_0010d338 = DAT_0010d338 + 1; uVar1 = ReadRegister32(in_RDI,0xc2000); WriteRegister32(in_RDI,0xc2000,uVar1 | 0x80); WriteRegister32(in_RDI,0xc4004,0xffffffff); WriteRegister32(in_RDI,0xc400c,0); WriteRegister32(in_RDI,0xc4008,0xffffffff); WriteRegister32(in_RDI,0xc4008,0xffffffff); uVar1 = ReadRegister32(in_RDI,0xc2000); WriteRegister32(in_RDI,0xc2000,uVar1 & 0xffffff7f); WriteRegister32(in_RDI,0x44474,0xffffffff); WriteRegister32(in_RDI,0x4447c,0); WriteRegister32(in_RDI,0x44478,0xffffffff); WriteRegister32(in_RDI,0x44478,0xffffffff); WriteRegister32(in_RDI,0x44464,0xffffffff); WriteRegister32(in_RDI,0x4446c,0); WriteRegister32(in_RDI,0x44468,0xffffffff); WriteRegister32(in_RDI,0x44468,0xffffffff); WriteRegister32(in_RDI,0x44404,0xffffffff); WriteRegister32(in_RDI,0x4440c,0); WriteRegister32(in_RDI,0x44408,0xffffffff); WriteRegister32(in_RDI,0x44408,0xffffffff); WriteRegister32(in_RDI,0x44414,0xffffffff); WriteRegister32(in_RDI,0x4441c,0); WriteRegister32(in_RDI,0x44418,0xffffffff); WriteRegister32(in_RDI,0x44418,0xffffffff); WriteRegister32(in_RDI,0x44424,0xffffffff); WriteRegister32(in_RDI,0x4442c,0); WriteRegister32(in_RDI,0x44428,0xffffffff); WriteRegister32(in_RDI,0x44428,0xffffffff); } interruptUnlock(); return 0; } so... #define SOUTH_CHICKEN1 (0xc2000) #define GEN8_MASTER_IRQ (0x44200) #define SDEIMR (0xc4004) #define SDEIIR (0xc4008) #define SDEIER (0xc400c) #define GEN11_DE_HPD_ISR (0x44470) #define GEN11_DE_HPD_IMR (0x44474) #define GEN11_DE_HPD_IIR (0x44478) #define GEN11_DE_HPD_IER (0x4447c) #define GEN8_DE_MISC_ISR (0x44460) #define GEN8_DE_MISC_IMR (0x44464) #define GEN8_DE_MISC_IIR (0x44468) #define GEN8_DE_MISC_IER (0x4446c) #define GEN8_DE_PIPE_ISR_A (0x44400) #define GEN8_DE_PIPE_IMR_A (0x44404) #define GEN8_DE_PIPE_IIR_A (0x44408) #define GEN8_DE_PIPE_IER_A (0x4440c) #define GEN8_DE_PIPE_ISR_B (0x44410) #define GEN8_DE_PIPE_IMR_B (0x44414) #define GEN8_DE_PIPE_IIR_B (0x44418) #define GEN8_DE_PIPE_IER_B (0x4441c) #define GEN8_DE_PIPE_ISR_C (0x44420) #define GEN8_DE_PIPE_IMR_C (0x44424) #define GEN8_DE_PIPE_IIR_C (0x44428) #define GEN8_DE_PIPE_IER_C (0x4442c) and them undefined8 AppleIntelFramebufferController::hwDisableInterrupts(void) { uint regValue; AppleIntelFramebufferController *thisPointer; interruptCounter = interruptCounter + 1; interruptLock(); if (thisPointer->interruptEnabledFlag != '\0') { disableInterruptCounter = disableInterruptCounter + 1; thisPointer->interruptEnabledFlag = 0; WriteRegister32(thisPointer, GEN8_MASTER_IRQ, 0); miscInterruptCounter = miscInterruptCounter + 1; regValue = ReadRegister32(thisPointer, SOUTH_CHICKEN1); WriteRegister32(thisPointer, SOUTH_CHICKEN1, regValue | 0x80); WriteRegister32(thisPointer, SDEIMR, 0xffffffff); WriteRegister32(thisPointer, SDEIER, 0); WriteRegister32(thisPointer, SDEIIR, 0xffffffff); WriteRegister32(thisPointer, SDEIIR, 0xffffffff); regValue = ReadRegister32(thisPointer, SOUTH_CHICKEN1); WriteRegister32(thisPointer, SOUTH_CHICKEN1, regValue & 0xffffff7f); WriteRegister32(thisPointer, GEN11_DE_HPD_IMR, 0xffffffff); WriteRegister32(thisPointer, GEN11_DE_HPD_IER, 0); WriteRegister32(thisPointer, GEN11_DE_HPD_IIR, 0xffffffff); WriteRegister32(thisPointer, GEN11_DE_HPD_IIR, 0xffffffff); WriteRegister32(thisPointer, GEN8_DE_MISC_IMR, 0xffffffff); WriteRegister32(thisPointer, GEN8_DE_MISC_IER, 0); WriteRegister32(thisPointer, GEN8_DE_MISC_IIR, 0xffffffff); WriteRegister32(thisPointer, GEN8_DE_MISC_IIR, 0xffffffff); WriteRegister32(thisPointer, GEN8_DE_PIPE_IMR_A, 0xffffffff); WriteRegister32(thisPointer, GEN8_DE_PIPE_IER_A, 0); WriteRegister32(thisPointer, GEN8_DE_PIPE_IIR_A, 0xffffffff); WriteRegister32(thisPointer, GEN8_DE_PIPE_IIR_A, 0xffffffff); WriteRegister32(thisPointer, GEN8_DE_PIPE_IMR_B, 0xffffffff); WriteRegister32(thisPointer, GEN8_DE_PIPE_IER_B, 0); WriteRegister32(thisPointer, GEN8_DE_PIPE_IIR_B, 0xffffffff); WriteRegister32(thisPointer, GEN8_DE_PIPE_IIR_B, 0xffffffff); WriteRegister32(thisPointer, GEN8_DE_PIPE_IMR_C, 0xffffffff); WriteRegister32(thisPointer, GEN8_DE_PIPE_IER_C, 0); WriteRegister32(thisPointer, GEN8_DE_PIPE_IIR_C, 0xffffffff); WriteRegister32(thisPointer, GEN8_DE_PIPE_IIR_C, 0xffffffff); } interruptUnlock(); return 0; } well i was hella frustrated and burnt out yesterday. ill get them for you tonight it's 8:24pm here, i got so mad last night i wiped my install in my haze of frustration BUT ill get it reinstalled now and get you pastes of my ioreg etc. Link to comment Share on other sites More sharing options...
jkbuha Posted May 8 Share Posted May 8 (edited) On 5/4/2024 at 1:02 PM, jalavoui said: guys only use -allow3d if you wanna test something or see some crashes nblue updates NootedBlue.kext.zip 29.56 kB · 4 downloads NootedBlue-master.zip 358.8 kB · 4 downloads benmacfreak can ypu post your ioreg ? i cant find card id with 0x9a68 /* TGL */ #define INTEL_TGL_12_GT1_IDS(info) \ INTEL_VGA_DEVICE(0x9A60, info), \ INTEL_VGA_DEVICE(0x9A68, info), \ INTEL_VGA_DEVICE(0x9A70, info) #define INTEL_TGL_12_GT2_IDS(info) \ INTEL_VGA_DEVICE(0x9A40, info), \ INTEL_VGA_DEVICE(0x9A49, info), \ INTEL_VGA_DEVICE(0x9A59, info), \ INTEL_VGA_DEVICE(0x9A78, info), \ INTEL_VGA_DEVICE(0x9AC0, info), \ INTEL_VGA_DEVICE(0x9AC9, info), \ INTEL_VGA_DEVICE(0x9AD9, info), \ INTEL_VGA_DEVICE(0x9AF8, info) Just stumbled across this project now, great achievement! I've been running a setup with a Dell Alder Lake laptop on macOS (via an RX 6950 XT eGPU setup) for over a year now, can't wait to use it with the LVDS display too! Using this kext gives me a slightly different About text, which means the Xe (ID: 46A6) is detected, but I still have only 8MB of VRAM. Do the boot-args need to be modified? Edit: attached ioreg XPS 9520 Macbook Air.ioreg.zip Edited May 8 by jkbuha screenshot Link to comment Share on other sites More sharing options...
jalavoui Posted May 8 Share Posted May 8 (edited) only ids tested is tgl you can add other ids to the info.plist of nblue/whatevergreen you can also try other kexts that are used in this thread like i2c, etc just check info.plist ids /* ADL-S */ #define INTEL_ADLS_IDS(info) \ INTEL_VGA_DEVICE(0x4680, info), \ INTEL_VGA_DEVICE(0x4682, info), \ INTEL_VGA_DEVICE(0x4688, info), \ INTEL_VGA_DEVICE(0x468A, info), \ INTEL_VGA_DEVICE(0x468B, info), \ INTEL_VGA_DEVICE(0x4690, info), \ INTEL_VGA_DEVICE(0x4692, info), \ INTEL_VGA_DEVICE(0x4693, info) /* ADL-P */ #define INTEL_ADLP_IDS(info) \ INTEL_VGA_DEVICE(0x46A0, info), \ INTEL_VGA_DEVICE(0x46A1, info), \ INTEL_VGA_DEVICE(0x46A2, info), \ INTEL_VGA_DEVICE(0x46A3, info), \ INTEL_VGA_DEVICE(0x46A6, info), \ INTEL_VGA_DEVICE(0x46A8, info), \ INTEL_VGA_DEVICE(0x46AA, info), \ INTEL_VGA_DEVICE(0x462A, info), \ INTEL_VGA_DEVICE(0x4626, info), \ INTEL_VGA_DEVICE(0x4628, info), \ INTEL_VGA_DEVICE(0x46B0, info), \ INTEL_VGA_DEVICE(0x46B1, info), \ INTEL_VGA_DEVICE(0x46B2, info), \ INTEL_VGA_DEVICE(0x46B3, info), \ INTEL_VGA_DEVICE(0x46C0, info), \ INTEL_VGA_DEVICE(0x46C1, info), \ INTEL_VGA_DEVICE(0x46C2, info), \ INTEL_VGA_DEVICE(0x46C3, info) /* ADL-N */ #define INTEL_ADLN_IDS(info) \ INTEL_VGA_DEVICE(0x46D0, info), \ INTEL_VGA_DEVICE(0x46D1, info), \ INTEL_VGA_DEVICE(0x46D2, info), \ INTEL_VGA_DEVICE(0x46D3, info), \ INTEL_VGA_DEVICE(0x46D4, info) static void hsw_enable_pc8(struct drm_i915_private *dev_priv) { drm_dbg_kms(&dev_priv->drm, "Enabling package C8+\n"); if (HAS_PCH_LPT_LP(dev_priv)) intel_de_rmw(dev_priv, SOUTH_DSPCLK_GATE_D, PCH_LP_PARTITION_LEVEL_DISABLE, 0); lpt_disable_clkout_dp(dev_priv); hsw_disable_lcpll(dev_priv, true, true); } if (((this->m_AppleIntelFramebufferController).field_0xc15 & 2) != 0) { _DAT_000fffd8 = _DAT_000fffd8 + 1; uVar22 = ReadRegister32(this,0xc2020); WriteRegister32(this,0xc2020,uVar22 | 0x1000); } patched with Wa_14011294188 but this code exists 2x todo for 2030 icl_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal) { struct drm_i915_private *i915 = gt->i915; icl_wa_init_mcr(gt, wal); /* WaModifyGamTlbPartitioning:icl */ wa_write_clr_set(wal, GEN11_GACB_PERF_CTRL, GEN11_HASH_CTRL_MASK, GEN11_HASH_CTRL_BIT0 | GEN11_HASH_CTRL_BIT4); /* Wa_1405766107:icl * Formerly known as WaCL2SFHalfMaxAlloc */ wa_write_or(wal, GEN11_LSN_UNSLCVC, GEN11_LSN_UNSLCVC_GAFS_HALF_SF_MAXALLOC | GEN11_LSN_UNSLCVC_GAFS_HALF_CL2_MAXALLOC); /* Wa_220166154:icl * Formerly known as WaDisCtxReload */ wa_write_or(wal, GEN8_GAMW_ECO_DEV_RW_IA, GAMW_ECO_DEV_CTX_RELOAD_DISABLE); /* Wa_1406463099:icl * Formerly known as WaGamTlbPendError */ wa_write_or(wal, GAMT_CHKN_BIT_REG, GAMT_CHKN_DISABLE_L3_COH_PIPE); /* * Wa_1408615072:icl,ehl (vsunit) * Wa_1407596294:icl,ehl (hsunit) */ wa_write_or(wal, UNSLICE_UNIT_LEVEL_CLKGATE, VSUNIT_CLKGATE_DIS | HSUNIT_CLKGATE_DIS); /* Wa_1407352427:icl,ehl */ wa_write_or(wal, UNSLICE_UNIT_LEVEL_CLKGATE2, PSDUNIT_CLKGATE_DIS); /* Wa_1406680159:icl,ehl */ wa_mcr_write_or(wal, GEN11_SUBSLICE_UNIT_LEVEL_CLKGATE, GWUNIT_CLKGATE_DIS); /* Wa_1607087056:icl,ehl,jsl */ if (IS_ICELAKE(i915) || ((IS_JASPERLAKE(i915) || IS_ELKHARTLAKE(i915)) && IS_GRAPHICS_STEP(i915, STEP_A0, STEP_B0))) wa_write_or(wal, GEN11_SLICE_UNIT_LEVEL_CLKGATE, L3_CLKGATE_DIS | L3_CR2X_CLKGATE_DIS); /* * This is not a documented workaround, but rather an optimization * to reduce sampler power. */ wa_mcr_write_clr(wal, GEN10_DFR_RATIO_EN_AND_CHICKEN, DFR_DISABLE); } Edited May 10 by jalavoui Link to comment Share on other sites More sharing options...
jalavoui Posted May 9 Share Posted May 9 (edited) 1st step to setup display comes from linux (depends on the display that we have) kernel: [ 19.189451] i915 0000:00:02.0: [drm:pps_init_registers [i915]] panel power sequencer register settings: PP_ON 0x7d00001, PP_OFF 0x1f40001, PP_DIV 0x60 this translates to efi-vars or driver defaults defaults from here _DAT_00100fd0 = _DAT_00100fd0 + 1; hwGetPanelTimingProperties(); uVar1 = *(uint *)&(this->m_AppleIntelFramebufferController).field_0x1540; if (uVar1 == 0) { uVar2 = uVar4 & 0xfffffe0f; uVar1 = 0x2e409c4; uVar3 = 0x7d0834; uVar4 = 0x60; } efi-vars are from pOVar3 = (OSMetaClassBase *) (**(code **)(**(long **)(in_RDI + 0xc20) + 0x2b8)) (*(long **)(in_RDI + 0xc20),"AAPL00,PanelPowerUp"); pOVar3 = (OSMetaClassBase *) (**(code **)(**(long **)(in_RDI + 0xc20) + 0x2b8)) (*(long **)(in_RDI + 0xc20),"AAPL00,PanelPowerOn"); pOVar3 = (OSMetaClassBase *) (**(code **)(**(long **)(in_RDI + 0xc20) + 0x2b8)) (*(long **)(in_RDI + 0xc20),"AAPL00,PanelPowerDown"); pOVar3 = (OSMetaClassBase *) (**(code **)(**(long **)(in_RDI + 0xc20) + 0x2b8)) (*(long **)(in_RDI + 0xc20),"AAPL00,PanelPowerOff"); pOVar3 = (OSMetaClassBase *) (**(code **)(**(long **)(in_RDI + 0xc20) + 0x2b8)) (*(long **)(in_RDI + 0xc20),"AAPL00,PanelCycleDelay"); Edited May 9 by jalavoui Link to comment Share on other sites More sharing options...
sergANt Posted May 9 Share Posted May 9 Hello everyone. First of all, I want to thank you for the work done on Intel 11th gen. It's incredible. I had almost lost hope. According to https://dgpu-docs.intel.com/devices/hardware-table.html TigerLake graphics can have three different architectures. I'm 'lucky' owner laptop based on i7-11800h CPU, iGPU - 9a60. Its not working using last NootedBlue.kext. I tried the last three versions posted here. The results are similar to benmacfreak (same iGPU arch - 9a68) described. E.g.: Logs and ioreg: Env: - NB: MSI Pulse GL76 11UDK, CPU i7-11800h, iGPU 0x9A60, dGPU disabled in DeviceProperty section config.plist - System: MacBookPro16,2; Ventura 13.6.6 - WhenverGreen: Disabled - IGPU Device Properties: do not inject - SSDT-PNLF.aml: Disabled - boot-args: -v keepsyms=1 debug=0x100 -nbluedbg -allow3d lspci.txt ioreg.zip opencore-debug.zip I hope that together we can make the 11th gen graphics work. Link to comment Share on other sites More sharing options...
Mastachief Posted May 10 Share Posted May 10 Jala are you using dual channel or single channel memory, and should fixes be for single channel? It gets complicated as when there are dual channel memory inserted in the memory banks or soldered, it becomes UHD instead of Iris Xe in the graphics section, I'm still reading but int basically duplicated some sections of the tenth gen to 11th gen, the entire register section should have been revamped to cover the engine changes yet there isn't, I believe the GT2 is easier to work on than the others at this point. It is also more common.I'm trying to get the graphics log on Ubuntu, is there another live USB I should be using? Link to comment Share on other sites More sharing options...
jalavoui Posted May 10 Share Posted May 10 (edited) this log line might be for dual channel hardware kernel[0]: (AppleIntelICLLPGraphicsFramebuffer) [IGFB][LOG ][DISPLAY ] Value read from Mailbox for MEM_SS_INFO = 0x120\ 2024-03-15 23:43:27.505578+0000 kernel[0]: (AppleIntelICLLPGraphicsFramebuffer) [IGFB][LOG ][DISPLAY ] RAM = 0x0\ you can try use intel gpu tools from linux and check regs (some linux distros use old kernels and need update) macos code seems to ativate this based on connectors config (that i've be ignoring for a while) GEN8_MASTER_IRQ (0x00044200): 0x80000000 GEN8_GT_ISR0 (0x00044300): 0x00000000 GEN8_GT_IMR0 (0x00044304): 0x00000000 GEN8_GT_IIR0 (0x00044308): 0x00000000 GEN8_GT_IER0 (0x0004430c): 0x00000000 GEN8_GT_ISR1 (0x00044310): 0x00000000 GEN8_GT_IMR1 (0x00044314): 0x00000000 GEN8_GT_IIR1 (0x00044318): 0x00000000 GEN8_GT_IER1 (0x0004431c): 0x00000000 GEN8_GT_ISR2 (0x00044320): 0x00000000 GEN8_GT_IMR2 (0x00044324): 0x00000000 GEN8_GT_IIR2 (0x00044328): 0x00000000 GEN8_GT_IER2 (0x0004432c): 0x00000000 GEN8_GT_ISR3 (0x00044330): 0x00000000 GEN8_GT_IMR3 (0x00044334): 0x00000000 GEN8_GT_IIR3 (0x00044338): 0x00000000 GEN8_GT_IER3 (0x0004433c): 0x00000000 GEN8_DE_PIPE_ISR0 (0x00044400): 0x00000000 GEN8_DE_PIPE_IMR0 (0x00044404): 0x6f8ff07e GEN8_DE_PIPE_IIR0 (0x00044408): 0x00000000 GEN8_DE_PIPE_IER0 (0x0004440c): 0x90700f89 GEN8_DE_PIPE_ISR1 (0x00044410): 0x00000000 GEN8_DE_PIPE_IMR1 (0x00044414): 0x00000000 GEN8_DE_PIPE_IIR1 (0x00044418): 0x00000000 GEN8_DE_PIPE_IER1 (0x0004441c): 0x00000000 GEN8_DE_PIPE_ISR2 (0x00044420): 0x00000000 GEN8_DE_PIPE_IMR2 (0x00044424): 0x00000000 GEN8_DE_PIPE_IIR2 (0x00044428): 0x00000000 GEN8_DE_PIPE_IER2 (0x0004442c): 0x00000000 GEN8_DE_PORT_ISR (0x00044440): 0x00000000 GEN8_DE_PORT_IMR (0x00044444): 0xc1800000 GEN8_DE_PORT_IIR (0x00044448): 0x00000000 GEN8_DE_PORT_IER (0x0004444c): 0x00003f07 GEN8_DE_MISC_ISR (0x00044460): 0x00000000 GEN8_DE_MISC_IMR (0x00044464): 0xdb8480f8 GEN8_DE_MISC_IIR (0x00044468): 0x00000000 GEN8_DE_MISC_IER (0x0004446c): 0x00080000 GEN8_PCU_ISR (0x000444e0): 0x00000000 GEN8_PCU_IMR (0x000444e4): 0xffffffff GEN8_PCU_IIR (0x000444e8): 0x00000000 GEN8_PCU_IER (0x000444ec): 0x00000000 RENDER_IMR (0x000020a8): 0x00000000 BSD_IMR (0x000120a8): 0x00000000 BLT_IMR (0x000220a8): 0x00000000 PRIVATE_PAT1 (0x000040e0): 0x00000000 PRIVATE_PAT2 (0x000040e4): 0x00000000 PWR_WELL_BIOS (0x00045400): 0x00000001 PWR_WELL_DRIVER (0x00045404): 0x00000003 PWR_WELL_KVM (0x00045408): 0x00000000 PWR_WELL_DEBUG (0x0004540c): 0x00000001 DPLL_STATUS (0x0006c060): 0x00000000 DPLL1_CFGCR1 (0x0006c040): 0x00000000 DPLL2_CFGCR1 (0x0006c048): 0x00000000 DPLL3_CFGCR1 (0x0006c050): 0x00000000 DPLL1_CFGCR2 (0x0006c044): 0x00000000 DPLL2_CFGCR2 (0x0006c04c): 0x00000000 DPLL3_CFGCR2 (0x0006c054): 0x418a01ca DPLL_CTRL1 (0x0006c058): 0x012800e7 DPLL_CTRL2 (0x0006c05c): 0x00000300 CDCLK_CTL (0x00046000): 0x00380158 LCPLL1_CTL (0x00046010): 0xcc000000 LCPLL2_CTL (0x00046014): 0x00000000 TRANS_CLK_SEL_A (0x00046140): 0x10000000 (None) TRANS_CLK_SEL_B (0x00046144): 0x00000000 (None) TRANS_CLK_SEL_C (0x00046148): 0x00000000 (None) WRPLL_CTL1 (0x00046040): 0x00000000 WRPLL_CTL2 (0x00046060): 0x00000000 PLANE_BUF_CFG_1_A (0x0007027c): 0x07df0000 PLANE_BUF_CFG_2_A (0x0007037c): 0x00000000 PLANE_BUF_CFG_3_A (0x0007047c): 0x00000000 PLANE_NV12_BUF_CFG_1_A (0x00070278): 0x00000000 PLANE_NV12_BUF_CFG_2_A (0x00070378): 0x00000000 PLANE_NV12_BUF_CFG_3_A (0x00070478): 0x00000000 PLANE_CTL_1_A (0x00070180): 0x84000400 (enabled) PLANE_CTL_2_A (0x00070280): 0x00000000 PLANE_CTL_3_A (0x00070380): 0x00000000 PLANE_KEYMAX_1_A (0x000701a0): 0xff000000 PLANE_KEYMAX_2_A (0x000702a0): 0x00000000 PLANE_KEYMAX_3_A (0x000703a0): 0x00000000 PLANE_KEYMSK_1_A (0x00070198): 0x00000000 PLANE_KEYMSK_2_A (0x00070298): 0x00000000 PLANE_KEYMSK_3_A (0x00070398): 0x00000000 PLANE_KEYVAL_1_A (0x00070194): 0x00000000 PLANE_KEYVAL_2_A (0x00070294): 0x00000000 PLANE_KEYVAL_3_A (0x00070394): 0x00000000 PLANE_OFFSET_1_A (0x000701a4): 0x00000000 (0, 0) PLANE_OFFSET_2_A (0x000702a4): 0x00000000 PLANE_OFFSET_3_A (0x000703a4): 0x00000000 PLANE_AUX_DIST_1_A (0x000701c0): 0x00000000 PLANE_AUX_DIST_2_A (0x000702c0): 0x00000000 PLANE_AUX_DIST_3_A (0x000703c0): 0x00000000 PLANE_AUX_OFFSET_1_A (0x000701c4): 0x00000000 PLANE_AUX_OFFSET_2_A (0x000702c4): 0x00000000 PLANE_AUX_OFFSET_3_A (0x000703c4): 0x00000000 PLANE_POS_1_A (0x0007018c): 0x00000000 PLANE_POS_2_A (0x0007028c): 0x00000000 PLANE_POS_3_A (0x0007038c): 0x00000000 PLANE_SIZE_1_A (0x00070190): 0x0383063f PLANE_SIZE_2_A (0x00070290): 0x00000000 PLANE_SIZE_3_A (0x00070390): 0x00000000 PLANE_STRIDE_1_A (0x00070188): 0x0000000d (0) PLANE_STRIDE_2_A (0x00070288): 0x00000000 PLANE_STRIDE_3_A (0x00070388): 0x00000000 PLANE_SURF_1_A (0x0007019c): 0x027c0000 PLANE_SURF_2_A (0x0007029c): 0x00000000 PLANE_SURF_3_A (0x0007039c): 0x00000000 PLANE_SURFLIVE_1_A (0x000701ac): 0x00880000 PLANE_SURFLIVE_2_A (0x000702ac): 0x00000000 PLANE_SURFLIVE_3_A (0x000703ac): 0x00000000 PLANE_WM_1_A_0 (0x00070240): 0x8000400e PLANE_WM_1_A_1 (0x00070244): 0x80010039 PLANE_WM_1_A_2 (0x00070248): 0x80010039 PLANE_WM_1_A_3 (0x0007024c): 0x80010039 PLANE_WM_1_A_4 (0x00070250): 0x80010039 PLANE_WM_1_A_5 (0x00070254): 0x80014047 PLANE_WM_1_A_6 (0x00070258): 0x80020071 PLANE_WM_1_A_7 (0x0007025c): 0x80020071 PLANE_WM_2_A_0 (0x00070340): 0x00000000 PLANE_WM_2_A_1 (0x00070344): 0x00000000 PLANE_WM_2_A_2 (0x00070348): 0x00000000 PLANE_WM_2_A_3 (0x0007034c): 0x00000000 PLANE_WM_2_A_4 (0x00070350): 0x00000000 PLANE_WM_2_A_5 (0x00070354): 0x00000000 PLANE_WM_2_A_6 (0x00070358): 0x00000000 PLANE_WM_2_A_7 (0x0007035c): 0x00000000 PLANE_WM_3_A_0 (0x00070440): 0x00000000 PLANE_WM_3_A_1 (0x00070444): 0x00000000 PLANE_WM_3_A_2 (0x00070448): 0x00000000 PLANE_WM_3_A_3 (0x0007044c): 0x00000000 PLANE_WM_3_A_4 (0x00070450): 0x00000000 PLANE_WM_3_A_5 (0x00070454): 0x00000000 PLANE_WM_3_A_6 (0x00070458): 0x00000000 PLANE_WM_3_A_7 (0x0007045c): 0x00000000 PLANE_WM_TRANS_1_A (0x00070268): 0x8000001c PLANE_WM_TRANS_2_A (0x00070368): 0x00000000 PLANE_WM_TRANS_3_A (0x00070468): 0x00000000 CUR_BUF_CFG_A (0x0007017c): 0x07ff07e0 CUR_BASE_A (0x00070084): 0x010c0000 CUR_CTL_A (0x00070080): 0x00000023 CUR_FBC_CTL_A (0x000700a0): 0x00000000 CUR_POS_A (0x00070088): 0x020300e9 CUR_SURFLIVE_A (0x000700ac): 0x010c0000 CUR_WM_A_0 (0x00070140): 0x80008006 CUR_WM_A_1 (0x00070144): 0x8001000d CUR_WM_A_2 (0x00070148): 0x8001000d CUR_WM_A_3 (0x0007014c): 0x8001000d CUR_WM_A_4 (0x00070150): 0x8001000d CUR_WM_A_5 (0x00070154): 0x80014010 CUR_WM_A_6 (0x00070158): 0x80020019 CUR_WM_A_7 (0x0007015c): 0x80020019 CUR_WM_TRANS_A (0x00070168): 0x80000014 PS_CTRL_1_A (0x00068180): 0x80000000 PS_CTRL_2_A (0x00068280): 0x00000000 PS_ECC_STAT_1_A (0x000681d0): 0x00000000 PS_ECC_STAT_2_A (0x000682d0): 0x00000000 PS_HPHASE_1_A (0x00068194): 0x00003aaa PS_HPHASE_2_A (0x00068294): 0x00000000 PS_HSCALE_1_A (0x00068190): 0x00006aab PS_HSCALE_2_A (0x00068290): 0x00000708 PS_PWR_GATE_1_A (0x00068160): 0x00000000 PS_PWR_GATE_2_A (0x00068260): 0x00000000 PS_VPHASE_1_A (0x00068188): 0x00003aaa PS_VPHASE_2_A (0x00068288): 0x00000000 PS_VSCALE_1_A (0x00068184): 0x00006aab PS_VSCALE_2_A (0x00068284): 0x00000100 PS_WIN_POS_1_A (0x00068170): 0x00000000 PS_WIN_POS_2_A (0x00068270): 0x00000000 PS_WIN_SZ_1_A (0x00068174): 0x07800438 PS_WIN_SZ_2_A (0x00068274): 0x00000000 PLANE_BUF_CFG_1_B (0x0007127c): 0x00000000 PLANE_BUF_CFG_2_B (0x0007137c): 0x00000000 PLANE_BUF_CFG_3_B (0x0007147c): 0x00000000 PLANE_NV12_BUF_CFG_1_B (0x00071278): 0x00000000 PLANE_NV12_BUF_CFG_2_B (0x00071378): 0x00000000 PLANE_NV12_BUF_CFG_3_B (0x00071478): 0x00000000 PLANE_CTL_1_B (0x00071180): 0x00000000 (disabled) PLANE_CTL_2_B (0x00071280): 0x00000000 PLANE_CTL_3_B (0x00071380): 0x00000000 PLANE_KEYMAX_1_B (0x000711a0): 0x00000000 PLANE_KEYMAX_2_B (0x000712a0): 0x00000000 PLANE_KEYMAX_3_B (0x000713a0): 0x00000000 PLANE_KEYMSK_1_B (0x00071198): 0x00000000 PLANE_KEYMSK_2_B (0x00071298): 0x00000000 PLANE_KEYMSK_3_B (0x00071398): 0x00000000 PLANE_KEYVAL_1_B (0x00071194): 0x00000000 PLANE_KEYVAL_2_B (0x00071294): 0x00000000 PLANE_KEYVAL_3_B (0x00071394): 0x00000000 PLANE_OFFSET_1_B (0x000711a4): 0x00000000 (0, 0) PLANE_OFFSET_2_B (0x000712a4): 0x00000000 PLANE_OFFSET_3_B (0x000713a4): 0x00000000 PLANE_AUX_DIST_1_B (0x000711c0): 0x00000000 PLANE_AUX_DIST_2_B (0x000712c0): 0x00000000 PLANE_AUX_DIST_3_B (0x000713c0): 0x00000000 PLANE_AUX_OFFSET_1_B (0x000711c4): 0x00000000 PLANE_AUX_OFFSET_2_B (0x000712c4): 0x00000000 PLANE_AUX_OFFSET_3_B (0x000713c4): 0x00000000 PLANE_POS_1_B (0x0007118c): 0x00000000 PLANE_POS_2_B (0x0007128c): 0x00000000 PLANE_POS_3_B (0x0007138c): 0x00000000 PLANE_SIZE_1_B (0x00071190): 0x00000000 PLANE_SIZE_2_B (0x00071290): 0x00000000 PLANE_SIZE_3_B (0x00071390): 0x00000000 PLANE_STRIDE_1_B (0x00071188): 0x00000000 (0) PLANE_STRIDE_2_B (0x00071288): 0x00000000 PLANE_STRIDE_3_B (0x00071388): 0x00000000 PLANE_SURF_1_B (0x0007119c): 0x00000000 PLANE_SURF_2_B (0x0007129c): 0x00000000 PLANE_SURF_3_B (0x0007139c): 0x00000000 PLANE_SURFLIVE_1_B (0x000711ac): 0x00000000 PLANE_SURFLIVE_2_B (0x000712ac): 0x00000000 PLANE_SURFLIVE_3_B (0x000713ac): 0x00000000 PLANE_WM_1_B_0 (0x00071240): 0x00000000 PLANE_WM_1_B_1 (0x00071244): 0x00000000 PLANE_WM_1_B_2 (0x00071248): 0x00000000 PLANE_WM_1_B_3 (0x0007124c): 0x00000000 PLANE_WM_1_B_4 (0x00071250): 0x00000000 PLANE_WM_1_B_5 (0x00071254): 0x00000000 PLANE_WM_1_B_6 (0x00071258): 0x00000000 PLANE_WM_1_B_7 (0x0007125c): 0x00000000 PLANE_WM_2_B_0 (0x00071340): 0x00000000 PLANE_WM_2_B_1 (0x00071344): 0x00000000 PLANE_WM_2_B_2 (0x00071348): 0x00000000 PLANE_WM_2_B_3 (0x0007134c): 0x00000000 PLANE_WM_2_B_4 (0x00071350): 0x00000000 PLANE_WM_2_B_5 (0x00071354): 0x00000000 PLANE_WM_2_B_6 (0x00071358): 0x00000000 PLANE_WM_2_B_7 (0x0007135c): 0x00000000 PLANE_WM_3_B_0 (0x00071440): 0x00000000 PLANE_WM_3_B_1 (0x00071444): 0x00000000 PLANE_WM_3_B_2 (0x00071448): 0x00000000 PLANE_WM_3_B_3 (0x0007144c): 0x00000000 PLANE_WM_3_B_4 (0x00071450): 0x00000000 PLANE_WM_3_B_5 (0x00071454): 0x00000000 PLANE_WM_3_B_6 (0x00071458): 0x00000000 PLANE_WM_3_B_7 (0x0007145c): 0x00000000 PLANE_WM_TRANS_1_B (0x00071268): 0x00000000 PLANE_WM_TRANS_2_B (0x00071368): 0x00000000 PLANE_WM_TRANS_3_B (0x00071468): 0x00000000 CUR_BUF_CFG_B (0x0007117c): 0x00000000 CUR_BASE_B (0x00071084): 0x00000000 CUR_CTL_B (0x00071080): 0x00000000 CUR_FBC_CTL_B (0x000710a0): 0x00000000 CUR_POS_B (0x00071088): 0x00000000 CUR_SURFLIVE_B (0x000710ac): 0x00000000 CUR_WM_B_0 (0x00071140): 0x00000000 CUR_WM_B_1 (0x00071144): 0x00000000 CUR_WM_B_2 (0x00071148): 0x00000000 CUR_WM_B_3 (0x0007114c): 0x00000000 CUR_WM_B_4 (0x00071150): 0x00000000 CUR_WM_B_5 (0x00071154): 0x00000000 CUR_WM_B_6 (0x00071158): 0x00000000 CUR_WM_B_7 (0x0007115c): 0x00000000 CUR_WM_TRANS_B (0x00071168): 0x00000000 PS_CTRL_1_B (0x00068980): 0x00000000 PS_CTRL_2_B (0x00068a80): 0x00000000 PS_ECC_STAT_1_B (0x000689d0): 0x00000000 PS_ECC_STAT_2_B (0x00068ad0): 0x00000000 PS_HPHASE_1_B (0x00068994): 0x00000000 PS_HPHASE_2_B (0x00068a94): 0x00000000 PS_HSCALE_1_B (0x00068990): 0x00000000 PS_HSCALE_2_B (0x00068a90): 0x00000000 PS_PWR_GATE_1_B (0x00068960): 0x00000000 PS_PWR_GATE_2_B (0x00068a60): 0x00000000 PS_VPHASE_1_B (0x00068988): 0x00000000 PS_VPHASE_2_B (0x00068a88): 0x00000000 PS_VSCALE_1_B (0x00068984): 0x00000000 PS_VSCALE_2_B (0x00068a84): 0x00000000 PS_WIN_POS_1_B (0x00068970): 0x00000000 PS_WIN_POS_2_B (0x00068a70): 0x00000000 PLANE_BUF_CFG_1_C (0x0007227c): 0x00000000 PLANE_BUF_CFG_2_C (0x0007237c): 0x00000000 PLANE_BUF_CFG_3_C (0x0007247c): 0x00000000 PLANE_NV12_BUF_CFG_1_C (0x00072278): 0x00000000 PLANE_NV12_BUF_CFG_2_C (0x00072378): 0x00000000 PLANE_NV12_BUF_CFG_3_C (0x00072478): 0x00000000 PLANE_CTL_1_C (0x00072180): 0x00000000 (disabled) PLANE_CTL_2_C (0x00072280): 0x00000000 PLANE_CTL_3_C (0x00072380): 0x00000000 PLANE_KEYMAX_1_C (0x000721a0): 0x00000000 PLANE_KEYMAX_2_C (0x000722a0): 0x00000000 PLANE_KEYMAX_3_C (0x000723a0): 0x00000000 PLANE_KEYMSK_1_C (0x00072198): 0x00000000 PLANE_KEYMSK_2_C (0x00072298): 0x00000000 PLANE_KEYMSK_3_C (0x00072398): 0x00000000 PLANE_KEYVAL_1_C (0x00072194): 0x00000000 PLANE_KEYVAL_2_C (0x00072294): 0x00000000 PLANE_KEYVAL_3_C (0x00072394): 0x00000000 PLANE_OFFSET_1_C (0x000721a4): 0x00000000 (0, 0) PLANE_OFFSET_2_C (0x000722a4): 0x00000000 PLANE_OFFSET_3_C (0x000723a4): 0x00000000 PLANE_AUX_DIST_1_C (0x000721c0): 0x00000000 PLANE_AUX_DIST_2_C (0x000722c0): 0x00000000 PLANE_AUX_DIST_3_C (0x000723c0): 0x00000000 PLANE_AUX_OFFSET_1_C (0x000721c4): 0x00000000 PLANE_AUX_OFFSET_2_C (0x000722c4): 0x00000000 PLANE_AUX_OFFSET_3_C (0x000723c4): 0x00000000 PLANE_POS_1_C (0x0007218c): 0x00000000 PLANE_POS_2_C (0x0007228c): 0x00000000 PLANE_POS_3_C (0x0007238c): 0x00000000 PLANE_SIZE_1_C (0x00072190): 0x00000000 PLANE_SIZE_2_C (0x00072290): 0x00000000 PLANE_SIZE_3_C (0x00072390): 0x00000000 PLANE_STRIDE_1_C (0x00072188): 0x00000000 (0) PLANE_STRIDE_2_C (0x00072288): 0x00000000 PLANE_STRIDE_3_C (0x00072388): 0x00000000 PLANE_SURF_1_C (0x0007219c): 0x00000000 PLANE_SURF_2_C (0x0007229c): 0x00000000 PLANE_SURF_3_C (0x0007239c): 0x00000000 PLANE_SURFLIVE_1_C (0x000721ac): 0x00000000 PLANE_SURFLIVE_2_C (0x000722ac): 0x00000000 PLANE_SURFLIVE_3_C (0x000723ac): 0x00000000 PLANE_WM_1_C_0 (0x00072240): 0x00000000 PLANE_WM_1_C_1 (0x00072244): 0x00000000 PLANE_WM_1_C_2 (0x00072248): 0x00000000 PLANE_WM_1_C_3 (0x0007224c): 0x00000000 PLANE_WM_1_C_4 (0x00072250): 0x00000000 PLANE_WM_1_C_5 (0x00072254): 0x00000000 PLANE_WM_1_C_6 (0x00072258): 0x00000000 PLANE_WM_1_C_7 (0x0007225c): 0x00000000 PLANE_WM_2_C_0 (0x00072340): 0x00000000 PLANE_WM_2_C_1 (0x00072344): 0x00000000 PLANE_WM_2_C_2 (0x00072348): 0x00000000 PLANE_WM_2_C_3 (0x0007234c): 0x00000000 PLANE_WM_2_C_4 (0x00072350): 0x00000000 PLANE_WM_2_C_5 (0x00072354): 0x00000000 PLANE_WM_2_C_6 (0x00072358): 0x00000000 PLANE_WM_2_C_7 (0x0007235c): 0x00000000 PLANE_WM_3_C_0 (0x00072440): 0x00000000 PLANE_WM_3_C_1 (0x00072444): 0x00000000 PLANE_WM_3_C_2 (0x00072448): 0x00000000 PLANE_WM_3_C_3 (0x0007244c): 0x00000000 PLANE_WM_3_C_4 (0x00072450): 0x00000000 PLANE_WM_3_C_5 (0x00072454): 0x00000000 PLANE_WM_3_C_6 (0x00072458): 0x00000000 PLANE_WM_3_C_7 (0x0007245c): 0x00000000 PLANE_WM_TRANS_1_C (0x00072268): 0x00000000 PLANE_WM_TRANS_2_C (0x00072368): 0x00000000 PLANE_WM_TRANS_3_C (0x00072468): 0x00000000 CUR_BUF_CFG_C (0x0007217c): 0x00000000 CUR_BASE_C (0x00072084): 0x00000000 CUR_CTL_C (0x00072080): 0x00000000 CUR_FBC_CTL_C (0x000720a0): 0x00000000 CUR_POS_C (0x00072088): 0x00000000 CUR_SURFLIVE_C (0x000720ac): 0x00000000 CUR_WM_C_0 (0x00072140): 0x00000000 CUR_WM_C_1 (0x00072144): 0x00000000 CUR_WM_C_2 (0x00072148): 0x00000000 CUR_WM_C_3 (0x0007214c): 0x00000000 CUR_WM_C_4 (0x00072150): 0x00000000 CUR_WM_C_5 (0x00072154): 0x00000000 CUR_WM_C_6 (0x00072158): 0x00000000 CUR_WM_C_7 (0x0007215c): 0x00000000 CUR_WM_TRANS_C (0x00072168): 0x00000000 PS_CTRL_1_C (0x00069180): 0x00000000 PS_ECC_STAT_1_C (0x000691d0): 0x00000000 PS_HPHASE_1_C (0x00069194): 0x00000000 PS_HSCALE_1_C (0x00069190): 0x00000000 PS_PWR_GATE_1_C (0x00069160): 0x00000000 PS_VPHASE_1_C (0x00069188): 0x00000000 PS_VSCALE_1_C (0x00069184): 0x00000000 PS_WIN_POS_1_C (0x00069170): 0x00000000 PS_WIN_SZ_1_C (0x00069174): 0x00000000 TRANS_CONF_EDP (0x0007f008): 0x00000000 (disabled, inactive, pf-pd) TRANS_HBLANK_EDP (0x0006f004): 0x00000000 (1 start, 1 end) TRANS_HSYNC_EDP (0x0006f008): 0x00000000 (1 start, 1 end) TRANS_HTOTAL_EDP (0x0006f000): 0x00000000 (1 active, 1 total) TRANS_SPACE_EDP (0x0006f024): 0x00000000 TRANS_VBLANK_EDP (0x0006f010): 0x00000000 (1 start, 1 end) TRANS_VSYNC_EDP (0x0006f014): 0x00000000 (1 start, 1 end) TRANS_VSYNCSHIFT_EDP (0x0006f028): 0x00000000 TRANS_VTOTAL_EDP (0x0006f00c): 0x00000000 (1 active, 1 total) TRANS_DATAM1_EDP (0x0006f030): 0x00000000 (TU 1, val 0x0 0) TRANS_DATAN1_EDP (0x0006f034): 0x00000000 (val 0x0 0) TRANS_LINKM1_EDP (0x0006f040): 0x00000000 (val 0x0 0) TRANS_LINKN1_EDP (0x0006f044): 0x00000000 (val 0x0 0) TRANS_DDI_FUNC_CTL_EDP (0x0006f400): 0x00000000 (disabled, no port, HDMI, 8 bpc, -VSync, -HSync, EDP A ON, x1) TRANS_MSA_MISC_EDP (0x0006f410): 0x00000000 TRANS_CONF_A (0x00070008): 0xc0000000 (enabled, active, pf-pd) TRANS_HBLANK_A (0x00060004): 0x0833077f (1920 start, 2100 end) TRANS_HSYNC_A (0x00060008): 0x081b07eb (2028 start, 2076 end) TRANS_HTOTAL_A (0x00060000): 0x0833077f (1920 active, 2100 total) TRANS_MULT_A (0x0006002c): 0x00000000 TRANS_SPACE_A (0x00060024): 0x00000000 TRANS_VBLANK_A (0x00060010): 0x04650437 (1080 start, 1126 end) TRANS_VSYNC_A (0x00060014): 0x044b0441 (1090 start, 1100 end) TRANS_VSYNCSHIFT_A (0x00060028): 0x00000000 TRANS_VTOTAL_A (0x0006000c): 0x04650437 (1080 active, 1126 total) TRANS_DATAM1_A (0x00060030): 0x7e64fa4f (TU 64, val 0x64fa4f 6617679) TRANS_DATAN1_A (0x00060034): 0x00800000 (val 0x800000 8388608) TRANS_LINKM1_A (0x00060040): 0x00043518 (val 0x43518 275736) TRANS_LINKN1_A (0x00060044): 0x00080000 (val 0x80000 524288) TRANS_DDI_FUNC_CTL_A (0x00060400): 0x8a000002 (enabled, no port, DP SST, 8 bpc, -VSync, -HSync, EDP A ON, x2) TRANS_MSA_MISC_A (0x00060410): 0x00000021 TRANS_CONF_B (0x00071008): 0x00000000 (disabled, inactive, pf-pd) TRANS_HBLANK_B (0x00061004): 0x00000000 (1 start, 1 end) TRANS_HSYNC_B (0x00061008): 0x00000000 (1 start, 1 end) TRANS_HTOTAL_B (0x00061000): 0x00000000 (1 active, 1 total) TRANS_MULT_B (0x0006102c): 0x00000000 TRANS_SPACE_B (0x00061024): 0x00000000 TRANS_VBLANK_B (0x00061010): 0x00000000 (1 start, 1 end) TRANS_VSYNC_B (0x00061014): 0x00000000 (1 start, 1 end) TRANS_VSYNCSHIFT_B (0x00061028): 0x00000000 TRANS_VTOTAL_B (0x0006100c): 0x00000000 (1 active, 1 total) TRANS_DATAM1_B (0x00061030): 0x00000000 (TU 1, val 0x0 0) TRANS_DATAN1_B (0x00061034): 0x00000000 (val 0x0 0) TRANS_LINKM1_B (0x00061040): 0x00000000 (val 0x0 0) TRANS_LINKN1_B (0x00061044): 0x00000000 (val 0x0 0) TRANS_DDI_FUNC_CTL_B (0x00061400): 0x00000000 (disabled, no port, HDMI, 8 bpc, -VSync, -HSync, EDP A ON, x1) TRANS_MSA_MISC_B (0x00061410): 0x00000000 TRANS_CONF_C (0x00072008): 0x00000000 (disabled, inactive, pf-pd) TRANS_HBLANK_C (0x00062004): 0x00000000 (1 start, 1 end) TRANS_HSYNC_C (0x00062008): 0x00000000 (1 start, 1 end) TRANS_HTOTAL_C (0x00062000): 0x00000000 (1 active, 1 total) TRANS_MULT_C (0x0006202c): 0x00000000 TRANS_SPACE_C (0x00062024): 0x00000000 TRANS_VBLANK_C (0x00062010): 0x00000000 (1 start, 1 end) TRANS_VSYNC_C (0x00062014): 0x00000000 (1 start, 1 end) TRANS_VSYNCSHIFT_C (0x00062028): 0x00000000 TRANS_VTOTAL_C (0x0006200c): 0x00000000 (1 active, 1 total) TRANS_DATAM1_C (0x00062030): 0x00000000 (TU 1, val 0x0 0) TRANS_DATAN1_C (0x00062034): 0x00000000 (val 0x0 0) TRANS_LINKM1_C (0x00062040): 0x00000000 (val 0x0 0) TRANS_LINKN1_C (0x00062044): 0x00000000 (val 0x0 0) TRANS_DDI_FUNC_CTL_C (0x00062400): 0x00000000 (disabled, no port, HDMI, 8 bpc, -VSync, -HSync, EDP A ON, x1) TRANS_MSA_MISC_C (0x00062410): 0x00000000 WM_LINETIME_A (0x00045270): 0x00000077 WM_LINETIME_B (0x00045274): 0x00000000 WM_LINETIME_C (0x00045278): 0x00000000 WM_MISC (0x00045260): 0x20000000 PLANE_AUX_DIST_4_A (0x000704c0): 0x00000000 PLANE_AUX_DIST_5_A (0x000705c0): 0x00000000 PLANE_AUX_DIST_6_A (0x000706c0): 0x00000000 PLANE_AUX_DIST_7_A (0x000707c0): 0x00000000 PLANE_CTL_4_A (0x00070480): 0x00000000 PLANE_CTL_5_A (0x00070580): 0x00000000 PLANE_CTL_6_A (0x00070680): 0x00000000 PLANE_CTL_7_A (0x00070780): 0x00000000 PLANE_BUF_CFG_4_A (0x0007057c): 0x00000000 PLANE_BUF_CFG_5_A (0x0007067c): 0x00000000 PLANE_BUF_CFG_6_A (0x0007077c): 0x00000000 PLANE_BUF_CFG_7_A (0x0007087c): 0x00000000 PLANE_COLOR_CTL_1_A (0x000701cc): 0x00002000 PLANE_COLOR_CTL_2_A (0x000702cc): 0x00000000 PLANE_COLOR_CTL_3_A (0x000703cc): 0x00000000 PLANE_COLOR_CTL_4_A (0x000704cc): 0x00000000 PLANE_COLOR_CTL_5_A (0x000705cc): 0x00000000 PLANE_COLOR_CTL_6_A (0x000706cc): 0x00000000 PLANE_COLOR_CTL_7_A (0x000707cc): 0x00000000 PLANE_KEYMAX_4_A (0x000704a0): 0x00000000 PLANE_KEYMAX_5_A (0x000705a0): 0x00000000 PLANE_KEYMAX_6_A (0x000706a0): 0x00000000 PLANE_KEYMAX_7_A (0x000707a0): 0x00000000 PLANE_NV12_BUF_CFG_4_A (0x00070578): 0x00000000 PLANE_NV12_BUF_CFG_5_A (0x00070678): 0x00000000 PLANE_NV12_BUF_CFG_6_A (0x00070778): 0x00000000 PLANE_NV12_BUF_CFG_7_A (0x00070878): 0x00000000 PLANE_POS_4_A (0x0007048c): 0x00000000 PLANE_POS_5_A (0x0007058c): 0x00000000 PLANE_POS_6_A (0x0007068c): 0x00000000 PLANE_POS_7_A (0x0007078c): 0x00000000 PLANE_SIZE_4_A (0x00070490): 0x00000000 PLANE_SIZE_5_A (0x00070590): 0x00000000 PLANE_SIZE_6_A (0x00070690): 0x00000000 PLANE_SIZE_7_A (0x00070790): 0x00000000 PLANE_WM_4_A_0 (0x00070540): 0x00000000 PLANE_WM_4_A_1 (0x00070544): 0x00000000 PLANE_WM_4_A_2 (0x00070548): 0x00000000 PLANE_WM_4_A_3 (0x0007054c): 0x00000000 PLANE_WM_4_A_4 (0x00070550): 0x00000000 PLANE_WM_4_A_5 (0x00070554): 0x00000000 PLANE_WM_4_A_6 (0x00070558): 0x00000000 PLANE_WM_4_A_7 (0x0007055c): 0x00000000 PLANE_WM_5_A_0 (0x00070640): 0x00000000 PLANE_WM_5_A_1 (0x00070644): 0x00000000 PLANE_WM_5_A_2 (0x00070648): 0x00000000 PLANE_WM_5_A_3 (0x0007064c): 0x00000000 PLANE_WM_5_A_4 (0x00070650): 0x00000000 PLANE_WM_5_A_5 (0x00070654): 0x00000000 PLANE_WM_5_A_6 (0x00070658): 0x00000000 PLANE_WM_5_A_7 (0x0007065c): 0x00000000 PLANE_WM_6_A_0 (0x00070740): 0x00000000 PLANE_WM_6_A_1 (0x00070744): 0x00000000 PLANE_WM_6_A_2 (0x00070748): 0x00000000 PLANE_WM_6_A_3 (0x0007074c): 0x00000000 PLANE_WM_6_A_4 (0x00070750): 0x00000000 PLANE_WM_6_A_5 (0x00070754): 0x00000000 PLANE_WM_6_A_6 (0x00070758): 0x00000000 PLANE_WM_6_A_7 (0x0007075c): 0x00000000 PLANE_WM_7_A_0 (0x00070840): 0x00000000 PLANE_WM_7_A_1 (0x00070844): 0x00000000 PLANE_WM_7_A_2 (0x00070848): 0x00000000 PLANE_WM_7_A_3 (0x0007084c): 0x00000000 PLANE_WM_7_A_4 (0x00070850): 0x00000000 PLANE_WM_7_A_5 (0x00070854): 0x00000000 PLANE_WM_7_A_6 (0x00070858): 0x00000000 PLANE_WM_7_A_7 (0x0007085c): 0x00000000 PLANE_WM_TRANS_4_A (0x00070568): 0x00000000 PLANE_WM_TRANS_5_A (0x00070668): 0x00000000 PLANE_WM_TRANS_6_A (0x00070768): 0x00000000 PLANE_WM_TRANS_7_A (0x00070868): 0x00000000 PLANE_AUX_DIST_4_B (0x000714c0): 0x00000000 PLANE_AUX_DIST_5_B (0x000715c0): 0x00000000 PLANE_AUX_DIST_6_B (0x000716c0): 0x00000000 PLANE_AUX_DIST_7_B (0x000717c0): 0x00000000 PLANE_CTL_4_B (0x00071480): 0x00000000 PLANE_CTL_5_B (0x00071580): 0x00000000 PLANE_CTL_6_B (0x00071680): 0x00000000 PLANE_CTL_7_B (0x00071780): 0x00000000 PLANE_BUF_CFG_4_B (0x0007157c): 0x00000000 PLANE_BUF_CFG_5_B (0x0007167c): 0x00000000 PLANE_BUF_CFG_6_B (0x0007177c): 0x00000000 PLANE_BUF_CFG_7_B (0x0007187c): 0x00000000 PLANE_COLOR_CTL_1_B (0x000711cc): 0x00000000 PLANE_COLOR_CTL_2_B (0x000712cc): 0x00000000 PLANE_COLOR_CTL_3_B (0x000713cc): 0x00000000 PLANE_COLOR_CTL_4_B (0x000714cc): 0x00000000 PLANE_COLOR_CTL_5_B (0x000715cc): 0x00000000 PLANE_COLOR_CTL_6_B (0x000716cc): 0x00000000 PLANE_COLOR_CTL_7_B (0x000717cc): 0x00000000 PLANE_KEYMAX_4_B (0x000714a0): 0x00000000 PLANE_KEYMAX_5_B (0x000715a0): 0x00000000 PLANE_KEYMAX_6_B (0x000716a0): 0x00000000 PLANE_KEYMAX_7_B (0x000717a0): 0x00000000 PLANE_NV12_BUF_CFG_4_B (0x00071578): 0x00000000 PLANE_NV12_BUF_CFG_5_B (0x00071678): 0x00000000 PLANE_NV12_BUF_CFG_6_B (0x00071778): 0x00000000 PLANE_NV12_BUF_CFG_7_B (0x00071878): 0x00000000 PLANE_POS_4_B (0x0007148c): 0x00000000 PLANE_POS_5_B (0x0007158c): 0x00000000 PLANE_POS_6_B (0x0007168c): 0x00000000 PLANE_POS_7_B (0x0007178c): 0x00000000 PLANE_SIZE_4_B (0x00071490): 0x00000000 PLANE_SIZE_5_B (0x00071590): 0x00000000 PLANE_SIZE_6_B (0x00071690): 0x00000000 PLANE_SIZE_7_B (0x00071790): 0x00000000 PLANE_WM_4_B_0 (0x00071540): 0x00000000 PLANE_WM_4_B_1 (0x00071544): 0x00000000 PLANE_WM_4_B_2 (0x00071548): 0x00000000 PLANE_WM_4_B_3 (0x0007154c): 0x00000000 PLANE_WM_4_B_4 (0x00071550): 0x00000000 PLANE_WM_4_B_5 (0x00071554): 0x00000000 PLANE_WM_4_B_6 (0x00071558): 0x00000000 PLANE_WM_4_B_7 (0x0007155c): 0x00000000 PLANE_WM_5_B_0 (0x00071640): 0x00000000 PLANE_WM_5_B_1 (0x00071644): 0x00000000 PLANE_WM_5_B_2 (0x00071648): 0x00000000 PLANE_WM_5_B_3 (0x0007164c): 0x00000000 PLANE_WM_5_B_4 (0x00071650): 0x00000000 PLANE_WM_5_B_5 (0x00071654): 0x00000000 PLANE_WM_5_B_6 (0x00071658): 0x00000000 PLANE_WM_5_B_7 (0x0007165c): 0x00000000 PLANE_WM_6_B_0 (0x00071740): 0x00000000 PLANE_WM_6_B_1 (0x00071744): 0x00000000 PLANE_WM_6_B_2 (0x00071748): 0x00000000 PLANE_WM_6_B_3 (0x0007174c): 0x00000000 PLANE_WM_6_B_4 (0x00071750): 0x00000000 PLANE_WM_6_B_5 (0x00071754): 0x00000000 PLANE_WM_6_B_6 (0x00071758): 0x00000000 PLANE_WM_6_B_7 (0x0007175c): 0x00000000 PLANE_WM_7_B_0 (0x00071840): 0x00000000 PLANE_WM_7_B_1 (0x00071844): 0x00000000 PLANE_WM_7_B_2 (0x00071848): 0x00000000 PLANE_WM_7_B_3 (0x0007184c): 0x00000000 PLANE_WM_7_B_4 (0x00071850): 0x00000000 PLANE_WM_7_B_5 (0x00071854): 0x00000000 PLANE_WM_7_B_6 (0x00071858): 0x00000000 PLANE_WM_7_B_7 (0x0007185c): 0x00000000 PLANE_WM_TRANS_4_B (0x00071568): 0x00000000 PLANE_WM_TRANS_5_B (0x00071668): 0x00000000 PLANE_WM_TRANS_6_B (0x00071768): 0x00000000 PLANE_WM_TRANS_7_B (0x00071868): 0x00000000 PLANE_AUX_DIST_4_C (0x000724c0): 0x00000000 PLANE_AUX_DIST_5_C (0x000725c0): 0x00000000 PLANE_AUX_DIST_6_C (0x000726c0): 0x00000000 PLANE_AUX_DIST_7_C (0x000727c0): 0x00000000 PLANE_CTL_4_C (0x00072480): 0x00000000 PLANE_CTL_5_C (0x00072580): 0x00000000 PLANE_CTL_6_C (0x00072680): 0x00000000 PLANE_CTL_7_C (0x00072780): 0x00000000 PLANE_BUF_CFG_4_C (0x0007257c): 0x00000000 PLANE_BUF_CFG_5_C (0x0007267c): 0x00000000 PLANE_BUF_CFG_6_C (0x0007277c): 0x00000000 PLANE_BUF_CFG_7_C (0x0007287c): 0x00000000 PLANE_COLOR_CTL_1_C (0x000721cc): 0x00000000 PLANE_COLOR_CTL_2_C (0x000722cc): 0x00000000 PLANE_COLOR_CTL_3_C (0x000723cc): 0x00000000 PLANE_COLOR_CTL_4_C (0x000724cc): 0x00000000 PLANE_COLOR_CTL_5_C (0x000725cc): 0x00000000 PLANE_COLOR_CTL_6_C (0x000726cc): 0x00000000 PLANE_COLOR_CTL_7_C (0x000727cc): 0x00000000 PLANE_KEYMAX_4_C (0x000724a0): 0x00000000 PLANE_KEYMAX_5_C (0x000725a0): 0x00000000 PLANE_KEYMAX_6_C (0x000726a0): 0x00000000 PLANE_KEYMAX_7_C (0x000727a0): 0x00000000 PLANE_NV12_BUF_CFG_4_C (0x00072578): 0x00000000 PLANE_NV12_BUF_CFG_5_C (0x00072678): 0x00000000 PLANE_NV12_BUF_CFG_6_C (0x00072778): 0x00000000 PLANE_NV12_BUF_CFG_7_C (0x00072878): 0x00000000 PLANE_POS_4_C (0x0007248c): 0x00000000 PLANE_POS_5_C (0x0007258c): 0x00000000 PLANE_POS_6_C (0x0007268c): 0x00000000 PLANE_POS_7_C (0x0007278c): 0x00000000 PLANE_SIZE_4_C (0x00072490): 0x00000000 PLANE_SIZE_5_C (0x00072590): 0x00000000 PLANE_SIZE_6_C (0x00072690): 0x00000000 PLANE_SIZE_7_C (0x00072790): 0x00000000 PLANE_WM_4_C_0 (0x00072540): 0x00000000 PLANE_WM_4_C_1 (0x00072544): 0x00000000 PLANE_WM_4_C_2 (0x00072548): 0x00000000 PLANE_WM_4_C_3 (0x0007254c): 0x00000000 PLANE_WM_4_C_4 (0x00072550): 0x00000000 PLANE_WM_4_C_5 (0x00072554): 0x00000000 PLANE_WM_4_C_6 (0x00072558): 0x00000000 PLANE_WM_4_C_7 (0x0007255c): 0x00000000 PLANE_WM_5_C_0 (0x00072640): 0x00000000 PLANE_WM_5_C_1 (0x00072644): 0x00000000 PLANE_WM_5_C_2 (0x00072648): 0x00000000 PLANE_WM_5_C_3 (0x0007264c): 0x00000000 PLANE_WM_5_C_4 (0x00072650): 0x00000000 PLANE_WM_5_C_5 (0x00072654): 0x00000000 PLANE_WM_5_C_6 (0x00072658): 0x00000000 PLANE_WM_5_C_7 (0x0007265c): 0x00000000 PLANE_WM_6_C_0 (0x00072740): 0x00000000 PLANE_WM_6_C_1 (0x00072744): 0x00000000 PLANE_WM_6_C_2 (0x00072748): 0x00000000 PLANE_WM_6_C_3 (0x0007274c): 0x00000000 PLANE_WM_6_C_4 (0x00072750): 0x00000000 PLANE_WM_6_C_5 (0x00072754): 0x00000000 PLANE_WM_6_C_6 (0x00072758): 0x00000000 PLANE_WM_6_C_7 (0x0007275c): 0x00000000 PLANE_WM_7_C_0 (0x00072840): 0x00000000 PLANE_WM_7_C_1 (0x00072844): 0x00000000 PLANE_WM_7_C_2 (0x00072848): 0x00000000 PLANE_WM_7_C_3 (0x0007284c): 0x00000000 PLANE_WM_7_C_4 (0x00072850): 0x00000000 PLANE_WM_7_C_5 (0x00072854): 0x00000000 PLANE_WM_7_C_6 (0x00072858): 0x00000000 PLANE_WM_7_C_7 (0x0007285c): 0x00000000 PLANE_WM_TRANS_4_C (0x00072468): 0x00000000 PLANE_WM_TRANS_5_C (0x00072468): 0x00000000 PLANE_WM_TRANS_6_C (0x00072468): 0x00000000 PLANE_WM_TRANS_7_C (0x00072468): 0x00000000 TRANS_DDI_FUNC_CTL_DSI0 (0x0006b400): 0x00030000 TRANS_DDI_FUNC_CTL_DSI1 (0x0006bc00): 0x00030000 TRANS_HTOTAL_DSI0 (0x0006b000): 0x00000000 TRANS_HTOTAL_DSI1 (0x0006b800): 0x00000000 TRANS_VTOTAL_DSI0 (0x0006b00c): 0x00000000 TRANS_VTOTAL_DSI1 (0x0006b80c): 0x00000000 MBUS_ABOX_CTL (0x00045038): 0xa2913050 MBUS_DBOX_CTL_A (0x0007003c): 0xb1038c02 MBUS_DBOX_CTL_B (0x0007103c): 0x00000000 MBUS_DBOX_CTL_C (0x0007203c): 0x00000000 DPLL4_ENABLE (0x00046018): 0x00000000 DPLL4_CFGCR0 (0x00164294): 0x018001d4 DPLL4_CFGCR1 (0x00164298): 0x00002644 DPLL0_SSC (0x00164b10): 0x401320ff DPLL1_SSC (0x00164c10): 0x401320ff DPLL4_SSC (0x00164e10): 0xffffffff TRANS_CLK_SEL_D (0x0004614c): 0x00000000 PLANE_OFFSET_4_A (0x000704a4): 0x00000000 PLANE_OFFSET_5_A (0x000705a4): 0x00000000 PLANE_OFFSET_6_A (0x000706a4): 0x00000000 PLANE_OFFSET_7_A (0x000707a4): 0x00000000 PLANE_KEYMSK_4_A (0x00070498): 0x00000000 PLANE_KEYMSK_5_A (0x00070598): 0x00000000 PLANE_KEYMSK_6_A (0x00070698): 0x00000000 PLANE_KEYMSK_7_A (0x00070798): 0x00000000 PLANE_KEYVAL_4_A (0x00070494): 0x00000000 PLANE_KEYVAL_5_A (0x00070594): 0x00000000 PLANE_KEYVAL_6_A (0x00070694): 0x00000000 PLANE_KEYVAL_7_A (0x00070794): 0x00000000 PLANE_STRIDE_4_A (0x00070488): 0x00000000 PLANE_STRIDE_5_A (0x00070588): 0x00000000 PLANE_STRIDE_6_A (0x00070688): 0x00000000 PLANE_STRIDE_7_A (0x00070788): 0x00000000 PLANE_SURF_4_A (0x0007049c): 0x00000000 PLANE_SURF_5_A (0x0007059c): 0x00000000 PLANE_SURF_6_A (0x0007069c): 0x00000000 PLANE_SURF_7_A (0x0007079c): 0x00000000 PLANE_SURFLIVE_4_A (0x000704ac): 0x00000000 PLANE_SURFLIVE_5_A (0x000705ac): 0x00000000 PLANE_SURFLIVE_6_A (0x000706ac): 0x00000000 PLANE_SURFLIVE_7_A (0x000707ac): 0x00000000 PLANE_OFFSET_4_B (0x000714a4): 0x00000000 PLANE_OFFSET_5_B (0x000715a4): 0x00000000 PLANE_OFFSET_6_B (0x000716a4): 0x00000000 PLANE_OFFSET_7_B (0x000717a4): 0x00000000 PLANE_KEYMSK_4_B (0x00071498): 0x00000000 PLANE_KEYMSK_5_B (0x00071598): 0x00000000 PLANE_KEYMSK_6_B (0x00071698): 0x00000000 PLANE_KEYMSK_7_B (0x00071798): 0x00000000 PLANE_KEYVAL_4_B (0x00071494): 0x00000000 PLANE_KEYVAL_5_B (0x00071594): 0x00000000 PLANE_KEYVAL_6_B (0x00071694): 0x00000000 PLANE_KEYVAL_7_B (0x00071794): 0x00000000 PLANE_STRIDE_4_B (0x00071488): 0x00000000 PLANE_STRIDE_5_B (0x00071588): 0x00000000 PLANE_STRIDE_6_B (0x00071688): 0x00000000 PLANE_STRIDE_7_B (0x00071788): 0x00000000 PLANE_SURF_4_B (0x0007149c): 0x00000000 PLANE_SURF_5_B (0x0007159c): 0x00000000 PLANE_SURF_6_B (0x0007169c): 0x00000000 PLANE_SURF_7_B (0x0007179c): 0x00000000 PLANE_SURFLIVE_4_B (0x000714ac): 0x00000000 PLANE_SURFLIVE_5_B (0x000715ac): 0x00000000 PLANE_SURFLIVE_6_B (0x000716ac): 0x00000000 PLANE_SURFLIVE_7_B (0x000717ac): 0x00000000 PLANE_OFFSET_4_C (0x000724a4): 0x00000000 PLANE_OFFSET_5_C (0x000725a4): 0x00000000 PLANE_OFFSET_6_C (0x000726a4): 0x00000000 PLANE_OFFSET_7_C (0x000727a4): 0x00000000 PLANE_KEYMSK_4_C (0x00072498): 0x00000000 PLANE_KEYMSK_5_C (0x00072598): 0x00000000 PLANE_KEYMSK_6_C (0x00072698): 0x00000000 PLANE_KEYMSK_7_C (0x00072798): 0x00000000 PLANE_KEYVAL_4_C (0x00072494): 0x00000000 PLANE_KEYVAL_5_C (0x00072594): 0x00000000 PLANE_KEYVAL_6_C (0x00072694): 0x00000000 PLANE_KEYVAL_7_C (0x00072794): 0x00000000 PLANE_STRIDE_4_C (0x00072488): 0x00000000 PLANE_STRIDE_5_C (0x00072588): 0x00000000 PLANE_STRIDE_6_C (0x00072688): 0x00000000 PLANE_STRIDE_7_C (0x00072788): 0x00000000 PLANE_SURF_4_C (0x0007249c): 0x00000000 PLANE_SURF_5_C (0x0007259c): 0x00000000 PLANE_SURF_6_C (0x0007269c): 0x00000000 PLANE_SURF_7_C (0x0007279c): 0x00000000 PLANE_SURFLIVE_4_C (0x000724ac): 0x00000000 PLANE_SURFLIVE_5_C (0x000725ac): 0x00000000 PLANE_SURFLIVE_6_C (0x000726ac): 0x00000000 PLANE_SURFLIVE_7_C (0x000727ac): 0x00000000 PLANE_AUX_DIST_1_D (0x000731c0): 0x00000000 PLANE_AUX_DIST_2_D (0x000732c0): 0x00000000 PLANE_AUX_DIST_3_D (0x000733c0): 0x00000000 PLANE_AUX_DIST_4_D (0x000734c0): 0x00000000 PLANE_AUX_DIST_5_D (0x000735c0): 0x00000000 PLANE_AUX_DIST_6_D (0x000736c0): 0x00000000 PLANE_AUX_DIST_7_D (0x000737c0): 0x00000000 PLANE_CTL_1_D (0x00073180): 0x00000000 PLANE_CTL_2_D (0x00073280): 0x00000000 PLANE_CTL_3_D (0x00073380): 0x00000000 PLANE_CTL_4_D (0x00073480): 0x00000000 PLANE_CTL_5_D (0x00073580): 0x00000000 PLANE_CTL_6_D (0x00073680): 0x00000000 PLANE_CTL_7_D (0x00073780): 0x00000000 PLANE_BUF_CFG_1_D (0x0007327c): 0x00000000 PLANE_BUF_CFG_2_D (0x0007337c): 0x00000000 PLANE_BUF_CFG_3_D (0x0007347c): 0x00000000 PLANE_BUF_CFG_4_D (0x0007357c): 0x00000000 PLANE_BUF_CFG_5_D (0x0007367c): 0x00000000 PLANE_BUF_CFG_6_D (0x0007377c): 0x00000000 PLANE_BUF_CFG_7_D (0x0007387c): 0x00000000 PLANE_COLOR_CTL_1_D (0x000731cc): 0x00000000 PLANE_COLOR_CTL_2_D (0x000732cc): 0x00000000 PLANE_COLOR_CTL_3_D (0x000733cc): 0x00000000 PLANE_COLOR_CTL_4_D (0x000734cc): 0x00000000 PLANE_COLOR_CTL_5_D (0x000735cc): 0x00000000 PLANE_COLOR_CTL_6_D (0x000736cc): 0x00000000 PLANE_COLOR_CTL_7_D (0x000737cc): 0x00000000 PLANE_OFFSET_1_D (0x000731a4): 0x00000000 PLANE_OFFSET_2_D (0x000732a4): 0x00000000 PLANE_OFFSET_3_D (0x000733a4): 0x00000000 PLANE_OFFSET_4_D (0x000734a4): 0x00000000 PLANE_OFFSET_5_D (0x000735a4): 0x00000000 PLANE_OFFSET_6_D (0x000736a4): 0x00000000 PLANE_OFFSET_7_D (0x000737a4): 0x00000000 PLANE_KEYMAX_1_D (0x000731a0): 0x00000000 PLANE_KEYMAX_2_D (0x000732a0): 0x00000000 PLANE_KEYMAX_3_D (0x000733a0): 0x00000000 PLANE_KEYMAX_4_D (0x000734a0): 0x00000000 PLANE_KEYMAX_5_D (0x000735a0): 0x00000000 PLANE_KEYMAX_6_D (0x000736a0): 0x00000000 PLANE_KEYMAX_7_D (0x000737a0): 0x00000000 PLANE_KEYMSK_1_D (0x00073198): 0x00000000 PLANE_KEYMSK_2_D (0x00073298): 0x00000000 PLANE_KEYMSK_3_D (0x00073398): 0x00000000 PLANE_KEYMSK_4_D (0x00073498): 0x00000000 PLANE_KEYMSK_5_D (0x00073598): 0x00000000 PLANE_KEYMSK_6_D (0x00073698): 0x00000000 PLANE_KEYMSK_7_D (0x00073798): 0x00000000 PLANE_KEYVAL_1_D (0x00073194): 0x00000000 PLANE_KEYVAL_2_D (0x00073294): 0x00000000 PLANE_KEYVAL_3_D (0x00073394): 0x00000000 PLANE_KEYVAL_4_D (0x00073494): 0x00000000 PLANE_KEYVAL_5_D (0x00073594): 0x00000000 PLANE_KEYVAL_6_D (0x00073694): 0x00000000 PLANE_KEYVAL_7_D (0x00073794): 0x00000000 PLANE_STRIDE_1_D (0x00073188): 0x00000000 PLANE_STRIDE_2_D (0x00073288): 0x00000000 PLANE_STRIDE_3_D (0x00073388): 0x00000000 PLANE_STRIDE_4_D (0x00073488): 0x00000000 PLANE_STRIDE_5_D (0x00073588): 0x00000000 PLANE_STRIDE_6_D (0x00073688): 0x00000000 PLANE_STRIDE_7_D (0x00073788): 0x00000000 PLANE_SURF_1_D (0x0007319c): 0x00000000 PLANE_SURF_2_D (0x0007329c): 0x00000000 PLANE_SURF_3_D (0x0007339c): 0x00000000 PLANE_SURF_4_D (0x0007349c): 0x00000000 PLANE_SURF_5_D (0x0007359c): 0x00000000 PLANE_SURF_6_D (0x0007369c): 0x00000000 PLANE_SURF_7_D (0x0007379c): 0x00000000 PLANE_SURFLIVE_1_D (0x000731ac): 0x00000000 PLANE_SURFLIVE_2_D (0x000732ac): 0x00000000 PLANE_SURFLIVE_3_D (0x000733ac): 0x00000000 PLANE_SURFLIVE_4_D (0x000734ac): 0x00000000 PLANE_SURFLIVE_5_D (0x000735ac): 0x00000000 PLANE_SURFLIVE_6_D (0x000736ac): 0x00000000 PLANE_SURFLIVE_7_D (0x000737ac): 0x00000000 PLANE_POS_1_D (0x0007318c): 0x00000000 PLANE_POS_2_D (0x0007328c): 0x00000000 PLANE_POS_3_D (0x0007338c): 0x00000000 PLANE_POS_4_D (0x0007348c): 0x00000000 PLANE_POS_5_D (0x0007358c): 0x00000000 PLANE_POS_6_D (0x0007368c): 0x00000000 PLANE_POS_7_D (0x0007378c): 0x00000000 PLANE_SIZE_1_D (0x00073190): 0x00000000 PLANE_SIZE_2_D (0x00073290): 0x00000000 PLANE_SIZE_3_D (0x00073390): 0x00000000 PLANE_SIZE_4_D (0x00073490): 0x00000000 PLANE_SIZE_5_D (0x00073590): 0x00000000 PLANE_SIZE_6_D (0x00073690): 0x00000000 PLANE_SIZE_7_D (0x00073790): 0x00000000 PLANE_WM_1_D_0 (0x00073240): 0x00000000 PLANE_WM_1_D_1 (0x00073244): 0x00000000 PLANE_WM_1_D_2 (0x00073248): 0x00000000 PLANE_WM_1_D_3 (0x0007324c): 0x00000000 PLANE_WM_1_D_4 (0x00073250): 0x00000000 PLANE_WM_1_D_5 (0x00073254): 0x00000000 PLANE_WM_1_D_6 (0x00073258): 0x00000000 PLANE_WM_1_D_7 (0x0007325c): 0x00000000 PLANE_WM_2_D_0 (0x00073340): 0x00000000 PLANE_WM_2_D_1 (0x00073344): 0x00000000 PLANE_WM_2_D_2 (0x00073348): 0x00000000 PLANE_WM_2_D_3 (0x0007334c): 0x00000000 PLANE_WM_2_D_4 (0x00073350): 0x00000000 PLANE_WM_2_D_5 (0x00073354): 0x00000000 PLANE_WM_2_D_6 (0x00073358): 0x00000000 PLANE_WM_2_D_7 (0x0007335c): 0x00000000 PLANE_WM_3_D_0 (0x00073440): 0x00000000 PLANE_WM_3_D_1 (0x00073444): 0x00000000 PLANE_WM_3_D_2 (0x00073448): 0x00000000 PLANE_WM_3_D_3 (0x0007344c): 0x00000000 PLANE_WM_3_D_4 (0x00073450): 0x00000000 PLANE_WM_3_D_5 (0x00073454): 0x00000000 PLANE_WM_3_D_6 (0x00073458): 0x00000000 PLANE_WM_3_D_7 (0x0007345c): 0x00000000 PLANE_WM_4_D_0 (0x00073540): 0x00000000 PLANE_WM_4_D_1 (0x00073544): 0x00000000 PLANE_WM_4_D_2 (0x00073548): 0x00000000 PLANE_WM_4_D_3 (0x0007354c): 0x00000000 PLANE_WM_4_D_4 (0x00073550): 0x00000000 PLANE_WM_4_D_5 (0x00073554): 0x00000000 PLANE_WM_4_D_6 (0x00073558): 0x00000000 PLANE_WM_4_D_7 (0x0007355c): 0x00000000 PLANE_WM_5_D_0 (0x00073640): 0x00000000 PLANE_WM_5_D_1 (0x00073644): 0x00000000 PLANE_WM_5_D_2 (0x00073648): 0x00000000 PLANE_WM_5_D_3 (0x0007364c): 0x00000000 PLANE_WM_5_D_4 (0x00073650): 0x00000000 PLANE_WM_5_D_5 (0x00073654): 0x00000000 PLANE_WM_5_D_6 (0x00073658): 0x00000000 PLANE_WM_5_D_7 (0x0007365c): 0x00000000 PLANE_WM_6_D_0 (0x00073740): 0x00000000 PLANE_WM_6_D_1 (0x00073744): 0x00000000 PLANE_WM_6_D_2 (0x00073748): 0x00000000 PLANE_WM_6_D_3 (0x0007374c): 0x00000000 PLANE_WM_6_D_4 (0x00073750): 0x00000000 PLANE_WM_6_D_5 (0x00073754): 0x00000000 PLANE_WM_6_D_6 (0x00073758): 0x00000000 PLANE_WM_6_D_7 (0x0007375c): 0x00000000 PLANE_WM_7_D_0 (0x00073840): 0x00000000 PLANE_WM_7_D_1 (0x00073844): 0x00000000 PLANE_WM_7_D_2 (0x00073848): 0x00000000 PLANE_WM_7_D_3 (0x0007384c): 0x00000000 PLANE_WM_7_D_4 (0x00073850): 0x00000000 PLANE_WM_7_D_5 (0x00073854): 0x00000000 PLANE_WM_7_D_6 (0x00073858): 0x00000000 PLANE_WM_7_D_7 (0x0007385c): 0x00000000 PLANE_WM_TRANS_1_D (0x00073268): 0x00000000 PLANE_WM_TRANS_2_D (0x00073368): 0x00000000 PLANE_WM_TRANS_3_D (0x00073468): 0x00000000 PLANE_WM_TRANS_4_D (0x00073568): 0x00000000 PLANE_WM_TRANS_5_D (0x00073668): 0x00000000 PLANE_WM_TRANS_6_D (0x00073768): 0x00000000 PLANE_WM_TRANS_7_D (0x00073868): 0x00000000 CUR_BUF_CFG_D (0x0007317c): 0x00000000 CUR_BASE_D (0x00073084): 0x00000000 CUR_CTL_D (0x00073080): 0x00000000 CUR_FBC_CTL_D (0x000730a0): 0x00000000 CUR_POS_D (0x00073088): 0x00000000 CUR_SURFLIVE_D (0x000730ac): 0x00000000 CUR_WM_0_D (0x00073140): 0x00000000 CUR_WM_1_D (0x00073144): 0x00000000 CUR_WM_2_D (0x00073148): 0x00000000 CUR_WM_3_D (0x0007314c): 0x00000000 CUR_WM_4_D (0x00073150): 0x00000000 CUR_WM_5_D (0x00073154): 0x00000000 CUR_WM_6_D (0x00073158): 0x00000000 CUR_WM_7_D (0x0007315c): 0x00000000 CUR_WM_TRANS_D (0x00073168): 0x00000000 PS_CTRL_1_D (0x00069980): 0x00000000 PS_CTRL_2_D (0x00069a80): 0x00000000 PS_ECC_STAT_1_D (0x000699d0): 0x00000000 PS_ECC_STAT_2_D (0x00069ad0): 0x00000000 PS_HPHASE_1_D (0x00069994): 0x00000000 PS_HPHASE_2_D (0x00069a94): 0x00000000 PS_HSCALE_1_D (0x00069990): 0x00000000 PS_HSCALE_2_D (0x00069a90): 0x00000000 PS_PWR_GATE_1_D (0x00069960): 0x00000000 PS_PWR_GATE_2_D (0x00069a60): 0x00000000 PS_VPHASE_1_D (0x00069988): 0x00000000 PS_VPHASE_2_D (0x00069a88): 0x00000000 PS_VSCALE_1_D (0x00069984): 0x00000000 PS_VSCALE_2_D (0x00069a84): 0x00000000 PS_WIN_POS_1_D (0x00069970): 0x00000000 PS_WIN_POS_2_D (0x00069a70): 0x00000000 PS_WIN_SZ_1_D (0x00069974): 0x00000000 PS_WIN_SZ_2_D (0x00069a74): 0x00000000 TRANS_CONF_D (0x00073008): 0x00000000 TRANS_CONF_DSI0 (0x0007b008): 0x00000024 TRANS_CONF_DSI1 (0x0007b808): 0x00000024 TRANS_HBLANK_D (0x00063004): 0x00000000 TRANS_HSYNC_D (0x00063008): 0x00000000 TRANS_HTOTAL_D (0x00063000): 0x00000000 TRANS_MULT_D (0x0006302c): 0x00000000 TRANS_SPACE_D (0x00063024): 0x00000000 TRANS_VBLANK_D (0x00063010): 0x00000000 TRANS_VSYNC_D (0x00063014): 0x00000000 TRANS_VSYNCSHIFT_D (0x00063028): 0x00000000 TRANS_VTOTAL_D (0x0006300c): 0x00000000 TRANS_HSYNC_DSI0 (0x0006b008): 0x00000000 TRANS_HSYNC_DSI1 (0x0006b808): 0x00000000 TRANS_HTOTAL_DSI0 (0x0006b000): 0x00000000 TRANS_HTOTAL_DSI1 (0x0006b800): 0x00000000 TRANS_SPACE_DSI0 (0x0006b024): 0x00000000 TRANS_SPACE_DSI1 (0x0006b824): 0x00000000 TRANS_VBLANK_DSI0 (0x0006b010): 0x00000000 TRANS_VBLANK_DSI1 (0x0006b810): 0x00000000 TRANS_VSYNC_DSI0 (0x0006b014): 0x00000000 TRANS_VSYNC_DSI1 (0x0006b814): 0x00000000 TRANS_VSYNCSHIFT_DSI0 (0x0006b028): 0x00000000 TRANS_VSYNCSHIFT_DSI1 (0x0006b828): 0x00000000 TRANS_VTOTAL_DSI0 (0x0006b00c): 0x00000000 TRANS_VTOTAL_DSI1 (0x0006b80c): 0x00000000 TRANS_DATAM1_D (0x00063030): 0x00000000 TRANS_DATAN1_D (0x00063034): 0x00000000 TRANS_LINKM1_D (0x00063040): 0x00000000 TRANS_LINKN1_D (0x00063044): 0x00000000 TRANS_DDI_FUNC_CTL_D (0x00063400): 0x00000000 TRANS_MSA_MISC_D (0x00063410): 0x00000000 TRANS_DDI_FUNC_CTL_DSI0 (0x0006b400): 0x00030000 TRANS_DDI_FUNC_CTL_DSI1 (0x0006bc00): 0x00030000 MBUS_DBOX_CTL_D (0x0007303c): 0x00000000 WM_LINETIME_D (0x0004527c): 0x00000000 this code in macos is called only if if ((uVar1 >> 0x10 & 1) != 0) { _DAT_0010d348 = _DAT_0010d348 + 1; uVar2 = FastReadRegister32(this,*(void **)&(this->m_AppleIntelFramebufferController).field_0x9b0 ,0x44408); uVar9 = 0; if ((uVar2 & 1) != 0) { _DAT_0010d350 = _DAT_0010d350 + 1; lVar8 = getFBFromPipe(this,0); uVar9 = 1; if (lVar8 != 0) { _DAT_0010d358 = _DAT_0010d358 + 1; uVar3 = FastReadRegister32(this,*(void **)&(this->m_AppleIntelFramebufferController). field_0x9b0,0x701ac); *(undefined4 *)(&DAT_000090e8 + lVar8) = uVar3; } } if ((uVar2 & 8) != 0) { _DAT_0010d360 = _DAT_0010d360 + 1; uVar9 = uVar9 | 8; (this->m_AppleIntelFramebufferController).field_0xa0 = 1; } if ((int)uVar2 < 0) { _DAT_0010d368 = _DAT_0010d368 + 1; uVar9 = uVar9 | 0x40; stopCapturingMMIO(); handleSuccesiveUnderruns(); } if ((uVar2 & 4) != 0) { _DAT_0010d370 = _DAT_0010d370 + 1; uVar9 = uVar9 | 0x200; } FastWriteRegister32(this,*(void **)&(this->m_AppleIntelFramebufferController).field_0x9b0, 0x44408,uVar2); } i don't like conn patches but guess i will have to learn them sergANt idk why the kext isn't working for you maybe you can use xcode and try guess why or try whatevergreen can you check syslog using hacintool or from terminal ? if there's a good reason for probe fail it must be in syslog this is what i got using intel gpu tools reg.zip Edited May 10 by jalavoui Link to comment Share on other sites More sharing options...
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