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Delay after keying in password

Jasper Levi

By Jasper Levi,
in OSx86 10.12 (Sierra)

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MaLd0n
MaLd0n
Posted
Posted

the best result for 5820 is it, but no much pstates, the brumbaer kext solve, but sleep is gone! 

I dont use sleep ;)

with ssd, 5 or 6 seconds boot, fast open programs, dont need sleep ;)

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Jasper Levi
Jasper Levi
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the best result for 5820 is it, but no much pstates, the brumbaer kext solve, but sleep is gone! 

I dont use sleep ;)

with ssd, 5 or 6 seconds boot, fast open programs, dont need sleep ;)

 

That's an amazing kext. I wish it would work with sleep... Is the geekbench score in your signature achieved using PMDrvr? Is your 5820K overclocked or stock? That's a pretty high score,

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MaLd0n
MaLd0n
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without kext, overclock, but overclock is a Gigabyte preset in bios ;)


no diff performance with or without kext, only generate more pstates

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MaLd0n
MaLd0n
Posted
Posted

Yes!

MaLd0n 2017-05-19 às 11.28.57.png

I dont have problem with Okrasit patch, WORK VERY GOOD

 

Full DSDT Patched + SSDT Pike

 

LMU

01 lmu.png

PM

01 pm.png

EC

03 ec.png

SPSR and sSATA

4 SPSR and sSATA.png

IMEI

05 imei.png

HDMI

06 hdmi.png

ARPT

07- arpt.png

SATA

08 sata.png

FULL SBUS

09 sbus.png

PNLF

10 pnlf.png

SLPB

11 slpb.png

12.png

MaLd0n 2017-05-19 às 11.38.39.png

ETC, ETC

 

Like a real iMac 15, dont need 300 SSDTs to inject patches in DSDT ;)

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Jasper Levi
Jasper Levi
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For me, with typical load (Photoshop etc.), IPG shows (screenshot)

 

and AppleIntelInfo.kext gives me:

 

CPU Ratio Info:
------------------------------------------
Base Clock Frequency (BLCK)............. : 100 MHz
Maximum Efficiency Ratio/Frequency.......: 12 (1200 MHz)
Maximum non-Turbo Ratio/Frequency........: 33 (3300 MHz)
Maximum Turbo Ratio/Frequency............: 40 (4000 MHz)
P-State ratio * 100 = Frequency in MHz
------------------------------------------
CPU P-States [ 31 (33) 40 ]
CPU C3-Cores [ 1 2 5 6 8 11 ]
CPU C6-Cores [ 0 2 4 6 8 10 ]
CPU P-States [ (12) 31 33 40 ]
CPU C3-Cores [ 0 1 2 4 5 6 8 11 ]
CPU P-States [ 12 18 31 33 (40) ]
CPU C3-Cores [ 0 1 2 4 5 6 8 10 11 ]
CPU C6-Cores [ 0 2 4 6 8 10 11 ]
CPU C6-Cores [ 0 2 4 5 6 8 10 11 ]
CPU P-States [ (12) 18 22 31 33 40 ]
CPU P-States [ 12 18 22 23 31 (33) 40 ]
CPU C3-Cores [ 0 1 2 3 4 5 6 8 9 10 11 ]
CPU C6-Cores [ 0 1 2 3 4 5 6 8 10 11 ]
CPU P-States [ (12) 18 22 23 31 32 33 40 ]
CPU C3-Cores [ 0 1 2 3 4 5 6 7 8 9 10 11 ]
CPU C6-Cores [ 0 1 2 3 4 5 6 7 8 10 11 ]
CPU P-States [ (12) 18 22 23 26 31 32 33 40 ]
CPU P-States [ (12) 18 22 23 26 29 31 32 33 40 ]
CPU P-States [ (12) 17 18 22 23 26 29 31 32 33 40 ]
CPU P-States [ (12) 17 18 19 22 23 26 29 31 32 33 40 ]
CPU P-States [ (12) 17 18 19 20 22 23 26 29 31 32 33 40 ]
CPU P-States [ (12) 17 18 19 20 22 23 24 26 29 31 32 33 40 ]
CPU P-States [ (12) 16 17 18 19 20 22 23 24 26 29 31 32 33 40 ]
CPU P-States [ (12) 16 17 18 19 20 21 22 23 24 26 29 31 32 33 40 ]
CPU P-States [ 12 16 17 18 19 20 21 22 23 24 25 26 29 31 32 33 (40) ]
CPU P-States [ (12) 16 17 18 19 20 21 22 23 24 25 26 28 29 31 32 33 40 ]
CPU P-States [ (12) 16 17 18 19 20 21 22 23 24 25 26 27 28 29 31 32 33 40 ]
CPU P-States [ (12) 16 17 18 19 20 21 22 23 24 25 26 27 28 29 31 32 33 37 40 ]
CPU P-States [ (12) 16 17 18 19 20 21 22 23 24 25 26 27 28 29 31 32 33 34 37 40 ]
CPU P-States [ (12) 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 37 40 ]
CPU P-States [ 12 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 37 39 (40) ]
CPU P-States [ (12) 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 36 37 39 40 ]
CPU P-States [ (12) 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 36 37 39 40 ]
CPU P-States [ 12 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 36 37 38 39 (40) ]
CPU C6-Cores [ 0 1 2 3 4 5 6 7 8 9 10 11 ]
CPU P-States [ (12) 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 ]
CPU P-States [ (12) 13 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 ]
CPU P-States [ 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 (40) ]


without kexts never go below 2 Ghz, but no problem, it's intel, no AMD  :lol:

 

LOL I know what you mean! :lol:


So I dropped your SSDT back into my Clover/ACPI/patched folder, and I have the same ioreg (almost) as yours... B)

 

Thanks so much for all the hard work... 


By the way, there are three Performance Fixes by Okrasit. Do you know the differences between them?


Several of my replies to your posts have been bundled into one post somehow! I don't know how this happened...

post-682147-0-59814100-1495208092_thumb.png

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MaLd0n
MaLd0n
Posted
Posted

For me, with typical load (Photoshop etc.), IPG shows (screenshot)

 

and AppleIntelInfo.kext gives me:

 

CPU Ratio Info:

------------------------------------------

Base Clock Frequency (BLCK)............. : 100 MHz

Maximum Efficiency Ratio/Frequency.......: 12 (1200 MHz)

Maximum non-Turbo Ratio/Frequency........: 33 (3300 MHz)

Maximum Turbo Ratio/Frequency............: 40 (4000 MHz)

P-State ratio * 100 = Frequency in MHz

------------------------------------------

CPU P-States [ 31 (33) 40 ]

CPU C3-Cores [ 1 2 5 6 8 11 ]

CPU C6-Cores [ 0 2 4 6 8 10 ]

CPU P-States [ (12) 31 33 40 ]

CPU C3-Cores [ 0 1 2 4 5 6 8 11 ]

CPU P-States [ 12 18 31 33 (40) ]

CPU C3-Cores [ 0 1 2 4 5 6 8 10 11 ]

CPU C6-Cores [ 0 2 4 6 8 10 11 ]

CPU C6-Cores [ 0 2 4 5 6 8 10 11 ]

CPU P-States [ (12) 18 22 31 33 40 ]

CPU P-States [ 12 18 22 23 31 (33) 40 ]

CPU C3-Cores [ 0 1 2 3 4 5 6 8 9 10 11 ]

CPU C6-Cores [ 0 1 2 3 4 5 6 8 10 11 ]

CPU P-States [ (12) 18 22 23 31 32 33 40 ]

CPU C3-Cores [ 0 1 2 3 4 5 6 7 8 9 10 11 ]

CPU C6-Cores [ 0 1 2 3 4 5 6 7 8 10 11 ]

CPU P-States [ (12) 18 22 23 26 31 32 33 40 ]

CPU P-States [ (12) 18 22 23 26 29 31 32 33 40 ]

CPU P-States [ (12) 17 18 22 23 26 29 31 32 33 40 ]

CPU P-States [ (12) 17 18 19 22 23 26 29 31 32 33 40 ]

CPU P-States [ (12) 17 18 19 20 22 23 26 29 31 32 33 40 ]

CPU P-States [ (12) 17 18 19 20 22 23 24 26 29 31 32 33 40 ]

CPU P-States [ (12) 16 17 18 19 20 22 23 24 26 29 31 32 33 40 ]

CPU P-States [ (12) 16 17 18 19 20 21 22 23 24 26 29 31 32 33 40 ]

CPU P-States [ 12 16 17 18 19 20 21 22 23 24 25 26 29 31 32 33 (40) ]

CPU P-States [ (12) 16 17 18 19 20 21 22 23 24 25 26 28 29 31 32 33 40 ]

CPU P-States [ (12) 16 17 18 19 20 21 22 23 24 25 26 27 28 29 31 32 33 40 ]

CPU P-States [ (12) 16 17 18 19 20 21 22 23 24 25 26 27 28 29 31 32 33 37 40 ]

CPU P-States [ (12) 16 17 18 19 20 21 22 23 24 25 26 27 28 29 31 32 33 34 37 40 ]

CPU P-States [ (12) 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 37 40 ]

CPU P-States [ 12 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 37 39 (40) ]

CPU P-States [ (12) 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 36 37 39 40 ]

CPU P-States [ (12) 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 36 37 39 40 ]

CPU P-States [ 12 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 36 37 38 39 (40) ]

CPU C6-Cores [ 0 1 2 3 4 5 6 7 8 9 10 11 ]

CPU P-States [ (12) 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 ]

CPU P-States [ (12) 13 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 ]

CPU P-States [ 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 (40) ]

 

LOL I know what you mean! :lol:

So I dropped your SSDT back into my Clover/ACPI/patched folder, and I have the same ioreg (almost) as yours... B)

 

Thanks so much for all the hard work... 

By the way, there are three Performance Fixes by Okrasit. Do you know the differences between them?

Several of my replies to your posts have been bundled into one post somehow! I don't know how this happened...

no idea about Performance Fixes, i use only XCPM Performance Fix 1 © Okrasit and done

 

the replies is to avoid spam in topic, have a limit time :D

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Jasper Levi
Jasper Levi
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no idea about Performance Fixes, i use only XCPM Performance Fix 1 © Okrasit and done

 

the replies is to avoid spam in topic, have a limit time :D

 

See end of post #1 at http://www.insanelymac.com/forum/topic/314378-1012-pb-haswell-e-clover-kernel-patching-for-xcpm/

 

@okrasit - any performance fix for an i7 5820K that hits the flat turbo lines, but also comes down to 1.2 GHz when the system is idling please? Thanks in advance.

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Jasper Levi
Jasper Levi
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Hey @MaLd0n,

 

I was looking at the PCI section under System Information, and I noticed that the "Intel Corporation, C610/X99 series chipset USB XHC Host Controller" was not showing up. Could you please patch that into the DSDT and share it with me? I tried to do it on my own, but didn't succeed.

 

Thanks

DSDT.aml.zip

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Jasper Levi
Jasper Levi
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attachicon.gifDSDT.aml.zip

if u change things, let the compiler work

Return (Package () and Buffer ()

 

I did Compile after patching. This code

into device label XHCI set_label begin XHC end;
into_all all code_regex XHCI replaceall_matched begin XHC end;
into method label _DSM parent_label XHC remove_entry;
into device label XHC insert begin
Method (_DSM, 4, NotSerialized)\n
                {\n
                    Store (Package ()\n
                        {\n
                            "device-id", \n
                            Buffer ()\n
                            {\n
                                0x31, 0x8d, 0x00, 0x00\n
                            }, \n
		"name", "Intel XHCI Controller",\n
		"model", Buffer (0x37) {"Intel 99 Series Chipset Family USB xHCI Host Controller"},\n
		"device_type", Buffer (0x0E) {"USB Controller"},\n
		"AAPL,current-available", 0x0834,\n
		"AAPL,current-extra", 0x0A8C,\n
		"AAPL,current-in-sleep", 0x03E8,\n
		"AAPL,current-extra-in-sleep", 0x0834,\n
		"AAPL,max-port-current-in-sleep", 0x0A8C,\n

                           "AAPL,clock-id", \n
                            Buffer ()\n
                            {\n
                                0x01\n
                            }\n
                        }, Local0)\n
                    DTGP (Arg0, Arg1, Arg2, Arg3, RefOf (Local0))\n
                    Return (Local0)\n
                }
end;

gave the error that DGTP does not exist, and this code

into method label _DSM parent_adr 0x00140000 remove_entry;
into device name_adr 0x00140000 insert
begin
Name (_SUN, 0x0E)  // _SUN: Slot User Number\n
Method (_DSM, 4, NotSerialized)\n
                {\n
                    Store (Package ()\n
                        {\n                            
                            "device-id", \n
                            Buffer ()\n
                            {\n
                                0x31, 0x8d, 0x00, 0x00\n
                            }, \n
                            "name",\n 
                            Buffer ()\n
                            {\n
                            "Intel XHC Controller"\n
                            },\n 
                            "model",\n 
                            Buffer ()\n
                            {\n
                            "Intel 99 Series Chipset Family USB xHC Host Controller"\n
                            },\n 
                            "AAPL,current-available",\n 
                            0x0834,\n  
                            "AAPL,current-extra",\n  
                            0x0A8C,\n  
                            "AAPL,current-in-sleep",\n  
                            0x0A8C,\n  
                            "AAPL,max-port-current-in-sleep",\n  
                            0x0834,\n  
                            "AAPL,device-internal",\n  
                            Zero,\n  
                            Buffer ()\n 
                            {\n 
                                0x00\n 
                            },\n
                           "AAPL,clock-id", \n
                            Buffer ()\n
                            {\n
                                0x01\n
                            }\n
                        }, Local0)\n
                    DTGP (Arg0, Arg1, Arg2, Arg3, RefOf (Local0))\n
                    Return (Local0)\n
                }
end;

did compile without errors, but the PCI device still does not show up in System Information.

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MaLd0n
MaLd0n
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need a "AAPL,slot-name", and "model"

u dont need the patch ;)

 

add DTGP into definition block if u need

Method (DTGP, 5, NotSerialized)
    {
        If (LEqual (Arg0, Buffer (0x10)
        {
            /* 0000 */    0xC6, 0xB7, 0xB5, 0xA0, 0x18, 0x13, 0x1C, 0x44,
            /* 0008 */    0xB0, 0xC9, 0xFE, 0x69, 0x5E, 0xAF, 0x94, 0x9B
        }))
        {
            If (LEqual (Arg1, One))
            {
                If (LEqual (Arg2, Zero))
                {
                    Store (Buffer (One)
                    {
                        0x03
                    }, Arg4)
                    Return (One)
                }
                If (LEqual (Arg2, One))
                {
                    Return (One)
                }
            }
        }
        Store (Buffer (One)
        {
            0x00
        }, Arg4)
        Return (Zero)
    }
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Jasper Levi
Jasper Levi
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I tried it. It compiled without errors and booted without any panic, but there's still no XHCI showig up in my PCI Devices section. Attaching my current DSDT and ioreg for your perusal...

 

EDIT: it also does not show the built-in PCI Ethernet Controller like yours does...

 

Hey Bro, help me out please. You have done so much for me with the pre-edited DSDT. Just these small things remain...

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