Andy Vandijck Posted February 15, 2015 Share Posted February 15, 2015 (edited) It's not impossible after today. Look here at what I shared: https://github.com/andyvand/classdump-dyld/tree/master/Full It's the full dump of a retail system of Yosemite. This includes the graphics frameworks (which parallel through the graphics user clients the connection to the kernel class IOAccelerator). You would need to implement an IOFramebuffer to make initial non-accelerated picture (see VESA and the AMD docs I posted on the Developer's corner of this site... it's pretty well documented...) As for the non-documented parts... here's a good extra start... : http://sourceforge.net/p/vmsvga2/code/HEAD/tree/VMsvga2/branches/GL It actually shows how to implement a 2D graphics accelerator but it would need more work for Yosemite... The above example is based on the graphics accel for GMA950 which is actually supported only till 10.6.8 However... when you read through the code you will see that it is very easy to change that to any other... Here are symbols used by the private IOAccelerator framework to actually tie into the code of the driver: _ioAccelDeviceClassInitialize_ioAccelDeviceFinalize_ioAccelDeviceCopyFormatDescription_ioAccelDeviceCopyDebugDescription_ioAccelSharedClassInitialize_ioAccelSharedFinalize_ioAccelSharedCopyFormatDescription_ioAccelSharedCopyDebugDescription_ioAccelContextClassInitialize_ioAccelContextFinalize_ioAccelContextCopyFormatDescription_ioAccelContextCopyDebugDescription_ioAccelResourceClassInitialize__IOAccelResourceAlloc_ioAccelResourceFinalize_ioAccelResourceCopyFormatDescription_ioAccelResourceCopyDebugDescription_ioAccelDisplayPipeClassInitialize__ioAccelDisplayPipeVBLNotifyCallback_setPlaneIOSurface_ioAccelDisplayPipeFinalize_ioAccelDisplayPipeCopyFormatDescription_ioAccelDisplayPipeCopyDebugDescription_kIOAccelDeviceClass_kIOAccelSharedClass_kIOAccelContextClass_kIOAccelResourceClass_kIOAccelDisplayPipeClass_IOAccelDeviceGetTypeID.once_IOAccelSharedGetTypeID.once_IOAccelContextGetTypeID.once_IOAccelResourceGetTypeID.once_IOAccelDisplayPipeGetTypeID.once_kIOAccelDeviceID_kIOAccelSharedID_kIOAccelContextID_kIOAccelResourceID_kIOAccelDisplayPipeID_IOAccelCLContextCreate_IOAccelCLContextFinish_IOAccelCLContextFinishFenceEvent_IOAccelCLContextFinishResourceSysMem_IOAccelCLContextFlushResourceSysMem_IOAccelCLContextGetConnect_IOAccelCLContextGetDataBufferClassCount_IOAccelCLContextGetDataBufferResource_IOAccelCLContextGetFenceBuffer_IOAccelCLContextGetSidebandBuffer_IOAccelCLContextReclaimResources_IOAccelCLContextRelease_IOAccelCLContextRequestDataBuffer_IOAccelCLContextSetDataBufferClassUsedBytes_IOAccelCLContextSetExecutableName_IOAccelCLContextSubmitDataBuffers_IOAccelCLContextTestResourceSysMem_IOAccelContextAddResource_IOAccelContextCreate_IOAccelContextEnableBlockFences_IOAccelContextFinish_IOAccelContextFinishFenceEvent_IOAccelContextFinishResourceSysMem_IOAccelContextFlushResourceSysMem_IOAccelContextGetConnect_IOAccelContextGetDataBufferClassCount_IOAccelContextGetDataBufferResource_IOAccelContextGetFenceBuffer_IOAccelContextGetSidebandBuffer_IOAccelContextGetTypeID_IOAccelContextReclaimResources_IOAccelContextRelease_IOAccelContextRequestDataBuffer_IOAccelContextSetBackgroundRendering_IOAccelContextSetBlockFenceOnQueue_IOAccelContextSetDataBufferClassUsedBytes_IOAccelContextSetExecutableName_IOAccelContextSubmitDataBuffers_IOAccelContextTestResourceSysMem_IOAccelDeviceCreate_IOAccelDeviceGetConfig_IOAccelDeviceGetConfig64_IOAccelDeviceGetConnect_IOAccelDeviceGetName_IOAccelDeviceGetSurfaceInfo_IOAccelDeviceGetTypeID_IOAccelDeviceRelease_IOAccelDeviceSetFramebufferStereo_IOAccelDeviceTestEvent_IOAccelDeviceTestEventBasic_IOAccelDeviceTestEventEqual_IOAccelDeviceTestEventFast_IOAccelDeviceTestEventList_IOAccelDeviceTestEventSingle_IOAccelDisplayPipeCopyCapabilities_IOAccelDisplayPipeCreate_IOAccelDisplayPipeCreateSetVBLNotifyPort_IOAccelDisplayPipeGetDisplayModePipeScalerSetup_IOAccelDisplayPipeGetTypeID_IOAccelDisplayPipeRelease_IOAccelDisplayPipeRequestVBLNotifyCallback_IOAccelDisplayPipeTransactionBegin_IOAccelDisplayPipeTransactionEnd_IOAccelDisplayPipeTransactionSetOptions_IOAccelDisplayPipeTransactionSetPipeColorMatrix_IOAccelDisplayPipeTransactionSetPipePostGammaTable_IOAccelDisplayPipeTransactionSetPipePreGammaTable_IOAccelDisplayPipeTransactionSetPipeScaler_IOAccelDisplayPipeTransactionSetPlaneEmpty_IOAccelDisplayPipeTransactionSetPlaneIOAccelSurface_IOAccelDisplayPipeTransactionSetPlaneIOSurface_IOAccelDisplayPipeTransactionSetTimestamp_IOAccelDisplayPipeTransactionWait_IOAccelDisplayPlaneGammaTable_IOAccelGLContextClearDrawable_IOAccelGLContextCreate_IOAccelGLContextFinish_IOAccelGLContextFinishFenceEvent_IOAccelGLContextFinishResourceSysMem_IOAccelGLContextFlushResourceSysMem_IOAccelGLContextGetConnect_IOAccelGLContextGetDataBufferClassCount_IOAccelGLContextGetDataBufferResource_IOAccelGLContextGetFenceBuffer_IOAccelGLContextGetSidebandBuffer_IOAccelGLContextReadBuffer_IOAccelGLContextReclaimResources_IOAccelGLContextRelease_IOAccelGLContextRequestDataBuffer_IOAccelGLContextSetDataBufferClassUsedBytes_IOAccelGLContextSetDrawable_IOAccelGLContextSetExecutableName_IOAccelGLContextSetSurfaceVolatileState_IOAccelGLContextSetSwapInterval_IOAccelGLContextSetSwapRect_IOAccelGLContextSubmitDataBuffers_IOAccelGLContextTestResourceSysMem_IOAccelResourceCheckSysMem_IOAccelResourceClientSharedRetain_IOAccelResourceCreate_IOAccelResourceCreateAllocationIdentifierSet_IOAccelResourceCreateDataBuffer_IOAccelResourceFinishEvent_IOAccelResourceFinishSysMem_IOAccelResourceGetClientShared_IOAccelResourceGetClientSharedPrivate_IOAccelResourceGetDataBytes_IOAccelResourceGetDataSize_IOAccelResourceGetGPUVirtualAddress_IOAccelResourceGetPrivate_IOAccelResourceGetTypeID_IOAccelResourcePageoff_IOAccelResourceRelease_IOAccelResourceSetPurgeable_IOAccelResourceTestEvent_IOAccelSharedCreate_IOAccelSharedGetConnect_IOAccelSharedGetTypeID_IOAccelSharedRelease_IOAccelSharedSetWaitForGPUCallback_IOAccelVideoContextCreate_IOAccelVideoContextFinish_IOAccelVideoContextFinishFenceEvent_IOAccelVideoContextFinishResourceSysMem_IOAccelVideoContextFlushResourceSysMem_IOAccelVideoContextGetConnect_IOAccelVideoContextGetDataBufferClassCount_IOAccelVideoContextGetDataBufferResource_IOAccelVideoContextGetFenceBuffer_IOAccelVideoContextGetSidebandBuffer_IOAccelVideoContextReclaimResources_IOAccelVideoContextRelease_IOAccelVideoContextRequestDataBuffer_IOAccelVideoContextSetDataBufferClassUsedBytes_IOAccelVideoContextSetExecutableName_IOAccelVideoContextSubmitDataBuffers_IOAccelVideoContextTestResourceSysMem_ioAccelContextBlockFenceCallback_CFBundleGetIdentifier_CFBundleGetMainBundle_CFBundleGetValueForInfoDictionaryKey_CFGetRetainCount_CFGetTypeID_CFRelease_CFRetain_CFStringCreateFromExternalRepresentation_CFStringCreateWithFormat_CFStringGetCString_CFStringGetTypeID_IOCFUnserialize_IOConnectAddClient_IOConnectCallAsyncMethod_IOConnectCallAsyncScalarMethod_IOConnectCallMethod_IOConnectCallScalarMethod_IOConnectCallStructMethod_IOConnectMapMemory_IOConnectRelease_IONotificationPortCreate_IONotificationPortDestroy_IONotificationPortGetMachPort_IONotificationPortSetDispatchQueue_IOObjectRelease_IORegistryEntryCreateCFProperty_IORegistryEntryGetParentEntry_IOServiceOpen_IOSurfaceGetID_IOSurfaceGetTypeID_OSAtomicAdd32__Block_copy__Block_release__CFGetProgname__CFRuntimeCreateInstance__CFRuntimeRegisterClass___CFConstantStringClassReference___assert_rtn___bzero___stack_chk_fail___stack_chk_guard___stderrp_dispatch_async_dispatch_queue_create_dispatch_release_dispatch_retain_dlsym_fprintf_free_kCFAllocatorDefault_kCFAllocatorMallocZone_kCFBundleVersionKey_kIOMasterPortDefault_mach_port_get_attributes_mach_task_self__malloc_memcpy_msgtracer_log_with_keys_pthread_once_strncpydyld_stub_binderAs you can see it matches pretty much the real deal the kext above provides...As for the strings inside...IOAccelDeviceIOAccelSharedIOAccelContextEnableBlockFences/SourceCache/IOAcceleratorFamily/IOAcceleratorFamily-156.6/Framework/IOAccelContextRef.ccontext!context->fenceNotificationPortcom.apple.IOAccelerator.BlockFencescontext->context_connectwakePortioAccelContextBlockFenceCallbackrefcon != NULLresult == kIOReturnSuccessblockqueueIOServicemodelUnknown DeviceUnknown ApplicationIOAccelContextLogGPUHangCFGetTypeID(bundle_version) == CFStringGetTypeID()Unknown Versioncom.apple.ioacceleratorfamily.gpu_hangcom.apple.message.responsibletruefalsecom.apple.message.application_identifiercom.apple.message.application_versioncom.apple.message.device_nameGPU hang occurred, msgtracer returned %dIOAccelContextIOAccelResource/SourceCache/IOAcceleratorFamily/IOAcceleratorFamily-156.6/Framework/IOAccelResourceRef.cResource freed while busyIOAccelDisplayPipeThese show that you can easily get more info on it...Some info from the AMDRadeonX4000 kextAMDRadeonX4000_AMDGraphicsAccelerator[?:?:?]SpecialAMDKeyIOGLBundleNameIOVARendererIDIOGVACodecIOGVAEncoderRestricted%short [%short] %short:start=== AMD Graphics Accelerator successfully started ===IOFramebuffer[%u:%u:%u]ATY,intrevATY,cbitsiofb_no_regptrATY,SurfInfoATY,PageFlipEnableAccelNativeDMARowByteAlignmentAAPL,aux-power-connectedsystemWillSleepEntryExitsystemDidWakeVirtual space is readyHardware is powered upsystemWillChangeSpeedsystemDidChangeSpeed%short ** %short Device in slot: SLOT-%double **ATY,TileInfoATY,RefCLKSlot-%doublemodelhw.memsize%short::%short() - No Framebuffer mappings available. Accelerator could not be enabled.initialize_hardware------------------------%short PCIe Device: %short State: %short, channelResetMask 0x%08xENABLEDDISABLEDConfiguration: deviceBits: 0x%08x, capabilityBits: 0x%08xTotalVideoRAMBytes: 0x%016llx (%llu)IOMatchCategoryGPUDebugGARTSizeATI Radeon HD 2600 XTATI Radeon HD 2400ATI,Radeon HD 2600ATI Radeon HD 2600ATI Radeon HD 3870AMD Radeon HD 6630MAMDRadeonX4000_AMDAccelChannelUnknownGPURestartReportStart[%02u] AccelChannel: %shortCurrently pending command from %shortGLCtxCLCtxVideoCtxUnknownCtxPendingCommandTimestamp: 0x%08x, TotalDWords: 0x%08x, GART Offset=0x%016llx, stamp_idx=%double, estamp=0x%08xPendingCommandStart:PendingCommandEndGPURestartReportEndDiagnosis report buffer not allocatedSubmitClearStateSubmitting ClearStateInitAMDRadeonX4000_AMDAccelDeviceAMDRadeonX4000_AMDAccelDisplayMachinedisplayModeWillChangeExit %udisplayModeDidChangeExit - FAILEDInitialized HardwareCompleted set_display_mode_and_vramAMDRadeonX4000_AMDAccelEventMachine%short %short - %double: %short channel is hung! (timestamp=0x%08x, lastReadTimestamp=0x%08x) channelResetMask 0x%08xvirtual IOAccelChannel2 *AMDRadeonX4000_AMDAccelEventMachine::eventTimeout(int32_t)%short %short - %double: %short Could not determine the guilty channel. Returning the event channel: channelResetMask 0x%08xAMDRadeonX4000_AMDAccelResourcepageTextureDepthStencil currently requires signed char vendBuf. None presentpageTextureDepthStencil called for surface that does not require it.AMDRadeonX4000_AMDAccelSharedAMDRadeonX4000_AMDAccelSharedUserClientAMDRadeonX4000_AMDAccelStatisticsvramFreeBytesAMDRadeonX4000_AMDAccelSurfaceAMDRadeonX4000_AMDAccel2DContextAMDRadeonX4000_AMDAccelCommandBufferPoolAMDRadeonX4000_AMDInterruptEventSourceAMDRadeonX4000_AMDAccelVideoContextDefaultDataAMDRadeonX4000_AMDAccelUVDContextAMDRadeonX4000_AMDSPUAppContextAMDRadeonX4000_AMDSPUEventAMDRadeonX4000_AMDSPUContextAMDRadeonX4000_AMDAccelVCEContextAMDRadeonX4000_AMDTPTManagerAMDRadeonX4000_IAMDAtomicBlitManagerAMDRadeonX4000_AMDAtomicBlitManagerAMDRadeonX4000_AMDBltMgrAMDRadeonX4000_VendorGartAMDRadeonX4000_AMDHashTableACCELERATORGLCTXOCDCTX2DCTXSURFACESHAREDGARTPM4CAPHW_MEMORYHW_REGISTERSHW_RINGHW_DISPLAYHW_UTILHW DMA EngineALIGNMENT_MANAGERHW UVD EngineHW EngineHW PM4 EngineHW SYNCHash TableHW SPU EnginePM4 CMD UTILLINKED LISTHW VCE EngineHW Channel -- GeneralHW Channel -- PM4HW Channel -- COMPUTEHW Channel -- DMAHW Channel -- UVDHW Channel -- SPUHW Channel -- VCEDisplay MachineEvent MachineResourceStatisticsMemoryMapSysMemoryVidMemoryTaskCommandBufferDevice---------CRITICALERRORWARNINGINFO1INFO2TRACEDUMPTEST2UNKNOWNALWAYSTEST1KLOGDefaults!!!! pAMD_registry is NULL in klogInitLogLevels()KLOG is already initializedAMDRadeonX4000_AMDLinkedListAMDRadeonX4000_IAMDStatisticsManagerAMDRadeonX4000_AMDAccelStatisticsManagerAMDRadeonX4000_IAMDStatisticsGroupAMDRadeonX4000_AMDAccelStatisticsGroup%short | %shortAMDRadeonX4000_AMDHWChannelStatsGroupAMDRadeonX4000_AMDAccelCLContextAMDRadeonX4000_AMDAccelTaskAMDRadeonX4000_AMDAccelSysMemoryAMDRadeonX4000_AMDAccelVidMemoryAMDRadeonX4000_AMDAccelMemoryMapAMDSIGraphicsAcceleratorAMDPitcairnGraphicsAcceleratorAMDTahitiGraphicsAcceleratorAMDVerdeGraphicsAcceleratorAMDSIAtomicBlitManagerAMDSIDisplayMachineAMDSIResourceAMDSISurfaceAMDSIVideoContextAMDSIGLContextAMDSICLContextAMDCIGraphicsAcceleratorAMDBonaireGraphicsAcceleratorAMDHawaiiGraphicsAcceleratorAMDCIResourceAMDCICLContextAMDVIGraphicsAcceleratorAMDTongaGraphicsAcceleratorAMDVIDisplayMachineAMDVIResourceAMDRadeonX4000_AMDHWHandlerAMDRadeonX4000_AMDHWChannel%short %short%short Overflowed block waiting for PM4 to go idle.submitCommandBuffer%short: Timeout waiting for timestamp. 0x%08x[%02u] %sHWChannel: %short %shortEnabled:Disabled:IdleNot IdleIndirectCommandSize: 0x%08x, LastReadTimestamp: 0x%08x, NextSubmitTimestamp: 0x%08xCommands SubmittedCommands CompletedAMDRadeonX4000_AMDHWDisplayATIFEDSInfo2ATY,fb_offsetbuilt-inAMDRadeonX4000_AMDHWUtilitiesAMDRadeonX4000_AMDUVDInterruptEventSourceAMDRadeonX4000_AMDUVDHWChannelAMDRadeonX4000_AMDDMAHWChannelAMDRadeonX4000_AMDDMAHWEngineAMDRadeonX4000_AMDHWAlignManagerAMDRadeonX4000_AMDNullHWChannelNULLAMDRadeonX4000_AMDHWEngine[%02u] %short Engine: %short %short[%02u] %short Channel: %short %short%short Failed to reset hung GPU! result=%double ulResetBlockBitmap=0x%08x ulResetResultBitmap=0x%08xAMDRadeonX4000_AMDNullHWEngineAMDRadeonX4000_AMDHWGartATY,remap-sizeIODMACommandAMDRadeonX4000_IAMDHWInterfaceAMDRadeonX4000_IAMDHWDisplayAMDRadeonX4000_IAMDHWHandlerAMDRadeonX4000_IAMDHWAlignManagerAMDRadeonX4000_IAMDHWRegistersAMDRadeonX4000_IAMDHWMemoryAMDRadeonX4000_IAMDHWGartAMDRadeonX4000_IAMDHWRingAMDRadeonX4000_IAMDHWSemaphoreAMDRadeonX4000_IAMDHWSemaphorePoolAMDRadeonX4000_IAMDHWSemaphoreMemMgrAMDRadeonX4000_IAMDHWUtilitiesAMDRadeonX4000_IAMDPM4CommandsUtilityAMDRadeonX4000_IAMDHWEngineAMDRadeonX4000_IAMDHWChannelAMDRadeonX4000_IAMDHWVMMAMDRadeonX4000_IAMDHWVMContextDMA1VisibleNon-VisibleAMDRadeonX4000_AMDHWMemoryAMDRadeonX4000_AMDHWRegisters** Debug option for Panic __int128&& Power-Off Register Access enabled - panic now..."PANIC_ON_POWEROFF_REGISTER_ACCESS - Register READ attempt"@/SourceCache/GPUDriversAMD/GPUDriversAMD-1.30.5/Common/GLKernel/ATI/Hardware/AMDHWRegisters.cpp:172"PANIC_ON_POWEROFF_REGISTER_ACCESS - Register WRITE attempt"@/SourceCache/GPUDriversAMD/GPUDriversAMD-1.30.5/Common/GLKernel/ATI/Hardware/AMDHWRegisters.cpp:213AMDRadeonX4000_AMDHWRing[%02u] HWRing: %shortEnabledDisabledRingSizeInDwords: 0x%04x, FreeSpace: 0x%04x, Head: 0x%08x, LastSubmitPosition: 0x%08x, Tail: 0x%08xRB[%u]_RPTR: 0x%08x, RB[%u]_WPTR: 0x%08xHWRingDumpStart:0x%08x%short%short%short %short<= ReadPtr<= Tail<= LastSubmitHWRingDumpEndAMDRadeonX4000_AMDHWSemaphoreAMDRadeonX4000_AMDNullHWSemaphoreAMDRadeonX4000_AMDHWSemaphorePoolAMDRadeonX4000_AMDHWSemaphoreMemMgrAMDRadeonX4000_AMDHWVMContextAMDRadeonX4000_AMDHWVMMAMDRadeonX4000_AMDNULLVMMGRAPHICSCOMPUTE0COMPUTE1DRMDMA/SDMADRMDMA1/SDMAVCE1AMDRadeonX4000_AMDHardwareGpuDebugPolicy** m_gpuDebugPolicy value = 0x%08x*** totalMemSize: %double MB initialMemSize: %double MB%short GPU HangState 0x%08x, HangFlags 0x%08x: IndividualEngineHang %u, NonEngineBlockHang %u, FenceNotRetired %u, PerEngineReset %u, FullAsicReset %ucail_propertiesATY,bin_imageGPUDebugVM** GPU Hardware VM is %short (multispace: %short, page table updates with DMA: %short)enableddisabledATY,PPLIB_IRIATY,CAIL_IRI: ** GPU Debug Info Start **: 0x%08x %short: ** GPU Debug Info End **GPU HangFlags 0x%08x: AsicHangState 0x%08x, AsicResetRequirement 0x%08xIndividualEngineHang: %uNonEngineBlockHang : %uFenceNotRetired : %uPerEngineReset : %uFullAsicReset : %uGPU HangState 0x%08x: Hung Engines:GPUDebugMemSizeAMDRadeonX4000_AMDPM4CommandsUtilityAMDRadeonX4000_AMDPM4HWEngineAMDRadeonX4000_AMDPM4HWChannelAMDRadeonX4000_AMDSPUHWEngineAMDRadeonX4000_AMDSPUHWChannelAMDRadeonX4000_AMDVCEHWEngineAMDRadeonX4000_AMDVCEHWChannelAMDRadeonX4000_AMDUVDHWEngineAMDSIHWMemoryAMDSIDisplayAMDSIHWUtilitiesAMDSIVMContextAMDSIVMMAMDSIHardwareIOOCDBundleName** GPU ASIC Log Start **: 0x%08x** GPU ASIC Log End **** Debug option for Panic enabled - panic now..."PANIC_AFTER_DUMPING_LOG"@/SourceCache/GPUDriversAMD/GPUDriversAMD-1.30.5/Common/GLKernel/ATI/Hardware/SI/AMDSIHardware.cpp:2193[%u] PFP_HEADER_DUMP:0x%08x[%u] ME_HEADER_DUMP :SRBM_CNTL : 0x%08x | CP_ME_CNTL : 0x%08xSRBM_STATUS: 0x%08x | SRBM_STATUS2: 0x%08xGRBM_STATUS: 0x%08x | GRBM_STATUS2: 0x%08x[sh,se]=[%u,%u] spiDebugBusy 0x%08x: [LS,HS,ES]=[%u,%u,%u] [GS,VS,PS0,PS1]=[%u,%u,%u,%u] [CS0,CS1,CS2]=[%u,%u,%u]AMDTahitiHardwareAMDPitcairnHardwareAMDVerdeHardwareAMDSIHWAlignManagerAMDSIPM4EngineAMDTahitiPM4EngineAMDPitcairnPM4EngineAMDVerdePM4EngineAMDSIPM4ChannelAMDSICommandsRingAMDSIDMAEngineDMA0AMDSIDMAChannelAMDSIDMARingAMDSIVCEHWEngineVCELLQAMDSIVCEChannelAMDSIVCELLQChannelAMDSIVCERingAMDSIVCELLQRingAMDSIUVDChannelAMDSIUVDHWEngineAMDSIUVDRingAMDSISPUEngineAMDSISPUChannelAMDSISPURingAMDSIComputeRingAMDSIPM4ComputeChannelAMDCIHardware0x%08x"PANIC_AFTER_DUMPING_LOG"@/SourceCache/GPUDriversAMD/GPUDriversAMD-1.30.5/Common/GLKernel/ATI/Hardware/CI/AMDCIHardware.cpp:2324AMDBonaireHardwareAMDHawaiiHardwareAMDCIPM4Engine%short Failed to reset hung GPU: result %u, ulResetBlockBitmap 0x%08x, ulResetResultBitmap 0x%08xAMDCICommandsRingAMDCIsDMAEnginesDMA0sDMA1AMDCIsDMARingAMDCIPM4CommandsUtilityAMDCIDisplayAMDCIHWMemoryAMDCIHWUtilitiesAMDCIPM4ChannelAMDCIDMAChannelAMDCISAMUEngineSAMU RBISAMU GPCOMAMDCISAMURBIRingAMDCISAMURBIChannelAMDCISAMUGPCOMRingAMDCISAMUGPCOMChannelAMDCIUVDHWEngineAMDCIVCEHWEngineAMDCIVCEChannelAMDCIVCELLQChannelAMDCIVCERingAMDCIVCELLQRingAMDCIComputeRingAMDCIPM4ComputeChannelAMDVIHardware"PANIC_AFTER_DUMPING_LOG"@/SourceCache/GPUDriversAMD/GPUDriversAMD-1.30.5/Common/GLKernel/ATI/Hardware/VI/AMDVIHardware.cpp:2384AMDTongaHardwareAMDVIHWGartAMDVIHWMemoryAMDVIVMContextAMDVIVMMAMDVIDisplayAMDVIHWUtilitiesAMDVIsDMAChannelAMDVIsDMAEngineAMDVIsDMARingAMDVICommandsRingAMDVIComputeRingAMDVIPM4ChannelAMDVIPM4CommandsUtilityAMDVIPM4EngineAMDVIPM4ComputeChannelAMDVISAMUEngineAMDVISAMURBIRingAMDVISAMURBIChannelAMDVISAMUGPCOMRingAMDVISAMUGPCOMChannel113-C326DDR3DDR4GDDR5#213#113#177#359$$$$[ATI LIB=cail.a,2.0489,IA32]#414#103#140#175f32_rlc.data.temp.uc#2#447#106#145#101AMD Radeon Graphic ProcessorRADEONAMD RadeonDual GraphicsAMDRadeonX4000_IAMDSMLUVDAMDRadeonX4000_IAMDSMLDRMAMDRadeonX4000_IAMDSMLSPUAMDRadeonX4000_IAMDSMLVCEAMDRadeonX4000_IAMDSMLInterfaceAMDRadeonX4000_AMDSMLInterfaceAMDRadeonX4000_AMDSMLUVDAMDRadeonX4000_AMDSMLDRMAMDRadeonX4000_AMDSMLSPUAMDRadeonX4000_AMDSMLSPUMsgAMDRadeonX4000_AMDSMLVCEAMDRadeonX4000_AMDHDCPOpenSessionMsgAMDRadeonX4000_AMDHDCPCloseSessionMsgAMDRadeonX4000_AMDHDCPGetStatusMsgAMDRadeonX4000_AMDHDCPGetCertMsgAMDRadeonX4000_AMDFPGetCertMsgAMDRadeonX4000_AMDFPGenKeyMsgAMDRadeonX4000_AMDFPTestKeyMsgAMDRadeonX4000_AMDFPReleaseSessionMsgAMDRadeonX4000_AMDFPEncryptMsgAMDRadeonX4000_AMDSMLSIInterfaceAMDRadeonX4000_AMDUVDTrinityAMDRadeonX4000_AMDSIDRMAMDRadeonX4000_AMDSISPUAMDRadeonX4000_AMDSIVCEAMDRadeonX4000_AMDSMLCIKInterfaceAMDRadeonX4000_AMDUVDCIKAMDRadeonX4000_AMDCIKDRMAMDRadeonX4000_AMDCIKSPUAMDRadeonX4000_AMDCIKVCEAMDRadeonX4000_AMDSMLVIInterfaceAMDRadeonX4000_AMDUVDVIAMDRadeonX4000_AMDVIDRMAMDRadeonX4000_AMDVISPUAMDRadeonX4000_AMDVIVCEAMDRadeonAcceleratorHWChannelAMDRadeonX4000GLDriver@A|@void~?@long double}@M}1@Y}@U|@U|@A|double"unsigned long!double"int!@\"A!unsigned long!AT!unsigned long!A|int!XUk!A@bool~?int volatile!%}unsigned int!@M}1@A|@void~?@long double}@M}1@Y}@U|@U|@A|double"unsigned long!double"int!@\"A!unsigned long!AT!unsigned long!A|int!XUk!A@bool~?int volatile!%}unsigned int!@M}1@A|@void~?@long double}@M}1@Y}@U|@U|@A|double"unsigned long!double"int!@\"A!unsigned long!AT!unsigned long!A|int!XUk!A@bool~?int volatile!%}unsigned int!@M}1AMDRadeonX4000GLDriverAMDRadeonX4000GLDriver@(#)PROGRAM:AMDRadeonAccelerator PROJECT:GraphicsDrivers DEVELOPER:AMD BUILT:Dec 23 2014 00:18:161.3.0Functions in the kext (full listing):/System/Library/Extensions/AMDRadeonX4000.kext/Contents/MacOS/AMDRadeonX4000: file format mach-o-x86-64 SYMBOL TABLE: 0000000000001402 l 0e SECT 01 0000 [.text] __ZN37AMDRadeonX4000_AMDGraphicsAccelerator9MetaClassD1Ev 0000000000001d74 l 0e SECT 01 0000 [.text] __ZN37AMDRadeonX4000_AMDGraphicsAccelerator15getAccelChannelE20_eAMD_HW_ENGINE_TYPE18_eAMD_HW_RING_TYPE 0000000000004528 l 0e SECT 01 0000 [.text] __ZNK22IOGraphicsAccelerator211getWorkLoopEv 0000000000004536 l 0e SECT 01 0000 [.text] __ZN37AMDRadeonX4000_AMDGraphicsAccelerator9MetaClassD0Ev 0000000000004540 l 0e SECT 01 0000 [.text] __GLOBAL__I_a 0000000000004580 l 0e SECT 01 0000 [.text] __GLOBAL__D_a 00000000000045d2 l 0e SECT 01 0000 [.text] __ZN30AMDRadeonX4000_AMDAccelChannel9MetaClassD1Ev 0000000000005458 l 0e SECT 01 0000 [.text] __ZN30AMDRadeonX4000_AMDAccelChannel9MetaClassD0Ev 0000000000005462 l 0e SECT 01 0000 [.text] __ZN30AMDRadeonX4000_AMDAccelChannel12getHWChannelEv 000000000000546c l 0e SECT 01 0000 [.text] __ZN30AMDRadeonX4000_AMDAccelChannel7getNameEv 000000000000547a l 0e SECT 01 0000 [.text] __ZN24IOAccelCommandDescriptor4initEP22IOGraphicsAccelerator2 00000000000054c0 l 0e SECT 01 0000 [.text] __GLOBAL__I_a 0000000000005500 l 0e SECT 01 0000 [.text] __GLOBAL__D_a 0000000000005552 l 0e SECT 01 0000 [.text] __ZN29AMDRadeonX4000_AMDAccelDevice9MetaClassD1Ev 0000000000005864 l 0e SECT 01 0000 [.text] __ZN29AMDRadeonX4000_AMDAccelDevice9MetaClassD0Ev 0000000000005870 l 0e SECT 01 0000 [.text] __GLOBAL__I_a 00000000000058b0 l 0e SECT 01 0000 [.text] __GLOBAL__D_a 0000000000005902 l 0e SECT 01 0000 [.text] __ZN37AMDRadeonX4000_AMDAccelDisplayMachine9MetaClassD1Ev 0000000000007012 l 0e SECT 01 0000 [.text] __ZN37AMDRadeonX4000_AMDGraphicsAccelerator15getAccelChannelE20_eAMD_HW_ENGINE_TYPE18_eAMD_HW_RING_TYPE 00000000000093da l 0e SECT 01 0000 [.text] __ZN37AMDRadeonX4000_AMDAccelDisplayMachine9MetaClassD0Ev 00000000000093e4 l 0e SECT 01 0000 [.text] __ZN24IOAccelCommandDescriptor4initEP22IOGraphicsAccelerator2 0000000000009430 l 0e SECT 01 0000 [.text] __GLOBAL__I_a 0000000000009470 l 0e SECT 01 0000 [.text] __GLOBAL__D_a 00000000000094c2 l 0e SECT 01 0000 [.text] __ZN35AMDRadeonX4000_AMDAccelEventMachine9MetaClassD1Ev 000000000000a054 l 0e SECT 01 0000 [.text] __ZN35AMDRadeonX4000_AMDAccelEventMachine9MetaClassD0Ev 000000000000a05e l 0e SECT 01 0000 [.text] __ZN20IOAccelEventMachine216createEventQueueEv 000000000000a066 l 0e SECT 01 0000 [.text] __ZN20IOAccelEventMachine217destroyEventQueueEP17IOAccelEventQueue 000000000000a06c l 0e SECT 01 0000 [.text] __ZN20IOAccelEventMachine215cleanEventQueueEP17IOAccelEventQueue 000000000000a072 l 0e SECT 01 0000 [.text] __ZN24IOAccelEventMachineList221enableEventCollectionEv 000000000000a080 l 0e SECT 01 0000 [.text] __GLOBAL__I_a 000000000000a0c0 l 0e SECT 01 0000 [.text] __GLOBAL__D_a 000000000000a112 l 0e SECT 01 0000 [.text] __ZN31AMDRadeonX4000_AMDAccelResource9MetaClassD1Ev 000000000001189e l 0e SECT 01 0000 [.text] __ZNK16IOAccelResource214getRetainCountEv 00000000000118a8 l 0e SECT 01 0000 [.text] __ZN31AMDRadeonX4000_AMDAccelResource16getAlignedLengthEv 00000000000118e0 l 0e SECT 01 0000 [.text] __ZN31AMDRadeonX4000_AMDAccelResource19alignSurfaceToHTileEPjS0_ 00000000000118e6 l 0e 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[.text] __ZN27AMDRadeonX4000_AMDHWChannel18getChannelRingTypeEv 000000000004ef76 l 0e SECT 01 0000 [.text] __ZN27AMDRadeonX4000_AMDHWChannel33initializeSubmitCommandBufferInfoEP30AMD_SUBMIT_COMMAND_BUFFER_INFO 000000000004ef8c l 0e SECT 01 0000 [.text] __ZN27AMDRadeonX4000_AMDHWChannel25alignCommandBufferAddressEj 000000000004efa2 l 0e SECT 01 0000 [.text] __ZNK27AMDRadeonX4000_AMDHWChannel21writeSemaphoreCommandEPjyb 000000000004efaa l 0e SECT 01 0000 [.text] __ZN27AMDRadeonX4000_AMDHWChannel7getNameEv 000000000004efb4 l 0e SECT 01 0000 [.text] __ZN27AMDRadeonX4000_AMDHWChannel19dumpEngineHangStateEb 000000000004efce l 0e SECT 01 0000 [.text] __ZN27AMDRadeonX4000_AMDHWChannel21writeProfilingCommandEPjyjb 000000000004efd6 l 0e SECT 01 0000 [.text] __ZN27AMDRadeonX4000_AMDHWChannel10engineTypeEv 000000000004efe8 l 0e SECT 01 0000 [.text] __ZN27AMDRadeonX4000_AMDHWChannel18isDebugFlagEnabledEj 000000000004effc l 0e SECT 01 0000 [.text] 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[.text] __ZN26AMDRadeonX4000_AMDHWEngine9isEnabledEv 000000000004f466 l 0e SECT 01 0000 [.text] __ZN26AMDRadeonX4000_AMDHWEngine20setVirtualSpaceReadyEb 000000000004f46c l 0e SECT 01 0000 [.text] __ZN29AMDRadeonX4000_AMDDMAHWEngine27setMemoryAllocationsEnabledEb 000000000004f472 l 0e SECT 01 0000 [.text] __ZN29AMDRadeonX4000_AMDDMAHWEngine19initializeRegistersEv 000000000004f478 l 0e SECT 01 0000 [.text] __ZN29AMDRadeonX4000_AMDDMAHWEngine26systemWillChangeSpeedEventEv 000000000004f47e l 0e SECT 01 0000 [.text] __ZN29AMDRadeonX4000_AMDDMAHWEngine25systemDidChangeSpeedEventEv 000000000004f484 l 0e SECT 01 0000 [.text] __ZN26AMDRadeonX4000_AMDHWEngine10getVersionEj 000000000004f494 l 0e SECT 01 0000 [.text] __ZN26AMDRadeonX4000_AMDHWEngine15getChannelCountEv 000000000004f49e l 0e SECT 01 0000 [.text] __ZN26AMDRadeonX4000_AMDHWEngine22getTimestampIRQSourcexE18_eAMD_HW_RING_TYPE 000000000004f4a6 l 0e SECT 01 0000 [.text] __ZN26AMDRadeonX4000_AMDHWEngine14getFwvFunctionEv 000000000004f4b0 l 0e SECT 01 0000 [.text] __GLOBAL__I_a 000000000004f4f0 l 0e SECT 01 0000 [.text] __GLOBAL__D_a 000000000004f542 l 0e SECT 01 0000 [.text] __ZN32AMDRadeonX4000_AMDHWAlignManager9MetaClassD1Ev 00000000000501fa l 0e SECT 01 0000 [.text] __ZN32AMDRadeonX4000_AMDHWAlignManager9MetaClassD0Ev 0000000000050204 l 0e SECT 01 0000 [.text] __ZN33AMDRadeonX4000_IAMDHWAlignManager4initEv 0000000000050216 l 0e SECT 01 0000 [.text] __ZN32AMDRadeonX4000_AMDHWAlignManager9getHandleEv 0000000000050220 l 0e SECT 01 0000 [.text] __ZN32AMDRadeonX4000_AMDHWAlignManager15getAddrTileModeEj 0000000000050228 l 0e SECT 01 0000 [.text] __ZN32AMDRadeonX4000_AMDHWAlignManager12getArrayModeE13_AddrTileMode 0000000000050230 l 0e SECT 01 0000 [.text] __ZN32AMDRadeonX4000_AMDHWAlignManager11getTileTypeEj 0000000000050238 l 0e SECT 01 0000 [.text] __ZN32AMDRadeonX4000_AMDHWAlignManager16getMicroTileModeE13_AddrTileType 0000000000050240 l 0e SECT 01 0000 [.text] __ZN32AMDRadeonX4000_AMDHWAlignManager25getLinearAlignedTileIndexEv 000000000005024a l 0e SECT 01 0000 [.text] __ZN32AMDRadeonX4000_AMDHWAlignManager25getLinearGeneralTileIndexEv 0000000000050260 l 0e SECT 01 0000 [.text] __GLOBAL__I_a 00000000000502a0 l 0e SECT 01 0000 [.text] __GLOBAL__D_a 00000000000502f2 l 0e SECT 01 0000 [.text] __ZN31AMDRadeonX4000_AMDNullHWChannel9MetaClassD1Ev 0000000000050452 l 0e SECT 01 0000 [.text] __ZN31AMDRadeonX4000_AMDNullHWChannel4initEv 0000000000050464 l 0e SECT 01 0000 [.text] __ZN31AMDRadeonX4000_AMDNullHWChannel4freeEv 0000000000050476 l 0e SECT 01 0000 [.text] __ZN28AMDRadeonX4000_IAMDHWChannel4initEiP30AMDRadeonX4000_IAMDHWInterfaceP27AMDRadeonX4000_IAMDHWEngineP25AMDRadeonX4000_IAMDHWRingPKc 0000000000050488 l 0e SECT 01 0000 [.text] __ZN31AMDRadeonX4000_AMDNullHWChannel15getChannelIndexEv 0000000000050494 l 0e SECT 01 0000 [.text] __ZN31AMDRadeonX4000_AMDNullHWChannel18getChannelRingTypeEv 000000000005049c l 0e SECT 01 0000 [.text] __ZN31AMDRadeonX4000_AMDNullHWChannel9isEnabledEv 00000000000504a4 l 0e SECT 01 0000 [.text] __ZN31AMDRadeonX4000_AMDNullHWChannel7isEmptyEv 00000000000504ac l 0e SECT 01 0000 [.text] __ZN31AMDRadeonX4000_AMDNullHWChannel6isIdleEv 00000000000504b4 l 0e SECT 01 0000 [.text] __ZN31AMDRadeonX4000_AMDNullHWChannel18limitedWaitForIdleEjj 00000000000504bc l 0e SECT 01 0000 [.text] __ZN31AMDRadeonX4000_AMDNullHWChannel11waitForIdleEv 00000000000504c2 l 0e SECT 01 0000 [.text] __ZN31AMDRadeonX4000_AMDNullHWChannel33initializeSubmitCommandBufferInfoEP30AMD_SUBMIT_COMMAND_BUFFER_INFO 00000000000504c8 l 0e SECT 01 0000 [.text] __ZN31AMDRadeonX4000_AMDNullHWChannel19submitCommandBufferEP30AMD_SUBMIT_COMMAND_BUFFER_INFOPj 00000000000504d0 l 0e SECT 01 0000 [.text] __ZN31AMDRadeonX4000_AMDNullHWChannel16waitForTimestampEjPyb 00000000000504d8 l 0e SECT 01 0000 [.text] __ZN31AMDRadeonX4000_AMDNullHWChannel17checkForTimestampEj 00000000000504e0 l 0e SECT 01 0000 [.text] __ZN31AMDRadeonX4000_AMDNullHWChannel29waitForLastSubmittedTimestampEv 00000000000504e8 l 0e SECT 01 0000 [.text] __ZN31AMDRadeonX4000_AMDNullHWChannel25getCommandSubmitTimestampEv 00000000000504f4 l 0e SECT 01 0000 [.text] __ZN31AMDRadeonX4000_AMDNullHWChannel27getCommandLastReadTimestampEv 00000000000504fc l 0e SECT 01 0000 [.text] __ZN31AMDRadeonX4000_AMDNullHWChannel24setCommandTimestampPairsEPjS0_ 0000000000050502 l 0e SECT 01 0000 [.text] __ZN31AMDRadeonX4000_AMDNullHWChannel20alignIBCommandBufferEPjj 000000000005050a l 0e SECT 01 0000 [.text] __ZN31AMDRadeonX4000_AMDNullHWChannel25alignCommandBufferAddressEj 0000000000050512 l 0e SECT 01 0000 [.text] __ZN31AMDRadeonX4000_AMDNullHWChannel20getIBAlignmentFactorEv 000000000005051a l 0e SECT 01 0000 [.text] __ZN31AMDRadeonX4000_AMDNullHWChannel21getOneDwordNOPCommandEv 0000000000050522 l 0e SECT 01 0000 [.text] __ZN31AMDRadeonX4000_AMDNullHWChannel23writeSurfaceSyncCommandEPjjyyj 000000000005052c l 0e SECT 01 0000 [.text] __ZN31AMDRadeonX4000_AMDNullHWChannel22writeEventWriteCommandEPjjj 0000000000050536 l 0e SECT 01 0000 [.text] __ZN31AMDRadeonX4000_AMDNullHWChannel25writeEventWriteEOPCommandEPjjjyjjy 0000000000050540 l 0e SECT 01 0000 [.text] __ZNK31AMDRadeonX4000_AMDNullHWChannel21writeSemaphoreCommandEPjyb 0000000000050548 l 0e SECT 01 0000 [.text] __ZN31AMDRadeonX4000_AMDNullHWChannel7getNameEv 0000000000050556 l 0e SECT 01 0000 [.text] __ZN31AMDRadeonX4000_AMDNullHWChannel13setDebugFlagsEj 000000000005055c l 0e SECT 01 0000 [.text] __ZN31AMDRadeonX4000_AMDNullHWChannel15clearDebugFlagsEj 0000000000050562 l 0e SECT 01 0000 [.text] __ZN31AMDRadeonX4000_AMDNullHWChannel32timeStampEnableInterruptAndSleepEj 000000000005056a l 0e SECT 01 0000 [.text] __ZN31AMDRadeonX4000_AMDNullHWChannel25timeStampDisableInterruptEv 0000000000050570 l 0e SECT 01 0000 [.text] __ZN31AMDRadeonX4000_AMDNullHWChannel18isTimeStampExpiredEj 0000000000050578 l 0e SECT 01 0000 [.text] __ZN31AMDRadeonX4000_AMDNullHWChannel18vblEnableInterruptEv 000000000005057e l 0e SECT 01 0000 [.text] __ZN31AMDRadeonX4000_AMDNullHWChannel19vblDisableInterruptEv 0000000000050584 l 0e SECT 01 0000 [.text] __ZN31AMDRadeonX4000_AMDNullHWChannel19dumpEngineHangStateEb 000000000005058a l 0e SECT 01 0000 [.text] __ZN31AMDRadeonX4000_AMDNullHWChannel22hasPendingWaitCommandsEj 0000000000050592 l 0e SECT 01 0000 [.text] __ZN31AMDRadeonX4000_AMDNullHWChannel21writeProfilingCommandEPjyjb 000000000005059a l 0e SECT 01 0000 [.text] __ZN31AMDRadeonX4000_AMDNullHWChannel10engineTypeEv 00000000000505a6 l 0e SECT 01 0000 [.text] __ZN31AMDRadeonX4000_AMDNullHWChannel20writeDiagnosisReportERPcRj 00000000000505ac l 0e SECT 01 0000 [.text] __ZN31AMDRadeonX4000_AMDNullHWChannel18isDebugFlagEnabledEj 00000000000505b4 l 0e SECT 01 0000 [.text] __ZN31AMDRadeonX4000_AMDNullHWChannel9MetaClassD0Ev 00000000000505c0 l 0e SECT 01 0000 [.text] __GLOBAL__I_a 0000000000050600 l 0e SECT 01 0000 [.text] __GLOBAL__D_a 0000000000050652 l 0e SECT 01 0000 [.text] __ZN26AMDRadeonX4000_AMDHWEngine9MetaClassD1Ev 0000000000050efa l 0e SECT 01 0000 [.text] __ZN26AMDRadeonX4000_AMDHWEngine9MetaClassD0Ev 0000000000050f04 l 0e SECT 01 0000 [.text] __ZN27AMDRadeonX4000_IAMDHWEngine4initEv 0000000000050f16 l 0e SECT 01 0000 [.text] __ZN26AMDRadeonX4000_AMDHWEngine4typeEv 0000000000050f20 l 0e SECT 01 0000 [.text] __ZN26AMDRadeonX4000_AMDHWEngine9isEnabledEv 0000000000050f2a l 0e SECT 01 0000 [.text] __ZN26AMDRadeonX4000_AMDHWEngine20setVirtualSpaceReadyEb 0000000000050f30 l 0e SECT 01 0000 [.text] __ZN26AMDRadeonX4000_AMDHWEngine10getVersionEj 0000000000050f40 l 0e SECT 01 0000 [.text] __ZN26AMDRadeonX4000_AMDHWEngine15getChannelCountEv 0000000000050f4a l 0e SECT 01 0000 [.text] __ZN26AMDRadeonX4000_AMDHWEngine22getTimestampIRQSourcexE18_eAMD_HW_RING_TYPE 0000000000050f52 l 0e SECT 01 0000 [.text] __ZN26AMDRadeonX4000_AMDHWEngine14getFwvFunctionEv 0000000000050f60 l 0e SECT 01 0000 [.text] __GLOBAL__I_a 0000000000050fa0 l 0e SECT 01 0000 [.text] __GLOBAL__D_a 0000000000050ff2 l 0e SECT 01 0000 [.text] __ZN30AMDRadeonX4000_AMDNullHWEngine9MetaClassD1Ev 0000000000051152 l 0e SECT 01 0000 [.text] __ZN27AMDRadeonX4000_IAMDHWEngine4initEv 0000000000051164 l 0e SECT 01 0000 [.text] __ZN30AMDRadeonX4000_AMDNullHWEngine4freeEv 0000000000051176 l 0e SECT 01 0000 [.text] __ZN30AMDRadeonX4000_AMDNullHWEngine4typeEv 0000000000051182 l 0e SECT 01 0000 [.text] __ZN30AMDRadeonX4000_AMDNullHWEngine7powerUpEv 000000000005118a l 0e SECT 01 0000 [.text] __ZN30AMDRadeonX4000_AMDNullHWEngine8powerOffEv 0000000000051192 l 0e SECT 01 0000 [.text] __ZN30AMDRadeonX4000_AMDNullHWEngine5startEv 000000000005119a l 0e SECT 01 0000 [.text] __ZN30AMDRadeonX4000_AMDNullHWEngine4stopEv 00000000000511a2 l 0e SECT 01 0000 [.text] __ZN30AMDRadeonX4000_AMDNullHWEngine9isEnabledEv 00000000000511aa l 0e SECT 01 0000 [.text] __ZN30AMDRadeonX4000_AMDNullHWEngine20setVirtualSpaceReadyEb 00000000000511b0 l 0e SECT 01 0000 [.text] __ZN30AMDRadeonX4000_AMDNullHWEngine27setMemoryAllocationsEnabledEb 00000000000511b6 l 0e SECT 01 0000 [.text] __ZN30AMDRadeonX4000_AMDNullHWEngine19initializeRegistersEv 00000000000511bc l 0e SECT 01 0000 [.text] __ZN30AMDRadeonX4000_AMDNullHWEngine26systemWillChangeSpeedEventEv 00000000000511c2 l 0e SECT 01 0000 [.text] __ZN30AMDRadeonX4000_AMDNullHWEngine25systemDidChangeSpeedEventEv 00000000000511c8 l 0e SECT 01 0000 [.text] __ZN30AMDRadeonX4000_AMDNullHWEngine33initializeSubmitCommandBufferInfoEP30AMD_SUBMIT_COMMAND_BUFFER_INFO 00000000000511ce l 0e SECT 01 0000 [.text] __ZN30AMDRadeonX4000_AMDNullHWEngine6isIdleEv 00000000000511d6 l 0e SECT 01 0000 [.text] __ZN30AMDRadeonX4000_AMDNullHWEngine18limitedWaitForIdleEjj 00000000000511de l 0e SECT 01 0000 [.text] __ZN30AMDRadeonX4000_AMDNullHWEngine11waitForIdleEv 00000000000511e4 l 0e SECT 01 0000 [.text] __ZN30AMDRadeonX4000_AMDNullHWEngine25alignCommandBufferAddressEj 00000000000511ec l 0e SECT 01 0000 [.text] __ZN30AMDRadeonX4000_AMDNullHWEngine10getVersionEj 00000000000511f4 l 0e SECT 01 0000 [.text] __ZN30AMDRadeonX4000_AMDNullHWEngine15getChannelCountEv 00000000000511fc l 0e SECT 01 0000 [.text] __ZN30AMDRadeonX4000_AMDNullHWEngine12getHWChannelE18_eAMD_HW_RING_TYPE 0000000000051204 l 0e SECT 01 0000 [.text] __ZN30AMDRadeonX4000_AMDNullHWEngine22getTimestampIRQSourcexE18_eAMD_HW_RING_TYPE 000000000005120c l 0e SECT 01 0000 [.text] __ZN30AMDRadeonX4000_AMDNullHWEngine14getFwvFunctionEv 0000000000051214 l 0e SECT 01 0000 [.text] __ZN30AMDRadeonX4000_AMDNullHWEngine19dumpEngineHangStateEb 000000000005121a l 0e SECT 01 0000 [.text] __ZN30AMDRadeonX4000_AMDNullHWEngine20writeDiagnosisReportERPcRj 0000000000051220 l 0e SECT 01 0000 [.text] __ZN30AMDRadeonX4000_AMDNullHWEngine5resetE18_eAMD_HW_RING_TYPE 0000000000051228 l 0e SECT 01 0000 [.text] __ZN30AMDRadeonX4000_AMDNullHWEngine4initEP30AMDRadeonX4000_IAMDHWInterface20_eAMD_HW_ENGINE_TYPE 000000000005123a l 0e SECT 01 0000 [.text] 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0000 [.text] __GLOBAL__D_a 0000000000052592 l 0e SECT 01 0000 [.text] __ZN30AMDRadeonX4000_IAMDHWInterface9MetaClassD1Ev 000000000005266c l 0e SECT 01 0000 [.text] __ZN28AMDRadeonX4000_IAMDHWDisplay9MetaClassD1Ev 0000000000052746 l 0e SECT 01 0000 [.text] __ZN28AMDRadeonX4000_IAMDHWHandler9MetaClassD1Ev 0000000000052820 l 0e SECT 01 0000 [.text] __ZN33AMDRadeonX4000_IAMDHWAlignManager9MetaClassD1Ev 00000000000528fa l 0e SECT 01 0000 [.text] __ZN30AMDRadeonX4000_IAMDHWRegisters9MetaClassD1Ev 00000000000529d4 l 0e SECT 01 0000 [.text] __ZN27AMDRadeonX4000_IAMDHWMemory9MetaClassD1Ev 0000000000052aae l 0e SECT 01 0000 [.text] __ZN25AMDRadeonX4000_IAMDHWGart9MetaClassD1Ev 0000000000052b88 l 0e SECT 01 0000 [.text] __ZN25AMDRadeonX4000_IAMDHWRing9MetaClassD1Ev 0000000000052c62 l 0e SECT 01 0000 [.text] __ZN30AMDRadeonX4000_IAMDHWSemaphore9MetaClassD1Ev 0000000000052d3c l 0e SECT 01 0000 [.text] __ZN34AMDRadeonX4000_IAMDHWSemaphorePool9MetaClassD1Ev 0000000000052e16 l 0e SECT 01 0000 [.text] __ZN36AMDRadeonX4000_IAMDHWSemaphoreMemMgr9MetaClassD1Ev 0000000000052ef0 l 0e SECT 01 0000 [.text] __ZN30AMDRadeonX4000_IAMDHWUtilities9MetaClassD1Ev 0000000000052fca l 0e SECT 01 0000 [.text] __ZN37AMDRadeonX4000_IAMDPM4CommandsUtility9MetaClassD1Ev 00000000000530a4 l 0e SECT 01 0000 [.text] __ZN27AMDRadeonX4000_IAMDHWEngine9MetaClassD1Ev 000000000005317e l 0e SECT 01 0000 [.text] __ZN28AMDRadeonX4000_IAMDHWChannel9MetaClassD1Ev 0000000000053258 l 0e SECT 01 0000 [.text] __ZN24AMDRadeonX4000_IAMDHWVMM9MetaClassD1Ev 0000000000053332 l 0e SECT 01 0000 [.text] __ZN30AMDRadeonX4000_IAMDHWVMContext9MetaClassD1Ev 00000000000533da l 0e SECT 01 0000 [.text] __ZN27AMDRadeonX4000_IAMDHWMemory4initEv 00000000000533ec l 0e SECT 01 0000 [.text] __ZN27AMDRadeonX4000_IAMDHWMemory4freeEv 00000000000533fe l 0e SECT 01 0000 [.text] __ZN30AMDRadeonX4000_IAMDHWInterface4initEv 0000000000053410 l 0e SECT 01 0000 [.text] __ZN30AMDRadeonX4000_IAMDHWInterface4freeEv 0000000000053422 l 0e SECT 01 0000 [.text] __ZN30AMDRadeonX4000_IAMDHWInterface9MetaClassD0Ev 000000000005342c l 0e SECT 01 0000 [.text] __ZN28AMDRadeonX4000_IAMDHWDisplay9MetaClassD0Ev 0000000000053436 l 0e SECT 01 0000 [.text] __ZN28AMDRadeonX4000_IAMDHWHandler4initEv 0000000000053448 l 0e SECT 01 0000 [.text] __ZN28AMDRadeonX4000_IAMDHWHandler4freeEv 000000000005345a l 0e SECT 01 0000 [.text] __ZN28AMDRadeonX4000_IAMDHWHandler9MetaClassD0Ev 0000000000053464 l 0e SECT 01 0000 [.text] __ZN33AMDRadeonX4000_IAMDHWAlignManager4initEv 0000000000053476 l 0e SECT 01 0000 [.text] __ZN33AMDRadeonX4000_IAMDHWAlignManager4freeEv 0000000000053488 l 0e SECT 01 0000 [.text] __ZN33AMDRadeonX4000_IAMDHWAlignManager9MetaClassD0Ev 0000000000053492 l 0e SECT 01 0000 [.text] __ZN30AMDRadeonX4000_IAMDHWRegisters4initEv 00000000000534a4 l 0e SECT 01 0000 [.text] __ZN30AMDRadeonX4000_IAMDHWRegisters4freeEv 00000000000534b6 l 0e SECT 01 0000 [.text] __ZN30AMDRadeonX4000_IAMDHWRegisters9MetaClassD0Ev 00000000000534c0 l 0e SECT 01 0000 [.text] __ZN27AMDRadeonX4000_IAMDHWMemory9MetaClassD0Ev 00000000000534ca l 0e SECT 01 0000 [.text] __ZN25AMDRadeonX4000_IAMDHWGart4initEv 00000000000534dc l 0e SECT 01 0000 [.text] __ZN25AMDRadeonX4000_IAMDHWGart4freeEv 00000000000534ee l 0e SECT 01 0000 [.text] __ZN25AMDRadeonX4000_IAMDHWGart9MetaClassD0Ev 00000000000534f8 l 0e SECT 01 0000 [.text] __ZN25AMDRadeonX4000_IAMDHWRing4initEv 000000000005350a l 0e SECT 01 0000 [.text] __ZN25AMDRadeonX4000_IAMDHWRing4freeEv 000000000005351c l 0e SECT 01 0000 [.text] __ZN25AMDRadeonX4000_IAMDHWRing9MetaClassD0Ev 0000000000053526 l 0e SECT 01 0000 [.text] __ZN30AMDRadeonX4000_IAMDHWSemaphore4initEv 0000000000053538 l 0e SECT 01 0000 [.text] __ZN30AMDRadeonX4000_IAMDHWSemaphore4freeEv 000000000005354a l 0e SECT 01 0000 [.text] __ZN30AMDRadeonX4000_IAMDHWSemaphore9MetaClassD0Ev 0000000000053554 l 0e SECT 01 0000 [.text] __ZN34AMDRadeonX4000_IAMDHWSemaphorePool4initEv 0000000000053566 l 0e SECT 01 0000 [.text] __ZN34AMDRadeonX4000_IAMDHWSemaphorePool4freeEv 0000000000053578 l 0e SECT 01 0000 [.text] __ZN34AMDRadeonX4000_IAMDHWSemaphorePool9MetaClassD0Ev 0000000000053582 l 0e SECT 01 0000 [.text] __ZN36AMDRadeonX4000_IAMDHWSemaphoreMemMgr4initEv 0000000000053594 l 0e SECT 01 0000 [.text] __ZN36AMDRadeonX4000_IAMDHWSemaphoreMemMgr4freeEv 00000000000535a6 l 0e SECT 01 0000 [.text] __ZN36AMDRadeonX4000_IAMDHWSemaphoreMemMgr9MetaClassD0Ev 00000000000535b0 l 0e SECT 01 0000 [.text] __ZN30AMDRadeonX4000_IAMDHWUtilities4initEv 00000000000535c2 l 0e SECT 01 0000 [.text] __ZN30AMDRadeonX4000_IAMDHWUtilities4freeEv 00000000000535d4 l 0e SECT 01 0000 [.text] __ZN30AMDRadeonX4000_IAMDHWUtilities9MetaClassD0Ev 00000000000535de l 0e SECT 01 0000 [.text] __ZN37AMDRadeonX4000_IAMDPM4CommandsUtility4initEv 00000000000535f0 l 0e SECT 01 0000 [.text] __ZN37AMDRadeonX4000_IAMDPM4CommandsUtility4freeEv 0000000000053602 l 0e SECT 01 0000 [.text] __ZN37AMDRadeonX4000_IAMDPM4CommandsUtility9MetaClassD0Ev 000000000005360c l 0e SECT 01 0000 [.text] __ZN27AMDRadeonX4000_IAMDHWEngine4initEv 000000000005361e l 0e SECT 01 0000 [.text] __ZN27AMDRadeonX4000_IAMDHWEngine4freeEv 0000000000053630 l 0e SECT 01 0000 [.text] __ZN27AMDRadeonX4000_IAMDHWEngine9MetaClassD0Ev 000000000005363a l 0e SECT 01 0000 [.text] __ZN28AMDRadeonX4000_IAMDHWChannel4initEv 000000000005364c l 0e SECT 01 0000 [.text] __ZN28AMDRadeonX4000_IAMDHWChannel4freeEv 000000000005365e l 0e SECT 01 0000 [.text] __ZN28AMDRadeonX4000_IAMDHWChannel4initEiP30AMDRadeonX4000_IAMDHWInterfaceP27AMDRadeonX4000_IAMDHWEngineP25AMDRadeonX4000_IAMDHWRingPKc 0000000000053670 l 0e SECT 01 0000 [.text] __ZN28AMDRadeonX4000_IAMDHWChannel9MetaClassD0Ev 000000000005367a l 0e SECT 01 0000 [.text] __ZN24AMDRadeonX4000_IAMDHWVMM4initEv 000000000005368c l 0e SECT 01 0000 [.text] __ZN24AMDRadeonX4000_IAMDHWVMM4freeEv 000000000005369e l 0e SECT 01 0000 [.text] __ZN24AMDRadeonX4000_IAMDHWVMM9MetaClassD0Ev 00000000000536a8 l 0e SECT 01 0000 [.text] __ZN30AMDRadeonX4000_IAMDHWVMContext4initEv 00000000000536ba l 0e SECT 01 0000 [.text] __ZN30AMDRadeonX4000_IAMDHWVMContext4freeEv 00000000000536cc l 0e SECT 01 0000 [.text] __ZN30AMDRadeonX4000_IAMDHWVMContext9MetaClassD0Ev 00000000000536e0 l 0e SECT 01 0000 [.text] __GLOBAL__I_a 00000000000539b0 l 0e SECT 01 0000 [.text] __GLOBAL__D_a 0000000000053ac2 l 0e SECT 01 0000 [.text] __ZN26AMDRadeonX4000_AMDHWMemory9MetaClassD1Ev 000000000005553a l 0e SECT 01 0000 [.text] __ZN26AMDRadeonX4000_AMDHWMemory9MetaClassD0Ev 0000000000055544 l 0e SECT 01 0000 [.text] __ZN27AMDRadeonX4000_IAMDHWMemory4initEv 0000000000055556 l 0e SECT 01 0000 [.text] __ZN26AMDRadeonX4000_AMDHWMemory19getMemoryDescriptorEv 0000000000055564 l 0e SECT 01 0000 [.text] __ZN26AMDRadeonX4000_AMDHWMemory8isMappedEv 0000000000055570 l 0e SECT 01 0000 [.text] __ZN26AMDRadeonX4000_AMDHWMemory20setReservedNdrvSpaceEy 000000000005557a l 0e SECT 01 0000 [.text] __ZN26AMDRadeonX4000_AMDHWMemory12getTotalSizeEv 0000000000055584 l 0e SECT 01 0000 [.text] __ZN26AMDRadeonX4000_AMDHWMemory14getVisibleSizeEv 000000000005558e l 0e SECT 01 0000 [.text] __ZN26AMDRadeonX4000_AMDHWMemory16getInvisibleSizeEv 000000000005559c l 0e SECT 01 0000 [.text] __ZN26AMDRadeonX4000_AMDHWMemory24isNonVisibleMemoryExistsEv 00000000000555b0 l 0e SECT 01 0000 [.text] __GLOBAL__I_a 00000000000555f0 l 0e SECT 01 0000 [.text] __GLOBAL__D_a 0000000000055642 l 0e SECT 01 0000 [.text] __ZN29AMDRadeonX4000_AMDHWRegisters9MetaClassD1Ev 0000000000055b4c l 0e SECT 01 0000 [.text] __ZN29AMDRadeonX4000_AMDHWRegisters9MetaClassD0Ev 0000000000055b56 l 0e SECT 01 0000 [.text] __ZN30AMDRadeonX4000_IAMDHWRegisters4initEv 0000000000055b68 l 0e SECT 01 0000 [.text] __ZN29AMDRadeonX4000_AMDHWRegisters9isEnabledEv 0000000000055b80 l 0e SECT 01 0000 [.text] __GLOBAL__I_a 0000000000055bc0 l 0e SECT 01 0000 [.text] __GLOBAL__D_a 0000000000055c12 l 0e SECT 01 0000 [.text] __ZN24AMDRadeonX4000_AMDHWRing9MetaClassD1Ev 000000000005661c l 0e SECT 01 0000 [.text] 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0000000000056700 l 0e SECT 01 0000 [.text] __GLOBAL__I_a 0000000000056740 l 0e SECT 01 0000 [.text] __GLOBAL__D_a 0000000000056792 l 0e SECT 01 0000 [.text] __ZN29AMDRadeonX4000_AMDHWSemaphore9MetaClassD1Ev 0000000000056ca6 l 0e SECT 01 0000 [.text] __ZN30AMDRadeonX4000_IAMDHWSemaphore4initEv 0000000000056cb8 l 0e SECT 01 0000 [.text] __ZN29AMDRadeonX4000_AMDHWSemaphore6setTagEj 0000000000056cc4 l 0e SECT 01 0000 [.text] __ZN29AMDRadeonX4000_AMDHWSemaphore6getTagEv 0000000000056cd0 l 0e SECT 01 0000 [.text] __ZN29AMDRadeonX4000_AMDHWSemaphore11waitForDoneEv 0000000000056cfc l 0e SECT 01 0000 [.text] __ZN29AMDRadeonX4000_AMDHWSemaphore21registerEventListenerEP30AMDRadeonX4000_IAMDHWInterface19_eAMD_HW_EVENT_TYPE 0000000000056d04 l 0e SECT 01 0000 [.text] __ZN29AMDRadeonX4000_AMDHWSemaphore23unregisterEventListenerEP30AMDRadeonX4000_IAMDHWInterface19_eAMD_HW_EVENT_TYPE 0000000000056d0c l 0e SECT 01 0000 [.text] __ZN29AMDRadeonX4000_AMDHWSemaphore14getSignalEventEv 0000000000056d16 l 0e SECT 01 0000 [.text] __ZN29AMDRadeonX4000_AMDHWSemaphore12getWaitEventEv 0000000000056d20 l 0e SECT 01 0000 [.text] __ZN29AMDRadeonX4000_AMDHWSemaphore9MetaClassD0Ev 0000000000056d30 l 0e SECT 01 0000 [.text] __GLOBAL__I_a 0000000000056d70 l 0e SECT 01 0000 [.text] __GLOBAL__D_a 0000000000056dc2 l 0e SECT 01 0000 [.text] __ZN33AMDRadeonX4000_AMDNullHWSemaphore9MetaClassD1Ev 0000000000056f22 l 0e SECT 01 0000 [.text] __ZN33AMDRadeonX4000_AMDNullHWSemaphore9MetaClassD0Ev 0000000000056f2c l 0e SECT 01 0000 [.text] __ZN30AMDRadeonX4000_IAMDHWSemaphore4initEv 0000000000056f3e l 0e SECT 01 0000 [.text] __ZN33AMDRadeonX4000_AMDNullHWSemaphore4freeEv 0000000000056f44 l 0e SECT 01 0000 [.text] __ZN33AMDRadeonX4000_AMDNullHWSemaphore4waitEP12IOAccelEventiPjRj 0000000000056f4c l 0e SECT 01 0000 [.text] __ZN33AMDRadeonX4000_AMDNullHWSemaphore6signalEP12IOAccelEventiPjRj 0000000000056f54 l 0e SECT 01 0000 [.text] __ZN33AMDRadeonX4000_AMDNullHWSemaphore4doneEv 0000000000056f5c l 0e SECT 01 0000 [.text] __ZN33AMDRadeonX4000_AMDNullHWSemaphore5resetEv 0000000000056f62 l 0e SECT 01 0000 [.text] __ZN33AMDRadeonX4000_AMDNullHWSemaphore8setStateEb 0000000000056f68 l 0e SECT 01 0000 [.text] __ZN33AMDRadeonX4000_AMDNullHWSemaphore6setTagEj 0000000000056f72 l 0e SECT 01 0000 [.text] __ZN33AMDRadeonX4000_AMDNullHWSemaphore6getTagEv 0000000000056f7c l 0e SECT 01 0000 [.text] __ZN33AMDRadeonX4000_AMDNullHWSemaphore11waitForDoneEv 0000000000056f82 l 0e SECT 01 0000 [.text] __ZN33AMDRadeonX4000_AMDNullHWSemaphore21registerEventListenerEP30AMDRadeonX4000_IAMDHWInterface19_eAMD_HW_EVENT_TYPE 0000000000056f8a l 0e SECT 01 0000 [.text] __ZN33AMDRadeonX4000_AMDNullHWSemaphore23unregisterEventListenerEP30AMDRadeonX4000_IAMDHWInterface19_eAMD_HW_EVENT_TYPE 0000000000056f92 l 0e SECT 01 0000 [.text] __ZN33AMDRadeonX4000_AMDNullHWSemaphore14getSignalEventEv 0000000000056f9a l 0e SECT 01 0000 [.text] __ZN33AMDRadeonX4000_AMDNullHWSemaphore12getWaitEventEv 0000000000056fa2 l 0e SECT 01 0000 [.text] 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0000000000057c70 l 0e SECT 01 0000 [.text] __ZN35AMDRadeonX4000_AMDHWSemaphoreMemMgr9MetaClassD0Ev 0000000000057c7a l 0e SECT 01 0000 [.text] __ZN36AMDRadeonX4000_IAMDHWSemaphoreMemMgr4initEv 0000000000057c90 l 0e SECT 01 0000 [.text] __GLOBAL__I_a 0000000000057cd0 l 0e SECT 01 0000 [.text] __GLOBAL__D_a 0000000000057d22 l 0e SECT 01 0000 [.text] __ZN29AMDRadeonX4000_AMDHWVMContext9MetaClassD1Ev 0000000000058b24 l 0e SECT 01 0000 [.text] __ZN29AMDRadeonX4000_AMDHWVMContext9MetaClassD0Ev 0000000000058b2e l 0e SECT 01 0000 [.text] __ZN30AMDRadeonX4000_IAMDHWVMContext4initEv 0000000000058b40 l 0e SECT 01 0000 [.text] __ZN29AMDRadeonX4000_AMDHWVMContext10mapLocalVAEyyy 0000000000058b66 l 0e SECT 01 0000 [.text] __ZN29AMDRadeonX4000_AMDHWVMContext11mapSystemVAEyP18IOMemoryDescriptor 0000000000058b90 l 0e SECT 01 0000 [.text] __ZN29AMDRadeonX4000_AMDHWVMContext11mapSystemVAEyyy 0000000000058bb8 l 0e SECT 01 0000 [.text] __ZN29AMDRadeonX4000_AMDHWVMContext14getCurrentVMIDEv 0000000000058bd4 l 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0000 [.text] __GLOBAL__I_a 00000000000599e0 l 0e SECT 01 0000 [.text] __GLOBAL__D_a 0000000000059a32 l 0e SECT 01 0000 [.text] __ZN25AMDRadeonX4000_AMDNULLVMM9MetaClassD1Ev 0000000000059b92 l 0e SECT 01 0000 [.text] __ZN24AMDRadeonX4000_IAMDHWVMM4initEv 0000000000059ba4 l 0e SECT 01 0000 [.text] __ZN25AMDRadeonX4000_AMDNULLVMM4freeEv 0000000000059bb6 l 0e SECT 01 0000 [.text] __ZN25AMDRadeonX4000_AMDNULLVMM4initEP30AMDRadeonX4000_IAMDHWInterface 0000000000059bc8 l 0e SECT 01 0000 [.text] __ZN25AMDRadeonX4000_AMDNULLVMM20setVirtualSpaceReadyEb 0000000000059bce l 0e SECT 01 0000 [.text] __ZN25AMDRadeonX4000_AMDNULLVMM27setMemoryAllocationsEnabledEb 0000000000059bd4 l 0e SECT 01 0000 [.text] __ZN25AMDRadeonX4000_AMDNULLVMM15createVMContextEv 0000000000059bdc l 0e SECT 01 0000 [.text] __ZN25AMDRadeonX4000_AMDNULLVMM16releaseVMContextEP30AMDRadeonX4000_IAMDHWVMContext 0000000000059be2 l 0e SECT 01 0000 [.text] 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0000000000059c20 l 0e SECT 01 0000 [.text] __ZN25AMDRadeonX4000_AMDNULLVMM21getVMPTVirtualAddressEy 0000000000059c28 l 0e SECT 01 0000 [.text] __ZN25AMDRadeonX4000_AMDNULLVMM15getVMRangeStartEv 0000000000059c30 l 0e SECT 01 0000 [.text] __ZN25AMDRadeonX4000_AMDNULLVMM13getVMRangeEndEv 0000000000059c38 l 0e SECT 01 0000 [.text] __ZN25AMDRadeonX4000_AMDNULLVMM16getVMPTBCoverageEv 0000000000059c40 l 0e SECT 01 0000 [.text] __ZN25AMDRadeonX4000_AMDNULLVMM16getVMPTBVRAMSizeEv 0000000000059c48 l 0e SECT 01 0000 [.text] __ZN25AMDRadeonX4000_AMDNULLVMM16getVMPTDVRAMSizeEv 0000000000059c50 l 0e SECT 01 0000 [.text] __ZN25AMDRadeonX4000_AMDNULLVMM13getVMPTBTotalEv 0000000000059c58 l 0e SECT 01 0000 [.text] __ZN25AMDRadeonX4000_AMDNULLVMM14getVMPTBPerPTBEv 0000000000059c60 l 0e SECT 01 0000 [.text] __ZN25AMDRadeonX4000_AMDNULLVMM10getMinVMIDEv 0000000000059c68 l 0e SECT 01 0000 [.text] __ZN25AMDRadeonX4000_AMDNULLVMM10getMaxVMIDEv 0000000000059c70 l 0e SECT 01 0000 [.text] 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000000000005df90 l 0e SECT 01 0000 [.text] __GLOBAL__D_a 000000000005dfe2 l 0e SECT 01 0000 [.text] __ZN36AMDRadeonX4000_AMDPM4CommandsUtility9MetaClassD1Ev 000000000005e794 l 0e SECT 01 0000 [.text] __ZN36AMDRadeonX4000_AMDPM4CommandsUtility9MetaClassD0Ev 000000000005e7a0 l 0e SECT 01 0000 [.text] __GLOBAL__I_a 000000000005e7e0 l 0e SECT 01 0000 [.text] __GLOBAL__D_a 000000000005e832 l 0e SECT 01 0000 [.text] __ZN29AMDRadeonX4000_AMDPM4HWEngine9MetaClassD1Ev 000000000005eb3c l 0e SECT 01 0000 [.text] __ZN29AMDRadeonX4000_AMDPM4HWEngine9MetaClassD0Ev 000000000005eb46 l 0e SECT 01 0000 [.text] __ZN27AMDRadeonX4000_IAMDHWEngine4initEv 000000000005eb58 l 0e SECT 01 0000 [.text] __ZN26AMDRadeonX4000_AMDHWEngine4typeEv 000000000005eb62 l 0e SECT 01 0000 [.text] __ZN26AMDRadeonX4000_AMDHWEngine9isEnabledEv 000000000005eb6c l 0e SECT 01 0000 [.text] __ZN26AMDRadeonX4000_AMDHWEngine20setVirtualSpaceReadyEb 000000000005eb72 l 0e SECT 01 0000 [.text] __ZN29AMDRadeonX4000_AMDPM4HWEngine27setMemoryAllocationsEnabledEb 000000000005eb78 l 0e SECT 01 0000 [.text] __ZN29AMDRadeonX4000_AMDPM4HWEngine19initializeRegistersEv 000000000005eba8 l 0e SECT 01 0000 [.text] __ZN29AMDRadeonX4000_AMDPM4HWEngine25systemDidChangeSpeedEventEv 000000000005ebae l 0e SECT 01 0000 [.text] __ZN26AMDRadeonX4000_AMDHWEngine10getVersionEj 000000000005ebbe l 0e SECT 01 0000 [.text] __ZN26AMDRadeonX4000_AMDHWEngine15getChannelCountEv 000000000005ebc8 l 0e SECT 01 0000 [.text] __ZN26AMDRadeonX4000_AMDHWEngine22getTimestampIRQSourcexE18_eAMD_HW_RING_TYPE 000000000005ebd0 l 0e SECT 01 0000 [.text] __ZN26AMDRadeonX4000_AMDHWEngine14getFwvFunctionEv 000000000005ebe0 l 0e SECT 01 0000 [.text] __GLOBAL__I_a 000000000005ec20 l 0e SECT 01 0000 [.text] __GLOBAL__D_a 000000000005ec72 l 0e SECT 01 0000 [.text] __ZN30AMDRadeonX4000_AMDPM4HWChannel9MetaClassD1Ev 000000000005eef6 l 0e SECT 01 0000 [.text] __ZN30AMDRadeonX4000_AMDPM4HWChannel9MetaClassD0Ev 000000000005ef00 l 0e SECT 01 0000 [.text] __ZN28AMDRadeonX4000_IAMDHWChannel4initEv 000000000005ef12 l 0e SECT 01 0000 [.text] __ZN27AMDRadeonX4000_AMDHWChannel15getChannelIndexEv 000000000005ef1c l 0e SECT 01 0000 [.text] __ZN27AMDRadeonX4000_AMDHWChannel18getChannelRingTypeEv 000000000005ef38 l 0e SECT 01 0000 [.text] __ZN27AMDRadeonX4000_AMDHWChannel33initializeSubmitCommandBufferInfoEP30AMD_SUBMIT_COMMAND_BUFFER_INFO 000000000005ef4e l 0e SECT 01 0000 [.text] __ZN27AMDRadeonX4000_AMDHWChannel25alignCommandBufferAddressEj 000000000005ef64 l 0e SECT 01 0000 [.text] __ZN27AMDRadeonX4000_AMDHWChannel7getNameEv 000000000005ef6e l 0e SECT 01 0000 [.text] __ZN27AMDRadeonX4000_AMDHWChannel19dumpEngineHangStateEb 000000000005ef88 l 0e SECT 01 0000 [.text] __ZN27AMDRadeonX4000_AMDHWChannel21writeProfilingCommandEPjyjb 000000000005ef90 l 0e SECT 01 0000 [.text] __ZN27AMDRadeonX4000_AMDHWChannel10engineTypeEv 000000000005efa2 l 0e SECT 01 0000 [.text] __ZN27AMDRadeonX4000_AMDHWChannel18isDebugFlagEnabledEj 000000000005efb6 l 0e SECT 01 0000 [.text] __ZN27AMDRadeonX4000_AMDHWChannel24getTimestampInterruptRefEv 000000000005efc0 l 0e SECT 01 0000 [.text] __ZN27AMDRadeonX4000_AMDHWChannel25getHWStatisticsGroupTableEv 000000000005efce l 0e SECT 01 0000 [.text] __ZN27AMDRadeonX4000_AMDHWChannel23clearInterrupEnableFlagEv 000000000005efd8 l 0e SECT 01 0000 [.text] __ZN27AMDRadeonX4000_AMDHWChannel22getIndirectCommandSizeEv 000000000005efe4 l 0e SECT 01 0000 [.text] __ZN30AMDRadeonX4000_AMDPM4HWChannel30enableScratchRegisterWritebackEv 000000000005efea l 0e SECT 01 0000 [.text] __ZN30AMDRadeonX4000_AMDPM4HWChannel31disableScratchRegisterWritebackEv 000000000005eff0 l 0e SECT 01 0000 [.text] __GLOBAL__I_a 000000000005f030 l 0e SECT 01 0000 [.text] __GLOBAL__D_a 000000000005f082 l 0e SECT 01 0000 [.text] __ZN29AMDRadeonX4000_AMDSPUHWEngine9MetaClassD1Ev 000000000005fa7c l 0e SECT 01 0000 [.text] __ZN29AMDRadeonX4000_AMDSPUHWEngine9MetaClassD0Ev 000000000005fa86 l 0e SECT 01 0000 [.text] __ZN27AMDRadeonX4000_IAMDHWEngine4initEv 000000000005fa98 l 0e SECT 01 0000 [.text] __ZN26AMDRadeonX4000_AMDHWEngine4typeEv 000000000005faa2 l 0e SECT 01 0000 [.text] __ZN26AMDRadeonX4000_AMDHWEngine9isEnabledEv 000000000005faac l 0e SECT 01 0000 [.text] __ZN26AMDRadeonX4000_AMDHWEngine20setVirtualSpaceReadyEb 000000000005fab2 l 0e SECT 01 0000 [.text] __ZN29AMDRadeonX4000_AMDSPUHWEngine19initializeRegistersEv 000000000005fab8 l 0e SECT 01 0000 [.text] __ZN29AMDRadeonX4000_AMDSPUHWEngine26systemWillChangeSpeedEventEv 000000000005fabe l 0e SECT 01 0000 [.text] __ZN29AMDRadeonX4000_AMDSPUHWEngine25systemDidChangeSpeedEventEv 000000000005fac4 l 0e SECT 01 0000 [.text] __ZN29AMDRadeonX4000_AMDSPUHWEngine25alignCommandBufferAddressEj 000000000005fad6 l 0e SECT 01 0000 [.text] __ZN26AMDRadeonX4000_AMDHWEngine10getVersionEj 000000000005fae6 l 0e SECT 01 0000 [.text] __ZN26AMDRadeonX4000_AMDHWEngine15getChannelCountEv 000000000005faf0 l 0e SECT 01 0000 [.text] __ZN26AMDRadeonX4000_AMDHWEngine22getTimestampIRQSourcexE18_eAMD_HW_RING_TYPE 000000000005faf8 l 0e SECT 01 0000 [.text] __ZN26AMDRadeonX4000_AMDHWEngine14getFwvFunctionEv 000000000005fb00 l 0e SECT 01 0000 [.text] __GLOBAL__I_a 000000000005fb40 l 0e SECT 01 0000 [.text] __GLOBAL__D_a 000000000005fb92 l 0e SECT 01 0000 [.text] __ZN30AMDRadeonX4000_AMDSPUHWChannel9MetaClassD1Ev 000000000005fc9c l 0e SECT 01 0000 [.text] __ZN30AMDRadeonX4000_AMDSPUHWChannel9MetaClassD0Ev 000000000005fca6 l 0e SECT 01 0000 [.text] __ZN28AMDRadeonX4000_IAMDHWChannel4initEv 000000000005fcb8 l 0e SECT 01 0000 [.text] __ZN27AMDRadeonX4000_AMDHWChannel15getChannelIndexEv 000000000005fcc2 l 0e SECT 01 0000 [.text] __ZN27AMDRadeonX4000_AMDHWChannel18getChannelRingTypeEv 000000000005fcde l 0e SECT 01 0000 [.text] __ZN27AMDRadeonX4000_AMDHWChannel33initializeSubmitCommandBufferInfoEP30AMD_SUBMIT_COMMAND_BUFFER_INFO 000000000005fcf4 l 0e SECT 01 0000 [.text] __ZN27AMDRadeonX4000_AMDHWChannel25alignCommandBufferAddressEj 000000000005fd0a l 0e SECT 01 0000 [.text] __ZN30AMDRadeonX4000_AMDSPUHWChannel20getIBAlignmentFactorEv 000000000005fd16 l 0e SECT 01 0000 [.text] __ZN30AMDRadeonX4000_AMDSPUHWChannel21getOneDwordNOPCommandEv 000000000005fd22 l 0e SECT 01 0000 [.text] __ZNK27AMDRadeonX4000_AMDHWChannel21writeSemaphoreCommandEPjyb 000000000005fd2a l 0e SECT 01 0000 [.text] __ZN27AMDRadeonX4000_AMDHWChannel7getNameEv 000000000005fd34 l 0e SECT 01 0000 [.text] __ZN27AMDRadeonX4000_AMDHWChannel19dumpEngineHangStateEb 000000000005fd4e l 0e SECT 01 0000 [.text] __ZN27AMDRadeonX4000_AMDHWChannel21writeProfilingCommandEPjyjb 000000000005fd56 l 0e SECT 01 0000 [.text] __ZN27AMDRadeonX4000_AMDHWChannel10engineTypeEv 000000000005fd68 l 0e SECT 01 0000 [.text] __ZN27AMDRadeonX4000_AMDHWChannel18isDebugFlagEnabledEj 000000000005fd7c l 0e SECT 01 0000 [.text] __ZN27AMDRadeonX4000_AMDHWChannel24getTimestampInterruptRefEv 000000000005fd86 l 0e SECT 01 0000 [.text] __ZN27AMDRadeonX4000_AMDHWChannel25getHWStatisticsGroupTableEv 000000000005fd94 l 0e SECT 01 0000 [.text] __ZN27AMDRadeonX4000_AMDHWChannel23clearInterrupEnableFlagEv 000000000005fd9e l 0e SECT 01 0000 [.text] __ZN30AMDRadeonX4000_AMDSPUHWChannel22getIndirectCommandSizeEv 000000000005fdb0 l 0e SECT 01 0000 [.text] __GLOBAL__I_a 000000000005fdf0 l 0e SECT 01 0000 [.text] __GLOBAL__D_a 000000000005fe42 l 0e SECT 01 0000 [.text] __ZN29AMDRadeonX4000_AMDVCEHWEngine9MetaClassD1Ev 0000000000060c32 l 0e SECT 01 0000 [.text] __ZN29AMDRadeonX4000_AMDVCEHWEngine9MetaClassD0Ev 0000000000060c3c l 0e SECT 01 0000 [.text] __ZN27AMDRadeonX4000_IAMDHWEngine4initEv 0000000000060c4e l 0e SECT 01 0000 [.text] __ZN26AMDRadeonX4000_AMDHWEngine4typeEv 0000000000060c58 l 0e SECT 01 0000 [.text] __ZN26AMDRadeonX4000_AMDHWEngine9isEnabledEv 0000000000060c62 l 0e SECT 01 0000 [.text] __ZN26AMDRadeonX4000_AMDHWEngine20setVirtualSpaceReadyEb 0000000000060c68 l 0e SECT 01 0000 [.text] __ZN29AMDRadeonX4000_AMDVCEHWEngine19initializeRegistersEv 0000000000060c6e l 0e SECT 01 0000 [.text] __ZN29AMDRadeonX4000_AMDVCEHWEngine26systemWillChangeSpeedEventEv 0000000000060c74 l 0e SECT 01 0000 [.text] __ZN29AMDRadeonX4000_AMDVCEHWEngine25systemDidChangeSpeedEventEv 0000000000060c7a l 0e SECT 01 0000 [.text] __ZN29AMDRadeonX4000_AMDVCEHWEngine25alignCommandBufferAddressEj 0000000000060c86 l 0e SECT 01 0000 [.text] __ZN26AMDRadeonX4000_AMDHWEngine10getVersionEj 0000000000060c96 l 0e SECT 01 0000 [.text] __ZN26AMDRadeonX4000_AMDHWEngine15getChannelCountEv 0000000000060ca0 l 0e SECT 01 0000 [.text] __ZN26AMDRadeonX4000_AMDHWEngine22getTimestampIRQSourcexE18_eAMD_HW_RING_TYPE 0000000000060ca8 l 0e SECT 01 0000 [.text] __ZN26AMDRadeonX4000_AMDHWEngine14getFwvFunctionEv 0000000000060cb0 l 0e SECT 01 0000 [.text] __ZN29AMDRadeonX4000_AMDVCEHWEngine19dumpEngineHangStateEb 0000000000060cb6 l 0e SECT 01 0000 [.text] __ZN29AMDRadeonX4000_AMDVCEHWEngine18getTotalCapabilityEv 0000000000060cca l 0e SECT 01 0000 [.text] __ZN29AMDRadeonX4000_AMDVCEHWEngine20getCurrentCapabilityEv 0000000000060cde l 0e SECT 01 0000 [.text] __ZN29AMDRadeonX4000_AMDVCEHWEngine10getVCEVClkEv 0000000000060cea l 0e SECT 01 0000 [.text] __ZN29AMDRadeonX4000_AMDVCEHWEngine10getVCECClkEv 0000000000060d00 l 0e SECT 01 0000 [.text] __GLOBAL__I_a 0000000000060d40 l 0e SECT 01 0000 [.text] __GLOBAL__D_a 0000000000060d92 l 0e SECT 01 0000 [.text] __ZN30AMDRadeonX4000_AMDVCEHWChannel9MetaClassD1Ev 0000000000060efe l 0e SECT 01 0000 [.text] __ZN30AMDRadeonX4000_AMDVCEHWChannel9MetaClassD0Ev 0000000000060f08 l 0e SECT 01 0000 [.text] __ZN28AMDRadeonX4000_IAMDHWChannel4initEv 0000000000060f1a l 0e SECT 01 0000 [.text] __ZN27AMDRadeonX4000_AMDHWChannel15getChannelIndexEv 0000000000060f24 l 0e SECT 01 0000 [.text] __ZN27AMDRadeonX4000_AMDHWChannel18getChannelRingTypeEv 0000000000060f40 l 0e SECT 01 0000 [.text] __ZN27AMDRadeonX4000_AMDHWChannel33initializeSubmitCommandBufferInfoEP30AMD_SUBMIT_COMMAND_BUFFER_INFO 0000000000060f56 l 0e SECT 01 0000 [.text] __ZN27AMDRadeonX4000_AMDHWChannel25alignCommandBufferAddressEj 0000000000060f6c l 0e SECT 01 0000 [.text] __ZN30AMDRadeonX4000_AMDVCEHWChannel20getIBAlignmentFactorEv 0000000000060f78 l 0e SECT 01 0000 [.text] __ZN30AMDRadeonX4000_AMDVCEHWChannel21getOneDwordNOPCommandEv 0000000000060f80 l 0e SECT 01 0000 [.text] __ZNK27AMDRadeonX4000_AMDHWChannel21writeSemaphoreCommandEPjyb 0000000000060f88 l 0e SECT 01 0000 [.text] __ZN27AMDRadeonX4000_AMDHWChannel7getNameEv 0000000000060f92 l 0e SECT 01 0000 [.text] __ZN27AMDRadeonX4000_AMDHWChannel19dumpEngineHangStateEb 0000000000060fac l 0e SECT 01 0000 [.text] __ZN27AMDRadeonX4000_AMDHWChannel21writeProfilingCommandEPjyjb 0000000000060fb4 l 0e SECT 01 0000 [.text] __ZN27AMDRadeonX4000_AMDHWChannel10engineTypeEv 0000000000060fc6 l 0e SECT 01 0000 [.text] __ZN27AMDRadeonX4000_AMDHWChannel18isDebugFlagEnabledEj 0000000000060fda l 0e SECT 01 0000 [.text] __ZN27AMDRadeonX4000_AMDHWChannel24getTimestampInterruptRefEv 0000000000060fe4 l 0e SECT 01 0000 [.text] __ZN27AMDRadeonX4000_AMDHWChannel25getHWStatisticsGroupTableEv 0000000000060ff2 l 0e SECT 01 0000 [.text] __ZN27AMDRadeonX4000_AMDHWChannel23clearInterrupEnableFlagEv 0000000000060ffc l 0e SECT 01 0000 [.text] __ZN27AMDRadeonX4000_AMDHWChannel22getIndirectCommandSizeEv 0000000000061010 l 0e SECT 01 0000 [.text] __GLOBAL__I_a 0000000000061050 l 0e SECT 01 0000 [.text] __GLOBAL__D_a 00000000000610a2 l 0e SECT 01 0000 [.text] __ZN29AMDRadeonX4000_AMDUVDHWEngine9MetaClassD1Ev 00000000000629f0 l 0e SECT 01 0000 [.text] __ZN29AMDRadeonX4000_AMDUVDHWEngine9MetaClassD0Ev 00000000000629fa l 0e SECT 01 0000 [.text] __ZN27AMDRadeonX4000_IAMDHWEngine4initEv 0000000000062a0c l 0e SECT 01 0000 [.text] __ZN26AMDRadeonX4000_AMDHWEngine4typeEv 0000000000062a16 l 0e SECT 01 0000 [.text] __ZN29AMDRadeonX4000_AMDUVDHWEngine19initializeRegistersEv 0000000000062a1c l 0e SECT 01 0000 [.text] __ZN29AMDRadeonX4000_AMDUVDHWEngine26systemWillChangeSpeedEventEv 0000000000062a22 l 0e SECT 01 0000 [.text] __ZN29AMDRadeonX4000_AMDUVDHWEngine25systemDidChangeSpeedEventEv 0000000000062a28 l 0e SECT 01 0000 [.text] __ZN26AMDRadeonX4000_AMDHWEngine10getVersionEj 0000000000062a38 l 0e SECT 01 0000 [.text] __ZN26AMDRadeonX4000_AMDHWEngine15getChannelCountEv 0000000000062a42 l 0e SECT 01 0000 [.text] __ZN26AMDRadeonX4000_AMDHWEngine22getTimestampIRQSourcexE18_eAMD_HW_RING_TYPE 0000000000062a4a l 0e SECT 01 0000 [.text] __ZN26AMDRadeonX4000_AMDHWEngine14getFwvFunctionEv 0000000000062a52 l 0e SECT 01 0000 [.text] __ZN29AMDRadeonX4000_AMDUVDHWEngine18getFirmwareAddressEv 0000000000062a60 l 0e SECT 01 0000 [.text] __ZN29AMDRadeonX4000_AMDUVDHWEngine18getTotalCapabilityEv 0000000000062a74 l 0e SECT 01 0000 [.text] __ZN29AMDRadeonX4000_AMDUVDHWEngine20getCurrentCapabilityEv 0000000000062a88 l 0e SECT 01 0000 [.text] __ZN29AMDRadeonX4000_AMDUVDHWEngine10getUVDVclkEv 0000000000062a94 l 0e SECT 01 0000 [.text] __ZN29AMDRadeonX4000_AMDUVDHWEngine10getUVDDclkEv 0000000000062aa0 l 0e SECT 01 0000 [.text] __ZN29AMDRadeonX4000_AMDUVDHWEngine14getHWRegistersEv 0000000000062aaa l 0e SECT 01 0000 [.text] __ZN29AMDRadeonX4000_AMDUVDHWEngine12getKeySelectEv 0000000000062ab6 l 0e SECT 01 0000 [.text] __ZN29AMDRadeonX4000_AMDUVDHWEngine15setDpmSupportedEb 0000000000062ac4 l 0e SECT 01 0000 [.text] __ZN29AMDRadeonX4000_AMDUVDHWEngine14commitUVDFWMsgEP12_SML_UVD_MSGyy 0000000000062ad0 l 0e SECT 01 0000 [.text] __GLOBAL__I_a 0000000000062b10 l 0e SECT 01 0000 [.text] __GLOBAL__D_a 0000000000062b62 l 0e SECT 01 0000 [.text] __ZN13AMDSIHWMemory9MetaClassD1Ev 00000000000631de l 0e SECT 01 0000 [.text] __ZN13AMDSIHWMemory9MetaClassD0Ev 00000000000631e8 l 0e SECT 01 0000 [.text] __ZN27AMDRadeonX4000_IAMDHWMemory4initEv 00000000000631fa l 0e SECT 01 0000 [.text] __ZN26AMDRadeonX4000_AMDHWMemory19getMemoryDescriptorEv 0000000000063208 l 0e SECT 01 0000 [.text] __ZN26AMDRadeonX4000_AMDHWMemory8isMappedEv 0000000000063214 l 0e SECT 01 0000 [.text] __ZN26AMDRadeonX4000_AMDHWMemory20setReservedNdrvSpaceEy 000000000006321e l 0e SECT 01 0000 [.text] __ZN26AMDRadeonX4000_AMDHWMemory12getTotalSizeEv 0000000000063228 l 0e SECT 01 0000 [.text] __ZN26AMDRadeonX4000_AMDHWMemory14getVisibleSizeEv 0000000000063232 l 0e SECT 01 0000 [.text] __ZN26AMDRadeonX4000_AMDHWMemory16getInvisibleSizeEv 0000000000063240 l 0e SECT 01 0000 [.text] __ZN26AMDRadeonX4000_AMDHWMemory24isNonVisibleMemoryExistsEv 0000000000063260 l 0e SECT 01 0000 [.text] __GLOBAL__I_a 00000000000632a0 l 0e SECT 01 0000 [.text] __GLOBAL__D_a 00000000000632f2 l 0e SECT 01 0000 [.text] __ZN12AMDSIDisplay9MetaClassD1Ev 0000000000064a8e l 0e SECT 01 0000 [.text] __ZN12AMDSIDisplay9MetaClassD0Ev 0000000000064a98 l 0e SECT 01 0000 [.text] __ZN27AMDRadeonX4000_AMDHWDisplay10getBuiltInEj 0000000000064ab4 l 0e SECT 01 0000 [.text] __ZN27AMDRadeonX4000_AMDHWDisplay16getBuiltInExistsEv 0000000000064ac2 l 0e SECT 01 0000 [.text] __ZN27AMDRadeonX4000_AMDHWDisplay13getInterlacedEj 0000000000064adc l 0e SECT 01 0000 [.text] __ZN27AMDRadeonX4000_AMDHWDisplay20setFullScreenEnabledEjb 0000000000064b00 l 0e SECT 01 0000 [.text] __ZN27AMDRadeonX4000_AMDHWDisplay20getFullScreenEnabledEj 0000000000064b1c l 0e SECT 01 0000 [.text] __ZN12AMDSIDisplay28getNumberOfSupportedDisplaysEv 0000000000064b28 l 0e SECT 01 0000 [.text] __ZN27AMDRadeonX4000_AMDHWDisplay13isFEDSEnabledEv 0000000000064b36 l 0e SECT 01 0000 [.text] __ZN27AMDRadeonX4000_AMDHWDisplay13isFEDSEnabledEj 0000000000064b52 l 0e SECT 01 0000 [.text] __ZN27AMDRadeonX4000_AMDHWDisplay17FEDSIsColorBufferEj 0000000000064b6a l 0e SECT 01 0000 [.text] __ZN27AMDRadeonX4000_AMDHWDisplay20FEDSSetIsColorBufferEjj 0000000000064b82 l 0e SECT 01 0000 [.text] __ZN27AMDRadeonX4000_AMDHWDisplay27isAnyDisplayModeAccelBackedEv 0000000000064b8e l 0e SECT 01 0000 [.text] __ZN27AMDRadeonX4000_AMDHWDisplay24isDisplayModeAccelBackedEj 0000000000064ba8 l 0e SECT 01 0000 [.text] __ZN27AMDRadeonX4000_AMDHWDisplay14getScalerFlagsEj 0000000000064bca l 0e SECT 01 0000 [.text] __ZN27AMDRadeonX4000_AMDHWDisplay14isScaledNeededEv 0000000000064c12 l 0e SECT 01 0000 [.text] __ZN27AMDRadeonX4000_AMDHWDisplay14isScaledNeededEj 0000000000064c32 l 0e SECT 01 0000 [.text] __ZN27AMDRadeonX4000_AMDHWDisplay14isFedsRequiredEv 0000000000064c7a l 0e SECT 01 0000 [.text] __ZN27AMDRadeonX4000_AMDHWDisplay14isFedsRequiredEj 0000000000064cb0 l 0e SECT 01 0000 [.text] __ZNK27AMDRadeonX4000_AMDHWDisplay16getFedsParamInfoEv 0000000000064cba l 0e SECT 01 0000 [.text] __ZN27AMDRadeonX4000_AMDHWDisplay17isFEDSBufferDirtyEj 0000000000064cd4 l 0e SECT 01 0000 [.text] __ZN12AMDSIDisplay27writeTilingControlRegistersEjPjj 0000000000064ce0 l 0e SECT 01 0000 [.text] __GLOBAL__I_a 0000000000064d20 l 0e SECT 01 0000 [.text] __GLOBAL__D_a 0000000000064d72 l 0e SECT 01 0000 [.text] __ZN16AMDSIHWUtilities9MetaClassD1Ev 0000000000065076 l 0e SECT 01 0000 [.text] __ZN16AMDSIHWUtilities9MetaClassD0Ev 0000000000065080 l 0e SECT 01 0000 [.text] __ZN30AMDRadeonX4000_IAMDHWUtilities4initEv 00000000000650a0 l 0e SECT 01 0000 [.text] __GLOBAL__I_a 00000000000650e0 l 0e SECT 01 0000 [.text] __GLOBAL__D_a 0000000000065132 l 0e SECT 01 0000 [.text] __ZN14AMDSIVMContext9MetaClassD1Ev 000000000006648e l 0e SECT 01 0000 [.text] __ZN14AMDSIVMContext9MetaClassD0Ev 0000000000066498 l 0e SECT 01 0000 [.text] __ZN30AMDRadeonX4000_IAMDHWVMContext4initEv 00000000000664aa l 0e SECT 01 0000 [.text] __ZN29AMDRadeonX4000_AMDHWVMContext10mapLocalVAEyyy 00000000000664d0 l 0e SECT 01 0000 [.text] __ZN29AMDRadeonX4000_AMDHWVMContext11mapSystemVAEyP18IOMemoryDescriptor 00000000000664fa l 0e SECT 01 0000 [.text] __ZN29AMDRadeonX4000_AMDHWVMContext11mapSystemVAEyyy 0000000000066522 l 0e SECT 01 0000 [.text] __ZN29AMDRadeonX4000_AMDHWVMContext14getCurrentVMIDEv 000000000006653e l 0e SECT 01 0000 [.text] __ZN29AMDRadeonX4000_AMDHWVMContext16getPDBaseAddressEv 000000000006654c l 0e SECT 01 0000 [.text] __ZN29AMDRadeonX4000_AMDHWVMContext18isPageTableUpdatedEv 0000000000066558 l 0e SECT 01 0000 [.text] __ZN29AMDRadeonX4000_AMDHWVMContext21clearPageTableUpdatedEv 0000000000066570 l 0e SECT 01 0000 [.text] __GLOBAL__I_a 00000000000665b0 l 0e SECT 01 0000 [.text] __GLOBAL__D_a 0000000000066602 l 0e SECT 01 0000 [.text] __ZN8AMDSIVMM9MetaClassD1Ev 00000000000669a0 l 0e SECT 01 0000 [.text] __ZN8AMDSIVMM9MetaClassD0Ev 00000000000669aa l 0e SECT 01 0000 [.text] __ZN24AMDRadeonX4000_IAMDHWVMM4initEv 00000000000669bc l 0e SECT 01 0000 [.text] __ZN23AMDRadeonX4000_AMDHWVMM14getBaseAddressEv 00000000000669c6 l 0e SECT 01 0000 [.text] __ZN23AMDRadeonX4000_AMDHWVMM21getVMPTVirtualAddressEv 00000000000669d0 l 0e SECT 01 0000 [.text] __ZN23AMDRadeonX4000_AMDHWVMM21getVMPTVirtualAddressEy 0000000000066a08 l 0e SECT 01 0000 [.text] __ZN23AMDRadeonX4000_AMDHWVMM15getVMRangeStartEv 0000000000066a12 l 0e SECT 01 0000 [.text] __ZN23AMDRadeonX4000_AMDHWVMM13getVMRangeEndEv 0000000000066a20 l 0e SECT 01 0000 [.text] __ZN23AMDRadeonX4000_AMDHWVMM16getVMPTBCoverageEv 0000000000066a2e l 0e SECT 01 0000 [.text] __ZN23AMDRadeonX4000_AMDHWVMM16getVMPTBVRAMSizeEv 0000000000066a3c l 0e SECT 01 0000 [.text] __ZN23AMDRadeonX4000_AMDHWVMM16getVMPTDVRAMSizeEv 0000000000066a4a l 0e SECT 01 0000 [.text] __ZN23AMDRadeonX4000_AMDHWVMM13getVMPTBTotalEv 0000000000066a58 l 0e SECT 01 0000 [.text] __ZN23AMDRadeonX4000_AMDHWVMM14getVMPTBPerPTBEv 0000000000066a66 l 0e SECT 01 0000 [.text] __ZN8AMDSIVMM10getMinVMIDEv 0000000000066a72 l 0e SECT 01 0000 [.text] __ZN8AMDSIVMM10getMaxVMIDEv 0000000000066a7e l 0e SECT 01 0000 [.text] __ZN23AMDRadeonX4000_AMDHWVMM19getFragmentStrategyEv 0000000000066a8a l 0e SECT 01 0000 [.text] __ZN23AMDRadeonX4000_AMDHWVMM12getBIGKValueEv 0000000000066a96 l 0e SECT 01 0000 [.text] __ZN23AMDRadeonX4000_AMDHWVMM14getBIGKInBytesEv 0000000000066aa2 l 0e SECT 01 0000 [.text] __ZN23AMDRadeonX4000_AMDHWVMM20getFragmentAlignmentEv 0000000000066ab0 l 0e SECT 01 0000 [.text] __GLOBAL__I_a 0000000000066af0 l 0e SECT 01 0000 [.text] __GLOBAL__D_a 0000000000066b42 l 0e SECT 01 0000 [.text] __ZN13AMDSIHardware9MetaClassD1Ev 00000000000698d8 l 0e SECT 01 0000 [.text] __ZN13AMDSIHardware9MetaClassD0Ev 00000000000698e2 l 0e SECT 01 0000 [.text] __ZN30AMDRadeonX4000_IAMDHWInterface4initEv 00000000000698f4 l 0e SECT 01 0000 [.text] __ZN26AMDRadeonX4000_AMDHardware21getHWMemoryDescriptorEv 0000000000069902 l 0e SECT 01 0000 [.text] __ZN26AMDRadeonX4000_AMDHardware13getChipEngineEv 000000000006990e l 0e SECT 01 0000 [.text] __ZN26AMDRadeonX4000_AMDHardware13getConfigBitsEv 000000000006991a l 0e SECT 01 0000 [.text] __ZN26AMDRadeonX4000_AMDHardware17getHWCapabilitiesEv 0000000000069924 l 0e SECT 01 0000 [.text] __ZN26AMDRadeonX4000_AMDHardware23getAMDHwCailAdapterInfoEv 0000000000069932 l 0e SECT 01 0000 [.text] __ZN26AMDRadeonX4000_AMDHardware15getMaskSettingsEv 0000000000069940 l 0e SECT 01 0000 [.text] __ZN26AMDRadeonX4000_AMDHardware9getChipIDEv 000000000006994c l 0e SECT 01 0000 [.text] __ZN26AMDRadeonX4000_AMDHardware10getChipRevEv 0000000000069958 l 0e SECT 01 0000 [.text] __ZN26AMDRadeonX4000_AMDHardware14getSubSystemIDEv 0000000000069964 l 0e SECT 01 0000 [.text] __ZN26AMDRadeonX4000_AMDHardware9getFamilyEv 0000000000069970 l 0e SECT 01 0000 [.text] __ZN26AMDRadeonX4000_AMDHardware34getPreDefinedNdrvVramReservedSpaceEv 000000000006997c l 0e SECT 01 0000 [.text] __ZN26AMDRadeonX4000_AMDHardware22setTLBInvalidateNeededEj 0000000000069992 l 0e SECT 01 0000 [.text] __ZN26AMDRadeonX4000_AMDHardware19getDiagReportBufferEv 00000000000699ae l 0e SECT 01 0000 [.text] __ZN26AMDRadeonX4000_AMDHardware23getDiagReportBufferSizeEv 00000000000699ba l 0e SECT 01 0000 [.text] __ZN26AMDRadeonX4000_AMDHardware9isEnabledEv 00000000000699c6 l 0e SECT 01 0000 [.text] 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000000000006b032 l 0e SECT 01 0000 [.text] __ZN32AMDRadeonX4000_AMDHWAlignManager15getAddrTileModeEj 000000000006b03a l 0e SECT 01 0000 [.text] __ZN32AMDRadeonX4000_AMDHWAlignManager12getArrayModeE13_AddrTileMode 000000000006b042 l 0e SECT 01 0000 [.text] __ZN32AMDRadeonX4000_AMDHWAlignManager11getTileTypeEj 000000000006b04a l 0e SECT 01 0000 [.text] __ZN32AMDRadeonX4000_AMDHWAlignManager16getMicroTileModeE13_AddrTileType 000000000006b052 l 0e SECT 01 0000 [.text] __ZN32AMDRadeonX4000_AMDHWAlignManager25getLinearAlignedTileIndexEv 000000000006b05c l 0e SECT 01 0000 [.text] __ZN32AMDRadeonX4000_AMDHWAlignManager25getLinearGeneralTileIndexEv 000000000006b070 l 0e SECT 01 0000 [.text] __GLOBAL__I_a 000000000006b0b0 l 0e SECT 01 0000 [.text] __GLOBAL__D_a 000000000006b102 l 0e SECT 01 0000 [.text] __ZN14AMDSIPM4Engine9MetaClassD1Ev 000000000006b9a8 l 0e SECT 01 0000 [.text] __ZN14AMDSIPM4Engine9MetaClassD0Ev 000000000006b9b2 l 0e SECT 01 0000 [.text] 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__ZN29AMDRadeonX4000_AMDPM4HWEngine27setMemoryAllocationsEnabledEb 000000000006bd48 l 0e SECT 01 0000 [.text] __ZN29AMDRadeonX4000_AMDPM4HWEngine19initializeRegistersEv 000000000006bd78 l 0e SECT 01 0000 [.text] __ZN29AMDRadeonX4000_AMDPM4HWEngine25systemDidChangeSpeedEventEv 000000000006bd7e l 0e SECT 01 0000 [.text] __ZN14AMDSIPM4Engine25alignCommandBufferAddressEj 000000000006bd86 l 0e SECT 01 0000 [.text] __ZN26AMDRadeonX4000_AMDHWEngine10getVersionEj 000000000006bd96 l 0e SECT 01 0000 [.text] __ZN26AMDRadeonX4000_AMDHWEngine15getChannelCountEv 000000000006bda0 l 0e SECT 01 0000 [.text] __ZN26AMDRadeonX4000_AMDHWEngine22getTimestampIRQSourcexE18_eAMD_HW_RING_TYPE 000000000006bda8 l 0e SECT 01 0000 [.text] __ZN26AMDRadeonX4000_AMDHWEngine14getFwvFunctionEv 000000000006bdb0 l 0e SECT 01 0000 [.text] __ZN14AMDSIPM4Engine19dumpEngineHangStateEb 000000000006bdd0 l 0e SECT 01 0000 [.text] __GLOBAL__I_a 000000000006be10 l 0e SECT 01 0000 [.text] __GLOBAL__D_a 000000000006be62 l 0e SECT 01 0000 [.text] __ZN20AMDPitcairnPM4Engine9MetaClassD1Ev 000000000006c06c l 0e SECT 01 0000 [.text] __ZN20AMDPitcairnPM4Engine9MetaClassD0Ev 000000000006c076 l 0e SECT 01 0000 [.text] __ZN27AMDRadeonX4000_IAMDHWEngine4initEv 000000000006c088 l 0e SECT 01 0000 [.text] __ZN26AMDRadeonX4000_AMDHWEngine4typeEv 000000000006c092 l 0e SECT 01 0000 [.text] __ZN26AMDRadeonX4000_AMDHWEngine9isEnabledEv 000000000006c09c l 0e SECT 01 0000 [.text] __ZN26AMDRadeonX4000_AMDHWEngine20setVirtualSpaceReadyEb 000000000006c0a2 l 0e SECT 01 0000 [.text] __ZN29AMDRadeonX4000_AMDPM4HWEngine27setMemoryAllocationsEnabledEb 000000000006c0a8 l 0e SECT 01 0000 [.text] __ZN29AMDRadeonX4000_AMDPM4HWEngine19initializeRegistersEv 000000000006c0d8 l 0e SECT 01 0000 [.text] __ZN29AMDRadeonX4000_AMDPM4HWEngine25systemDidChangeSpeedEventEv 000000000006c0de l 0e SECT 01 0000 [.text] __ZN14AMDSIPM4Engine25alignCommandBufferAddressEj 000000000006c0e6 l 0e SECT 01 0000 [.text] __ZN26AMDRadeonX4000_AMDHWEngine10getVersionEj 000000000006c0f6 l 0e SECT 01 0000 [.text] __ZN26AMDRadeonX4000_AMDHWEngine15getChannelCountEv 000000000006c100 l 0e SECT 01 0000 [.text] __ZN26AMDRadeonX4000_AMDHWEngine22getTimestampIRQSourcexE18_eAMD_HW_RING_TYPE 000000000006c108 l 0e SECT 01 0000 [.text] __ZN26AMDRadeonX4000_AMDHWEngine14getFwvFunctionEv 000000000006c110 l 0e SECT 01 0000 [.text] __ZN14AMDSIPM4Engine19dumpEngineHangStateEb 000000000006c130 l 0e SECT 01 0000 [.text] __GLOBAL__I_a 000000000006c170 l 0e SECT 01 0000 [.text] __GLOBAL__D_a 000000000006c1c2 l 0e SECT 01 0000 [.text] __ZN17AMDVerdePM4Engine9MetaClassD1Ev 000000000006c3cc l 0e SECT 01 0000 [.text] __ZN17AMDVerdePM4Engine9MetaClassD0Ev 000000000006c3d6 l 0e SECT 01 0000 [.text] __ZN27AMDRadeonX4000_IAMDHWEngine4initEv 000000000006c3e8 l 0e SECT 01 0000 [.text] __ZN26AMDRadeonX4000_AMDHWEngine4typeEv 000000000006c3f2 l 0e SECT 01 0000 [.text] __ZN26AMDRadeonX4000_AMDHWEngine9isEnabledEv 000000000006c3fc l 0e SECT 01 0000 [.text] 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__GLOBAL__I_a 000000000006c4d0 l 0e SECT 01 0000 [.text] __GLOBAL__D_a 000000000006c522 l 0e SECT 01 0000 [.text] __ZN15AMDSIPM4Channel9MetaClassD1Ev 000000000006cdbe l 0e SECT 01 0000 [.text] __ZN15AMDSIPM4Channel9MetaClassD0Ev 000000000006cdc8 l 0e SECT 01 0000 [.text] __ZN28AMDRadeonX4000_IAMDHWChannel4initEv 000000000006cdda l 0e SECT 01 0000 [.text] __ZN27AMDRadeonX4000_AMDHWChannel15getChannelIndexEv 000000000006cde4 l 0e SECT 01 0000 [.text] __ZN27AMDRadeonX4000_AMDHWChannel18getChannelRingTypeEv 000000000006ce00 l 0e SECT 01 0000 [.text] __ZN27AMDRadeonX4000_AMDHWChannel33initializeSubmitCommandBufferInfoEP30AMD_SUBMIT_COMMAND_BUFFER_INFO 000000000006ce16 l 0e SECT 01 0000 [.text] __ZN27AMDRadeonX4000_AMDHWChannel25alignCommandBufferAddressEj 000000000006ce2c l 0e SECT 01 0000 [.text] __ZN27AMDRadeonX4000_AMDHWChannel7getNameEv 000000000006ce36 l 0e SECT 01 0000 [.text] __ZN27AMDRadeonX4000_AMDHWChannel19dumpEngineHangStateEb 000000000006ce50 l 0e SECT 01 0000 [.text] __ZN27AMDRadeonX4000_AMDHWChannel10engineTypeEv 000000000006ce62 l 0e SECT 01 0000 [.text] __ZN27AMDRadeonX4000_AMDHWChannel18isDebugFlagEnabledEj 000000000006ce76 l 0e SECT 01 0000 [.text] __ZN27AMDRadeonX4000_AMDHWChannel24getTimestampInterruptRefEv 000000000006ce80 l 0e SECT 01 0000 [.text] __ZN27AMDRadeonX4000_AMDHWChannel25getHWStatisticsGroupTableEv 000000000006ce8e l 0e SECT 01 0000 [.text] __ZN27AMDRadeonX4000_AMDHWChannel23clearInterrupEnableFlagEv 000000000006ce98 l 0e SECT 01 0000 [.text] __ZN27AMDRadeonX4000_AMDHWChannel22getIndirectCommandSizeEv 000000000006ceb0 l 0e SECT 01 0000 [.text] __GLOBAL__I_a 000000000006cef0 l 0e SECT 01 0000 [.text] __GLOBAL__D_a 000000000006cf42 l 0e SECT 01 0000 [.text] __ZN17AMDSICommandsRing9MetaClassD1Ev 000000000006d420 l 0e SECT 01 0000 [.text] __ZN17AMDSICommandsRing9MetaClassD0Ev 000000000006d42a l 0e SECT 01 0000 [.text] __ZN25AMDRadeonX4000_IAMDHWRing4initEv 000000000006d43c l 0e SECT 01 0000 [.text] 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000000000006d9ca l 0e SECT 01 0000 [.text] __ZN26AMDRadeonX4000_AMDHWEngine10getVersionEj 000000000006d9da l 0e SECT 01 0000 [.text] __ZN26AMDRadeonX4000_AMDHWEngine15getChannelCountEv 000000000006d9e4 l 0e SECT 01 0000 [.text] __ZN26AMDRadeonX4000_AMDHWEngine22getTimestampIRQSourcexE18_eAMD_HW_RING_TYPE 000000000006d9ec l 0e SECT 01 0000 [.text] __ZN26AMDRadeonX4000_AMDHWEngine14getFwvFunctionEv 000000000006da00 l 0e SECT 01 0000 [.text] __GLOBAL__I_a 000000000006da40 l 0e SECT 01 0000 [.text] __GLOBAL__D_a 000000000006da92 l 0e SECT 01 0000 [.text] __ZN15AMDSIDMAChannel9MetaClassD1Ev 000000000006e98a l 0e SECT 01 0000 [.text] __ZN15AMDSIDMAChannel9MetaClassD0Ev 000000000006e994 l 0e SECT 01 0000 [.text] __ZN28AMDRadeonX4000_IAMDHWChannel4initEv 000000000006e9a6 l 0e SECT 01 0000 [.text] __ZN27AMDRadeonX4000_AMDHWChannel15getChannelIndexEv 000000000006e9b0 l 0e SECT 01 0000 [.text] __ZN27AMDRadeonX4000_AMDHWChannel18getChannelRingTypeEv 000000000006e9cc l 0e SECT 01 0000 [.text] __ZN27AMDRadeonX4000_AMDHWChannel33initializeSubmitCommandBufferInfoEP30AMD_SUBMIT_COMMAND_BUFFER_INFO 000000000006e9e2 l 0e SECT 01 0000 [.text] __ZN27AMDRadeonX4000_AMDHWChannel25alignCommandBufferAddressEj 000000000006e9f8 l 0e SECT 01 0000 [.text] __ZN15AMDSIDMAChannel20getIBAlignmentFactorEv 000000000006ea04 l 0e SECT 01 0000 [.text] __ZN15AMDSIDMAChannel21getOneDwordNOPCommandEv 000000000006ea10 l 0e SECT 01 0000 [.text] __ZN27AMDRadeonX4000_AMDHWChannel7getNameEv 000000000006ea1a l 0e SECT 01 0000 [.text] __ZN27AMDRadeonX4000_AMDHWChannel19dumpEngineHangStateEb 000000000006ea34 l 0e SECT 01 0000 [.text] __ZN27AMDRadeonX4000_AMDHWChannel10engineTypeEv 000000000006ea46 l 0e SECT 01 0000 [.text] __ZN27AMDRadeonX4000_AMDHWChannel18isDebugFlagEnabledEj 000000000006ea5a l 0e SECT 01 0000 [.text] __ZN27AMDRadeonX4000_AMDHWChannel24getTimestampInterruptRefEv 000000000006ea64 l 0e SECT 01 0000 [.text] __ZN27AMDRadeonX4000_AMDHWChannel25getHWStatisticsGroupTableEv 000000000006ea72 l 0e SECT 01 0000 [.text] __ZN27AMDRadeonX4000_AMDHWChannel23clearInterrupEnableFlagEv 000000000006ea7c l 0e SECT 01 0000 [.text] __ZN27AMDRadeonX4000_AMDHWChannel22getIndirectCommandSizeEv 000000000006ea88 l 0e SECT 01 0000 [.text] __ZNK30AMDRadeonX4000_AMDDMAHWChannel13getDmaPktInfoE20AMD_DMA_COMMAND_TYPE 000000000006eaa0 l 0e SECT 01 0000 [.text] __GLOBAL__I_a 000000000006eae0 l 0e SECT 01 0000 [.text] __GLOBAL__D_a 000000000006eb32 l 0e SECT 01 0000 [.text] __ZN12AMDSIDMARing9MetaClassD1Ev 000000000006f23c l 0e SECT 01 0000 [.text] __ZN12AMDSIDMARing9MetaClassD0Ev 000000000006f246 l 0e SECT 01 0000 [.text] __ZN25AMDRadeonX4000_IAMDHWRing4initEv 000000000006f258 l 0e SECT 01 0000 [.text] __ZN24AMDRadeonX4000_AMDHWRing9isEnabledEv 000000000006f262 l 0e SECT 01 0000 [.text] __ZN24AMDRadeonX4000_AMDHWRing7getTailEv 000000000006f26e l 0e SECT 01 0000 [.text] __ZN24AMDRadeonX4000_AMDHWRing12getFreeSpaceEv 000000000006f29e l 0e SECT 01 0000 [.text] __ZN24AMDRadeonX4000_AMDHWRing7isEmptyEv 000000000006f2cc l 0e SECT 01 0000 [.text] __ZN24AMDRadeonX4000_AMDHWRing15getRingGartAddrEv 000000000006f2d6 l 0e SECT 01 0000 [.text] __ZN24AMDRadeonX4000_AMDHWRing7getSizeEv 000000000006f2e0 l 0e SECT 01 0000 [.text] __ZN24AMDRadeonX4000_AMDHWRing12getRingBlockEj 000000000006f2f2 l 0e SECT 01 0000 [.text] __ZN24AMDRadeonX4000_AMDHWRing11commitBlockEj 000000000006f302 l 0e SECT 01 0000 [.text] __ZN24AMDRadeonX4000_AMDHWRing9getRingIdEv 000000000006f30e l 0e SECT 01 0000 [.text] __ZN12AMDSIDMARing26enableReadPointerWriteBackEv 000000000006f314 l 0e SECT 01 0000 [.text] __ZN12AMDSIDMARing27disableReadPointerWriteBackEv 000000000006f320 l 0e SECT 01 0000 [.text] __GLOBAL__I_a 000000000006f360 l 0e SECT 01 0000 [.text] __GLOBAL__D_a 000000000006f3b2 l 0e SECT 01 0000 [.text] __ZN16AMDSIVCEHWEngine9MetaClassD1Ev 000000000006fa5a l 0e SECT 01 0000 [.text] __ZN16AMDSIVCEHWEngine9MetaClassD0Ev 000000000006fa64 l 0e SECT 01 0000 [.text] __ZN27AMDRadeonX4000_IAMDHWEngine4initEv 000000000006fa76 l 0e SECT 01 0000 [.text] __ZN26AMDRadeonX4000_AMDHWEngine4typeEv 000000000006fa80 l 0e SECT 01 0000 [.text] __ZN26AMDRadeonX4000_AMDHWEngine9isEnabledEv 000000000006fa8a l 0e SECT 01 0000 [.text] __ZN26AMDRadeonX4000_AMDHWEngine20setVirtualSpaceReadyEb 000000000006fa90 l 0e SECT 01 0000 [.text] __ZN29AMDRadeonX4000_AMDVCEHWEngine19initializeRegistersEv 000000000006fa96 l 0e SECT 01 0000 [.text] __ZN29AMDRadeonX4000_AMDVCEHWEngine26systemWillChangeSpeedEventEv 000000000006fa9c l 0e SECT 01 0000 [.text] __ZN29AMDRadeonX4000_AMDVCEHWEngine25systemDidChangeSpeedEventEv 000000000006faa2 l 0e SECT 01 0000 [.text] __ZN29AMDRadeonX4000_AMDVCEHWEngine25alignCommandBufferAddressEj 000000000006faae l 0e SECT 01 0000 [.text] __ZN26AMDRadeonX4000_AMDHWEngine10getVersionEj 000000000006fabe l 0e SECT 01 0000 [.text] __ZN26AMDRadeonX4000_AMDHWEngine15getChannelCountEv 000000000006fac8 l 0e SECT 01 0000 [.text] __ZN26AMDRadeonX4000_AMDHWEngine22getTimestampIRQSourcexE18_eAMD_HW_RING_TYPE 000000000006fad0 l 0e SECT 01 0000 [.text] __ZN26AMDRadeonX4000_AMDHWEngine14getFwvFunctionEv 000000000006fad8 l 0e SECT 01 0000 [.text] __ZN29AMDRadeonX4000_AMDVCEHWEngine18getTotalCapabilityEv 000000000006faec l 0e SECT 01 0000 [.text] __ZN29AMDRadeonX4000_AMDVCEHWEngine20getCurrentCapabilityEv 000000000006fb00 l 0e SECT 01 0000 [.text] __ZN29AMDRadeonX4000_AMDVCEHWEngine10getVCEVClkEv 000000000006fb0c l 0e SECT 01 0000 [.text] __ZN29AMDRadeonX4000_AMDVCEHWEngine10getVCECClkEv 000000000006fb20 l 0e SECT 01 0000 [.text] __GLOBAL__I_a 000000000006fb60 l 0e SECT 01 0000 [.text] __GLOBAL__D_a 000000000006fbb2 l 0e SECT 01 0000 [.text] __ZN15AMDSIVCEChannel9MetaClassD1Ev 000000000006fed8 l 0e SECT 01 0000 [.text] __ZN15AMDSIVCEChannel9MetaClassD0Ev 000000000006fee2 l 0e SECT 01 0000 [.text] __ZN28AMDRadeonX4000_IAMDHWChannel4initEv 000000000006fef4 l 0e SECT 01 0000 [.text] __ZN27AMDRadeonX4000_AMDHWChannel15getChannelIndexEv 000000000006fefe l 0e SECT 01 0000 [.text] __ZN27AMDRadeonX4000_AMDHWChannel18getChannelRingTypeEv 000000000006ff1a l 0e SECT 01 0000 [.text] __ZN27AMDRadeonX4000_AMDHWChannel33initializeSubmitCommandBufferInfoEP30AMD_SUBMIT_COMMAND_BUFFER_INFO 000000000006ff30 l 0e SECT 01 0000 [.text] __ZN27AMDRadeonX4000_AMDHWChannel25alignCommandBufferAddressEj 000000000006ff46 l 0e SECT 01 0000 [.text] __ZN30AMDRadeonX4000_AMDVCEHWChannel20getIBAlignmentFactorEv 000000000006ff52 l 0e SECT 01 0000 [.text] __ZN30AMDRadeonX4000_AMDVCEHWChannel21getOneDwordNOPCommandEv 000000000006ff5a l 0e SECT 01 0000 [.text] __ZN27AMDRadeonX4000_AMDHWChannel7getNameEv 000000000006ff64 l 0e SECT 01 0000 [.text] __ZN27AMDRadeonX4000_AMDHWChannel19dumpEngineHangStateEb 000000000006ff7e l 0e SECT 01 0000 [.text] __ZN27AMDRadeonX4000_AMDHWChannel21writeProfilingCommandEPjyjb 000000000006ff86 l 0e SECT 01 0000 [.text] __ZN27AMDRadeonX4000_AMDHWChannel10engineTypeEv 000000000006ff98 l 0e SECT 01 0000 [.text] __ZN27AMDRadeonX4000_AMDHWChannel18isDebugFlagEnabledEj 000000000006ffac l 0e SECT 01 0000 [.text] __ZN27AMDRadeonX4000_AMDHWChannel24getTimestampInterruptRefEv 000000000006ffb6 l 0e SECT 01 0000 [.text] __ZN27AMDRadeonX4000_AMDHWChannel25getHWStatisticsGroupTableEv 000000000006ffc4 l 0e SECT 01 0000 [.text] __ZN27AMDRadeonX4000_AMDHWChannel23clearInterrupEnableFlagEv 000000000006ffd0 l 0e SECT 01 0000 [.text] __GLOBAL__I_a 0000000000070010 l 0e SECT 01 0000 [.text] __GLOBAL__D_a 0000000000070062 l 0e SECT 01 0000 [.text] __ZN18AMDSIVCELLQChannel9MetaClassD1Ev 00000000000701f2 l 0e SECT 01 0000 [.text] __ZN18AMDSIVCELLQChannel9MetaClassD0Ev 00000000000701fc l 0e SECT 01 0000 [.text] __ZN28AMDRadeonX4000_IAMDHWChannel4initEv 000000000007020e l 0e SECT 01 0000 [.text] __ZN27AMDRadeonX4000_AMDHWChannel15getChannelIndexEv 0000000000070218 l 0e SECT 01 0000 [.text] __ZN27AMDRadeonX4000_AMDHWChannel18getChannelRingTypeEv 0000000000070234 l 0e SECT 01 0000 [.text] __ZN27AMDRadeonX4000_AMDHWChannel33initializeSubmitCommandBufferInfoEP30AMD_SUBMIT_COMMAND_BUFFER_INFO 000000000007024a l 0e SECT 01 0000 [.text] __ZN27AMDRadeonX4000_AMDHWChannel25alignCommandBufferAddressEj 0000000000070260 l 0e SECT 01 0000 [.text] __ZN30AMDRadeonX4000_AMDVCEHWChannel20getIBAlignmentFactorEv 000000000007026c l 0e SECT 01 0000 [.text] __ZN30AMDRadeonX4000_AMDVCEHWChannel21getOneDwordNOPCommandEv 0000000000070274 l 0e SECT 01 0000 [.text] __ZN27AMDRadeonX4000_AMDHWChannel7getNameEv 000000000007027e l 0e SECT 01 0000 [.text] __ZN27AMDRadeonX4000_AMDHWChannel19dumpEngineHangStateEb 0000000000070298 l 0e SECT 01 0000 [.text] __ZN27AMDRadeonX4000_AMDHWChannel21writeProfilingCommandEPjyjb 00000000000702a0 l 0e SECT 01 0000 [.text] __ZN27AMDRadeonX4000_AMDHWChannel10engineTypeEv 00000000000702b2 l 0e SECT 01 0000 [.text] __ZN27AMDRadeonX4000_AMDHWChannel18isDebugFlagEnabledEj 00000000000702c6 l 0e SECT 01 0000 [.text] __ZN27AMDRadeonX4000_AMDHWChannel24getTimestampInterruptRefEv 00000000000702d0 l 0e SECT 01 0000 [.text] __ZN27AMDRadeonX4000_AMDHWChannel25getHWStatisticsGroupTableEv 00000000000702de l 0e SECT 01 0000 [.text] __ZN27AMDRadeonX4000_AMDHWChannel23clearInterrupEnableFlagEv 00000000000702f0 l 0e SECT 01 0000 [.text] __GLOBAL__I_a 0000000000070330 l 0e SECT 01 0000 [.text] __GLOBAL__D_a 0000000000070382 l 0e SECT 01 0000 [.text] __ZN12AMDSIVCERing9MetaClassD1Ev 00000000000707ac l 0e SECT 01 0000 [.text] __ZN12AMDSIVCERing9MetaClassD0Ev 00000000000707b6 l 0e SECT 01 0000 [.text] __ZN25AMDRadeonX4000_IAMDHWRing4initEv 00000000000707c8 l 0e SECT 01 0000 [.text] __ZN24AMDRadeonX4000_AMDHWRing9isEnabledEv 00000000000707d2 l 0e SECT 01 0000 [.text] __ZN24AMDRadeonX4000_AMDHWRing7getTailEv 00000000000707de l 0e SECT 01 0000 [.text] __ZN24AMDRadeonX4000_AMDHWRing12getFreeSpaceEv 000000000007080e l 0e SECT 01 0000 [.text] __ZN24AMDRadeonX4000_AMDHWRing7isEmptyEv 000000000007083c l 0e SECT 01 0000 [.text] __ZN24AMDRadeonX4000_AMDHWRing15getRingGartAddrEv 0000000000070846 l 0e SECT 01 0000 [.text] __ZN24AMDRadeonX4000_AMDHWRing7getSizeEv 0000000000070850 l 0e SECT 01 0000 [.text] __ZN24AMDRadeonX4000_AMDHWRing12getRingBlockEj 0000000000070862 l 0e SECT 01 0000 [.text] __ZN24AMDRadeonX4000_AMDHWRing11commitBlockEj 0000000000070872 l 0e SECT 01 0000 [.text] __ZN24AMDRadeonX4000_AMDHWRing9getRingIdEv 0000000000070880 l 0e SECT 01 0000 [.text] __GLOBAL__I_a 00000000000708c0 l 0e SECT 01 0000 [.text] __GLOBAL__D_a 0000000000070912 l 0e SECT 01 0000 [.text] __ZN15AMDSIVCELLQRing9MetaClassD1Ev 0000000000070b9a l 0e SECT 01 0000 [.text] __ZN15AMDSIVCELLQRing9MetaClassD0Ev 0000000000070ba4 l 0e SECT 01 0000 [.text] __ZN25AMDRadeonX4000_IAMDHWRing4initEv 0000000000070bb6 l 0e SECT 01 0000 [.text] __ZN24AMDRadeonX4000_AMDHWRing9isEnabledEv 0000000000070bc0 l 0e SECT 01 0000 [.text] __ZN24AMDRadeonX4000_AMDHWRing7getTailEv 0000000000070bcc l 0e SECT 01 0000 [.text] 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__ZN27AMDRadeonX4000_AMDHWChannel15getChannelIndexEv 0000000000071248 l 0e SECT 01 0000 [.text] __ZN27AMDRadeonX4000_AMDHWChannel18getChannelRingTypeEv 0000000000071264 l 0e SECT 01 0000 [.text] __ZN27AMDRadeonX4000_AMDHWChannel33initializeSubmitCommandBufferInfoEP30AMD_SUBMIT_COMMAND_BUFFER_INFO 000000000007127a l 0e SECT 01 0000 [.text] __ZN27AMDRadeonX4000_AMDHWChannel25alignCommandBufferAddressEj 0000000000071290 l 0e SECT 01 0000 [.text] __ZN15AMDSIUVDChannel20getIBAlignmentFactorEv 000000000007129c l 0e SECT 01 0000 [.text] __ZN27AMDRadeonX4000_AMDHWChannel7getNameEv 00000000000712a6 l 0e SECT 01 0000 [.text] __ZN27AMDRadeonX4000_AMDHWChannel19dumpEngineHangStateEb 00000000000712c0 l 0e SECT 01 0000 [.text] __ZN27AMDRadeonX4000_AMDHWChannel21writeProfilingCommandEPjyjb 00000000000712c8 l 0e SECT 01 0000 [.text] __ZN27AMDRadeonX4000_AMDHWChannel10engineTypeEv 00000000000712da l 0e SECT 01 0000 [.text] __ZN27AMDRadeonX4000_AMDHWChannel18isDebugFlagEnabledEj 00000000000712ee l 0e SECT 01 0000 [.text] __ZN27AMDRadeonX4000_AMDHWChannel24getTimestampInterruptRefEv 00000000000712f8 l 0e SECT 01 0000 [.text] __ZN27AMDRadeonX4000_AMDHWChannel25getHWStatisticsGroupTableEv 0000000000071306 l 0e SECT 01 0000 [.text] __ZN27AMDRadeonX4000_AMDHWChannel23clearInterrupEnableFlagEv 0000000000071310 l 0e SECT 01 0000 [.text] __ZN15AMDSIUVDChannel22getIndirectCommandSizeEv 0000000000071320 l 0e SECT 01 0000 [.text] __GLOBAL__I_a 0000000000071360 l 0e SECT 01 0000 [.text] __GLOBAL__D_a 00000000000713b2 l 0e SECT 01 0000 [.text] __ZN16AMDSIUVDHWEngine9MetaClassD1Ev 0000000000071a3c l 0e SECT 01 0000 [.text] __ZN27AMDRadeonX4000_IAMDHWEngine4initEv 0000000000071a4e l 0e SECT 01 0000 [.text] __ZN16AMDSIUVDHWEngine4freeEv 0000000000071a60 l 0e SECT 01 0000 [.text] __ZN26AMDRadeonX4000_AMDHWEngine4typeEv 0000000000071a6a l 0e SECT 01 0000 [.text] __ZN29AMDRadeonX4000_AMDUVDHWEngine19initializeRegistersEv 0000000000071a70 l 0e SECT 01 0000 [.text] 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01 0000 [.text] __ZN29AMDRadeonX4000_AMDUVDHWEngine10getUVDDclkEv 0000000000071af8 l 0e SECT 01 0000 [.text] __ZN29AMDRadeonX4000_AMDUVDHWEngine14getHWRegistersEv 0000000000071b02 l 0e SECT 01 0000 [.text] __ZN29AMDRadeonX4000_AMDUVDHWEngine12getKeySelectEv 0000000000071b0e l 0e SECT 01 0000 [.text] __ZN29AMDRadeonX4000_AMDUVDHWEngine15setDpmSupportedEb 0000000000071b1c l 0e SECT 01 0000 [.text] __ZN16AMDSIUVDHWEngine9MetaClassD0Ev 0000000000071b30 l 0e SECT 01 0000 [.text] __GLOBAL__I_a 0000000000071b70 l 0e SECT 01 0000 [.text] __GLOBAL__D_a 0000000000071bc2 l 0e SECT 01 0000 [.text] __ZN12AMDSIUVDRing9MetaClassD1Ev 0000000000072046 l 0e SECT 01 0000 [.text] __ZN12AMDSIUVDRing9MetaClassD0Ev 0000000000072050 l 0e SECT 01 0000 [.text] __ZN25AMDRadeonX4000_IAMDHWRing4initEv 0000000000072062 l 0e SECT 01 0000 [.text] __ZN24AMDRadeonX4000_AMDHWRing9isEnabledEv 000000000007206c l 0e SECT 01 0000 [.text] __ZN24AMDRadeonX4000_AMDHWRing7getTailEv 0000000000072078 l 0e SECT 01 0000 [.text] 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[.text] __ZN26AMDRadeonX4000_AMDHWEngine14getFwvFunctionEv 0000000000072e30 l 0e SECT 01 0000 [.text] __GLOBAL__I_a 0000000000072e70 l 0e SECT 01 0000 [.text] __GLOBAL__D_a 0000000000072ec2 l 0e SECT 01 0000 [.text] __ZN15AMDSISPUChannel9MetaClassD1Ev 000000000007311a l 0e SECT 01 0000 [.text] __ZN15AMDSISPUChannel9MetaClassD0Ev 0000000000073124 l 0e SECT 01 0000 [.text] __ZN28AMDRadeonX4000_IAMDHWChannel4initEv 0000000000073136 l 0e SECT 01 0000 [.text] __ZN27AMDRadeonX4000_AMDHWChannel15getChannelIndexEv 0000000000073140 l 0e SECT 01 0000 [.text] __ZN27AMDRadeonX4000_AMDHWChannel18getChannelRingTypeEv 000000000007315c l 0e SECT 01 0000 [.text] __ZN27AMDRadeonX4000_AMDHWChannel33initializeSubmitCommandBufferInfoEP30AMD_SUBMIT_COMMAND_BUFFER_INFO 0000000000073172 l 0e SECT 01 0000 [.text] __ZN27AMDRadeonX4000_AMDHWChannel25alignCommandBufferAddressEj 0000000000073188 l 0e SECT 01 0000 [.text] __ZN30AMDRadeonX4000_AMDSPUHWChannel20getIBAlignmentFactorEv 0000000000073194 l 0e SECT 01 0000 [.text] __ZN30AMDRadeonX4000_AMDSPUHWChannel21getOneDwordNOPCommandEv 00000000000731a0 l 0e SECT 01 0000 [.text] __ZNK27AMDRadeonX4000_AMDHWChannel21writeSemaphoreCommandEPjyb 00000000000731a8 l 0e SECT 01 0000 [.text] __ZN27AMDRadeonX4000_AMDHWChannel7getNameEv 00000000000731b2 l 0e SECT 01 0000 [.text] __ZN27AMDRadeonX4000_AMDHWChannel19dumpEngineHangStateEb 00000000000731cc l 0e SECT 01 0000 [.text] __ZN27AMDRadeonX4000_AMDHWChannel21writeProfilingCommandEPjyjb 00000000000731d4 l 0e SECT 01 0000 [.text] __ZN27AMDRadeonX4000_AMDHWChannel10engineTypeEv 00000000000731e6 l 0e SECT 01 0000 [.text] __ZN27AMDRadeonX4000_AMDHWChannel18isDebugFlagEnabledEj 00000000000731fa l 0e SECT 01 0000 [.text] __ZN27AMDRadeonX4000_AMDHWChannel24getTimestampInterruptRefEv 0000000000073204 l 0e SECT 01 0000 [.text] __ZN27AMDRadeonX4000_AMDHWChannel25getHWStatisticsGroupTableEv 0000000000073212 l 0e SECT 01 0000 [.text] __ZN27AMDRadeonX4000_AMDHWChannel23clearInterrupEnableFlagEv 000000000007321c l 0e SECT 01 0000 [.text] __ZN30AMDRadeonX4000_AMDSPUHWChannel22getIndirectCommandSizeEv 0000000000073230 l 0e SECT 01 0000 [.text] __GLOBAL__I_a 0000000000073270 l 0e SECT 01 0000 [.text] __GLOBAL__D_a 00000000000732c2 l 0e SECT 01 0000 [.text] __ZN12AMDSISPURing9MetaClassD1Ev 0000000000073722 l 0e SECT 01 0000 [.text] __ZN12AMDSISPURing9MetaClassD0Ev 000000000007372c l 0e SECT 01 0000 [.text] __ZN25AMDRadeonX4000_IAMDHWRing4initEv 000000000007373e l 0e SECT 01 0000 [.text] __ZN24AMDRadeonX4000_AMDHWRing9isEnabledEv 0000000000073748 l 0e SECT 01 0000 [.text] __ZN24AMDRadeonX4000_AMDHWRing7getTailEv 0000000000073754 l 0e SECT 01 0000 [.text] __ZN24AMDRadeonX4000_AMDHWRing12getFreeSpaceEv 0000000000073784 l 0e SECT 01 0000 [.text] __ZN24AMDRadeonX4000_AMDHWRing7isEmptyEv 00000000000737b2 l 0e SECT 01 0000 [.text] __ZN24AMDRadeonX4000_AMDHWRing15getRingGartAddrEv 00000000000737bc l 0e SECT 01 0000 [.text] __ZN24AMDRadeonX4000_AMDHWRing7getSizeEv 00000000000737c6 l 0e SECT 01 0000 [.text] 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[.text] __ZN27AMDRadeonX4000_AMDHWChannel33initializeSubmitCommandBufferInfoEP30AMD_SUBMIT_COMMAND_BUFFER_INFO 00000000000746bc l 0e SECT 01 0000 [.text] __ZN27AMDRadeonX4000_AMDHWChannel25alignCommandBufferAddressEj 00000000000746d2 l 0e SECT 01 0000 [.text] __ZN27AMDRadeonX4000_AMDHWChannel7getNameEv 00000000000746dc l 0e SECT 01 0000 [.text] __ZN27AMDRadeonX4000_AMDHWChannel19dumpEngineHangStateEb 00000000000746f6 l 0e SECT 01 0000 [.text] __ZN27AMDRadeonX4000_AMDHWChannel10engineTypeEv 0000000000074708 l 0e SECT 01 0000 [.text] __ZN27AMDRadeonX4000_AMDHWChannel18isDebugFlagEnabledEj 000000000007471c l 0e SECT 01 0000 [.text] __ZN27AMDRadeonX4000_AMDHWChannel24getTimestampInterruptRefEv 0000000000074726 l 0e SECT 01 0000 [.text] __ZN27AMDRadeonX4000_AMDHWChannel25getHWStatisticsGroupTableEv 0000000000074734 l 0e SECT 01 0000 [.text] __ZN27AMDRadeonX4000_AMDHWChannel23clearInterrupEnableFlagEv 000000000007473e l 0e SECT 01 0000 [.text] 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000000000007719a l 0e SECT 01 0000 [.text] __ZN26AMDRadeonX4000_AMDHardware9getChipIDEv 00000000000771a6 l 0e SECT 01 0000 [.text] __ZN26AMDRadeonX4000_AMDHardware10getChipRevEv 00000000000771b2 l 0e SECT 01 0000 [.text] __ZN26AMDRadeonX4000_AMDHardware14getSubSystemIDEv 00000000000771be l 0e SECT 01 0000 [.text] __ZN26AMDRadeonX4000_AMDHardware9getFamilyEv 00000000000771ca l 0e SECT 01 0000 [.text] __ZN26AMDRadeonX4000_AMDHardware34getPreDefinedNdrvVramReservedSpaceEv 00000000000771d6 l 0e SECT 01 0000 [.text] __ZN26AMDRadeonX4000_AMDHardware22setTLBInvalidateNeededEj 00000000000771ec l 0e SECT 01 0000 [.text] __ZN26AMDRadeonX4000_AMDHardware19getDiagReportBufferEv 0000000000077208 l 0e SECT 01 0000 [.text] __ZN26AMDRadeonX4000_AMDHardware23getDiagReportBufferSizeEv 0000000000077214 l 0e SECT 01 0000 [.text] __ZN26AMDRadeonX4000_AMDHardware9isEnabledEv 0000000000077220 l 0e SECT 01 0000 [.text] __ZN26AMDRadeonX4000_AMDHardware24isMultiEngineSyncEnabledEv 000000000007722c l 0e SECT 01 0000 [.text] __ZN26AMDRadeonX4000_AMDHardware13getCailHandleEv 000000000007723a l 0e SECT 01 0000 [.text] __ZN26AMDRadeonX4000_AMDHardware15getAMDHWHandlerEv 0000000000077244 l 0e SECT 01 0000 [.text] __ZN26AMDRadeonX4000_AMDHardware14getHWRegistersEv 0000000000077252 l 0e SECT 01 0000 [.text] __ZN26AMDRadeonX4000_AMDHardware11getHWMemoryEv 0000000000077260 l 0e SECT 01 0000 [.text] __ZN26AMDRadeonX4000_AMDHardware9getHWGartEv 000000000007726e l 0e SECT 01 0000 [.text] __ZN26AMDRadeonX4000_AMDHardware8getHWVMMEv 000000000007727c l 0e SECT 01 0000 [.text] __ZN26AMDRadeonX4000_AMDHardware12getHWDisplayEv 000000000007728a l 0e SECT 01 0000 [.text] __ZN26AMDRadeonX4000_AMDHardware17getHWAlignManagerEv 0000000000077298 l 0e SECT 01 0000 [.text] __ZN13AMDCIHardware16getHWWorkaroundsEv 00000000000772a6 l 0e SECT 01 0000 [.text] __ZN26AMDRadeonX4000_AMDHardware17getAMDHWUtilitiesEv 00000000000772b4 l 0e SECT 01 0000 [.text] __ZN26AMDRadeonX4000_AMDHardware11getHWEngineE20_eAMD_HW_ENGINE_TYPE 00000000000772c4 l 0e SECT 01 0000 [.text] __ZN26AMDRadeonX4000_AMDHardware15getChannelCountEv 00000000000772d0 l 0e SECT 01 0000 [.text] __ZN26AMDRadeonX4000_AMDHardware29getChannelWriteBackDescriptorEv 00000000000772de l 0e SECT 01 0000 [.text] __ZN26AMDRadeonX4000_AMDHardware28getChannelWriteBackFrameSizeEv 00000000000772ea l 0e SECT 01 0000 [.text] __ZN26AMDRadeonX4000_AMDHardware18getHWSemaphorePoolEv 00000000000772f8 l 0e SECT 01 0000 [.text] __ZN26AMDRadeonX4000_AMDHardware14getIOPCIDeviceEv 0000000000077302 l 0e SECT 01 0000 [.text] __ZN26AMDRadeonX4000_AMDHardware6getSMLEv 0000000000077310 l 0e SECT 01 0000 [.text] __ZN26AMDRadeonX4000_AMDHardware21getPM4CommandsUtilityEv 000000000007731e l 0e SECT 01 0000 [.text] __ZN26AMDRadeonX4000_AMDHardware17getGpuDebugPolicyEv 000000000007732a l 0e SECT 01 0000 [.text] __ZNK26AMDRadeonX4000_AMDHardware10getCailIriEv 0000000000077338 l 0e SECT 01 0000 [.text] __ZN26AMDRadeonX4000_AMDHardware11setPPLibIriEP24CAIL_IRI_REGISTRY_STRUCT 0000000000077380 l 0e SECT 01 0000 [.text] __ZN13AMDCIHardware23getGPUVMDefaultSettingsEv 000000000007738c l 0e SECT 01 0000 [.text] __ZN13AMDCIHardware22getMEQCmdQueueSelIndexEv 0000000000077398 l 0e SECT 01 0000 [.text] __ZN13AMDCIHardware36shallInitializeMC_VM_MD_L1_TLB3_CNTLEv 00000000000773a0 l 0e SECT 01 0000 [.text] __ZN13AMDCIHardware17allocatePM4EngineEv 00000000000773b0 l 0e SECT 01 0000 [.text] __GLOBAL__I_a 00000000000773f0 l 0e SECT 01 0000 [.text] __GLOBAL__D_a 0000000000077442 l 0e SECT 01 0000 [.text] __ZN18AMDBonaireHardware9MetaClassD1Ev 00000000000776ce l 0e SECT 01 0000 [.text] __ZN30AMDRadeonX4000_IAMDHWInterface4initEv 00000000000776e0 l 0e SECT 01 0000 [.text] __ZN18AMDBonaireHardware4freeEv 00000000000776f2 l 0e SECT 01 0000 [.text] __ZN26AMDRadeonX4000_AMDHardware21getHWMemoryDescriptorEv 0000000000077700 l 0e SECT 01 0000 [.text] __ZN26AMDRadeonX4000_AMDHardware13getChipEngineEv 000000000007770c l 0e SECT 01 0000 [.text] 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[.text] __GLOBAL__D_a 000000000007d202 l 0e SECT 01 0000 [.text] __ZN15AMDCIPM4Channel9MetaClassD1Ev 000000000007e09c l 0e SECT 01 0000 [.text] __ZN15AMDCIPM4Channel9MetaClassD0Ev 000000000007e0a6 l 0e SECT 01 0000 [.text] __ZN28AMDRadeonX4000_IAMDHWChannel4initEv 000000000007e0b8 l 0e SECT 01 0000 [.text] __ZN27AMDRadeonX4000_AMDHWChannel15getChannelIndexEv 000000000007e0c2 l 0e SECT 01 0000 [.text] __ZN27AMDRadeonX4000_AMDHWChannel18getChannelRingTypeEv 000000000007e0de l 0e SECT 01 0000 [.text] __ZN27AMDRadeonX4000_AMDHWChannel33initializeSubmitCommandBufferInfoEP30AMD_SUBMIT_COMMAND_BUFFER_INFO 000000000007e0f4 l 0e SECT 01 0000 [.text] __ZN27AMDRadeonX4000_AMDHWChannel25alignCommandBufferAddressEj 000000000007e10a l 0e SECT 01 0000 [.text] __ZN27AMDRadeonX4000_AMDHWChannel7getNameEv 000000000007e114 l 0e SECT 01 0000 [.text] __ZN27AMDRadeonX4000_AMDHWChannel19dumpEngineHangStateEb 000000000007e12e l 0e SECT 01 0000 [.text] __ZN27AMDRadeonX4000_AMDHWChannel10engineTypeEv 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0e SECT 01 0000 [.text] __GLOBAL__D_a 000000000007e232 l 0e SECT 01 0000 [.text] __ZN15AMDCIDMAChannel9MetaClassD1Ev 000000000007ef3a l 0e SECT 01 0000 [.text] __ZN15AMDCIDMAChannel9MetaClassD0Ev 000000000007ef44 l 0e SECT 01 0000 [.text] __ZN28AMDRadeonX4000_IAMDHWChannel4initEv 000000000007ef56 l 0e SECT 01 0000 [.text] __ZN27AMDRadeonX4000_AMDHWChannel15getChannelIndexEv 000000000007ef60 l 0e SECT 01 0000 [.text] __ZN27AMDRadeonX4000_AMDHWChannel18getChannelRingTypeEv 000000000007ef7c l 0e SECT 01 0000 [.text] __ZN27AMDRadeonX4000_AMDHWChannel33initializeSubmitCommandBufferInfoEP30AMD_SUBMIT_COMMAND_BUFFER_INFO 000000000007ef92 l 0e SECT 01 0000 [.text] __ZN27AMDRadeonX4000_AMDHWChannel25alignCommandBufferAddressEj 000000000007efa8 l 0e SECT 01 0000 [.text] __ZN15AMDCIDMAChannel20getIBAlignmentFactorEv 000000000007efb4 l 0e SECT 01 0000 [.text] __ZN15AMDCIDMAChannel21getOneDwordNOPCommandEv 000000000007efbc l 0e SECT 01 0000 [.text] __ZN27AMDRadeonX4000_AMDHWChannel7getNameEv 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000000000007f8fc l 0e SECT 01 0000 [.text] __ZN26AMDRadeonX4000_AMDHWEngine15getChannelCountEv 000000000007f906 l 0e SECT 01 0000 [.text] __ZN26AMDRadeonX4000_AMDHWEngine22getTimestampIRQSourcexE18_eAMD_HW_RING_TYPE 000000000007f90e l 0e SECT 01 0000 [.text] __ZN26AMDRadeonX4000_AMDHWEngine14getFwvFunctionEv 000000000007f920 l 0e SECT 01 0000 [.text] __GLOBAL__I_a 000000000007f960 l 0e SECT 01 0000 [.text] __GLOBAL__D_a 000000000007f9b2 l 0e SECT 01 0000 [.text] __ZN16AMDCISAMURBIRing9MetaClassD1Ev 000000000007fe14 l 0e SECT 01 0000 [.text] __ZN16AMDCISAMURBIRing9MetaClassD0Ev 000000000007fe1e l 0e SECT 01 0000 [.text] __ZN25AMDRadeonX4000_IAMDHWRing4initEv 000000000007fe30 l 0e SECT 01 0000 [.text] __ZN24AMDRadeonX4000_AMDHWRing9isEnabledEv 000000000007fe3a l 0e SECT 01 0000 [.text] __ZN24AMDRadeonX4000_AMDHWRing7isEmptyEv 000000000007fe68 l 0e SECT 01 0000 [.text] __ZN24AMDRadeonX4000_AMDHWRing15getRingGartAddrEv 000000000007fe72 l 0e SECT 01 0000 [.text] __ZN24AMDRadeonX4000_AMDHWRing7getSizeEv 000000000007fe7c l 0e SECT 01 0000 [.text] __ZN24AMDRadeonX4000_AMDHWRing12getRingBlockEj 000000000007fe8e l 0e SECT 01 0000 [.text] __ZN24AMDRadeonX4000_AMDHWRing9getRingIdEv 000000000007fea0 l 0e SECT 01 0000 [.text] __GLOBAL__I_a 000000000007fee0 l 0e SECT 01 0000 [.text] __GLOBAL__D_a 000000000007ff32 l 0e SECT 01 0000 [.text] __ZN19AMDCISAMURBIChannel9MetaClassD1Ev 000000000008018a l 0e SECT 01 0000 [.text] __ZN19AMDCISAMURBIChannel9MetaClassD0Ev 0000000000080194 l 0e SECT 01 0000 [.text] __ZN28AMDRadeonX4000_IAMDHWChannel4initEv 00000000000801a6 l 0e SECT 01 0000 [.text] __ZN27AMDRadeonX4000_AMDHWChannel15getChannelIndexEv 00000000000801b0 l 0e SECT 01 0000 [.text] __ZN27AMDRadeonX4000_AMDHWChannel18getChannelRingTypeEv 00000000000801cc l 0e SECT 01 0000 [.text] __ZN27AMDRadeonX4000_AMDHWChannel33initializeSubmitCommandBufferInfoEP30AMD_SUBMIT_COMMAND_BUFFER_INFO 00000000000801e2 l 0e SECT 01 0000 [.text] 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[.text] __ZN27AMDRadeonX4000_AMDHWChannel25getHWStatisticsGroupTableEv 0000000000080282 l 0e SECT 01 0000 [.text] __ZN27AMDRadeonX4000_AMDHWChannel23clearInterrupEnableFlagEv 000000000008028c l 0e SECT 01 0000 [.text] __ZN30AMDRadeonX4000_AMDSPUHWChannel22getIndirectCommandSizeEv 00000000000802a0 l 0e SECT 01 0000 [.text] __GLOBAL__I_a 00000000000802e0 l 0e SECT 01 0000 [.text] __GLOBAL__D_a 0000000000080332 l 0e SECT 01 0000 [.text] __ZN18AMDCISAMUGPCOMRing9MetaClassD1Ev 0000000000080936 l 0e SECT 01 0000 [.text] __ZN18AMDCISAMUGPCOMRing9MetaClassD0Ev 0000000000080940 l 0e SECT 01 0000 [.text] __ZN25AMDRadeonX4000_IAMDHWRing4initEv 0000000000080952 l 0e SECT 01 0000 [.text] __ZN24AMDRadeonX4000_AMDHWRing9isEnabledEv 000000000008095c l 0e SECT 01 0000 [.text] __ZN24AMDRadeonX4000_AMDHWRing7getTailEv 0000000000080968 l 0e SECT 01 0000 [.text] __ZN24AMDRadeonX4000_AMDHWRing12getFreeSpaceEv 0000000000080998 l 0e SECT 01 0000 [.text] __ZN24AMDRadeonX4000_AMDHWRing7isEmptyEv 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0000000000080d1c l 0e SECT 01 0000 [.text] __ZN27AMDRadeonX4000_AMDHWChannel18getChannelRingTypeEv 0000000000080d38 l 0e SECT 01 0000 [.text] __ZN27AMDRadeonX4000_AMDHWChannel33initializeSubmitCommandBufferInfoEP30AMD_SUBMIT_COMMAND_BUFFER_INFO 0000000000080d4e l 0e SECT 01 0000 [.text] __ZN27AMDRadeonX4000_AMDHWChannel25alignCommandBufferAddressEj 0000000000080d64 l 0e SECT 01 0000 [.text] __ZN30AMDRadeonX4000_AMDSPUHWChannel20getIBAlignmentFactorEv 0000000000080d70 l 0e SECT 01 0000 [.text] __ZN30AMDRadeonX4000_AMDSPUHWChannel21getOneDwordNOPCommandEv 0000000000080d7c l 0e SECT 01 0000 [.text] __ZNK27AMDRadeonX4000_AMDHWChannel21writeSemaphoreCommandEPjyb 0000000000080d84 l 0e SECT 01 0000 [.text] __ZN27AMDRadeonX4000_AMDHWChannel7getNameEv 0000000000080d8e l 0e SECT 01 0000 [.text] __ZN27AMDRadeonX4000_AMDHWChannel19dumpEngineHangStateEb 0000000000080da8 l 0e SECT 01 0000 [.text] __ZN27AMDRadeonX4000_AMDHWChannel21writeProfilingCommandEPjyjb 0000000000080db0 l 0e SECT 01 0000 [.text] __ZN27AMDRadeonX4000_AMDHWChannel10engineTypeEv 0000000000080dc2 l 0e SECT 01 0000 [.text] __ZN27AMDRadeonX4000_AMDHWChannel18isDebugFlagEnabledEj 0000000000080dd6 l 0e SECT 01 0000 [.text] __ZN27AMDRadeonX4000_AMDHWChannel24getTimestampInterruptRefEv 0000000000080de0 l 0e SECT 01 0000 [.text] __ZN27AMDRadeonX4000_AMDHWChannel25getHWStatisticsGroupTableEv 0000000000080dee l 0e SECT 01 0000 [.text] __ZN27AMDRadeonX4000_AMDHWChannel23clearInterrupEnableFlagEv 0000000000080df8 l 0e SECT 01 0000 [.text] __ZN30AMDRadeonX4000_AMDSPUHWChannel22getIndirectCommandSizeEv 0000000000080e10 l 0e SECT 01 0000 [.text] __GLOBAL__I_a 0000000000080e50 l 0e SECT 01 0000 [.text] __GLOBAL__D_a 0000000000080ea2 l 0e SECT 01 0000 [.text] __ZN16AMDCIUVDHWEngine9MetaClassD1Ev 000000000008126e l 0e SECT 01 0000 [.text] __ZN27AMDRadeonX4000_IAMDHWEngine4initEv 0000000000081280 l 0e SECT 01 0000 [.text] __ZN16AMDCIUVDHWEngine4freeEv 0000000000081292 l 0e SECT 01 0000 [.text] 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[.text] __ZN29AMDRadeonX4000_AMDUVDHWEngine20getCurrentCapabilityEv 0000000000081312 l 0e SECT 01 0000 [.text] __ZN29AMDRadeonX4000_AMDUVDHWEngine14getHWRegistersEv 000000000008131c l 0e SECT 01 0000 [.text] __ZN29AMDRadeonX4000_AMDUVDHWEngine12getKeySelectEv 0000000000081328 l 0e SECT 01 0000 [.text] __ZN29AMDRadeonX4000_AMDUVDHWEngine15setDpmSupportedEb 0000000000081336 l 0e SECT 01 0000 [.text] __ZN16AMDCIUVDHWEngine9MetaClassD0Ev 0000000000081340 l 0e SECT 01 0000 [.text] __GLOBAL__I_a 0000000000081380 l 0e SECT 01 0000 [.text] __GLOBAL__D_a 00000000000813d2 l 0e SECT 01 0000 [.text] __ZN16AMDCIVCEHWEngine9MetaClassD1Ev 0000000000081a8c l 0e SECT 01 0000 [.text] __ZN16AMDCIVCEHWEngine9MetaClassD0Ev 0000000000081a96 l 0e SECT 01 0000 [.text] __ZN27AMDRadeonX4000_IAMDHWEngine4initEv 0000000000081aa8 l 0e SECT 01 0000 [.text] __ZN26AMDRadeonX4000_AMDHWEngine4typeEv 0000000000081ab2 l 0e SECT 01 0000 [.text] __ZN26AMDRadeonX4000_AMDHWEngine9isEnabledEv 0000000000081abc l 0e SECT 01 0000 [.text] __ZN26AMDRadeonX4000_AMDHWEngine20setVirtualSpaceReadyEb 0000000000081ac2 l 0e SECT 01 0000 [.text] __ZN29AMDRadeonX4000_AMDVCEHWEngine19initializeRegistersEv 0000000000081ac8 l 0e SECT 01 0000 [.text] __ZN29AMDRadeonX4000_AMDVCEHWEngine26systemWillChangeSpeedEventEv 0000000000081ace l 0e SECT 01 0000 [.text] __ZN29AMDRadeonX4000_AMDVCEHWEngine25systemDidChangeSpeedEventEv 0000000000081ad4 l 0e SECT 01 0000 [.text] __ZN29AMDRadeonX4000_AMDVCEHWEngine25alignCommandBufferAddressEj 0000000000081ae0 l 0e SECT 01 0000 [.text] __ZN26AMDRadeonX4000_AMDHWEngine10getVersionEj 0000000000081af0 l 0e SECT 01 0000 [.text] __ZN26AMDRadeonX4000_AMDHWEngine15getChannelCountEv 0000000000081afa l 0e SECT 01 0000 [.text] __ZN26AMDRadeonX4000_AMDHWEngine22getTimestampIRQSourcexE18_eAMD_HW_RING_TYPE 0000000000081b02 l 0e SECT 01 0000 [.text] __ZN26AMDRadeonX4000_AMDHWEngine14getFwvFunctionEv 0000000000081b0a l 0e SECT 01 0000 [.text] __ZN29AMDRadeonX4000_AMDVCEHWEngine18getTotalCapabilityEv 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0000000000081f66 l 0e SECT 01 0000 [.text] __ZN30AMDRadeonX4000_AMDVCEHWChannel20getIBAlignmentFactorEv 0000000000081f72 l 0e SECT 01 0000 [.text] __ZN30AMDRadeonX4000_AMDVCEHWChannel21getOneDwordNOPCommandEv 0000000000081f7a l 0e SECT 01 0000 [.text] __ZN27AMDRadeonX4000_AMDHWChannel7getNameEv 0000000000081f84 l 0e SECT 01 0000 [.text] __ZN27AMDRadeonX4000_AMDHWChannel19dumpEngineHangStateEb 0000000000081f9e l 0e SECT 01 0000 [.text] __ZN27AMDRadeonX4000_AMDHWChannel21writeProfilingCommandEPjyjb 0000000000081fa6 l 0e SECT 01 0000 [.text] __ZN27AMDRadeonX4000_AMDHWChannel10engineTypeEv 0000000000081fb8 l 0e SECT 01 0000 [.text] __ZN27AMDRadeonX4000_AMDHWChannel18isDebugFlagEnabledEj 0000000000081fcc l 0e SECT 01 0000 [.text] __ZN27AMDRadeonX4000_AMDHWChannel24getTimestampInterruptRefEv 0000000000081fd6 l 0e SECT 01 0000 [.text] __ZN27AMDRadeonX4000_AMDHWChannel25getHWStatisticsGroupTableEv 0000000000081fe4 l 0e SECT 01 0000 [.text] __ZN27AMDRadeonX4000_AMDHWChannel23clearInterrupEnableFlagEv 0000000000081ff0 l 0e SECT 01 0000 [.text] __GLOBAL__I_a 0000000000082030 l 0e SECT 01 0000 [.text] __GLOBAL__D_a 0000000000082082 l 0e SECT 01 0000 [.text] __ZN18AMDCIVCELLQChannel9MetaClassD1Ev 0000000000082212 l 0e SECT 01 0000 [.text] __ZN18AMDCIVCELLQChannel9MetaClassD0Ev 000000000008221c l 0e SECT 01 0000 [.text] __ZN28AMDRadeonX4000_IAMDHWChannel4initEv 000000000008222e l 0e SECT 01 0000 [.text] __ZN27AMDRadeonX4000_AMDHWChannel15getChannelIndexEv 0000000000082238 l 0e SECT 01 0000 [.text] __ZN27AMDRadeonX4000_AMDHWChannel18getChannelRingTypeEv 0000000000082254 l 0e SECT 01 0000 [.text] __ZN27AMDRadeonX4000_AMDHWChannel33initializeSubmitCommandBufferInfoEP30AMD_SUBMIT_COMMAND_BUFFER_INFO 000000000008226a l 0e SECT 01 0000 [.text] __ZN27AMDRadeonX4000_AMDHWChannel25alignCommandBufferAddressEj 0000000000082280 l 0e SECT 01 0000 [.text] __ZN30AMDRadeonX4000_AMDVCEHWChannel20getIBAlignmentFactorEv 000000000008228c l 0e SECT 01 0000 [.text] __ZN30AMDRadeonX4000_AMDVCEHWChannel21getOneDwordNOPCommandEv 0000000000082294 l 0e SECT 01 0000 [.text] __ZN27AMDRadeonX4000_AMDHWChannel7getNameEv 000000000008229e l 0e SECT 01 0000 [.text] __ZN27AMDRadeonX4000_AMDHWChannel19dumpEngineHangStateEb 00000000000822b8 l 0e SECT 01 0000 [.text] __ZN27AMDRadeonX4000_AMDHWChannel21writeProfilingCommandEPjyjb 00000000000822c0 l 0e SECT 01 0000 [.text] __ZN27AMDRadeonX4000_AMDHWChannel10engineTypeEv 00000000000822d2 l 0e SECT 01 0000 [.text] __ZN27AMDRadeonX4000_AMDHWChannel18isDebugFlagEnabledEj 00000000000822e6 l 0e SECT 01 0000 [.text] __ZN27AMDRadeonX4000_AMDHWChannel24getTimestampInterruptRefEv 00000000000822f0 l 0e SECT 01 0000 [.text] __ZN27AMDRadeonX4000_AMDHWChannel25getHWStatisticsGroupTableEv 00000000000822fe l 0e SECT 01 0000 [.text] __ZN27AMDRadeonX4000_AMDHWChannel23clearInterrupEnableFlagEv 0000000000082310 l 0e SECT 01 0000 [.text] __GLOBAL__I_a 0000000000082350 l 0e SECT 01 0000 [.text] __GLOBAL__D_a 00000000000823a2 l 0e SECT 01 0000 [.text] __ZN12AMDCIVCERing9MetaClassD1Ev 00000000000827cc l 0e SECT 01 0000 [.text] __ZN12AMDCIVCERing9MetaClassD0Ev 00000000000827d6 l 0e SECT 01 0000 [.text] __ZN25AMDRadeonX4000_IAMDHWRing4initEv 00000000000827e8 l 0e SECT 01 0000 [.text] __ZN24AMDRadeonX4000_AMDHWRing9isEnabledEv 00000000000827f2 l 0e SECT 01 0000 [.text] __ZN24AMDRadeonX4000_AMDHWRing7getTailEv 00000000000827fe l 0e SECT 01 0000 [.text] __ZN24AMDRadeonX4000_AMDHWRing12getFreeSpaceEv 000000000008282e l 0e SECT 01 0000 [.text] __ZN24AMDRadeonX4000_AMDHWRing7isEmptyEv 000000000008285c l 0e SECT 01 0000 [.text] __ZN24AMDRadeonX4000_AMDHWRing15getRingGartAddrEv 0000000000082866 l 0e SECT 01 0000 [.text] __ZN24AMDRadeonX4000_AMDHWRing7getSizeEv 0000000000082870 l 0e SECT 01 0000 [.text] __ZN24AMDRadeonX4000_AMDHWRing12getRingBlockEj 0000000000082882 l 0e SECT 01 0000 [.text] __ZN24AMDRadeonX4000_AMDHWRing11commitBlockEj 0000000000082892 l 0e SECT 01 0000 [.text] __ZN24AMDRadeonX4000_AMDHWRing9getRingIdEv 00000000000828a0 l 0e SECT 01 0000 [.text] __GLOBAL__I_a 00000000000828e0 l 0e SECT 01 0000 [.text] __GLOBAL__D_a 0000000000082932 l 0e SECT 01 0000 [.text] __ZN15AMDCIVCELLQRing9MetaClassD1Ev 0000000000082bba l 0e SECT 01 0000 [.text] __ZN15AMDCIVCELLQRing9MetaClassD0Ev 0000000000082bc4 l 0e SECT 01 0000 [.text] __ZN25AMDRadeonX4000_IAMDHWRing4initEv 0000000000082bd6 l 0e SECT 01 0000 [.text] __ZN24AMDRadeonX4000_AMDHWRing9isEnabledEv 0000000000082be0 l 0e SECT 01 0000 [.text] __ZN24AMDRadeonX4000_AMDHWRing7getTailEv 0000000000082bec l 0e SECT 01 0000 [.text] __ZN24AMDRadeonX4000_AMDHWRing12getFreeSpaceEv 0000000000082c1c l 0e SECT 01 0000 [.text] __ZN24AMDRadeonX4000_AMDHWRing7isEmptyEv 0000000000082c4a l 0e SECT 01 0000 [.text] __ZN24AMDRadeonX4000_AMDHWRing15getRingGartAddrEv 0000000000082c54 l 0e SECT 01 0000 [.text] __ZN24AMDRadeonX4000_AMDHWRing7getSizeEv 0000000000082c5e l 0e SECT 01 0000 [.text] __ZN24AMDRadeonX4000_AMDHWRing12getRingBlockEj 0000000000082c70 l 0e SECT 01 0000 [.text] __ZN24AMDRadeonX4000_AMDHWRing11commitBlockEj 0000000000082c80 l 0e SECT 01 0000 [.text] __ZN24AMDRadeonX4000_AMDHWRing9getRingIdEv 0000000000082c90 l 0e SECT 01 0000 [.text] __GLOBAL__I_a 0000000000082cd0 l 0e SECT 01 0000 [.text] __GLOBAL__D_a 0000000000082d22 l 0e SECT 01 0000 [.text] __ZN16AMDCIComputeRing9MetaClassD1Ev 0000000000083106 l 0e SECT 01 0000 [.text] __ZN16AMDCIComputeRing9MetaClassD0Ev 0000000000083110 l 0e SECT 01 0000 [.text] __ZN25AMDRadeonX4000_IAMDHWRing4initEv 0000000000083122 l 0e SECT 01 0000 [.text] __ZN24AMDRadeonX4000_AMDHWRing9isEnabledEv 000000000008312c l 0e SECT 01 0000 [.text] __ZN24AMDRadeonX4000_AMDHWRing7getHeadEv 000000000008313c l 0e SECT 01 0000 [.text] __ZN24AMDRadeonX4000_AMDHWRing7getTailEv 0000000000083148 l 0e SECT 01 0000 [.text] __ZN24AMDRadeonX4000_AMDHWRing12getFreeSpaceEv 0000000000083178 l 0e SECT 01 0000 [.text] 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l 0e SECT 01 0000 [.text] __ZN27AMDRadeonX4000_AMDHWChannel24getTimestampInterruptRefEv 0000000000083d8e l 0e SECT 01 0000 [.text] __ZN27AMDRadeonX4000_AMDHWChannel25getHWStatisticsGroupTableEv 0000000000083d9c l 0e SECT 01 0000 [.text] __ZN27AMDRadeonX4000_AMDHWChannel23clearInterrupEnableFlagEv 0000000000083da6 l 0e SECT 01 0000 [.text] __ZN27AMDRadeonX4000_AMDHWChannel22getIndirectCommandSizeEv 0000000000083db2 l 0e SECT 01 0000 [.text] __ZN30AMDRadeonX4000_AMDPM4HWChannel30enableScratchRegisterWritebackEv 0000000000083db8 l 0e SECT 01 0000 [.text] __ZN30AMDRadeonX4000_AMDPM4HWChannel31disableScratchRegisterWritebackEv 0000000000083dbe l 0e SECT 01 0000 [.text] __ZN22AMDCIPM4ComputeChannel19setupPerFramePacketEjjjj 0000000000083dc4 l 0e SECT 01 0000 [.text] __ZN22AMDCIPM4ComputeChannel19resetPerFramePacketEv 0000000000083dd0 l 0e SECT 01 0000 [.text] __GLOBAL__I_a 0000000000083e10 l 0e SECT 01 0000 [.text] __GLOBAL__D_a 0000000000083e62 l 0e SECT 01 0000 [.text] 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01 0000 [.text] __ZN26AMDRadeonX4000_AMDHWMemory12getTotalSizeEv 0000000000087cae l 0e SECT 01 0000 [.text] __ZN26AMDRadeonX4000_AMDHWMemory14getVisibleSizeEv 0000000000087cb8 l 0e SECT 01 0000 [.text] __ZN26AMDRadeonX4000_AMDHWMemory16getInvisibleSizeEv 0000000000087cc6 l 0e SECT 01 0000 [.text] __ZN26AMDRadeonX4000_AMDHWMemory24isNonVisibleMemoryExistsEv 0000000000087ce0 l 0e SECT 01 0000 [.text] __GLOBAL__I_a 0000000000087d20 l 0e SECT 01 0000 [.text] __GLOBAL__D_a 0000000000087d72 l 0e SECT 01 0000 [.text] __ZN14AMDVIVMContext9MetaClassD1Ev 00000000000890c8 l 0e SECT 01 0000 [.text] __ZN14AMDVIVMContext9MetaClassD0Ev 00000000000890d2 l 0e SECT 01 0000 [.text] __ZN30AMDRadeonX4000_IAMDHWVMContext4initEv 00000000000890e4 l 0e SECT 01 0000 [.text] __ZN29AMDRadeonX4000_AMDHWVMContext10mapLocalVAEyyy 000000000008910a l 0e SECT 01 0000 [.text] __ZN29AMDRadeonX4000_AMDHWVMContext11mapSystemVAEyP18IOMemoryDescriptor 0000000000089134 l 0e SECT 01 0000 [.text] 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0e SECT 01 0000 [.text] __ZN23AMDRadeonX4000_AMDHWVMM21getVMPTVirtualAddressEy 0000000000089638 l 0e SECT 01 0000 [.text] __ZN23AMDRadeonX4000_AMDHWVMM15getVMRangeStartEv 0000000000089642 l 0e SECT 01 0000 [.text] __ZN23AMDRadeonX4000_AMDHWVMM13getVMRangeEndEv 0000000000089650 l 0e SECT 01 0000 [.text] __ZN23AMDRadeonX4000_AMDHWVMM16getVMPTBCoverageEv 000000000008965e l 0e SECT 01 0000 [.text] __ZN23AMDRadeonX4000_AMDHWVMM16getVMPTBVRAMSizeEv 000000000008966c l 0e SECT 01 0000 [.text] __ZN23AMDRadeonX4000_AMDHWVMM16getVMPTDVRAMSizeEv 000000000008967a l 0e SECT 01 0000 [.text] __ZN23AMDRadeonX4000_AMDHWVMM13getVMPTBTotalEv 0000000000089688 l 0e SECT 01 0000 [.text] __ZN23AMDRadeonX4000_AMDHWVMM14getVMPTBPerPTBEv 0000000000089696 l 0e SECT 01 0000 [.text] __ZN8AMDVIVMM10getMinVMIDEv 00000000000896a2 l 0e SECT 01 0000 [.text] __ZN8AMDVIVMM10getMaxVMIDEv 00000000000896ae l 0e SECT 01 0000 [.text] __ZN23AMDRadeonX4000_AMDHWVMM19getFragmentStrategyEv 00000000000896ba l 0e SECT 01 0000 [.text] __ZN23AMDRadeonX4000_AMDHWVMM12getBIGKValueEv 00000000000896c6 l 0e SECT 01 0000 [.text] __ZN23AMDRadeonX4000_AMDHWVMM14getBIGKInBytesEv 00000000000896d2 l 0e SECT 01 0000 [.text] __ZN23AMDRadeonX4000_AMDHWVMM20getFragmentAlignmentEv 00000000000896e0 l 0e SECT 01 0000 [.text] __GLOBAL__I_a 0000000000089720 l 0e SECT 01 0000 [.text] __GLOBAL__D_a 0000000000089772 l 0e SECT 01 0000 [.text] __ZN12AMDVIDisplay9MetaClassD1Ev 000000000008b184 l 0e SECT 01 0000 [.text] __ZN12AMDVIDisplay9MetaClassD0Ev 000000000008b18e l 0e SECT 01 0000 [.text] __ZN27AMDRadeonX4000_AMDHWDisplay10getBuiltInEj 000000000008b1aa l 0e SECT 01 0000 [.text] __ZN27AMDRadeonX4000_AMDHWDisplay16getBuiltInExistsEv 000000000008b1b8 l 0e SECT 01 0000 [.text] __ZN27AMDRadeonX4000_AMDHWDisplay13getInterlacedEj 000000000008b1d2 l 0e SECT 01 0000 [.text] __ZN27AMDRadeonX4000_AMDHWDisplay20setFullScreenEnabledEjb 000000000008b1f6 l 0e SECT 01 0000 [.text] __ZN27AMDRadeonX4000_AMDHWDisplay20getFullScreenEnabledEj 000000000008b212 l 0e SECT 01 0000 [.text] __ZN12AMDVIDisplay28getNumberOfSupportedDisplaysEv 000000000008b21e l 0e SECT 01 0000 [.text] __ZN27AMDRadeonX4000_AMDHWDisplay13isFEDSEnabledEv 000000000008b22c l 0e SECT 01 0000 [.text] __ZN27AMDRadeonX4000_AMDHWDisplay13isFEDSEnabledEj 000000000008b248 l 0e SECT 01 0000 [.text] __ZN27AMDRadeonX4000_AMDHWDisplay17FEDSIsColorBufferEj 000000000008b260 l 0e SECT 01 0000 [.text] __ZN27AMDRadeonX4000_AMDHWDisplay20FEDSSetIsColorBufferEjj 000000000008b278 l 0e SECT 01 0000 [.text] __ZN27AMDRadeonX4000_AMDHWDisplay27isAnyDisplayModeAccelBackedEv 000000000008b284 l 0e SECT 01 0000 [.text] __ZN27AMDRadeonX4000_AMDHWDisplay24isDisplayModeAccelBackedEj 000000000008b29e l 0e SECT 01 0000 [.text] __ZN27AMDRadeonX4000_AMDHWDisplay14getScalerFlagsEj 000000000008b2c0 l 0e SECT 01 0000 [.text] __ZN27AMDRadeonX4000_AMDHWDisplay14isScaledNeededEv 000000000008b308 l 0e SECT 01 0000 [.text] __ZN27AMDRadeonX4000_AMDHWDisplay14isScaledNeededEj 000000000008b328 l 0e SECT 01 0000 [.text] __ZN27AMDRadeonX4000_AMDHWDisplay14isFedsRequiredEv 000000000008b370 l 0e SECT 01 0000 [.text] __ZN27AMDRadeonX4000_AMDHWDisplay14isFedsRequiredEj 000000000008b3a6 l 0e SECT 01 0000 [.text] __ZNK27AMDRadeonX4000_AMDHWDisplay16getFedsParamInfoEv 000000000008b3b0 l 0e SECT 01 0000 [.text] __ZN27AMDRadeonX4000_AMDHWDisplay17isFEDSBufferDirtyEj 000000000008b3d0 l 0e SECT 01 0000 [.text] __GLOBAL__I_a 000000000008b410 l 0e SECT 01 0000 [.text] __GLOBAL__D_a 000000000008b462 l 0e SECT 01 0000 [.text] __ZN16AMDVIHWUtilities9MetaClassD1Ev 000000000008b734 l 0e SECT 01 0000 [.text] __ZN16AMDVIHWUtilities9MetaClassD0Ev 000000000008b73e l 0e SECT 01 0000 [.text] __ZN30AMDRadeonX4000_IAMDHWUtilities4initEv 000000000008b750 l 0e SECT 01 0000 [.text] __GLOBAL__I_a 000000000008b790 l 0e SECT 01 0000 [.text] __GLOBAL__D_a 000000000008b7e2 l 0e SECT 01 0000 [.text] __ZN16AMDVIsDMAChannel9MetaClassD1Ev 000000000008c4ea l 0e SECT 01 0000 [.text] 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0e SECT 01 0000 [.text] __ZN27AMDRadeonX4000_AMDHWChannel19dumpEngineHangStateEb 000000000008ee2c l 0e SECT 01 0000 [.text] __ZN27AMDRadeonX4000_AMDHWChannel10engineTypeEv 000000000008ee3e l 0e SECT 01 0000 [.text] __ZN27AMDRadeonX4000_AMDHWChannel18isDebugFlagEnabledEj 000000000008ee52 l 0e SECT 01 0000 [.text] __ZN27AMDRadeonX4000_AMDHWChannel24getTimestampInterruptRefEv 000000000008ee5c l 0e SECT 01 0000 [.text] __ZN27AMDRadeonX4000_AMDHWChannel25getHWStatisticsGroupTableEv 000000000008ee6a l 0e SECT 01 0000 [.text] __ZN27AMDRadeonX4000_AMDHWChannel23clearInterrupEnableFlagEv 000000000008ee74 l 0e SECT 01 0000 [.text] __ZN27AMDRadeonX4000_AMDHWChannel22getIndirectCommandSizeEv 000000000008ee80 l 0e SECT 01 0000 [.text] __ZN30AMDRadeonX4000_AMDPM4HWChannel30enableScratchRegisterWritebackEv 000000000008ee86 l 0e SECT 01 0000 [.text] __ZN30AMDRadeonX4000_AMDPM4HWChannel31disableScratchRegisterWritebackEv 000000000008ee8c l 0e SECT 01 0000 [.text] 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0000000000092134 l 0e SECT 01 0000 [.text] __ZN22AMDVIPM4ComputeChannel9MetaClassD0Ev 000000000009213e l 0e SECT 01 0000 [.text] __ZN28AMDRadeonX4000_IAMDHWChannel4initEv 0000000000092150 l 0e SECT 01 0000 [.text] __ZN27AMDRadeonX4000_AMDHWChannel15getChannelIndexEv 000000000009215a l 0e SECT 01 0000 [.text] __ZN27AMDRadeonX4000_AMDHWChannel18getChannelRingTypeEv 0000000000092176 l 0e SECT 01 0000 [.text] __ZN27AMDRadeonX4000_AMDHWChannel33initializeSubmitCommandBufferInfoEP30AMD_SUBMIT_COMMAND_BUFFER_INFO 000000000009218c l 0e SECT 01 0000 [.text] __ZN27AMDRadeonX4000_AMDHWChannel25alignCommandBufferAddressEj 00000000000921a2 l 0e SECT 01 0000 [.text] __ZN22AMDVIPM4ComputeChannel20getIBAlignmentFactorEv 00000000000921ae l 0e SECT 01 0000 [.text] __ZN22AMDVIPM4ComputeChannel21getOneDwordNOPCommandEv 00000000000921ba l 0e SECT 01 0000 [.text] __ZN27AMDRadeonX4000_AMDHWChannel7getNameEv 00000000000921c4 l 0e SECT 01 0000 [.text] __ZN27AMDRadeonX4000_AMDHWChannel19dumpEngineHangStateEb 00000000000921de l 0e SECT 01 0000 [.text] __ZN27AMDRadeonX4000_AMDHWChannel21writeProfilingCommandEPjyjb 00000000000921e6 l 0e SECT 01 0000 [.text] __ZN27AMDRadeonX4000_AMDHWChannel10engineTypeEv 00000000000921f8 l 0e SECT 01 0000 [.text] __ZN27AMDRadeonX4000_AMDHWChannel18isDebugFlagEnabledEj 000000000009220c l 0e SECT 01 0000 [.text] __ZN27AMDRadeonX4000_AMDHWChannel24getTimestampInterruptRefEv 0000000000092216 l 0e SECT 01 0000 [.text] __ZN27AMDRadeonX4000_AMDHWChannel25getHWStatisticsGroupTableEv 0000000000092224 l 0e SECT 01 0000 [.text] __ZN27AMDRadeonX4000_AMDHWChannel23clearInterrupEnableFlagEv 000000000009222e l 0e SECT 01 0000 [.text] __ZN27AMDRadeonX4000_AMDHWChannel22getIndirectCommandSizeEv 000000000009223a l 0e SECT 01 0000 [.text] __ZN30AMDRadeonX4000_AMDPM4HWChannel30enableScratchRegisterWritebackEv 0000000000092240 l 0e SECT 01 0000 [.text] __ZN30AMDRadeonX4000_AMDPM4HWChannel31disableScratchRegisterWritebackEv 0000000000092246 l 0e SECT 01 0000 [.text] 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00000000000926b0 l 0e SECT 01 0000 [.text] __ZN29AMDRadeonX4000_AMDSPUHWEngine25systemDidChangeSpeedEventEv 00000000000926b6 l 0e SECT 01 0000 [.text] __ZN29AMDRadeonX4000_AMDSPUHWEngine25alignCommandBufferAddressEj 00000000000926c8 l 0e SECT 01 0000 [.text] __ZN26AMDRadeonX4000_AMDHWEngine10getVersionEj 00000000000926d8 l 0e SECT 01 0000 [.text] __ZN26AMDRadeonX4000_AMDHWEngine15getChannelCountEv 00000000000926e2 l 0e SECT 01 0000 [.text] __ZN26AMDRadeonX4000_AMDHWEngine22getTimestampIRQSourcexE18_eAMD_HW_RING_TYPE 00000000000926ea l 0e SECT 01 0000 [.text] __ZN26AMDRadeonX4000_AMDHWEngine14getFwvFunctionEv 0000000000092700 l 0e SECT 01 0000 [.text] __GLOBAL__I_a 0000000000092740 l 0e SECT 01 0000 [.text] __GLOBAL__D_a 0000000000092792 l 0e SECT 01 0000 [.text] __ZN16AMDVISAMURBIRing9MetaClassD1Ev 0000000000092a7c l 0e SECT 01 0000 [.text] __ZN16AMDVISAMURBIRing9MetaClassD0Ev 0000000000092a86 l 0e SECT 01 0000 [.text] __ZN25AMDRadeonX4000_IAMDHWRing4initEv 0000000000092a98 l 0e SECT 01 0000 [.text] __ZN24AMDRadeonX4000_AMDHWRing9isEnabledEv 0000000000092aa2 l 0e SECT 01 0000 [.text] __ZN24AMDRadeonX4000_AMDHWRing7isEmptyEv 0000000000092ad0 l 0e SECT 01 0000 [.text] __ZN24AMDRadeonX4000_AMDHWRing15getRingGartAddrEv 0000000000092ada l 0e SECT 01 0000 [.text] __ZN24AMDRadeonX4000_AMDHWRing7getSizeEv 0000000000092ae4 l 0e SECT 01 0000 [.text] __ZN24AMDRadeonX4000_AMDHWRing12getRingBlockEj 0000000000092af6 l 0e SECT 01 0000 [.text] __ZN24AMDRadeonX4000_AMDHWRing9getRingIdEv 0000000000092b10 l 0e SECT 01 0000 [.text] __GLOBAL__I_a 0000000000092b50 l 0e SECT 01 0000 [.text] __GLOBAL__D_a 0000000000092ba2 l 0e SECT 01 0000 [.text] __ZN19AMDVISAMURBIChannel9MetaClassD1Ev 0000000000092d26 l 0e SECT 01 0000 [.text] __ZN19AMDVISAMURBIChannel9MetaClassD0Ev 0000000000092d30 l 0e SECT 01 0000 [.text] __ZN28AMDRadeonX4000_IAMDHWChannel4initEv 0000000000092d42 l 0e SECT 01 0000 [.text] __ZN27AMDRadeonX4000_AMDHWChannel15getChannelIndexEv 0000000000092d4c l 0e SECT 01 0000 [.text] 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__ZN27AMDRadeonX4000_AMDHWChannel10engineTypeEv 0000000000092df2 l 0e SECT 01 0000 [.text] __ZN27AMDRadeonX4000_AMDHWChannel18isDebugFlagEnabledEj 0000000000092e06 l 0e SECT 01 0000 [.text] __ZN27AMDRadeonX4000_AMDHWChannel24getTimestampInterruptRefEv 0000000000092e10 l 0e SECT 01 0000 [.text] __ZN27AMDRadeonX4000_AMDHWChannel25getHWStatisticsGroupTableEv 0000000000092e1e l 0e SECT 01 0000 [.text] __ZN27AMDRadeonX4000_AMDHWChannel23clearInterrupEnableFlagEv 0000000000092e28 l 0e SECT 01 0000 [.text] __ZN30AMDRadeonX4000_AMDSPUHWChannel22getIndirectCommandSizeEv 0000000000092e40 l 0e SECT 01 0000 [.text] __GLOBAL__I_a 0000000000092e80 l 0e SECT 01 0000 [.text] __GLOBAL__D_a 0000000000092ed2 l 0e SECT 01 0000 [.text] __ZN18AMDVISAMUGPCOMRing9MetaClassD1Ev 0000000000093248 l 0e SECT 01 0000 [.text] __ZN18AMDVISAMUGPCOMRing9MetaClassD0Ev 0000000000093252 l 0e SECT 01 0000 [.text] __ZN25AMDRadeonX4000_IAMDHWRing4initEv 0000000000093264 l 0e SECT 01 0000 [.text] __ZN24AMDRadeonX4000_AMDHWRing9isEnabledEv 000000000009326e l 0e SECT 01 0000 [.text] __ZN24AMDRadeonX4000_AMDHWRing7getTailEv 000000000009327a l 0e SECT 01 0000 [.text] __ZN24AMDRadeonX4000_AMDHWRing12getFreeSpaceEv 00000000000932aa l 0e SECT 01 0000 [.text] __ZN24AMDRadeonX4000_AMDHWRing7isEmptyEv 00000000000932d8 l 0e SECT 01 0000 [.text] __ZN24AMDRadeonX4000_AMDHWRing15getRingGartAddrEv 00000000000932e2 l 0e SECT 01 0000 [.text] __ZN24AMDRadeonX4000_AMDHWRing7getSizeEv 00000000000932ec l 0e SECT 01 0000 [.text] __ZN24AMDRadeonX4000_AMDHWRing12getRingBlockEj 00000000000932fe l 0e SECT 01 0000 [.text] __ZN24AMDRadeonX4000_AMDHWRing9getRingIdEv 000000000009330a l 0e SECT 01 0000 [.text] __ZN18AMDCISAMUGPCOMRing15getFeedbackAddrEv 0000000000093318 l 0e SECT 01 0000 [.text] __ZN18AMDCISAMUGPCOMRing18getFeedbackBufSizeEv 0000000000093330 l 0e SECT 01 0000 [.text] __GLOBAL__I_a 0000000000093370 l 0e SECT 01 0000 [.text] __GLOBAL__D_a 00000000000933c2 l 0e SECT 01 0000 [.text] __ZN21AMDVISAMUGPCOMChannel9MetaClassD1Ev 0000000000093546 l 0e SECT 01 0000 [.text] __ZN21AMDVISAMUGPCOMChannel9MetaClassD0Ev 0000000000093550 l 0e SECT 01 0000 [.text] __ZN28AMDRadeonX4000_IAMDHWChannel4initEv 0000000000093562 l 0e SECT 01 0000 [.text] __ZN27AMDRadeonX4000_AMDHWChannel15getChannelIndexEv 000000000009356c l 0e SECT 01 0000 [.text] __ZN27AMDRadeonX4000_AMDHWChannel18getChannelRingTypeEv 0000000000093588 l 0e SECT 01 0000 [.text] __ZN27AMDRadeonX4000_AMDHWChannel33initializeSubmitCommandBufferInfoEP30AMD_SUBMIT_COMMAND_BUFFER_INFO 000000000009359e l 0e SECT 01 0000 [.text] __ZN27AMDRadeonX4000_AMDHWChannel25alignCommandBufferAddressEj 00000000000935b4 l 0e SECT 01 0000 [.text] __ZN30AMDRadeonX4000_AMDSPUHWChannel20getIBAlignmentFactorEv 00000000000935c0 l 0e SECT 01 0000 [.text] __ZN30AMDRadeonX4000_AMDSPUHWChannel21getOneDwordNOPCommandEv 00000000000935cc l 0e SECT 01 0000 [.text] __ZNK27AMDRadeonX4000_AMDHWChannel21writeSemaphoreCommandEPjyb 00000000000935d4 l 0e SECT 01 0000 [.text] __ZN27AMDRadeonX4000_AMDHWChannel7getNameEv 00000000000935de l 0e SECT 01 0000 [.text] __ZN27AMDRadeonX4000_AMDHWChannel19dumpEngineHangStateEb 00000000000935f8 l 0e SECT 01 0000 [.text] __ZN27AMDRadeonX4000_AMDHWChannel21writeProfilingCommandEPjyjb 0000000000093600 l 0e SECT 01 0000 [.text] __ZN27AMDRadeonX4000_AMDHWChannel10engineTypeEv 0000000000093612 l 0e SECT 01 0000 [.text] __ZN27AMDRadeonX4000_AMDHWChannel18isDebugFlagEnabledEj 0000000000093626 l 0e SECT 01 0000 [.text] __ZN27AMDRadeonX4000_AMDHWChannel24getTimestampInterruptRefEv 0000000000093630 l 0e SECT 01 0000 [.text] __ZN27AMDRadeonX4000_AMDHWChannel25getHWStatisticsGroupTableEv 000000000009363e l 0e SECT 01 0000 [.text] __ZN27AMDRadeonX4000_AMDHWChannel23clearInterrupEnableFlagEv 0000000000093648 l 0e SECT 01 0000 [.text] __ZN30AMDRadeonX4000_AMDSPUHWChannel22getIndirectCommandSizeEv 0000000000093660 l 0e SECT 01 0000 [.text] __GLOBAL__I_a 00000000000936a0 l 0e SECT 01 0000 [.text] __GLOBAL__D_a 000000000009496c l 0e SECT 01 0000 [.text] _shl 0000000000094b78 g 1e SECT 01 0000 [.text] __start 0000000000094b92 g 1e SECT 01 0000 [.text] _OSKextGetCurrentIdentifier 0000000000094ba3 g 1e SECT 01 0000 [.text] _OSKextGetCurrentVersionString 0000000000094bb4 g 1e SECT 01 0000 [.text] _OSKextGetCurrentLoadTag 0000000000094bc4 g 1e SECT 01 0000 [.text] __stop 000000000009844c l 0e SECT 01 0000 [.text] __ZN10AuxSurfMgrD1Ev 0000000000098456 l 0e SECT 01 0000 [.text] __ZN10AuxSurfMgrD0Ev 0000000000098472 l 0e SECT 01 0000 [.text] __ZN10AuxSurfMgr27HwlRequiresHTileMappingSurfEv 000000000009847a l 0e SECT 01 0000 [.text] __ZN10AuxSurfMgr21HwlInitCmaskAsTexSurfEPK13_UBM_SURFINFOP13CachedAuxSurf 0000000000098486 l 0e SECT 01 0000 [.text] __ZN10AuxSurfMgr24HwlDestroyCmaskAsTexSurfEP13CachedAuxSurf 000000000009848c l 0e SECT 01 0000 [.text] __ZN10AuxSurfMgr21HwlInitFmaskAsTexSurfEPK13_UBM_SURFINFOP13CachedAuxSurf 0000000000098498 l 0e SECT 01 0000 [.text] __ZN10AuxSurfMgr24HwlDestroyFmaskAsTexSurfEP13CachedAuxSurf 000000000009849e l 0e SECT 01 0000 [.text] __ZN10AuxSurfMgr20HwlInitOffsetTexSurfEPK13_UBM_SURFINFOP13CachedAuxSurf 00000000000984aa l 0e SECT 01 0000 [.text] __ZN10AuxSurfMgr23HwlDestroyOffsetTexSurfEP13CachedAuxSurf 00000000000984b0 l 0e SECT 01 0000 [.text] __ZN10AuxSurfMgr23HwlInitHtileAsColorSurfEPK13_UBM_SURFINFOP13CachedAuxSurf 00000000000984bc l 0e SECT 01 0000 [.text] __ZN10AuxSurfMgr26HwlDestroyHtileAsColorSurfEP13CachedAuxSurf 00000000000984c2 l 0e SECT 01 0000 [.text] __ZN10AuxSurfMgr14HwlInitHiSSurfEPK13_UBM_SURFINFOP13CachedAuxSurf 00000000000984ce l 0e SECT 01 0000 [.text] __ZN10AuxSurfMgr17HwlDestroyHiSSurfEP13CachedAuxSurf 00000000000984d4 l 0e SECT 01 0000 [.text] __ZN10AuxSurfMgr23HwlInitNeighborMaskSurfEPK13_UBM_SURFINFOP13CachedAuxSurf 00000000000984e0 l 0e SECT 01 0000 [.text] __ZN10AuxSurfMgr26HwlDestroyNeighborMaskSurfEP13CachedAuxSurf 00000000000984e6 l 0e SECT 01 0000 [.text] __ZN10AuxSurfMgr19HwlInitEdgeMaskSurfEPK13_UBM_SURFINFOP13CachedAuxSurf 00000000000984f2 l 0e SECT 01 0000 [.text] __ZN10AuxSurfMgr22HwlDestroyEdgeMaskSurfEP13CachedAuxSurf 00000000000984f8 l 0e SECT 01 0000 [.text] __ZN10AuxSurfMgr17HwlInitPixPreSurfEPK13_UBM_SURFINFOP13CachedAuxSurf 0000000000098504 l 0e SECT 01 0000 [.text] __ZN10AuxSurfMgr20HwlDestroyPixPreSurfEP13CachedAuxSurf 000000000009850a l 0e SECT 01 0000 [.text] __ZN10AuxSurfMgr15HwlInitGradSurfEPK13_UBM_SURFINFOP13CachedAuxSurf 0000000000098516 l 0e SECT 01 0000 [.text] __ZN10AuxSurfMgr18HwlDestroyGradSurfEP13CachedAuxSurf 000000000009851c l 0e SECT 01 0000 [.text] __ZN10AuxSurfMgr21HwlInitAdvAaDepthSurfEPK13_UBM_SURFINFOP13CachedAuxSurf 0000000000098528 l 0e SECT 01 0000 [.text] __ZN10AuxSurfMgr24HwlDestroyAdvAaDepthSurfEP13CachedAuxSurf 000000000009852e l 0e SECT 01 0000 [.text] __ZN10AuxSurfMgr22HwlInitMlaaSepEdgeSurfEPK13_UBM_SURFINFOP13CachedAuxSurf 000000000009853a l 0e SECT 01 0000 [.text] __ZN10AuxSurfMgr25HwlDestroyMlaaSepEdgeSurfEP13CachedAuxSurf 0000000000098540 l 0e SECT 01 0000 [.text] __ZN10AuxSurfMgr24HwlInitMlaaEdgeCountSurfEPK13_UBM_SURFINFOP13CachedAuxSurf21MlaaEdgeCountSurfDesc 000000000009854c l 0e SECT 01 0000 [.text] __ZN10AuxSurfMgr27HwlDestroyMlaaEdgeCountSurfEP13CachedAuxSurf 0000000000098552 l 0e SECT 01 0000 [.text] __ZN10AuxSurfMgr22HwlInitHTileOffsetSurfEPK13_UBM_SURFINFOS2_P13CachedAuxSurf 000000000009855e l 0e SECT 01 0000 [.text] __ZN10AuxSurfMgr25HwlDestroyHTileOffsetSurfEP13CachedAuxSurf 0000000000098564 l 0e SECT 01 0000 [.text] __ZN10AuxSurfMgr23HwlInitHTileMappingSurfEPK13_UBM_SURFINFOS2_P13CachedAuxSurf 0000000000098570 l 0e SECT 01 0000 [.text] __ZN10AuxSurfMgr26HwlDestroyHTileMappingSurfEP13CachedAuxSurf 0000000000098722 l 0e SECT 01 0000 [.text] __ZN9BltDeviceD1Ev 000000000009872c l 0e SECT 01 0000 [.text] __ZN9BltDeviceD0Ev 0000000000098748 l 0e SECT 01 0000 [.text] __ZN9BltDevice7HwlInitEPK15_UBM_DEVICEINFO 0000000000098750 l 0e SECT 01 0000 [.text] __ZN9BltDevice7HwlTrimEv 0000000000098758 l 0e SECT 01 0000 [.text] __ZN9BltDevice10HwlDestroyEv 0000000000098760 l 0e SECT 01 0000 [.text] __ZN9BltDevice25HwlNotifyShadowMemoryInfoEP26_UBM_STATESHADOWMEMORYINFO 000000000009876c l 0e SECT 01 0000 [.text] __ZN9BltDevice17HwlClearStateInitEv 0000000000098778 l 0e SECT 01 0000 [.text] __ZN9BltDevice19HwlComputeStateInitEv 000000000009ff84 l 0e SECT 01 0000 [.text] __ZN6BltMgr22HwlGetShadowMemorySizeEv 000000000009ff8c l 0e SECT 01 0000 [.text] __ZN6BltMgr7HwlInitEv 000000000009ff94 l 0e SECT 01 0000 [.text] __ZN6BltMgr7HwlTrimEv 000000000009ff9c l 0e SECT 01 0000 [.text] __ZN6BltMgr10HwlDestroyEv 000000000009ffa4 l 0e SECT 01 0000 [.text] __ZN6BltMgr14HwlInitBltInfoEP7BltInfo 000000000009ffaa l 0e SECT 01 0000 [.text] __ZN6BltMgr17HwlGpuLoadShadersEP9BltDevice 000000000009ffb6 l 0e SECT 01 0000 [.text] __ZN6BltMgr22HwlCreateHtileSurfInfoEP13_UBM_SURFINFOS1_ 000000000009ffbc l 0e SECT 01 0000 [.text] __ZN6BltMgr36HwlIsCompressedDepthResolveSupportedEP7BltInfo 000000000009ffc4 l 0e SECT 01 0000 [.text] __ZN6BltMgr29HwlIsOptimizedYuvBltSupportedEPK13_UBM_SURFINFOj 000000000009ffcc l 0e SECT 01 0000 [.text] __ZN6BltMgr24HwlGetHtileCopyBltEngineEv 00000000000a72e4 l 0e SECT 01 0000 [.text] __ZN9BltShaderD1Ev 00000000000a72ee l 0e SECT 01 0000 [.text] __ZN9BltShaderD0Ev 00000000000a730a l 0e SECT 01 0000 [.text] __ZN9BltShader7GpuLoadEP9BltDevicePv13LARGE_INTEGER 00000000000a7310 l 0e SECT 01 0000 [.text] __ZNK9BltShader16GetShaderMemSizeEv 00000000000a731a l 0e SECT 01 0000 [.text] __ZNK9BltShader23GetRoundedShaderMemSizeEv 00000000000a7586 l 0e SECT 01 0000 [.text] __ZN15ShaderVidMemMgr21GpuLoadInitialShadersEP9BltDevice 00000000000a7592 l 0e SECT 01 0000 [.text] __ZN15ShaderVidMemMgr16GetComputeShaderEj 00000000000a759a l 0e SECT 01 0000 [.text] __ZN15ShaderVidMemMgr17GpuLoadAllShadersEP9BltDevice 00000000000a75a6 l 0e SECT 01 0000 [.text] __ZNK15ShaderVidMemMgr18HwlVidMemAllocInfoEP22_UBM_ALLOCVIDMEM_INPUT 00000000000a7784 l 0e SECT 01 0000 [.text] __ZNK13SurfAttribute11GetTileModeEPK13_UBM_SURFINFO 00000000000a7790 l 0e SECT 01 0000 [.text] __ZNK13SurfAttribute11GetTileTypeEPK13_UBM_SURFINFO 00000000000a779c l 0e SECT 01 0000 [.text] __ZNK13SurfAttribute25GetLinearAlignedTileIndexEv 00000000000a77a8 l 0e SECT 01 0000 [.text] __ZNK13SurfAttribute33GetLinearAlignedSurfacePitchAlignEj 00000000000a77b0 l 0e SECT 01 0000 [.text] __ZNK13SurfAttribute33GetLinearAlignedSurfaceSliceAlignEj 00000000000a77b8 l 0e SECT 01 0000 [.text] __ZNK13SurfAttribute21GetMacroTileDimensionEjPjS0_ 00000000000aacb4 l 0e SECT 01 0000 [.text] __ZN15SiBltAuxSurfMgrD1Ev 00000000000aacbe l 0e SECT 01 0000 [.text] __ZN15SiBltAuxSurfMgrD0Ev 00000000000aacda l 0e SECT 01 0000 [.text] __ZN10AuxSurfMgr27HwlRequiresHTileMappingSurfEv 00000000000aace2 l 0e SECT 01 0000 [.text] __ZN15SiBltAuxSurfMgr24HwlDestroyCmaskAsTexSurfEP13CachedAuxSurf 00000000000aace8 l 0e SECT 01 0000 [.text] __ZN15SiBltAuxSurfMgr24HwlDestroyFmaskAsTexSurfEP13CachedAuxSurf 00000000000aacee l 0e SECT 01 0000 [.text] __ZN15SiBltAuxSurfMgr26HwlDestroyHtileAsColorSurfEP13CachedAuxSurf 00000000000aacf4 l 0e SECT 01 0000 [.text] __ZN15SiBltAuxSurfMgr17HwlDestroyHiSSurfEP13CachedAuxSurf 00000000000aacfa l 0e SECT 01 0000 [.text] __ZN15SiBltAuxSurfMgr26HwlDestroyNeighborMaskSurfEP13CachedAuxSurf 00000000000aad00 l 0e SECT 01 0000 [.text] __ZN15SiBltAuxSurfMgr22HwlDestroyEdgeMaskSurfEP13CachedAuxSurf 00000000000aad06 l 0e SECT 01 0000 [.text] __ZN15SiBltAuxSurfMgr20HwlDestroyPixPreSurfEP13CachedAuxSurf 00000000000aad0c l 0e SECT 01 0000 [.text] __ZN15SiBltAuxSurfMgr18HwlDestroyGradSurfEP13CachedAuxSurf 00000000000aad12 l 0e SECT 01 0000 [.text] __ZN15SiBltAuxSurfMgr24HwlDestroyAdvAaDepthSurfEP13CachedAuxSurf 00000000000aad18 l 0e SECT 01 0000 [.text] __ZN15SiBltAuxSurfMgr25HwlDestroyMlaaSepEdgeSurfEP13CachedAuxSurf 00000000000aad1e l 0e SECT 01 0000 [.text] __ZN15SiBltAuxSurfMgr27HwlDestroyMlaaEdgeCountSurfEP13CachedAuxSurf 00000000000aad24 l 0e SECT 01 0000 [.text] __ZN10AuxSurfMgr23HwlInitHTileMappingSurfEPK13_UBM_SURFINFOS2_P13CachedAuxSurf 00000000000aad30 l 0e SECT 01 0000 [.text] __ZN10AuxSurfMgr26HwlDestroyHTileMappingSurfEP13CachedAuxSurf 00000000000b21aa l 0e SECT 01 0000 [.text] __ZN11SiBltDevice17HwlClearStateInitEv 00000000000b21b6 l 0e SECT 01 0000 [.text] __ZN9BltDevice19HwlComputeStateInitEv 00000000000b6552 l 0e SECT 01 0000 [.text] __ZN6BltMgr7HwlTrimEv 00000000000b655a l 0e SECT 01 0000 [.text] __ZNK8SiBltMgr20HwlGetMaxWidthHeightEv 00000000000b6566 l 0e SECT 01 0000 [.text] __ZN8SiBltMgr24HwlGetHtileCopyBltEngineEv 00000000000bc20c l 0e SECT 01 0000 [.text] __ZN16SiBltPixelShaderD1Ev 00000000000bc216 l 0e SECT 01 0000 [.text] __ZN16SiBltPixelShaderD0Ev 00000000000bdd24 l 0e SECT 01 0000 [.text] __ZN11SiBltShaderD1Ev 00000000000bdd2e l 0e SECT 01 0000 [.text] __ZN11SiBltShaderD0Ev 00000000000bdd4a l 0e SECT 01 0000 [.text] __ZNK9BltShader16GetShaderMemSizeEv 00000000000bdd54 l 0e SECT 01 0000 [.text] __ZNK9BltShader23GetRoundedShaderMemSizeEv 00000000000cb12a l 0e SECT 01 0000 [.text] __ZN18SiBltComputeShaderD1Ev 00000000000cb134 l 0e SECT 01 0000 [.text] __ZN18SiBltComputeShaderD0Ev 00000000000cb150 l 0e SECT 01 0000 [.text] __ZNK9BltShader16GetShaderMemSizeEv 00000000000cb15a l 0e SECT 01 0000 [.text] __ZNK9BltShader23GetRoundedShaderMemSizeEv 00000000000cb164 l 0e SECT 01 0000 [.text] __ZN17SiBltVertexShaderD1Ev 00000000000cb16e l 0e SECT 01 0000 [.text] __ZN17SiBltVertexShaderD0Ev 00000000000d086c l 0e SECT 01 0000 [.text] __ZNK7AddrLib15HwlGetTileIndexEPK25_ADDR_GET_TILEINDEX_INPUTP26_ADDR_GET_TILEINDEX_OUTPUT 00000000000d0878 l 0e SECT 01 0000 [.text] __ZNK7AddrLib17HwlComputeDccInfoEPK27_ADDR_COMPUTE_DCCINFO_INPUTP28_ADDR_COMPUTE_DCCINFO_OUTPUT 00000000000d0884 l 0e SECT 01 0000 [.text] __ZNK7AddrLib28HwlComputeCmaskAddrFromCoordEPK39_ADDR_COMPUTE_CMASK_ADDRFROMCOORD_INPUTP40_ADDR_COMPUTE_CMASK_ADDRFROMCOORD_OUTPUT 00000000000d0890 l 0e SECT 01 0000 [.text] __ZNK7AddrLib19HwlOverrideTileModeEPK32_ADDR_COMPUTE_SURFACE_INFO_INPUTP13_AddrTileModeP13_AddrTileType 00000000000d0898 l 0e SECT 01 0000 [.text] __ZNK7AddrLib16HwlPadDimensionsE13_AddrTileModej19_ADDR_SURFACE_FLAGSjP14_ADDR_TILEINFOjjPjjS4_jS4_j 00000000000d089e l 0e SECT 01 0000 [.text] __ZNK7AddrLib24HwlComputeMacroModeIndexEi19_ADDR_SURFACE_FLAGSjjP14_ADDR_TILEINFOP13_AddrTileModeP13_AddrTileType 00000000000d3428 l 0e SECT 01 0000 [.text] __ZNK14EgBasedAddrLib22HwlGetMaxCmaskBlockMaxEv 00000000000d3434 l 0e SECT 01 0000 [.text] __ZNK7AddrLib15HwlGetTileIndexEPK25_ADDR_GET_TILEINDEX_INPUTP26_ADDR_GET_TILEINDEX_OUTPUT 00000000000d3440 l 0e SECT 01 0000 [.text] __ZNK7AddrLib17HwlComputeDccInfoEPK27_ADDR_COMPUTE_DCCINFO_INPUTP28_ADDR_COMPUTE_DCCINFO_OUTPUT 00000000000d344c l 0e SECT 01 0000 [.text] __ZNK7AddrLib28HwlComputeCmaskAddrFromCoordEPK39_ADDR_COMPUTE_CMASK_ADDRFROMCOORD_INPUTP40_ADDR_COMPUTE_CMASK_ADDRFROMCOORD_OUTPUT 00000000000d3458 l 0e SECT 01 0000 [.text] __ZNK7AddrLib19HwlOverrideTileModeEPK32_ADDR_COMPUTE_SURFACE_INFO_INPUTP13_AddrTileModeP13_AddrTileType 00000000000d3460 l 0e SECT 01 0000 [.text] __ZNK7AddrLib16HwlPadDimensionsE13_AddrTileModej19_ADDR_SURFACE_FLAGSjP14_ADDR_TILEINFOjjPjjS4_jS4_j 00000000000d3466 l 0e SECT 01 0000 [.text] __ZNK7AddrLib24HwlComputeMacroModeIndexEi19_ADDR_SURFACE_FLAGSjjP14_ADDR_TILEINFOP13_AddrTileModeP13_AddrTileType 00000000000d3472 l 0e SECT 01 0000 [.text] __ZNK11R800AddrLib16HwlPreAdjustBankEjjP14_ADDR_TILEINFO 00000000000d347a l 0e SECT 01 0000 [.text] __ZNK14EgBasedAddrLib21HwlPostCheckTileIndexEPK14_ADDR_TILEINFO13_AddrTileMode13_AddrTileTypei 00000000000d3486 l 0e SECT 01 0000 [.text] __ZNK14EgBasedAddrLib24HwlFmaskPreThunkSurfInfoEPK30_ADDR_COMPUTE_FMASK_INFO_INPUTPK31_ADDR_COMPUTE_FMASK_INFO_OUTPUTP32_ADDR_COMPUTE_SURFACE_INFO_INPUTP33_ADDR_COMPUTE_SURFACE_INFO_OUTPUT 00000000000d348c l 0e SECT 01 0000 [.text] __ZNK14EgBasedAddrLib25HwlFmaskPostThunkSurfInfoEPK33_ADDR_COMPUTE_SURFACE_INFO_OUTPUTP31_ADDR_COMPUTE_FMASK_INFO_OUTPUT 00000000000d3492 l 0e SECT 01 0000 [.text] __ZNK14EgBasedAddrLib32HwlStereoCheckRightOffsetPaddingEv 00000000000d59a0 l 0e SECT 01 0000 [.text] __ZNK14EgBasedAddrLib22HwlGetMaxCmaskBlockMaxEv 00000000000d59ac l 0e SECT 01 0000 [.text] __ZNK7AddrLib17HwlComputeDccInfoEPK27_ADDR_COMPUTE_DCCINFO_INPUTP28_ADDR_COMPUTE_DCCINFO_OUTPUT 00000000000d59b8 l 0e SECT 01 0000 [.text] __ZNK7AddrLib28HwlComputeCmaskAddrFromCoordEPK39_ADDR_COMPUTE_CMASK_ADDRFROMCOORD_INPUTP40_ADDR_COMPUTE_CMASK_ADDRFROMCOORD_OUTPUT 00000000000d59c4 l 0e SECT 01 0000 [.text] __ZNK7AddrLib16HwlPadDimensionsE13_AddrTileModej19_ADDR_SURFACE_FLAGSjP14_ADDR_TILEINFOjjPjjS4_jS4_j 00000000000d59ca l 0e SECT 01 0000 [.text] __ZNK7AddrLib24HwlComputeMacroModeIndexEi19_ADDR_SURFACE_FLAGSjjP14_ADDR_TILEINFOP13_AddrTileModeP13_AddrTileType 00000000000d59d6 l 0e SECT 01 0000 [.text] __ZNK9SIAddrLib24HwlSanityCheckMacroTiledEP14_ADDR_TILEINFO 00000000000d59e2 l 0e SECT 01 0000 [.text] __ZNK14EgBasedAddrLib32HwlStereoCheckRightOffsetPaddingEv 00000000000d59ea l 0e SECT 01 0000 [.text] __ZNK9SIAddrLib24HwlReduceBankWidthHeightEjj19_ADDR_SURFACE_FLAGSjjjP14_ADDR_TILEINFO 00000000000d6e41 l 0e SECT 01 0000 [.text] __ZL14AddrInsertBitsyyjj 00000000000d704a l 0e SECT 01 0000 [.text] __ZNK14EgBasedAddrLib22HwlGetMaxCmaskBlockMaxEv 00000000000d7056 l 0e SECT 01 0000 [.text] __ZNK9SIAddrLib24HwlSanityCheckMacroTiledEP14_ADDR_TILEINFO 00000000000d7062 l 0e SECT 01 0000 [.text] __ZNK9SIAddrLib24HwlReduceBankWidthHeightEjj19_ADDR_SURFACE_FLAGSjjjP14_ADDR_TILEINFO 00000000000da9a8 l 0e SECT 01 0000 [.text] __ZNK14EgBasedAddrLib22HwlGetMaxCmaskBlockMaxEv 00000000000da9b4 l 0e SECT 01 0000 [.text] __ZNK7AddrLib15HwlGetTileIndexEPK25_ADDR_GET_TILEINDEX_INPUTP26_ADDR_GET_TILEINDEX_OUTPUT 00000000000da9c0 l 0e SECT 01 0000 [.text] __ZNK7AddrLib17HwlComputeDccInfoEPK27_ADDR_COMPUTE_DCCINFO_INPUTP28_ADDR_COMPUTE_DCCINFO_OUTPUT 00000000000da9cc l 0e SECT 01 0000 [.text] __ZNK7AddrLib28HwlComputeCmaskAddrFromCoordEPK39_ADDR_COMPUTE_CMASK_ADDRFROMCOORD_INPUTP40_ADDR_COMPUTE_CMASK_ADDRFROMCOORD_OUTPUT 00000000000da9d8 l 0e SECT 01 0000 [.text] __ZNK7AddrLib19HwlOverrideTileModeEPK32_ADDR_COMPUTE_SURFACE_INFO_INPUTP13_AddrTileModeP13_AddrTileType 00000000000da9e0 l 0e SECT 01 0000 [.text] __ZNK7AddrLib16HwlPadDimensionsE13_AddrTileModej19_ADDR_SURFACE_FLAGSjP14_ADDR_TILEINFOjjPjjS4_jS4_j 00000000000da9e6 l 0e SECT 01 0000 [.text] __ZNK7AddrLib24HwlComputeMacroModeIndexEi19_ADDR_SURFACE_FLAGSjjP14_ADDR_TILEINFOP13_AddrTileModeP13_AddrTileType 00000000000da9f2 l 0e SECT 01 0000 [.text] __ZNK14EgBasedAddrLib21HwlPostCheckTileIndexEPK14_ADDR_TILEINFO13_AddrTileMode13_AddrTileTypei 00000000000da9fe l 0e SECT 01 0000 [.text] __ZNK14EgBasedAddrLib24HwlFmaskPreThunkSurfInfoEPK30_ADDR_COMPUTE_FMASK_INFO_INPUTPK31_ADDR_COMPUTE_FMASK_INFO_OUTPUTP32_ADDR_COMPUTE_SURFACE_INFO_INPUTP33_ADDR_COMPUTE_SURFACE_INFO_OUTPUT 00000000000daa04 l 0e SECT 01 0000 [.text] __ZNK14EgBasedAddrLib25HwlFmaskPostThunkSurfInfoEPK33_ADDR_COMPUTE_SURFACE_INFO_OUTPUTP31_ADDR_COMPUTE_FMASK_INFO_OUTPUT 00000000000daa0a l 0e SECT 01 0000 [.text] __ZNK14EgBasedAddrLib32HwlStereoCheckRightOffsetPaddingEv 00000000000db3bb l 0e SECT 01 0000 [.text] _should_vbios_post 00000000000db405 l 0e SECT 01 0000 [.text] _post_vbios 00000000000dbe24 l 0e SECT 01 0000 [.text] _get_atom_bios_string 00000000000dca1f l 0e SECT 01 0000 [.text] _Bonaire_RestoreAdapterCfgRegisters 00000000000dca9b l 0e SECT 01 0000 [.text] _Bonaire_GetPcieLinkSpeedSupport 00000000000dcc33 l 0e SECT 01 0000 [.text] _Bonair_CheckPcieLinkUpconfigSupport 00000000000dccf1 l 0e SECT 01 0000 [.text] _Bonaire_PCIELane_Switch 00000000000dcda0 l 0e SECT 01 0000 [.text] _Bonaire_UpdateSwConstantForHwConfig 00000000000dce34 l 0e SECT 01 0000 [.text] _Bonaire_CheckMemoryConfiguration 00000000000dce99 l 0e SECT 01 0000 [.text] _Bonaire_SetupCgReferenceClock 00000000000dcec1 l 0e SECT 01 0000 [.text] _Bonaire_GetGbTileMode 00000000000dcef4 l 0e SECT 01 0000 [.text] _Bonaire_GetGbMacroTileMode 00000000000dcf11 l 0e SECT 01 0000 [.text] _Bonaire_EnableCpInterrupt 00000000000dcf4a l 0e SECT 01 0000 [.text] _Bonaire_DisableCpInterrupt 00000000000dcf83 l 0e SECT 01 0000 [.text] _Bonaire_DisableCpIdleInterrupt 00000000000dcfbc l 0e SECT 01 0000 [.text] _Bonaire_ResetRlc 00000000000dd017 l 0e SECT 01 0000 [.text] _Bonaire_UpdateGfxClockGating 00000000000dd0ed l 0e SECT 01 0000 [.text] _Bonaire_UpdateSystemClockGating 00000000000dd98a l 0e SECT 01 0000 [.text] _Bonaire_UpdateMultimediaClockGating 00000000000ddab8 l 0e SECT 01 0000 [.text] _Bonaire_UpdateVceClockGating 00000000000ddb53 l 0e SECT 01 0000 [.text] _Bonaire_UpdateCoarseGrainClockGating 00000000000ddcd2 l 0e SECT 01 0000 [.text] _Bonaire_UpdateMediumGrainClockGating 00000000000ddf60 l 0e SECT 01 0000 [.text] _Bonaire_DisableUvdMediumGrainClockGating 00000000000ddfaa l 0e SECT 01 0000 [.text] _Bonaire_EnableUvdMediumGrainClockGating 00000000000ddff7 l 0e SECT 01 0000 [.text] _Bonaire_UpdateXdmaSclkGating 00000000000de071 l 0e SECT 01 0000 [.text] _Bonaire_InitNonsurfAperture 00000000000de0a4 l 0e SECT 01 0000 [.text] _Bonaire_ProgramPcieGen3 00000000000de454 l 0e SECT 01 0000 [.text] _Bonaire_InitUvdClocks 00000000000de57e l 0e SECT 01 0000 [.text] _Bonaire_InitVceClocks 00000000000de732 l 0e SECT 01 0000 [.text] _Bonaire_InitAcpClocks 00000000000de7ef l 0e SECT 01 0000 [.text] _Bonaire_InitSamuClocks 00000000000de8bb l 0e SECT 01 0000 [.text] _Bonaire_CheckAcpHarvested 00000000000de922 l 0e SECT 01 0000 [.text] _Bonaire_LoadUcode 00000000000dea05 l 0e SECT 01 0000 [.text] _Bonaire_InitCSBHeader 00000000000dea64 l 0e SECT 01 0000 [.text] _Bonaire_InitMasterPacketHeader 00000000000deac3 l 0e SECT 01 0000 [.text] _Bonaire_MicroEngineControlCp 00000000000dee3c l 0e SECT 01 0000 [.text] _Bonaire_MicroEngineControlMec 00000000000df394 l 0e SECT 01 0000 [.text] _Bonaire_MicroEngineControlSdma 00000000000df95c l 0e SECT 01 0000 [.text] _Bonaire_QueryCuReservationRegisterInfo 00000000000df978 l 0e SECT 01 0000 [.text] _Bonaire_UpdateAsicConfigRegisters 00000000000dfe9c l 0e SECT 01 0000 [.text] _Bonaire_CsQueryRegWriteList 00000000000dfeae l 0e SECT 01 0000 [.text] _Bonaire_CsQueryMetaDataRegList 00000000000dfec0 l 0e SECT 01 0000 [.text] _Bonaire_AsicState 00000000000dff40 l 0e SECT 01 0000 [.text] _Bonaire_WaitForIdle 00000000000dffa0 l 0e SECT 01 0000 [.text] _Bonaire_WaitForIdleGui 00000000000e000d l 0e SECT 01 0000 [.text] _Bonaire_IsDisplayBlockHang 00000000000e0182 l 0e SECT 01 0000 [.text] _Bonaire_IsGuiIdle 00000000000e01e1 l 0e SECT 01 0000 [.text] _Bonaire_WaitForIdleSdma 00000000000e0276 l 0e SECT 01 0000 [.text] _Bonaire_WaitForIdleCp 00000000000e02e3 l 0e SECT 01 0000 [.text] _Bonaire_WaitForIdleVce 00000000000e0358 l 0e SECT 01 0000 [.text] _Bonaire_WaitForIdleUvd 00000000000e03cd l 0e SECT 01 0000 [.text] _Bonaire_SelectSeSh 00000000000e041b l 0e SECT 01 0000 [.text] _Bonaire_CheckAsicBlockState 00000000000e053f l 0e SECT 01 0000 [.text] _Bonaire_TdrBegin 00000000000e0832 l 0e SECT 01 0000 [.text] _Bonaire_MonitorEngineInternalState 00000000000e097e l 0e SECT 01 0000 [.text] _Bonaire_MonitorPerformanceCounter 00000000000e0ab1 l 0e SECT 01 0000 [.text] _Bonaire_LiteResetEngine 00000000000e0c40 l 0e SECT 01 0000 [.text] _Bonaire_IsNonEngineChipHung 00000000000e0c7b l 0e SECT 01 0000 [.text] _Bonaire_EncodeBlocksForReset 00000000000e0d04 l 0e SECT 01 0000 [.text] _Bonaire_SoftResetMethod 00000000000e0e95 l 0e SECT 01 0000 [.text] _Bonaire_DisableFbMemAccess 00000000000e10e2 l 0e SECT 01 0000 [.text] _Bonaire_EnableFbMemAccess 00000000000e12a9 l 0e SECT 01 0000 [.text] _Bonaire_PostLiteReset 00000000000e1383 l 0e SECT 01 0000 [.text] _Bonaire_PreLiteReset 00000000000e1389 l 0e SECT 01 0000 [.text] _Bonaire_UvdInit 00000000000e1897 l 0e SECT 01 0000 [.text] _Bonaire_UvdSuspend 00000000000e1ae0 l 0e SECT 01 0000 [.text] _Bonaire_SetupUvdCacheWindows 00000000000e1b8f l 0e SECT 01 0000 [.text] _Bonaire_VceInit 00000000000e1ef8 l 0e SECT 01 0000 [.text] _Bonaire_VceSuspend 00000000000e20c0 l 0e SECT 01 0000 [.text] _Bonaire_SamuInit 00000000000e258e l 0e SECT 01 0000 [.text] _Bonaire_SamuSuspend 00000000000e25e0 l 0e SECT 01 0000 [.text] _Bonaire_SamuSetClk 00000000000e270a l 0e SECT 01 0000 [.text] _Bonaire_SamuCheckDebugBoard 00000000000e273a l 0e SECT 01 0000 [.text] _Bonaire_SamuSrbmSoftReset 00000000000e2749 l 0e SECT 01 0000 [.text] _Bonaire_RaiseSamuResetInterrupt 00000000000e27e7 l 0e SECT 01 0000 [.text] _Bonaire_UpdateSamuSwClockGating 00000000000e2844 l 0e SECT 01 0000 [.text] _Bonaire_HdpHideReservedBlock 00000000000e28cc l 0e SECT 01 0000 [.text] _Bonaire_HdpUnhideReservedBlock 00000000000e29f5 l 0e SECT 01 0000 [.text] _Bonaire_ExecuteDmaCopy 00000000000e2abb l 0e SECT 01 0000 [.text] _Bonaire_ClearFbMemory 00000000000e2bf2 l 0e SECT 01 0000 [.text] _Bonaire_CfSetPeerApertureDefault 00000000000e2d3a l 0e SECT 01 0000 [.text] _Bonaire_CfEnableMailbox 00000000000e2db8 l 0e SECT 01 0000 [.text] _Bonaire_LocalHaltRlc 00000000000e2f35 l 0e SECT 01 0000 [.text] _Bonaire_ClockGatingControl 00000000000e2fa6 l 0e SECT 01 0000 [.text] _Bonaire_EnableLBPW 00000000000e2fe1 l 0e SECT 01 0000 [.text] _Bonaire_micro_engine_control 00000000000e303a l 0e SECT 01 0000 [.text] _Bonaire_get_indirect_register_smc 00000000000e3052 l 0e SECT 01 0000 [.text] _Bonaire_set_indirect_register_smc 00000000000e306d l 0e SECT 01 0000 [.text] _Bonaire_get_indirect_register_pcie 00000000000e3085 l 0e SECT 01 0000 [.text] _Bonaire_set_indirect_register_pcie 00000000000e30a0 l 0e SECT 01 0000 [.text] _bonaire_get_indirect_register_sam_sab 00000000000e30b8 l 0e SECT 01 0000 [.text] _bonaire_set_indirect_register_sam_sab 00000000000e30d3 l 0e SECT 01 0000 [.text] _bonaire_get_indirect_register_sam 00000000000e30eb l 0e SECT 01 0000 [.text] _bonaire_set_indirect_register_sam 00000000000e3106 l 0e SECT 01 0000 [.text] _Bonaire_ReadMmPciConfigRegister 00000000000e315d l 0e SECT 01 0000 [.text] _Bonaire_WriteMmPciConfigRegister 00000000000e31b8 l 0e SECT 01 0000 [.text] _Bonaire_GpioReadPin 00000000000e3250 l 0e SECT 01 0000 [.text] _Bonaire_GetPaScRasterConfig 00000000000e32a3 l 0e SECT 01 0000 [.text] _Bonaire_SwitchMcConfigContext 00000000000e3375 l 0e SECT 01 0000 [.text] _bonaire_perform_grbm_soft_reset 00000000000e33e7 l 0e SECT 01 0000 [.text] _bonaire_perform_srbm_soft_reset 00000000000e3632 l 0e SECT 01 0000 [.text] _bonaire_halt_rlc 00000000000e376c l 0e SECT 01 0000 [.text] _bonaire_access_doorbell_aperture 00000000000e3822 l 0e SECT 01 0000 [.text] _bonaire_set_uvd_dynamic_clock_mode 00000000000e38a9 l 0e SECT 01 0000 [.text] _bonaire_set_vce_sw_clock_gating 00000000000e3999 l 0e SECT 01 0000 [.text] _bonaire_set_vce_dyn_clock_gating 00000000000e3a53 l 0e SECT 01 0000 [.text] _bonaire_init_vce_clock_gating 00000000000e3ae7 l 0e SECT 01 0000 [.text] _bonaire_program_samu_sw_clock_gating 00000000000e3b6b l 0e SECT 01 0000 [.text] _bonaire_local_update_rlc 00000000000e3ba0 l 0e SECT 01 0000 [.text] _Bonaire_IsSAMUHung 00000000000e3bd1 l 0e SECT 01 0000 [.text] _bonaire_load_ucode_via_port_register 00000000000e3c49 l 0e SECT 01 0000 [.text] _bonaire_set_uvd_clock 00000000000e3d50 l 0e SECT 01 0000 [.text] _bonaire_link_equalization_callback 00000000000e4014 l 0e SECT 01 0000 [.text] _bonaire_update_register_golden_settings 00000000000e42df l 0e SECT 01 0000 [.text] _bonaire_init_ucode_buffer 00000000000e4324 l 0e SECT 01 0000 [.text] _bonaire_init_ECC 00000000000e4595 l 0e SECT 01 0000 [.text] _bonaire_init_power_gating 00000000000e45e1 l 0e SECT 01 0000 [.text] _bonaire_init_LBPW 00000000000e46a9 l 0e SECT 01 0000 [.text] _bonaire_init_clock_gating 00000000000e4771 l 0e SECT 01 0000 [.text] _bonaire_init_rlc 00000000000e4864 l 0e SECT 01 0000 [.text] _bonaire_unhalt_rlc 00000000000e48ab l 0e SECT 01 0000 [.text] _bonaire_program_pcie_link_width 00000000000e48b6 l 0e SECT 01 0000 [.text] _bonaire_program_aspm 00000000000ea4cf l 0e SECT 01 0000 [.text] _get_master_offset_to_caps 00000000000ea60a l 0e SECT 01 0000 [.text] _check_pcie_cap 00000000000eba0f l 0e SECT 01 0000 [.text] _check_register_state_in_group 00000000000eceb2 l 0e SECT 01 0000 [.text] _CopyMcToMcViaCpDma 00000000000ed541 l 0e SECT 01 0000 [.text] _check_next_p2p 00000000000ed6cf l 0e SECT 01 0000 [.text] _check_mvpu_switch_port_info 00000000000ed83b l 0e SECT 01 0000 [.text] _set_PCI_to_PCI_bridge_info 00000000000ed8a2 l 0e SECT 01 0000 [.text] _get_asic_caps_set_from_table 00000000000eefe0 l 0e SECT 01 0000 [.text] _check_CF_ID_info 00000000000ef2fd l 0e SECT 01 0000 [.text] _collect_crossfire_info 00000000000f125c l 0e SECT 01 0000 [.text] _reserve_fb_for_rlc 00000000000f1605 l 0e SECT 01 0000 [.text] _check_and_reserve_fb_for_samu 00000000000f169a l 0e SECT 01 0000 [.text] _reserve_fb_for_micro_engine 00000000000f1710 l 0e SECT 01 0000 [.text] _add_block_from_fb_high 00000000000f1b36 l 0e SECT 01 0000 [.text] _get_rlc_buffer_info 00000000000f1ead l 0e SECT 01 0000 [.text] _get_clear_state_buffer_size_for_llano_trinity 00000000000f24eb l 0e SECT 01 0000 [.text] _get_next_border 00000000000f2536 l 0e SECT 01 0000 [.text] _add_new_block 00000000000f268a l 0e SECT 01 0000 [.text] _overlap_new_block 00000000000f46b5 l 0e SECT 01 0000 [.text] _iri_release 00000000000f46dd l 0e SECT 01 0000 [.text] _iri_call 00000000000f4ad9 l 0e SECT 01 0000 [.text] _get_p2p_flush_command 00000000000f4b14 l 0e SECT 01 0000 [.text] _setup_uvd_clock 00000000000f4b4a l 0e SECT 01 0000 [.text] _switch_pcie_lane 00000000000f4b85 l 0e SECT 01 0000 [.text] _query_aspm_inactivity_cap 00000000000f4bbb l 0e SECT 01 0000 [.text] _switch_ultra_low_power_state 00000000000f4cb7 l 0e SECT 01 0000 [.text] _query_adapter_info 00000000000f4d13 l 0e SECT 01 0000 [.text] _query_cf_memory_client_group 00000000000f4d42 l 0e SECT 01 0000 [.text] _get_cf_p2p_flush_command_ex 00000000000f4d7d l 0e SECT 01 0000 [.text] _query_system_info 00000000000f4dd6 l 0e SECT 01 0000 [.text] _power_control 00000000000f4e21 l 0e SECT 01 0000 [.text] _setup_vce_clock 00000000000f4e57 l 0e SECT 01 0000 [.text] _query_mc_address_range 00000000000f4e88 l 0e SECT 01 0000 [.text] _micro_engine_control 00000000000f4eab l 0e SECT 01 0000 [.text] _setup_samu_clock 00000000000f4ed8 l 0e SECT 01 0000 [.text] _setup_acp_clock 00000000000f4f12 l 0e SECT 01 0000 [.text] _event_notification 00000000000f4f34 l 0e SECT 01 0000 [.text] _query_micro_code_info 00000000000f4f67 l 0e SECT 01 0000 [.text] _get_firmware_image 00000000000f5120 l 0e SECT 01 0000 [.text] _cs_init_meta_data_list_reg_value 00000000000f51a2 l 0e SECT 01 0000 [.text] _cs_init_meta_data_list_reg_number 00000000000f5224 l 0e SECT 01 0000 [.text] _set_gen2_tls 00000000000f5270 l 0e SECT 01 0000 [.text] _fill_meta_data 00000000000f5678 l 0e SECT 01 0000 [.text] _get_powerplay_IRI 00000000000f5d2f l 0e SECT 01 0000 [.text] _write_pci_cfg_registers 00000000000f6bbd l 0e SECT 01 0000 [.text] _wait_for_multiobj_condition 00000000000f748b l 0e SECT 01 0000 [.text] _acpi_control_method_function_ext 00000000000f7f77 l 0e SECT 01 0000 [.text] _get_max_MC_address_space 00000000000f8932 l 0e SECT 01 0000 [.text] _adjust_fb_size 00000000000f89a1 l 0e SECT 01 0000 [.text] _get_available_range_from_top 00000000000f89ff l 0e SECT 01 0000 [.text] _get_available_range_from_base 00000000000f9268 l 0e SECT 01 0000 [.text] _perform_power_control 00000000000f9a44 l 0e SECT 01 0000 [.text] _perform_enable_LBPW 00000000000fa301 l 0e SECT 01 0000 [.text] _update_gfx_medium_grain_power_gating 00000000000fa5d8 l 0e SECT 01 0000 [.text] _update_gfx_coarse_grain_power_gating 00000000000fa68c l 0e SECT 01 0000 [.text] _update_gmc_power_gating_mode 00000000000fa7f4 l 0e SECT 01 0000 [.text] _update_drmdma_power_gating_mode 00000000000fa87d l 0e SECT 01 0000 [.text] _update_gfx_clock_gating 00000000000faa47 l 0e SECT 01 0000 [.text] _update_mc_light_sleep_mode 00000000000facff l 0e SECT 01 0000 [.text] _update_mc_medium_grain_clock_gating_mode 00000000000fafb7 l 0e SECT 01 0000 [.text] _update_drmdma_medium_grain_clock_gating_mode 00000000000fb150 l 0e SECT 01 0000 [.text] _update_bif_medium_grain_light_sleep_mode 00000000000fb1c1 l 0e SECT 01 0000 [.text] _update_uvd_medium_grain_clock_gating_mode 00000000000fb2a6 l 0e SECT 01 0000 [.text] _update_spu_medium_grain_clock_gating_mode 00000000000fb32f l 0e SECT 01 0000 [.text] _update_xdma_sclk_gating_mode 00000000000fb3a7 l 0e SECT 01 0000 [.text] _update_xdma_light_sleep_mode 00000000000fb41f l 0e SECT 01 0000 [.text] _update_hdp_medium_grain_clock_gating_mode 00000000000fb497 l 0e SECT 01 0000 [.text] _update_hdp_light_sleep_mode 00000000000fb506 l 0e SECT 01 0000 [.text] _update_drm_light_sleep_mode 00000000000fb575 l 0e SECT 01 0000 [.text] _disable_uvd_power_gating 00000000000fb6b3 l 0e SECT 01 0000 [.text] _enable_uvd_power_gating 00000000000fb8fd l 0e SECT 01 0000 [.text] _disable_vce_power_gating 00000000000fba34 l 0e SECT 01 0000 [.text] _enable_vce_power_gating 00000000000fbca4 l 0e SECT 01 0000 [.text] _update_coarse_grain_clock_gating 00000000000fbf04 l 0e SECT 01 0000 [.text] _update_medium_grain_clock_gating 00000000000fc0a4 l 0e SECT 01 0000 [.text] _local_halt_rlc 00000000000fc17b l 0e SECT 01 0000 [.text] _local_update_rlc 00000000000fc1b0 l 0e SECT 01 0000 [.text] _disable_gfx_static_medium_grain_power_gating 00000000000fc1e6 l 0e SECT 01 0000 [.text] _disable_gfx_dyn_medium_grain_power_gating 00000000000fc46a l 0e SECT 01 0000 [.text] _Carrizo_EnableSckSlowDownOnPowerUp 00000000000fc4b0 l 0e SECT 01 0000 [.text] _Carrizo_EnableSckSlowDownOnPowerDown 00000000000fc4f6 l 0e SECT 01 0000 [.text] _Carrizo_EnableCpPowerGating 00000000000fc53c l 0e SECT 01 0000 [.text] _Carrizo_UpdateGfxPowerGating 00000000000fc8c5 l 0e SECT 01 0000 [.text] _Carrizo_SetupASIC 00000000000fc8db l 0e SECT 01 0000 [.text] _Carrizo_SetupCgReferenceClock 00000000000fc8fd l 0e SECT 01 0000 [.text] _Carrizo_CheckDsmuSupport 00000000000fc903 l 0e SECT 01 0000 [.text] _Carrizo_UpdateSwConstantForHwConfig 00000000000fc9fd l 0e SECT 01 0000 [.text] _Carrizo_ZeroFbConfigAndSize 00000000000fca8e l 0e SECT 01 0000 [.text] _Carrizo_FillMetaData 00000000000fcaea l 0e SECT 01 0000 [.text] _Carrizo_UpdateCoarseGrainClockGating 00000000000fcc3c l 0e SECT 01 0000 [.text] _Carrizo_UpdateMediumGrainClockGating 00000000000fce8a l 0e SECT 01 0000 [.text] _Carrizo_PowerGatingControl 00000000000fcea7 l 0e SECT 01 0000 [.text] _Carrizo_CheckAcpHarvested 00000000000fcf0e l 0e SECT 01 0000 [.text] _Carrizo_FormatSmuDramDataBuffer 00000000000fd00f l 0e SECT 01 0000 [.text] _carrizo_wait_rlc_serdes_master_idle 00000000000fd11d l 0e SECT 01 0000 [.text] _carrizo_send_serdes_cmd 00000000000fd1a1 l 0e SECT 01 0000 [.text] _carrizo_register_update_for_asic_sku 00000000000fd660 l 0e SECT 01 0000 [.text] _carrizo_init_ucode_buffer 00000000000fd6b0 l 0e SECT 01 0000 [.text] _carrizo_halt_rlc 00000000000fd6ed l 0e SECT 01 0000 [.text] _carrizo_reset_rlc 00000000000fd6ff l 0e SECT 01 0000 [.text] _carrizo_init_power_gating 00000000000fd77f l 0e SECT 01 0000 [.text] _carrizo_init_LBPW 00000000000fd833 l 0e SECT 01 0000 [.text] _carrizo_init_clock_gating 00000000000fd886 l 0e SECT 01 0000 [.text] _carrizo_init_nonsurf_aperture 00000000000fd891 l 0e SECT 01 0000 [.text] _carrizo_init_uvd_clocks 00000000000fd89c l 0e SECT 01 0000 [.text] _carrizo_init_vce_clocks 00000000000fd8a7 l 0e SECT 01 0000 [.text] _carrizo_init_acp_clocks 00000000000fd8b2 l 0e SECT 01 0000 [.text] _Carrizo_DisableGfxDynamicMGPowerGating 00000000000fd9ec l 0e SECT 01 0000 [.text] _select_se 00000000000fe453 l 0e SECT 01 0000 [.text] _set_gb_addr_config_registers 00000000000fe4fe l 0e SECT 01 0000 [.text] _Cayman_halt_micro_engine 00000000000fe9f7 l 0e SECT 01 0000 [.text] _Cayman_set_clk_bypass_mode 00000000000feab9 l 0e SECT 01 0000 [.text] _Cayman_disable_FB_mem_access 00000000000fed6a l 0e SECT 01 0000 [.text] _Cayman_soft_reset_method 00000000000ff1b2 l 0e SECT 01 0000 [.text] _Cayman_encode_blocks_for_reset 00000000000ff34b l 0e SECT 01 0000 [.text] _Cayman_check_asic_block_state 00000000000ff660 l 0e SECT 01 0000 [.text] _enable_electrical_idle_detectors 00000000000ffd1e l 0e SECT 01 0000 [.text] _program_upll 00000000000fff3f l 0e SECT 01 0000 [.text] _select_upll_vclk_dclk 0000000000100033 l 0e SECT 01 0000 [.text] _set_uvd_dynamic_clock_mode 000000000010009b l 0e SECT 01 0000 [.text] _program_spread_spectrum 000000000010052d l 0e SECT 01 0000 [.text] _select_upll_bypass 0000000000100ce1 l 0e SECT 01 0000 [.text] _get_gb_addr_config_setting 0000000000100dfc l 0e SECT 01 0000 [.text] _setup_peer_aperture_mc_addr 0000000000100f75 l 0e SECT 01 0000 [.text] _setup_peer_system_bar 0000000000101953 l 0e SECT 01 0000 [.text] _reset_grbm_srbm 0000000000101a3a l 0e SECT 01 0000 [.text] _Cayman_WaitForVBlank 0000000000101ae9 l 0e SECT 01 0000 [.text] _Cayman_IsCounterMoving 0000000000101b3c l 0e SECT 01 0000 [.text] _Cayman_init_additional_registers 0000000000101b98 l 0e SECT 01 0000 [.text] _Cayman_init_shader_pipe_registers 0000000000101e11 l 0e SECT 01 0000 [.text] _Cayman_init_nonsurf_aperture 0000000000101e44 l 0e SECT 01 0000 [.text] _Cayman_init_LBPW 0000000000101e8a l 0e SECT 01 0000 [.text] _Cayman_init_RLC_legacy_mode 000000000010202d l 0e SECT 01 0000 [.text] _Cayman_program_PCIE_Gen2 000000000010230a l 0e SECT 01 0000 [.text] _Cayman_program_aspm 0000000000102603 l 0e SECT 01 0000 [.text] _init_uvd_clocks 000000000010278a l 0e SECT 01 0000 [.text] _init_uvd_internal_clock_gating 000000000010281c l 0e SECT 01 0000 [.text] _Cayman_enable_FB_mem_access 0000000000102c02 l 0e SECT 01 0000 [.text] _select_se 0000000000103c35 l 0e SECT 01 0000 [.text] _set_gb_addr_config_registers 0000000000103c8b l 0e SECT 01 0000 [.text] _Cypress_halt_micro_engine 0000000000103daf l 0e SECT 01 0000 [.text] _bif_soft_reset 000000000010407a l 0e SECT 01 0000 [.text] _asic_hot_reset 000000000010414b l 0e SECT 01 0000 [.text] _Cypress_set_clk_bypass_mode 000000000010420d l 0e SECT 01 0000 [.text] _Cypress_soft_reset_method 0000000000104738 l 0e SECT 01 0000 [.text] _Cypress_check_asic_block_state 00000000001049b5 l 0e SECT 01 0000 [.text] _enable_electrical_idle_detectors 000000000010511a l 0e SECT 01 0000 [.text] _program_upll 0000000000105350 l 0e SECT 01 0000 [.text] _select_upll_vclk_dclk 0000000000105444 l 0e SECT 01 0000 [.text] _set_uvd_clk_gating_branches 00000000001054ae l 0e SECT 01 0000 [.text] _set_uvd_dynamic_clock_mode 0000000000105521 l 0e SECT 01 0000 [.text] _program_spread_spectrum 00000000001059e6 l 0e SECT 01 0000 [.text] _select_upll_bypass 0000000000106131 l 0e SECT 01 0000 [.text] _get_gb_addr_config_setting 000000000010624c l 0e SECT 01 0000 [.text] _setup_peer_aperture_mc_addr 00000000001063c5 l 0e SECT 01 0000 [.text] _setup_peer_system_bar 0000000000106e23 l 0e SECT 01 0000 [.text] _Cypress_init_additional_registers 0000000000106ed6 l 0e SECT 01 0000 [.text] _Cypress_init_shader_pipe_registers 000000000010713d l 0e SECT 01 0000 [.text] _Cypress_init_nonsurf_aperture 0000000000107170 l 0e SECT 01 0000 [.text] _Cypress_init_RLC_legacy_mode 0000000000107288 l 0e SECT 01 0000 [.text] _Cypress_program_PCIE_Gen2 0000000000107634 l 0e SECT 01 0000 [.text] _Cypress_program_aspm 00000000001079c5 l 0e SECT 01 0000 [.text] _init_uvd_clocks 0000000000107b4c l 0e SECT 01 0000 [.text] _init_uvd_internal_clock_gating 0000000000107f6f l 0e SECT 01 0000 [.text] _set_uvd_clock 00000000001086cd l 0e SECT 01 0000 [.text] _force_vce_clock_on 0000000000108ed1 l 0e SECT 01 0000 [.text] _Godavari_FormatSmuDramDataBuffer 0000000000109587 l 0e SECT 01 0000 [.text] _find_smu_entry 0000000000109f2c l 0e SECT 01 0000 [.text] _Iceland_SetupASIC 0000000000109f42 l 0e SECT 01 0000 [.text] _Iceland_RestoreAdapterCfgRegisters 0000000000109fa8 l 0e SECT 01 0000 [.text] _Iceland_FindAsicRevID 0000000000109fca l 0e SECT 01 0000 [.text] _Iceland_UpdateSwConstantForHwConfig 000000000010a05e l 0e SECT 01 0000 [.text] _Iceland_CheckMemoryConfiguration 000000000010a0c3 l 0e SECT 01 0000 [.text] _Iceland_IsFlrSupported 000000000010a0fa l 0e SECT 01 0000 [.text] _Iceland_GetGbTileMode 000000000010a12d l 0e SECT 01 0000 [.text] _Iceland_GetGbMacroTileMode 000000000010a14b l 0e SECT 01 0000 [.text] _Iceland_EnableCpInterrupt 000000000010a184 l 0e SECT 01 0000 [.text] _Iceland_DisableCpInterrupt 000000000010a1bd l 0e SECT 01 0000 [.text] _Iceland_DisableCpIdleInterrupt 000000000010a1f6 l 0e SECT 01 0000 [.text] _Iceland_UpdateCoarseGrainClockGating 000000000010a44b l 0e SECT 01 0000 [.text] _Iceland_UpdateMediumGrainClockGating 000000000010a6c9 l 0e SECT 01 0000 [.text] _Iceland_UpdateXdmaSclkGating 000000000010a6cf l 0e SECT 01 0000 [.text] _Iceland_ZeroFbConfigAndSize 000000000010a704 l 0e SECT 01 0000 [.text] _Iceland_FormatSmuDramDataBuffer 000000000010a865 l 0e SECT 01 0000 [.text] _Iceland_InitCSBHeader 000000000010a8c4 l 0e SECT 01 0000 [.text] _Iceland_MicroEngineControlCp 000000000010ac38 l 0e SECT 01 0000 [.text] _Iceland_MicroEngineControlMec 000000000010b2f8 l 0e SECT 01 0000 [.text] _Iceland_MicroEngineControlSdma 000000000010b92c l 0e SECT 01 0000 [.text] _Iceland_LoadRlcUcode 000000000010ba20 l 0e SECT 01 0000 [.text] _Iceland_GetRlcSaveRestoreRegisterListInfo 000000000010ba6e l 0e SECT 01 0000 [.text] _Iceland_QueryCuReservationRegisterInfo 000000000010ba8a l 0e SECT 01 0000 [.text] _Iceland_AsicState 000000000010baee l 0e SECT 01 0000 [.text] _Iceland_GetHungBlocks 000000000010bde8 l 0e SECT 01 0000 [.text] _Iceland_TdrBegin 000000000010c0f2 l 0e SECT 01 0000 [.text] _Iceland_MonitorEngineInternalState 000000000010c1f3 l 0e SECT 01 0000 [.text] _Iceland_CheckAsicBlockState 000000000010c2ed l 0e SECT 01 0000 [.text] _Iceland_SoftResetMethod 000000000010c46d l 0e SECT 01 0000 [.text] _Iceland_FunctionLevelReset 000000000010c612 l 0e SECT 01 0000 [.text] _Iceland_PostLiteReset 000000000010c798 l 0e SECT 01 0000 [.text] _Iceland_PreLiteReset 000000000010caa0 l 0e SECT 01 0000 [.text] _Iceland_CfInitPeerAperture 000000000010cc32 l 0e SECT 01 0000 [.text] _Iceland_CfSetPeerApertureDefault 000000000010cd7a l 0e SECT 01 0000 [.text] _Iceland_CfCloseTemporaryMailBox 000000000010ce0c l 0e SECT 01 0000 [.text] _Iceland_CfEnableMailbox 000000000010ce8a l 0e SECT 01 0000 [.text] _Iceland_LocalHaltRlc 000000000010cf15 l 0e SECT 01 0000 [.text] _Iceland_PowerGatingControl 000000000010cf2b l 0e SECT 01 0000 [.text] _Iceland_EnableLBPW 000000000010cf66 l 0e SECT 01 0000 [.text] _Iceland_EnterRlcSafeMode 000000000010d05a l 0e SECT 01 0000 [.text] _Iceland_ExitRlcSafeMode 000000000010d107 l 0e SECT 01 0000 [.text] _Iceland_WaitForDmaEngineIdle 000000000010d190 l 0e SECT 01 0000 [.text] _Iceland_WaitForIdleGui 000000000010d2c0 l 0e SECT 01 0000 [.text] _iceland_perform_grbm_soft_reset 000000000010d332 l 0e SECT 01 0000 [.text] _iceland_perform_srbm_soft_reset 000000000010d3a4 l 0e SECT 01 0000 [.text] _iceland_halt_rlc 000000000010d3e1 l 0e SECT 01 0000 [.text] _iceland_wait_rlc_serdes_master_idle 000000000010d4ef l 0e SECT 01 0000 [.text] _Iceland_IsVCEHung 000000000010d55e l 0e SECT 01 0000 [.text] _iceland_send_serdes_cmd 000000000010d5e2 l 0e SECT 01 0000 [.text] _iceland_register_update_for_asic_sku 000000000010d6dc l 0e SECT 01 0000 [.text] _iceland_init_ucode_buffer 000000000010d72c l 0e SECT 01 0000 [.text] _iceland_init_ECC 000000000010d94c l 0e SECT 01 0000 [.text] _iceland_reset_rlc 000000000010d95e l 0e SECT 01 0000 [.text] _iceland_init_power_gating 000000000010d99f l 0e SECT 01 0000 [.text] _iceland_init_LBPW 000000000010da53 l 0e SECT 01 0000 [.text] _iceland_init_clock_gating 000000000010da96 l 0e SECT 01 0000 [.text] _iceland_init_nonsurf_aperture 000000000010daa1 l 0e SECT 01 0000 [.text] _iceland_program_PCIE_Gen3 000000000010daac l 0e SECT 01 0000 [.text] _iceland_program_pcie_link_width 000000000010dab7 l 0e SECT 01 0000 [.text] _iceland_program_aspm 000000000010dac2 l 0e SECT 01 0000 [.text] _iceland_restore_audio_enablement 000000000010fb0e l 0e SECT 01 0000 [.text] _CailCompareEngineReadWritePointers 0000000000110740 l 0e SECT 01 0000 [.text] _Spectre_EnableRlcChubHandshaking 0000000000110786 l 0e SECT 01 0000 [.text] _Spectre_EnableSckSlowDownOnPowerUp 00000000001107cc l 0e SECT 01 0000 [.text] _Spectre_EnableSckSlowDownOnPowerDown 0000000000110812 l 0e SECT 01 0000 [.text] _Spectre_EnableCpPowerGating 0000000000110858 l 0e SECT 01 0000 [.text] _Spectre_EnableGDSPowerGating 000000000011089e l 0e SECT 01 0000 [.text] _Spectre_UpdateGfxPowerGating 0000000000110b8a l 0e SECT 01 0000 [.text] _Spectre_EnterRlcSafeMode 0000000000110c73 l 0e SECT 01 0000 [.text] _Spectre_ExitRlcSafeMode 0000000000110e0a l 0e SECT 01 0000 [.text] _Spectre_SetupCgReferenceClock 0000000000110e2c l 0e SECT 01 0000 [.text] _Spectre_MemoryConfigAndSize 0000000000110e86 l 0e SECT 01 0000 [.text] _Spectre_GetIntegrateAsicFbMcBaseAddr 0000000000110ea0 l 0e SECT 01 0000 [.text] _Spectre_ReserveFbMcRange 0000000000110f3b l 0e SECT 01 0000 [.text] _Spectre_UpdateSwConstantForHwConfig 0000000000111035 l 0e SECT 01 0000 [.text] _Spectre_CheckDsmuSupport 0000000000111071 l 0e SECT 01 0000 [.text] _Spectre_GetRlcSaveRestoreRegisterListInfo 00000000001110bf l 0e SECT 01 0000 [.text] _Spectre_PowerGatingControl 00000000001110dc l 0e SECT 01 0000 [.text] _Spectre_CheckAcpHarvested 0000000000111143 l 0e SECT 01 0000 [.text] _Spectre_EventNotification 000000000011141c l 0e SECT 01 0000 [.text] _Spectre_DisableGfxStaticMGPowerGating 0000000000111452 l 0e SECT 01 0000 [.text] _Spectre_DisableGfxDynamicMGPowerGating 0000000000111802 l 0e SECT 01 0000 [.text] _set_uvd_clock 0000000000112597 l 0e SECT 01 0000 [.text] _disable_cp_interrupt 0000000000112615 l 0e SECT 01 0000 [.text] _enable_cp_interrupt 0000000000112956 l 0e SECT 01 0000 [.text] _wait_for_vce_idle 0000000000112afe l 0e SECT 01 0000 [.text] _select_se_sh 00000000001131d2 l 0e SECT 01 0000 [.text] _disable_FB_mem_access 0000000000113410 l 0e SECT 01 0000 [.text] _set_clk_bypass_mode 00000000001134f7 l 0e SECT 01 0000 [.text] _powerdown_spll 000000000011357f l 0e SECT 01 0000 [.text] _soft_reset_method 0000000000113fd4 l 0e SECT 01 0000 [.text] _check_asic_block_state 00000000001146a5 l 0e SECT 01 0000 [.text] _program_upll 00000000001148c6 l 0e SECT 01 0000 [.text] _select_upll_vclk_dclk 00000000001149f1 l 0e SECT 01 0000 [.text] _set_uvd_dynamic_clock_mode 0000000000114a59 l 0e SECT 01 0000 [.text] _program_spread_spectrum 0000000000114eb5 l 0e SECT 01 0000 [.text] _select_upll_bypass 0000000000115780 l 0e SECT 01 0000 [.text] _program_vcepll 00000000001159a1 l 0e SECT 01 0000 [.text] _select_vcepll_evclk_ecclk 0000000000115aa7 l 0e SECT 01 0000 [.text] _program_vcepll_spread_spectrum 0000000000115e01 l 0e SECT 01 0000 [.text] _select_vcepll_bypass 0000000000116378 l 0e SECT 01 0000 [.text] _Tahiti_SetupPeerDataAperture 0000000000116409 l 0e SECT 01 0000 [.text] _Tahiti_SetupPeerApertureMcAddr 000000000011659b l 0e SECT 01 0000 [.text] _Tahiti_SetupPeerSystemBar 0000000000116683 l 0e SECT 01 0000 [.text] _Tahiti_SetupP2pBarCfg 000000000011673d l 0e SECT 01 0000 [.text] _Tahiti_SetupMemoryClientGroup 0000000000117a4b l 0e SECT 01 0000 [.text] _Tahiti_CheckPcieLinkUpconfigSupport 0000000000117b09 l 0e SECT 01 0000 [.text] _Tahiti_CheckPcieAspmSupport 0000000000117b6f l 0e SECT 01 0000 [.text] _Tahiti_ProgramPcieLinkWidth 0000000000117bdf l 0e SECT 01 0000 [.text] _Tahiti_ZeroFbConfigAndSize 0000000000117c70 l 0e SECT 01 0000 [.text] _resync_peer_aperture_internal_state 0000000000117cc7 l 0e SECT 01 0000 [.text] _Tahiti_CfEnableMailbox 0000000000117fa0 l 0e SECT 01 0000 [.text] _Tahiti_GetPaScRasterConfig 000000000011801c l 0e SECT 01 0000 [.text] _init_additional_registers 000000000011807b l 0e SECT 01 0000 [.text] _update_register_golden_settings 00000000001185e3 l 0e SECT 01 0000 [.text] _init_ECC 0000000000118973 l 0e SECT 01 0000 [.text] _reset_rlc 00000000001189de l 0e SECT 01 0000 [.text] _init_power_gating 0000000000118a3d l 0e SECT 01 0000 [.text] _init_LBPW 0000000000118ac4 l 0e SECT 01 0000 [.text] _init_clock_gating 0000000000118b75 l 0e SECT 01 0000 [.text] _init_rlc 0000000000118bfb l 0e SECT 01 0000 [.text] _init_nonsurf_aperture 0000000000118c2e l 0e SECT 01 0000 [.text] _program_PCIE_Gen3 0000000000118e47 l 0e SECT 01 0000 [.text] _program_aspm 0000000000119491 l 0e SECT 01 0000 [.text] _init_uvd_clocks 0000000000119613 l 0e SECT 01 0000 [.text] _init_vce_clocks 0000000000119795 l 0e SECT 01 0000 [.text] _link_equalization_callback 0000000000119cc5 l 0e SECT 01 0000 [.text] _Tonga_SetupASIC 0000000000119cdb l 0e SECT 01 0000 [.text] _Tonga_IsDisplayBlockHang 0000000000119e87 l 0e SECT 01 0000 [.text] _Tonga_CheckAsicBlockState 0000000000119fed l 0e SECT 01 0000 [.text] _Tonga_DisableFbMemAccess 000000000011a22d l 0e SECT 01 0000 [.text] _Tonga_EnableFbMemAccess 000000000011a3f4 l 0e SECT 01 0000 [.text] _Tonga_ProgramAspm 000000000011a775 l 0e SECT 01 0000 [.text] _Tonga_MonitorEngineInternalState 000000000011a8ec l 0e SECT 01 0000 [.text] _Tonga_SoftResetMethod 000000000011aac9 l 0e SECT 01 0000 [.text] _Tonga_CheckAcpHarvested 000000000011ab41 l 0e SECT 01 0000 [.text] _Tonga_ZeroFbConfigAndSize 000000000011abd2 l 0e SECT 01 0000 [.text] _Tonga_GetFbMemorySize 000000000011ac30 l 0e SECT 01 0000 [.text] _Tonga_InitCSBHeader 000000000011ac70 l 0e SECT 01 0000 [.text] _Tonga_MicroEngineControlCp 000000000011b158 l 0e SECT 01 0000 [.text] _Tonga_MicroEngineControlMec 000000000011b858 l 0e SECT 01 0000 [.text] _Tonga_MicroEngineControlSdma 000000000011be88 l 0e SECT 01 0000 [.text] _Tonga_GetFbMcBaseAddress 000000000011bea2 l 0e SECT 01 0000 [.text] _Tonga_DoorbellApertureControl 000000000011bedf l 0e SECT 01 0000 [.text] _Tonga_UpdateGfxClockGating 000000000011c027 l 0e SECT 01 0000 [.text] _Tonga_UpdateSystemClockGating 000000000011c2e3 l 0e SECT 01 0000 [.text] _Tonga_UvdInit 000000000011cbb4 l 0e SECT 01 0000 [.text] _Tonga_UvdSuspend 000000000011ce41 l 0e SECT 01 0000 [.text] _Tonga_IsUVDIdle 000000000011ce6a l 0e SECT 01 0000 [.text] _Tonga_SetupUvdCacheWindows 000000000011ceff l 0e SECT 01 0000 [.text] _Tonga_VceInit 000000000011d394 l 0e SECT 01 0000 [.text] _Tonga_VceSuspend 000000000011d60a l 0e SECT 01 0000 [.text] _Tonga_SamuInit 000000000011db71 l 0e SECT 01 0000 [.text] _Tonga_SamuSuspend 000000000011dc99 l 0e SECT 01 0000 [.text] _Tonga_SamuSetClk 000000000011ddc3 l 0e SECT 01 0000 [.text] _Tonga_SamuCheckDebugBoard 000000000011ddd3 l 0e SECT 01 0000 [.text] _Tonga_SamuSrbmSoftReset 000000000011de0b l 0e SECT 01 0000 [.text] _Tonga_RaiseSamuResetInterrupt 000000000011dea9 l 0e SECT 01 0000 [.text] _tonga_get_indirect_register_sam 000000000011dec1 l 0e SECT 01 0000 [.text] _tonga_set_indirect_register_sam 000000000011dedc l 0e SECT 01 0000 [.text] _Tonga_UpdateVceClockGating 000000000011dfe9 l 0e SECT 01 0000 [.text] _Tonga_UpdateVceLightSleep 000000000011e0bf l 0e SECT 01 0000 [.text] _Tonga_UpdateSamuLightSleep 000000000011e165 l 0e SECT 01 0000 [.text] _Tonga_GetDoutScratch3 000000000011e19f l 0e SECT 01 0000 [.text] _Tonga_DetectHwVirtualization 000000000011e294 l 0e SECT 01 0000 [.text] _Tonga_CalculateVirtualizationReservedOffset 000000000011e36c l 0e SECT 01 0000 [.text] _tonga_set_uvd_clk_gating_branches 000000000011e3db l 0e SECT 01 0000 [.text] _tonga_set_uvd_dynamic_clock_mode 000000000011eab8 l 0e SECT 01 0000 [.text] _tonga_process_ind_reg_list 000000000011eb72 l 0e SECT 01 0000 [.text] _tonga_set_sdma_door_bell_and_id 000000000011ec1b l 0e SECT 01 0000 [.text] _Tonga_RestoreAdapterCfgRegisters 000000000011ec66 l 0e SECT 01 0000 [.text] _tonga_set_reg_in_uvd_dpg_mode 000000000011eca5 l 0e SECT 01 0000 [.text] _tonga_set_uvd_dynamic_clock_mode_in_dpg_mode 000000000011ed05 l 0e SECT 01 0000 [.text] _tonga_set_vce_light_sleep 000000000011ed4c l 0e SECT 01 0000 [.text] _tonga_set_vce_sw_clock_gating 000000000011eeea l 0e SECT 01 0000 [.text] _tonga_set_vce_dyn_clock_gating 000000000011efff l 0e SECT 01 0000 [.text] _tonga_override_vce_clock_gating 000000000011f046 l 0e SECT 01 0000 [.text] _tonga_perform_srbm_soft_reset 000000000011f0b8 l 0e SECT 01 0000 [.text] _tonga_register_update_for_asic_sku 000000000011f48b l 0e SECT 01 0000 [.text] _tonga_init_ECC 000000000011f4e8 l 0e SECT 01 0000 [.text] _tonga_init_ucode_buffer 000000000011f525 l 0e SECT 01 0000 [.text] _tonga_halt_rlc 000000000011f52d l 0e SECT 01 0000 [.text] _tonga_reset_rlc 000000000011f54c l 0e SECT 01 0000 [.text] _tonga_init_power_gating 000000000011f5c4 l 0e SECT 01 0000 [.text] _tonga_init_LBPW 000000000011f678 l 0e SECT 01 0000 [.text] _tonga_init_nonsurf_aperture 000000000011f683 l 0e SECT 01 0000 [.text] _tonga_program_PCIE_Gen3 000000000011f68e l 0e SECT 01 0000 [.text] _tonga_program_pcie_link_width 000000000011f699 l 0e SECT 01 0000 [.text] _tonga_init_uvd_clocks 000000000011f6a4 l 0e SECT 01 0000 [.text] _tonga_init_vce_clocks 000000000011f6af l 0e SECT 01 0000 [.text] _tonga_init_acp_clocks 000000000011f6ba l 0e SECT 01 0000 [.text] _tonga_init_samu_clocks 000000000011f6c5 l 0e SECT 01 0000 [.text] _tonga_restore_audio_enablement 000000000011f719 l 0e SECT 01 0000 [.text] _cail_tonga_force_ECCV2 000000000011f8fb l 0e SECT 01 0000 [.text] _tonga_program_samu_sw_clock_gating 000000000012108c l 0e SECT 01 0000 [.text] _NotImplemented 0000000000123ed2 l 0e SECT 01 0000 [.text] __ZN25AMDRadeonX4000_IAMDSMLUVD9MetaClassD1Ev 0000000000123fcc l 0e SECT 01 0000 [.text] __ZN25AMDRadeonX4000_IAMDSMLDRM9MetaClassD1Ev 00000000001240c6 l 0e SECT 01 0000 [.text] __ZN25AMDRadeonX4000_IAMDSMLSPU9MetaClassD1Ev 00000000001241c0 l 0e SECT 01 0000 [.text] __ZN25AMDRadeonX4000_IAMDSMLVCE9MetaClassD1Ev 00000000001242ba l 0e SECT 01 0000 [.text] __ZN31AMDRadeonX4000_IAMDSMLInterface9MetaClassD1Ev 0000000000124362 l 0e SECT 01 0000 [.text] __ZN25AMDRadeonX4000_IAMDSMLUVD4initEv 0000000000124374 l 0e SECT 01 0000 [.text] __ZN25AMDRadeonX4000_IAMDSMLUVD4freeEv 0000000000124386 l 0e SECT 01 0000 [.text] __ZN25AMDRadeonX4000_IAMDSMLDRM4initEv 0000000000124398 l 0e SECT 01 0000 [.text] __ZN25AMDRadeonX4000_IAMDSMLDRM4freeEv 00000000001243aa l 0e SECT 01 0000 [.text] __ZN25AMDRadeonX4000_IAMDSMLSPU4initEv 00000000001243bc l 0e SECT 01 0000 [.text] __ZN25AMDRadeonX4000_IAMDSMLSPU4freeEv 00000000001243ce l 0e SECT 01 0000 [.text] __ZN25AMDRadeonX4000_IAMDSMLVCE4initEv 00000000001243e0 l 0e SECT 01 0000 [.text] __ZN25AMDRadeonX4000_IAMDSMLVCE4freeEv 00000000001243f2 l 0e SECT 01 0000 [.text] __ZN31AMDRadeonX4000_IAMDSMLInterface4initEv 0000000000124404 l 0e SECT 01 0000 [.text] __ZN31AMDRadeonX4000_IAMDSMLInterface4freeEv 0000000000124416 l 0e SECT 01 0000 [.text] __ZN25AMDRadeonX4000_IAMDSMLUVD9MetaClassD0Ev 0000000000124420 l 0e SECT 01 0000 [.text] __ZN25AMDRadeonX4000_IAMDSMLDRM9MetaClassD0Ev 000000000012442a l 0e SECT 01 0000 [.text] __ZN25AMDRadeonX4000_IAMDSMLSPU9MetaClassD0Ev 0000000000124434 l 0e SECT 01 0000 [.text] __ZN25AMDRadeonX4000_IAMDSMLVCE9MetaClassD0Ev 000000000012443e l 0e SECT 01 0000 [.text] __ZN31AMDRadeonX4000_IAMDSMLInterface9MetaClassD0Ev 0000000000124450 l 0e SECT 01 0000 [.text] __GLOBAL__I_a 0000000000124540 l 0e SECT 01 0000 [.text] __GLOBAL__D_a 00000000001245c2 l 0e SECT 01 0000 [.text] __ZN30AMDRadeonX4000_AMDSMLInterface9MetaClassD1Ev 0000000000124c20 l 0e SECT 01 0000 [.text] __ZN30AMDRadeonX4000_AMDSMLInterface9MetaClassD0Ev 0000000000124c2a l 0e SECT 01 0000 [.text] __ZN31AMDRadeonX4000_IAMDSMLInterface4initEv 0000000000124c3c l 0e SECT 01 0000 [.text] __ZN30AMDRadeonX4000_AMDSMLInterface9createUVDEv 0000000000124c42 l 0e SECT 01 0000 [.text] __ZN30AMDRadeonX4000_AMDSMLInterface9createDRMEv 0000000000124c48 l 0e SECT 01 0000 [.text] __ZN30AMDRadeonX4000_AMDSMLInterface9createSPUEv 0000000000124c4e l 0e SECT 01 0000 [.text] __ZN30AMDRadeonX4000_AMDSMLInterface9createVCEEv 0000000000124c60 l 0e SECT 01 0000 [.text] __GLOBAL__I_a 0000000000124ca0 l 0e SECT 01 0000 [.text] __GLOBAL__D_a 0000000000124cf2 l 0e SECT 01 0000 [.text] __ZN24AMDRadeonX4000_AMDSMLUVD9MetaClassD1Ev 0000000000125472 l 0e SECT 01 0000 [.text] __ZN24AMDRadeonX4000_AMDSMLUVD9MetaClassD0Ev 000000000012547c l 0e SECT 01 0000 [.text] __ZN25AMDRadeonX4000_IAMDSMLUVD4initEv 0000000000125490 l 0e SECT 01 0000 [.text] __GLOBAL__I_a 00000000001254d0 l 0e SECT 01 0000 [.text] __GLOBAL__D_a 0000000000125522 l 0e SECT 01 0000 [.text] __ZN24AMDRadeonX4000_AMDSMLDRM9MetaClassD1Ev 00000000001256da l 0e SECT 01 0000 [.text] __ZN24AMDRadeonX4000_AMDSMLDRM9MetaClassD0Ev 00000000001256f0 l 0e SECT 01 0000 [.text] __GLOBAL__I_a 0000000000125730 l 0e SECT 01 0000 [.text] __GLOBAL__D_a 0000000000125782 l 0e SECT 01 0000 [.text] __ZN24AMDRadeonX4000_AMDSMLSPU9MetaClassD1Ev 00000000001258c6 l 0e SECT 01 0000 [.text] __ZN24AMDRadeonX4000_AMDSMLSPU9MetaClassD0Ev 00000000001258d0 l 0e SECT 01 0000 [.text] __ZN24AMDRadeonX4000_AMDSMLSPU22writeSetPremContentCmdEP15_SAMU_GPCOM_CMD 00000000001258e0 l 0e SECT 01 0000 [.text] __GLOBAL__I_a 0000000000125920 l 0e SECT 01 0000 [.text] __GLOBAL__D_a 0000000000125972 l 0e SECT 01 0000 [.text] __ZN27AMDRadeonX4000_AMDSMLSPUMsg9MetaClassD1Ev 0000000000125b72 l 0e SECT 01 0000 [.text] __ZN27AMDRadeonX4000_AMDSMLSPUMsg9MetaClassD0Ev 0000000000125b7c l 0e SECT 01 0000 [.text] __ZN27AMDRadeonX4000_AMDSMLSPUMsg6getMsgEv 0000000000125b84 l 0e SECT 01 0000 [.text] __ZN27AMDRadeonX4000_AMDSMLSPUMsg10getMsgSizeEv 0000000000125b8e l 0e SECT 01 0000 [.text] __ZN27AMDRadeonX4000_AMDSMLSPUMsg13getMsgMemSizeEv 0000000000125b98 l 0e SECT 01 0000 [.text] __ZN27AMDRadeonX4000_AMDSMLSPUMsg12getMsgOffsetEv 0000000000125ba2 l 0e SECT 01 0000 [.text] __ZN27AMDRadeonX4000_AMDSMLSPUMsg10getBuffersEv 0000000000125bac l 0e SECT 01 0000 [.text] __ZN27AMDRadeonX4000_AMDSMLSPUMsg12setMsgBufferEy 0000000000125bb6 l 0e SECT 01 0000 [.text] __ZN27AMDRadeonX4000_AMDSMLSPUMsg12setOutBufferEiyPh 0000000000125bbc l 0e SECT 01 0000 [.text] __ZN27AMDRadeonX4000_AMDSMLSPUMsg9getOutputEv 0000000000125bc2 l 0e SECT 01 0000 [.text] __ZN27AMDRadeonX4000_AMDSMLSPUMsg16getOutputMemSizeEi 0000000000125bd4 l 0e SECT 01 0000 [.text] __ZN27AMDRadeonX4000_AMDSMLSPUMsg17getOutputDataSizeEi 0000000000125be6 l 0e SECT 01 0000 [.text] __ZN27AMDRadeonX4000_AMDSMLSPUMsg16getNumOutBuffersEv 0000000000125bf0 l 0e SECT 01 0000 [.text] __GLOBAL__I_a 0000000000125c30 l 0e SECT 01 0000 [.text] __GLOBAL__D_a 0000000000125c92 l 0e SECT 01 0000 [.text] __ZN24AMDRadeonX4000_AMDSMLVCE9MetaClassD1Ev 0000000000125ffc l 0e SECT 01 0000 [.text] __ZN24AMDRadeonX4000_AMDSMLVCE9MetaClassD0Ev 0000000000126006 l 0e SECT 01 0000 [.text] __ZN25AMDRadeonX4000_IAMDSMLVCE4initEv 0000000000126020 l 0e SECT 01 0000 [.text] __GLOBAL__I_a 0000000000126060 l 0e SECT 01 0000 [.text] __GLOBAL__D_a 00000000001260b2 l 0e SECT 01 0000 [.text] __ZN36AMDRadeonX4000_AMDHDCPOpenSessionMsg9MetaClassD1Ev 00000000001263a8 l 0e SECT 01 0000 [.text] __ZN37AMDRadeonX4000_AMDHDCPCloseSessionMsg9MetaClassD1Ev 00000000001265da l 0e SECT 01 0000 [.text] __ZN34AMDRadeonX4000_AMDHDCPGetStatusMsg9MetaClassD1Ev 00000000001268e8 l 0e SECT 01 0000 [.text] __ZN32AMDRadeonX4000_AMDHDCPGetCertMsg9MetaClassD1Ev 0000000000126b88 l 0e SECT 01 0000 [.text] __ZN30AMDRadeonX4000_AMDFPGetCertMsg9MetaClassD1Ev 0000000000126e6a l 0e SECT 01 0000 [.text] __ZN29AMDRadeonX4000_AMDFPGenKeyMsg9MetaClassD1Ev 00000000001271b0 l 0e SECT 01 0000 [.text] __ZN30AMDRadeonX4000_AMDFPTestKeyMsg9MetaClassD1Ev 000000000012749c l 0e SECT 01 0000 [.text] __ZN37AMDRadeonX4000_AMDFPReleaseSessionMsg9MetaClassD1Ev 00000000001276ce l 0e SECT 01 0000 [.text] __ZN30AMDRadeonX4000_AMDFPEncryptMsg9MetaClassD1Ev 00000000001279f2 l 0e SECT 01 0000 [.text] __ZN36AMDRadeonX4000_AMDHDCPOpenSessionMsg9MetaClassD0Ev 00000000001279fc l 0e SECT 01 0000 [.text] __ZN36AMDRadeonX4000_AMDHDCPOpenSessionMsg6getMsgEv 0000000000127a0a l 0e SECT 01 0000 [.text] __ZN27AMDRadeonX4000_AMDSMLSPUMsg10getMsgSizeEv 0000000000127a14 l 0e SECT 01 0000 [.text] __ZN27AMDRadeonX4000_AMDSMLSPUMsg13getMsgMemSizeEv 0000000000127a1e l 0e SECT 01 0000 [.text] __ZN27AMDRadeonX4000_AMDSMLSPUMsg12getMsgOffsetEv 0000000000127a28 l 0e SECT 01 0000 [.text] __ZN27AMDRadeonX4000_AMDSMLSPUMsg10getBuffersEv 0000000000127a32 l 0e SECT 01 0000 [.text] __ZN27AMDRadeonX4000_AMDSMLSPUMsg12setMsgBufferEy 0000000000127a3c l 0e SECT 01 0000 [.text] __ZN27AMDRadeonX4000_AMDSMLSPUMsg16getOutputMemSizeEi 0000000000127a4e l 0e SECT 01 0000 [.text] __ZN27AMDRadeonX4000_AMDSMLSPUMsg17getOutputDataSizeEi 0000000000127a60 l 0e SECT 01 0000 [.text] __ZN27AMDRadeonX4000_AMDSMLSPUMsg16getNumOutBuffersEv 0000000000127a6a l 0e SECT 01 0000 [.text] __ZN37AMDRadeonX4000_AMDHDCPCloseSessionMsg9MetaClassD0Ev 0000000000127a74 l 0e SECT 01 0000 [.text] __ZN37AMDRadeonX4000_AMDHDCPCloseSessionMsg6getMsgEv 0000000000127a82 l 0e SECT 01 0000 [.text] __ZN27AMDRadeonX4000_AMDSMLSPUMsg12setOutBufferEiyPh 0000000000127a88 l 0e SECT 01 0000 [.text] __ZN27AMDRadeonX4000_AMDSMLSPUMsg9getOutputEv 0000000000127a8e l 0e SECT 01 0000 [.text] __ZN34AMDRadeonX4000_AMDHDCPGetStatusMsg9MetaClassD0Ev 0000000000127a98 l 0e SECT 01 0000 [.text] __ZN34AMDRadeonX4000_AMDHDCPGetStatusMsg6getMsgEv 0000000000127aa6 l 0e SECT 01 0000 [.text] __ZN32AMDRadeonX4000_AMDHDCPGetCertMsg9MetaClassD0Ev 0000000000127ab0 l 0e SECT 01 0000 [.text] __ZN32AMDRadeonX4000_AMDHDCPGetCertMsg6getMsgEv 0000000000127abe l 0e SECT 01 0000 [.text] __ZN30AMDRadeonX4000_AMDFPGetCertMsg9MetaClassD0Ev 0000000000127ac8 l 0e SECT 01 0000 [.text] __ZN30AMDRadeonX4000_AMDFPGetCertMsg6getMsgEv 0000000000127ad6 l 0e SECT 01 0000 [.text] __ZN29AMDRadeonX4000_AMDFPGenKeyMsg9MetaClassD0Ev 0000000000127ae0 l 0e SECT 01 0000 [.text] __ZN29AMDRadeonX4000_AMDFPGenKeyMsg6getMsgEv 0000000000127aee l 0e SECT 01 0000 [.text] __ZN30AMDRadeonX4000_AMDFPTestKeyMsg9MetaClassD0Ev 0000000000127af8 l 0e SECT 01 0000 [.text] __ZN30AMDRadeonX4000_AMDFPTestKeyMsg6getMsgEv 0000000000127b06 l 0e SECT 01 0000 [.text] __ZN37AMDRadeonX4000_AMDFPReleaseSessionMsg9MetaClassD0Ev 0000000000127b10 l 0e SECT 01 0000 [.text] __ZN37AMDRadeonX4000_AMDFPReleaseSessionMsg6getMsgEv 0000000000127b1e l 0e SECT 01 0000 [.text] __ZN30AMDRadeonX4000_AMDFPEncryptMsg9MetaClassD0Ev 0000000000127b28 l 0e SECT 01 0000 [.text] __ZN30AMDRadeonX4000_AMDFPEncryptMsg6getMsgEv 0000000000127b40 l 0e SECT 01 0000 [.text] __GLOBAL__I_a 0000000000127cd0 l 0e SECT 01 0000 [.text] __GLOBAL__D_a 0000000000127d82 l 0e SECT 01 0000 [.text] __ZN32AMDRadeonX4000_AMDSMLSIInterface9MetaClassD1Ev 0000000000127fa6 l 0e SECT 01 0000 [.text] __ZN32AMDRadeonX4000_AMDSMLSIInterface9MetaClassD0Ev 0000000000127fb0 l 0e SECT 01 0000 [.text] __ZN31AMDRadeonX4000_IAMDSMLInterface4initEv 0000000000127fd0 l 0e SECT 01 0000 [.text] __GLOBAL__I_a 0000000000128010 l 0e SECT 01 0000 [.text] __GLOBAL__D_a 0000000000128062 l 0e SECT 01 0000 [.text] __ZN28AMDRadeonX4000_AMDUVDTrinity9MetaClassD1Ev 0000000000128248 l 0e SECT 01 0000 [.text] __ZN28AMDRadeonX4000_AMDUVDTrinity9MetaClassD0Ev 0000000000128252 l 0e SECT 01 0000 [.text] __ZN25AMDRadeonX4000_IAMDSMLUVD4initEv 0000000000128270 l 0e SECT 01 0000 [.text] __GLOBAL__I_a 00000000001282b0 l 0e SECT 01 0000 [.text] __GLOBAL__D_a 0000000000128302 l 0e SECT 01 0000 [.text] __ZN23AMDRadeonX4000_AMDSIDRM9MetaClassD1Ev 0000000000128c38 l 0e SECT 01 0000 [.text] __ZN23AMDRadeonX4000_AMDSIDRM9MetaClassD0Ev 0000000000128c50 l 0e SECT 01 0000 [.text] __GLOBAL__I_a 0000000000128c90 l 0e SECT 01 0000 [.text] __GLOBAL__D_a 0000000000128ce2 l 0e SECT 01 0000 [.text] __ZN23AMDRadeonX4000_AMDSISPU9MetaClassD1Ev 000000000012937e l 0e SECT 01 0000 [.text] __ZN23AMDRadeonX4000_AMDSISPU9MetaClassD0Ev 0000000000129388 l 0e SECT 01 0000 [.text] __ZN24AMDRadeonX4000_AMDSMLSPU22writeSetPremContentCmdEP15_SAMU_GPCOM_CMD 0000000000129390 l 0e SECT 01 0000 [.text] __GLOBAL__I_a 00000000001293d0 l 0e SECT 01 0000 [.text] __GLOBAL__D_a 0000000000129422 l 0e SECT 01 0000 [.text] __ZN23AMDRadeonX4000_AMDSIVCE9MetaClassD1Ev 000000000012977a l 0e SECT 01 0000 [.text] __ZN23AMDRadeonX4000_AMDSIVCE9MetaClassD0Ev 0000000000129784 l 0e SECT 01 0000 [.text] __ZN25AMDRadeonX4000_IAMDSMLVCE4initEv 00000000001297a0 l 0e SECT 01 0000 [.text] __GLOBAL__I_a 00000000001297e0 l 0e SECT 01 0000 [.text] __GLOBAL__D_a 0000000000129832 l 0e SECT 01 0000 [.text] __ZN33AMDRadeonX4000_AMDSMLCIKInterface9MetaClassD1Ev 0000000000129a56 l 0e SECT 01 0000 [.text] __ZN33AMDRadeonX4000_AMDSMLCIKInterface9MetaClassD0Ev 0000000000129a60 l 0e SECT 01 0000 [.text] __ZN31AMDRadeonX4000_IAMDSMLInterface4initEv 0000000000129a80 l 0e SECT 01 0000 [.text] __GLOBAL__I_a 0000000000129ac0 l 0e SECT 01 0000 [.text] __GLOBAL__D_a 0000000000129b12 l 0e SECT 01 0000 [.text] __ZN24AMDRadeonX4000_AMDUVDCIK9MetaClassD1Ev 0000000000129eaa l 0e SECT 01 0000 [.text] __ZN24AMDRadeonX4000_AMDUVDCIK9MetaClassD0Ev 0000000000129eb4 l 0e SECT 01 0000 [.text] __ZN25AMDRadeonX4000_IAMDSMLUVD4initEv 0000000000129ed0 l 0e SECT 01 0000 [.text] __GLOBAL__I_a 0000000000129f10 l 0e SECT 01 0000 [.text] __GLOBAL__D_a 0000000000129f62 l 0e SECT 01 0000 [.text] __ZN24AMDRadeonX4000_AMDCIKDRM9MetaClassD1Ev 000000000012a934 l 0e SECT 01 0000 [.text] __ZN24AMDRadeonX4000_AMDCIKDRM9MetaClassD0Ev 000000000012a940 l 0e SECT 01 0000 [.text] __GLOBAL__I_a 000000000012a980 l 0e SECT 01 0000 [.text] __GLOBAL__D_a 000000000012a9d2 l 0e SECT 01 0000 [.text] __ZN24AMDRadeonX4000_AMDCIKSPU9MetaClassD1Ev 000000000012b100 l 0e SECT 01 0000 [.text] __ZN24AMDRadeonX4000_AMDCIKSPU9MetaClassD0Ev 000000000012b110 l 0e SECT 01 0000 [.text] __GLOBAL__I_a 000000000012b150 l 0e SECT 01 0000 [.text] __GLOBAL__D_a 000000000012b1a2 l 0e SECT 01 0000 [.text] __ZN24AMDRadeonX4000_AMDCIKVCE9MetaClassD1Ev 000000000012b3d6 l 0e SECT 01 0000 [.text] __ZN24AMDRadeonX4000_AMDCIKVCE9MetaClassD0Ev 000000000012b3e0 l 0e SECT 01 0000 [.text] __ZN25AMDRadeonX4000_IAMDSMLVCE4initEv 000000000012b400 l 0e SECT 01 0000 [.text] __GLOBAL__I_a 000000000012b440 l 0e SECT 01 0000 [.text] __GLOBAL__D_a 000000000012b492 l 0e SECT 01 0000 [.text] __ZN32AMDRadeonX4000_AMDSMLVIInterface9MetaClassD1Ev 000000000012b6b6 l 0e SECT 01 0000 [.text] __ZN32AMDRadeonX4000_AMDSMLVIInterface9MetaClassD0Ev 000000000012b6c0 l 0e SECT 01 0000 [.text] __ZN31AMDRadeonX4000_IAMDSMLInterface4initEv 000000000012b6e0 l 0e SECT 01 0000 [.text] __GLOBAL__I_a 000000000012b720 l 0e SECT 01 0000 [.text] __GLOBAL__D_a 000000000012b772 l 0e SECT 01 0000 [.text] __ZN23AMDRadeonX4000_AMDUVDVI9MetaClassD1Ev 000000000012b910 l 0e SECT 01 0000 [.text] __ZN23AMDRadeonX4000_AMDUVDVI9MetaClassD0Ev 000000000012b91a l 0e SECT 01 0000 [.text] __ZN25AMDRadeonX4000_IAMDSMLUVD4initEv 000000000012b930 l 0e SECT 01 0000 [.text] __GLOBAL__I_a 000000000012b970 l 0e SECT 01 0000 [.text] __GLOBAL__D_a 000000000012b9c2 l 0e SECT 01 0000 [.text] __ZN23AMDRadeonX4000_AMDVIDRM9MetaClassD1Ev 000000000012c394 l 0e SECT 01 0000 [.text] __ZN23AMDRadeonX4000_AMDVIDRM9MetaClassD0Ev 000000000012c3a0 l 0e SECT 01 0000 [.text] __GLOBAL__I_a 000000000012c3e0 l 0e SECT 01 0000 [.text] __GLOBAL__D_a 000000000012c432 l 0e SECT 01 0000 [.text] __ZN23AMDRadeonX4000_AMDVISPU9MetaClassD1Ev 000000000012c61c l 0e SECT 01 0000 [.text] __ZN23AMDRadeonX4000_AMDVISPU9MetaClassD0Ev 000000000012c630 l 0e SECT 01 0000 [.text] __GLOBAL__I_a 000000000012c670 l 0e SECT 01 0000 [.text] __GLOBAL__D_a 000000000012c6c2 l 0e SECT 01 0000 [.text] __ZN23AMDRadeonX4000_AMDVIVCE9MetaClassD1Ev 000000000012c92e l 0e SECT 01 0000 [.text] __ZN23AMDRadeonX4000_AMDVIVCE9MetaClassD0Ev 000000000012c938 l 0e SECT 01 0000 [.text] __ZN25AMDRadeonX4000_IAMDSMLVCE4initEv 000000000012c950 l 0e SECT 01 0000 [.text] __GLOBAL__I_a 000000000012c990 l 0e SECT 01 0000 [.text] __GLOBAL__D_a 000000000012f630 l 0e SECT 03 0000 [.const] __ZL28g_AMDGraphicsAcceleratorName 000000000012f66c l 0e SECT 03 0000 [.const] __ZL13tokenArgSizes 000000000012f6a0 l 0e SECT 03 0000 [.const] __ZL15deviceTypeTable 000000000012f6d0 l 0e SECT 03 0000 [.const] __ZL15deviceTypeTable 000000000012f700 l 0e SECT 03 0000 [.const] __ZL18tokenArgSizeVaries 000000000012f710 l 0e SECT 03 0000 [.const] __ZL13tokenArgSizes 000000000012f740 l 0e SECT 03 0000 [.const] __ZZN14AMDSIGLContext31write_kernel_render_target_regsEPjE16hwLog2NumSamples 000000000012f790 l 0e SECT 03 0000 [.const] __ZZL10getDbZInfoPK31AMDRadeonX4000_AMDAccelResourcejbbP19SI_HwWorkAroundsRecE16hwLog2NumSamples 000000000012f7e0 l 0e SECT 03 0000 [.const] __ZL13tokenArgSizes 000000000012f800 l 0e SECT 03 0000 [.const] __ZZN14AMDSICLContext13getPixelBytesEjjE10pixelBytes 000000000012fee0 l 0e SECT 03 0000 [.const] __ZL13tokenArgSizes 000000000012fef0 l 0e SECT 03 0000 [.const] __ZZN14AMDCICLContext13getPixelBytesEjjE10pixelBytes 00000000001305d0 l 0e SECT 03 0000 [.const] __ZL15deviceTypeTable 00000000001305e8 l 0e SECT 03 0000 [.const] __ZZN27AMDRadeonX4000_AMDHWChannel20initStatisticsGroupsEvE11channelName 0000000000130a40 l 0e SECT 03 0000 [.const] __ZZN12AMDSIDisplay12getPixelModeEjjE14pixelModeTable 0000000000130b30 l 0e SECT 03 0000 [.const] __ZZN13AMDSIHardware25programPageTableRegistersEP22AMD_VM_PAGE_TABLE_INFOjE25VM_CONTEXT_BASE_ADDRESSES 0000000000130b70 l 0e SECT 03 0000 [.const] __ZN35AMD_SI_ASIC_HANG_LOG_DUMP_REGISTERSL24asicHangLogDumpRegistersE 0000000000131400 l 0e SECT 03 0000 [.const] __ZN35AMD_SI_ASIC_HANG_LOG_DUMP_REGISTERSL36asicHangLogDumpReorderQueueRegistersE 0000000000131470 l 0e SECT 03 0000 [.const] __ZN35AMD_SI_ASIC_HANG_LOG_DUMP_REGISTERSL36asicHangLogDumpMeStateQueueRegistersE 00000000001314e0 l 0e SECT 03 0000 [.const] __ZN12TAHITI_UCODEL14aF32_PFP_UcodeE 0000000000133660 l 0e SECT 03 0000 [.const] __ZN12TAHITI_UCODEL13aF32_ME_UcodeE 00000000001357e0 l 0e SECT 03 0000 [.const] __ZN12TAHITI_UCODEL13aF32_CE_UcodeE 0000000000137960 l 0e SECT 03 0000 [.const] __ZN14PITCAIRN_UCODEL14aF32_PFP_UcodeE 0000000000139ae0 l 0e SECT 03 0000 [.const] __ZN14PITCAIRN_UCODEL13aF32_ME_UcodeE 000000000013bc60 l 0e SECT 03 0000 [.const] __ZN14PITCAIRN_UCODEL13aF32_CE_UcodeE 000000000013dde0 l 0e SECT 03 0000 [.const] __ZN11VERDE_UCODEL14aF32_PFP_UcodeE 000000000013ff60 l 0e SECT 03 0000 [.const] __ZN11VERDE_UCODEL13aF32_ME_UcodeE 00000000001420e0 l 0e SECT 03 0000 [.const] __ZN11VERDE_UCODEL13aF32_CE_UcodeE 0000000000144260 l 0e SECT 03 0000 [.const] __ZZN15AMDSIDMAChannel18submitVMInvalidateEjyjE25VM_CONTEXT_BASE_ADDRESSES 00000000001442c0 l 0e SECT 03 0000 [.const] __ZZN13AMDCIHardware25programPageTableRegistersEP22AMD_VM_PAGE_TABLE_INFOjE25VM_CONTEXT_BASE_ADDRESSES 0000000000144300 l 0e SECT 03 0000 [.const] __ZN35AMD_CI_ASIC_HANG_LOG_DUMP_REGISTERSL24asicHangLogDumpRegistersE 0000000000144ba0 l 0e SECT 03 0000 [.const] __ZN35AMD_CI_ASIC_HANG_LOG_DUMP_REGISTERSL36asicHangLogDumpReorderQueueRegistersE 0000000000144bd0 l 0e SECT 03 0000 [.const] __ZN35AMD_CI_ASIC_HANG_LOG_DUMP_REGISTERSL36asicHangLogDumpMeStateQueueRegistersE 0000000000144c30 l 0e SECT 03 0000 [.const] __ZL15engineRingTable 00000000001450a0 l 0e SECT 03 0000 [.const] __ZZN12AMDCIDisplay12getPixelModeEjjE14pixelModeTable 0000000000145160 l 0e SECT 03 0000 [.const] __ZZN15AMDCIDMAChannel18submitVMInvalidateEjyjE25VM_CONTEXT_BASE_ADDRESSES 0000000000145260 l 0e SECT 03 0000 [.const] __ZZN13AMDVIHardware25programPageTableRegistersEP22AMD_VM_PAGE_TABLE_INFOjE25VM_CONTEXT_BASE_ADDRESSES 00000000001452a0 l 0e SECT 03 0000 [.const] __ZN35AMD_VI_ASIC_HANG_LOG_DUMP_REGISTERSL24asicHangLogDumpRegistersE 0000000000145b40 l 0e SECT 03 0000 [.const] __ZN35AMD_VI_ASIC_HANG_LOG_DUMP_REGISTERSL36asicHangLogDumpReorderQueueRegistersE 0000000000145b70 l 0e SECT 03 0000 [.const] __ZN35AMD_VI_ASIC_HANG_LOG_DUMP_REGISTERSL36asicHangLogDumpMeStateQueueRegistersE 0000000000145fe0 l 0e SECT 03 0000 [.const] __ZZN12AMDVIDisplay12getPixelModeEjjE14pixelModeTable 00000000001460b0 l 0e SECT 03 0000 [.const] __ZZN16AMDVIsDMAChannel18submitVMInvalidateEjyjE25VM_CONTEXT_BASE_ADDRESSES 00000000001460f0 l 0e SECT 03 0000 [.const] __ZL15engineRingTable 00000000001463f0 l 0e SECT 03 0000 [.const] _bp 0000000000146400 l 0e SECT 03 0000 [.const] _dp_l 0000000000146410 l 0e SECT 03 0000 [.const] _dp_h 0000000000146420 l 0e SECT 03 0000 [.const] ___qdivrem.zero 00000000001464a0 l 0e SECT 03 0000 [.const] __ZZN6BltMgr29SelectAAResolveTentFilterTapsEP7BltInfojfP22AAResolveTapDescriptorjE10pixOffsets 00000000001464c8 l 0e SECT 03 0000 [.const] __ZZN6BltMgr18DesktopCompositionEP9BltDeviceP27_UBM_DESKTOPCOMPOSITIONINFOE14StdGrayWeights 000000000014658c l 0e SECT 03 0000 [.const] __ZL15Desc_NOT_PACKED 0000000000146608 l 0e SECT 03 0000 [.const] __ZL27Desc_SPLIT_G70_B54__R70_B10 0000000000146684 l 0e SECT 03 0000 [.const] __ZL27Desc_SPLIT_B70_G10__R70_G76 0000000000146700 l 0e SECT 03 0000 [.const] __ZL21Desc_G70_B54__R70_B10 000000000014677c l 0e SECT 03 0000 [.const] __ZL21Desc_B70_R32__G70_R76 00000000001467f8 l 0e SECT 03 0000 [.const] __ZL21Desc_B70_R30__G70_R74 0000000000146874 l 0e SECT 03 0000 [.const] __ZL18Desc_B70__G70__R70 00000000001468f0 l 0e SECT 03 0000 [.const] __ZL12Desc_R70_G76 000000000014696c l 0e SECT 03 0000 [.const] __ZL12Desc_G70_B54 00000000001469e8 l 0e SECT 03 0000 [.const] __ZL11Desc_NATIVE 0000000000146bc0 l 0e SECT 03 0000 [.const] __ZL10CRC32Table 0000000000146fe0 l 0e SECT 03 0000 [.const] __ZZN11SiBltDevice26WaitOnFlushAndInvTimestampEvE16ClearedTimestamp 0000000000146fe4 l 0e SECT 03 0000 [.const] __ZZN11SiBltDevice12WaitOnCsDoneEvE16ClearedTimestamp 0000000000146ff0 l 0e SECT 03 0000 [.const] __ZL16ViContextRegDefs 0000000000147050 l 0e SECT 03 0000 [.const] __ZL16CiContextRegDefs 00000000001470b0 l 0e SECT 03 0000 [.const] __ZL16SiContextRegDefs 0000000000147110 l 0e SECT 03 0000 [.const] __ZL18siGfxShaderRegDefs 0000000000147130 l 0e SECT 03 0000 [.const] __ZL22SiComputeShaderRegDefs 00000000001471d4 l 0e SECT 03 0000 [.const] __ZL21UbmDefaultPatchHandle 00000000001471e0 l 0e SECT 03 0000 [.const] __ZZN13SiBltDrawRegs22SetupAndWriteClipRectsEPK7BltInfoPK10_UBM_RECTLjE8ClipRule 0000000000147200 l 0e SECT 03 0000 [.const] __ZZN13SiBltDrawRegs31SetupAndWriteCentroidPrioritiesEPK7BltInfoE26pDefaultCentroidPriorities 0000000000147240 l 0e SECT 03 0000 [.const] __ZZN13SiBltDrawRegs15SetupAlphaBlendEPK7BltInfoE23SiUbmBlendModeToHwTable 0000000000147330 l 0e SECT 03 0000 [.const] __ZL19RectToVertTransform 0000000000147360 l 0e SECT 03 0000 [.const] __ZL14TransposeRect0 00000000001473b0 l 0e SECT 03 0000 [.const] __ZL15TransposeRect90 0000000000147400 l 0e SECT 03 0000 [.const] __ZL16TransposeRect180 0000000000147450 l 0e SECT 03 0000 [.const] __ZL16TransposeRect270 00000000001474a0 l 0e SECT 03 0000 [.const] __ZZN8SiBltMgr27SetupRectPosTexTexConstantsEPK7BltInfoE22MirrorTransformDefault 00000000001474b0 l 0e SECT 03 0000 [.const] __ZL14VertRotation90 00000000001474c0 l 0e SECT 03 0000 [.const] __ZL15VertRotation180 00000000001474d0 l 0e SECT 03 0000 [.const] __ZL15VertRotation270 00000000001474e0 l 0e SECT 03 0000 [.const] __ZZN8SiBltMgr23HwlGetDefaultSampleLocsEjE13SiSampleLocs2 00000000001474f0 l 0e SECT 03 0000 [.const] __ZZN8SiBltMgr23HwlGetDefaultSampleLocsEjE13SiSampleLocs4 0000000000147510 l 0e SECT 03 0000 [.const] __ZZN8SiBltMgr23HwlGetDefaultSampleLocsEjE13SiSampleLocs8 0000000000147550 l 0e SECT 03 0000 [.const] __ZZN8SiBltMgr23HwlGetDefaultSampleLocsEjE14SiSampleLocs16 00000000001475d0 l 0e SECT 03 0000 [.const] __ZZN8SiBltMgr23HwlGetDefaultSampleLocsEjE17SiQuadSampleLocs2 0000000000147610 l 0e SECT 03 0000 [.const] __ZZN8SiBltMgr23HwlGetDefaultSampleLocsEjE17SiQuadSampleLocs4 0000000000147690 l 0e SECT 03 0000 [.const] __ZZN8SiBltMgr23HwlGetDefaultSampleLocsEjE17SiQuadSampleLocs8 0000000000147790 l 0e SECT 03 0000 [.const] __ZZN8SiBltMgr23HwlGetDefaultSampleLocsEjE18SiQuadSampleLocs16 0000000000147990 l 0e SECT 03 0000 [.const] __ZZN8SiBltMgr22SetupDitherTextureDataEPK13_UBM_SURFINFOE9DitherTex 0000000000147d90 l 0e SECT 03 0000 [.const] __ZZNK11SiBltResFmt9GetDstSelE11_UBM_FORMATjjE16CompSwizToDstSel 00000000001482e0 l 0e SECT 03 0000 [.const] __ZL25gShaderCode_si_RectPos_VS 00000000001483e0 l 0e SECT 03 0000 [.const] __ZL26gShRegisters_si_RectPos_VS 00000000001483f0 l 0e SECT 03 0000 [.const] __ZL31gContextRegisters_si_RectPos_VS 0000000000148400 l 0e SECT 03 0000 [.const] __ZL31gUserElementTable_si_RectPos_VS 0000000000148430 l 0e SECT 03 0000 [.const] __ZL27gOutSemantics_si_RectPos_VS 0000000000148440 l 0e SECT 03 0000 [.const] __ZL31gShaderCode_si_RectPosTexTex_VS 0000000000148780 l 0e SECT 03 0000 [.const] __ZL32gShRegisters_si_RectPosTexTex_VS 0000000000148790 l 0e SECT 03 0000 [.const] __ZL37gContextRegisters_si_RectPosTexTex_VS 00000000001487a0 l 0e SECT 03 0000 [.const] __ZL37gUserElementTable_si_RectPosTexTex_VS 00000000001487d0 l 0e SECT 03 0000 [.const] __ZL33gOutSemantics_si_RectPosTexTex_VS 00000000001487f0 l 0e SECT 03 0000 [.const] __ZL32gShaderCode_si_RectPosTexFast_VS 0000000000148880 l 0e SECT 03 0000 [.const] __ZL33gShRegisters_si_RectPosTexFast_VS 0000000000148890 l 0e SECT 03 0000 [.const] __ZL38gContextRegisters_si_RectPosTexFast_VS 00000000001488a0 l 0e SECT 03 0000 [.const] __ZL38gUserElementTable_si_RectPosTexFast_VS 0000000000148900 l 0e SECT 03 0000 [.const] __ZL34gOutSemantics_si_RectPosTexFast_VS 0000000000148910 l 0e SECT 03 0000 [.const] __ZL30gShaderCode_si_VertPosColor_VS 0000000000148960 l 0e SECT 03 0000 [.const] __ZL31gShRegisters_si_VertPosColor_VS 0000000000148970 l 0e SECT 03 0000 [.const] __ZL36gContextRegisters_si_VertPosColor_VS 0000000000148980 l 0e SECT 03 0000 [.const] __ZL36gUserElementTable_si_VertPosColor_VS 00000000001489b0 l 0e SECT 03 0000 [.const] __ZL32gOutSemantics_si_VertPosColor_VS 00000000001489c0 l 0e SECT 03 0000 [.const] __ZL40gShaderCode_si_RectPosTexTexComposite_VS 0000000000148b40 l 0e SECT 03 0000 [.const] __ZL41gShRegisters_si_RectPosTexTexComposite_VS 0000000000148b50 l 0e SECT 03 0000 [.const] __ZL46gContextRegisters_si_RectPosTexTexComposite_VS 0000000000148b60 l 0e SECT 03 0000 [.const] __ZL46gUserElementTable_si_RectPosTexTexComposite_VS 0000000000148b90 l 0e SECT 03 0000 [.const] __ZL42gOutSemantics_si_RectPosTexTexComposite_VS 0000000000148bb0 l 0e SECT 03 0000 [.const] __ZL22gShaderCode_si_Zero_PS 0000000000148bd0 l 0e SECT 03 0000 [.const] __ZL23gShRegisters_si_Zero_PS 0000000000148be0 l 0e SECT 03 0000 [.const] __ZL28gContextRegisters_si_Zero_PS 0000000000148c20 l 0e SECT 03 0000 [.const] __ZL28gUserElementTable_si_Zero_PS 0000000000148c40 l 0e SECT 03 0000 [.const] __ZL23gInSemantics_si_Zero_PS 0000000000148c54 l 0e SECT 03 0000 [.const] __ZL27gPatchInfoOffset_si_Zero_PS 0000000000148c60 l 0e SECT 03 0000 [.const] __ZL25gPatchInfoCode_si_Zero_PS 0000000000148d00 l 0e SECT 03 0000 [.const] __ZL23gShaderCode_si_Const_PS 0000000000148d30 l 0e SECT 03 0000 [.const] __ZL24gShRegisters_si_Const_PS 0000000000148d40 l 0e SECT 03 0000 [.const] __ZL29gContextRegisters_si_Const_PS 0000000000148d80 l 0e SECT 03 0000 [.const] __ZL29gUserElementTable_si_Const_PS 0000000000148da0 l 0e SECT 03 0000 [.const] __ZL24gInSemantics_si_Const_PS 0000000000148db4 l 0e SECT 03 0000 [.const] __ZL28gPatchInfoOffset_si_Const_PS 0000000000148dc0 l 0e SECT 03 0000 [.const] __ZL26gPatchInfoCode_si_Const_PS 0000000000148e60 l 0e SECT 03 0000 [.const] __ZL21gShaderCode_si_Tex_PS 0000000000148ea0 l 0e SECT 03 0000 [.const] __ZL22gShRegisters_si_Tex_PS 0000000000148eb0 l 0e SECT 03 0000 [.const] __ZL27gContextRegisters_si_Tex_PS 0000000000148ef0 l 0e SECT 03 0000 [.const] __ZL27gUserElementTable_si_Tex_PS 0000000000148f20 l 0e SECT 03 0000 [.const] __ZL22gInSemantics_si_Tex_PS 0000000000148f34 l 0e SECT 03 0000 [.const] __ZL26gPatchInfoOffset_si_Tex_PS 0000000000148f40 l 0e SECT 03 0000 [.const] __ZL24gPatchInfoCode_si_Tex_PS 0000000000148fe0 l 0e SECT 03 0000 [.const] __ZL26gShaderCode_si_TexCoord_PS 0000000000149020 l 0e SECT 03 0000 [.const] __ZL27gShRegisters_si_TexCoord_PS 0000000000149030 l 0e SECT 03 0000 [.const] __ZL32gContextRegisters_si_TexCoord_PS 0000000000149070 l 0e SECT 03 0000 [.const] __ZL32gUserElementTable_si_TexCoord_PS 0000000000149090 l 0e SECT 03 0000 [.const] __ZL27gInSemantics_si_TexCoord_PS 00000000001490a4 l 0e SECT 03 0000 [.const] __ZL31gPatchInfoOffset_si_TexCoord_PS 00000000001490b0 l 0e SECT 03 0000 [.const] __ZL29gPatchInfoCode_si_TexCoord_PS 0000000000149150 l 0e SECT 03 0000 [.const] __ZL29gShaderCode_si_TexGammaDst_PS 0000000000149250 l 0e SECT 03 0000 [.const] __ZL30gShRegisters_si_TexGammaDst_PS 0000000000149260 l 0e SECT 03 0000 [.const] __ZL35gContextRegisters_si_TexGammaDst_PS 00000000001492a0 l 0e SECT 03 0000 [.const] __ZL35gUserElementTable_si_TexGammaDst_PS 00000000001492d0 l 0e SECT 03 0000 [.const] __ZL30gInSemantics_si_TexGammaDst_PS 00000000001492e4 l 0e SECT 03 0000 [.const] __ZL34gPatchInfoOffset_si_TexGammaDst_PS 00000000001492f0 l 0e SECT 03 0000 [.const] __ZL32gPatchInfoCode_si_TexGammaDst_PS 0000000000149390 l 0e SECT 03 0000 [.const] __ZL30gShaderCode_si_MsaaResolve1_PS 00000000001493d0 l 0e SECT 03 0000 [.const] __ZL31gShRegisters_si_MsaaResolve1_PS 00000000001493e0 l 0e SECT 03 0000 [.const] __ZL36gContextRegisters_si_MsaaResolve1_PS 0000000000149420 l 0e SECT 03 0000 [.const] __ZL36gUserElementTable_si_MsaaResolve1_PS 0000000000149450 l 0e SECT 03 0000 [.const] __ZL31gInSemantics_si_MsaaResolve1_PS 0000000000149464 l 0e SECT 03 0000 [.const] __ZL35gPatchInfoOffset_si_MsaaResolve1_PS 0000000000149470 l 0e SECT 03 0000 [.const] __ZL33gPatchInfoCode_si_MsaaResolve1_PS 0000000000149510 l 0e SECT 03 0000 [.const] __ZL30gShaderCode_si_MsaaResolve2_PS 0000000000149580 l 0e SECT 03 0000 [.const] __ZL31gShRegisters_si_MsaaResolve2_PS 0000000000149590 l 0e SECT 03 0000 [.const] __ZL36gContextRegisters_si_MsaaResolve2_PS 00000000001495d0 l 0e SECT 03 0000 [.const] __ZL36gUserElementTable_si_MsaaResolve2_PS 0000000000149600 l 0e SECT 03 0000 [.const] __ZL31gInSemantics_si_MsaaResolve2_PS 0000000000149614 l 0e SECT 03 0000 [.const] __ZL35gPatchInfoOffset_si_MsaaResolve2_PS 0000000000149620 l 0e SECT 03 0000 [.const] __ZL33gPatchInfoCode_si_MsaaResolve2_PS 00000000001496c0 l 0e SECT 03 0000 [.const] __ZL30gShaderCode_si_MsaaResolve4_PS 0000000000149770 l 0e SECT 03 0000 [.const] __ZL31gShRegisters_si_MsaaResolve4_PS 0000000000149780 l 0e SECT 03 0000 [.const] __ZL36gContextRegisters_si_MsaaResolve4_PS 00000000001497c0 l 0e SECT 03 0000 [.const] __ZL36gUserElementTable_si_MsaaResolve4_PS 00000000001497f0 l 0e SECT 03 0000 [.const] __ZL31gInSemantics_si_MsaaResolve4_PS 0000000000149804 l 0e SECT 03 0000 [.const] __ZL35gPatchInfoOffset_si_MsaaResolve4_PS 0000000000149810 l 0e SECT 03 0000 [.const] __ZL33gPatchInfoCode_si_MsaaResolve4_PS 00000000001498b0 l 0e SECT 03 0000 [.const] __ZL30gShaderCode_si_MsaaResolve8_PS 00000000001499e0 l 0e SECT 03 0000 [.const] __ZL31gShRegisters_si_MsaaResolve8_PS 00000000001499f0 l 0e SECT 03 0000 [.const] __ZL36gContextRegisters_si_MsaaResolve8_PS 0000000000149a30 l 0e SECT 03 0000 [.const] __ZL36gUserElementTable_si_MsaaResolve8_PS 0000000000149a60 l 0e SECT 03 0000 [.const] __ZL31gInSemantics_si_MsaaResolve8_PS 0000000000149a74 l 0e SECT 03 0000 [.const] __ZL35gPatchInfoOffset_si_MsaaResolve8_PS 0000000000149a80 l 0e SECT 03 0000 [.const] __ZL33gPatchInfoCode_si_MsaaResolve8_PS 0000000000149b20 l 0e SECT 03 0000 [.const] __ZL33gShaderCode_si_MsaaFMaskExpand_PS 0000000000149ba0 l 0e SECT 03 0000 [.const] __ZL34gShRegisters_si_MsaaFMaskExpand_PS 0000000000149bb0 l 0e SECT 03 0000 [.const] __ZL39gContextRegisters_si_MsaaFMaskExpand_PS 0000000000149bf0 l 0e SECT 03 0000 [.const] __ZL39gUserElementTable_si_MsaaFMaskExpand_PS 0000000000149c20 l 0e SECT 03 0000 [.const] __ZL34gInSemantics_si_MsaaFMaskExpand_PS 0000000000149c34 l 0e SECT 03 0000 [.const] __ZL38gPatchInfoOffset_si_MsaaFMaskExpand_PS 0000000000149c40 l 0e SECT 03 0000 [.const] __ZL36gPatchInfoCode_si_MsaaFMaskExpand_PS 0000000000149ce0 l 0e SECT 03 0000 [.const] __ZL34gShaderCode_si_MsaaDepthResolve_PS 0000000000149d20 l 0e SECT 03 0000 [.const] __ZL35gShRegisters_si_MsaaDepthResolve_PS 0000000000149d30 l 0e SECT 03 0000 [.const] __ZL40gContextRegisters_si_MsaaDepthResolve_PS 0000000000149d70 l 0e SECT 03 0000 [.const] __ZL40gUserElementTable_si_MsaaDepthResolve_PS 0000000000149da0 l 0e SECT 03 0000 [.const] __ZL35gInSemantics_si_MsaaDepthResolve_PS 0000000000149db4 l 0e SECT 03 0000 [.const] __ZL39gPatchInfoOffset_si_MsaaDepthResolve_PS 0000000000149dc0 l 0e SECT 03 0000 [.const] __ZL37gPatchInfoCode_si_MsaaDepthResolve_PS 0000000000149e60 l 0e SECT 03 0000 [.const] __ZL41gShaderCode_si_MsaaDepthStencilResolve_PS 0000000000149ec0 l 0e SECT 03 0000 [.const] __ZL42gShRegisters_si_MsaaDepthStencilResolve_PS 0000000000149ed0 l 0e SECT 03 0000 [.const] __ZL47gContextRegisters_si_MsaaDepthStencilResolve_PS 0000000000149f10 l 0e SECT 03 0000 [.const] __ZL47gUserElementTable_si_MsaaDepthStencilResolve_PS 0000000000149f60 l 0e SECT 03 0000 [.const] __ZL42gInSemantics_si_MsaaDepthStencilResolve_PS 0000000000149f74 l 0e SECT 03 0000 [.const] __ZL46gPatchInfoOffset_si_MsaaDepthStencilResolve_PS 0000000000149f80 l 0e SECT 03 0000 [.const] __ZL44gPatchInfoCode_si_MsaaDepthStencilResolve_PS 000000000014a020 l 0e SECT 03 0000 [.const] __ZL36gShaderCode_si_TexZStencilAsColor_PS 000000000014a080 l 0e SECT 03 0000 [.const] __ZL37gShRegisters_si_TexZStencilAsColor_PS 000000000014a090 l 0e SECT 03 0000 [.const] __ZL42gContextRegisters_si_TexZStencilAsColor_PS 000000000014a0d0 l 0e SECT 03 0000 [.const] __ZL42gUserElementTable_si_TexZStencilAsColor_PS 000000000014a120 l 0e SECT 03 0000 [.const] __ZL37gInSemantics_si_TexZStencilAsColor_PS 000000000014a134 l 0e SECT 03 0000 [.const] __ZL41gPatchInfoOffset_si_TexZStencilAsColor_PS 000000000014a140 l 0e SECT 03 0000 [.const] __ZL39gPatchInfoCode_si_TexZStencilAsColor_PS 000000000014a1e0 l 0e SECT 03 0000 [.const] __ZL40gShaderCode_si_MsaaTexZStencilAsColor_PS 000000000014a240 l 0e SECT 03 0000 [.const] __ZL41gShRegisters_si_MsaaTexZStencilAsColor_PS 000000000014a250 l 0e SECT 03 0000 [.const] __ZL46gContextRegisters_si_MsaaTexZStencilAsColor_PS 000000000014a290 l 0e SECT 03 0000 [.const] __ZL46gUserElementTable_si_MsaaTexZStencilAsColor_PS 000000000014a2b0 l 0e SECT 03 0000 [.const] __ZL41gInSemantics_si_MsaaTexZStencilAsColor_PS 000000000014a2c4 l 0e SECT 03 0000 [.const] __ZL45gPatchInfoOffset_si_MsaaTexZStencilAsColor_PS 000000000014a2d0 l 0e SECT 03 0000 [.const] __ZL43gPatchInfoCode_si_MsaaTexZStencilAsColor_PS 000000000014a370 l 0e SECT 03 0000 [.const] __ZL24gShaderCode_si_TexAsZ_PS 000000000014a3b0 l 0e SECT 03 0000 [.const] __ZL25gShRegisters_si_TexAsZ_PS 000000000014a3c0 l 0e SECT 03 0000 [.const] __ZL30gContextRegisters_si_TexAsZ_PS 000000000014a400 l 0e SECT 03 0000 [.const] __ZL30gUserElementTable_si_TexAsZ_PS 000000000014a430 l 0e SECT 03 0000 [.const] __ZL25gInSemantics_si_TexAsZ_PS 000000000014a444 l 0e SECT 03 0000 [.const] __ZL29gPatchInfoOffset_si_TexAsZ_PS 000000000014a450 l 0e SECT 03 0000 [.const] __ZL27gPatchInfoCode_si_TexAsZ_PS 000000000014a4f0 l 0e SECT 03 0000 [.const] __ZL31gShaderCode_si_TexAsZStencil_PS 000000000014a550 l 0e SECT 03 0000 [.const] __ZL32gShRegisters_si_TexAsZStencil_PS 000000000014a560 l 0e SECT 03 0000 [.const] __ZL37gContextRegisters_si_TexAsZStencil_PS 000000000014a5a0 l 0e SECT 03 0000 [.const] __ZL37gUserElementTable_si_TexAsZStencil_PS 000000000014a5f0 l 0e SECT 03 0000 [.const] __ZL32gInSemantics_si_TexAsZStencil_PS 000000000014a604 l 0e SECT 03 0000 [.const] __ZL36gPatchInfoOffset_si_TexAsZStencil_PS 000000000014a610 l 0e SECT 03 0000 [.const] __ZL34gPatchInfoCode_si_TexAsZStencil_PS 000000000014a6b0 l 0e SECT 03 0000 [.const] __ZL28gShaderCode_si_MsaaTexAsZ_PS 000000000014a700 l 0e SECT 03 0000 [.const] __ZL29gShRegisters_si_MsaaTexAsZ_PS 000000000014a710 l 0e SECT 03 0000 [.const] __ZL34gContextRegisters_si_MsaaTexAsZ_PS 000000000014a750 l 0e SECT 03 0000 [.const] __ZL34gUserElementTable_si_MsaaTexAsZ_PS 000000000014a780 l 0e SECT 03 0000 [.const] __ZL29gInSemantics_si_MsaaTexAsZ_PS 000000000014a794 l 0e SECT 03 0000 [.const] __ZL33gPatchInfoOffset_si_MsaaTexAsZ_PS 000000000014a7a0 l 0e SECT 03 0000 [.const] __ZL31gPatchInfoCode_si_MsaaTexAsZ_PS 000000000014a840 l 0e SECT 03 0000 [.const] __ZL35gShaderCode_si_MsaaTexAsZStencil_PS 000000000014a8a0 l 0e SECT 03 0000 [.const] __ZL36gShRegisters_si_MsaaTexAsZStencil_PS 000000000014a8b0 l 0e SECT 03 0000 [.const] __ZL41gContextRegisters_si_MsaaTexAsZStencil_PS 000000000014a8f0 l 0e SECT 03 0000 [.const] __ZL41gUserElementTable_si_MsaaTexAsZStencil_PS 000000000014a940 l 0e SECT 03 0000 [.const] __ZL36gInSemantics_si_MsaaTexAsZStencil_PS 000000000014a954 l 0e SECT 03 0000 [.const] __ZL40gPatchInfoOffset_si_MsaaTexAsZStencil_PS 000000000014a960 l 0e SECT 03 0000 [.const] __ZL38gPatchInfoCode_si_MsaaTexAsZStencil_PS 000000000014aa00 l 0e SECT 03 0000 [.const] __ZL24gShaderCode_si_VolTex_PS 000000000014aa50 l 0e SECT 03 0000 [.const] __ZL25gShRegisters_si_VolTex_PS 000000000014aa60 l 0e SECT 03 0000 [.const] __ZL30gContextRegisters_si_VolTex_PS 000000000014aaa0 l 0e SECT 03 0000 [.const] __ZL30gUserElementTable_si_VolTex_PS 000000000014aad0 l 0e SECT 03 0000 [.const] __ZL25gInSemantics_si_VolTex_PS 000000000014aae4 l 0e SECT 03 0000 [.const] __ZL29gPatchInfoOffset_si_VolTex_PS 000000000014aaf0 l 0e SECT 03 0000 [.const] __ZL27gPatchInfoCode_si_VolTex_PS 000000000014ab90 l 0e SECT 03 0000 [.const] __ZL24gShaderCode_si_AAText_PS 000000000014ac60 l 0e SECT 03 0000 [.const] __ZL25gShRegisters_si_AAText_PS 000000000014ac70 l 0e SECT 03 0000 [.const] __ZL30gContextRegisters_si_AAText_PS 000000000014acb0 l 0e SECT 03 0000 [.const] __ZL30gUserElementTable_si_AAText_PS 000000000014ad00 l 0e SECT 03 0000 [.const] __ZL25gInSemantics_si_AAText_PS 000000000014ad14 l 0e SECT 03 0000 [.const] __ZL29gPatchInfoOffset_si_AAText_PS 000000000014ad20 l 0e SECT 03 0000 [.const] __ZL27gPatchInfoCode_si_AAText_PS 000000000014adc0 l 0e SECT 03 0000 [.const] __ZL28gShaderCode_si_SlowAAText_PS 000000000014ae80 l 0e SECT 03 0000 [.const] __ZL29gShRegisters_si_SlowAAText_PS 000000000014ae90 l 0e SECT 03 0000 [.const] __ZL34gContextRegisters_si_SlowAAText_PS 000000000014aed0 l 0e SECT 03 0000 [.const] __ZL34gUserElementTable_si_SlowAAText_PS 000000000014af30 l 0e SECT 03 0000 [.const] __ZL29gInSemantics_si_SlowAAText_PS 000000000014af58 l 0e SECT 03 0000 [.const] __ZL33gPatchInfoOffset_si_SlowAAText_PS 000000000014af60 l 0e SECT 03 0000 [.const] __ZL31gPatchInfoCode_si_SlowAAText_PS 000000000014b000 l 0e SECT 03 0000 [.const] __ZL32gShaderCode_si_ClearTypeGamma_PS 000000000014b180 l 0e SECT 03 0000 [.const] __ZL33gShRegisters_si_ClearTypeGamma_PS 000000000014b190 l 0e SECT 03 0000 [.const] __ZL38gContextRegisters_si_ClearTypeGamma_PS 000000000014b1d0 l 0e SECT 03 0000 [.const] __ZL38gUserElementTable_si_ClearTypeGamma_PS 000000000014b220 l 0e SECT 03 0000 [.const] __ZL33gInSemantics_si_ClearTypeGamma_PS 000000000014b248 l 0e SECT 03 0000 [.const] __ZL37gPatchInfoOffset_si_ClearTypeGamma_PS 000000000014b250 l 0e SECT 03 0000 [.const] __ZL35gPatchInfoCode_si_ClearTypeGamma_PS 000000000014b2f0 l 0e SECT 03 0000 [.const] __ZL29gShaderCode_si_TexColorKey_PS 000000000014b430 l 0e SECT 03 0000 [.const] __ZL30gShRegisters_si_TexColorKey_PS 000000000014b440 l 0e SECT 03 0000 [.const] __ZL35gContextRegisters_si_TexColorKey_PS 000000000014b480 l 0e SECT 03 0000 [.const] __ZL35gUserElementTable_si_TexColorKey_PS 000000000014b4e0 l 0e SECT 03 0000 [.const] __ZL30gInSemantics_si_TexColorKey_PS 000000000014b508 l 0e SECT 03 0000 [.const] __ZL34gPatchInfoOffset_si_TexColorKey_PS 000000000014b510 l 0e SECT 03 0000 [.const] __ZL32gPatchInfoCode_si_TexColorKey_PS 000000000014b5b0 l 0e SECT 03 0000 [.const] __ZL32gShaderCode_si_TexSrcColorKey_PS 000000000014b670 l 0e SECT 03 0000 [.const] __ZL33gShRegisters_si_TexSrcColorKey_PS 000000000014b680 l 0e SECT 03 0000 [.const] __ZL38gContextRegisters_si_TexSrcColorKey_PS 000000000014b6c0 l 0e SECT 03 0000 [.const] __ZL38gUserElementTable_si_TexSrcColorKey_PS 000000000014b710 l 0e SECT 03 0000 [.const] __ZL33gInSemantics_si_TexSrcColorKey_PS 000000000014b724 l 0e SECT 03 0000 [.const] __ZL37gPatchInfoOffset_si_TexSrcColorKey_PS 000000000014b730 l 0e SECT 03 0000 [.const] __ZL35gPatchInfoCode_si_TexSrcColorKey_PS 000000000014b7d0 l 0e SECT 03 0000 [.const] __ZL29gShaderCode_si_TexMulConst_PS 000000000014b830 l 0e SECT 03 0000 [.const] __ZL30gShRegisters_si_TexMulConst_PS 000000000014b840 l 0e SECT 03 0000 [.const] __ZL35gContextRegisters_si_TexMulConst_PS 000000000014b880 l 0e SECT 03 0000 [.const] __ZL35gUserElementTable_si_TexMulConst_PS 000000000014b8d0 l 0e SECT 03 0000 [.const] __ZL30gInSemantics_si_TexMulConst_PS 000000000014b8e4 l 0e SECT 03 0000 [.const] __ZL34gPatchInfoOffset_si_TexMulConst_PS 000000000014b8f0 l 0e SECT 03 0000 [.const] __ZL32gPatchInfoCode_si_TexMulConst_PS 000000000014b990 l 0e SECT 03 0000 [.const] __ZL27gShaderCode_si_TexDither_PS 000000000014ba00 l 0e SECT 03 0000 [.const] __ZL28gShRegisters_si_TexDither_PS 000000000014ba10 l 0e SECT 03 0000 [.const] __ZL33gContextRegisters_si_TexDither_PS 000000000014ba50 l 0e SECT 03 0000 [.const] __ZL33gUserElementTable_si_TexDither_PS 000000000014bab0 l 0e SECT 03 0000 [.const] __ZL28gInSemantics_si_TexDither_PS 000000000014bac4 l 0e SECT 03 0000 [.const] __ZL32gPatchInfoOffset_si_TexDither_PS 000000000014bad0 l 0e SECT 03 0000 [.const] __ZL30gPatchInfoCode_si_TexDither_PS 000000000014bb70 l 0e SECT 03 0000 [.const] __ZL26gShaderCode_si_YuvToRgb_PS 000000000014bc40 l 0e SECT 03 0000 [.const] __ZL27gShRegisters_si_YuvToRgb_PS 000000000014bc50 l 0e SECT 03 0000 [.const] __ZL32gContextRegisters_si_YuvToRgb_PS 000000000014bc90 l 0e SECT 03 0000 [.const] __ZL32gUserElementTable_si_YuvToRgb_PS 000000000014bce0 l 0e SECT 03 0000 [.const] __ZL27gInSemantics_si_YuvToRgb_PS 000000000014bcf4 l 0e SECT 03 0000 [.const] __ZL31gPatchInfoOffset_si_YuvToRgb_PS 000000000014bd00 l 0e SECT 03 0000 [.const] __ZL29gPatchInfoCode_si_YuvToRgb_PS 000000000014bda0 l 0e SECT 03 0000 [.const] __ZL31gShaderCode_si_YuvIntUvToRgb_PS 000000000014be50 l 0e SECT 03 0000 [.const] __ZL32gShRegisters_si_YuvIntUvToRgb_PS 000000000014be60 l 0e SECT 03 0000 [.const] __ZL37gContextRegisters_si_YuvIntUvToRgb_PS 000000000014bea0 l 0e SECT 03 0000 [.const] __ZL37gUserElementTable_si_YuvIntUvToRgb_PS 000000000014bf00 l 0e SECT 03 0000 [.const] __ZL32gInSemantics_si_YuvIntUvToRgb_PS 000000000014bf14 l 0e SECT 03 0000 [.const] __ZL36gPatchInfoOffset_si_YuvIntUvToRgb_PS 000000000014bf20 l 0e SECT 03 0000 [.const] __ZL34gPatchInfoCode_si_YuvIntUvToRgb_PS 000000000014bfc0 l 0e SECT 03 0000 [.const] __ZL32gShaderCode_si_YuvIntUvToYuy2_PS 000000000014c060 l 0e SECT 03 0000 [.const] __ZL33gShRegisters_si_YuvIntUvToYuy2_PS 000000000014c070 l 0e SECT 03 0000 [.const] __ZL38gContextRegisters_si_YuvIntUvToYuy2_PS 000000000014c0b0 l 0e SECT 03 0000 [.const] __ZL38gUserElementTable_si_YuvIntUvToYuy2_PS 000000000014c110 l 0e SECT 03 0000 [.const] __ZL33gInSemantics_si_YuvIntUvToYuy2_PS 000000000014c124 l 0e SECT 03 0000 [.const] __ZL37gPatchInfoOffset_si_YuvIntUvToYuy2_PS 000000000014c130 l 0e SECT 03 0000 [.const] __ZL35gPatchInfoCode_si_YuvIntUvToYuy2_PS 000000000014c1d0 l 0e SECT 03 0000 [.const] __ZL27gShaderCode_si_YuvToYuy2_PS 000000000014c280 l 0e SECT 03 0000 [.const] __ZL28gShRegisters_si_YuvToYuy2_PS 000000000014c290 l 0e SECT 03 0000 [.const] __ZL33gContextRegisters_si_YuvToYuy2_PS 000000000014c2d0 l 0e SECT 03 0000 [.const] __ZL33gUserElementTable_si_YuvToYuy2_PS 000000000014c320 l 0e SECT 03 0000 [.const] __ZL28gInSemantics_si_YuvToYuy2_PS 000000000014c334 l 0e SECT 03 0000 [.const] __ZL32gPatchInfoOffset_si_YuvToYuy2_PS 000000000014c340 l 0e SECT 03 0000 [.const] __ZL30gPatchInfoCode_si_YuvToYuy2_PS 000000000014c3e0 l 0e SECT 03 0000 [.const] __ZL35gShaderCode_si_MsaaFMaskResolve2_PS 000000000014c480 l 0e SECT 03 0000 [.const] __ZL36gShRegisters_si_MsaaFMaskResolve2_PS 000000000014c490 l 0e SECT 03 0000 [.const] __ZL41gContextRegisters_si_MsaaFMaskResolve2_PS 000000000014c4d0 l 0e SECT 03 0000 [.const] __ZL41gUserElementTable_si_MsaaFMaskResolve2_PS 000000000014c500 l 0e SECT 03 0000 [.const] __ZL36gInSemantics_si_MsaaFMaskResolve2_PS 000000000014c514 l 0e SECT 03 0000 [.const] __ZL40gPatchInfoOffset_si_MsaaFMaskResolve2_PS 000000000014c520 l 0e SECT 03 0000 [.const] __ZL38gPatchInfoCode_si_MsaaFMaskResolve2_PS 000000000014c5c0 l 0e SECT 03 0000 [.const] __ZL35gShaderCode_si_MsaaFMaskResolve4_PS 000000000014c6f0 l 0e SECT 03 0000 [.const] __ZL36gShRegisters_si_MsaaFMaskResolve4_PS 000000000014c700 l 0e SECT 03 0000 [.const] __ZL41gContextRegisters_si_MsaaFMaskResolve4_PS 000000000014c740 l 0e SECT 03 0000 [.const] __ZL41gUserElementTable_si_MsaaFMaskResolve4_PS 000000000014c770 l 0e SECT 03 0000 [.const] __ZL36gInSemantics_si_MsaaFMaskResolve4_PS 000000000014c784 l 0e SECT 03 0000 [.const] __ZL40gPatchInfoOffset_si_MsaaFMaskResolve4_PS 000000000014c790 l 0e SECT 03 0000 [.const] __ZL38gPatchInfoCode_si_MsaaFMaskResolve4_PS 000000000014c830 l 0e SECT 03 0000 [.const] __ZL35gShaderCode_si_MsaaFMaskResolve8_PS 000000000014ca00 l 0e SECT 03 0000 [.const] __ZL36gShRegisters_si_MsaaFMaskResolve8_PS 000000000014ca10 l 0e SECT 03 0000 [.const] __ZL41gContextRegisters_si_MsaaFMaskResolve8_PS 000000000014ca50 l 0e SECT 03 0000 [.const] __ZL41gUserElementTable_si_MsaaFMaskResolve8_PS 000000000014ca80 l 0e SECT 03 0000 [.const] __ZL36gInSemantics_si_MsaaFMaskResolve8_PS 000000000014ca94 l 0e SECT 03 0000 [.const] __ZL40gPatchInfoOffset_si_MsaaFMaskResolve8_PS 000000000014caa0 l 0e SECT 03 0000 [.const] __ZL38gPatchInfoCode_si_MsaaFMaskResolve8_PS 000000000014cb40 l 0e SECT 03 0000 [.const] __ZL44gShaderCode_si_MsaaFMaskResolve2Frag4Samp_PS 000000000014cce0 l 0e SECT 03 0000 [.const] __ZL45gShRegisters_si_MsaaFMaskResolve2Frag4Samp_PS 000000000014ccf0 l 0e SECT 03 0000 [.const] __ZL50gContextRegisters_si_MsaaFMaskResolve2Frag4Samp_PS 000000000014cd30 l 0e SECT 03 0000 [.const] __ZL50gUserElementTable_si_MsaaFMaskResolve2Frag4Samp_PS 000000000014cd60 l 0e SECT 03 0000 [.const] __ZL45gInSemantics_si_MsaaFMaskResolve2Frag4Samp_PS 000000000014cd74 l 0e SECT 03 0000 [.const] __ZL49gPatchInfoOffset_si_MsaaFMaskResolve2Frag4Samp_PS 000000000014cd80 l 0e SECT 03 0000 [.const] __ZL47gPatchInfoCode_si_MsaaFMaskResolve2Frag4Samp_PS 000000000014ce20 l 0e SECT 03 0000 [.const] __ZL44gShaderCode_si_MsaaFMaskResolve2Frag8Samp_PS 000000000014d160 l 0e SECT 03 0000 [.const] __ZL45gShRegisters_si_MsaaFMaskResolve2Frag8Samp_PS 000000000014d170 l 0e SECT 03 0000 [.const] __ZL50gContextRegisters_si_MsaaFMaskResolve2Frag8Samp_PS 000000000014d1b0 l 0e SECT 03 0000 [.const] __ZL50gUserElementTable_si_MsaaFMaskResolve2Frag8Samp_PS 000000000014d1e0 l 0e SECT 03 0000 [.const] __ZL45gInSemantics_si_MsaaFMaskResolve2Frag8Samp_PS 000000000014d1f4 l 0e SECT 03 0000 [.const] __ZL49gPatchInfoOffset_si_MsaaFMaskResolve2Frag8Samp_PS 000000000014d200 l 0e SECT 03 0000 [.const] __ZL47gPatchInfoCode_si_MsaaFMaskResolve2Frag8Samp_PS 000000000014d2a0 l 0e SECT 03 0000 [.const] __ZL45gShaderCode_si_MsaaFMaskResolve2Frag16Samp_PS 000000000014d930 l 0e SECT 03 0000 [.const] __ZL46gShRegisters_si_MsaaFMaskResolve2Frag16Samp_PS 000000000014d940 l 0e SECT 03 0000 [.const] __ZL51gContextRegisters_si_MsaaFMaskResolve2Frag16Samp_PS 000000000014d980 l 0e SECT 03 0000 [.const] __ZL51gUserElementTable_si_MsaaFMaskResolve2Frag16Samp_PS 000000000014d9b0 l 0e SECT 03 0000 [.const] __ZL46gInSemantics_si_MsaaFMaskResolve2Frag16Samp_PS 000000000014d9c4 l 0e SECT 03 0000 [.const] __ZL50gPatchInfoOffset_si_MsaaFMaskResolve2Frag16Samp_PS 000000000014d9d0 l 0e SECT 03 0000 [.const] __ZL48gPatchInfoCode_si_MsaaFMaskResolve2Frag16Samp_PS 000000000014da70 l 0e SECT 03 0000 [.const] __ZL44gShaderCode_si_MsaaFMaskResolve4Frag8Samp_PS 000000000014dd30 l 0e SECT 03 0000 [.const] __ZL45gShRegisters_si_MsaaFMaskResolve4Frag8Samp_PS 000000000014dd40 l 0e SECT 03 0000 [.const] __ZL50gContextRegisters_si_MsaaFMaskResolve4Frag8Samp_PS 000000000014dd80 l 0e SECT 03 0000 [.const] __ZL50gUserElementTable_si_MsaaFMaskResolve4Frag8Samp_PS 000000000014ddb0 l 0e SECT 03 0000 [.const] __ZL45gInSemantics_si_MsaaFMaskResolve4Frag8Samp_PS 000000000014ddc4 l 0e SECT 03 0000 [.const] __ZL49gPatchInfoOffset_si_MsaaFMaskResolve4Frag8Samp_PS 000000000014ddd0 l 0e SECT 03 0000 [.const] __ZL47gPatchInfoCode_si_MsaaFMaskResolve4Frag8Samp_PS 000000000014de70 l 0e SECT 03 0000 [.const] __ZL45gShaderCode_si_MsaaFMaskResolve4Frag16Samp_PS 000000000014e480 l 0e SECT 03 0000 [.const] __ZL46gShRegisters_si_MsaaFMaskResolve4Frag16Samp_PS 000000000014e490 l 0e SECT 03 0000 [.const] __ZL51gContextRegisters_si_MsaaFMaskResolve4Frag16Samp_PS 000000000014e4d0 l 0e SECT 03 0000 [.const] __ZL51gUserElementTable_si_MsaaFMaskResolve4Frag16Samp_PS 000000000014e500 l 0e SECT 03 0000 [.const] __ZL46gInSemantics_si_MsaaFMaskResolve4Frag16Samp_PS 000000000014e514 l 0e SECT 03 0000 [.const] __ZL50gPatchInfoOffset_si_MsaaFMaskResolve4Frag16Samp_PS 000000000014e520 l 0e SECT 03 0000 [.const] __ZL48gPatchInfoCode_si_MsaaFMaskResolve4Frag16Samp_PS 000000000014e5c0 l 0e SECT 03 0000 [.const] __ZL45gShaderCode_si_MsaaFMaskResolve8Frag16Samp_PS 000000000014eb10 l 0e SECT 03 0000 [.const] __ZL46gShRegisters_si_MsaaFMaskResolve8Frag16Samp_PS 000000000014eb20 l 0e SECT 03 0000 [.const] __ZL51gContextRegisters_si_MsaaFMaskResolve8Frag16Samp_PS 000000000014eb60 l 0e SECT 03 0000 [.const] __ZL51gUserElementTable_si_MsaaFMaskResolve8Frag16Samp_PS 000000000014eb90 l 0e SECT 03 0000 [.const] __ZL46gInSemantics_si_MsaaFMaskResolve8Frag16Samp_PS 000000000014eba4 l 0e SECT 03 0000 [.const] __ZL50gPatchInfoOffset_si_MsaaFMaskResolve8Frag16Samp_PS 000000000014ebb0 l 0e SECT 03 0000 [.const] __ZL48gPatchInfoCode_si_MsaaFMaskResolve8Frag16Samp_PS 000000000014ec50 l 0e SECT 03 0000 [.const] __ZL32gShaderCode_si_ColorTransform_PS 000000000014eea0 l 0e SECT 03 0000 [.const] __ZL33gShRegisters_si_ColorTransform_PS 000000000014eeb0 l 0e SECT 03 0000 [.const] __ZL38gContextRegisters_si_ColorTransform_PS 000000000014eef0 l 0e SECT 03 0000 [.const] __ZL38gUserElementTable_si_ColorTransform_PS 000000000014ef40 l 0e SECT 03 0000 [.const] __ZL33gInSemantics_si_ColorTransform_PS 000000000014ef54 l 0e SECT 03 0000 [.const] __ZL37gPatchInfoOffset_si_ColorTransform_PS 000000000014ef60 l 0e SECT 03 0000 [.const] __ZL35gPatchInfoCode_si_ColorTransform_PS 000000000014f000 l 0e SECT 03 0000 [.const] __ZL39gShaderCode_si_NonEvenLinearFilter1D_PS 000000000014f130 l 0e SECT 03 0000 [.const] __ZL40gShRegisters_si_NonEvenLinearFilter1D_PS 000000000014f140 l 0e SECT 03 0000 [.const] __ZL45gContextRegisters_si_NonEvenLinearFilter1D_PS 000000000014f180 l 0e SECT 03 0000 [.const] __ZL45gUserElementTable_si_NonEvenLinearFilter1D_PS 000000000014f1d0 l 0e SECT 03 0000 [.const] __ZL40gInSemantics_si_NonEvenLinearFilter1D_PS 000000000014f1e4 l 0e SECT 03 0000 [.const] __ZL44gPatchInfoOffset_si_NonEvenLinearFilter1D_PS 000000000014f1f0 l 0e SECT 03 0000 [.const] __ZL42gPatchInfoCode_si_NonEvenLinearFilter1D_PS 000000000014f290 l 0e SECT 03 0000 [.const] __ZL39gShaderCode_si_NonEvenLinearFilter2D_PS 000000000014f4c0 l 0e SECT 03 0000 [.const] __ZL40gShRegisters_si_NonEvenLinearFilter2D_PS 000000000014f4d0 l 0e SECT 03 0000 [.const] __ZL45gContextRegisters_si_NonEvenLinearFilter2D_PS 000000000014f510 l 0e SECT 03 0000 [.const] __ZL45gUserElementTable_si_NonEvenLinearFilter2D_PS 000000000014f560 l 0e SECT 03 0000 [.const] __ZL40gInSemantics_si_NonEvenLinearFilter2D_PS 000000000014f574 l 0e SECT 03 0000 [.const] __ZL44gPatchInfoOffset_si_NonEvenLinearFilter2D_PS 000000000014f580 l 0e SECT 03 0000 [.const] __ZL42gPatchInfoCode_si_NonEvenLinearFilter2D_PS 000000000014f620 l 0e SECT 03 0000 [.const] __ZL39gShaderCode_si_NonEvenLinearFilter3D_PS 000000000014f930 l 0e SECT 03 0000 [.const] __ZL40gShRegisters_si_NonEvenLinearFilter3D_PS 000000000014f940 l 0e SECT 03 0000 [.const] __ZL45gContextRegisters_si_NonEvenLinearFilter3D_PS 000000000014f980 l 0e SECT 03 0000 [.const] __ZL45gUserElementTable_si_NonEvenLinearFilter3D_PS 000000000014f9d0 l 0e SECT 03 0000 [.const] __ZL40gInSemantics_si_NonEvenLinearFilter3D_PS 000000000014f9e4 l 0e SECT 03 0000 [.const] __ZL44gPatchInfoOffset_si_NonEvenLinearFilter3D_PS 000000000014f9f0 l 0e SECT 03 0000 [.const] __ZL42gPatchInfoCode_si_NonEvenLinearFilter3D_PS 000000000014fa90 l 0e SECT 03 0000 [.const] __ZL39gShaderCode_si_MLAACalcSepEdgeLength_PS 000000000014fea0 l 0e SECT 03 0000 [.const] __ZL40gShRegisters_si_MLAACalcSepEdgeLength_PS 000000000014feb0 l 0e SECT 03 0000 [.const] __ZL45gContextRegisters_si_MLAACalcSepEdgeLength_PS 000000000014fef0 l 0e SECT 03 0000 [.const] __ZL45gUserElementTable_si_MLAACalcSepEdgeLength_PS 000000000014ff20 l 0e SECT 03 0000 [.const] __ZL40gInSemantics_si_MLAACalcSepEdgeLength_PS 000000000014ff34 l 0e SECT 03 0000 [.const] __ZL44gPatchInfoOffset_si_MLAACalcSepEdgeLength_PS 000000000014ff40 l 0e SECT 03 0000 [.const] __ZL42gPatchInfoCode_si_MLAACalcSepEdgeLength_PS 0000000000150080 l 0e SECT 03 0000 [.const] __ZL43gShaderCode_si_MLAACalcSepEdgeLengthFast_PS 00000000001506f0 l 0e SECT 03 0000 [.const] __ZL44gShRegisters_si_MLAACalcSepEdgeLengthFast_PS 0000000000150700 l 0e SECT 03 0000 [.const] __ZL49gContextRegisters_si_MLAACalcSepEdgeLengthFast_PS 0000000000150740 l 0e SECT 03 0000 [.const] __ZL49gUserElementTable_si_MLAACalcSepEdgeLengthFast_PS 0000000000150770 l 0e SECT 03 0000 [.const] __ZL44gInSemantics_si_MLAACalcSepEdgeLengthFast_PS 0000000000150784 l 0e SECT 03 0000 [.const] __ZL48gPatchInfoOffset_si_MLAACalcSepEdgeLengthFast_PS 0000000000150790 l 0e SECT 03 0000 [.const] __ZL46gPatchInfoCode_si_MLAACalcSepEdgeLengthFast_PS 0000000000150830 l 0e SECT 03 0000 [.const] __ZL46gShaderCode_si_MLAACalcSepEdgeLengthInitial_PS 0000000000150a30 l 0e SECT 03 0000 [.const] __ZL47gShRegisters_si_MLAACalcSepEdgeLengthInitial_PS 0000000000150a40 l 0e SECT 03 0000 [.const] __ZL52gContextRegisters_si_MLAACalcSepEdgeLengthInitial_PS 0000000000150a80 l 0e SECT 03 0000 [.const] __ZL52gUserElementTable_si_MLAACalcSepEdgeLengthInitial_PS 0000000000150ab0 l 0e SECT 03 0000 [.const] __ZL47gInSemantics_si_MLAACalcSepEdgeLengthInitial_PS 0000000000150ac4 l 0e SECT 03 0000 [.const] __ZL51gPatchInfoOffset_si_MLAACalcSepEdgeLengthInitial_PS 0000000000150ad0 l 0e SECT 03 0000 [.const] __ZL49gPatchInfoCode_si_MLAACalcSepEdgeLengthInitial_PS 0000000000150c10 l 0e SECT 03 0000 [.const] __ZL32gShaderCode_si_MLAAFinalBlend_PS 0000000000151530 l 0e SECT 03 0000 [.const] __ZL33gShRegisters_si_MLAAFinalBlend_PS 0000000000151540 l 0e SECT 03 0000 [.const] __ZL38gContextRegisters_si_MLAAFinalBlend_PS 0000000000151580 l 0e SECT 03 0000 [.const] __ZL38gUserElementTable_si_MLAAFinalBlend_PS 00000000001515a0 l 0e SECT 03 0000 [.const] __ZL33gInSemantics_si_MLAAFinalBlend_PS 00000000001515b4 l 0e SECT 03 0000 [.const] __ZL37gPatchInfoOffset_si_MLAAFinalBlend_PS 00000000001515c0 l 0e SECT 03 0000 [.const] __ZL35gPatchInfoCode_si_MLAAFinalBlend_PS 0000000000151660 l 0e SECT 03 0000 [.const] __ZL36gShaderCode_si_MLAAFinalBlendFast_PS 0000000000152010 l 0e SECT 03 0000 [.const] __ZL37gShRegisters_si_MLAAFinalBlendFast_PS 0000000000152020 l 0e SECT 03 0000 [.const] __ZL42gContextRegisters_si_MLAAFinalBlendFast_PS 0000000000152060 l 0e SECT 03 0000 [.const] __ZL42gUserElementTable_si_MLAAFinalBlendFast_PS 0000000000152090 l 0e SECT 03 0000 [.const] __ZL37gInSemantics_si_MLAAFinalBlendFast_PS 00000000001520a4 l 0e SECT 03 0000 [.const] __ZL41gPatchInfoOffset_si_MLAAFinalBlendFast_PS 00000000001520b0 l 0e SECT 03 0000 [.const] __ZL39gPatchInfoCode_si_MLAAFinalBlendFast_PS 0000000000152150 l 0e SECT 03 0000 [.const] __ZL33gShaderCode_si_MLAAFindSepEdge_PS 0000000000152250 l 0e SECT 03 0000 [.const] __ZL34gShRegisters_si_MLAAFindSepEdge_PS 0000000000152260 l 0e SECT 03 0000 [.const] __ZL39gContextRegisters_si_MLAAFindSepEdge_PS 00000000001522a0 l 0e SECT 03 0000 [.const] __ZL39gUserElementTable_si_MLAAFindSepEdge_PS 00000000001522d0 l 0e SECT 03 0000 [.const] __ZL34gInSemantics_si_MLAAFindSepEdge_PS 00000000001522e4 l 0e SECT 03 0000 [.const] __ZL38gPatchInfoOffset_si_MLAAFindSepEdge_PS 00000000001522f0 l 0e SECT 03 0000 [.const] __ZL36gPatchInfoCode_si_MLAAFindSepEdge_PS 0000000000152390 l 0e SECT 03 0000 [.const] __ZL30gShaderCode_si_GenZRangeTex_PS 00000000001526f0 l 0e SECT 03 0000 [.const] __ZL31gShRegisters_si_GenZRangeTex_PS 0000000000152700 l 0e SECT 03 0000 [.const] __ZL36gContextRegisters_si_GenZRangeTex_PS 0000000000152740 l 0e SECT 03 0000 [.const] __ZL36gUserElementTable_si_GenZRangeTex_PS 0000000000152790 l 0e SECT 03 0000 [.const] __ZL31gInSemantics_si_GenZRangeTex_PS 00000000001527a4 l 0e SECT 03 0000 [.const] __ZL35gPatchInfoOffset_si_GenZRangeTex_PS 00000000001527b0 l 0e SECT 03 0000 [.const] __ZL33gPatchInfoCode_si_GenZRangeTex_PS 0000000000152850 l 0e SECT 03 0000 [.const] __ZL30gShaderCode_si_GenZRangeMip_PS 00000000001528f0 l 0e SECT 03 0000 [.const] __ZL31gShRegisters_si_GenZRangeMip_PS 0000000000152900 l 0e SECT 03 0000 [.const] __ZL36gContextRegisters_si_GenZRangeMip_PS 0000000000152940 l 0e SECT 03 0000 [.const] __ZL36gUserElementTable_si_GenZRangeMip_PS 0000000000152990 l 0e SECT 03 0000 [.const] __ZL31gInSemantics_si_GenZRangeMip_PS 00000000001529a4 l 0e SECT 03 0000 [.const] __ZL35gPatchInfoOffset_si_GenZRangeMip_PS 00000000001529b0 l 0e SECT 03 0000 [.const] __ZL33gPatchInfoCode_si_GenZRangeMip_PS 0000000000152a50 l 0e SECT 03 0000 [.const] __ZL33gShaderCode_si_GenZRangeMipOdd_PS 0000000000152c50 l 0e SECT 03 0000 [.const] __ZL34gShRegisters_si_GenZRangeMipOdd_PS 0000000000152c60 l 0e SECT 03 0000 [.const] __ZL39gContextRegisters_si_GenZRangeMipOdd_PS 0000000000152ca0 l 0e SECT 03 0000 [.const] __ZL39gUserElementTable_si_GenZRangeMipOdd_PS 0000000000152cd0 l 0e SECT 03 0000 [.const] __ZL34gInSemantics_si_GenZRangeMipOdd_PS 0000000000152ce4 l 0e SECT 03 0000 [.const] __ZL38gPatchInfoOffset_si_GenZRangeMipOdd_PS 0000000000152cf0 l 0e SECT 03 0000 [.const] __ZL36gPatchInfoCode_si_GenZRangeMipOdd_PS 0000000000152d90 l 0e SECT 03 0000 [.const] __ZL27gShaderCode_si_Composite_PS 0000000000153490 l 0e SECT 03 0000 [.const] __ZL28gShRegisters_si_Composite_PS 00000000001534a0 l 0e SECT 03 0000 [.const] __ZL33gContextRegisters_si_Composite_PS 00000000001534e0 l 0e SECT 03 0000 [.const] __ZL33gUserElementTable_si_Composite_PS 0000000000153530 l 0e SECT 03 0000 [.const] __ZL28gInSemantics_si_Composite_PS 0000000000153558 l 0e SECT 03 0000 [.const] __ZL32gPatchInfoOffset_si_Composite_PS 0000000000153560 l 0e SECT 03 0000 [.const] __ZL30gPatchInfoCode_si_Composite_PS 0000000000153600 l 0e SECT 03 0000 [.const] __ZL29gShaderCode_si_BufferClear_CS 0000000000153630 l 0e SECT 03 0000 [.const] __ZL30gShRegisters_si_BufferClear_CS 0000000000153658 l 0e SECT 03 0000 [.const] __ZL35gContextRegisters_si_BufferClear_CS 0000000000153660 l 0e SECT 03 0000 [.const] __ZL35gUserElementTable_si_BufferClear_CS 0000000000153690 l 0e SECT 03 0000 [.const] __ZL28gShaderCode_si_BufferCopy_CS 00000000001536b0 l 0e SECT 03 0000 [.const] __ZL29gShRegisters_si_BufferCopy_CS 00000000001536d8 l 0e SECT 03 0000 [.const] __ZL34gContextRegisters_si_BufferCopy_CS 00000000001536e0 l 0e SECT 03 0000 [.const] __ZL34gUserElementTable_si_BufferCopy_CS 0000000000153710 l 0e SECT 03 0000 [.const] __ZL30gShaderCode_si_SurfaceClear_CS 0000000000153770 l 0e SECT 03 0000 [.const] __ZL31gShRegisters_si_SurfaceClear_CS 0000000000153798 l 0e SECT 03 0000 [.const] __ZL36gContextRegisters_si_SurfaceClear_CS 00000000001537a0 l 0e SECT 03 0000 [.const] __ZL36gUserElementTable_si_SurfaceClear_CS 00000000001537d0 l 0e SECT 03 0000 [.const] __ZL31gShaderCode_si_LinGenDstCopy_CS 0000000000153850 l 0e SECT 03 0000 [.const] __ZL32gShRegisters_si_LinGenDstCopy_CS 0000000000153878 l 0e SECT 03 0000 [.const] __ZL37gContextRegisters_si_LinGenDstCopy_CS 0000000000153880 l 0e SECT 03 0000 [.const] __ZL37gUserElementTable_si_LinGenDstCopy_CS 00000000001538d0 l 0e SECT 03 0000 [.const] __ZL31gShaderCode_si_LinGenSrcCopy_CS 0000000000153940 l 0e SECT 03 0000 [.const] __ZL32gShRegisters_si_LinGenSrcCopy_CS 0000000000153968 l 0e SECT 03 0000 [.const] __ZL37gContextRegisters_si_LinGenSrcCopy_CS 0000000000153970 l 0e SECT 03 0000 [.const] __ZL37gUserElementTable_si_LinGenSrcCopy_CS 00000000001539c0 l 0e SECT 03 0000 [.const] __ZL34gShaderCode_si_LinGenSrcDstCopy_CS 0000000000153a40 l 0e SECT 03 0000 [.const] __ZL35gShRegisters_si_LinGenSrcDstCopy_CS 0000000000153a68 l 0e SECT 03 0000 [.const] __ZL40gContextRegisters_si_LinGenSrcDstCopy_CS 0000000000153a70 l 0e SECT 03 0000 [.const] __ZL40gUserElementTable_si_LinGenSrcDstCopy_CS 0000000000153ac0 l 0e SECT 03 0000 [.const] __ZL27gShaderCode_si_HtileCopy_CS 0000000000153af0 l 0e SECT 03 0000 [.const] __ZL28gShRegisters_si_HtileCopy_CS 0000000000153b18 l 0e SECT 03 0000 [.const] __ZL33gContextRegisters_si_HtileCopy_CS 0000000000153b20 l 0e SECT 03 0000 [.const] __ZL33gUserElementTable_si_HtileCopy_CS 0000000000153b50 l 0e SECT 03 0000 [.const] __ZL38gShaderCode_si_MsaaFMaskExpand2Samp_CS 0000000000153bf0 l 0e SECT 03 0000 [.const] __ZL39gShRegisters_si_MsaaFMaskExpand2Samp_CS 0000000000153c18 l 0e SECT 03 0000 [.const] __ZL44gContextRegisters_si_MsaaFMaskExpand2Samp_CS 0000000000153c20 l 0e SECT 03 0000 [.const] __ZL44gUserElementTable_si_MsaaFMaskExpand2Samp_CS 0000000000153c40 l 0e SECT 03 0000 [.const] __ZL38gShaderCode_si_MsaaFMaskExpand4Samp_CS 0000000000153d50 l 0e SECT 03 0000 [.const] __ZL39gShRegisters_si_MsaaFMaskExpand4Samp_CS 0000000000153d78 l 0e SECT 03 0000 [.const] __ZL44gContextRegisters_si_MsaaFMaskExpand4Samp_CS 0000000000153d80 l 0e SECT 03 0000 [.const] __ZL44gUserElementTable_si_MsaaFMaskExpand4Samp_CS 0000000000153da0 l 0e SECT 03 0000 [.const] __ZL38gShaderCode_si_MsaaFMaskExpand8Samp_CS 0000000000153f70 l 0e SECT 03 0000 [.const] __ZL39gShRegisters_si_MsaaFMaskExpand8Samp_CS 0000000000153f98 l 0e SECT 03 0000 [.const] __ZL44gContextRegisters_si_MsaaFMaskExpand8Samp_CS 0000000000153fa0 l 0e SECT 03 0000 [.const] __ZL44gUserElementTable_si_MsaaFMaskExpand8Samp_CS 0000000000153fc0 l 0e SECT 03 0000 [.const] __ZL32gShaderCode_si_FastDepthClear_CS 0000000000154020 l 0e SECT 03 0000 [.const] __ZL33gShRegisters_si_FastDepthClear_CS 0000000000154048 l 0e SECT 03 0000 [.const] __ZL38gContextRegisters_si_FastDepthClear_CS 0000000000154050 l 0e SECT 03 0000 [.const] __ZL38gUserElementTable_si_FastDepthClear_CS 0000000000154080 l 0e SECT 03 0000 [.const] __ZL35gShaderCode_si_FastDepthExpClear_CS 0000000000154110 l 0e SECT 03 0000 [.const] __ZL36gShRegisters_si_FastDepthExpClear_CS 0000000000154138 l 0e SECT 03 0000 [.const] __ZL41gContextRegisters_si_FastDepthExpClear_CS 0000000000154140 l 0e SECT 03 0000 [.const] __ZL41gUserElementTable_si_FastDepthExpClear_CS 0000000000154170 l 0e SECT 03 0000 [.const] __ZL37gShaderCode_si_LinGenDstRepackCopy_CS 0000000000154250 l 0e SECT 03 0000 [.const] __ZL38gShRegisters_si_LinGenDstRepackCopy_CS 0000000000154278 l 0e SECT 03 0000 [.const] __ZL43gContextRegisters_si_LinGenDstRepackCopy_CS 0000000000154280 l 0e SECT 03 0000 [.const] __ZL43gUserElementTable_si_LinGenDstRepackCopy_CS 00000000001542d0 l 0e SECT 03 0000 [.const] __ZL31gShaderCode_si_VolumeTexCopy_CS 0000000000154360 l 0e SECT 03 0000 [.const] __ZL32gShRegisters_si_VolumeTexCopy_CS 0000000000154388 l 0e SECT 03 0000 [.const] __ZL37gContextRegisters_si_VolumeTexCopy_CS 0000000000154390 l 0e SECT 03 0000 [.const] __ZL37gUserElementTable_si_VolumeTexCopy_CS 00000000001543e0 l 0e SECT 03 0000 [.const] __ZL29gShaderCode_si_GenerateHiS_PS 0000000000154480 l 0e SECT 03 0000 [.const] __ZL30gShRegisters_si_GenerateHiS_PS 0000000000154490 l 0e SECT 03 0000 [.const] __ZL35gContextRegisters_si_GenerateHiS_PS 00000000001544d0 l 0e SECT 03 0000 [.const] __ZL35gUserElementTable_si_GenerateHiS_PS 0000000000154520 l 0e SECT 03 0000 [.const] __ZL30gInSemantics_si_GenerateHiS_PS 0000000000154534 l 0e SECT 03 0000 [.const] __ZL34gPatchInfoOffset_si_GenerateHiS_PS 0000000000154540 l 0e SECT 03 0000 [.const] __ZL32gPatchInfoCode_si_GenerateHiS_PS 00000000001545e0 l 0e SECT 03 0000 [.const] __ZL27gShaderCode_si_AdvAARes1_PS 0000000000154640 l 0e SECT 03 0000 [.const] __ZL28gShRegisters_si_AdvAARes1_PS 0000000000154650 l 0e SECT 03 0000 [.const] __ZL33gContextRegisters_si_AdvAARes1_PS 0000000000154690 l 0e SECT 03 0000 [.const] __ZL33gUserElementTable_si_AdvAARes1_PS 00000000001546c0 l 0e SECT 03 0000 [.const] __ZL28gInSemantics_si_AdvAARes1_PS 00000000001546d4 l 0e SECT 03 0000 [.const] __ZL32gPatchInfoOffset_si_AdvAARes1_PS 00000000001546e0 l 0e SECT 03 0000 [.const] __ZL30gPatchInfoCode_si_AdvAARes1_PS 0000000000154820 l 0e SECT 03 0000 [.const] __ZL36gShaderCode_si_AdvAAEdgeMask4Samp_PS 0000000000154a00 l 0e SECT 03 0000 [.const] __ZL37gShRegisters_si_AdvAAEdgeMask4Samp_PS 0000000000154a10 l 0e SECT 03 0000 [.const] __ZL42gContextRegisters_si_AdvAAEdgeMask4Samp_PS 0000000000154a50 l 0e SECT 03 0000 [.const] __ZL42gUserElementTable_si_AdvAAEdgeMask4Samp_PS 0000000000154a80 l 0e SECT 03 0000 [.const] __ZL37gInSemantics_si_AdvAAEdgeMask4Samp_PS 0000000000154a94 l 0e SECT 03 0000 [.const] __ZL41gPatchInfoOffset_si_AdvAAEdgeMask4Samp_PS 0000000000154aa0 l 0e SECT 03 0000 [.const] __ZL39gPatchInfoCode_si_AdvAAEdgeMask4Samp_PS 0000000000154c80 l 0e SECT 03 0000 [.const] __ZL36gShaderCode_si_AdvAAEdgeMask8Samp_PS 0000000000154fa0 l 0e SECT 03 0000 [.const] __ZL37gShRegisters_si_AdvAAEdgeMask8Samp_PS 0000000000154fb0 l 0e SECT 03 0000 [.const] __ZL42gContextRegisters_si_AdvAAEdgeMask8Samp_PS 0000000000154ff0 l 0e SECT 03 0000 [.const] __ZL42gUserElementTable_si_AdvAAEdgeMask8Samp_PS 0000000000155020 l 0e SECT 03 0000 [.const] __ZL37gInSemantics_si_AdvAAEdgeMask8Samp_PS 0000000000155034 l 0e SECT 03 0000 [.const] __ZL41gPatchInfoOffset_si_AdvAAEdgeMask8Samp_PS 0000000000155040 l 0e SECT 03 0000 [.const] __ZL39gPatchInfoCode_si_AdvAAEdgeMask8Samp_PS 0000000000155220 l 0e SECT 03 0000 [.const] __ZL37gShaderCode_si_AdvAAFilterMaskFast_PS 0000000000155460 l 0e SECT 03 0000 [.const] __ZL38gShRegisters_si_AdvAAFilterMaskFast_PS 0000000000155470 l 0e SECT 03 0000 [.const] __ZL43gContextRegisters_si_AdvAAFilterMaskFast_PS 00000000001554b0 l 0e SECT 03 0000 [.const] __ZL43gUserElementTable_si_AdvAAFilterMaskFast_PS 00000000001554d0 l 0e SECT 03 0000 [.const] __ZL38gInSemantics_si_AdvAAFilterMaskFast_PS 00000000001554e4 l 0e SECT 03 0000 [.const] __ZL42gPatchInfoOffset_si_AdvAAFilterMaskFast_PS 00000000001554f0 l 0e SECT 03 0000 [.const] __ZL40gPatchInfoCode_si_AdvAAFilterMaskFast_PS 0000000000155590 l 0e SECT 03 0000 [.const] __ZL37gShaderCode_si_AdvAAGrad4SampNoReZ_PS 0000000000156e90 l 0e SECT 03 0000 [.const] __ZL38gShRegisters_si_AdvAAGrad4SampNoReZ_PS 0000000000156ea0 l 0e SECT 03 0000 [.const] __ZL43gContextRegisters_si_AdvAAGrad4SampNoReZ_PS 0000000000156ee0 l 0e SECT 03 0000 [.const] __ZL43gUserElementTable_si_AdvAAGrad4SampNoReZ_PS 0000000000156f10 l 0e SECT 03 0000 [.const] __ZL38gInSemantics_si_AdvAAGrad4SampNoReZ_PS 0000000000156f24 l 0e SECT 03 0000 [.const] __ZL42gPatchInfoOffset_si_AdvAAGrad4SampNoReZ_PS 0000000000156f30 l 0e SECT 03 0000 [.const] __ZL40gPatchInfoCode_si_AdvAAGrad4SampNoReZ_PS 0000000000156fd0 l 0e SECT 03 0000 [.const] __ZL37gShaderCode_si_AdvAAGrad8SampNoReZ_PS 0000000000159c30 l 0e SECT 03 0000 [.const] __ZL38gShRegisters_si_AdvAAGrad8SampNoReZ_PS 0000000000159c40 l 0e SECT 03 0000 [.const] __ZL43gContextRegisters_si_AdvAAGrad8SampNoReZ_PS 0000000000159c80 l 0e SECT 03 0000 [.const] __ZL43gUserElementTable_si_AdvAAGrad8SampNoReZ_PS 0000000000159cb0 l 0e SECT 03 0000 [.const] __ZL38gInSemantics_si_AdvAAGrad8SampNoReZ_PS 0000000000159cc4 l 0e SECT 03 0000 [.const] __ZL42gPatchInfoOffset_si_AdvAAGrad8SampNoReZ_PS 0000000000159cd0 l 0e SECT 03 0000 [.const] __ZL40gPatchInfoCode_si_AdvAAGrad8SampNoReZ_PS 0000000000159d70 l 0e SECT 03 0000 [.const] __ZL36gShaderCode_si_AdvAAEdG4SampNoReZ_PS 000000000015bf60 l 0e SECT 03 0000 [.const] __ZL37gShRegisters_si_AdvAAEdG4SampNoReZ_PS 000000000015bf70 l 0e SECT 03 0000 [.const] __ZL42gContextRegisters_si_AdvAAEdG4SampNoReZ_PS 000000000015bfb0 l 0e SECT 03 0000 [.const] __ZL42gUserElementTable_si_AdvAAEdG4SampNoReZ_PS 000000000015bfe0 l 0e SECT 03 0000 [.const] __ZL37gInSemantics_si_AdvAAEdG4SampNoReZ_PS 000000000015bff4 l 0e SECT 03 0000 [.const] __ZL41gPatchInfoOffset_si_AdvAAEdG4SampNoReZ_PS 000000000015c000 l 0e SECT 03 0000 [.const] __ZL39gPatchInfoCode_si_AdvAAEdG4SampNoReZ_PS 000000000015c0a0 l 0e SECT 03 0000 [.const] __ZL36gShaderCode_si_AdvAAEdG8SampNoReZ_PS 0000000000160310 l 0e SECT 03 0000 [.const] __ZL37gShRegisters_si_AdvAAEdG8SampNoReZ_PS 0000000000160320 l 0e SECT 03 0000 [.const] __ZL42gContextRegisters_si_AdvAAEdG8SampNoReZ_PS 0000000000160360 l 0e SECT 03 0000 [.const] __ZL42gUserElementTable_si_AdvAAEdG8SampNoReZ_PS 0000000000160390 l 0e SECT 03 0000 [.const] __ZL37gInSemantics_si_AdvAAEdG8SampNoReZ_PS 00000000001603a4 l 0e SECT 03 0000 [.const] __ZL41gPatchInfoOffset_si_AdvAAEdG8SampNoReZ_PS 00000000001603b0 l 0e SECT 03 0000 [.const] __ZL39gPatchInfoCode_si_AdvAAEdG8SampNoReZ_PS 0000000000160450 l 0e SECT 03 0000 [.const] __ZL41gShaderCode_si_AdvAAFMaskEdgeMask4Samp_PS 00000000001606c0 l 0e SECT 03 0000 [.const] __ZL42gShRegisters_si_AdvAAFMaskEdgeMask4Samp_PS 00000000001606d0 l 0e SECT 03 0000 [.const] __ZL47gContextRegisters_si_AdvAAFMaskEdgeMask4Samp_PS 0000000000160710 l 0e SECT 03 0000 [.const] __ZL47gUserElementTable_si_AdvAAFMaskEdgeMask4Samp_PS 0000000000160740 l 0e SECT 03 0000 [.const] __ZL42gInSemantics_si_AdvAAFMaskEdgeMask4Samp_PS 0000000000160754 l 0e SECT 03 0000 [.const] __ZL46gPatchInfoOffset_si_AdvAAFMaskEdgeMask4Samp_PS 0000000000160760 l 0e SECT 03 0000 [.const] __ZL44gPatchInfoCode_si_AdvAAFMaskEdgeMask4Samp_PS 0000000000160940 l 0e SECT 03 0000 [.const] __ZL41gShaderCode_si_AdvAAFMaskEdgeMask8Samp_PS 0000000000160dc0 l 0e SECT 03 0000 [.const] __ZL42gShRegisters_si_AdvAAFMaskEdgeMask8Samp_PS 0000000000160dd0 l 0e SECT 03 0000 [.const] __ZL47gContextRegisters_si_AdvAAFMaskEdgeMask8Samp_PS 0000000000160e10 l 0e SECT 03 0000 [.const] __ZL47gUserElementTable_si_AdvAAFMaskEdgeMask8Samp_PS 0000000000160e40 l 0e SECT 03 0000 [.const] __ZL42gInSemantics_si_AdvAAFMaskEdgeMask8Samp_PS 0000000000160e54 l 0e SECT 03 0000 [.const] __ZL46gPatchInfoOffset_si_AdvAAFMaskEdgeMask8Samp_PS 0000000000160e60 l 0e SECT 03 0000 [.const] __ZL44gPatchInfoCode_si_AdvAAFMaskEdgeMask8Samp_PS 0000000000161040 l 0e SECT 03 0000 [.const] __ZL41gShaderCode_si_AdvAAFMaskEdG4SampNoReZ_PS 00000000001633e0 l 0e SECT 03 0000 [.const] __ZL42gShRegisters_si_AdvAAFMaskEdG4SampNoReZ_PS 00000000001633f0 l 0e SECT 03 0000 [.const] __ZL47gContextRegisters_si_AdvAAFMaskEdG4SampNoReZ_PS 0000000000163430 l 0e SECT 03 0000 [.const] __ZL47gUserElementTable_si_AdvAAFMaskEdG4SampNoReZ_PS 0000000000163460 l 0e SECT 03 0000 [.const] __ZL42gInSemantics_si_AdvAAFMaskEdG4SampNoReZ_PS 0000000000163474 l 0e SECT 03 0000 [.const] __ZL46gPatchInfoOffset_si_AdvAAFMaskEdG4SampNoReZ_PS 0000000000163480 l 0e SECT 03 0000 [.const] __ZL44gPatchInfoCode_si_AdvAAFMaskEdG4SampNoReZ_PS 0000000000163520 l 0e SECT 03 0000 [.const] __ZL41gShaderCode_si_AdvAAFMaskEdG8SampNoReZ_PS 0000000000167ab0 l 0e SECT 03 0000 [.const] __ZL42gShRegisters_si_AdvAAFMaskEdG8SampNoReZ_PS 0000000000167ac0 l 0e SECT 03 0000 [.const] __ZL47gContextRegisters_si_AdvAAFMaskEdG8SampNoReZ_PS 0000000000167b00 l 0e SECT 03 0000 [.const] __ZL47gUserElementTable_si_AdvAAFMaskEdG8SampNoReZ_PS 0000000000167b30 l 0e SECT 03 0000 [.const] __ZL42gInSemantics_si_AdvAAFMaskEdG8SampNoReZ_PS 0000000000167b44 l 0e SECT 03 0000 [.const] __ZL46gPatchInfoOffset_si_AdvAAFMaskEdG8SampNoReZ_PS 0000000000167b50 l 0e SECT 03 0000 [.const] __ZL44gPatchInfoCode_si_AdvAAFMaskEdG8SampNoReZ_PS 0000000000167bf0 l 0e SECT 03 0000 [.const] __ZL25gShaderCode_ci_RectPos_VS 0000000000167ce0 l 0e SECT 03 0000 [.const] __ZL26gShRegisters_ci_RectPos_VS 0000000000167cf0 l 0e SECT 03 0000 [.const] __ZL31gContextRegisters_ci_RectPos_VS 0000000000167d00 l 0e SECT 03 0000 [.const] __ZL31gUserElementTable_ci_RectPos_VS 0000000000167d30 l 0e SECT 03 0000 [.const] __ZL27gOutSemantics_ci_RectPos_VS 0000000000167d40 l 0e SECT 03 0000 [.const] __ZL31gShaderCode_ci_RectPosTexTex_VS 00000000001680c0 l 0e SECT 03 0000 [.const] __ZL32gShRegisters_ci_RectPosTexTex_VS 00000000001680d0 l 0e SECT 03 0000 [.const] __ZL37gContextRegisters_ci_RectPosTexTex_VS 00000000001680e0 l 0e SECT 03 0000 [.const] __ZL37gUserElementTable_ci_RectPosTexTex_VS 0000000000168110 l 0e SECT 03 0000 [.const] __ZL33gOutSemantics_ci_RectPosTexTex_VS 0000000000168130 l 0e SECT 03 0000 [.const] __ZL32gShaderCode_ci_RectPosTexFast_VS 00000000001681c0 l 0e SECT 03 0000 [.const] __ZL33gShRegisters_ci_RectPosTexFast_VS 00000000001681d0 l 0e SECT 03 0000 [.const] __ZL38gContextRegisters_ci_RectPosTexFast_VS 00000000001681e0 l 0e SECT 03 0000 [.const] __ZL38gUserElementTable_ci_RectPosTexFast_VS 0000000000168240 l 0e SECT 03 0000 [.const] __ZL34gOutSemantics_ci_RectPosTexFast_VS 0000000000168250 l 0e SECT 03 0000 [.const] __ZL30gShaderCode_ci_VertPosColor_VS 00000000001682a0 l 0e SECT 03 0000 [.const] __ZL31gShRegisters_ci_VertPosColor_VS 00000000001682b0 l 0e SECT 03 0000 [.const] __ZL36gContextRegisters_ci_VertPosColor_VS 00000000001682c0 l 0e SECT 03 0000 [.const] __ZL36gUserElementTable_ci_VertPosColor_VS 00000000001682f0 l 0e SECT 03 0000 [.const] __ZL32gOutSemantics_ci_VertPosColor_VS 0000000000168300 l 0e SECT 03 0000 [.const] __ZL40gShaderCode_ci_RectPosTexTexComposite_VS 00000000001684a0 l 0e SECT 03 0000 [.const] __ZL41gShRegisters_ci_RectPosTexTexComposite_VS 00000000001684b0 l 0e SECT 03 0000 [.const] __ZL46gContextRegisters_ci_RectPosTexTexComposite_VS 00000000001684c0 l 0e SECT 03 0000 [.const] __ZL46gUserElementTable_ci_RectPosTexTexComposite_VS 00000000001684f0 l 0e SECT 03 0000 [.const] __ZL42gOutSemantics_ci_RectPosTexTexComposite_VS 0000000000168510 l 0e SECT 03 0000 [.const] __ZL22gShaderCode_ci_Zero_PS 0000000000168530 l 0e SECT 03 0000 [.const] __ZL23gShRegisters_ci_Zero_PS 0000000000168540 l 0e SECT 03 0000 [.const] __ZL28gContextRegisters_ci_Zero_PS 0000000000168580 l 0e SECT 03 0000 [.const] __ZL28gUserElementTable_ci_Zero_PS 00000000001685a0 l 0e SECT 03 0000 [.const] __ZL23gInSemantics_ci_Zero_PS 00000000001685b4 l 0e SECT 03 0000 [.const] __ZL27gPatchInfoOffset_ci_Zero_PS 00000000001685c0 l 0e SECT 03 0000 [.const] __ZL25gPatchInfoCode_ci_Zero_PS 0000000000168660 l 0e SECT 03 0000 [.const] __ZL23gShaderCode_ci_Const_PS 0000000000168690 l 0e SECT 03 0000 [.const] __ZL24gShRegisters_ci_Const_PS 00000000001686a0 l 0e SECT 03 0000 [.const] __ZL29gContextRegisters_ci_Const_PS 00000000001686e0 l 0e SECT 03 0000 [.const] __ZL29gUserElementTable_ci_Const_PS 0000000000168700 l 0e SECT 03 0000 [.const] __ZL24gInSemantics_ci_Const_PS 0000000000168714 l 0e SECT 03 0000 [.const] __ZL28gPatchInfoOffset_ci_Const_PS 0000000000168720 l 0e SECT 03 0000 [.const] __ZL26gPatchInfoCode_ci_Const_PS 00000000001687c0 l 0e SECT 03 0000 [.const] __ZL21gShaderCode_ci_Tex_PS 0000000000168800 l 0e SECT 03 0000 [.const] __ZL22gShRegisters_ci_Tex_PS 0000000000168810 l 0e SECT 03 0000 [.const] __ZL27gContextRegisters_ci_Tex_PS 0000000000168850 l 0e SECT 03 0000 [.const] __ZL27gUserElementTable_ci_Tex_PS 0000000000168880 l 0e SECT 03 0000 [.const] __ZL22gInSemantics_ci_Tex_PS 0000000000168894 l 0e SECT 03 0000 [.const] __ZL26gPatchInfoOffset_ci_Tex_PS 00000000001688a0 l 0e SECT 03 0000 [.const] __ZL24gPatchInfoCode_ci_Tex_PS 0000000000168940 l 0e SECT 03 0000 [.const] __ZL26gShaderCode_ci_TexCoord_PS 0000000000168980 l 0e SECT 03 0000 [.const] __ZL27gShRegisters_ci_TexCoord_PS 0000000000168990 l 0e SECT 03 0000 [.const] __ZL32gContextRegisters_ci_TexCoord_PS 00000000001689d0 l 0e SECT 03 0000 [.const] __ZL32gUserElementTable_ci_TexCoord_PS 00000000001689f0 l 0e SECT 03 0000 [.const] __ZL27gInSemantics_ci_TexCoord_PS 0000000000168a04 l 0e SECT 03 0000 [.const] __ZL31gPatchInfoOffset_ci_TexCoord_PS 0000000000168a10 l 0e SECT 03 0000 [.const] __ZL29gPatchInfoCode_ci_TexCoord_PS 0000000000168ab0 l 0e SECT 03 0000 [.const] __ZL29gShaderCode_ci_TexGammaDst_PS 0000000000168ba0 l 0e SECT 03 0000 [.const] __ZL30gShRegisters_ci_TexGammaDst_PS 0000000000168bb0 l 0e SECT 03 0000 [.const] __ZL35gContextRegisters_ci_TexGammaDst_PS 0000000000168bf0 l 0e SECT 03 0000 [.const] __ZL35gUserElementTable_ci_TexGammaDst_PS 0000000000168c20 l 0e SECT 03 0000 [.const] __ZL30gInSemantics_ci_TexGammaDst_PS 0000000000168c34 l 0e SECT 03 0000 [.const] __ZL34gPatchInfoOffset_ci_TexGammaDst_PS 0000000000168c40 l 0e SECT 03 0000 [.const] __ZL32gPatchInfoCode_ci_TexGammaDst_PS 0000000000168ce0 l 0e SECT 03 0000 [.const] __ZL30gShaderCode_ci_MsaaResolve1_PS 0000000000168d20 l 0e SECT 03 0000 [.const] __ZL31gShRegisters_ci_MsaaResolve1_PS 0000000000168d30 l 0e SECT 03 0000 [.const] __ZL36gContextRegisters_ci_MsaaResolve1_PS 0000000000168d70 l 0e SECT 03 0000 [.const] __ZL36gUserElementTable_ci_MsaaResolve1_PS 0000000000168da0 l 0e SECT 03 0000 [.const] __ZL31gInSemantics_ci_MsaaResolve1_PS 0000000000168db4 l 0e SECT 03 0000 [.const] __ZL35gPatchInfoOffset_ci_MsaaResolve1_PS 0000000000168dc0 l 0e SECT 03 0000 [.const] __ZL33gPatchInfoCode_ci_MsaaResolve1_PS 0000000000168e60 l 0e SECT 03 0000 [.const] __ZL30gShaderCode_ci_MsaaResolve2_PS 0000000000168ed0 l 0e SECT 03 0000 [.const] __ZL31gShRegisters_ci_MsaaResolve2_PS 0000000000168ee0 l 0e SECT 03 0000 [.const] __ZL36gContextRegisters_ci_MsaaResolve2_PS 0000000000168f20 l 0e SECT 03 0000 [.const] __ZL36gUserElementTable_ci_MsaaResolve2_PS 0000000000168f50 l 0e SECT 03 0000 [.const] __ZL31gInSemantics_ci_MsaaResolve2_PS 0000000000168f64 l 0e SECT 03 0000 [.const] __ZL35gPatchInfoOffset_ci_MsaaResolve2_PS 0000000000168f70 l 0e SECT 03 0000 [.const] __ZL33gPatchInfoCode_ci_MsaaResolve2_PS 0000000000169010 l 0e SECT 03 0000 [.const] __ZL30gShaderCode_ci_MsaaResolve4_PS 00000000001690c0 l 0e SECT 03 0000 [.const] __ZL31gShRegisters_ci_MsaaResolve4_PS 00000000001690d0 l 0e SECT 03 0000 [.const] __ZL36gContextRegisters_ci_MsaaResolve4_PS 0000000000169110 l 0e SECT 03 0000 [.const] __ZL36gUserElementTable_ci_MsaaResolve4_PS 0000000000169140 l 0e SECT 03 0000 [.const] __ZL31gInSemantics_ci_MsaaResolve4_PS 0000000000169154 l 0e SECT 03 0000 [.const] __ZL35gPatchInfoOffset_ci_MsaaResolve4_PS 0000000000169160 l 0e SECT 03 0000 [.const] __ZL33gPatchInfoCode_ci_MsaaResolve4_PS 0000000000169200 l 0e SECT 03 0000 [.const] __ZL30gShaderCode_ci_MsaaResolve8_PS 0000000000169330 l 0e SECT 03 0000 [.const] __ZL31gShRegisters_ci_MsaaResolve8_PS 0000000000169340 l 0e SECT 03 0000 [.const] __ZL36gContextRegisters_ci_MsaaResolve8_PS 0000000000169380 l 0e SECT 03 0000 [.const] __ZL36gUserElementTable_ci_MsaaResolve8_PS 00000000001693b0 l 0e SECT 03 0000 [.const] __ZL31gInSemantics_ci_MsaaResolve8_PS 00000000001693c4 l 0e SECT 03 0000 [.const] __ZL35gPatchInfoOffset_ci_MsaaResolve8_PS 00000000001693d0 l 0e SECT 03 0000 [.const] __ZL33gPatchInfoCode_ci_MsaaResolve8_PS 0000000000169470 l 0e SECT 03 0000 [.const] __ZL33gShaderCode_ci_MsaaFMaskExpand_PS 0000000000169510 l 0e SECT 03 0000 [.const] __ZL34gShRegisters_ci_MsaaFMaskExpand_PS 0000000000169520 l 0e SECT 03 0000 [.const] __ZL39gContextRegisters_ci_MsaaFMaskExpand_PS 0000000000169560 l 0e SECT 03 0000 [.const] __ZL39gUserElementTable_ci_MsaaFMaskExpand_PS 0000000000169590 l 0e SECT 03 0000 [.const] __ZL34gInSemantics_ci_MsaaFMaskExpand_PS 00000000001695a4 l 0e SECT 03 0000 [.const] __ZL38gPatchInfoOffset_ci_MsaaFMaskExpand_PS 00000000001695b0 l 0e SECT 03 0000 [.const] __ZL36gPatchInfoCode_ci_MsaaFMaskExpand_PS 0000000000169650 l 0e SECT 03 0000 [.const] __ZL34gShaderCode_ci_MsaaDepthResolve_PS 0000000000169690 l 0e SECT 03 0000 [.const] __ZL35gShRegisters_ci_MsaaDepthResolve_PS 00000000001696a0 l 0e SECT 03 0000 [.const] __ZL40gContextRegisters_ci_MsaaDepthResolve_PS 00000000001696e0 l 0e SECT 03 0000 [.const] __ZL40gUserElementTable_ci_MsaaDepthResolve_PS 0000000000169710 l 0e SECT 03 0000 [.const] __ZL35gInSemantics_ci_MsaaDepthResolve_PS 0000000000169724 l 0e SECT 03 0000 [.const] __ZL39gPatchInfoOffset_ci_MsaaDepthResolve_PS 0000000000169730 l 0e SECT 03 0000 [.const] __ZL37gPatchInfoCode_ci_MsaaDepthResolve_PS 00000000001697d0 l 0e SECT 03 0000 [.const] __ZL41gShaderCode_ci_MsaaDepthStencilResolve_PS 0000000000169830 l 0e SECT 03 0000 [.const] __ZL42gShRegisters_ci_MsaaDepthStencilResolve_PS 0000000000169840 l 0e SECT 03 0000 [.const] __ZL47gContextRegisters_ci_MsaaDepthStencilResolve_PS 0000000000169880 l 0e SECT 03 0000 [.const] __ZL47gUserElementTable_ci_MsaaDepthStencilResolve_PS 00000000001698d0 l 0e SECT 03 0000 [.const] __ZL42gInSemantics_ci_MsaaDepthStencilResolve_PS 00000000001698e4 l 0e SECT 03 0000 [.const] __ZL46gPatchInfoOffset_ci_MsaaDepthStencilResolve_PS 00000000001698f0 l 0e SECT 03 0000 [.const] __ZL44gPatchInfoCode_ci_MsaaDepthStencilResolve_PS 0000000000169990 l 0e SECT 03 0000 [.const] __ZL36gShaderCode_ci_TexZStencilAsColor_PS 00000000001699f0 l 0e SECT 03 0000 [.const] __ZL37gShRegisters_ci_TexZStencilAsColor_PS 0000000000169a00 l 0e SECT 03 0000 [.const] __ZL42gContextRegisters_ci_TexZStencilAsColor_PS 0000000000169a40 l 0e SECT 03 0000 [.const] __ZL42gUserElementTable_ci_TexZStencilAsColor_PS 0000000000169a90 l 0e SECT 03 0000 [.const] __ZL37gInSemantics_ci_TexZStencilAsColor_PS 0000000000169aa4 l 0e SECT 03 0000 [.const] __ZL41gPatchInfoOffset_ci_TexZStencilAsColor_PS 0000000000169ab0 l 0e SECT 03 0000 [.const] __ZL39gPatchInfoCode_ci_TexZStencilAsColor_PS 0000000000169b50 l 0e SECT 03 0000 [.const] __ZL29gShaderCode_ci_TexAlphaOne_PS 0000000000169ba0 l 0e SECT 03 0000 [.const] __ZL30gShRegisters_ci_TexAlphaOne_PS 0000000000169bb0 l 0e SECT 03 0000 [.const] __ZL35gContextRegisters_ci_TexAlphaOne_PS 0000000000169bf0 l 0e SECT 03 0000 [.const] __ZL35gUserElementTable_ci_TexAlphaOne_PS 0000000000169c20 l 0e SECT 03 0000 [.const] __ZL30gInSemantics_ci_TexAlphaOne_PS 0000000000169c34 l 0e SECT 03 0000 [.const] __ZL34gPatchInfoOffset_ci_TexAlphaOne_PS 0000000000169c40 l 0e SECT 03 0000 [.const] __ZL32gPatchInfoCode_ci_TexAlphaOne_PS 0000000000169ce0 l 0e SECT 03 0000 [.const] __ZL32gShaderCode_ci_TexAlphaOneInt_PS 0000000000169d30 l 0e SECT 03 0000 [.const] __ZL33gShRegisters_ci_TexAlphaOneInt_PS 0000000000169d40 l 0e SECT 03 0000 [.const] __ZL38gContextRegisters_ci_TexAlphaOneInt_PS 0000000000169d80 l 0e SECT 03 0000 [.const] __ZL38gUserElementTable_ci_TexAlphaOneInt_PS 0000000000169db0 l 0e SECT 03 0000 [.const] __ZL33gInSemantics_ci_TexAlphaOneInt_PS 0000000000169dc4 l 0e SECT 03 0000 [.const] __ZL37gPatchInfoOffset_ci_TexAlphaOneInt_PS 0000000000169dd0 l 0e SECT 03 0000 [.const] __ZL35gPatchInfoCode_ci_TexAlphaOneInt_PS 0000000000169e70 l 0e SECT 03 0000 [.const] __ZL40gShaderCode_ci_MsaaTexZStencilAsColor_PS 0000000000169ed0 l 0e SECT 03 0000 [.const] __ZL41gShRegisters_ci_MsaaTexZStencilAsColor_PS 0000000000169ee0 l 0e SECT 03 0000 [.const] __ZL46gContextRegisters_ci_MsaaTexZStencilAsColor_PS 0000000000169f20 l 0e SECT 03 0000 [.const] __ZL46gUserElementTable_ci_MsaaTexZStencilAsColor_PS 0000000000169f40 l 0e SECT 03 0000 [.const] __ZL41gInSemantics_ci_MsaaTexZStencilAsColor_PS 0000000000169f54 l 0e SECT 03 0000 [.const] __ZL45gPatchInfoOffset_ci_MsaaTexZStencilAsColor_PS 0000000000169f60 l 0e SECT 03 0000 [.const] __ZL43gPatchInfoCode_ci_MsaaTexZStencilAsColor_PS 000000000016a000 l 0e SECT 03 0000 [.const] __ZL24gShaderCode_ci_TexAsZ_PS 000000000016a040 l 0e SECT 03 0000 [.const] __ZL25gShRegisters_ci_TexAsZ_PS 000000000016a050 l 0e SECT 03 0000 [.const] __ZL30gContextRegisters_ci_TexAsZ_PS 000000000016a090 l 0e SECT 03 0000 [.const] __ZL30gUserElementTable_ci_TexAsZ_PS 000000000016a0c0 l 0e SECT 03 0000 [.const] __ZL25gInSemantics_ci_TexAsZ_PS 000000000016a0d4 l 0e SECT 03 0000 [.const] __ZL29gPatchInfoOffset_ci_TexAsZ_PS 000000000016a0e0 l 0e SECT 03 0000 [.const] __ZL27gPatchInfoCode_ci_TexAsZ_PS 000000000016a180 l 0e SECT 03 0000 [.const] __ZL31gShaderCode_ci_TexAsZStencil_PS 000000000016a1e0 l 0e SECT 03 0000 [.const] __ZL32gShRegisters_ci_TexAsZStencil_PS 000000000016a1f0 l 0e SECT 03 0000 [.const] __ZL37gContextRegisters_ci_TexAsZStencil_PS 000000000016a230 l 0e SECT 03 0000 [.const] __ZL37gUserElementTable_ci_TexAsZStencil_PS 000000000016a280 l 0e SECT 03 0000 [.const] __ZL32gInSemantics_ci_TexAsZStencil_PS 000000000016a294 l 0e SECT 03 0000 [.const] __ZL36gPatchInfoOffset_ci_TexAsZStencil_PS 000000000016a2a0 l 0e SECT 03 0000 [.const] __ZL34gPatchInfoCode_ci_TexAsZStencil_PS 000000000016a340 l 0e SECT 03 0000 [.const] __ZL28gShaderCode_ci_MsaaTexAsZ_PS 000000000016a390 l 0e SECT 03 0000 [.const] __ZL29gShRegisters_ci_MsaaTexAsZ_PS 000000000016a3a0 l 0e SECT 03 0000 [.const] __ZL34gContextRegisters_ci_MsaaTexAsZ_PS 000000000016a3e0 l 0e SECT 03 0000 [.const] __ZL34gUserElementTable_ci_MsaaTexAsZ_PS 000000000016a410 l 0e SECT 03 0000 [.const] __ZL29gInSemantics_ci_MsaaTexAsZ_PS 000000000016a424 l 0e SECT 03 0000 [.const] __ZL33gPatchInfoOffset_ci_MsaaTexAsZ_PS 000000000016a430 l 0e SECT 03 0000 [.const] __ZL31gPatchInfoCode_ci_MsaaTexAsZ_PS 000000000016a4d0 l 0e SECT 03 0000 [.const] __ZL35gShaderCode_ci_MsaaTexAsZStencil_PS 000000000016a530 l 0e SECT 03 0000 [.const] __ZL36gShRegisters_ci_MsaaTexAsZStencil_PS 000000000016a540 l 0e SECT 03 0000 [.const] __ZL41gContextRegisters_ci_MsaaTexAsZStencil_PS 000000000016a580 l 0e SECT 03 0000 [.const] __ZL41gUserElementTable_ci_MsaaTexAsZStencil_PS 000000000016a5d0 l 0e SECT 03 0000 [.const] __ZL36gInSemantics_ci_MsaaTexAsZStencil_PS 000000000016a5e4 l 0e SECT 03 0000 [.const] __ZL40gPatchInfoOffset_ci_MsaaTexAsZStencil_PS 000000000016a5f0 l 0e SECT 03 0000 [.const] __ZL38gPatchInfoCode_ci_MsaaTexAsZStencil_PS 000000000016a690 l 0e SECT 03 0000 [.const] __ZL24gShaderCode_ci_VolTex_PS 000000000016a6e0 l 0e SECT 03 0000 [.const] __ZL25gShRegisters_ci_VolTex_PS 000000000016a6f0 l 0e SECT 03 0000 [.const] __ZL30gContextRegisters_ci_VolTex_PS 000000000016a730 l 0e SECT 03 0000 [.const] __ZL30gUserElementTable_ci_VolTex_PS 000000000016a760 l 0e SECT 03 0000 [.const] __ZL25gInSemantics_ci_VolTex_PS 000000000016a774 l 0e SECT 03 0000 [.const] __ZL29gPatchInfoOffset_ci_VolTex_PS 000000000016a780 l 0e SECT 03 0000 [.const] __ZL27gPatchInfoCode_ci_VolTex_PS 000000000016a820 l 0e SECT 03 0000 [.const] __ZL24gShaderCode_ci_AAText_PS 000000000016a8f0 l 0e SECT 03 0000 [.const] __ZL25gShRegisters_ci_AAText_PS 000000000016a900 l 0e SECT 03 0000 [.const] __ZL30gContextRegisters_ci_AAText_PS 000000000016a940 l 0e SECT 03 0000 [.const] __ZL30gUserElementTable_ci_AAText_PS 000000000016a990 l 0e SECT 03 0000 [.const] __ZL25gInSemantics_ci_AAText_PS 000000000016a9a4 l 0e SECT 03 0000 [.const] __ZL29gPatchInfoOffset_ci_AAText_PS 000000000016a9b0 l 0e SECT 03 0000 [.const] __ZL27gPatchInfoCode_ci_AAText_PS 000000000016aa50 l 0e SECT 03 0000 [.const] __ZL28gShaderCode_ci_SlowAAText_PS 000000000016ab10 l 0e SECT 03 0000 [.const] __ZL29gShRegisters_ci_SlowAAText_PS 000000000016ab20 l 0e SECT 03 0000 [.const] __ZL34gContextRegisters_ci_SlowAAText_PS 000000000016ab60 l 0e SECT 03 0000 [.const] __ZL34gUserElementTable_ci_SlowAAText_PS 000000000016abc0 l 0e SECT 03 0000 [.const] __ZL29gInSemantics_ci_SlowAAText_PS 000000000016abe8 l 0e SECT 03 0000 [.const] __ZL33gPatchInfoOffset_ci_SlowAAText_PS 000000000016abf0 l 0e SECT 03 0000 [.const] __ZL31gPatchInfoCode_ci_SlowAAText_PS 000000000016ac90 l 0e SECT 03 0000 [.const] __ZL32gShaderCode_ci_ClearTypeGamma_PS 000000000016ae10 l 0e SECT 03 0000 [.const] __ZL33gShRegisters_ci_ClearTypeGamma_PS 000000000016ae20 l 0e SECT 03 0000 [.const] __ZL38gContextRegisters_ci_ClearTypeGamma_PS 000000000016ae60 l 0e SECT 03 0000 [.const] __ZL38gUserElementTable_ci_ClearTypeGamma_PS 000000000016aeb0 l 0e SECT 03 0000 [.const] __ZL33gInSemantics_ci_ClearTypeGamma_PS 000000000016aed8 l 0e SECT 03 0000 [.const] __ZL37gPatchInfoOffset_ci_ClearTypeGamma_PS 000000000016aee0 l 0e SECT 03 0000 [.const] __ZL35gPatchInfoCode_ci_ClearTypeGamma_PS 000000000016af80 l 0e SECT 03 0000 [.const] __ZL29gShaderCode_ci_TexColorKey_PS 000000000016b0d0 l 0e SECT 03 0000 [.const] __ZL30gShRegisters_ci_TexColorKey_PS 000000000016b0e0 l 0e SECT 03 0000 [.const] __ZL35gContextRegisters_ci_TexColorKey_PS 000000000016b120 l 0e SECT 03 0000 [.const] __ZL35gUserElementTable_ci_TexColorKey_PS 000000000016b180 l 0e SECT 03 0000 [.const] __ZL30gInSemantics_ci_TexColorKey_PS 000000000016b1a8 l 0e SECT 03 0000 [.const] __ZL34gPatchInfoOffset_ci_TexColorKey_PS 000000000016b1b0 l 0e SECT 03 0000 [.const] __ZL32gPatchInfoCode_ci_TexColorKey_PS 000000000016b250 l 0e SECT 03 0000 [.const] __ZL32gShaderCode_ci_TexSrcColorKey_PS 000000000016b310 l 0e SECT 03 0000 [.const] __ZL33gShRegisters_ci_TexSrcColorKey_PS 000000000016b320 l 0e SECT 03 0000 [.const] __ZL38gContextRegisters_ci_TexSrcColorKey_PS 000000000016b360 l 0e SECT 03 0000 [.const] __ZL38gUserElementTable_ci_TexSrcColorKey_PS 000000000016b3b0 l 0e SECT 03 0000 [.const] __ZL33gInSemantics_ci_TexSrcColorKey_PS 000000000016b3c4 l 0e SECT 03 0000 [.const] __ZL37gPatchInfoOffset_ci_TexSrcColorKey_PS 000000000016b3d0 l 0e SECT 03 0000 [.const] __ZL35gPatchInfoCode_ci_TexSrcColorKey_PS 000000000016b470 l 0e SECT 03 0000 [.const] __ZL29gShaderCode_ci_TexMulConst_PS 000000000016b4d0 l 0e SECT 03 0000 [.const] __ZL30gShRegisters_ci_TexMulConst_PS 000000000016b4e0 l 0e SECT 03 0000 [.const] __ZL35gContextRegisters_ci_TexMulConst_PS 000000000016b520 l 0e SECT 03 0000 [.const] __ZL35gUserElementTable_ci_TexMulConst_PS 000000000016b570 l 0e SECT 03 0000 [.const] __ZL30gInSemantics_ci_TexMulConst_PS 000000000016b584 l 0e SECT 03 0000 [.const] __ZL34gPatchInfoOffset_ci_TexMulConst_PS 000000000016b590 l 0e SECT 03 0000 [.const] __ZL32gPatchInfoCode_ci_TexMulConst_PS 000000000016b630 l 0e SECT 03 0000 [.const] __ZL27gShaderCode_ci_TexDither_PS 000000000016b6a0 l 0e SECT 03 0000 [.const] __ZL28gShRegisters_ci_TexDither_PS 000000000016b6b0 l 0e SECT 03 0000 [.const] __ZL33gContextRegisters_ci_TexDither_PS 000000000016b6f0 l 0e SECT 03 0000 [.const] __ZL33gUserElementTable_ci_TexDither_PS 000000000016b750 l 0e SECT 03 0000 [.const] __ZL28gInSemantics_ci_TexDither_PS 000000000016b764 l 0e SECT 03 0000 [.const] __ZL32gPatchInfoOffset_ci_TexDither_PS 000000000016b770 l 0e SECT 03 0000 [.const] __ZL30gPatchInfoCode_ci_TexDither_PS 000000000016b810 l 0e SECT 03 0000 [.const] __ZL26gShaderCode_ci_YuvToRgb_PS 000000000016b8e0 l 0e SECT 03 0000 [.const] __ZL27gShRegisters_ci_YuvToRgb_PS 000000000016b8f0 l 0e SECT 03 0000 [.const] __ZL32gContextRegisters_ci_YuvToRgb_PS 000000000016b930 l 0e SECT 03 0000 [.const] __ZL32gUserElementTable_ci_YuvToRgb_PS 000000000016b980 l 0e SECT 03 0000 [.const] __ZL27gInSemantics_ci_YuvToRgb_PS 000000000016b994 l 0e SECT 03 0000 [.const] __ZL31gPatchInfoOffset_ci_YuvToRgb_PS 000000000016b9a0 l 0e SECT 03 0000 [.const] __ZL29gPatchInfoCode_ci_YuvToRgb_PS 000000000016ba40 l 0e SECT 03 0000 [.const] __ZL31gShaderCode_ci_YuvIntUvToRgb_PS 000000000016baf0 l 0e SECT 03 0000 [.const] __ZL32gShRegisters_ci_YuvIntUvToRgb_PS 000000000016bb00 l 0e SECT 03 0000 [.const] __ZL37gContextRegisters_ci_YuvIntUvToRgb_PS 000000000016bb40 l 0e SECT 03 0000 [.const] __ZL37gUserElementTable_ci_YuvIntUvToRgb_PS 000000000016bba0 l 0e SECT 03 0000 [.const] __ZL32gInSemantics_ci_YuvIntUvToRgb_PS 000000000016bbb4 l 0e SECT 03 0000 [.const] __ZL36gPatchInfoOffset_ci_YuvIntUvToRgb_PS 000000000016bbc0 l 0e SECT 03 0000 [.const] __ZL34gPatchInfoCode_ci_YuvIntUvToRgb_PS 000000000016bc60 l 0e SECT 03 0000 [.const] __ZL32gShaderCode_ci_YuvIntUvToYuy2_PS 000000000016bd00 l 0e SECT 03 0000 [.const] __ZL33gShRegisters_ci_YuvIntUvToYuy2_PS 000000000016bd10 l 0e SECT 03 0000 [.const] __ZL38gContextRegisters_ci_YuvIntUvToYuy2_PS 000000000016bd50 l 0e SECT 03 0000 [.const] __ZL38gUserElementTable_ci_YuvIntUvToYuy2_PS 000000000016bdb0 l 0e SECT 03 0000 [.const] __ZL33gInSemantics_ci_YuvIntUvToYuy2_PS 000000000016bdc4 l 0e SECT 03 0000 [.const] __ZL37gPatchInfoOffset_ci_YuvIntUvToYuy2_PS 000000000016bdd0 l 0e SECT 03 0000 [.const] __ZL35gPatchInfoCode_ci_YuvIntUvToYuy2_PS 000000000016be70 l 0e SECT 03 0000 [.const] __ZL27gShaderCode_ci_YuvToYuy2_PS 000000000016bf20 l 0e SECT 03 0000 [.const] __ZL28gShRegisters_ci_YuvToYuy2_PS 000000000016bf30 l 0e SECT 03 0000 [.const] __ZL33gContextRegisters_ci_YuvToYuy2_PS 000000000016bf70 l 0e SECT 03 0000 [.const] __ZL33gUserElementTable_ci_YuvToYuy2_PS 000000000016bfc0 l 0e SECT 03 0000 [.const] __ZL28gInSemantics_ci_YuvToYuy2_PS 000000000016bfd4 l 0e SECT 03 0000 [.const] __ZL32gPatchInfoOffset_ci_YuvToYuy2_PS 000000000016bfe0 l 0e SECT 03 0000 [.const] __ZL30gPatchInfoCode_ci_YuvToYuy2_PS 000000000016c080 l 0e SECT 03 0000 [.const] __ZL35gShaderCode_ci_MsaaFMaskResolve2_PS 000000000016c140 l 0e SECT 03 0000 [.const] __ZL36gShRegisters_ci_MsaaFMaskResolve2_PS 000000000016c150 l 0e SECT 03 0000 [.const] __ZL41gContextRegisters_ci_MsaaFMaskResolve2_PS 000000000016c190 l 0e SECT 03 0000 [.const] __ZL41gUserElementTable_ci_MsaaFMaskResolve2_PS 000000000016c1c0 l 0e SECT 03 0000 [.const] __ZL36gInSemantics_ci_MsaaFMaskResolve2_PS 000000000016c1d4 l 0e SECT 03 0000 [.const] __ZL40gPatchInfoOffset_ci_MsaaFMaskResolve2_PS 000000000016c1e0 l 0e SECT 03 0000 [.const] __ZL38gPatchInfoCode_ci_MsaaFMaskResolve2_PS 000000000016c280 l 0e SECT 03 0000 [.const] __ZL35gShaderCode_ci_MsaaFMaskResolve4_PS 000000000016c3c0 l 0e SECT 03 0000 [.const] __ZL36gShRegisters_ci_MsaaFMaskResolve4_PS 000000000016c3d0 l 0e SECT 03 0000 [.const] __ZL41gContextRegisters_ci_MsaaFMaskResolve4_PS 000000000016c410 l 0e SECT 03 0000 [.const] __ZL41gUserElementTable_ci_MsaaFMaskResolve4_PS 000000000016c440 l 0e SECT 03 0000 [.const] __ZL36gInSemantics_ci_MsaaFMaskResolve4_PS 000000000016c454 l 0e SECT 03 0000 [.const] __ZL40gPatchInfoOffset_ci_MsaaFMaskResolve4_PS 000000000016c460 l 0e SECT 03 0000 [.const] __ZL38gPatchInfoCode_ci_MsaaFMaskResolve4_PS 000000000016c500 l 0e SECT 03 0000 [.const] __ZL35gShaderCode_ci_MsaaFMaskResolve8_PS 000000000016c6e0 l 0e SECT 03 0000 [.const] __ZL36gShRegisters_ci_MsaaFMaskResolve8_PS 000000000016c6f0 l 0e SECT 03 0000 [.const] __ZL41gContextRegisters_ci_MsaaFMaskResolve8_PS 000000000016c730 l 0e SECT 03 0000 [.const] __ZL41gUserElementTable_ci_MsaaFMaskResolve8_PS 000000000016c760 l 0e SECT 03 0000 [.const] __ZL36gInSemantics_ci_MsaaFMaskResolve8_PS 000000000016c774 l 0e SECT 03 0000 [.const] __ZL40gPatchInfoOffset_ci_MsaaFMaskResolve8_PS 000000000016c780 l 0e SECT 03 0000 [.const] __ZL38gPatchInfoCode_ci_MsaaFMaskResolve8_PS 000000000016c820 l 0e SECT 03 0000 [.const] __ZL44gShaderCode_ci_MsaaFMaskResolve2Frag4Samp_PS 000000000016c9d0 l 0e SECT 03 0000 [.const] __ZL45gShRegisters_ci_MsaaFMaskResolve2Frag4Samp_PS 000000000016c9e0 l 0e SECT 03 0000 [.const] __ZL50gContextRegisters_ci_MsaaFMaskResolve2Frag4Samp_PS 000000000016ca20 l 0e SECT 03 0000 [.const] __ZL50gUserElementTable_ci_MsaaFMaskResolve2Frag4Samp_PS 000000000016ca50 l 0e SECT 03 0000 [.const] __ZL45gInSemantics_ci_MsaaFMaskResolve2Frag4Samp_PS 000000000016ca64 l 0e SECT 03 0000 [.const] __ZL49gPatchInfoOffset_ci_MsaaFMaskResolve2Frag4Samp_PS 000000000016ca70 l 0e SECT 03 0000 [.const] __ZL47gPatchInfoCode_ci_MsaaFMaskResolve2Frag4Samp_PS 000000000016cb10 l 0e SECT 03 0000 [.const] __ZL44gShaderCode_ci_MsaaFMaskResolve2Frag8Samp_PS 000000000016ce00 l 0e SECT 03 0000 [.const] __ZL45gShRegisters_ci_MsaaFMaskResolve2Frag8Samp_PS 000000000016ce10 l 0e SECT 03 0000 [.const] __ZL50gContextRegisters_ci_MsaaFMaskResolve2Frag8Samp_PS 000000000016ce50 l 0e SECT 03 0000 [.const] __ZL50gUserElementTable_ci_MsaaFMaskResolve2Frag8Samp_PS 000000000016ce80 l 0e SECT 03 0000 [.const] __ZL45gInSemantics_ci_MsaaFMaskResolve2Frag8Samp_PS 000000000016ce94 l 0e SECT 03 0000 [.const] __ZL49gPatchInfoOffset_ci_MsaaFMaskResolve2Frag8Samp_PS 000000000016cea0 l 0e SECT 03 0000 [.const] __ZL47gPatchInfoCode_ci_MsaaFMaskResolve2Frag8Samp_PS 000000000016cf40 l 0e SECT 03 0000 [.const] __ZL45gShaderCode_ci_MsaaFMaskResolve2Frag16Samp_PS 000000000016d4a0 l 0e SECT 03 0000 [.const] __ZL46gShRegisters_ci_MsaaFMaskResolve2Frag16Samp_PS 000000000016d4b0 l 0e SECT 03 0000 [.const] __ZL51gContextRegisters_ci_MsaaFMaskResolve2Frag16Samp_PS 000000000016d4f0 l 0e SECT 03 0000 [.const] __ZL51gUserElementTable_ci_MsaaFMaskResolve2Frag16Samp_PS 000000000016d520 l 0e SECT 03 0000 [.const] __ZL46gInSemantics_ci_MsaaFMaskResolve2Frag16Samp_PS 000000000016d534 l 0e SECT 03 0000 [.const] __ZL50gPatchInfoOffset_ci_MsaaFMaskResolve2Frag16Samp_PS 000000000016d540 l 0e SECT 03 0000 [.const] __ZL48gPatchInfoCode_ci_MsaaFMaskResolve2Frag16Samp_PS 000000000016d5e0 l 0e SECT 03 0000 [.const] __ZL44gShaderCode_ci_MsaaFMaskResolve4Frag8Samp_PS 000000000016d880 l 0e SECT 03 0000 [.const] __ZL45gShRegisters_ci_MsaaFMaskResolve4Frag8Samp_PS 000000000016d890 l 0e SECT 03 0000 [.const] __ZL50gContextRegisters_ci_MsaaFMaskResolve4Frag8Samp_PS 000000000016d8d0 l 0e SECT 03 0000 [.const] __ZL50gUserElementTable_ci_MsaaFMaskResolve4Frag8Samp_PS 000000000016d900 l 0e SECT 03 0000 [.const] __ZL45gInSemantics_ci_MsaaFMaskResolve4Frag8Samp_PS 000000000016d914 l 0e SECT 03 0000 [.const] __ZL49gPatchInfoOffset_ci_MsaaFMaskResolve4Frag8Samp_PS 000000000016d920 l 0e SECT 03 0000 [.const] __ZL47gPatchInfoCode_ci_MsaaFMaskResolve4Frag8Samp_PS 000000000016d9c0 l 0e SECT 03 0000 [.const] __ZL45gShaderCode_ci_MsaaFMaskResolve4Frag16Samp_PS 000000000016def0 l 0e SECT 03 0000 [.const] __ZL46gShRegisters_ci_MsaaFMaskResolve4Frag16Samp_PS 000000000016df00 l 0e SECT 03 0000 [.const] __ZL51gContextRegisters_ci_MsaaFMaskResolve4Frag16Samp_PS 000000000016df40 l 0e SECT 03 0000 [.const] __ZL51gUserElementTable_ci_MsaaFMaskResolve4Frag16Samp_PS 000000000016df70 l 0e SECT 03 0000 [.const] __ZL46gInSemantics_ci_MsaaFMaskResolve4Frag16Samp_PS 000000000016df84 l 0e SECT 03 0000 [.const] __ZL50gPatchInfoOffset_ci_MsaaFMaskResolve4Frag16Samp_PS 000000000016df90 l 0e SECT 03 0000 [.const] __ZL48gPatchInfoCode_ci_MsaaFMaskResolve4Frag16Samp_PS 000000000016e030 l 0e SECT 03 0000 [.const] __ZL45gShaderCode_ci_MsaaFMaskResolve8Frag16Samp_PS 000000000016e500 l 0e SECT 03 0000 [.const] __ZL46gShRegisters_ci_MsaaFMaskResolve8Frag16Samp_PS 000000000016e510 l 0e SECT 03 0000 [.const] __ZL51gContextRegisters_ci_MsaaFMaskResolve8Frag16Samp_PS 000000000016e550 l 0e SECT 03 0000 [.const] __ZL51gUserElementTable_ci_MsaaFMaskResolve8Frag16Samp_PS 000000000016e580 l 0e SECT 03 0000 [.const] __ZL46gInSemantics_ci_MsaaFMaskResolve8Frag16Samp_PS 000000000016e594 l 0e SECT 03 0000 [.const] __ZL50gPatchInfoOffset_ci_MsaaFMaskResolve8Frag16Samp_PS 000000000016e5a0 l 0e SECT 03 0000 [.const] __ZL48gPatchInfoCode_ci_MsaaFMaskResolve8Frag16Samp_PS 000000000016e640 l 0e SECT 03 0000 [.const] __ZL32gShaderCode_ci_ColorTransform_PS 000000000016e880 l 0e SECT 03 0000 [.const] __ZL33gShRegisters_ci_ColorTransform_PS 000000000016e890 l 0e SECT 03 0000 [.const] __ZL38gContextRegisters_ci_ColorTransform_PS 000000000016e8d0 l 0e SECT 03 0000 [.const] __ZL38gUserElementTable_ci_ColorTransform_PS 000000000016e920 l 0e SECT 03 0000 [.const] __ZL33gInSemantics_ci_ColorTransform_PS 000000000016e934 l 0e SECT 03 0000 [.const] __ZL37gPatchInfoOffset_ci_ColorTransform_PS 000000000016e940 l 0e SECT 03 0000 [.const] __ZL35gPatchInfoCode_ci_ColorTransform_PS 000000000016e9e0 l 0e SECT 03 0000 [.const] __ZL39gShaderCode_ci_NonEvenLinearFilter1D_PS 000000000016eb00 l 0e SECT 03 0000 [.const] __ZL40gShRegisters_ci_NonEvenLinearFilter1D_PS 000000000016eb10 l 0e SECT 03 0000 [.const] __ZL45gContextRegisters_ci_NonEvenLinearFilter1D_PS 000000000016eb50 l 0e SECT 03 0000 [.const] __ZL45gUserElementTable_ci_NonEvenLinearFilter1D_PS 000000000016eba0 l 0e SECT 03 0000 [.const] __ZL40gInSemantics_ci_NonEvenLinearFilter1D_PS 000000000016ebb4 l 0e SECT 03 0000 [.const] __ZL44gPatchInfoOffset_ci_NonEvenLinearFilter1D_PS 000000000016ebc0 l 0e SECT 03 0000 [.const] __ZL42gPatchInfoCode_ci_NonEvenLinearFilter1D_PS 000000000016ec60 l 0e SECT 03 0000 [.const] __ZL39gShaderCode_ci_NonEvenLinearFilter2D_PS 000000000016ee40 l 0e SECT 03 0000 [.const] __ZL40gShRegisters_ci_NonEvenLinearFilter2D_PS 000000000016ee50 l 0e SECT 03 0000 [.const] __ZL45gContextRegisters_ci_NonEvenLinearFilter2D_PS 000000000016ee90 l 0e SECT 03 0000 [.const] __ZL45gUserElementTable_ci_NonEvenLinearFilter2D_PS 000000000016eee0 l 0e SECT 03 0000 [.const] __ZL40gInSemantics_ci_NonEvenLinearFilter2D_PS 000000000016eef4 l 0e SECT 03 0000 [.const] __ZL44gPatchInfoOffset_ci_NonEvenLinearFilter2D_PS 000000000016ef00 l 0e SECT 03 0000 [.const] __ZL42gPatchInfoCode_ci_NonEvenLinearFilter2D_PS 000000000016efa0 l 0e SECT 03 0000 [.const] __ZL39gShaderCode_ci_NonEvenLinearFilter3D_PS 000000000016f250 l 0e SECT 03 0000 [.const] __ZL40gShRegisters_ci_NonEvenLinearFilter3D_PS 000000000016f260 l 0e SECT 03 0000 [.const] __ZL45gContextRegisters_ci_NonEvenLinearFilter3D_PS 000000000016f2a0 l 0e SECT 03 0000 [.const] __ZL45gUserElementTable_ci_NonEvenLinearFilter3D_PS 000000000016f2f0 l 0e SECT 03 0000 [.const] __ZL40gInSemantics_ci_NonEvenLinearFilter3D_PS 000000000016f304 l 0e SECT 03 0000 [.const] __ZL44gPatchInfoOffset_ci_NonEvenLinearFilter3D_PS 000000000016f310 l 0e SECT 03 0000 [.const] __ZL42gPatchInfoCode_ci_NonEvenLinearFilter3D_PS 000000000016f3b0 l 0e SECT 03 0000 [.const] __ZL39gShaderCode_ci_MLAACalcSepEdgeLength_PS 000000000016f7c0 l 0e SECT 03 0000 [.const] __ZL40gShRegisters_ci_MLAACalcSepEdgeLength_PS 000000000016f7d0 l 0e SECT 03 0000 [.const] __ZL45gContextRegisters_ci_MLAACalcSepEdgeLength_PS 000000000016f810 l 0e SECT 03 0000 [.const] __ZL45gUserElementTable_ci_MLAACalcSepEdgeLength_PS 000000000016f840 l 0e SECT 03 0000 [.const] __ZL40gInSemantics_ci_MLAACalcSepEdgeLength_PS 000000000016f854 l 0e SECT 03 0000 [.const] __ZL44gPatchInfoOffset_ci_MLAACalcSepEdgeLength_PS 000000000016f860 l 0e SECT 03 0000 [.const] __ZL42gPatchInfoCode_ci_MLAACalcSepEdgeLength_PS 000000000016f9a0 l 0e SECT 03 0000 [.const] __ZL43gShaderCode_ci_MLAACalcSepEdgeLengthFast_PS 000000000016ffe0 l 0e SECT 03 0000 [.const] __ZL44gShRegisters_ci_MLAACalcSepEdgeLengthFast_PS 000000000016fff0 l 0e SECT 03 0000 [.const] __ZL49gContextRegisters_ci_MLAACalcSepEdgeLengthFast_PS 0000000000170030 l 0e SECT 03 0000 [.const] __ZL49gUserElementTable_ci_MLAACalcSepEdgeLengthFast_PS 0000000000170060 l 0e SECT 03 0000 [.const] __ZL44gInSemantics_ci_MLAACalcSepEdgeLengthFast_PS 0000000000170074 l 0e SECT 03 0000 [.const] __ZL48gPatchInfoOffset_ci_MLAACalcSepEdgeLengthFast_PS 0000000000170080 l 0e SECT 03 0000 [.const] __ZL46gPatchInfoCode_ci_MLAACalcSepEdgeLengthFast_PS 0000000000170120 l 0e SECT 03 0000 [.const] __ZL46gShaderCode_ci_MLAACalcSepEdgeLengthInitial_PS 0000000000170320 l 0e SECT 03 0000 [.const] __ZL47gShRegisters_ci_MLAACalcSepEdgeLengthInitial_PS 0000000000170330 l 0e SECT 03 0000 [.const] __ZL52gContextRegisters_ci_MLAACalcSepEdgeLengthInitial_PS 0000000000170370 l 0e SECT 03 0000 [.const] __ZL52gUserElementTable_ci_MLAACalcSepEdgeLengthInitial_PS 00000000001703a0 l 0e SECT 03 0000 [.const] __ZL47gInSemantics_ci_MLAACalcSepEdgeLengthInitial_PS 00000000001703b4 l 0e SECT 03 0000 [.const] __ZL51gPatchInfoOffset_ci_MLAACalcSepEdgeLengthInitial_PS 00000000001703c0 l 0e SECT 03 0000 [.const] __ZL49gPatchInfoCode_ci_MLAACalcSepEdgeLengthInitial_PS 0000000000170500 l 0e SECT 03 0000 [.const] __ZL32gShaderCode_ci_MLAAFinalBlend_PS 0000000000170d70 l 0e SECT 03 0000 [.const] __ZL33gShRegisters_ci_MLAAFinalBlend_PS 0000000000170d80 l 0e SECT 03 0000 [.const] __ZL38gContextRegisters_ci_MLAAFinalBlend_PS 0000000000170dc0 l 0e SECT 03 0000 [.const] __ZL38gUserElementTable_ci_MLAAFinalBlend_PS 0000000000170de0 l 0e SECT 03 0000 [.const] __ZL33gInSemantics_ci_MLAAFinalBlend_PS 0000000000170df4 l 0e SECT 03 0000 [.const] __ZL37gPatchInfoOffset_ci_MLAAFinalBlend_PS 0000000000170e00 l 0e SECT 03 0000 [.const] __ZL35gPatchInfoCode_ci_MLAAFinalBlend_PS 0000000000170ea0 l 0e SECT 03 0000 [.const] __ZL36gShaderCode_ci_MLAAFinalBlendFast_PS 00000000001717a0 l 0e SECT 03 0000 [.const] __ZL37gShRegisters_ci_MLAAFinalBlendFast_PS 00000000001717b0 l 0e SECT 03 0000 [.const] __ZL42gContextRegisters_ci_MLAAFinalBlendFast_PS 00000000001717f0 l 0e SECT 03 0000 [.const] __ZL42gUserElementTable_ci_MLAAFinalBlendFast_PS 0000000000171820 l 0e SECT 03 0000 [.const] __ZL37gInSemantics_ci_MLAAFinalBlendFast_PS 0000000000171834 l 0e SECT 03 0000 [.const] __ZL41gPatchInfoOffset_ci_MLAAFinalBlendFast_PS 0000000000171840 l 0e SECT 03 0000 [.const] __ZL39gPatchInfoCode_ci_MLAAFinalBlendFast_PS 00000000001718e0 l 0e SECT 03 0000 [.const] __ZL33gShaderCode_ci_MLAAFindSepEdge_PS 00000000001719e0 l 0e SECT 03 0000 [.const] __ZL34gShRegisters_ci_MLAAFindSepEdge_PS 00000000001719f0 l 0e SECT 03 0000 [.const] __ZL39gContextRegisters_ci_MLAAFindSepEdge_PS 0000000000171a30 l 0e SECT 03 0000 [.const] __ZL39gUserElementTable_ci_MLAAFindSepEdge_PS 0000000000171a60 l 0e SECT 03 0000 [.const] __ZL34gInSemantics_ci_MLAAFindSepEdge_PS 0000000000171a74 l 0e SECT 03 0000 [.const] __ZL38gPatchInfoOffset_ci_MLAAFindSepEdge_PS 0000000000171a80 l 0e SECT 03 0000 [.const] __ZL36gPatchInfoCode_ci_MLAAFindSepEdge_PS 0000000000171b20 l 0e SECT 03 0000 [.const] __ZL30gShaderCode_ci_GenZRangeTex_PS 0000000000171e60 l 0e SECT 03 0000 [.const] __ZL31gShRegisters_ci_GenZRangeTex_PS 0000000000171e70 l 0e SECT 03 0000 [.const] __ZL36gContextRegisters_ci_GenZRangeTex_PS 0000000000171eb0 l 0e SECT 03 0000 [.const] __ZL36gUserElementTable_ci_GenZRangeTex_PS 0000000000171f00 l 0e SECT 03 0000 [.const] __ZL31gInSemantics_ci_GenZRangeTex_PS 0000000000171f14 l 0e SECT 03 0000 [.const] __ZL35gPatchInfoOffset_ci_GenZRangeTex_PS 0000000000171f20 l 0e SECT 03 0000 [.const] __ZL33gPatchInfoCode_ci_GenZRangeTex_PS 0000000000171fc0 l 0e SECT 03 0000 [.const] __ZL30gShaderCode_ci_GenZRangeMip_PS 0000000000172060 l 0e SECT 03 0000 [.const] __ZL31gShRegisters_ci_GenZRangeMip_PS 0000000000172070 l 0e SECT 03 0000 [.const] __ZL36gContextRegisters_ci_GenZRangeMip_PS 00000000001720b0 l 0e SECT 03 0000 [.const] __ZL36gUserElementTable_ci_GenZRangeMip_PS 0000000000172100 l 0e SECT 03 0000 [.const] __ZL31gInSemantics_ci_GenZRangeMip_PS 0000000000172114 l 0e SECT 03 0000 [.const] __ZL35gPatchInfoOffset_ci_GenZRangeMip_PS 0000000000172120 l 0e SECT 03 0000 [.const] __ZL33gPatchInfoCode_ci_GenZRangeMip_PS 00000000001721c0 l 0e SECT 03 0000 [.const] __ZL33gShaderCode_ci_GenZRangeMipOdd_PS 00000000001723c0 l 0e SECT 03 0000 [.const] __ZL34gShRegisters_ci_GenZRangeMipOdd_PS 00000000001723d0 l 0e SECT 03 0000 [.const] __ZL39gContextRegisters_ci_GenZRangeMipOdd_PS 0000000000172410 l 0e SECT 03 0000 [.const] __ZL39gUserElementTable_ci_GenZRangeMipOdd_PS 0000000000172440 l 0e SECT 03 0000 [.const] __ZL34gInSemantics_ci_GenZRangeMipOdd_PS 0000000000172454 l 0e SECT 03 0000 [.const] __ZL38gPatchInfoOffset_ci_GenZRangeMipOdd_PS 0000000000172460 l 0e SECT 03 0000 [.const] __ZL36gPatchInfoCode_ci_GenZRangeMipOdd_PS 0000000000172500 l 0e SECT 03 0000 [.const] __ZL27gShaderCode_ci_Composite_PS 0000000000172bb0 l 0e SECT 03 0000 [.const] __ZL28gShRegisters_ci_Composite_PS 0000000000172bc0 l 0e SECT 03 0000 [.const] __ZL33gContextRegisters_ci_Composite_PS 0000000000172c00 l 0e SECT 03 0000 [.const] __ZL33gUserElementTable_ci_Composite_PS 0000000000172c50 l 0e SECT 03 0000 [.const] __ZL28gInSemantics_ci_Composite_PS 0000000000172c78 l 0e SECT 03 0000 [.const] __ZL32gPatchInfoOffset_ci_Composite_PS 0000000000172c80 l 0e SECT 03 0000 [.const] __ZL30gPatchInfoCode_ci_Composite_PS 0000000000172d20 l 0e SECT 03 0000 [.const] __ZL29gShaderCode_ci_BufferClear_CS 0000000000172d50 l 0e SECT 03 0000 [.const] __ZL30gShRegisters_ci_BufferClear_CS 0000000000172d78 l 0e SECT 03 0000 [.const] __ZL35gContextRegisters_ci_BufferClear_CS 0000000000172d80 l 0e SECT 03 0000 [.const] __ZL35gUserElementTable_ci_BufferClear_CS 0000000000172db0 l 0e SECT 03 0000 [.const] __ZL28gShaderCode_ci_BufferCopy_CS 0000000000172dd0 l 0e SECT 03 0000 [.const] __ZL29gShRegisters_ci_BufferCopy_CS 0000000000172df8 l 0e SECT 03 0000 [.const] __ZL34gContextRegisters_ci_BufferCopy_CS 0000000000172e00 l 0e SECT 03 0000 [.const] __ZL34gUserElementTable_ci_BufferCopy_CS 0000000000172e30 l 0e SECT 03 0000 [.const] __ZL30gShaderCode_ci_SurfaceClear_CS 0000000000172e90 l 0e SECT 03 0000 [.const] __ZL31gShRegisters_ci_SurfaceClear_CS 0000000000172eb8 l 0e SECT 03 0000 [.const] __ZL36gContextRegisters_ci_SurfaceClear_CS 0000000000172ec0 l 0e SECT 03 0000 [.const] __ZL36gUserElementTable_ci_SurfaceClear_CS 0000000000172ef0 l 0e SECT 03 0000 [.const] __ZL31gShaderCode_ci_LinGenDstCopy_CS 0000000000172f70 l 0e SECT 03 0000 [.const] __ZL32gShRegisters_ci_LinGenDstCopy_CS 0000000000172f98 l 0e SECT 03 0000 [.const] __ZL37gContextRegisters_ci_LinGenDstCopy_CS 0000000000172fa0 l 0e SECT 03 0000 [.const] __ZL37gUserElementTable_ci_LinGenDstCopy_CS 0000000000172ff0 l 0e SECT 03 0000 [.const] __ZL31gShaderCode_ci_LinGenSrcCopy_CS 0000000000173060 l 0e SECT 03 0000 [.const] __ZL32gShRegisters_ci_LinGenSrcCopy_CS 0000000000173088 l 0e SECT 03 0000 [.const] __ZL37gContextRegisters_ci_LinGenSrcCopy_CS 0000000000173090 l 0e SECT 03 0000 [.const] __ZL37gUserElementTable_ci_LinGenSrcCopy_CS 00000000001730e0 l 0e SECT 03 0000 [.const] __ZL34gShaderCode_ci_LinGenSrcDstCopy_CS 0000000000173160 l 0e SECT 03 0000 [.const] __ZL35gShRegisters_ci_LinGenSrcDstCopy_CS 0000000000173188 l 0e SECT 03 0000 [.const] __ZL40gContextRegisters_ci_LinGenSrcDstCopy_CS 0000000000173190 l 0e SECT 03 0000 [.const] __ZL40gUserElementTable_ci_LinGenSrcDstCopy_CS 00000000001731e0 l 0e SECT 03 0000 [.const] __ZL27gShaderCode_ci_HtileCopy_CS 0000000000173210 l 0e SECT 03 0000 [.const] __ZL28gShRegisters_ci_HtileCopy_CS 0000000000173238 l 0e SECT 03 0000 [.const] __ZL33gContextRegisters_ci_HtileCopy_CS 0000000000173240 l 0e SECT 03 0000 [.const] __ZL33gUserElementTable_ci_HtileCopy_CS 0000000000173270 l 0e SECT 03 0000 [.const] __ZL38gShaderCode_ci_MsaaFMaskExpand2Samp_CS 0000000000173310 l 0e SECT 03 0000 [.const] __ZL39gShRegisters_ci_MsaaFMaskExpand2Samp_CS 0000000000173338 l 0e SECT 03 0000 [.const] __ZL44gContextRegisters_ci_MsaaFMaskExpand2Samp_CS 0000000000173340 l 0e SECT 03 0000 [.const] __ZL44gUserElementTable_ci_MsaaFMaskExpand2Samp_CS 0000000000173360 l 0e SECT 03 0000 [.const] __ZL38gShaderCode_ci_MsaaFMaskExpand4Samp_CS 0000000000173460 l 0e SECT 03 0000 [.const] __ZL39gShRegisters_ci_MsaaFMaskExpand4Samp_CS 0000000000173488 l 0e SECT 03 0000 [.const] __ZL44gContextRegisters_ci_MsaaFMaskExpand4Samp_CS 0000000000173490 l 0e SECT 03 0000 [.const] __ZL44gUserElementTable_ci_MsaaFMaskExpand4Samp_CS 00000000001734b0 l 0e SECT 03 0000 [.const] __ZL38gShaderCode_ci_MsaaFMaskExpand8Samp_CS 0000000000173670 l 0e SECT 03 0000 [.const] __ZL39gShRegisters_ci_MsaaFMaskExpand8Samp_CS 0000000000173698 l 0e SECT 03 0000 [.const] __ZL44gContextRegisters_ci_MsaaFMaskExpand8Samp_CS 00000000001736a0 l 0e SECT 03 0000 [.const] __ZL44gUserElementTable_ci_MsaaFMaskExpand8Samp_CS 00000000001736c0 l 0e SECT 03 0000 [.const] __ZL32gShaderCode_ci_FastDepthClear_CS 0000000000173720 l 0e SECT 03 0000 [.const] __ZL33gShRegisters_ci_FastDepthClear_CS 0000000000173748 l 0e SECT 03 0000 [.const] __ZL38gContextRegisters_ci_FastDepthClear_CS 0000000000173750 l 0e SECT 03 0000 [.const] __ZL38gUserElementTable_ci_FastDepthClear_CS 0000000000173780 l 0e SECT 03 0000 [.const] __ZL35gShaderCode_ci_FastDepthExpClear_CS 0000000000173810 l 0e SECT 03 0000 [.const] __ZL36gShRegisters_ci_FastDepthExpClear_CS 0000000000173838 l 0e SECT 03 0000 [.const] __ZL41gContextRegisters_ci_FastDepthExpClear_CS 0000000000173840 l 0e SECT 03 0000 [.const] __ZL41gUserElementTable_ci_FastDepthExpClear_CS 0000000000173870 l 0e SECT 03 0000 [.const] __ZL37gShaderCode_ci_LinGenDstRepackCopy_CS 0000000000173950 l 0e SECT 03 0000 [.const] __ZL38gShRegisters_ci_LinGenDstRepackCopy_CS 0000000000173978 l 0e SECT 03 0000 [.const] __ZL43gContextRegisters_ci_LinGenDstRepackCopy_CS 0000000000173980 l 0e SECT 03 0000 [.const] __ZL43gUserElementTable_ci_LinGenDstRepackCopy_CS 00000000001739d0 l 0e SECT 03 0000 [.const] __ZL31gShaderCode_ci_VolumeTexCopy_CS 0000000000173a60 l 0e SECT 03 0000 [.const] __ZL32gShRegisters_ci_VolumeTexCopy_CS 0000000000173a88 l 0e SECT 03 0000 [.const] __ZL37gContextRegisters_ci_VolumeTexCopy_CS 0000000000173a90 l 0e SECT 03 0000 [.const] __ZL37gUserElementTable_ci_VolumeTexCopy_CS 0000000000173ae0 l 0e SECT 03 0000 [.const] __ZL29gShaderCode_ci_GenerateHiS_PS 0000000000173b80 l 0e SECT 03 0000 [.const] __ZL30gShRegisters_ci_GenerateHiS_PS 0000000000173b90 l 0e SECT 03 0000 [.const] __ZL35gContextRegisters_ci_GenerateHiS_PS 0000000000173bd0 l 0e SECT 03 0000 [.const] __ZL35gUserElementTable_ci_GenerateHiS_PS 0000000000173c20 l 0e SECT 03 0000 [.const] __ZL30gInSemantics_ci_GenerateHiS_PS 0000000000173c34 l 0e SECT 03 0000 [.const] __ZL34gPatchInfoOffset_ci_GenerateHiS_PS 0000000000173c40 l 0e SECT 03 0000 [.const] __ZL32gPatchInfoCode_ci_GenerateHiS_PS 0000000000173ce0 l 0e SECT 03 0000 [.const] __ZL27gShaderCode_ci_AdvAARes1_PS 0000000000173d40 l 0e SECT 03 0000 [.const] __ZL28gShRegisters_ci_AdvAARes1_PS 0000000000173d50 l 0e SECT 03 0000 [.const] __ZL33gContextRegisters_ci_AdvAARes1_PS 0000000000173d90 l 0e SECT 03 0000 [.const] __ZL33gUserElementTable_ci_AdvAARes1_PS 0000000000173dc0 l 0e SECT 03 0000 [.const] __ZL28gInSemantics_ci_AdvAARes1_PS 0000000000173dd4 l 0e SECT 03 0000 [.const] __ZL32gPatchInfoOffset_ci_AdvAARes1_PS 0000000000173de0 l 0e SECT 03 0000 [.const] __ZL30gPatchInfoCode_ci_AdvAARes1_PS 0000000000173f20 l 0e SECT 03 0000 [.const] __ZL36gShaderCode_ci_AdvAAEdgeMask4Samp_PS 00000000001740f0 l 0e SECT 03 0000 [.const] __ZL37gShRegisters_ci_AdvAAEdgeMask4Samp_PS 0000000000174100 l 0e SECT 03 0000 [.const] __ZL42gContextRegisters_ci_AdvAAEdgeMask4Samp_PS 0000000000174140 l 0e SECT 03 0000 [.const] __ZL42gUserElementTable_ci_AdvAAEdgeMask4Samp_PS 0000000000174170 l 0e SECT 03 0000 [.const] __ZL37gInSemantics_ci_AdvAAEdgeMask4Samp_PS 0000000000174184 l 0e SECT 03 0000 [.const] __ZL41gPatchInfoOffset_ci_AdvAAEdgeMask4Samp_PS 0000000000174190 l 0e SECT 03 0000 [.const] __ZL39gPatchInfoCode_ci_AdvAAEdgeMask4Samp_PS 0000000000174370 l 0e SECT 03 0000 [.const] __ZL36gShaderCode_ci_AdvAAEdgeMask8Samp_PS 0000000000174660 l 0e SECT 03 0000 [.const] __ZL37gShRegisters_ci_AdvAAEdgeMask8Samp_PS 0000000000174670 l 0e SECT 03 0000 [.const] __ZL42gContextRegisters_ci_AdvAAEdgeMask8Samp_PS 00000000001746b0 l 0e SECT 03 0000 [.const] __ZL42gUserElementTable_ci_AdvAAEdgeMask8Samp_PS 00000000001746e0 l 0e SECT 03 0000 [.const] __ZL37gInSemantics_ci_AdvAAEdgeMask8Samp_PS 00000000001746f4 l 0e SECT 03 0000 [.const] __ZL41gPatchInfoOffset_ci_AdvAAEdgeMask8Samp_PS 0000000000174700 l 0e SECT 03 0000 [.const] __ZL39gPatchInfoCode_ci_AdvAAEdgeMask8Samp_PS 00000000001748e0 l 0e SECT 03 0000 [.const] __ZL37gShaderCode_ci_AdvAAFilterMaskFast_PS 0000000000174b20 l 0e SECT 03 0000 [.const] __ZL38gShRegisters_ci_AdvAAFilterMaskFast_PS 0000000000174b30 l 0e SECT 03 0000 [.const] __ZL43gContextRegisters_ci_AdvAAFilterMaskFast_PS 0000000000174b70 l 0e SECT 03 0000 [.const] __ZL43gUserElementTable_ci_AdvAAFilterMaskFast_PS 0000000000174b90 l 0e SECT 03 0000 [.const] __ZL38gInSemantics_ci_AdvAAFilterMaskFast_PS 0000000000174ba4 l 0e SECT 03 0000 [.const] __ZL42gPatchInfoOffset_ci_AdvAAFilterMaskFast_PS 0000000000174bb0 l 0e SECT 03 0000 [.const] __ZL40gPatchInfoCode_ci_AdvAAFilterMaskFast_PS 0000000000174c50 l 0e SECT 03 0000 [.const] __ZL37gShaderCode_ci_AdvAAGrad4SampNoReZ_PS 0000000000176530 l 0e SECT 03 0000 [.const] __ZL38gShRegisters_ci_AdvAAGrad4SampNoReZ_PS 0000000000176540 l 0e SECT 03 0000 [.const] __ZL43gContextRegisters_ci_AdvAAGrad4SampNoReZ_PS 0000000000176580 l 0e SECT 03 0000 [.const] __ZL43gUserElementTable_ci_AdvAAGrad4SampNoReZ_PS 00000000001765b0 l 0e SECT 03 0000 [.const] __ZL38gInSemantics_ci_AdvAAGrad4SampNoReZ_PS 00000000001765c4 l 0e SECT 03 0000 [.const] __ZL42gPatchInfoOffset_ci_AdvAAGrad4SampNoReZ_PS 00000000001765d0 l 0e SECT 03 0000 [.const] __ZL40gPatchInfoCode_ci_AdvAAGrad4SampNoReZ_PS 0000000000176670 l 0e SECT 03 0000 [.const] __ZL37gShaderCode_ci_AdvAAGrad8SampNoReZ_PS 00000000001797b0 l 0e SECT 03 0000 [.const] __ZL38gShRegisters_ci_AdvAAGrad8SampNoReZ_PS 00000000001797c0 l 0e SECT 03 0000 [.const] __ZL43gContextRegisters_ci_AdvAAGrad8SampNoReZ_PS 0000000000179800 l 0e SECT 03 0000 [.const] __ZL43gUserElementTable_ci_AdvAAGrad8SampNoReZ_PS 0000000000179830 l 0e SECT 03 0000 [.const] __ZL38gInSemantics_ci_AdvAAGrad8SampNoReZ_PS 0000000000179844 l 0e SECT 03 0000 [.const] __ZL42gPatchInfoOffset_ci_AdvAAGrad8SampNoReZ_PS 0000000000179850 l 0e SECT 03 0000 [.const] __ZL40gPatchInfoCode_ci_AdvAAGrad8SampNoReZ_PS 00000000001798f0 l 0e SECT 03 0000 [.const] __ZL36gShaderCode_ci_AdvAAEdG4SampNoReZ_PS 000000000017b960 l 0e SECT 03 0000 [.const] __ZL37gShRegisters_ci_AdvAAEdG4SampNoReZ_PS 000000000017b970 l 0e SECT 03 0000 [.const] __ZL42gContextRegisters_ci_AdvAAEdG4SampNoReZ_PS 000000000017b9b0 l 0e SECT 03 0000 [.const] __ZL42gUserElementTable_ci_AdvAAEdG4SampNoReZ_PS 000000000017b9e0 l 0e SECT 03 0000 [.const] __ZL37gInSemantics_ci_AdvAAEdG4SampNoReZ_PS 000000000017b9f4 l 0e SECT 03 0000 [.const] __ZL41gPatchInfoOffset_ci_AdvAAEdG4SampNoReZ_PS 000000000017ba00 l 0e SECT 03 0000 [.const] __ZL39gPatchInfoCode_ci_AdvAAEdG4SampNoReZ_PS 000000000017baa0 l 0e SECT 03 0000 [.const] __ZL36gShaderCode_ci_AdvAAEdG8SampNoReZ_PS 000000000017fa70 l 0e SECT 03 0000 [.const] __ZL37gShRegisters_ci_AdvAAEdG8SampNoReZ_PS 000000000017fa80 l 0e SECT 03 0000 [.const] __ZL42gContextRegisters_ci_AdvAAEdG8SampNoReZ_PS 000000000017fac0 l 0e SECT 03 0000 [.const] __ZL42gUserElementTable_ci_AdvAAEdG8SampNoReZ_PS 000000000017faf0 l 0e SECT 03 0000 [.const] __ZL37gInSemantics_ci_AdvAAEdG8SampNoReZ_PS 000000000017fb04 l 0e SECT 03 0000 [.const] __ZL41gPatchInfoOffset_ci_AdvAAEdG8SampNoReZ_PS 000000000017fb10 l 0e SECT 03 0000 [.const] __ZL39gPatchInfoCode_ci_AdvAAEdG8SampNoReZ_PS 000000000017fbb0 l 0e SECT 03 0000 [.const] __ZL41gShaderCode_ci_AdvAAFMaskEdgeMask4Samp_PS 000000000017fe20 l 0e SECT 03 0000 [.const] __ZL42gShRegisters_ci_AdvAAFMaskEdgeMask4Samp_PS 000000000017fe30 l 0e SECT 03 0000 [.const] __ZL47gContextRegisters_ci_AdvAAFMaskEdgeMask4Samp_PS 000000000017fe70 l 0e SECT 03 0000 [.const] __ZL47gUserElementTable_ci_AdvAAFMaskEdgeMask4Samp_PS 000000000017fea0 l 0e SECT 03 0000 [.const] __ZL42gInSemantics_ci_AdvAAFMaskEdgeMask4Samp_PS 000000000017feb4 l 0e SECT 03 0000 [.const] __ZL46gPatchInfoOffset_ci_AdvAAFMaskEdgeMask4Samp_PS 000000000017fec0 l 0e SECT 03 0000 [.const] __ZL44gPatchInfoCode_ci_AdvAAFMaskEdgeMask4Samp_PS 00000000001800a0 l 0e SECT 03 0000 [.const] __ZL41gShaderCode_ci_AdvAAFMaskEdgeMask8Samp_PS 0000000000180520 l 0e SECT 03 0000 [.const] __ZL42gShRegisters_ci_AdvAAFMaskEdgeMask8Samp_PS 0000000000180530 l 0e SECT 03 0000 [.const] __ZL47gContextRegisters_ci_AdvAAFMaskEdgeMask8Samp_PS 0000000000180570 l 0e SECT 03 0000 [.const] __ZL47gUserElementTable_ci_AdvAAFMaskEdgeMask8Samp_PS 00000000001805a0 l 0e SECT 03 0000 [.const] __ZL42gInSemantics_ci_AdvAAFMaskEdgeMask8Samp_PS 00000000001805b4 l 0e SECT 03 0000 [.const] __ZL46gPatchInfoOffset_ci_AdvAAFMaskEdgeMask8Samp_PS 00000000001805c0 l 0e SECT 03 0000 [.const] __ZL44gPatchInfoCode_ci_AdvAAFMaskEdgeMask8Samp_PS 00000000001807a0 l 0e SECT 03 0000 [.const] __ZL41gShaderCode_ci_AdvAAFMaskEdG4SampNoReZ_PS 00000000001829b0 l 0e SECT 03 0000 [.const] __ZL42gShRegisters_ci_AdvAAFMaskEdG4SampNoReZ_PS 00000000001829c0 l 0e SECT 03 0000 [.const] __ZL47gContextRegisters_ci_AdvAAFMaskEdG4SampNoReZ_PS 0000000000182a00 l 0e SECT 03 0000 [.const] __ZL47gUserElementTable_ci_AdvAAFMaskEdG4SampNoReZ_PS 0000000000182a30 l 0e SECT 03 0000 [.const] __ZL42gInSemantics_ci_AdvAAFMaskEdG4SampNoReZ_PS 0000000000182a44 l 0e SECT 03 0000 [.const] __ZL46gPatchInfoOffset_ci_AdvAAFMaskEdG4SampNoReZ_PS 0000000000182a50 l 0e SECT 03 0000 [.const] __ZL44gPatchInfoCode_ci_AdvAAFMaskEdG4SampNoReZ_PS 0000000000182af0 l 0e SECT 03 0000 [.const] __ZL41gShaderCode_ci_AdvAAFMaskEdG8SampNoReZ_PS 0000000000186d30 l 0e SECT 03 0000 [.const] __ZL42gShRegisters_ci_AdvAAFMaskEdG8SampNoReZ_PS 0000000000186d40 l 0e SECT 03 0000 [.const] __ZL47gContextRegisters_ci_AdvAAFMaskEdG8SampNoReZ_PS 0000000000186d80 l 0e SECT 03 0000 [.const] __ZL47gUserElementTable_ci_AdvAAFMaskEdG8SampNoReZ_PS 0000000000186db0 l 0e SECT 03 0000 [.const] __ZL42gInSemantics_ci_AdvAAFMaskEdG8SampNoReZ_PS 0000000000186dc4 l 0e SECT 03 0000 [.const] __ZL46gPatchInfoOffset_ci_AdvAAFMaskEdG8SampNoReZ_PS 0000000000186dd0 l 0e SECT 03 0000 [.const] __ZL44gPatchInfoCode_ci_AdvAAFMaskEdG8SampNoReZ_PS 0000000000186e70 l 0e SECT 03 0000 [.const] __ZL25gShaderCode_vi_RectPos_VS 0000000000186fc0 l 0e SECT 03 0000 [.const] __ZL26gShRegisters_vi_RectPos_VS 0000000000186fd0 l 0e SECT 03 0000 [.const] __ZL31gContextRegisters_vi_RectPos_VS 0000000000186fe0 l 0e SECT 03 0000 [.const] __ZL31gUserElementTable_vi_RectPos_VS 0000000000187010 l 0e SECT 03 0000 [.const] __ZL27gOutSemantics_vi_RectPos_VS 0000000000187020 l 0e SECT 03 0000 [.const] __ZL31gShaderCode_vi_RectPosTexTex_VS 00000000001874b0 l 0e SECT 03 0000 [.const] __ZL32gShRegisters_vi_RectPosTexTex_VS 00000000001874c0 l 0e SECT 03 0000 [.const] __ZL37gContextRegisters_vi_RectPosTexTex_VS 00000000001874d0 l 0e SECT 03 0000 [.const] __ZL37gUserElementTable_vi_RectPosTexTex_VS 0000000000187500 l 0e SECT 03 0000 [.const] __ZL33gOutSemantics_vi_RectPosTexTex_VS 0000000000187520 l 0e SECT 03 0000 [.const] __ZL32gShaderCode_vi_RectPosTexFast_VS 00000000001875b0 l 0e SECT 03 0000 [.const] __ZL33gShRegisters_vi_RectPosTexFast_VS 00000000001875c0 l 0e SECT 03 0000 [.const] __ZL38gContextRegisters_vi_RectPosTexFast_VS 00000000001875d0 l 0e SECT 03 0000 [.const] __ZL38gUserElementTable_vi_RectPosTexFast_VS 0000000000187630 l 0e SECT 03 0000 [.const] __ZL34gOutSemantics_vi_RectPosTexFast_VS 0000000000187640 l 0e SECT 03 0000 [.const] __ZL30gShaderCode_vi_VertPosColor_VS 0000000000187690 l 0e SECT 03 0000 [.const] __ZL31gShRegisters_vi_VertPosColor_VS 00000000001876a0 l 0e SECT 03 0000 [.const] __ZL36gContextRegisters_vi_VertPosColor_VS 00000000001876b0 l 0e SECT 03 0000 [.const] __ZL36gUserElementTable_vi_VertPosColor_VS 00000000001876e0 l 0e SECT 03 0000 [.const] __ZL32gOutSemantics_vi_VertPosColor_VS 00000000001876f0 l 0e SECT 03 0000 [.const] __ZL40gShaderCode_vi_RectPosTexTexComposite_VS 00000000001878c0 l 0e SECT 03 0000 [.const] __ZL41gShRegisters_vi_RectPosTexTexComposite_VS 00000000001878d0 l 0e SECT 03 0000 [.const] __ZL46gContextRegisters_vi_RectPosTexTexComposite_VS 00000000001878e0 l 0e SECT 03 0000 [.const] __ZL46gUserElementTable_vi_RectPosTexTexComposite_VS 0000000000187910 l 0e SECT 03 0000 [.const] __ZL42gOutSemantics_vi_RectPosTexTexComposite_VS 0000000000187930 l 0e SECT 03 0000 [.const] __ZL22gShaderCode_vi_Zero_PS 0000000000187950 l 0e SECT 03 0000 [.const] __ZL23gShRegisters_vi_Zero_PS 0000000000187960 l 0e SECT 03 0000 [.const] __ZL28gContextRegisters_vi_Zero_PS 00000000001879a0 l 0e SECT 03 0000 [.const] __ZL28gUserElementTable_vi_Zero_PS 00000000001879c0 l 0e SECT 03 0000 [.const] __ZL23gInSemantics_vi_Zero_PS 00000000001879d4 l 0e SECT 03 0000 [.const] __ZL27gPatchInfoOffset_vi_Zero_PS 00000000001879e0 l 0e SECT 03 0000 [.const] __ZL25gPatchInfoCode_vi_Zero_PS 0000000000187ad0 l 0e SECT 03 0000 [.const] __ZL23gShaderCode_vi_Const_PS 0000000000187b00 l 0e SECT 03 0000 [.const] __ZL24gShRegisters_vi_Const_PS 0000000000187b10 l 0e SECT 03 0000 [.const] __ZL29gContextRegisters_vi_Const_PS 0000000000187b50 l 0e SECT 03 0000 [.const] __ZL29gUserElementTable_vi_Const_PS 0000000000187b70 l 0e SECT 03 0000 [.const] __ZL24gInSemantics_vi_Const_PS 0000000000187b84 l 0e SECT 03 0000 [.const] __ZL28gPatchInfoOffset_vi_Const_PS 0000000000187b90 l 0e SECT 03 0000 [.const] __ZL26gPatchInfoCode_vi_Const_PS 0000000000187c80 l 0e SECT 03 0000 [.const] __ZL21gShaderCode_vi_Tex_PS 0000000000187cd0 l 0e SECT 03 0000 [.const] __ZL22gShRegisters_vi_Tex_PS 0000000000187ce0 l 0e SECT 03 0000 [.const] __ZL27gContextRegisters_vi_Tex_PS 0000000000187d20 l 0e SECT 03 0000 [.const] __ZL27gUserElementTable_vi_Tex_PS 0000000000187d50 l 0e SECT 03 0000 [.const] __ZL22gInSemantics_vi_Tex_PS 0000000000187d64 l 0e SECT 03 0000 [.const] __ZL26gPatchInfoOffset_vi_Tex_PS 0000000000187d70 l 0e SECT 03 0000 [.const] __ZL24gPatchInfoCode_vi_Tex_PS 0000000000187e60 l 0e SECT 03 0000 [.const] __ZL26gShaderCode_vi_TexCoord_PS 0000000000187ea0 l 0e SECT 03 0000 [.const] __ZL27gShRegisters_vi_TexCoord_PS 0000000000187eb0 l 0e SECT 03 0000 [.const] __ZL32gContextRegisters_vi_TexCoord_PS 0000000000187ef0 l 0e SECT 03 0000 [.const] __ZL32gUserElementTable_vi_TexCoord_PS 0000000000187f10 l 0e SECT 03 0000 [.const] __ZL27gInSemantics_vi_TexCoord_PS 0000000000187f24 l 0e SECT 03 0000 [.const] __ZL31gPatchInfoOffset_vi_TexCoord_PS 0000000000187f30 l 0e SECT 03 0000 [.const] __ZL29gPatchInfoCode_vi_TexCoord_PS 0000000000188020 l 0e SECT 03 0000 [.const] __ZL29gShaderCode_vi_TexGammaDst_PS 0000000000188120 l 0e SECT 03 0000 [.const] __ZL30gShRegisters_vi_TexGammaDst_PS 0000000000188130 l 0e SECT 03 0000 [.const] __ZL35gContextRegisters_vi_TexGammaDst_PS 0000000000188170 l 0e SECT 03 0000 [.const] __ZL35gUserElementTable_vi_TexGammaDst_PS 00000000001881a0 l 0e SECT 03 0000 [.const] __ZL30gInSemantics_vi_TexGammaDst_PS 00000000001881b4 l 0e SECT 03 0000 [.const] __ZL34gPatchInfoOffset_vi_TexGammaDst_PS 00000000001881c0 l 0e SECT 03 0000 [.const] __ZL32gPatchInfoCode_vi_TexGammaDst_PS 00000000001882b0 l 0e SECT 03 0000 [.const] __ZL30gShaderCode_vi_MsaaResolve1_PS 0000000000188300 l 0e SECT 03 0000 [.const] __ZL31gShRegisters_vi_MsaaResolve1_PS 0000000000188310 l 0e SECT 03 0000 [.const] __ZL36gContextRegisters_vi_MsaaResolve1_PS 0000000000188350 l 0e SECT 03 0000 [.const] __ZL36gUserElementTable_vi_MsaaResolve1_PS 0000000000188380 l 0e SECT 03 0000 [.const] __ZL31gInSemantics_vi_MsaaResolve1_PS 0000000000188394 l 0e SECT 03 0000 [.const] __ZL35gPatchInfoOffset_vi_MsaaResolve1_PS 00000000001883a0 l 0e SECT 03 0000 [.const] __ZL33gPatchInfoCode_vi_MsaaResolve1_PS 0000000000188490 l 0e SECT 03 0000 [.const] __ZL30gShaderCode_vi_MsaaResolve2_PS 0000000000188510 l 0e SECT 03 0000 [.const] __ZL31gShRegisters_vi_MsaaResolve2_PS 0000000000188520 l 0e SECT 03 0000 [.const] __ZL36gContextRegisters_vi_MsaaResolve2_PS 0000000000188560 l 0e SECT 03 0000 [.const] __ZL36gUserElementTable_vi_MsaaResolve2_PS 0000000000188590 l 0e SECT 03 0000 [.const] __ZL31gInSemantics_vi_MsaaResolve2_PS 00000000001885a4 l 0e SECT 03 0000 [.const] __ZL35gPatchInfoOffset_vi_MsaaResolve2_PS 00000000001885b0 l 0e SECT 03 0000 [.const] __ZL33gPatchInfoCode_vi_MsaaResolve2_PS 00000000001886a0 l 0e SECT 03 0000 [.const] __ZL30gShaderCode_vi_MsaaResolve4_PS 0000000000188760 l 0e SECT 03 0000 [.const] __ZL31gShRegisters_vi_MsaaResolve4_PS 0000000000188770 l 0e SECT 03 0000 [.const] __ZL36gContextRegisters_vi_MsaaResolve4_PS 00000000001887b0 l 0e SECT 03 0000 [.const] __ZL36gUserElementTable_vi_MsaaResolve4_PS 00000000001887e0 l 0e SECT 03 0000 [.const] __ZL31gInSemantics_vi_MsaaResolve4_PS 00000000001887f4 l 0e SECT 03 0000 [.const] __ZL35gPatchInfoOffset_vi_MsaaResolve4_PS 0000000000188800 l 0e SECT 03 0000 [.const] __ZL33gPatchInfoCode_vi_MsaaResolve4_PS 00000000001888f0 l 0e SECT 03 0000 [.const] __ZL30gShaderCode_vi_MsaaResolve8_PS 0000000000188a20 l 0e SECT 03 0000 [.const] __ZL31gShRegisters_vi_MsaaResolve8_PS 0000000000188a30 l 0e SECT 03 0000 [.const] __ZL36gContextRegisters_vi_MsaaResolve8_PS 0000000000188a70 l 0e SECT 03 0000 [.const] __ZL36gUserElementTable_vi_MsaaResolve8_PS 0000000000188aa0 l 0e SECT 03 0000 [.const] __ZL31gInSemantics_vi_MsaaResolve8_PS 0000000000188ab4 l 0e SECT 03 0000 [.const] __ZL35gPatchInfoOffset_vi_MsaaResolve8_PS 0000000000188ac0 l 0e SECT 03 0000 [.const] __ZL33gPatchInfoCode_vi_MsaaResolve8_PS 0000000000188bb0 l 0e SECT 03 0000 [.const] __ZL33gShaderCode_vi_MsaaFMaskExpand_PS 0000000000188c60 l 0e SECT 03 0000 [.const] __ZL34gShRegisters_vi_MsaaFMaskExpand_PS 0000000000188c70 l 0e SECT 03 0000 [.const] __ZL39gContextRegisters_vi_MsaaFMaskExpand_PS 0000000000188cb0 l 0e SECT 03 0000 [.const] __ZL39gUserElementTable_vi_MsaaFMaskExpand_PS 0000000000188ce0 l 0e SECT 03 0000 [.const] __ZL34gInSemantics_vi_MsaaFMaskExpand_PS 0000000000188cf4 l 0e SECT 03 0000 [.const] __ZL38gPatchInfoOffset_vi_MsaaFMaskExpand_PS 0000000000188d00 l 0e SECT 03 0000 [.const] __ZL36gPatchInfoCode_vi_MsaaFMaskExpand_PS 0000000000188df0 l 0e SECT 03 0000 [.const] __ZL34gShaderCode_vi_MsaaDepthResolve_PS 0000000000188e40 l 0e SECT 03 0000 [.const] __ZL35gShRegisters_vi_MsaaDepthResolve_PS 0000000000188e50 l 0e SECT 03 0000 [.const] __ZL40gContextRegisters_vi_MsaaDepthResolve_PS 0000000000188e90 l 0e SECT 03 0000 [.const] __ZL40gUserElementTable_vi_MsaaDepthResolve_PS 0000000000188ec0 l 0e SECT 03 0000 [.const] __ZL35gInSemantics_vi_MsaaDepthResolve_PS 0000000000188ed4 l 0e SECT 03 0000 [.const] __ZL39gPatchInfoOffset_vi_MsaaDepthResolve_PS 0000000000188ee0 l 0e SECT 03 0000 [.const] __ZL37gPatchInfoCode_vi_MsaaDepthResolve_PS 0000000000188fd0 l 0e SECT 03 0000 [.const] __ZL41gShaderCode_vi_MsaaDepthStencilResolve_PS 0000000000189040 l 0e SECT 03 0000 [.const] __ZL42gShRegisters_vi_MsaaDepthStencilResolve_PS 0000000000189050 l 0e SECT 03 0000 [.const] __ZL47gContextRegisters_vi_MsaaDepthStencilResolve_PS 0000000000189090 l 0e SECT 03 0000 [.const] __ZL47gUserElementTable_vi_MsaaDepthStencilResolve_PS 00000000001890e0 l 0e SECT 03 0000 [.const] __ZL42gInSemantics_vi_MsaaDepthStencilResolve_PS 00000000001890f4 l 0e SECT 03 0000 [.const] __ZL46gPatchInfoOffset_vi_MsaaDepthStencilResolve_PS 0000000000189100 l 0e SECT 03 0000 [.const] __ZL44gPatchInfoCode_vi_MsaaDepthStencilResolve_PS 00000000001891f0 l 0e SECT 03 0000 [.const] __ZL36gShaderCode_vi_TexZStencilAsColor_PS 0000000000189260 l 0e SECT 03 0000 [.const] __ZL37gShRegisters_vi_TexZStencilAsColor_PS 0000000000189270 l 0e SECT 03 0000 [.const] __ZL42gContextRegisters_vi_TexZStencilAsColor_PS 00000000001892b0 l 0e SECT 03 0000 [.const] __ZL42gUserElementTable_vi_TexZStencilAsColor_PS 0000000000189300 l 0e SECT 03 0000 [.const] __ZL37gInSemantics_vi_TexZStencilAsColor_PS 0000000000189314 l 0e SECT 03 0000 [.const] __ZL41gPatchInfoOffset_vi_TexZStencilAsColor_PS 0000000000189320 l 0e SECT 03 0000 [.const] __ZL39gPatchInfoCode_vi_TexZStencilAsColor_PS 0000000000189410 l 0e SECT 03 0000 [.const] __ZL30gShRegisters_vi_TexAlphaOne_PS 0000000000189420 l 0e SECT 03 0000 [.const] __ZL35gContextRegisters_vi_TexAlphaOne_PS 0000000000189460 l 0e SECT 03 0000 [.const] __ZL35gUserElementTable_vi_TexAlphaOne_PS 0000000000189490 l 0e SECT 03 0000 [.const] __ZL30gInSemantics_vi_TexAlphaOne_PS 00000000001894a4 l 0e SECT 03 0000 [.const] __ZL34gPatchInfoOffset_vi_TexAlphaOne_PS 00000000001894b0 l 0e SECT 03 0000 [.const] __ZL32gPatchInfoCode_vi_TexAlphaOne_PS 00000000001895a0 l 0e SECT 03 0000 [.const] __ZL32gShaderCode_vi_TexAlphaOneInt_PS 00000000001895f0 l 0e SECT 03 0000 [.const] __ZL33gShRegisters_vi_TexAlphaOneInt_PS 0000000000189600 l 0e SECT 03 0000 [.const] __ZL38gContextRegisters_vi_TexAlphaOneInt_PS 0000000000189640 l 0e SECT 03 0000 [.const] __ZL38gUserElementTable_vi_TexAlphaOneInt_PS 0000000000189670 l 0e SECT 03 0000 [.const] __ZL33gInSemantics_vi_TexAlphaOneInt_PS 0000000000189684 l 0e SECT 03 0000 [.const] __ZL37gPatchInfoOffset_vi_TexAlphaOneInt_PS 0000000000189690 l 0e SECT 03 0000 [.const] __ZL35gPatchInfoCode_vi_TexAlphaOneInt_PS 0000000000189780 l 0e SECT 03 0000 [.const] __ZL40gShaderCode_vi_MsaaTexZStencilAsColor_PS 00000000001897f0 l 0e SECT 03 0000 [.const] __ZL41gShRegisters_vi_MsaaTexZStencilAsColor_PS 0000000000189800 l 0e SECT 03 0000 [.const] __ZL46gContextRegisters_vi_MsaaTexZStencilAsColor_PS 0000000000189840 l 0e SECT 03 0000 [.const] __ZL46gUserElementTable_vi_MsaaTexZStencilAsColor_PS 0000000000189860 l 0e SECT 03 0000 [.const] __ZL41gInSemantics_vi_MsaaTexZStencilAsColor_PS 0000000000189874 l 0e SECT 03 0000 [.const] __ZL45gPatchInfoOffset_vi_MsaaTexZStencilAsColor_PS 0000000000189880 l 0e SECT 03 0000 [.const] __ZL43gPatchInfoCode_vi_MsaaTexZStencilAsColor_PS 0000000000189970 l 0e SECT 03 0000 [.const] __ZL24gShaderCode_vi_TexAsZ_PS 00000000001899c0 l 0e SECT 03 0000 [.const] __ZL25gShRegisters_vi_TexAsZ_PS 00000000001899d0 l 0e SECT 03 0000 [.const] __ZL30gContextRegisters_vi_TexAsZ_PS 0000000000189a10 l 0e SECT 03 0000 [.const] __ZL30gUserElementTable_vi_TexAsZ_PS 0000000000189a40 l 0e SECT 03 0000 [.const] __ZL25gInSemantics_vi_TexAsZ_PS 0000000000189a54 l 0e SECT 03 0000 [.const] __ZL29gPatchInfoOffset_vi_TexAsZ_PS 0000000000189a60 l 0e SECT 03 0000 [.const] __ZL27gPatchInfoCode_vi_TexAsZ_PS 0000000000189b50 l 0e SECT 03 0000 [.const] __ZL31gShaderCode_vi_TexAsZStencil_PS 0000000000189bc0 l 0e SECT 03 0000 [.const] __ZL32gShRegisters_vi_TexAsZStencil_PS 0000000000189bd0 l 0e SECT 03 0000 [.const] __ZL37gContextRegisters_vi_TexAsZStencil_PS 0000000000189c10 l 0e SECT 03 0000 [.const] __ZL37gUserElementTable_vi_TexAsZStencil_PS 0000000000189c60 l 0e SECT 03 0000 [.const] __ZL32gInSemantics_vi_TexAsZStencil_PS 0000000000189c74 l 0e SECT 03 0000 [.const] __ZL36gPatchInfoOffset_vi_TexAsZStencil_PS 0000000000189c80 l 0e SECT 03 0000 [.const] __ZL34gPatchInfoCode_vi_TexAsZStencil_PS 0000000000189d70 l 0e SECT 03 0000 [.const] __ZL28gShaderCode_vi_MsaaTexAsZ_PS 0000000000189dc0 l 0e SECT 03 0000 [.const] __ZL29gShRegisters_vi_MsaaTexAsZ_PS 0000000000189dd0 l 0e SECT 03 0000 [.const] __ZL34gContextRegisters_vi_MsaaTexAsZ_PS 0000000000189e10 l 0e SECT 03 0000 [.const] __ZL34gUserElementTable_vi_MsaaTexAsZ_PS 0000000000189e40 l 0e SECT 03 0000 [.const] __ZL29gInSemantics_vi_MsaaTexAsZ_PS 0000000000189e54 l 0e SECT 03 0000 [.const] __ZL33gPatchInfoOffset_vi_MsaaTexAsZ_PS 0000000000189e60 l 0e SECT 03 0000 [.const] __ZL31gPatchInfoCode_vi_MsaaTexAsZ_PS 0000000000189f50 l 0e SECT 03 0000 [.const] __ZL35gShaderCode_vi_MsaaTexAsZStencil_PS 0000000000189fc0 l 0e SECT 03 0000 [.const] __ZL36gShRegisters_vi_MsaaTexAsZStencil_PS 0000000000189fd0 l 0e SECT 03 0000 [.const] __ZL41gContextRegisters_vi_MsaaTexAsZStencil_PS 000000000018a010 l 0e SECT 03 0000 [.const] __ZL41gUserElementTable_vi_MsaaTexAsZStencil_PS 000000000018a060 l 0e SECT 03 0000 [.const] __ZL36gInSemantics_vi_MsaaTexAsZStencil_PS 000000000018a074 l 0e SECT 03 0000 [.const] __ZL40gPatchInfoOffset_vi_MsaaTexAsZStencil_PS 000000000018a080 l 0e SECT 03 0000 [.const] __ZL38gPatchInfoCode_vi_MsaaTexAsZStencil_PS 000000000018a170 l 0e SECT 03 0000 [.const] __ZL24gShaderCode_vi_VolTex_PS 000000000018a1c0 l 0e SECT 03 0000 [.const] __ZL25gShRegisters_vi_VolTex_PS 000000000018a1d0 l 0e SECT 03 0000 [.const] __ZL30gContextRegisters_vi_VolTex_PS 000000000018a210 l 0e SECT 03 0000 [.const] __ZL30gUserElementTable_vi_VolTex_PS 000000000018a240 l 0e SECT 03 0000 [.const] __ZL25gInSemantics_vi_VolTex_PS 000000000018a254 l 0e SECT 03 0000 [.const] __ZL29gPatchInfoOffset_vi_VolTex_PS 000000000018a260 l 0e SECT 03 0000 [.const] __ZL27gPatchInfoCode_vi_VolTex_PS 000000000018a350 l 0e SECT 03 0000 [.const] __ZL24gShaderCode_vi_AAText_PS 000000000018a430 l 0e SECT 03 0000 [.const] __ZL25gShRegisters_vi_AAText_PS 000000000018a440 l 0e SECT 03 0000 [.const] __ZL30gContextRegisters_vi_AAText_PS 000000000018a480 l 0e SECT 03 0000 [.const] __ZL30gUserElementTable_vi_AAText_PS 000000000018a4d0 l 0e SECT 03 0000 [.const] __ZL25gInSemantics_vi_AAText_PS 000000000018a4e4 l 0e SECT 03 0000 [.const] __ZL29gPatchInfoOffset_vi_AAText_PS 000000000018a4f0 l 0e SECT 03 0000 [.const] __ZL27gPatchInfoCode_vi_AAText_PS 000000000018a5e0 l 0e SECT 03 0000 [.const] __ZL28gShaderCode_vi_SlowAAText_PS 000000000018a6c0 l 0e SECT 03 0000 [.const] __ZL29gShRegisters_vi_SlowAAText_PS 000000000018a6d0 l 0e SECT 03 0000 [.const] __ZL34gContextRegisters_vi_SlowAAText_PS 000000000018a710 l 0e SECT 03 0000 [.const] __ZL34gUserElementTable_vi_SlowAAText_PS 000000000018a770 l 0e SECT 03 0000 [.const] __ZL29gInSemantics_vi_SlowAAText_PS 000000000018a798 l 0e SECT 03 0000 [.const] __ZL33gPatchInfoOffset_vi_SlowAAText_PS 000000000018a7a0 l 0e SECT 03 0000 [.const] __ZL31gPatchInfoCode_vi_SlowAAText_PS 000000000018a890 l 0e SECT 03 0000 [.const] __ZL32gShaderCode_vi_ClearTypeGamma_PS 000000000018aa40 l 0e SECT 03 0000 [.const] __ZL33gShRegisters_vi_ClearTypeGamma_PS 000000000018aa50 l 0e SECT 03 0000 [.const] __ZL38gContextRegisters_vi_ClearTypeGamma_PS 000000000018aa90 l 0e SECT 03 0000 [.const] __ZL38gUserElementTable_vi_ClearTypeGamma_PS 000000000018aae0 l 0e SECT 03 0000 [.const] __ZL33gInSemantics_vi_ClearTypeGamma_PS 000000000018ab08 l 0e SECT 03 0000 [.const] __ZL37gPatchInfoOffset_vi_ClearTypeGamma_PS 000000000018ab10 l 0e SECT 03 0000 [.const] __ZL35gPatchInfoCode_vi_ClearTypeGamma_PS 000000000018ac00 l 0e SECT 03 0000 [.const] __ZL29gShaderCode_vi_TexColorKey_PS 000000000018ada0 l 0e SECT 03 0000 [.const] __ZL30gShRegisters_vi_TexColorKey_PS 000000000018adb0 l 0e SECT 03 0000 [.const] __ZL35gContextRegisters_vi_TexColorKey_PS 000000000018adf0 l 0e SECT 03 0000 [.const] __ZL35gUserElementTable_vi_TexColorKey_PS 000000000018ae50 l 0e SECT 03 0000 [.const] __ZL30gInSemantics_vi_TexColorKey_PS 000000000018ae78 l 0e SECT 03 0000 [.const] __ZL34gPatchInfoOffset_vi_TexColorKey_PS 000000000018ae80 l 0e SECT 03 0000 [.const] __ZL32gPatchInfoCode_vi_TexColorKey_PS 000000000018af70 l 0e SECT 03 0000 [.const] __ZL32gShaderCode_vi_TexSrcColorKey_PS 000000000018b060 l 0e SECT 03 0000 [.const] __ZL33gShRegisters_vi_TexSrcColorKey_PS 000000000018b070 l 0e SECT 03 0000 [.const] __ZL38gContextRegisters_vi_TexSrcColorKey_PS 000000000018b0b0 l 0e SECT 03 0000 [.const] __ZL38gUserElementTable_vi_TexSrcColorKey_PS 000000000018b100 l 0e SECT 03 0000 [.const] __ZL33gInSemantics_vi_TexSrcColorKey_PS 000000000018b114 l 0e SECT 03 0000 [.const] __ZL37gPatchInfoOffset_vi_TexSrcColorKey_PS 000000000018b120 l 0e SECT 03 0000 [.const] __ZL35gPatchInfoCode_vi_TexSrcColorKey_PS 000000000018b210 l 0e SECT 03 0000 [.const] __ZL29gShaderCode_vi_TexMulConst_PS 000000000018b280 l 0e SECT 03 0000 [.const] __ZL30gShRegisters_vi_TexMulConst_PS 000000000018b290 l 0e SECT 03 0000 [.const] __ZL35gContextRegisters_vi_TexMulConst_PS 000000000018b2d0 l 0e SECT 03 0000 [.const] __ZL35gUserElementTable_vi_TexMulConst_PS 000000000018b320 l 0e SECT 03 0000 [.const] __ZL30gInSemantics_vi_TexMulConst_PS 000000000018b334 l 0e SECT 03 0000 [.const] __ZL34gPatchInfoOffset_vi_TexMulConst_PS 000000000018b340 l 0e SECT 03 0000 [.const] __ZL32gPatchInfoCode_vi_TexMulConst_PS 000000000018b430 l 0e SECT 03 0000 [.const] __ZL27gShaderCode_vi_TexDither_PS 000000000018b4b0 l 0e SECT 03 0000 [.const] __ZL28gShRegisters_vi_TexDither_PS 000000000018b4c0 l 0e SECT 03 0000 [.const] __ZL33gContextRegisters_vi_TexDither_PS 000000000018b500 l 0e SECT 03 0000 [.const] __ZL33gUserElementTable_vi_TexDither_PS 000000000018b560 l 0e SECT 03 0000 [.const] __ZL28gInSemantics_vi_TexDither_PS 000000000018b574 l 0e SECT 03 0000 [.const] __ZL32gPatchInfoOffset_vi_TexDither_PS 000000000018b580 l 0e SECT 03 0000 [.const] __ZL30gPatchInfoCode_vi_TexDither_PS 000000000018b670 l 0e SECT 03 0000 [.const] __ZL26gShaderCode_vi_YuvToRgb_PS 000000000018b790 l 0e SECT 03 0000 [.const] __ZL27gShRegisters_vi_YuvToRgb_PS 000000000018b7a0 l 0e SECT 03 0000 [.const] __ZL32gContextRegisters_vi_YuvToRgb_PS 000000000018b7e0 l 0e SECT 03 0000 [.const] __ZL32gUserElementTable_vi_YuvToRgb_PS 000000000018b830 l 0e SECT 03 0000 [.const] __ZL27gInSemantics_vi_YuvToRgb_PS 000000000018b844 l 0e SECT 03 0000 [.const] __ZL31gPatchInfoOffset_vi_YuvToRgb_PS 000000000018b850 l 0e SECT 03 0000 [.const] __ZL29gPatchInfoCode_vi_YuvToRgb_PS 000000000018b940 l 0e SECT 03 0000 [.const] __ZL31gShaderCode_vi_YuvIntUvToRgb_PS 000000000018ba30 l 0e SECT 03 0000 [.const] __ZL32gShRegisters_vi_YuvIntUvToRgb_PS 000000000018ba40 l 0e SECT 03 0000 [.const] __ZL37gContextRegisters_vi_YuvIntUvToRgb_PS 000000000018ba80 l 0e SECT 03 0000 [.const] __ZL37gUserElementTable_vi_YuvIntUvToRgb_PS 000000000018bae0 l 0e SECT 03 0000 [.const] __ZL32gInSemantics_vi_YuvIntUvToRgb_PS 000000000018baf4 l 0e SECT 03 0000 [.const] __ZL36gPatchInfoOffset_vi_YuvIntUvToRgb_PS 000000000018bb00 l 0e SECT 03 0000 [.const] __ZL34gPatchInfoCode_vi_YuvIntUvToRgb_PS 000000000018bbf0 l 0e SECT 03 0000 [.const] __ZL32gShaderCode_vi_YuvIntUvToYuy2_PS 000000000018bcb0 l 0e SECT 03 0000 [.const] __ZL33gShRegisters_vi_YuvIntUvToYuy2_PS 000000000018bcc0 l 0e SECT 03 0000 [.const] __ZL38gContextRegisters_vi_YuvIntUvToYuy2_PS 000000000018bd00 l 0e SECT 03 0000 [.const] __ZL38gUserElementTable_vi_YuvIntUvToYuy2_PS 000000000018bd60 l 0e SECT 03 0000 [.const] __ZL33gInSemantics_vi_YuvIntUvToYuy2_PS 000000000018bd74 l 0e SECT 03 0000 [.const] __ZL37gPatchInfoOffset_vi_YuvIntUvToYuy2_PS 000000000018bd80 l 0e SECT 03 0000 [.const] __ZL35gPatchInfoCode_vi_YuvIntUvToYuy2_PS 000000000018be70 l 0e SECT 03 0000 [.const] __ZL27gShaderCode_vi_YuvToYuy2_PS 000000000018bf50 l 0e SECT 03 0000 [.const] __ZL28gShRegisters_vi_YuvToYuy2_PS 000000000018bf60 l 0e SECT 03 0000 [.const] __ZL33gContextRegisters_vi_YuvToYuy2_PS 000000000018bfa0 l 0e SECT 03 0000 [.const] __ZL33gUserElementTable_vi_YuvToYuy2_PS 000000000018bff0 l 0e SECT 03 0000 [.const] __ZL28gInSemantics_vi_YuvToYuy2_PS 000000000018c004 l 0e SECT 03 0000 [.const] __ZL32gPatchInfoOffset_vi_YuvToYuy2_PS 000000000018c010 l 0e SECT 03 0000 [.const] __ZL30gPatchInfoCode_vi_YuvToYuy2_PS 000000000018c100 l 0e SECT 03 0000 [.const] __ZL35gShaderCode_vi_MsaaFMaskResolve2_PS 000000000018c1d0 l 0e SECT 03 0000 [.const] __ZL36gShRegisters_vi_MsaaFMaskResolve2_PS 000000000018c1e0 l 0e SECT 03 0000 [.const] __ZL41gContextRegisters_vi_MsaaFMaskResolve2_PS 000000000018c220 l 0e SECT 03 0000 [.const] __ZL41gUserElementTable_vi_MsaaFMaskResolve2_PS 000000000018c250 l 0e SECT 03 0000 [.const] __ZL36gInSemantics_vi_MsaaFMaskResolve2_PS 000000000018c264 l 0e SECT 03 0000 [.const] __ZL40gPatchInfoOffset_vi_MsaaFMaskResolve2_PS 000000000018c270 l 0e SECT 03 0000 [.const] __ZL38gPatchInfoCode_vi_MsaaFMaskResolve2_PS 000000000018c360 l 0e SECT 03 0000 [.const] __ZL35gShaderCode_vi_MsaaFMaskResolve4_PS 000000000018c4b0 l 0e SECT 03 0000 [.const] __ZL36gShRegisters_vi_MsaaFMaskResolve4_PS 000000000018c4c0 l 0e SECT 03 0000 [.const] __ZL41gContextRegisters_vi_MsaaFMaskResolve4_PS 000000000018c500 l 0e SECT 03 0000 [.const] __ZL41gUserElementTable_vi_MsaaFMaskResolve4_PS 000000000018c530 l 0e SECT 03 0000 [.const] __ZL36gInSemantics_vi_MsaaFMaskResolve4_PS 000000000018c544 l 0e SECT 03 0000 [.const] __ZL40gPatchInfoOffset_vi_MsaaFMaskResolve4_PS 000000000018c550 l 0e SECT 03 0000 [.const] __ZL38gPatchInfoCode_vi_MsaaFMaskResolve4_PS 000000000018c640 l 0e SECT 03 0000 [.const] __ZL35gShaderCode_vi_MsaaFMaskResolve8_PS 000000000018c830 l 0e SECT 03 0000 [.const] __ZL36gShRegisters_vi_MsaaFMaskResolve8_PS 000000000018c840 l 0e SECT 03 0000 [.const] __ZL41gContextRegisters_vi_MsaaFMaskResolve8_PS 000000000018c880 l 0e SECT 03 0000 [.const] __ZL41gUserElementTable_vi_MsaaFMaskResolve8_PS 000000000018c8b0 l 0e SECT 03 0000 [.const] __ZL36gInSemantics_vi_MsaaFMaskResolve8_PS 000000000018c8c4 l 0e SECT 03 0000 [.const] __ZL40gPatchInfoOffset_vi_MsaaFMaskResolve8_PS 000000000018c8d0 l 0e SECT 03 0000 [.const] __ZL38gPatchInfoCode_vi_MsaaFMaskResolve8_PS 000000000018c9c0 l 0e SECT 03 0000 [.const] __ZL44gShaderCode_vi_MsaaFMaskResolve2Frag4Samp_PS 000000000018cb80 l 0e SECT 03 0000 [.const] __ZL45gShRegisters_vi_MsaaFMaskResolve2Frag4Samp_PS 000000000018cb90 l 0e SECT 03 0000 [.const] __ZL50gContextRegisters_vi_MsaaFMaskResolve2Frag4Samp_PS 000000000018cbd0 l 0e SECT 03 0000 [.const] __ZL50gUserElementTable_vi_MsaaFMaskResolve2Frag4Samp_PS 000000000018cc00 l 0e SECT 03 0000 [.const] __ZL45gInSemantics_vi_MsaaFMaskResolve2Frag4Samp_PS 000000000018cc14 l 0e SECT 03 0000 [.const] __ZL49gPatchInfoOffset_vi_MsaaFMaskResolve2Frag4Samp_PS 000000000018cc20 l 0e SECT 03 0000 [.const] __ZL47gPatchInfoCode_vi_MsaaFMaskResolve2Frag4Samp_PS 000000000018cd10 l 0e SECT 03 0000 [.const] __ZL44gShaderCode_vi_MsaaFMaskResolve2Frag8Samp_PS 000000000018d010 l 0e SECT 03 0000 [.const] __ZL45gShRegisters_vi_MsaaFMaskResolve2Frag8Samp_PS 000000000018d020 l 0e SECT 03 0000 [.const] __ZL50gContextRegisters_vi_MsaaFMaskResolve2Frag8Samp_PS 000000000018d060 l 0e SECT 03 0000 [.const] __ZL50gUserElementTable_vi_MsaaFMaskResolve2Frag8Samp_PS 000000000018d090 l 0e SECT 03 0000 [.const] __ZL45gInSemantics_vi_MsaaFMaskResolve2Frag8Samp_PS 000000000018d0a4 l 0e SECT 03 0000 [.const] __ZL49gPatchInfoOffset_vi_MsaaFMaskResolve2Frag8Samp_PS 000000000018d0b0 l 0e SECT 03 0000 [.const] __ZL47gPatchInfoCode_vi_MsaaFMaskResolve2Frag8Samp_PS 000000000018d1a0 l 0e SECT 03 0000 [.const] __ZL45gShaderCode_vi_MsaaFMaskResolve2Frag16Samp_PS 000000000018d7d0 l 0e SECT 03 0000 [.const] __ZL46gShRegisters_vi_MsaaFMaskResolve2Frag16Samp_PS 000000000018d7e0 l 0e SECT 03 0000 [.const] __ZL51gContextRegisters_vi_MsaaFMaskResolve2Frag16Samp_PS 000000000018d820 l 0e SECT 03 0000 [.const] __ZL51gUserElementTable_vi_MsaaFMaskResolve2Frag16Samp_PS 000000000018d850 l 0e SECT 03 0000 [.const] __ZL46gInSemantics_vi_MsaaFMaskResolve2Frag16Samp_PS 000000000018d864 l 0e SECT 03 0000 [.const] __ZL50gPatchInfoOffset_vi_MsaaFMaskResolve2Frag16Samp_PS 000000000018d870 l 0e SECT 03 0000 [.const] __ZL48gPatchInfoCode_vi_MsaaFMaskResolve2Frag16Samp_PS 000000000018d960 l 0e SECT 03 0000 [.const] __ZL44gShaderCode_vi_MsaaFMaskResolve4Frag8Samp_PS 000000000018dc10 l 0e SECT 03 0000 [.const] __ZL45gShRegisters_vi_MsaaFMaskResolve4Frag8Samp_PS 000000000018dc20 l 0e SECT 03 0000 [.const] __ZL50gContextRegisters_vi_MsaaFMaskResolve4Frag8Samp_PS 000000000018dc60 l 0e SECT 03 0000 [.const] __ZL50gUserElementTable_vi_MsaaFMaskResolve4Frag8Samp_PS 000000000018dc90 l 0e SECT 03 0000 [.const] __ZL45gInSemantics_vi_MsaaFMaskResolve4Frag8Samp_PS 000000000018dca4 l 0e SECT 03 0000 [.const] __ZL49gPatchInfoOffset_vi_MsaaFMaskResolve4Frag8Samp_PS 000000000018dcb0 l 0e SECT 03 0000 [.const] __ZL47gPatchInfoCode_vi_MsaaFMaskResolve4Frag8Samp_PS 000000000018dda0 l 0e SECT 03 0000 [.const] __ZL45gShaderCode_vi_MsaaFMaskResolve4Frag16Samp_PS 000000000018e340 l 0e SECT 03 0000 [.const] __ZL46gShRegisters_vi_MsaaFMaskResolve4Frag16Samp_PS 000000000018e350 l 0e SECT 03 0000 [.const] __ZL51gContextRegisters_vi_MsaaFMaskResolve4Frag16Samp_PS 000000000018e390 l 0e SECT 03 0000 [.const] __ZL51gUserElementTable_vi_MsaaFMaskResolve4Frag16Samp_PS 000000000018e3c0 l 0e SECT 03 0000 [.const] __ZL46gInSemantics_vi_MsaaFMaskResolve4Frag16Samp_PS 000000000018e3d4 l 0e SECT 03 0000 [.const] __ZL50gPatchInfoOffset_vi_MsaaFMaskResolve4Frag16Samp_PS 000000000018e3e0 l 0e SECT 03 0000 [.const] __ZL48gPatchInfoCode_vi_MsaaFMaskResolve4Frag16Samp_PS 000000000018e4d0 l 0e SECT 03 0000 [.const] __ZL45gShaderCode_vi_MsaaFMaskResolve8Frag16Samp_PS 000000000018e9a0 l 0e SECT 03 0000 [.const] __ZL46gShRegisters_vi_MsaaFMaskResolve8Frag16Samp_PS 000000000018e9b0 l 0e SECT 03 0000 [.const] __ZL51gContextRegisters_vi_MsaaFMaskResolve8Frag16Samp_PS 000000000018e9f0 l 0e SECT 03 0000 [.const] __ZL51gUserElementTable_vi_MsaaFMaskResolve8Frag16Samp_PS 000000000018ea20 l 0e SECT 03 0000 [.const] __ZL46gInSemantics_vi_MsaaFMaskResolve8Frag16Samp_PS 000000000018ea34 l 0e SECT 03 0000 [.const] __ZL50gPatchInfoOffset_vi_MsaaFMaskResolve8Frag16Samp_PS 000000000018ea40 l 0e SECT 03 0000 [.const] __ZL48gPatchInfoCode_vi_MsaaFMaskResolve8Frag16Samp_PS 000000000018eb30 l 0e SECT 03 0000 [.const] __ZL32gShaderCode_vi_ColorTransform_PS 000000000018edc0 l 0e SECT 03 0000 [.const] __ZL33gShRegisters_vi_ColorTransform_PS 000000000018edd0 l 0e SECT 03 0000 [.const] __ZL38gContextRegisters_vi_ColorTransform_PS 000000000018ee10 l 0e SECT 03 0000 [.const] __ZL38gUserElementTable_vi_ColorTransform_PS 000000000018ee60 l 0e SECT 03 0000 [.const] __ZL33gInSemantics_vi_ColorTransform_PS 000000000018ee74 l 0e SECT 03 0000 [.const] __ZL37gPatchInfoOffset_vi_ColorTransform_PS 000000000018ee80 l 0e SECT 03 0000 [.const] __ZL35gPatchInfoCode_vi_ColorTransform_PS 000000000018ef70 l 0e SECT 03 0000 [.const] __ZL39gShaderCode_vi_NonEvenLinearFilter1D_PS 000000000018f0c0 l 0e SECT 03 0000 [.const] __ZL40gShRegisters_vi_NonEvenLinearFilter1D_PS 000000000018f0d0 l 0e SECT 03 0000 [.const] __ZL45gContextRegisters_vi_NonEvenLinearFilter1D_PS 000000000018f110 l 0e SECT 03 0000 [.const] __ZL45gUserElementTable_vi_NonEvenLinearFilter1D_PS 000000000018f160 l 0e SECT 03 0000 [.const] __ZL40gInSemantics_vi_NonEvenLinearFilter1D_PS 000000000018f174 l 0e SECT 03 0000 [.const] __ZL44gPatchInfoOffset_vi_NonEvenLinearFilter1D_PS 000000000018f180 l 0e SECT 03 0000 [.const] __ZL42gPatchInfoCode_vi_NonEvenLinearFilter1D_PS 000000000018f270 l 0e SECT 03 0000 [.const] __ZL39gShaderCode_vi_NonEvenLinearFilter2D_PS 000000000018f4a0 l 0e SECT 03 0000 [.const] __ZL40gShRegisters_vi_NonEvenLinearFilter2D_PS 000000000018f4b0 l 0e SECT 03 0000 [.const] __ZL45gContextRegisters_vi_NonEvenLinearFilter2D_PS 000000000018f4f0 l 0e SECT 03 0000 [.const] __ZL45gUserElementTable_vi_NonEvenLinearFilter2D_PS 000000000018f540 l 0e SECT 03 0000 [.const] __ZL40gInSemantics_vi_NonEvenLinearFilter2D_PS 000000000018f554 l 0e SECT 03 0000 [.const] __ZL44gPatchInfoOffset_vi_NonEvenLinearFilter2D_PS 000000000018f560 l 0e SECT 03 0000 [.const] __ZL42gPatchInfoCode_vi_NonEvenLinearFilter2D_PS 000000000018f650 l 0e SECT 03 0000 [.const] __ZL39gShaderCode_vi_NonEvenLinearFilter3D_PS 000000000018f960 l 0e SECT 03 0000 [.const] __ZL40gShRegisters_vi_NonEvenLinearFilter3D_PS 000000000018f970 l 0e SECT 03 0000 [.const] __ZL45gContextRegisters_vi_NonEvenLinearFilter3D_PS 000000000018f9b0 l 0e SECT 03 0000 [.const] __ZL45gUserElementTable_vi_NonEvenLinearFilter3D_PS 000000000018fa00 l 0e SECT 03 0000 [.const] __ZL40gInSemantics_vi_NonEvenLinearFilter3D_PS 000000000018fa14 l 0e SECT 03 0000 [.const] __ZL44gPatchInfoOffset_vi_NonEvenLinearFilter3D_PS 000000000018fa20 l 0e SECT 03 0000 [.const] __ZL42gPatchInfoCode_vi_NonEvenLinearFilter3D_PS 000000000018fb10 l 0e SECT 03 0000 [.const] __ZL39gShaderCode_vi_MLAACalcSepEdgeLength_PS 000000000018ff40 l 0e SECT 03 0000 [.const] __ZL40gShRegisters_vi_MLAACalcSepEdgeLength_PS 000000000018ff50 l 0e SECT 03 0000 [.const] __ZL45gContextRegisters_vi_MLAACalcSepEdgeLength_PS 000000000018ff90 l 0e SECT 03 0000 [.const] __ZL45gUserElementTable_vi_MLAACalcSepEdgeLength_PS 000000000018ffc0 l 0e SECT 03 0000 [.const] __ZL40gInSemantics_vi_MLAACalcSepEdgeLength_PS 000000000018ffd4 l 0e SECT 03 0000 [.const] __ZL44gPatchInfoOffset_vi_MLAACalcSepEdgeLength_PS 000000000018ffe0 l 0e SECT 03 0000 [.const] __ZL42gPatchInfoCode_vi_MLAACalcSepEdgeLength_PS 00000000001901c0 l 0e SECT 03 0000 [.const] __ZL43gShaderCode_vi_MLAACalcSepEdgeLengthFast_PS 0000000000190810 l 0e SECT 03 0000 [.const] __ZL44gShRegisters_vi_MLAACalcSepEdgeLengthFast_PS 0000000000190820 l 0e SECT 03 0000 [.const] __ZL49gContextRegisters_vi_MLAACalcSepEdgeLengthFast_PS 0000000000190860 l 0e SECT 03 0000 [.const] __ZL49gUserElementTable_vi_MLAACalcSepEdgeLengthFast_PS 0000000000190890 l 0e SECT 03 0000 [.const] __ZL44gInSemantics_vi_MLAACalcSepEdgeLengthFast_PS 00000000001908a4 l 0e SECT 03 0000 [.const] __ZL48gPatchInfoOffset_vi_MLAACalcSepEdgeLengthFast_PS 00000000001908b0 l 0e SECT 03 0000 [.const] __ZL46gPatchInfoCode_vi_MLAACalcSepEdgeLengthFast_PS 00000000001909a0 l 0e SECT 03 0000 [.const] __ZL46gShaderCode_vi_MLAACalcSepEdgeLengthInitial_PS 0000000000190bb0 l 0e SECT 03 0000 [.const] __ZL47gShRegisters_vi_MLAACalcSepEdgeLengthInitial_PS 0000000000190bc0 l 0e SECT 03 0000 [.const] __ZL52gContextRegisters_vi_MLAACalcSepEdgeLengthInitial_PS 0000000000190c00 l 0e SECT 03 0000 [.const] __ZL52gUserElementTable_vi_MLAACalcSepEdgeLengthInitial_PS 0000000000190c30 l 0e SECT 03 0000 [.const] __ZL47gInSemantics_vi_MLAACalcSepEdgeLengthInitial_PS 0000000000190c44 l 0e SECT 03 0000 [.const] __ZL51gPatchInfoOffset_vi_MLAACalcSepEdgeLengthInitial_PS 0000000000190c50 l 0e SECT 03 0000 [.const] __ZL49gPatchInfoCode_vi_MLAACalcSepEdgeLengthInitial_PS 0000000000190e30 l 0e SECT 03 0000 [.const] __ZL32gShaderCode_vi_MLAAFinalBlend_PS 00000000001916b0 l 0e SECT 03 0000 [.const] __ZL33gShRegisters_vi_MLAAFinalBlend_PS 00000000001916c0 l 0e SECT 03 0000 [.const] __ZL38gContextRegisters_vi_MLAAFinalBlend_PS 0000000000191700 l 0e SECT 03 0000 [.const] __ZL38gUserElementTable_vi_MLAAFinalBlend_PS 0000000000191720 l 0e SECT 03 0000 [.const] __ZL33gInSemantics_vi_MLAAFinalBlend_PS 0000000000191734 l 0e SECT 03 0000 [.const] __ZL37gPatchInfoOffset_vi_MLAAFinalBlend_PS 0000000000191740 l 0e SECT 03 0000 [.const] __ZL35gPatchInfoCode_vi_MLAAFinalBlend_PS 0000000000191830 l 0e SECT 03 0000 [.const] __ZL36gShaderCode_vi_MLAAFinalBlendFast_PS 0000000000192140 l 0e SECT 03 0000 [.const] __ZL37gShRegisters_vi_MLAAFinalBlendFast_PS 0000000000192150 l 0e SECT 03 0000 [.const] __ZL42gContextRegisters_vi_MLAAFinalBlendFast_PS 0000000000192190 l 0e SECT 03 0000 [.const] __ZL42gUserElementTable_vi_MLAAFinalBlendFast_PS 00000000001921c0 l 0e SECT 03 0000 [.const] __ZL37gInSemantics_vi_MLAAFinalBlendFast_PS 00000000001921d4 l 0e SECT 03 0000 [.const] __ZL41gPatchInfoOffset_vi_MLAAFinalBlendFast_PS 00000000001921e0 l 0e SECT 03 0000 [.const] __ZL39gPatchInfoCode_vi_MLAAFinalBlendFast_PS 00000000001922d0 l 0e SECT 03 0000 [.const] __ZL33gShaderCode_vi_MLAAFindSepEdge_PS 00000000001923e0 l 0e SECT 03 0000 [.const] __ZL34gShRegisters_vi_MLAAFindSepEdge_PS 00000000001923f0 l 0e SECT 03 0000 [.const] __ZL39gContextRegisters_vi_MLAAFindSepEdge_PS 0000000000192430 l 0e SECT 03 0000 [.const] __ZL39gUserElementTable_vi_MLAAFindSepEdge_PS 0000000000192460 l 0e SECT 03 0000 [.const] __ZL34gInSemantics_vi_MLAAFindSepEdge_PS 0000000000192474 l 0e SECT 03 0000 [.const] __ZL38gPatchInfoOffset_vi_MLAAFindSepEdge_PS 0000000000192480 l 0e SECT 03 0000 [.const] __ZL36gPatchInfoCode_vi_MLAAFindSepEdge_PS 0000000000192570 l 0e SECT 03 0000 [.const] __ZL30gShaderCode_vi_GenZRangeTex_PS 00000000001928e0 l 0e SECT 03 0000 [.const] __ZL31gShRegisters_vi_GenZRangeTex_PS 00000000001928f0 l 0e SECT 03 0000 [.const] __ZL36gContextRegisters_vi_GenZRangeTex_PS 0000000000192930 l 0e SECT 03 0000 [.const] __ZL36gUserElementTable_vi_GenZRangeTex_PS 0000000000192980 l 0e SECT 03 0000 [.const] __ZL31gInSemantics_vi_GenZRangeTex_PS 0000000000192994 l 0e SECT 03 0000 [.const] __ZL35gPatchInfoOffset_vi_GenZRangeTex_PS 00000000001929a0 l 0e SECT 03 0000 [.const] __ZL33gPatchInfoCode_vi_GenZRangeTex_PS 0000000000192a90 l 0e SECT 03 0000 [.const] __ZL30gShaderCode_vi_GenZRangeMip_PS 0000000000192b40 l 0e SECT 03 0000 [.const] __ZL31gShRegisters_vi_GenZRangeMip_PS 0000000000192b50 l 0e SECT 03 0000 [.const] __ZL36gContextRegisters_vi_GenZRangeMip_PS 0000000000192b90 l 0e SECT 03 0000 [.const] __ZL36gUserElementTable_vi_GenZRangeMip_PS 0000000000192be0 l 0e SECT 03 0000 [.const] __ZL31gInSemantics_vi_GenZRangeMip_PS 0000000000192bf4 l 0e SECT 03 0000 [.const] __ZL35gPatchInfoOffset_vi_GenZRangeMip_PS 0000000000192c00 l 0e SECT 03 0000 [.const] __ZL33gPatchInfoCode_vi_GenZRangeMip_PS 0000000000192cf0 l 0e SECT 03 0000 [.const] __ZL33gShaderCode_vi_GenZRangeMipOdd_PS 0000000000192f00 l 0e SECT 03 0000 [.const] __ZL34gShRegisters_vi_GenZRangeMipOdd_PS 0000000000192f10 l 0e SECT 03 0000 [.const] __ZL39gContextRegisters_vi_GenZRangeMipOdd_PS 0000000000192f50 l 0e SECT 03 0000 [.const] __ZL39gUserElementTable_vi_GenZRangeMipOdd_PS 0000000000192f80 l 0e SECT 03 0000 [.const] __ZL34gInSemantics_vi_GenZRangeMipOdd_PS 0000000000192f94 l 0e SECT 03 0000 [.const] __ZL38gPatchInfoOffset_vi_GenZRangeMipOdd_PS 0000000000192fa0 l 0e SECT 03 0000 [.const] __ZL36gPatchInfoCode_vi_GenZRangeMipOdd_PS 0000000000193090 l 0e SECT 03 0000 [.const] __ZL27gShaderCode_vi_Composite_PS 0000000000193890 l 0e SECT 03 0000 [.const] __ZL28gShRegisters_vi_Composite_PS 00000000001938a0 l 0e SECT 03 0000 [.const] __ZL33gContextRegisters_vi_Composite_PS 00000000001938e0 l 0e SECT 03 0000 [.const] __ZL33gUserElementTable_vi_Composite_PS 0000000000193930 l 0e SECT 03 0000 [.const] __ZL28gInSemantics_vi_Composite_PS 0000000000193958 l 0e SECT 03 0000 [.const] __ZL32gPatchInfoOffset_vi_Composite_PS 0000000000193960 l 0e SECT 03 0000 [.const] __ZL30gPatchInfoCode_vi_Composite_PS 0000000000193a50 l 0e SECT 03 0000 [.const] __ZL29gShaderCode_vi_BufferClear_CS 0000000000193a80 l 0e SECT 03 0000 [.const] __ZL30gShRegisters_vi_BufferClear_CS 0000000000193aa8 l 0e SECT 03 0000 [.const] __ZL35gContextRegisters_vi_BufferClear_CS 0000000000193ab0 l 0e SECT 03 0000 [.const] __ZL35gUserElementTable_vi_BufferClear_CS 0000000000193ae0 l 0e SECT 03 0000 [.const] __ZL28gShaderCode_vi_BufferCopy_CS 0000000000193b00 l 0e SECT 03 0000 [.const] __ZL29gShRegisters_vi_BufferCopy_CS 0000000000193b28 l 0e SECT 03 0000 [.const] __ZL34gContextRegisters_vi_BufferCopy_CS 0000000000193b30 l 0e SECT 03 0000 [.const] __ZL34gUserElementTable_vi_BufferCopy_CS 0000000000193b60 l 0e SECT 03 0000 [.const] __ZL30gShaderCode_vi_SurfaceClear_CS 0000000000193bc0 l 0e SECT 03 0000 [.const] __ZL31gShRegisters_vi_SurfaceClear_CS 0000000000193be8 l 0e SECT 03 0000 [.const] __ZL36gContextRegisters_vi_SurfaceClear_CS 0000000000193bf0 l 0e SECT 03 0000 [.const] __ZL36gUserElementTable_vi_SurfaceClear_CS 0000000000193c20 l 0e SECT 03 0000 [.const] __ZL31gShaderCode_vi_LinGenDstCopy_CS 0000000000193cb0 l 0e SECT 03 0000 [.const] __ZL32gShRegisters_vi_LinGenDstCopy_CS 0000000000193cd8 l 0e SECT 03 0000 [.const] __ZL37gContextRegisters_vi_LinGenDstCopy_CS 0000000000193ce0 l 0e SECT 03 0000 [.const] __ZL37gUserElementTable_vi_LinGenDstCopy_CS 0000000000193d30 l 0e SECT 03 0000 [.const] __ZL31gShaderCode_vi_LinGenSrcCopy_CS 0000000000193db0 l 0e SECT 03 0000 [.const] __ZL32gShRegisters_vi_LinGenSrcCopy_CS 0000000000193dd8 l 0e SECT 03 0000 [.const] __ZL37gContextRegisters_vi_LinGenSrcCopy_CS 0000000000193de0 l 0e SECT 03 0000 [.const] __ZL37gUserElementTable_vi_LinGenSrcCopy_CS 0000000000193e30 l 0e SECT 03 0000 [.const] __ZL34gShaderCode_vi_LinGenSrcDstCopy_CS 0000000000193eb0 l 0e SECT 03 0000 [.const] __ZL35gShRegisters_vi_LinGenSrcDstCopy_CS 0000000000193ed8 l 0e SECT 03 0000 [.const] __ZL40gContextRegisters_vi_LinGenSrcDstCopy_CS 0000000000193ee0 l 0e SECT 03 0000 [.const] __ZL40gUserElementTable_vi_LinGenSrcDstCopy_CS 0000000000193f30 l 0e SECT 03 0000 [.const] __ZL27gShaderCode_vi_HtileCopy_CS 0000000000193f60 l 0e SECT 03 0000 [.const] __ZL28gShRegisters_vi_HtileCopy_CS 0000000000193f88 l 0e SECT 03 0000 [.const] __ZL33gContextRegisters_vi_HtileCopy_CS 0000000000193f90 l 0e SECT 03 0000 [.const] __ZL33gUserElementTable_vi_HtileCopy_CS 0000000000193fc0 l 0e SECT 03 0000 [.const] __ZL38gShaderCode_vi_MsaaFMaskExpand2Samp_CS 0000000000194060 l 0e SECT 03 0000 [.const] __ZL39gShRegisters_vi_MsaaFMaskExpand2Samp_CS 0000000000194088 l 0e SECT 03 0000 [.const] __ZL44gContextRegisters_vi_MsaaFMaskExpand2Samp_CS 0000000000194090 l 0e SECT 03 0000 [.const] __ZL44gUserElementTable_vi_MsaaFMaskExpand2Samp_CS 00000000001940b0 l 0e SECT 03 0000 [.const] __ZL38gShaderCode_vi_MsaaFMaskExpand4Samp_CS 00000000001941c0 l 0e SECT 03 0000 [.const] __ZL39gShRegisters_vi_MsaaFMaskExpand4Samp_CS 00000000001941e8 l 0e SECT 03 0000 [.const] __ZL44gContextRegisters_vi_MsaaFMaskExpand4Samp_CS 00000000001941f0 l 0e SECT 03 0000 [.const] __ZL44gUserElementTable_vi_MsaaFMaskExpand4Samp_CS 0000000000194210 l 0e SECT 03 0000 [.const] __ZL38gShaderCode_vi_MsaaFMaskExpand8Samp_CS 00000000001943e0 l 0e SECT 03 0000 [.const] __ZL39gShRegisters_vi_MsaaFMaskExpand8Samp_CS 0000000000194408 l 0e SECT 03 0000 [.const] __ZL44gContextRegisters_vi_MsaaFMaskExpand8Samp_CS 0000000000194410 l 0e SECT 03 0000 [.const] __ZL44gUserElementTable_vi_MsaaFMaskExpand8Samp_CS 0000000000194430 l 0e SECT 03 0000 [.const] __ZL32gShaderCode_vi_FastDepthClear_CS 0000000000194490 l 0e SECT 03 0000 [.const] __ZL33gShRegisters_vi_FastDepthClear_CS 00000000001944b8 l 0e SECT 03 0000 [.const] __ZL38gContextRegisters_vi_FastDepthClear_CS 00000000001944c0 l 0e SECT 03 0000 [.const] __ZL38gUserElementTable_vi_FastDepthClear_CS 00000000001944f0 l 0e SECT 03 0000 [.const] __ZL35gShaderCode_vi_FastDepthExpClear_CS 0000000000194580 l 0e SECT 03 0000 [.const] __ZL36gShRegisters_vi_FastDepthExpClear_CS 00000000001945a8 l 0e SECT 03 0000 [.const] __ZL41gContextRegisters_vi_FastDepthExpClear_CS 00000000001945b0 l 0e SECT 03 0000 [.const] __ZL41gUserElementTable_vi_FastDepthExpClear_CS 00000000001945e0 l 0e SECT 03 0000 [.const] __ZL37gShaderCode_vi_LinGenDstRepackCopy_CS 00000000001946e0 l 0e SECT 03 0000 [.const] __ZL38gShRegisters_vi_LinGenDstRepackCopy_CS 0000000000194708 l 0e SECT 03 0000 [.const] __ZL43gContextRegisters_vi_LinGenDstRepackCopy_CS 0000000000194710 l 0e SECT 03 0000 [.const] __ZL43gUserElementTable_vi_LinGenDstRepackCopy_CS 0000000000194760 l 0e SECT 03 0000 [.const] __ZL31gShaderCode_vi_VolumeTexCopy_CS 0000000000194800 l 0e SECT 03 0000 [.const] __ZL32gShRegisters_vi_VolumeTexCopy_CS 0000000000194828 l 0e SECT 03 0000 [.const] __ZL37gContextRegisters_vi_VolumeTexCopy_CS 0000000000194830 l 0e SECT 03 0000 [.const] __ZL37gUserElementTable_vi_VolumeTexCopy_CS 0000000000194880 l 0e SECT 03 0000 [.const] __ZL29gShaderCode_vi_GenerateHiS_PS 0000000000194930 l 0e SECT 03 0000 [.const] __ZL30gShRegisters_vi_GenerateHiS_PS 0000000000194940 l 0e SECT 03 0000 [.const] __ZL35gContextRegisters_vi_GenerateHiS_PS 0000000000194980 l 0e SECT 03 0000 [.const] __ZL35gUserElementTable_vi_GenerateHiS_PS 00000000001949d0 l 0e SECT 03 0000 [.const] __ZL30gInSemantics_vi_GenerateHiS_PS 00000000001949e4 l 0e SECT 03 0000 [.const] __ZL34gPatchInfoOffset_vi_GenerateHiS_PS 00000000001949f0 l 0e SECT 03 0000 [.const] __ZL32gPatchInfoCode_vi_GenerateHiS_PS 0000000000194ae0 l 0e SECT 03 0000 [.const] __ZL27gShaderCode_vi_AdvAARes1_PS 0000000000194b60 l 0e SECT 03 0000 [.const] __ZL28gShRegisters_vi_AdvAARes1_PS 0000000000194b70 l 0e SECT 03 0000 [.const] __ZL33gContextRegisters_vi_AdvAARes1_PS 0000000000194bb0 l 0e SECT 03 0000 [.const] __ZL33gUserElementTable_vi_AdvAARes1_PS 0000000000194be0 l 0e SECT 03 0000 [.const] __ZL28gInSemantics_vi_AdvAARes1_PS 0000000000194bf4 l 0e SECT 03 0000 [.const] __ZL32gPatchInfoOffset_vi_AdvAARes1_PS 0000000000194c00 l 0e SECT 03 0000 [.const] __ZL30gPatchInfoCode_vi_AdvAARes1_PS 0000000000194de0 l 0e SECT 03 0000 [.const] __ZL36gShaderCode_vi_AdvAAEdgeMask4Samp_PS 0000000000194ff0 l 0e SECT 03 0000 [.const] __ZL37gShRegisters_vi_AdvAAEdgeMask4Samp_PS 0000000000195000 l 0e SECT 03 0000 [.const] __ZL42gContextRegisters_vi_AdvAAEdgeMask4Samp_PS 0000000000195040 l 0e SECT 03 0000 [.const] __ZL42gUserElementTable_vi_AdvAAEdgeMask4Samp_PS 0000000000195070 l 0e SECT 03 0000 [.const] __ZL37gInSemantics_vi_AdvAAEdgeMask4Samp_PS 0000000000195084 l 0e SECT 03 0000 [.const] __ZL41gPatchInfoOffset_vi_AdvAAEdgeMask4Samp_PS 0000000000195090 l 0e SECT 03 0000 [.const] __ZL39gPatchInfoCode_vi_AdvAAEdgeMask4Samp_PS 0000000000195360 l 0e SECT 03 0000 [.const] __ZL36gShaderCode_vi_AdvAAEdgeMask8Samp_PS 00000000001956b0 l 0e SECT 03 0000 [.const] __ZL37gShRegisters_vi_AdvAAEdgeMask8Samp_PS 00000000001956c0 l 0e SECT 03 0000 [.const] __ZL42gContextRegisters_vi_AdvAAEdgeMask8Samp_PS 0000000000195700 l 0e SECT 03 0000 [.const] __ZL42gUserElementTable_vi_AdvAAEdgeMask8Samp_PS 0000000000195730 l 0e SECT 03 0000 [.const] __ZL37gInSemantics_vi_AdvAAEdgeMask8Samp_PS 0000000000195744 l 0e SECT 03 0000 [.const] __ZL41gPatchInfoOffset_vi_AdvAAEdgeMask8Samp_PS 0000000000195750 l 0e SECT 03 0000 [.const] __ZL39gPatchInfoCode_vi_AdvAAEdgeMask8Samp_PS 0000000000195a20 l 0e SECT 03 0000 [.const] __ZL37gShaderCode_vi_AdvAAFilterMaskFast_PS 0000000000195c70 l 0e SECT 03 0000 [.const] __ZL38gShRegisters_vi_AdvAAFilterMaskFast_PS 0000000000195c80 l 0e SECT 03 0000 [.const] __ZL43gContextRegisters_vi_AdvAAFilterMaskFast_PS 0000000000195cc0 l 0e SECT 03 0000 [.const] __ZL43gUserElementTable_vi_AdvAAFilterMaskFast_PS 0000000000195ce0 l 0e SECT 03 0000 [.const] __ZL38gInSemantics_vi_AdvAAFilterMaskFast_PS 0000000000195cf4 l 0e SECT 03 0000 [.const] __ZL42gPatchInfoOffset_vi_AdvAAFilterMaskFast_PS 0000000000195d00 l 0e SECT 03 0000 [.const] __ZL40gPatchInfoCode_vi_AdvAAFilterMaskFast_PS 0000000000195df0 l 0e SECT 03 0000 [.const] __ZL37gShaderCode_vi_AdvAAGrad4SampNoReZ_PS 00000000001976f0 l 0e SECT 03 0000 [.const] __ZL38gShRegisters_vi_AdvAAGrad4SampNoReZ_PS 0000000000197700 l 0e SECT 03 0000 [.const] __ZL43gContextRegisters_vi_AdvAAGrad4SampNoReZ_PS 0000000000197740 l 0e SECT 03 0000 [.const] __ZL43gUserElementTable_vi_AdvAAGrad4SampNoReZ_PS 0000000000197770 l 0e SECT 03 0000 [.const] __ZL38gInSemantics_vi_AdvAAGrad4SampNoReZ_PS 0000000000197784 l 0e SECT 03 0000 [.const] __ZL42gPatchInfoOffset_vi_AdvAAGrad4SampNoReZ_PS 0000000000197790 l 0e SECT 03 0000 [.const] __ZL40gPatchInfoCode_vi_AdvAAGrad4SampNoReZ_PS 0000000000197880 l 0e SECT 03 0000 [.const] __ZL37gShaderCode_vi_AdvAAGrad8SampNoReZ_PS 000000000019af50 l 0e SECT 03 0000 [.const] __ZL38gShRegisters_vi_AdvAAGrad8SampNoReZ_PS 000000000019af60 l 0e SECT 03 0000 [.const] __ZL43gContextRegisters_vi_AdvAAGrad8SampNoReZ_PS 000000000019afa0 l 0e SECT 03 0000 [.const] __ZL43gUserElementTable_vi_AdvAAGrad8SampNoReZ_PS 000000000019afd0 l 0e SECT 03 0000 [.const] __ZL38gInSemantics_vi_AdvAAGrad8SampNoReZ_PS 000000000019afe4 l 0e SECT 03 0000 [.const] __ZL42gPatchInfoOffset_vi_AdvAAGrad8SampNoReZ_PS 000000000019aff0 l 0e SECT 03 0000 [.const] __ZL40gPatchInfoCode_vi_AdvAAGrad8SampNoReZ_PS 000000000019b0e0 l 0e SECT 03 0000 [.const] __ZL36gShaderCode_vi_AdvAAEdG4SampNoReZ_PS 000000000019d160 l 0e SECT 03 0000 [.const] __ZL37gShRegisters_vi_AdvAAEdG4SampNoReZ_PS 000000000019d170 l 0e SECT 03 0000 [.const] __ZL42gContextRegisters_vi_AdvAAEdG4SampNoReZ_PS 000000000019d1b0 l 0e SECT 03 0000 [.const] __ZL42gUserElementTable_vi_AdvAAEdG4SampNoReZ_PS 000000000019d1e0 l 0e SECT 03 0000 [.const] __ZL37gInSemantics_vi_AdvAAEdG4SampNoReZ_PS 000000000019d1f4 l 0e SECT 03 0000 [.const] __ZL41gPatchInfoOffset_vi_AdvAAEdG4SampNoReZ_PS 000000000019d200 l 0e SECT 03 0000 [.const] __ZL39gPatchInfoCode_vi_AdvAAEdG4SampNoReZ_PS 000000000019d2f0 l 0e SECT 03 0000 [.const] __ZL36gShaderCode_vi_AdvAAEdG8SampNoReZ_PS 00000000001a12e0 l 0e SECT 03 0000 [.const] __ZL37gShRegisters_vi_AdvAAEdG8SampNoReZ_PS 00000000001a12f0 l 0e SECT 03 0000 [.const] __ZL42gContextRegisters_vi_AdvAAEdG8SampNoReZ_PS 00000000001a1330 l 0e SECT 03 0000 [.const] __ZL42gUserElementTable_vi_AdvAAEdG8SampNoReZ_PS 00000000001a1360 l 0e SECT 03 0000 [.const] __ZL37gInSemantics_vi_AdvAAEdG8SampNoReZ_PS 00000000001a1374 l 0e SECT 03 0000 [.const] __ZL41gPatchInfoOffset_vi_AdvAAEdG8SampNoReZ_PS 00000000001a1380 l 0e SECT 03 0000 [.const] __ZL39gPatchInfoCode_vi_AdvAAEdG8SampNoReZ_PS 00000000001a1470 l 0e SECT 03 0000 [.const] __ZL41gShaderCode_vi_AdvAAFMaskEdgeMask4Samp_PS 00000000001a1720 l 0e SECT 03 0000 [.const] __ZL42gShRegisters_vi_AdvAAFMaskEdgeMask4Samp_PS 00000000001a1730 l 0e SECT 03 0000 [.const] __ZL47gContextRegisters_vi_AdvAAFMaskEdgeMask4Samp_PS 00000000001a1770 l 0e SECT 03 0000 [.const] __ZL47gUserElementTable_vi_AdvAAFMaskEdgeMask4Samp_PS 00000000001a17a0 l 0e SECT 03 0000 [.const] __ZL42gInSemantics_vi_AdvAAFMaskEdgeMask4Samp_PS 00000000001a17b4 l 0e SECT 03 0000 [.const] __ZL46gPatchInfoOffset_vi_AdvAAFMaskEdgeMask4Samp_PS 00000000001a17c0 l 0e SECT 03 0000 [.const] __ZL44gPatchInfoCode_vi_AdvAAFMaskEdgeMask4Samp_PS 00000000001a1a90 l 0e SECT 03 0000 [.const] __ZL41gShaderCode_vi_AdvAAFMaskEdgeMask8Samp_PS 00000000001a1f70 l 0e SECT 03 0000 [.const] __ZL42gShRegisters_vi_AdvAAFMaskEdgeMask8Samp_PS 00000000001a1f80 l 0e SECT 03 0000 [.const] __ZL47gContextRegisters_vi_AdvAAFMaskEdgeMask8Samp_PS 00000000001a1fc0 l 0e SECT 03 0000 [.const] __ZL47gUserElementTable_vi_AdvAAFMaskEdgeMask8Samp_PS 00000000001a1ff0 l 0e SECT 03 0000 [.const] __ZL42gInSemantics_vi_AdvAAFMaskEdgeMask8Samp_PS 00000000001a2004 l 0e SECT 03 0000 [.const] __ZL46gPatchInfoOffset_vi_AdvAAFMaskEdgeMask8Samp_PS 00000000001a2010 l 0e SECT 03 0000 [.const] __ZL44gPatchInfoCode_vi_AdvAAFMaskEdgeMask8Samp_PS 00000000001a22e0 l 0e SECT 03 0000 [.const] __ZL41gShaderCode_vi_AdvAAFMaskEdG4SampNoReZ_PS 00000000001a4510 l 0e SECT 03 0000 [.const] __ZL42gShRegisters_vi_AdvAAFMaskEdG4SampNoReZ_PS 00000000001a4520 l 0e SECT 03 0000 [.const] __ZL47gContextRegisters_vi_AdvAAFMaskEdG4SampNoReZ_PS 00000000001a4560 l 0e SECT 03 0000 [.const] __ZL47gUserElementTable_vi_AdvAAFMaskEdG4SampNoReZ_PS 00000000001a4590 l 0e SECT 03 0000 [.const] __ZL42gInSemantics_vi_AdvAAFMaskEdG4SampNoReZ_PS 00000000001a45a4 l 0e SECT 03 0000 [.const] __ZL46gPatchInfoOffset_vi_AdvAAFMaskEdG4SampNoReZ_PS 00000000001a45b0 l 0e SECT 03 0000 [.const] __ZL44gPatchInfoCode_vi_AdvAAFMaskEdG4SampNoReZ_PS 00000000001a46a0 l 0e SECT 03 0000 [.const] __ZL41gShaderCode_vi_AdvAAFMaskEdG8SampNoReZ_PS 00000000001a8910 l 0e SECT 03 0000 [.const] __ZL42gShRegisters_vi_AdvAAFMaskEdG8SampNoReZ_PS 00000000001a8920 l 0e SECT 03 0000 [.const] __ZL47gContextRegisters_vi_AdvAAFMaskEdG8SampNoReZ_PS 00000000001a8960 l 0e SECT 03 0000 [.const] __ZL47gUserElementTable_vi_AdvAAFMaskEdG8SampNoReZ_PS 00000000001a8990 l 0e SECT 03 0000 [.const] __ZL42gInSemantics_vi_AdvAAFMaskEdG8SampNoReZ_PS 00000000001a89a4 l 0e SECT 03 0000 [.const] __ZL46gPatchInfoOffset_vi_AdvAAFMaskEdG8SampNoReZ_PS 00000000001a89b0 l 0e SECT 03 0000 [.const] __ZL44gPatchInfoCode_vi_AdvAAFMaskEdG8SampNoReZ_PS 00000000001a90f0 l 0e SECT 03 0000 [.const] __ZZNK11R800AddrLib16HwlSetupTileInfoE13_AddrTileMode19_ADDR_SURFACE_FLAGSjjjjP14_ADDR_TILEINFOS3_13_AddrTileTypeP33_ADDR_COMPUTE_SURFACE_INFO_OUTPUTE11tileInfoDef 00000000001a9110 l 0e SECT 03 0000 [.const] __ZZNK11R800AddrLib16HwlSetupTileInfoE13_AddrTileMode19_ADDR_SURFACE_FLAGSjjjjP14_ADDR_TILEINFOS3_13_AddrTileTypeP33_ADDR_COMPUTE_SURFACE_INFO_OUTPUTE19sCompressZTileSplit 00000000001a9190 l 0e SECT 03 0000 [.const] __ZZNK14EgBasedAddrLib21HwlComputeBaseSwizzleEPK32_ADDR_COMPUTE_BASE_SWIZZLE_INPUTP33_ADDR_COMPUTE_BASE_SWIZZLE_OUTPUTE17bankRotationArray 00000000001a9230 l 0e SECT 03 0000 [.const] _BONAIRE_CRTC_OFFSETS 00000000001a9250 l 0e SECT 03 0000 [.const] _BONAIRE_CRTC_STATUS_FRAME_COUNT 00000000001a96e0 l 0e SECT 03 0000 [.const] _ulTrinityEyefinityNotsupportedDidTbl 00000000001a9718 l 0e SECT 03 0000 [.const] _EmbeddedBoardGroup 00000000001acd90 l 0e SECT 03 0000 [.const] _LB_TYPE 00000000001ace40 l 0e SECT 03 0000 [.const] _P2P_BAR_2 00000000001acea0 l 0e SECT 03 0000 [.const] _P2P_BAR_4 00000000001ad000 l 0e SECT 03 0000 [.const] _WCB_NUM 00000000001ad060 l 0e SECT 03 0000 [.const] _MAIL_BOX_FOR_CLIENT 00000000001ad0d0 l 0e SECT 03 0000 [.const] _CAIL_Encoded_PCIELanes 00000000001ad0f0 l 0e SECT 03 0000 [.const] _ulEngineIndexTbl 00000000001ad150 l 0e SECT 03 0000 [.const] _ulNoOfChannel 00000000001ad180 l 0e SECT 03 0000 [.const] _PowerControlOppositeActionTbl 00000000001ad1b0 l 0e SECT 03 0000 [.const] _CARRIZO_DCP_OFFSETS 00000000001ad210 l 0e SECT 03 0000 [.const] _MC_XPB_CLG_CFGn_CAYMAN 00000000001ad2d0 l 0e SECT 03 0000 [.const] _DCIO_OFFSETS 00000000001ad2f0 l 0e SECT 03 0000 [.const] _CRTC_STATUS_FRAME_COUNT 00000000001ad310 l 0e SECT 03 0000 [.const] _CaymanBankMap 00000000001ad320 l 0e SECT 03 0000 [.const] _DCP_OFFSETS 00000000001ad360 l 0e SECT 03 0000 [.const] _CypressSpiPerfCounter 00000000001ad3a0 l 0e SECT 03 0000 [.const] _MC_XPB_CLG_CFGn_CYPRESS 00000000001ad460 l 0e SECT 03 0000 [.const] _DCP_OFFSETS 00000000001ad480 l 0e SECT 03 0000 [.const] _CypressBankMap 00000000001ad490 l 0e SECT 03 0000 [.const] _SECT_CTRLCONST_def_1 00000000001ad498 l 0e SECT 03 0000 [.const] _SECT_CLEAR_def_1 00000000001ad4b0 l 0e SECT 03 0000 [.const] _SECT_CONTEXT_def_1 00000000001adc50 l 0e SECT 03 0000 [.const] _SECT_CONTEXT_def_2 00000000001adc70 l 0e SECT 03 0000 [.const] _SECT_CONTEXT_def_3 00000000001add50 l 0e SECT 03 0000 [.const] _SECT_CONTEXT_def_4 00000000001adee0 l 0e SECT 03 0000 [.const] _SECT_CONTEXT_def_5 00000000001adf00 l 0e SECT 03 0000 [.const] _SECT_CONTEXT_def_6 00000000001adfe0 l 0e SECT 03 0000 [.const] _SECT_CONTEXT_def_7 00000000001ae490 l 0e SECT 03 0000 [.const] _SECT_CTRLCONST_def_1 00000000001ae498 l 0e SECT 03 0000 [.const] _SECT_CLEAR_def_1 00000000001ae4b0 l 0e SECT 03 0000 [.const] _SECT_CONTEXT_def_1 00000000001aec50 l 0e SECT 03 0000 [.const] _SECT_CONTEXT_def_2 00000000001aec70 l 0e SECT 03 0000 [.const] _SECT_CONTEXT_def_3 00000000001aed50 l 0e SECT 03 0000 [.const] _SECT_CONTEXT_def_4 00000000001aeee0 l 0e SECT 03 0000 [.const] _SECT_CONTEXT_def_5 00000000001aef00 l 0e SECT 03 0000 [.const] _SECT_CONTEXT_def_6 00000000001aefe0 l 0e SECT 03 0000 [.const] _SECT_CONTEXT_def_7 00000000001af4c0 l 0e SECT 03 0000 [.const] _DCP_OFFSETS 00000000001af4e0 l 0e SECT 03 0000 [.const] _CRTC_STATUS_FRAME_COUNT 00000000001af500 l 0e SECT 03 0000 [.const] _TONGA_RLC_SRM_INDEX_CNTL_DATA_OFFSETS 00000000001af520 l 0e SECT 03 0000 [.const] _TONGA_DCP_OFFSETS 00000000001af560 l 0e SECT 03 0000 [.const] _TONGA_CRTC_OFFSETS 00000000001af580 l 0e SECT 03 0000 [.const] _TONGA_CRTC_STATUS_FRAME_COUNT 00000000001af5c0 l 0e SECT 03 0000 [.const] _si_SECT_CONTEXT_def_1 00000000001af910 l 0e SECT 03 0000 [.const] _si_SECT_CONTEXT_def_2 00000000001afd50 l 0e SECT 03 0000 [.const] _si_SECT_CONTEXT_def_3 00000000001afd70 l 0e SECT 03 0000 [.const] _si_SECT_CONTEXT_def_4 00000000001affe4 l 0e SECT 03 0000 [.const] _si_SECT_CONTEXT_def_5 00000000001affe8 l 0e SECT 03 0000 [.const] _si_SECT_CONTEXT_def_6 00000000001afff0 l 0e SECT 03 0000 [.const] _si_SECT_CONTEXT_def_7 00000000001b03a0 l 0e SECT 03 0000 [.const] _ci_SECT_CONTEXT_def_1 00000000001b06f0 l 0e SECT 03 0000 [.const] _ci_SECT_CONTEXT_def_2 00000000001b0b40 l 0e SECT 03 0000 [.const] _ci_SECT_CONTEXT_def_3 00000000001b0b60 l 0e SECT 03 0000 [.const] _ci_SECT_CONTEXT_def_4 00000000001b0dd4 l 0e SECT 03 0000 [.const] _ci_SECT_CONTEXT_def_5 00000000001b0ddc l 0e SECT 03 0000 [.const] _ci_SECT_CONTEXT_def_6 00000000001b0de0 l 0e SECT 03 0000 [.const] _ci_SECT_CONTEXT_def_7 00000000001b1190 l 0e SECT 03 0000 [.const] _vi_SECT_CONTEXT_def_1 00000000001b14e0 l 0e SECT 03 0000 [.const] _vi_SECT_CONTEXT_def_2 00000000001b1930 l 0e SECT 03 0000 [.const] _vi_SECT_CONTEXT_def_3 00000000001b1950 l 0e SECT 03 0000 [.const] _vi_SECT_CONTEXT_def_4 00000000001b1bc4 l 0e SECT 03 0000 [.const] _vi_SECT_CONTEXT_def_5 00000000001b1bcc l 0e SECT 03 0000 [.const] _vi_SECT_CONTEXT_def_6 00000000001b1bd0 l 0e SECT 03 0000 [.const] _vi_SECT_CONTEXT_def_7 00000000001b1f80 l 0e SECT 03 0000 [.const] __ZL9va_data_6 00000000001e7b90 l 0e SECT 03 0000 [.const] __ZL14stSPUKernel_SI 0000000000227bd0 l 0e SECT 03 0000 [.const] __ZL16fair_play_si_app 000000000022a220 l 0e SECT 03 0000 [.const] __ZL11hdcp_si_app 000000000022c770 l 0e SECT 03 0000 [.const] __ZL14aucSI_Firmware 0000000000239760 l 0e SECT 03 0000 [.const] __ZL11va_data_cik 00000000002724c0 l 0e SECT 03 0000 [.const] __ZL14stSPUKernel_CI 00000000002b2500 l 0e SECT 03 0000 [.const] __ZL11kapp_ci_app 00000000002ba210 l 0e SECT 03 0000 [.const] __ZL16fair_play_ci_app 00000000002bd840 l 0e SECT 03 0000 [.const] __ZL11hdcp_ci_app 00000000002c0e70 l 0e SECT 03 0000 [.const] __ZL14aucCI_Firmware 00000000002d65b0 l 0e SECT 03 0000 [.const] __ZL10va_data_vi 0000000000321308 l 0e SECT 03 0000 [.const] __ZL14stSPUKernel_VI 0000000000361340 l 0e SECT 03 0000 [.const] __ZL14aucVI_Firmware 0000000000387fd0 l 0e SECT 04 0000 [__TEXT.__ustring] _bmask 0000000000389980 l 0e SECT 08 0000 [.const_data] __ZL14gATYModelNames 0000000000389d00 l 0e SECT 08 0000 [.const_data] __ZTV24IOAccelCommandDescriptor 000000000038a7b0 l 0e SECT 08 0000 [.const_data] __ZZN29AMDRadeonX4000_AMDAccelDevice11deviceStartEvE11methodDescs 000000000038b200 l 0e SECT 08 0000 [.const_data] __ZTV24IOAccelCommandDescriptor 000000000038c700 l 0e SECT 08 0000 [.const_data] __ZZN39AMDRadeonX4000_AMDAccelSharedUserClient26getTargetAndMethodForIndexEPP9IOServicejE11methodDescs 000000000038f250 l 0e SECT 08 0000 [.const_data] __ZZN35AMDRadeonX4000_AMDAccelVideoContext12contextStartEvE11methodDescs 000000000039a060 l 0e SECT 08 0000 [.const_data] __ZZN14AMDSIGLContext26getTargetAndMethodForIndexEPP9IOServicejE11methodDescs 000000000039a0c0 l 0e SECT 08 0000 [.const_data] __ZTV24IOAccelCommandDescriptor 000000000039ad60 l 0e SECT 08 0000 [.const_data] __ZZN14AMDSICLContext12contextStartEvE11methodDescs 000000000039e190 l 0e SECT 08 0000 [.const_data] __ZZN14AMDCICLContext12contextStartEvE11methodDescs 00000000003bddc0 l 0e SECT 08 0000 [.const_data] __ZTV9BltDevice 00000000003be450 l 0e SECT 08 0000 [.const_data] __ZTV18SiBltComputeShader 00000000003be4a0 l 0e SECT 08 0000 [.const_data] __ZTV17SiBltVertexShader 00000000003bee90 l 0e SECT 08 0000 [.const_data] _CailControlInfo1 00000000003bf240 l 0e SECT 08 0000 [.const_data] _CailDisableFlag1 00000000003bf3a0 l 0e SECT 08 0000 [.const_data] _CailDisableFlag2 00000000003bf410 l 0e SECT 08 0000 [.const_data] _CailEnableFlag1 00000000003bf510 l 0e SECT 08 0000 [.const_data] _CailDisableClockGatingFlags 00000000003bf6b0 l 0e SECT 08 0000 [.const_data] _CailDisablePowerGatingFlags 00000000003bf7c0 l 0e SECT 08 0000 [.const_data] _CailCapOverride 00000000003bfb40 l 0e SECT 08 0000 [.const_data] _AcfMemberTbl 00000000003bfd50 l 0e SECT 08 0000 [.const_data] _CAIL_IRI_Services 00000000003bfeb0 l 0e SECT 08 0000 [.const_data] _SECT_CONTEXT_defs 00000000003bff30 l 0e SECT 08 0000 [.const_data] _SECT_CLEAR_defs 00000000003bff50 l 0e SECT 08 0000 [.const_data] _SECT_CTRLCONST_defs 00000000003bff70 l 0e SECT 08 0000 [.const_data] _SECT_CONTEXT_defs 00000000003bfff0 l 0e SECT 08 0000 [.const_data] _SECT_CLEAR_defs 00000000003c0010 l 0e SECT 08 0000 [.const_data] _SECT_CTRLCONST_defs 00000000003c0030 l 0e SECT 08 0000 [.const_data] _si_SECT_CONTEXT_defs 00000000003c00b0 l 0e SECT 08 0000 [.const_data] _si_cs_data 00000000003c00d0 l 0e SECT 08 0000 [.const_data] _ci_SECT_CONTEXT_defs 00000000003c0150 l 0e SECT 08 0000 [.const_data] _ci_cs_data 00000000003c0170 l 0e SECT 08 0000 [.const_data] _vi_SECT_CONTEXT_defs 00000000003c01f0 l 0e SECT 08 0000 [.const_data] _vi_cs_data 00000000003c41d8 l 0e SECT 08 0000 [.const_data] __ZL22stVCEFW_SouthernIsland 00000000003c5f20 l 0e SECT 09 0000 [.data] __ZL22AMDHWChannelStatsNames 00000000003c7510 l 0e SECT 09 0000 [.data] __ZL29gShaderCode_si_TexAlphaOne_PS 00000000003c7560 l 0e SECT 09 0000 [.data] __ZL30gShRegisters_si_TexAlphaOne_PS 00000000003c7570 l 0e SECT 09 0000 [.data] __ZL35gContextRegisters_si_TexAlphaOne_PS 00000000003c75b0 l 0e SECT 09 0000 [.data] __ZL35gUserElementTable_si_TexAlphaOne_PS 00000000003c75e0 l 0e SECT 09 0000 [.data] __ZL30gInSemantics_si_TexAlphaOne_PS 00000000003c75f4 l 0e SECT 09 0000 [.data] __ZL34gPatchInfoOffset_si_TexAlphaOne_PS 00000000003c7600 l 0e SECT 09 0000 [.data] __ZL32gPatchInfoCode_si_TexAlphaOne_PS 00000000003c76a0 l 0e SECT 09 0000 [.data] __ZL32gShaderCode_si_TexAlphaOneInt_PS 00000000003c76f0 l 0e SECT 09 0000 [.data] __ZL33gShRegisters_si_TexAlphaOneInt_PS 00000000003c7700 l 0e SECT 09 0000 [.data] __ZL38gContextRegisters_si_TexAlphaOneInt_PS 00000000003c7740 l 0e SECT 09 0000 [.data] __ZL38gUserElementTable_si_TexAlphaOneInt_PS 00000000003c7770 l 0e SECT 09 0000 [.data] __ZL33gInSemantics_si_TexAlphaOneInt_PS 00000000003c7784 l 0e SECT 09 0000 [.data] __ZL37gPatchInfoOffset_si_TexAlphaOneInt_PS 00000000003c7790 l 0e SECT 09 0000 [.data] __ZL35gPatchInfoCode_si_TexAlphaOneInt_PS 00000000003c7830 l 0e SECT 09 0000 [.data] __ZL29gShaderCode_vi_TexAlphaOne_PS 00000000003c7880 l 0e SECT 09 0000 [.data] _aRLC_Ucode 00000000003c84a0 l 0e SECT 09 0000 [.data] _aBARTS_GoldenRegisterSettings_A11 00000000003c86f0 l 0e SECT 09 0000 [.data] _BARTS_HwConstants 00000000003c8760 l 0e SECT 09 0000 [.data] _aRLC_Ucode 00000000003ca790 l 0e SECT 09 0000 [.data] _aF32_SDMA0_Ucode 00000000003cb820 l 0e SECT 09 0000 [.data] _aF32_SDMA1_Ucode 00000000003cc8b0 l 0e SECT 09 0000 [.data] _aF32_PFP_Ucode 00000000003cea60 l 0e SECT 09 0000 [.data] _aF32_CE_Ucode 00000000003d0c10 l 0e SECT 09 0000 [.data] _aF32_ME_Ucode 00000000003d2dc0 l 0e SECT 09 0000 [.data] _aF32_MEC_Ucode 00000000003d7070 l 0e SECT 09 0000 [.data] _BonaireAsicStateCheckRegList 00000000003d7630 l 0e SECT 09 0000 [.data] _aBONAIRE_GoldenRegisterSettings_A0 00000000003d8160 l 0e SECT 09 0000 [.data] _aBONAIRE_GoldenRegisterSettings_A1 00000000003d8cc0 l 0e SECT 09 0000 [.data] _Bonaire_UcodeInfo 00000000003d8d00 l 0e SECT 09 0000 [.data] _sRlcScratchRamInfo 00000000003d8d20 l 0e SECT 09 0000 [.data] _Bonaire_HwConstants 00000000003d8dd0 l 0e SECT 09 0000 [.data] _sBonaireGbMacroTileModeRecords 00000000003d8e10 l 0e SECT 09 0000 [.data] _sBonaireGbTileModeRecords 00000000003d8f10 l 0e SECT 09 0000 [.data] _BonaireAsicSetupTable 00000000003d9040 l 0e SECT 09 0000 [.data] _aRLC_Ucode 00000000003d9c60 l 0e SECT 09 0000 [.data] _aCAICOS_GoldenRegisterSettings_A11 00000000003d9ec8 l 0e SECT 09 0000 [.data] _CAICOS_HwConstants 00000000003e2370 l 0e SECT 09 0000 [.data] _SumoId1 00000000003e2380 l 0e SECT 09 0000 [.data] _SumoBtcGroup1 00000000003e23a0 l 0e SECT 09 0000 [.data] _SumoId2 00000000003e23ac l 0e SECT 09 0000 [.data] _SumoBtcGroup2 00000000003e23b8 l 0e SECT 09 0000 [.data] _SumoId3 00000000003e23d0 l 0e SECT 09 0000 [.data] _SumoEgBtcGroup1 00000000003e2408 l 0e SECT 09 0000 [.data] _SumoId4 00000000003e2420 l 0e SECT 09 0000 [.data] _SumoEgBtcGroup2 00000000003e2440 l 0e SECT 09 0000 [.data] _TrinityId1 00000000003e2490 l 0e SECT 09 0000 [.data] _TrinityBtcGroup1 00000000003e24d0 l 0e SECT 09 0000 [.data] _TrinityId2 00000000003e2510 l 0e SECT 09 0000 [.data] _TrinityBtcGroup2 00000000003e2574 l 0e SECT 09 0000 [.data] _TrinityId3 00000000003e2580 l 0e SECT 09 0000 [.data] _TrinityBtcGroup3 00000000003e2590 l 0e SECT 09 0000 [.data] _TrinityId4 00000000003e25bc l 0e SECT 09 0000 [.data] _TrinityCaicosGroup 00000000003e25d0 l 0e SECT 09 0000 [.data] _TrinitySolarSystemGroup 00000000003e2630 l 0e SECT 09 0000 [.data] _TrinitySIGroup 00000000003e2650 l 0e SECT 09 0000 [.data] _KaveriMobileId1 00000000003e2660 l 0e SECT 09 0000 [.data] _KaveriMobileGroup1 00000000003e2680 l 0e SECT 09 0000 [.data] _KaveriMobileId2 00000000003e2690 l 0e SECT 09 0000 [.data] _KaveriMobileGroup2 00000000003e26b0 l 0e SECT 09 0000 [.data] _KaveriMobileId3 00000000003e26c0 l 0e SECT 09 0000 [.data] _KaveriMobileGroup3 00000000003e26d8 l 0e SECT 09 0000 [.data] _KaveriMobileId4 00000000003e26e0 l 0e SECT 09 0000 [.data] _KaveriMobileGroup4 00000000003e26f0 l 0e SECT 09 0000 [.data] _KaveriAIOId1 00000000003e2700 l 0e SECT 09 0000 [.data] _KaveriAIOGroup1 00000000003e2718 l 0e SECT 09 0000 [.data] _KaveriAIOId2 00000000003e2730 l 0e SECT 09 0000 [.data] _KaveriAIOGroup2 00000000003e2750 l 0e SECT 09 0000 [.data] _KaveriEmbeddedId 00000000003e2758 l 0e SECT 09 0000 [.data] _KaveriEmbeddedGroup 00000000003e2760 l 0e SECT 09 0000 [.data] _KaveriDesktopId 00000000003e2770 l 0e SECT 09 0000 [.data] _KaveriDesktopGroup 00000000003e2790 l 0e SECT 09 0000 [.data] _easfBinaryTable 00000000003e2ed0 l 0e SECT 09 0000 [.data] _CapeVerdeRLCSaveRestoreRegisterList 00000000003e3290 l 0e SECT 09 0000 [.data] _CAPEVERDE_GoldenRegisterSettingsA11 00000000003e3fc0 l 0e SECT 09 0000 [.data] _CAPEVERDE_GoldenRegisterSettingsA12 00000000003e4cf0 l 0e SECT 09 0000 [.data] _CapeVerde_HwConstants 00000000003e4d70 l 0e SECT 09 0000 [.data] _aRLC_Ucode 00000000003e6d70 l 0e SECT 09 0000 [.data] _CapeVerde_RLC 00000000003e6d90 l 0e SECT 09 0000 [.data] _sCapeVerdeGbTileModeRecords 00000000003e6e90 l 0e SECT 09 0000 [.data] _CarrizoAsicSetupTable 00000000003e6fa0 l 0e SECT 09 0000 [.data] _aCarrizo_GoldenRegisterSettings 00000000003e7148 l 0e SECT 09 0000 [.data] _Carrizo_UcodeInfo 00000000003e71a0 l 0e SECT 09 0000 [.data] _Carrizo_RLC_UCODE 00000000003e71c8 l 0e SECT 09 0000 [.data] _Carrizo_SDMA0_UCODE 00000000003e71f0 l 0e SECT 09 0000 [.data] _Carrizo_SDMA1_UCODE 00000000003e7218 l 0e SECT 09 0000 [.data] _Carrizo_CE_UCODE 00000000003e7240 l 0e SECT 09 0000 [.data] _Carrizo_PFP_UCODE 00000000003e7268 l 0e SECT 09 0000 [.data] _Carrizo_ME_UCODE 00000000003e7290 l 0e SECT 09 0000 [.data] _Carrizo_MEC1_UCODE 00000000003e72b8 l 0e SECT 09 0000 [.data] _Carrizo_MEC2_UCODE 00000000003e72e0 l 0e SECT 09 0000 [.data] _aF32_MEC_Ucode 0000000000427460 l 0e SECT 09 0000 [.data] _aF32_ME_Ucode 000000000042b5e0 l 0e SECT 09 0000 [.data] _aF32_PFP_Ucode 000000000042f760 l 0e SECT 09 0000 [.data] _aF32_CE_Ucode 00000000004318e0 l 0e SECT 09 0000 [.data] _aF32_SDMA1_Ucode 0000000000434160 l 0e SECT 09 0000 [.data] _aF32_SDMA0_Ucode 00000000004369e0 l 0e SECT 09 0000 [.data] _aRLC_Ucode 00000000004399e0 l 0e SECT 09 0000 [.data] _sRlcScratchRamInfo 0000000000439a48 l 0e SECT 09 0000 [.data] _CzCsTaskList 0000000000439a58 l 0e SECT 09 0000 [.data] _Carrizo_HwConstants_8812 0000000000439b10 l 0e SECT 09 0000 [.data] _CzCsTaskArray 0000000000439b60 l 0e SECT 09 0000 [.data] _SysClockGatingTaskTable 0000000000439d30 l 0e SECT 09 0000 [.data] _SdmaRingRegSaveRestore 0000000000439e10 l 0e SECT 09 0000 [.data] _ReinitGnbNonGfxReg 0000000000439f10 l 0e SECT 09 0000 [.data] _HaltSDMA 0000000000439f50 l 0e SECT 09 0000 [.data] _StartSDMA 0000000000439fa0 l 0e SECT 09 0000 [.data] _register_restore 000000000043b5f0 l 0e SECT 09 0000 [.data] _register_list_format 000000000043b690 l 0e SECT 09 0000 [.data] _register_restore_separate 000000000043b700 l 0e SECT 09 0000 [.data] _register_list_format_separate 000000000043b730 l 0e SECT 09 0000 [.data] _sCarrizoGbMacroTileModeRecords 000000000043b7b0 l 0e SECT 09 0000 [.data] _sCarrizoGbTileModeRecords 000000000043b8c0 l 0e SECT 09 0000 [.data] _CaymanAsicSetupTable 000000000043b980 l 0e SECT 09 0000 [.data] _MEMORY_CLIENT_GROUP_CAYMAN 000000000043ba40 l 0e SECT 09 0000 [.data] _MAIL_BOX_CAYMAN 000000000043bb00 l 0e SECT 09 0000 [.data] _WCB_NUM_CAYMAN 000000000043bbc0 l 0e SECT 09 0000 [.data] _P2P_BAR_2_CAYMAN 000000000043bc80 l 0e SECT 09 0000 [.data] _P2P_BAR_4_CAYMAN 000000000043bf70 l 0e SECT 09 0000 [.data] _CF_MEM_CLT_GUP_RANGE_CAYMAN 000000000043c090 l 0e SECT 09 0000 [.data] _aRLC_Ucode 000000000043d0b0 l 0e SECT 09 0000 [.data] _CaymanAsicStateCheckRegList 000000000043d5b0 l 0e SECT 09 0000 [.data] _aCAYMAN_GoldenRegisterSettings_A11 000000000043d838 l 0e SECT 09 0000 [.data] _CAYMAN_HwConstants 000000000043d8a0 l 0e SECT 09 0000 [.data] _aCEDAR_GoldenRegisterSettings 000000000043dd98 l 0e SECT 09 0000 [.data] _CEDAR_HwConstants 000000000043de20 l 0e SECT 09 0000 [.data] _CypressAsicSetupTable 000000000043deb0 l 0e SECT 09 0000 [.data] _MEMORY_CLIENT_GROUP_CYPRESS 000000000043df70 l 0e SECT 09 0000 [.data] _MAIL_BOX_CYPRESS 000000000043e030 l 0e SECT 09 0000 [.data] _WCB_NUM_CYPRESS 000000000043e0f0 l 0e SECT 09 0000 [.data] _P2P_BAR_2_CYPRESS 000000000043e1b0 l 0e SECT 09 0000 [.data] _P2P_BAR_4_CYPRESS 000000000043e4a0 l 0e SECT 09 0000 [.data] _CF_MEM_CLT_GUP_RANGE_CYPRESS 000000000043e5c0 l 0e SECT 09 0000 [.data] _aRLC_Ucode 000000000043f1e0 l 0e SECT 09 0000 [.data] _CypressAsicStateCheckRegList 000000000043f5f0 l 0e SECT 09 0000 [.data] _aCYPRESS_GoldenRegisterSettings_A11 000000000043ffc0 l 0e SECT 09 0000 [.data] _aCYPRESS_GoldenRegisterSettings_A12 0000000000441330 l 0e SECT 09 0000 [.data] _CYPRESS_HwConstants 00000000004413e0 l 0e SECT 09 0000 [.data] _DevastatorRLCSaveRestoreRegisterList 0000000000441850 l 0e SECT 09 0000 [.data] _aDevastator_GoldenRegisterSettings 0000000000441b30 l 0e SECT 09 0000 [.data] _aScrapper_GoldenRegisterSettings 0000000000442058 l 0e SECT 09 0000 [.data] _Devastator_RLC 0000000000442070 l 0e SECT 09 0000 [.data] _Devastator_HwConstants 00000000004420e0 l 0e SECT 09 0000 [.data] _aRLC_Ucode 0000000000443fd0 l 0e SECT 09 0000 [.data] _aGodavari_GoldenRegisterSettings 0000000000444558 l 0e SECT 09 0000 [.data] _Godavari_UcodeInfo 0000000000444598 l 0e SECT 09 0000 [.data] _sRlcScratchRamInfo 00000000004445b8 l 0e SECT 09 0000 [.data] _Godavari_HwConstants_2411 0000000000444670 l 0e SECT 09 0000 [.data] _GodavariRLCSaveRestoreRegisterList 0000000000444b78 l 0e SECT 09 0000 [.data] _Godavari_RLC_UCODE 0000000000444ba0 l 0e SECT 09 0000 [.data] _aRLC_Ucode 00000000004473e0 l 0e SECT 09 0000 [.data] _HAINAN_GoldenRegisterSettingsA0 00000000004478e8 l 0e SECT 09 0000 [.data] _Hainan_HwConstants 0000000000447970 l 0e SECT 09 0000 [.data] _aRLC_Ucode 0000000000449970 l 0e SECT 09 0000 [.data] _Hainan_RLC 00000000004499f0 l 0e SECT 09 0000 [.data] _aHAWAII_GoldenRegisterSettings 000000000044ae80 l 0e SECT 09 0000 [.data] _Hawaii_UcodeInfo 000000000044aec0 l 0e SECT 09 0000 [.data] _sRlcScratchRamInfo 000000000044aee0 l 0e SECT 09 0000 [.data] _Hawaii_HwConstants 000000000044af90 l 0e SECT 09 0000 [.data] _Hawaii_RLC_UCODE 000000000044afb8 l 0e SECT 09 0000 [.data] _Hawaii_SDMA0_UCODE 000000000044afe0 l 0e SECT 09 0000 [.data] _Hawaii_SDMA1_UCODE 000000000044b008 l 0e SECT 09 0000 [.data] _Hawaii_CE_UCODE 000000000044b030 l 0e SECT 09 0000 [.data] _Hawaii_PFP_UCODE 000000000044b058 l 0e SECT 09 0000 [.data] _Hawaii_ME_UCODE 000000000044b080 l 0e SECT 09 0000 [.data] _Hawaii_MEC1_UCODE 000000000044b0b0 l 0e SECT 09 0000 [.data] _aF32_MEC_Ucode 000000000044f230 l 0e SECT 09 0000 [.data] _aF32_ME_Ucode 00000000004513b0 l 0e SECT 09 0000 [.data] _aF32_PFP_Ucode 0000000000453530 l 0e SECT 09 0000 [.data] _aF32_CE_Ucode 00000000004556b0 l 0e SECT 09 0000 [.data] _aF32_SDMA1_Ucode 0000000000456720 l 0e SECT 09 0000 [.data] _aF32_SDMA0_Ucode 0000000000457790 l 0e SECT 09 0000 [.data] _aRLC_Ucode 0000000000459790 l 0e SECT 09 0000 [.data] _sHawaiiGbMacroTileModeRecords 00000000004597d0 l 0e SECT 09 0000 [.data] _sHawaiiGbTileModeRecords 00000000004598d0 l 0e SECT 09 0000 [.data] _IcelandAsicSetupTable 0000000000459af0 l 0e SECT 09 0000 [.data] _IcelandAsicStateCheckRegList 0000000000459ff0 l 0e SECT 09 0000 [.data] _aICELAND_GoldenRegisterSettings_A0 000000000045a4b8 l 0e SECT 09 0000 [.data] _Iceland_UcodeInfo 000000000045a510 l 0e SECT 09 0000 [.data] _Iceland_RLC_UCODE 000000000045a538 l 0e SECT 09 0000 [.data] _Iceland_SDMA0_UCODE 000000000045a560 l 0e SECT 09 0000 [.data] _Iceland_SDMA1_UCODE 000000000045a588 l 0e SECT 09 0000 [.data] _Iceland_CE_UCODE 000000000045a5b0 l 0e SECT 09 0000 [.data] _Iceland_PFP_UCODE 000000000045a5d8 l 0e SECT 09 0000 [.data] _Iceland_ME_UCODE 000000000045a600 l 0e SECT 09 0000 [.data] _Iceland_MEC1_UCODE 000000000045a628 l 0e SECT 09 0000 [.data] _Iceland_MEC2_UCODE 000000000045a650 l 0e SECT 09 0000 [.data] _aF32_MEC_Ucode 000000000049a7d0 l 0e SECT 09 0000 [.data] _aF32_ME_Ucode 000000000049e950 l 0e SECT 09 0000 [.data] _aF32_PFP_Ucode 00000000004a2ad0 l 0e SECT 09 0000 [.data] _aF32_CE_Ucode 00000000004a4c50 l 0e SECT 09 0000 [.data] _aF32_SDMA0_Ucode 00000000004a6cd0 l 0e SECT 09 0000 [.data] _aRLC_Ucode 00000000004a8cd0 l 0e SECT 09 0000 [.data] _Iceland_HwConstants 00000000004a8d90 l 0e SECT 09 0000 [.data] _sIcelandGbMacroTileModeRecords 00000000004a8e10 l 0e SECT 09 0000 [.data] _sIcelandGbTileModeRecords 00000000004a8f00 l 0e SECT 09 0000 [.data] _aRLC_Ucode 00000000004a9b20 l 0e SECT 09 0000 [.data] _aJUNIPER_GoldenRegisterSettings_A11 00000000004aa260 l 0e SECT 09 0000 [.data] _aJUNIPER_GoldenRegisterSettings_A12 00000000004aa9b8 l 0e SECT 09 0000 [.data] _JUNIPER_HwConstants 00000000004aaa20 l 0e SECT 09 0000 [.data] _aF32_SDMA0_Ucode 00000000004abab0 l 0e SECT 09 0000 [.data] _aF32_SDMA1_Ucode 00000000004acb40 l 0e SECT 09 0000 [.data] _aF32_PFP_Ucode 00000000004aecf0 l 0e SECT 09 0000 [.data] _aF32_CE_Ucode 00000000004b0ea0 l 0e SECT 09 0000 [.data] _aF32_ME_Ucode 00000000004b3050 l 0e SECT 09 0000 [.data] _aF32_MEC_Ucode 00000000004b7960 l 0e SECT 09 0000 [.data] _aKalindi_GoldenRegisterSettings 00000000004b7ef8 l 0e SECT 09 0000 [.data] _Kalindi_UcodeInfo 00000000004b7f38 l 0e SECT 09 0000 [.data] _sRlcScratchRamInfo 00000000004b7f58 l 0e SECT 09 0000 [.data] _Kalindi_HwConstants_4882 00000000004b8010 l 0e SECT 09 0000 [.data] _KalindiRLCSaveRestoreRegisterList 00000000004b8518 l 0e SECT 09 0000 [.data] _Kalindi_RLC_UCODE 00000000004b8540 l 0e SECT 09 0000 [.data] _aRLC_Ucode 00000000004bad90 l 0e SECT 09 0000 [.data] _OLAND_GoldenRegisterSettingsA0 00000000004bb2e0 l 0e SECT 09 0000 [.data] _Oland_HwConstants 00000000004bb360 l 0e SECT 09 0000 [.data] _aRLC_Ucode 00000000004bd360 l 0e SECT 09 0000 [.data] _Oland_RLC 00000000004bd380 l 0e SECT 09 0000 [.data] _sOlandGbTileModeRecords 00000000004bd4c0 l 0e SECT 09 0000 [.data] _aPITCAIRN_GoldenRegisterSettingsA11 00000000004bdaf0 l 0e SECT 09 0000 [.data] _aPITCAIRN_GoldenRegisterSettingsA12 00000000004be1e8 l 0e SECT 09 0000 [.data] _Pitcairn_HwConstants 00000000004be270 l 0e SECT 09 0000 [.data] _aRLC_Ucode 00000000004c0270 l 0e SECT 09 0000 [.data] _Pitcairn_RLC 00000000004c0290 l 0e SECT 09 0000 [.data] _SiNi_EngineDependencyTbl 00000000004c0380 l 0e SECT 09 0000 [.data] _aRLC_Ucode 00000000004c0fa0 l 0e SECT 09 0000 [.data] _aREDWOOD_GoldenRegisterSettings 00000000004c1598 l 0e SECT 09 0000 [.data] _REDWOOD_HwConstants 00000000004c1660 l 0e SECT 09 0000 [.data] _aSpectre_GoldenRegisterSettings 00000000004c1ec8 l 0e SECT 09 0000 [.data] _Spectre_UcodeInfo 00000000004c1f08 l 0e SECT 09 0000 [.data] _sRlcScratchRamInfo 00000000004c1f28 l 0e SECT 09 0000 [.data] _Spectre_HwConstants_8812 00000000004c1fe0 l 0e SECT 09 0000 [.data] _SpectreRLCSaveRestoreRegisterList 00000000004c26d0 l 0e SECT 09 0000 [.data] _Spectre_RLC_UCODE 00000000004c26f8 l 0e SECT 09 0000 [.data] _Spectre_SDMA0_UCODE 00000000004c2720 l 0e SECT 09 0000 [.data] _Spectre_SDMA1_UCODE 00000000004c2748 l 0e SECT 09 0000 [.data] _Spectre_CE_UCODE 00000000004c2770 l 0e SECT 09 0000 [.data] _Spectre_PFP_UCODE 00000000004c2798 l 0e SECT 09 0000 [.data] _Spectre_ME_UCODE 00000000004c27c0 l 0e SECT 09 0000 [.data] _Spectre_MEC1_UCODE 00000000004c27e8 l 0e SECT 09 0000 [.data] _Spectre_MEC2_UCODE 00000000004c2810 l 0e SECT 09 0000 [.data] _aF32_MEC_Ucode 00000000004c6990 l 0e SECT 09 0000 [.data] _aF32_ME_Ucode 00000000004c8b10 l 0e SECT 09 0000 [.data] _aF32_PFP_Ucode 00000000004cac90 l 0e SECT 09 0000 [.data] _aF32_CE_Ucode 00000000004cce10 l 0e SECT 09 0000 [.data] _aF32_SDMA1_Ucode 00000000004cde80 l 0e SECT 09 0000 [.data] _aF32_SDMA0_Ucode 00000000004ceef0 l 0e SECT 09 0000 [.data] _aRLC_Ucode 00000000004d16f0 l 0e SECT 09 0000 [.data] _sSpectreGbMacroTileModeRecords 00000000004d1730 l 0e SECT 09 0000 [.data] _sSpectreGbTileModeRecords 00000000004d1870 l 0e SECT 09 0000 [.data] _SumoRLCSaveRestoreRegisterList 00000000004d19c0 l 0e SECT 09 0000 [.data] _aRLC_Ucode 00000000004d2630 l 0e SECT 09 0000 [.data] _aSuperSUMO_GoldenRegisterSettings 00000000004d29e0 l 0e SECT 09 0000 [.data] _aSUMO_GoldenRegisterSettings 00000000004d2db0 l 0e SECT 09 0000 [.data] _aWrestler_GoldenRegisterSettings 00000000004d3038 l 0e SECT 09 0000 [.data] _Wrestler_HwConstants 00000000004d30a0 l 0e SECT 09 0000 [.data] _SumoAsicStateCheckRegListWithUVD 00000000004d3218 l 0e SECT 09 0000 [.data] _SumoAsicStateRegInfo 00000000004d3228 l 0e SECT 09 0000 [.data] _StrippedSumo_HwConstants 00000000004d3290 l 0e SECT 09 0000 [.data] _Sumo_HwConstants 00000000004d32f8 l 0e SECT 09 0000 [.data] _SuperSumo3Simd_HwConstants 00000000004d3360 l 0e SECT 09 0000 [.data] _SuperSumo4Simd_HwConstants 00000000004d33c8 l 0e SECT 09 0000 [.data] _SuperSumo_HwConstants 00000000004d3c30 l 0e SECT 09 0000 [.data] _TahitiAsicSetupTable 00000000004d3d50 l 0e SECT 09 0000 [.data] _TahitiAsicStateCheckRegList 00000000004d4400 l 0e SECT 09 0000 [.data] _aTAHITI_GoldenRegisterSettingsA11 00000000004d4bf0 l 0e SECT 09 0000 [.data] _aTAHITI_GoldenRegisterSettingsA21 00000000004d5488 l 0e SECT 09 0000 [.data] _Tahiti_HwConstants 00000000004d5510 l 0e SECT 09 0000 [.data] _aRLC_Ucode 00000000004d7510 l 0e SECT 09 0000 [.data] _Tahiti_RLC 00000000004d7530 l 0e SECT 09 0000 [.data] _sTahitiGbTileModeRecords 00000000004d7630 l 0e SECT 09 0000 [.data] _TongaAsicSetupTable 00000000004d7860 l 0e SECT 09 0000 [.data] _TongaAsicStateCheckRegList 00000000004d7de0 l 0e SECT 09 0000 [.data] _aTONGA_GoldenRegisterSettings_A1 00000000004d83f0 l 0e SECT 09 0000 [.data] _Tonga_UcodeInfo 00000000004d8450 l 0e SECT 09 0000 [.data] _aTONGA_GoldenRegisterSettings_A0 00000000004d8a60 l 0e SECT 09 0000 [.data] _Tonga_UcodeInfo_A0 00000000004d8ab8 l 0e SECT 09 0000 [.data] _Tonga_RLC_UCODE_A0 00000000004d8ae0 l 0e SECT 09 0000 [.data] _Tonga_SDMA0_UCODE 00000000004d8b08 l 0e SECT 09 0000 [.data] _Tonga_SDMA1_UCODE 00000000004d8b30 l 0e SECT 09 0000 [.data] _Tonga_CE_UCODE 00000000004d8b58 l 0e SECT 09 0000 [.data] _Tonga_PFP_UCODE 00000000004d8b80 l 0e SECT 09 0000 [.data] _Tonga_ME_UCODE 00000000004d8ba8 l 0e SECT 09 0000 [.data] _Tonga_MEC1_UCODE 00000000004d8bd0 l 0e SECT 09 0000 [.data] _Tonga_MEC2_UCODE 00000000004d8c00 l 0e SECT 09 0000 [.data] _aF32_MEC_Ucode 0000000000518d80 l 0e SECT 09 0000 [.data] _aF32_ME_Ucode 000000000051cf00 l 0e SECT 09 0000 [.data] _aF32_PFP_Ucode 0000000000521080 l 0e SECT 09 0000 [.data] _aF32_CE_Ucode 0000000000523200 l 0e SECT 09 0000 [.data] _aF32_SDMA0_Ucode 0000000000525a80 l 0e SECT 09 0000 [.data] _aRLC_Ucode_A0 0000000000527a80 l 0e SECT 09 0000 [.data] _Tonga_RLC_UCODE 0000000000527ab0 l 0e SECT 09 0000 [.data] _aRLC_Ucode 0000000000529ab0 l 0e SECT 09 0000 [.data] _sRlcScratchRamInfo 0000000000529b18 l 0e SECT 09 0000 [.data] _Tonga_HwConstants 0000000000529bd0 l 0e SECT 09 0000 [.data] _register_restore 000000000052b2f0 l 0e SECT 09 0000 [.data] _register_list_format 000000000052b390 l 0e SECT 09 0000 [.data] _register_restore_separate 000000000052b468 l 0e SECT 09 0000 [.data] _register_list_format_separate 000000000052b480 l 0e SECT 09 0000 [.data] _sTongaGbMacroTileModeRecords 000000000052b500 l 0e SECT 09 0000 [.data] _sTongaGbTileModeRecords 000000000052b600 l 0e SECT 09 0000 [.data] _aRLC_Ucode 000000000052c220 l 0e SECT 09 0000 [.data] _aTURKS_GoldenRegisterSettings_A11 000000000052c488 l 0e SECT 09 0000 [.data] _TURKS_HwConstants 000000000052ec88 g 1e SECT 0a 0000 [__DATA.__common] __realmain 000000000052ec90 g 1e SECT 0a 0000 [__DATA.__common] __antimain 000000000052f320 l 0e SECT 0b 0000 [.bss] __ZL24bindingDoesWriteBitfield 000000000052f340 l 0e SECT 0b 0000 [.bss] __ZL28gl_assert_wait_timeout_event 000000000052f344 l 0e SECT 0b 0000 [.bss] __ZL28gl_assert_wait_timeout_event 000000000052f348 l 0e SECT 0b 0000 [.bss] __ZL28gl_assert_wait_timeout_event 000000000052f34c l 0e SECT 0b 0000 [.bss] __ZL28gl_assert_wait_timeout_event 000000000052f350 l 0e SECT 0b 0000 [.bss] __ZL28gl_assert_wait_timeout_event 000000000052f354 l 0e SECT 0b 0000 [.bss] __ZL28gl_assert_wait_timeout_event 000000000052f358 l 0e SECT 0b 0000 [.bss] __ZL28gl_assert_wait_timeout_event 000000000052f35c l 0e SECT 0b 0000 [.bss] __ZL28gl_assert_wait_timeout_event 000000000052f360 l 0e SECT 0b 0000 [.bss] __ZL28gl_assert_wait_timeout_event 000000000052f368 l 0e SECT 0b 0000 [.bss] _sRlcScratchRamInfo 0000000000146250 g 0f SECT 03 0000 [.const] _AMDRadeonAccelerator_VERS_NUM 0000000000146150 g 0f SECT 03 0000 [.const] _AMDRadeonAccelerator_VERS_STRING 00000000003e2360 g 0f SECT 09 0000 [.data] _APUNotSupportDualGraphicsBranding 00000000000dab3f g 0f SECT 01 0000 [.text] _ATI_Read_AGP 00000000000dab91 g 0f SECT 01 0000 [.text] _ATI_Write_AGP 00000000000dabfb g 0f SECT 01 0000 [.text] _ATI_Write_AGP_BusCntl 00000000000dbfbf g 0f SECT 01 0000 [.text] _ATOM_CheckExtPwrConnect 00000000000dc0d7 g 0f SECT 01 0000 [.text] _ATOM_CheckForFireGLBoard 00000000000dc1ba g 0f SECT 01 0000 [.text] _ATOM_CheckInternalSSInfo 00000000000dc38b g 0f SECT 01 0000 [.text] _ATOM_CheckSdiSupport 00000000000db2ea g 0f SECT 01 0000 [.text] _ATOM_CheckVBIOSInfo 00000000000db4f1 g 0f SECT 01 0000 [.text] _ATOM_CheckVBIOSTableRevision 00000000000db582 g 0f SECT 01 0000 [.text] _ATOM_Check_BIOSReserveFB_BLOCK 00000000000db80a g 0f SECT 01 0000 [.text] _ATOM_Check_BIOSSupportInfo 00000000000db6a1 g 0f SECT 01 0000 [.text] _ATOM_ExecuteBIOSTable 00000000000dc280 g 0f SECT 01 0000 [.text] _ATOM_GetPLLDividers 00000000000db536 g 0f SECT 01 0000 [.text] _ATOM_GetTablePointer 00000000000dc02b g 0f SECT 01 0000 [.text] _ATOM_InitFanCntl 00000000000db080 g 0f SECT 01 0000 [.text] _ATOM_InitParser 00000000000dbe72 g 0f SECT 01 0000 [.text] _ATOM_NoBiosInitializeAdapter 00000000000db309 g 0f SECT 01 0000 [.text] _ATOM_PostVBIOS 00000000000db5cf g 0f SECT 01 0000 [.text] _ATOM_QueryBIOSReserveFB 00000000000db7b0 g 0f SECT 01 0000 [.text] _ATOM_QueryTableRevision 00000000000f9e4c g 0f SECT 01 0000 [.text] _AddAlignment 00000000000f9f70 g 0f SECT 01 0000 [.text] _AddPowerOf2Alignment 00000000000cd25a g 0f SECT 01 0000 [.text] _AddrCombineBankPipeSwizzle 00000000000cd2c0 g 0f SECT 01 0000 [.text] _AddrComputeBaseSwizzle 00000000000cd0a4 g 0f SECT 01 0000 [.text] _AddrComputeCmaskAddrFromCoord 00000000000cd0d7 g 0f SECT 01 0000 [.text] _AddrComputeCmaskCoordFromAddr 00000000000cd071 g 0f SECT 01 0000 [.text] _AddrComputeCmaskInfo 00000000000cd1a3 g 0f SECT 01 0000 [.text] _AddrComputeDccInfo 00000000000cd13d g 0f SECT 01 0000 [.text] _AddrComputeFmaskAddrFromCoord 00000000000cd170 g 0f SECT 01 0000 [.text] _AddrComputeFmaskCoordFromAddr 00000000000cd10a g 0f SECT 01 0000 [.text] _AddrComputeFmaskInfo 00000000000cd00b g 0f SECT 01 0000 [.text] _AddrComputeHtileAddrFromCoord 00000000000cd03e g 0f SECT 01 0000 [.text] _AddrComputeHtileCoordFromAddr 00000000000ccfd8 g 0f SECT 01 0000 [.text] _AddrComputeHtileInfo 00000000000cd452 g 0f SECT 01 0000 [.text] _AddrComputePrtInfo 00000000000cd28d g 0f SECT 01 0000 [.text] _AddrComputeSliceSwizzle 00000000000ccf72 g 0f SECT 01 0000 [.text] _AddrComputeSurfaceAddrFromCoord 00000000000ccfa5 g 0f SECT 01 0000 [.text] _AddrComputeSurfaceCoordFromAddr 00000000000ccf3f g 0f SECT 01 0000 [.text] _AddrComputeSurfaceInfo 00000000000cd3b9 g 0f SECT 01 0000 [.text] _AddrConvertTileIndex 00000000000cd3ec g 0f SECT 01 0000 [.text] _AddrConvertTileIndex1 00000000000cd386 g 0f SECT 01 0000 [.text] _AddrConvertTileInfoToHW 00000000000ccf07 g 0f SECT 01 0000 [.text] _AddrCreate 00000000000ccf11 g 0f SECT 01 0000 [.text] _AddrDestroy 00000000000cd227 g 0f SECT 01 0000 [.text] _AddrExtractBankPipeSwizzle 00000000000cd41f g 0f SECT 01 0000 [.text] _AddrGetTileIndex 00000000000cd1d6 g 0f SECT 01 0000 [.text] _AddrGetVersion 00000000000cd20a g 0f SECT 01 0000 [.text] _AddrUseCombinedSwizzle 00000000000cd1ed g 0f SECT 01 0000 [.text] _AddrUseTileIndex 00000000000f80d3 g 0f SECT 01 0000 [.text] _AdjustRequestedMcAddressRangeInfo 000000000052c700 g 0f SECT 09 0000 [.data] _AlignmentMask 0000000000121293 g 0f SECT 01 0000 [.text] _AllocateMemory 00000000003e1980 g 0f SECT 09 0000 [.data] _AsicNameTable 00000000000dbeda g 0f SECT 01 0000 [.text] _Atomcail_ulNoBiosMemoryConfigAndSize 00000000003c86d8 g 0f SECT 09 0000 [.data] _BARTS_GoldenSettings_A11 00000000003d8140 g 0f SECT 09 0000 [.data] _BONAIRE_GoldenSettings_A0 00000000003d8c68 g 0f SECT 09 0000 [.data] _BONAIRE_GoldenSettings_A1 00000000003c8480 g 0f SECT 09 0000 [.data] _Barts_RLC 00000000003d7358 g 0f SECT 09 0000 [.data] _BonaireAsicStateRegInfo 00000000003d7370 g 0f SECT 09 0000 [.data] _BonaireEngineRunningStateRegInfo 00000000003d75f0 g 0f SECT 09 0000 [.data] _BonaireFeatureSupport1 00000000003d6f70 g 0f SECT 09 0000 [.data] _BonaireMicroEngineRegisters 00000000003d8c80 g 0f SECT 09 0000 [.data] _BonaireTcpChanSteerLo 00000000003d0be0 g 0f SECT 09 0000 [.data] _Bonaire_CE_UCODE 00000000003d6f40 g 0f SECT 09 0000 [.data] _Bonaire_MEC1_UCODE 00000000003d2d90 g 0f SECT 09 0000 [.data] _Bonaire_ME_UCODE 00000000003cea30 g 0f SECT 09 0000 [.data] _Bonaire_PFP_UCODE 00000000003ca760 g 0f SECT 09 0000 [.data] _Bonaire_RLC_UCODE 00000000003cb7f8 g 0f SECT 09 0000 [.data] _Bonaire_SDMA0_UCODE 00000000003cc888 g 0f SECT 09 0000 [.data] _Bonaire_SDMA1_UCODE 00000000000dc414 g 0f SECT 01 0000 [.text] _Bonaire_SetupASIC 00000000003d9eb0 g 0f SECT 09 0000 [.data] _CAICOS_GoldenSettings_A11 00000000003e1970 g 0f SECT 09 0000 [.data] _CAILAsicCapsExceptionTable 00000000003dafb0 g 0f SECT 09 0000 [.data] _CAILAsicCapsInitTable 00000000000e8f88 g 0f SECT 01 0000 [.text] _CAILCheckForcedAGPSpeed 00000000000e848e g 0f SECT 01 0000 [.text] _CAILConnectedStandbyControl 00000000000e7e71 g 0f SECT 01 0000 [.text] _CAILCrossFireControl 00000000000e7e18 g 0f SECT 01 0000 [.text] _CAILCrossFireSupport 00000000000e639a g 0f SECT 01 0000 [.text] _CAILDoorbellApertureControl 00000000000e69e7 g 0f SECT 01 0000 [.text] _CAILEarlyASICInit 00000000000e7941 g 0f SECT 01 0000 [.text] _CAILEvaluateAsicHangState 00000000000e8480 g 0f SECT 01 0000 [.text] _CAILEventNotification 00000000000e73b0 g 0f SECT 01 0000 [.text] _CAILExit 00000000000e553c g 0f SECT 01 0000 [.text] _CAILFixChipsetBugs 00000000000e7378 g 0f SECT 01 0000 [.text] _CAILGetDynamicClockMode 00000000000e4ce4 g 0f SECT 01 0000 [.text] _CAILGetExtensionSize 00000000000e789d g 0f SECT 01 0000 [.text] _CAILGetHungBlocks 00000000000e7a31 g 0f SECT 01 0000 [.text] _CAILInitEasf 00000000000f2c25 g 0f SECT 01 0000 [.text] _CAILInitFunctionPointer 00000000000e4d5f g 0f SECT 01 0000 [.text] _CAILInitialize 00000000000e84ba g 0f SECT 01 0000 [.text] _CAILIoAccess 00000000000e756c g 0f SECT 01 0000 [.text] _CAILLiteResetVPU 00000000000e83b1 g 0f SECT 01 0000 [.text] _CAILMicroEngineControl 00000000000e4f07 g 0f SECT 01 0000 [.text] _CAILNoBiosInitializeAdapter 00000000000e768a g 0f SECT 01 0000 [.text] _CAILPerEngineReset 00000000000e4cef g 0f SECT 01 0000 [.text] _CAILPostVBIOS 00000000000e8388 g 0f SECT 01 0000 [.text] _CAILPowerControl 00000000000e4ff9 g 0f SECT 01 0000 [.text] _CAILQueryASICInfo 00000000000e6e69 g 0f SECT 01 0000 [.text] _CAILQueryASICName 00000000000e6ff5 g 0f SECT 01 0000 [.text] _CAILQueryASICNameEx 00000000000e751f g 0f SECT 01 0000 [.text] _CAILQueryASICRunningState 00000000000e7174 g 0f SECT 01 0000 [.text] _CAILQueryDualGraphicsBrandingName 00000000000e8355 g 0f SECT 01 0000 [.text] _CAILQueryEngineDependency 00000000000e7577 g 0f SECT 01 0000 [.text] _CAILQueryEngineRunningState 00000000000e65b2 g 0f SECT 01 0000 [.text] _CAILQueryMCAddressRange 00000000000e5435 g 0f SECT 01 0000 [.text] _CAILQuerySystemInfo 00000000000e6589 g 0f SECT 01 0000 [.text] _CAILReleaseMCAddressRange 00000000000e64ea g 0f SECT 01 0000 [.text] _CAILReserveMCAddressRange 00000000000e4ee1 g 0f SECT 01 0000 [.text] _CAILResetAndInitializeGUI 00000000000e7630 g 0f SECT 01 0000 [.text] _CAILResetEngine 00000000000e7cec g 0f SECT 01 0000 [.text] _CAILSamuControl 00000000000e7370 g 0f SECT 01 0000 [.text] _CAILSetDynamicClock 00000000000e78ab g 0f SECT 01 0000 [.text] _CAILSoftResetHungBlocks 00000000000e7502 g 0f SECT 01 0000 [.text] _CAILSurpriseRemoval 00000000000f4789 g 0f SECT 01 0000 [.text] _CAILSwitchPCIELane 00000000000e7a9d g 0f SECT 01 0000 [.text] _CAILUvdControl 00000000000e6d7c g 0f SECT 01 0000 [.text] _CAILVPURecoveryBegin 00000000000e6df6 g 0f SECT 01 0000 [.text] _CAILVPURecoveryEnd 00000000000e7bd4 g 0f SECT 01 0000 [.text] _CAILVceControl 00000000000e609e g 0f SECT 01 0000 [.text] _CAIL_ASICSetup 00000000000eb49a g 0f SECT 01 0000 [.text] _CAIL_AccessSpringDale 00000000000e84b4 g 0f SECT 01 0000 [.text] _CAIL_AsicShutDown 000000000010e58c g 0f SECT 01 0000 [.text] _CAIL_BridgeASPMWorkaround 000000000010e723 g 0f SECT 01 0000 [.text] _CAIL_CheckAspmCapability 00000000003dadf0 g 0f SECT 09 0000 [.data] _CAIL_DDI_CAPS_AMETHYST_A0 00000000003dae30 g 0f SECT 09 0000 [.data] _CAIL_DDI_CAPS_AMETHYST_A1 00000000003da5b0 g 0f SECT 09 0000 [.data] _CAIL_DDI_CAPS_BARTS_A11 00000000003daf30 g 0f SECT 09 0000 [.data] _CAIL_DDI_CAPS_BERMUDA_A0 00000000003da5f0 g 0f SECT 09 0000 [.data] _CAIL_DDI_CAPS_BLACKCOMB_A11 00000000003da930 g 0f SECT 09 0000 [.data] _CAIL_DDI_CAPS_BONAIRE_A0 00000000003da970 g 0f SECT 09 0000 [.data] _CAIL_DDI_CAPS_BONAIRE_A1 00000000003da030 g 0f SECT 09 0000 [.data] _CAIL_DDI_CAPS_BROADWAY_A11 00000000003da3b0 g 0f SECT 09 0000 [.data] _CAIL_DDI_CAPS_CAICOS_A11 00000000003da7b0 g 0f SECT 09 0000 [.data] _CAIL_DDI_CAPS_CAPEVERDE_A11 00000000003da7f0 g 0f SECT 09 0000 [.data] _CAIL_DDI_CAPS_CAPEVERDE_A12 00000000003daef0 g 0f SECT 09 0000 [.data] _CAIL_DDI_CAPS_CARRIZO_SIMNOW 00000000003da570 g 0f SECT 09 0000 [.data] _CAIL_DDI_CAPS_CAYMAN_A11 00000000003da0f0 g 0f SECT 09 0000 [.data] _CAIL_DDI_CAPS_CEDAR_A11 00000000003da130 g 0f SECT 09 0000 [.data] _CAIL_DDI_CAPS_CEDAR_MV_A11 00000000003d9f30 g 0f SECT 09 0000 [.data] _CAIL_DDI_CAPS_CYPRESS_A11 00000000003d9f70 g 0f SECT 09 0000 [.data] _CAIL_DDI_CAPS_CYPRESS_FS_A11 00000000003da8b0 g 0f SECT 09 0000 [.data] _CAIL_DDI_CAPS_DEVASTATOR_A0 00000000003da530 g 0f SECT 09 0000 [.data] _CAIL_DDI_CAPS_EMBEDDED_WHISTLER_A11 00000000003daf70 g 0f SECT 09 0000 [.data] _CAIL_DDI_CAPS_FIJI_A0 00000000003dae70 g 0f SECT 09 0000 [.data] _CAIL_DDI_CAPS_GODAVARI_A0 00000000003daeb0 g 0f SECT 09 0000 [.data] _CAIL_DDI_CAPS_GODAVARI_TABLET_A0 00000000003dacb0 g 0f SECT 09 0000 [.data] _CAIL_DDI_CAPS_HAWAII_A0 00000000003da830 g 0f SECT 09 0000 [.data] _CAIL_DDI_CAPS_HEATHROW_A11 00000000003da870 g 0f SECT 09 0000 [.data] _CAIL_DDI_CAPS_HEATHROW_A12 00000000003da330 g 0f SECT 09 0000 [.data] _CAIL_DDI_CAPS_IBIZA_A11 00000000003dad30 g 0f SECT 09 0000 [.data] _CAIL_DDI_CAPS_ICELAND_A0 00000000003d9ff0 g 0f SECT 09 0000 [.data] _CAIL_DDI_CAPS_JUNIPER_A11 00000000003daab0 g 0f SECT 09 0000 [.data] _CAIL_DDI_CAPS_KALINDI_A0 00000000003daaf0 g 0f SECT 09 0000 [.data] _CAIL_DDI_CAPS_KALINDI_A0_E 00000000003dab30 g 0f SECT 09 0000 [.data] _CAIL_DDI_CAPS_KALINDI_A1 00000000003dab70 g 0f SECT 09 0000 [.data] _CAIL_DDI_CAPS_KALINDI_A1_E 00000000003da370 g 0f SECT 09 0000 [.data] _CAIL_DDI_CAPS_KAUAI_A11 00000000003d9fb0 g 0f SECT 09 0000 [.data] _CAIL_DDI_CAPS_LEXINGTON_A11 00000000003da470 g 0f SECT 09 0000 [.data] _CAIL_DDI_CAPS_LOMBOK_A11 00000000003da0b0 g 0f SECT 09 0000 [.data] _CAIL_DDI_CAPS_MADISON_A11 00000000003dabf0 g 0f SECT 09 0000 [.data] _CAIL_DDI_CAPS_MARS_A0 00000000003dacf0 g 0f SECT 09 0000 [.data] _CAIL_DDI_CAPS_MAUI_A0 00000000003dabb0 g 0f SECT 09 0000 [.data] _CAIL_DDI_CAPS_OLAND_A0 00000000003dac30 g 0f SECT 09 0000 [.data] _CAIL_DDI_CAPS_OLAND_PRO_GL 00000000003da170 g 0f SECT 09 0000 [.data] _CAIL_DDI_CAPS_PARK_A11 00000000003da6b0 g 0f SECT 09 0000 [.data] _CAIL_DDI_CAPS_PITCAIRN_A11 00000000003da6f0 g 0f SECT 09 0000 [.data] _CAIL_DDI_CAPS_PITCAIRN_A12 00000000003da070 g 0f SECT 09 0000 [.data] _CAIL_DDI_CAPS_REDWOOD_A11 00000000003da9b0 g 0f SECT 09 0000 [.data] _CAIL_DDI_CAPS_SATURN_A0 00000000003da9f0 g 0f SECT 09 0000 [.data] _CAIL_DDI_CAPS_SATURN_A1 00000000003da8f0 g 0f SECT 09 0000 [.data] _CAIL_DDI_CAPS_SCRAPPER_LITE_A0 00000000003da3f0 g 0f SECT 09 0000 [.data] _CAIL_DDI_CAPS_SEYMOUR_A11 00000000003daa30 g 0f SECT 09 0000 [.data] _CAIL_DDI_CAPS_SPECTRE_A0 00000000003daa70 g 0f SECT 09 0000 [.data] _CAIL_DDI_CAPS_SPECTRE_A0_E 00000000003da1f0 g 0f SECT 09 0000 [.data] _CAIL_DDI_CAPS_SUMO_A0 00000000003da2b0 g 0f SECT 09 0000 [.data] _CAIL_DDI_CAPS_SUMO_B0 00000000003dac70 g 0f SECT 09 0000 [.data] _CAIL_DDI_CAPS_SUN_A0 00000000003da1b0 g 0f SECT 09 0000 [.data] _CAIL_DDI_CAPS_SUPERSUMO_A0 00000000003da270 g 0f SECT 09 0000 [.data] _CAIL_DDI_CAPS_SUPERSUMO_B0 00000000003da630 g 0f SECT 09 0000 [.data] _CAIL_DDI_CAPS_TAHITI_A11 00000000003da670 g 0f SECT 09 0000 [.data] _CAIL_DDI_CAPS_TAHITI_A21 00000000003da4b0 g 0f SECT 09 0000 [.data] _CAIL_DDI_CAPS_THAMES_A11 00000000003dad70 g 0f SECT 09 0000 [.data] _CAIL_DDI_CAPS_TONGA_A0 00000000003dadb0 g 0f SECT 09 0000 [.data] _CAIL_DDI_CAPS_TONGA_A1 00000000003da430 g 0f SECT 09 0000 [.data] _CAIL_DDI_CAPS_TURKS_A11 00000000003da4f0 g 0f SECT 09 0000 [.data] _CAIL_DDI_CAPS_WHISTLER_A11 00000000003da730 g 0f SECT 09 0000 [.data] _CAIL_DDI_CAPS_WIMBLEDON_A11 00000000003da770 g 0f SECT 09 0000 [.data] _CAIL_DDI_CAPS_WIMBLEDON_A12 00000000003da230 g 0f SECT 09 0000 [.data] _CAIL_DDI_CAPS_WRESTLER_A0 00000000003da2f0 g 0f SECT 09 0000 [.data] _CAIL_DDI_CAPS_WRESTLER_A1 00000000000e63e4 g 0f SECT 01 0000 [.text] _CAIL_ExecuteBIOSTable 00000000000e697c g 0f SECT 01 0000 [.text] _CAIL_GetGuiStatus 00000000000e65db g 0f SECT 01 0000 [.text] _CAIL_InitAdditionInfo 00000000000e7f10 g 0f SECT 01 0000 [.text] _CAIL_InitParameter 00000000000e6790 g 0f SECT 01 0000 [.text] _CAIL_QueryAdditionInfo 00000000000e63b3 g 0f SECT 01 0000 [.text] _CAIL_QueryBIOSReserveFB 00000000000e8140 g 0f SECT 01 0000 [.text] _CAIL_QueryParameter 00000000000e6490 g 0f SECT 01 0000 [.text] _CAIL_QueryTableRevision 00000000000e8340 g 0f SECT 01 0000 [.text] _CAIL_ReConfigUmaSpLayout 00000000000e6cf3 g 0f SECT 01 0000 [.text] _CAIL_TuneNorthBridge 000000000010f243 g 0f SECT 01 0000 [.text] _CAIL_VPURecoveryBegin 000000000010f406 g 0f SECT 01 0000 [.text] _CAIL_VPURecoveryEnd 00000000000e69a5 g 0f SECT 01 0000 [.text] _CAIL_WaitForIdle 00000000000e69c6 g 0f SECT 01 0000 [.text] _CAIL_WaitForMCIdle 00000000003e3fa8 g 0f SECT 09 0000 [.data] _CAPEVERDE_GoldenSettings_A11 00000000003e4cd8 g 0f SECT 09 0000 [.data] _CAPEVERDE_GoldenSettings_A12 00000000003e7188 g 0f SECT 09 0000 [.data] _CARRIZO_GoldenSettings_A0_8812 000000000043d7d0 g 0f SECT 09 0000 [.data] _CAYMAN_GoldenSettings_A11 000000000043dd80 g 0f SECT 09 0000 [.data] _CEDAR_GoldenSettings_A11 00000000004d3a50 g 0f SECT 09 0000 [.data] _CF_MEM_CLT_GUP_RANGE_TAHITI 0000000000122599 g 0f SECT 01 0000 [.text] _CSBGetBuffer 00000000001224fc g 0f SECT 01 0000 [.text] _CSBGetBufferSize 000000000043ffa8 g 0f SECT 09 0000 [.data] _CYPRESS_GoldenSettings_A11 0000000000440968 g 0f SECT 09 0000 [.data] _CYPRESS_GoldenSettings_A12 00000000003d9c40 g 0f SECT 09 0000 [.data] _Caicos_RLC 00000000000ed521 g 0f SECT 01 0000 [.text] _CailAllocatSysResource 00000000000f3e64 g 0f SECT 01 0000 [.text] _CailAllocateLargeMemory 00000000000f3ddb g 0f SECT 01 0000 [.text] _CailAllocateMemory 00000000000e84f0 g 0f SECT 01 0000 [.text] _CailCapsEnabled 00000000000ef9c4 g 0f SECT 01 0000 [.text] _CailCfCheckMaxXDMASupportedMVPUNumber 00000000000eec1f g 0f SECT 01 0000 [.text] _CailCfCloseTemporaryMailBox 00000000000ef8c4 g 0f SECT 01 0000 [.text] _CailCfConfigSetup 00000000000eea82 g 0f SECT 01 0000 [.text] _CailCfGetP2PFlushCommand 00000000000ef683 g 0f SECT 01 0000 [.text] _CailCfGetP2PFlushCommandEx 00000000000ee453 g 0f SECT 01 0000 [.text] _CailCfInitPeerAperture 00000000000ee7ef g 0f SECT 01 0000 [.text] _CailCfInitXdmaAperture 00000000000eeb37 g 0f SECT 01 0000 [.text] _CailCfOpenTemporaryMailBox 00000000000ef640 g 0f SECT 01 0000 [.text] _CailCfQueryMemoryClientGroup 00000000000ef833 g 0f SECT 01 0000 [.text] _CailCfResyncPeerApertureInternalState 00000000000ee72c g 0f SECT 01 0000 [.text] _CailCfSetPeerApertureDefault 00000000000ee9f9 g 0f SECT 01 0000 [.text] _CailCfSetXdmaApertureDefault 00000000000e9a50 g 0f SECT 01 0000 [.text] _CailCheckAGPCalibrationFix 00000000000e968c g 0f SECT 01 0000 [.text] _CailCheckAGPFastWrite 00000000000e982f g 0f SECT 01 0000 [.text] _CailCheckAGPWrite 00000000000ea8e0 g 0f SECT 01 0000 [.text] _CailCheckASICInfo 00000000000ea6aa g 0f SECT 01 0000 [.text] _CailCheckAdapterFireGLBoard 00000000000eb075 g 0f SECT 01 0000 [.text] _CailCheckAsic64bitBars 00000000000ebe53 g 0f SECT 01 0000 [.text] _CailCheckAsicResetState 00000000000eb89c g 0f SECT 01 0000 [.text] _CailCheckAsicState 00000000000eb2d8 g 0f SECT 01 0000 [.text] _CailCheckBIOSDependentASICInfo 00000000000e9aae g 0f SECT 01 0000 [.text] _CailCheckChipSetInfo 00000000000ef0c6 g 0f SECT 01 0000 [.text] _CailCheckCrossFireAsicCfg 00000000000eee48 g 0f SECT 01 0000 [.text] _CailCheckCrossFireAsicIDInfo 00000000000e9226 g 0f SECT 01 0000 [.text] _CailCheckH2PBridge 00000000000e9ee5 g 0f SECT 01 0000 [.text] _CailCheckNBAutoCalibration 00000000000e9315 g 0f SECT 01 0000 [.text] _CailCheckP2PBridge 00000000000ea6f1 g 0f SECT 01 0000 [.text] _CailCheckPCIELinkStatus 00000000000eb0bb g 0f SECT 01 0000 [.text] _CailCheckPowerXpress 00000000000f0a10 g 0f SECT 01 0000 [.text] _CailCheckReservedFbBlock 00000000000e903b g 0f SECT 01 0000 [.text] _CailCheckRomlength_HeaderOffset 00000000000ea892 g 0f SECT 01 0000 [.text] _CailCheckRootPCIELinkSpeed 000000000010ffac g 0f SECT 01 0000 [.text] _CailCheckSPIPerformanceCounter 00000000000e9a28 g 0f SECT 01 0000 [.text] _CailCheckSavePCIConfig 00000000000e9415 g 0f SECT 01 0000 [.text] _CailCheckSupportedAGPRate 00000000000ea078 g 0f SECT 01 0000 [.text] _CailCheckTargetBridgeInfo 00000000000e8fde g 0f SECT 01 0000 [.text] _CailCheckVidMemoryType 00000000000ed19f g 0f SECT 01 0000 [.text] _CailCleanUpResource 00000000000ed487 g 0f SECT 01 0000 [.text] _CailConnectedStandbyQueryRegisterList 00000000000ed4d1 g 0f SECT 01 0000 [.text] _CailConnectedStandbySetMasterPacketMCAddress 00000000000f3f14 g 0f SECT 01 0000 [.text] _CailDelayMicroSeconds 00000000000ed08f g 0f SECT 01 0000 [.text] _CailDetectECCSupport 00000000000ebe9c g 0f SECT 01 0000 [.text] _CailDisableBridgeASPM 00000000000eb64a g 0f SECT 01 0000 [.text] _CailDoTuneNorthBridge 00000000000ed366 g 0f SECT 01 0000 [.text] _CailEnableAspmOnOtherFunction 00000000000f9b22 g 0f SECT 01 0000 [.text] _CailEnterCriticalSection 00000000000ebc55 g 0f SECT 01 0000 [.text] _CailEvaluateEnginesState 00000000000ebd24 g 0f SECT 01 0000 [.text] _CailEvaluateNonEngineAsicState 00000000000ea66d g 0f SECT 01 0000 [.text] _CailFindAsicRevID 00000000000f006b g 0f SECT 01 0000 [.text] _CailGetCSBBufferSize 00000000000e90a0 g 0f SECT 01 0000 [.text] _CailGetCapsPointer 00000000000f439b g 0f SECT 01 0000 [.text] _CailGetEfuseBoxBitSetting 00000000000eb25d g 0f SECT 01 0000 [.text] _CailGetGfxDebugBarAddr 00000000000f3766 g 0f SECT 01 0000 [.text] _CailGetIndReg 00000000000e953b g 0f SECT 01 0000 [.text] _CailGetMasterOffsetToAgpCaps 00000000000f37bb g 0f SECT 01 0000 [.text] _CailGetPCIEIndReg 00000000000f39ef g 0f SECT 01 0000 [.text] _CailGetPCIEPortPReg 00000000000f4335 g 0f SECT 01 0000 [.text] _CailGetParserStaticBuffer 00000000000e9dda g 0f SECT 01 0000 [.text] _CailGetPhysicalAddressforSpringdale 00000000000f3b09 g 0f SECT 01 0000 [.text] _CailGetPifPhy0IndReg 00000000000f3c23 g 0f SECT 01 0000 [.text] _CailGetPifPhy1IndReg 00000000000f38d5 g 0f SECT 01 0000 [.text] _CailGetSmcIndReg 0000000000443e00 g 0f SECT 09 0000 [.data] _CailGodavariMetaDataList_CP_CE_PFP_ME 0000000000443e40 g 0f SECT 09 0000 [.data] _CailGodavariMetaDataList_MEC1 0000000000443c80 g 0f SECT 09 0000 [.data] _CailGodavariMetaDataList_SDMA0 0000000000443d40 g 0f SECT 09 0000 [.data] _CailGodavariMetaDataList_SDMA1 00000000000ed45a g 0f SECT 01 0000 [.text] _CailGpioReadPin 00000000000eb10e g 0f SECT 01 0000 [.text] _CailIdentifyCrossDisplayAndXGP 00000000000f0246 g 0f SECT 01 0000 [.text] _CailInitCSBCommandBuffer 00000000000ea6b7 g 0f SECT 01 0000 [.text] _CailInitCapTable 00000000000ec89e g 0f SECT 01 0000 [.text] _CailInitializeSamuFwInfo 00000000000ea595 g 0f SECT 01 0000 [.text] _CailIsAGPMasterEnabled 00000000000e97e8 g 0f SECT 01 0000 [.text] _CailIsAGPMasterFastWriteSupported 00000000000e9791 g 0f SECT 01 0000 [.text] _CailIsAGPTargetFastWriteSupported 00000000000dac86 g 0f SECT 01 0000 [.text] _CailIsPCIEToAGPBridgePresent 00000000004b7750 g 0f SECT 09 0000 [.data] _CailKalindiMetaDataList_CP_CE_PFP_ME 00000000004b7790 g 0f SECT 09 0000 [.data] _CailKalindiMetaDataList_MEC1 00000000004b75d0 g 0f SECT 09 0000 [.data] _CailKalindiMetaDataList_SDMA0 00000000004b7690 g 0f SECT 09 0000 [.data] _CailKalindiMetaDataList_SDMA1 00000000000f9b4b g 0f SECT 01 0000 [.text] _CailLeaveCriticalSection 000000000010fe9d g 0f SECT 01 0000 [.text] _CailMonitorEngineInternalState 000000000010fa6d g 0f SECT 01 0000 [.text] _CailMonitorEngineReadWritePointers 0000000000110176 g 0f SECT 01 0000 [.text] _CailMonitorPerformanceCounter 00000000000ebdf9 g 0f SECT 01 0000 [.text] _CailPrepareUMASPInterleaving 00000000000e6ce9 g 0f SECT 01 0000 [.text] _CailQuerySpecificAsicCaps 00000000000f3db7 g 0f SECT 01 0000 [.text] _CailReadATIRegister 00000000000f42a0 g 0f SECT 01 0000 [.text] _CailReadDataFromFBBlock 00000000000f4294 g 0f SECT 01 0000 [.text] _CailReadFBData 00000000000f3f44 g 0f SECT 01 0000 [.text] _CailReadFBViaMmr 00000000000e954a g 0f SECT 01 0000 [.text] _CailReadInRealIDforVIA 00000000000f4324 g 0f SECT 01 0000 [.text] _CailReadMC 00000000000f43d9 g 0f SECT 01 0000 [.text] _CailReadMmPciConfigRegister 00000000000f42ef g 0f SECT 01 0000 [.text] _CailReadPCIConfigData 00000000000f4313 g 0f SECT 01 0000 [.text] _CailReadPLL 00000000000f4342 g 0f SECT 01 0000 [.text] _CailReadRcuIndData 00000000000f455f g 0f SECT 01 0000 [.text] _CailReadSamIndirectRegister 00000000000f4543 g 0f SECT 01 0000 [.text] _CailReadSamSabIndirectRegister 00000000000e8b89 g 0f SECT 01 0000 [.text] _CailReadinOverrideRegistrySetting 00000000000e8627 g 0f SECT 01 0000 [.text] _CailReadinRegistryFlags 00000000000f3ec0 g 0f SECT 01 0000 [.text] _CailReleaseLargeMemory 00000000000f3e30 g 0f SECT 01 0000 [.text] _CailReleaseMemory 000000000010fa07 g 0f SECT 01 0000 [.text] _CailRestorePciCfgSpace 00000000000eca90 g 0f SECT 01 0000 [.text] _CailSamuEngineParameters 00000000000ec9da g 0f SECT 01 0000 [.text] _CailSamuInit 00000000000ecacb g 0f SECT 01 0000 [.text] _CailSamuLoad 00000000000ecd00 g 0f SECT 01 0000 [.text] _CailSamuSetClk 00000000000eca4d g 0f SECT 01 0000 [.text] _CailSamuSuspend 00000000000e850a g 0f SECT 01 0000 [.text] _CailSaveCailInitInfo 000000000010f9b2 g 0f SECT 01 0000 [.text] _CailSavePciCfgSpace 00000000000e912b g 0f SECT 01 0000 [.text] _CailSetAgpTargetInfo 00000000000f0158 g 0f SECT 01 0000 [.text] _CailSetCSBBufferMCAddress 00000000000e8b53 g 0f SECT 01 0000 [.text] _CailSetCaps 00000000000f3789 g 0f SECT 01 0000 [.text] _CailSetIndReg 00000000000eb5dc g 0f SECT 01 0000 [.text] _CailSetOptimalNB 00000000000f3845 g 0f SECT 01 0000 [.text] _CailSetPCIEIndReg 00000000000f3a79 g 0f SECT 01 0000 [.text] _CailSetPCIEPortPReg 00000000000f3b93 g 0f SECT 01 0000 [.text] _CailSetPifPhy0IndReg 00000000000f3cad g 0f SECT 01 0000 [.text] _CailSetPifPhy1IndReg 00000000000eb30c g 0f SECT 01 0000 [.text] _CailSetRegulatorData 00000000000dad37 g 0f SECT 01 0000 [.text] _CailSetRialtoCapTable 00000000000f395f g 0f SECT 01 0000 [.text] _CailSetSmcIndReg 00000000000ebfde g 0f SECT 01 0000 [.text] _CailSetupCgReferenceClock 00000000000eb438 g 0f SECT 01 0000 [.text] _CailSetupChipsetRegisters 00000000000daec1 g 0f SECT 01 0000 [.text] _CailSetupRialtoAGP 00000000000ec0fe g 0f SECT 01 0000 [.text] _CailSynchronizeMaxPayloadSize 00000000000e8b6d g 0f SECT 01 0000 [.text] _CailUnSetCaps 00000000000f3d3d g 0f SECT 01 0000 [.text] _CailUpdateUvdCtxIndRegisters 00000000000ec5a5 g 0f SECT 01 0000 [.text] _CailUvdEngineParameters 00000000000ec2e1 g 0f SECT 01 0000 [.text] _CailUvdInit 00000000000ec5c2 g 0f SECT 01 0000 [.text] _CailUvdLoadEngine 00000000000ec55f g 0f SECT 01 0000 [.text] _CailUvdPowerOnOff 00000000000ec42b g 0f SECT 01 0000 [.text] _CailUvdQueryClockInfo 00000000000ec459 g 0f SECT 01 0000 [.text] _CailUvdSetVclkDclk 00000000000ec4f3 g 0f SECT 01 0000 [.text] _CailUvdSetupCacheWindowsAndFwv 00000000000ec393 g 0f SECT 01 0000 [.text] _CailUvdSuspend 00000000000ec819 g 0f SECT 01 0000 [.text] _CailVceEngineParameters 00000000000ec5fd g 0f SECT 01 0000 [.text] _CailVceInit 00000000000ec863 g 0f SECT 01 0000 [.text] _CailVceLoadEngine 00000000000ec7d3 g 0f SECT 01 0000 [.text] _CailVcePowerOnOff 00000000000ec71b g 0f SECT 01 0000 [.text] _CailVceQueryClockInfo 00000000000ec749 g 0f SECT 01 0000 [.text] _CailVceSetEvclkEcclk 00000000000ec695 g 0f SECT 01 0000 [.text] _CailVceSuspend 00000000000ed44f g 0f SECT 01 0000 [.text] _CailWaitForDmaEngineIdle 00000000000f3f2f g 0f SECT 01 0000 [.text] _CailWriteATIRegister 00000000000f424c g 0f SECT 01 0000 [.text] _CailWriteDataToFBBlock 00000000000f4240 g 0f SECT 01 0000 [.text] _CailWriteFBData 00000000000f40cd g 0f SECT 01 0000 [.text] _CailWriteFBViaMmr 00000000000f432f g 0f SECT 01 0000 [.text] _CailWriteMC 00000000000f4486 g 0f SECT 01 0000 [.text] _CailWriteMmPciConfigRegister 00000000000f4301 g 0f SECT 01 0000 [.text] _CailWritePCIConfigData 00000000000f431e g 0f SECT 01 0000 [.text] _CailWritePLL 00000000000f436c g 0f SECT 01 0000 [.text] _CailWriteRcuIndData 00000000000f456d g 0f SECT 01 0000 [.text] _CailWriteSamIndirectRegister 00000000000f4551 g 0f SECT 01 0000 [.text] _CailWriteSamSabIndirectRegister 00000000000f73a4 g 0f SECT 01 0000 [.text] _Cail_AcpiMethod_CheckAtcsSupported 00000000000f740d g 0f SECT 01 0000 [.text] _Cail_AcpiMethod_NotifySbiosLaneWidthChange 00000000000f7604 g 0f SECT 01 0000 [.text] _Cail_AcpiMethod_NotifySbiosPcieDeviceReady 00000000000f7645 g 0f SECT 01 0000 [.text] _Cail_AcpiMethod_QuerySbiosPciePerformance 00000000000ed034 g 0f SECT 01 0000 [.text] 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[.text] _Cail_CapeVerde_SetVcePowerGating 00000000000fa908 g 0f SECT 01 0000 [.text] _Cail_CapeVerde_UpdateSystemClockGatingMode 00000000000fb851 g 0f SECT 01 0000 [.text] _Cail_CapeVerde_VcePgfsmPowerDown 00000000000fb7a5 g 0f SECT 01 0000 [.text] _Cail_CapeVerde_VcePgfsmPowerUp 00000000000fc21c g 0f SECT 01 0000 [.text] _Cail_Carrizo_InitCPJumpTable 00000000000fc777 g 0f SECT 01 0000 [.text] _Cail_Carrizo_InitFunctionPointer 00000000000fc2e4 g 0f SECT 01 0000 [.text] _Cail_Carrizo_InitializePowerGating 0000000000101544 g 0f SECT 01 0000 [.text] _Cail_Cayman_ApplyMaxReadRequestSizeWorkaround 00000000000fddf3 g 0f SECT 01 0000 [.text] _Cail_Cayman_AsicState 000000000010139a g 0f SECT 01 0000 [.text] _Cail_Cayman_CfCloseTemporaryMailBox 0000000000101237 g 0f SECT 01 0000 [.text] _Cail_Cayman_CfGetP2PFlushCommand 0000000000100834 g 0f SECT 01 0000 [.text] _Cail_Cayman_CfInitPeerAperture 00000000001012f3 g 0f SECT 01 0000 [.text] _Cail_Cayman_CfOpenTemporaryMailBox 000000000010142c g 0f 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[.text] _Cail_Devastator_SetUvdVclkDclk 000000000010856c g 0f SECT 01 0000 [.text] _Cail_Devastator_SetVceEclk 0000000000108250 g 0f SECT 01 0000 [.text] _Cail_Devastator_SetVceStallSignal 0000000000108e9b g 0f SECT 01 0000 [.text] _Cail_Devastator_SetupCgReferenceClock 0000000000107bca g 0f SECT 01 0000 [.text] _Cail_Devastator_Soft_Reset_VCE 0000000000107d11 g 0f SECT 01 0000 [.text] _Cail_Devastator_UnblackoutMC 0000000000108489 g 0f SECT 01 0000 [.text] _Cail_Devastator_VCE_WaitForIdle 0000000000108979 g 0f SECT 01 0000 [.text] _Cail_Devastator_VceInit 0000000000108ca4 g 0f SECT 01 0000 [.text] _Cail_Devastator_VceSuspend 0000000000107d6a g 0f SECT 01 0000 [.text] _Cail_Devastator_ulNoBiosMemoryConfigAndSize 00000000000f978b g 0f SECT 01 0000 [.text] _Cail_DisablePowerGatingClockGating 00000000000f08a6 g 0f SECT 01 0000 [.text] _Cail_EnableEASE 00000000000ed0c4 g 0f SECT 01 0000 [.text] _Cail_EnableExtendedTagField 00000000000ebf34 g 0f SECT 01 0000 [.text] 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[.text] _Cail_MCILAtiDebugPost 00000000000f5fa1 g 0f SECT 01 0000 [.text] _Cail_MCILCopyMemory 00000000000f7399 g 0f SECT 01 0000 [.text] _Cail_MCILDecryptUVDFW 00000000000f6062 g 0f SECT 01 0000 [.text] _Cail_MCILDelayForVPURecover 00000000000f6043 g 0f SECT 01 0000 [.text] _Cail_MCILDelayInMicroSecond 00000000000f7a31 g 0f SECT 01 0000 [.text] _Cail_MCILDisableCAC 00000000000f5814 g 0f SECT 01 0000 [.text] _Cail_MCILEnableTdrClock 00000000000f52d0 g 0f SECT 01 0000 [.text] _Cail_MCILExit 00000000000f6500 g 0f SECT 01 0000 [.text] _Cail_MCILFreeMemory 00000000000f5417 g 0f SECT 01 0000 [.text] _Cail_MCILGetGraphicsDeviceTypes 00000000000f62f7 g 0f SECT 01 0000 [.text] _Cail_MCILGetRegistryString 00000000000f6182 g 0f SECT 01 0000 [.text] _Cail_MCILGetRegistryValue 00000000000f52c4 g 0f SECT 01 0000 [.text] _Cail_MCILInitialize 00000000000f7728 g 0f SECT 01 0000 [.text] _Cail_MCILInterlockedCompareExchange 00000000000f7750 g 0f SECT 01 0000 [.text] _Cail_MCILInterlockedExchange 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[.text] _Cail_MCILReadRomImage 00000000000f63ad g 0f SECT 01 0000 [.text] _Cail_MCILSetRegistryString 00000000000f623e g 0f SECT 01 0000 [.text] _Cail_MCILSetRegistryValue 00000000000f5c7c g 0f SECT 01 0000 [.text] _Cail_MCILSyncExecute 00000000000f7aee g 0f SECT 01 0000 [.text] _Cail_MCILTrace0 00000000000f7af6 g 0f SECT 01 0000 [.text] _Cail_MCILTrace1 00000000000f7afe g 0f SECT 01 0000 [.text] _Cail_MCILTrace2 00000000000f5720 g 0f SECT 01 0000 [.text] _Cail_MCILTurnOnAsicBlock 00000000000f670b g 0f SECT 01 0000 [.text] _Cail_MCILUnlockMemory 00000000000f6979 g 0f SECT 01 0000 [.text] _Cail_MCILUnmapMemory 00000000000f6827 g 0f SECT 01 0000 [.text] _Cail_MCILUnmapVirtualFromGartSpace 00000000000f58bc g 0f SECT 01 0000 [.text] _Cail_MCILUpdateClockGating 00000000000f6a3f g 0f SECT 01 0000 [.text] _Cail_MCILWaitFor 00000000000f77d6 g 0f SECT 01 0000 [.text] _Cail_MCILWaitForFwLoadFinished 00000000000f5ac8 g 0f SECT 01 0000 [.text] _Cail_MCILWritePciCfg 00000000000f5e07 g 0f SECT 01 0000 [.text] _Cail_MCILWritePciCfgByBusNo 00000000000f6f81 g 0f SECT 01 0000 [.text] _Cail_MCILWriteReg 000000000010f5ef g 0f SECT 01 0000 [.text] _Cail_PCICfgResetMethod 000000000010f4f5 g 0f SECT 01 0000 [.text] _Cail_PCIeHotResetMethod 00000000000f9781 g 0f SECT 01 0000 [.text] _Cail_PerformPowerControl 00000000000f8ba1 g 0f SECT 01 0000 [.text] _Cail_PowerControl 00000000000e624b g 0f SECT 01 0000 [.text] _Cail_Powerdown 00000000000e5e8a g 0f SECT 01 0000 [.text] _Cail_Powerup 00000000000ea5e3 g 0f SECT 01 0000 [.text] _Cail_PreInit_AsicCaps 000000000010e241 g 0f SECT 01 0000 [.text] _Cail_Radeon_QueryGUIStatus 00000000000f9964 g 0f SECT 01 0000 [.text] _Cail_RestoreClockPowerGating 00000000000f71a8 g 0f SECT 01 0000 [.text] _Cail_RestoreFloatPointState 00000000000f70f4 g 0f SECT 01 0000 [.text] _Cail_SaveFloatPointState 00000000000f9be4 g 0f SECT 01 0000 [.text] _Cail_SearchStringForPattern 00000000000f0920 g 0f SECT 01 0000 [.text] _Cail_SearchTableInEasfBinary 00000000000ed479 g 0f SECT 01 0000 [.text] _Cail_SetSmuDfsBypassMode 0000000000110d14 g 0f SECT 01 0000 [.text] _Cail_Spectre_GetSmuFwVersion 0000000000110375 g 0f SECT 01 0000 [.text] _Cail_Spectre_InitCPJumpTable 0000000000110d23 g 0f SECT 01 0000 [.text] _Cail_Spectre_InitFunctionPointer 000000000011033f g 0f SECT 01 0000 [.text] _Cail_Spectre_InitSaveRestoreBuffer 0000000000110437 g 0f SECT 01 0000 [.text] _Cail_Spectre_InitializePowerGating 00000000001102e4 g 0f SECT 01 0000 [.text] _Cail_Spectre_IsVbiosPosted 00000000001102fa g 0f SECT 01 0000 [.text] _Cail_Spectre_RestoreAdapterCfgRegisters 0000000000110acc g 0f SECT 01 0000 [.text] _Cail_Spectre_RestoreGfxSafeMode 0000000000111a64 g 0f SECT 01 0000 [.text] _Cail_Sumo_EnableF32 0000000000111a04 g 0f SECT 01 0000 [.text] _Cail_Sumo_GetClearStateAndRlcSaveRestoreRegisterListInfo 0000000000111488 g 0f SECT 01 0000 [.text] _Cail_Sumo_GetIntegrateAsicFbMcBaseAddr 00000000001116b5 g 0f SECT 01 0000 [.text] _Cail_Sumo_InitUvdClock 0000000000111995 g 0f SECT 01 0000 [.text] _Cail_Sumo_InitializeClearStateBuffer 000000000011195d g 0f SECT 01 0000 [.text] _Cail_Sumo_InitializeRlcHistoryBuffer 0000000000111a85 g 0f SECT 01 0000 [.text] _Cail_Sumo_Powerdown 0000000000111677 g 0f SECT 01 0000 [.text] _Cail_Sumo_RestoreAdapterCfgRegisters 0000000000111943 g 0f SECT 01 0000 [.text] _Cail_Sumo_SetAdditionalUvdClockGatingBranchParameter 0000000000111904 g 0f SECT 01 0000 [.text] _Cail_Sumo_SetAdditionalUvdDynamicClockModeParameter 000000000011170e g 0f SECT 01 0000 [.text] _Cail_Sumo_SetUvdVclkDclk 0000000000111ac3 g 0f SECT 01 0000 [.text] _Cail_Sumo_init_additional_registers 00000000001114a2 g 0f SECT 01 0000 [.text] _Cail_Sumo_ulNoBiosMemoryConfigAndSize 0000000000111b0e g 0f SECT 01 0000 [.text] _Cail_Tahiti_AsicState 0000000000116a23 g 0f SECT 01 0000 [.text] _Cail_Tahiti_CfCloseTemporaryMailBox 0000000000116ae8 g 0f SECT 01 0000 [.text] _Cail_Tahiti_CfGetP2PFlushCommand 00000000001161ed g 0f SECT 01 0000 [.text] _Cail_Tahiti_CfInitPeerAperture 0000000000116e07 g 0f SECT 01 0000 [.text] _Cail_Tahiti_CfInitXdmaAperture 000000000011697c g 0f SECT 01 0000 [.text] _Cail_Tahiti_CfOpenTemporaryMailBox 0000000000116831 g 0f SECT 01 0000 [.text] _Cail_Tahiti_CfSetPeerApertureDefault 0000000000116f77 g 0f SECT 01 0000 [.text] _Cail_Tahiti_CfSetXdmaApertureDefault 0000000000111cfe g 0f SECT 01 0000 [.text] _Cail_Tahiti_CheckAsicDowngradeInfo 0000000000116174 g 0f SECT 01 0000 [.text] _Cail_Tahiti_CheckCfAsicCfg 0000000000111c98 g 0f SECT 01 0000 [.text] _Cail_Tahiti_CheckFireGL 000000000011238e g 0f SECT 01 0000 [.text] _Cail_Tahiti_CheckMemoryConfiguration 0000000000116cea g 0f SECT 01 0000 [.text] _Cail_Tahiti_DetectECCSupport 0000000000117400 g 0f SECT 01 0000 [.text] _Cail_Tahiti_Disable_ASPM 00000000001129c3 g 0f SECT 01 0000 [.text] _Cail_Tahiti_EnableLBPW 0000000000117d45 g 0f SECT 01 0000 [.text] _Cail_Tahiti_EventNotification 00000000001160bd g 0f SECT 01 0000 [.text] _Cail_Tahiti_ExecuteDmaCopy 0000000000111b65 g 0f SECT 01 0000 [.text] _Cail_Tahiti_FindAsicRevID 0000000000116cb0 g 0f SECT 01 0000 [.text] _Cail_Tahiti_GetDoutScratch3 0000000000111ba9 g 0f SECT 01 0000 [.text] _Cail_Tahiti_GetFbMemorySize 0000000000116ab5 g 0f SECT 01 0000 [.text] _Cail_Tahiti_GetGbTileMode 00000000001160b2 g 0f SECT 01 0000 [.text] _Cail_Tahiti_GetMaxDmaCopyLengthBytes 0000000000116bc2 g 0f SECT 01 0000 [.text] _Cail_Tahiti_GetPcieLinkSpeedSupport 0000000000115760 g 0f SECT 01 0000 [.text] _Cail_Tahiti_GetSmcIndReg 0000000000112642 g 0f SECT 01 0000 [.text] _Cail_Tahiti_Get_PCIE_Speed 00000000001175ce g 0f SECT 01 0000 [.text] _Cail_Tahiti_GpioReadPin 0000000000117666 g 0f SECT 01 0000 [.text] _Cail_Tahiti_InitFunctionPointer 000000000011399e g 0f SECT 01 0000 [.text] _Cail_Tahiti_IsDisplayBlockHang 0000000000113b18 g 0f SECT 01 0000 [.text] _Cail_Tahiti_IsGuiIdle 0000000000114108 g 0f SECT 01 0000 [.text] _Cail_Tahiti_IsNonEngineChipHung 0000000000113b76 g 0f SECT 01 0000 [.text] _Cail_Tahiti_IsUVDIdle 0000000000113b9f g 0f SECT 01 0000 [.text] _Cail_Tahiti_IsVCEIdle 0000000000113e55 g 0f SECT 01 0000 [.text] _Cail_Tahiti_LiteResetEngine 00000000001122cf g 0f SECT 01 0000 [.text] _Cail_Tahiti_MemoryConfigAndSize 0000000000113bc7 g 0f SECT 01 0000 [.text] _Cail_Tahiti_MonitorEngineInternalState 0000000000113d6c g 0f SECT 01 0000 [.text] _Cail_Tahiti_MonitorLBPWPerformanceCounter 000000000011751f g 0f SECT 01 0000 [.text] _Cail_Tahiti_PCIELane_Switch 000000000011749c g 0f SECT 01 0000 [.text] _Cail_Tahiti_PCIELane_Switch_With_Workaround 0000000000116fd8 g 0f SECT 01 0000 [.text] _Cail_Tahiti_PCIELane_Switch_Workaround 0000000000112c5a g 0f SECT 01 0000 [.text] _Cail_Tahiti_Powerdown 0000000000112cf7 g 0f SECT 01 0000 [.text] _Cail_Tahiti_QueryGUIStatus 00000000001138b8 g 0f SECT 01 0000 [.text] _Cail_Tahiti_ResetHW 0000000000113843 g 0f SECT 01 0000 [.text] _Cail_Tahiti_RestoreAdapterCfgRegisters 000000000011746a g 0f SECT 01 0000 [.text] _Cail_Tahiti_Restore_ASPM 0000000000115770 g 0f SECT 01 0000 [.text] _Cail_Tahiti_SetSmcIndReg 0000000000114fa9 g 0f SECT 01 0000 [.text] _Cail_Tahiti_SetUvdVclkDclk 0000000000115f07 g 0f SECT 01 0000 [.text] _Cail_Tahiti_SetVceEvclkEcclk 0000000000112430 g 0f SECT 01 0000 [.text] _Cail_Tahiti_SetupASIC 0000000000111c70 g 0f SECT 01 0000 [.text] _Cail_Tahiti_SetupCgReferenceClock 00000000001150cb g 0f SECT 01 0000 [.text] _Cail_Tahiti_SetupUvdCacheWindowsAndFwv 0000000000117fe2 g 0f SECT 01 0000 [.text] _Cail_Tahiti_UpdateGbTilingModeTable 0000000000111bd6 g 0f SECT 01 0000 [.text] _Cail_Tahiti_UpdateSwConstantForHwConfig 0000000000112b4c g 0f SECT 01 0000 [.text] _Cail_Tahiti_UpdateVceInternalClockGating 0000000000114142 g 0f SECT 01 0000 [.text] _Cail_Tahiti_UvdInit 0000000000114bcc g 0f SECT 01 0000 [.text] _Cail_Tahiti_UvdSuspend 0000000000112d0a g 0f SECT 01 0000 [.text] _Cail_Tahiti_VPURecoveryBegin 00000000001137c8 g 0f SECT 01 0000 [.text] _Cail_Tahiti_VPURecoveryEnd 0000000000115191 g 0f SECT 01 0000 [.text] _Cail_Tahiti_VceFirmwareValidation 00000000001152e5 g 0f SECT 01 0000 [.text] _Cail_Tahiti_VceInit 0000000000115c2c g 0f SECT 01 0000 [.text] _Cail_Tahiti_VceSuspend 0000000000116029 g 0f SECT 01 0000 [.text] _Cail_Tahiti_WaitForDmaEngineIdle 00000000001127dc g 0f SECT 01 0000 [.text] _Cail_Tahiti_WaitForIdle 0000000000111af4 g 0f SECT 01 0000 [.text] _Cail_Tahiti_WaitForMCIdle_Setup 00000000001124b0 g 0f SECT 01 0000 [.text] _Cail_Tahiti_halt_rlc 0000000000112658 g 0f SECT 01 0000 [.text] _Cail_Tahiti_program_PCIE_Gen3 00000000001125c4 g 0f SECT 01 0000 [.text] _Cail_Tahiti_unhalt_rlc 000000000011e572 g 0f SECT 01 0000 [.text] _Cail_Tonga_CheckAsicDowngradeInfo 0000000000119a5c g 0f SECT 01 0000 [.text] _Cail_Tonga_InitFunctionPointer 000000000011e65b g 0f SECT 01 0000 [.text] _Cail_Tonga_InitRlcSaveRestoreList 000000000011e2ee g 0f SECT 01 0000 [.text] _Cail_Tonga_InitUvdClockGating 000000000011e48d g 0f SECT 01 0000 [.text] _Cail_Tonga_InitVceClockGating 00000000000ebfba g 0f SECT 01 0000 [.text] _Cail_UpdateAsicInfBeforeQueried 00000000000f04cb g 0f SECT 01 0000 [.text] _Cail_ValidateEasf 000000000010f619 g 0f SECT 01 0000 [.text] _Cail_ValidateLinkStatus 000000000010ed70 g 0f SECT 01 0000 [.text] _Cail_WaitFor 000000000010e891 g 0f SECT 01 0000 [.text] _Cail_WaitForMCIdle_Internal 00000000000e63a8 g 0f SECT 01 0000 [.text] _Cail_WriteAndReadI2C 00000000000efcf1 g 0f SECT 01 0000 [.text] _CalcClksClkv 00000000000efd73 g 0f SECT 01 0000 [.text] _CalcUPllClksClkv 00000000000efae2 g 0f SECT 01 0000 [.text] _CalcUpllDividers 00000000000efd9e g 0f SECT 01 0000 [.text] _CalcVcePllClksClkv 00000000000efe8a g 0f SECT 01 0000 [.text] _CalcVcepllDividers 000000000052c790 g 0f SECT 09 0000 [.data] _CallTable 00000000001210ce g 0f SECT 01 0000 [.text] _CallerDebugFunc 00000000003e3250 g 0f SECT 09 0000 [.data] _CapeVerdeFeatureSupport1 00000000003e6f40 g 0f SECT 09 0000 [.data] _CarrizoFeatureSupport1 00000000000fc6fb g 0f SECT 01 0000 [.text] _Carrizo_set_cpg_door_bell 000000000043b8a0 g 0f SECT 09 0000 [.data] _CaymanAddrConfigMask 000000000043d320 g 0f SECT 09 0000 [.data] _CaymanAsicStateRegInfo 000000000043d330 g 0f SECT 09 0000 [.data] _CaymanEngineRunningStateRegInfo 000000000043d7f0 g 0f SECT 09 0000 [.data] _CaymanHarvestRemapTbl 000000000043d090 g 0f SECT 09 0000 [.data] _Cayman_RLC 00000000000fef4b g 0f SECT 01 0000 [.text] _Cayman_restore_display 00000000000fe925 g 0f SECT 01 0000 [.text] _Cayman_save_display 00000000000ef7de g 0f SECT 01 0000 [.text] _CheckAPUForDualGraphicsBrandingSupport 000000000010e300 g 0f SECT 01 0000 [.text] _CheckForStereoConnector 000000000012292c g 0f SECT 01 0000 [.text] _CiBuffer_GetBuffer 000000000012286e g 0f SECT 01 0000 [.text] _CiBuffer_GetBufferSize 00000000000f9b09 g 0f SECT 01 0000 [.text] _ClearMemory 000000000012044a g 0f SECT 01 0000 [.text] _CommonDestinationDataTransformation 0000000000120497 g 0f SECT 01 0000 [.text] _CommonOperationDataTransformation 0000000000120408 g 0f SECT 01 0000 [.text] _CommonSourceDataTransformation 00000000000f86c8 g 0f SECT 01 0000 [.text] _ConvertFbOffsetToMcAddr 00000000000f872b g 0f SECT 01 0000 [.text] _ConvertMcAddrToFbOffset 00000000000edbb1 g 0f SECT 01 0000 [.text] _CopyDDI_CAPS 00000000000ece63 g 0f SECT 01 0000 [.text] _CopyFbToFbViaCpDma 00000000000ece16 g 0f SECT 01 0000 [.text] _CopyFbToRegisterViaCpDma 00000000000eccf6 g 0f SECT 01 0000 [.text] _CopyMcToMc 00000000000ecbc6 g 0f SECT 01 0000 [.text] _CopyVirtualToMc 00000000000f9eb5 g 0f SECT 01 0000 [.text] _CreateValidBitFieldMask 00000000003e1a10 g 0f SECT 09 0000 [.data] _CrossFireGroupTbl 00000000003e2210 g 0f SECT 09 0000 [.data] _CrossFireXDMAGroupTbl 000000000043de00 g 0f SECT 09 0000 [.data] _CypressAddrConfigMask 000000000043f358 g 0f SECT 09 0000 [.data] _CypressAsicStateRegInfo 000000000043f370 g 0f SECT 09 0000 [.data] _CypressEngineRunningStateRegInfo 0000000000440980 g 0f SECT 09 0000 [.data] _CypressHarvestRemapTbl 0000000000103d35 g 0f SECT 01 0000 [.text] _Cypress_LinkResetWorkaround 000000000043f1c0 g 0f SECT 09 0000 [.data] _Cypress_RLC 0000000000121360 g 0f SECT 01 0000 [.text] _DBGGetMask 0000000000121318 g 0f SECT 01 0000 [.text] _DBGMemoryCopy 0000000000121348 g 0f SECT 01 0000 [.text] _DBGReadReg 0000000000121330 g 0f SECT 01 0000 [.text] _DBGWriteReg 0000000000441b18 g 0f SECT 09 0000 [.data] _DEVASTATOR_GoldenSettings_A0 00000000001224d1 g 0f SECT 01 0000 [.text] _DebugTrigerFunction 00000000001210b4 g 0f SECT 01 0000 [.text] _DelayMicroseconds 000000000012109c g 0f SECT 01 0000 [.text] _DelayMilliseconds 000000000052c728 g 0f SECT 09 0000 [.data] _DestinationAlignmentShift 00000000004415d0 g 0f SECT 09 0000 [.data] _DevastatorEngineRunningStateRegInfo 00000000000ebf89 g 0f SECT 01 0000 [.text] _DisableUVDSupportCap 00000000000f27dd g 0f SECT 01 0000 [.text] _DummyCailAsicState 00000000000f2c09 g 0f SECT 01 0000 [.text] _DummyCailCalculateVirtualizationReservedOffset 00000000000f29a7 g 0f SECT 01 0000 [.text] _DummyCailCfCheckAsicCfg 00000000000f299c g 0f SECT 01 0000 [.text] _DummyCailCfCloseTemporaryMailBox 00000000000f2b11 g 0f SECT 01 0000 [.text] _DummyCailCfEnableMailbox 00000000000f29af g 0f SECT 01 0000 [.text] _DummyCailCfGetP2PFlushCommand 00000000000f2965 g 0f SECT 01 0000 [.text] _DummyCailCfInitPeerAperture 00000000000f297b g 0f SECT 01 0000 [.text] _DummyCailCfInitXdmaAperture 00000000000f2991 g 0f SECT 01 0000 [.text] _DummyCailCfOpenTemporaryMailBox 00000000000f29ba g 0f SECT 01 0000 [.text] _DummyCailCfResyncPeerApertureInternalState 00000000000f2970 g 0f SECT 01 0000 [.text] _DummyCailCfSetPeerApertureDefault 00000000000f2986 g 0f SECT 01 0000 [.text] _DummyCailCfSetXdmaApertureDefault 00000000000f2b2f g 0f SECT 01 0000 [.text] _DummyCailCfSetupMemoryClientGroup 00000000000f2b29 g 0f SECT 01 0000 [.text] _DummyCailCfSetupP2pBarCfg 00000000000f2b1d g 0f SECT 01 0000 [.text] _DummyCailCfSetupPeerApertureMcAddr 00000000000f2b17 g 0f SECT 01 0000 [.text] _DummyCailCfSetupPeerDataAperture 00000000000f2b23 g 0f SECT 01 0000 [.text] _DummyCailCfSetupPeerSystemBar 00000000000f2b0b g 0f SECT 01 0000 [.text] _DummyCailCheckAcpHarvested 00000000000f2abf g 0f SECT 01 0000 [.text] _DummyCailCheckAsicBlockState 00000000000f2a43 g 0f SECT 01 0000 [.text] _DummyCailCheckDsmuSupport 00000000000f2786 g 0f SECT 01 0000 [.text] _DummyCailCheckFireGL 00000000000f2780 g 0f SECT 01 0000 [.text] _DummyCailCheckMemoryConfiguration 00000000000f2bd6 g 0f SECT 01 0000 [.text] _DummyCailCheckPcieAspmSupport 00000000000f2bd0 g 0f SECT 01 0000 [.text] _DummyCailCheckPcieLinkUpconfigSupport 00000000000f2a5b g 0f SECT 01 0000 [.text] _DummyCailClearFbMemory 00000000000f29db g 0f SECT 01 0000 [.text] _DummyCailClockGatingControl 00000000000f2be4 g 0f SECT 01 0000 [.text] _DummyCailCsQueryMetaDataRegList 00000000000f2bdc g 0f SECT 01 0000 [.text] _DummyCailCsQueryRegWriteList 00000000000f27b2 g 0f SECT 01 0000 [.text] _DummyCailDetectEccSupport 00000000000f2c03 g 0f SECT 01 0000 [.text] _DummyCailDetectHwVirtualization 00000000000f2b41 g 0f SECT 01 0000 [.text] _DummyCailDisableCpIdleInterrupt 00000000000f2a4f g 0f SECT 01 0000 [.text] _DummyCailDisableCpInterrupt 00000000000f2af7 g 0f SECT 01 0000 [.text] _DummyCailDisableFbMemAccess 00000000000f2b4d g 0f SECT 01 0000 [.text] _DummyCailDisableUvdMediumGrainClockGating 00000000000f2b7d g 0f SECT 01 0000 [.text] _DummyCailDoorbellApertureControl 00000000000f2a55 g 0f SECT 01 0000 [.text] _DummyCailEnableCpInterrupt 00000000000f2afd g 0f SECT 01 0000 [.text] _DummyCailEnableFbMemAccess 00000000000f29eb g 0f SECT 01 0000 [.text] _DummyCailEnableLbpw 00000000000f2b53 g 0f SECT 01 0000 [.text] _DummyCailEnableUvdMediumGrainClockGating 00000000000f2ac5 g 0f SECT 01 0000 [.text] _DummyCailEncodeBlocksForReset 00000000000f2bec g 0f SECT 01 0000 [.text] _DummyCailEnterRlcSafeMode 00000000000f29f3 g 0f SECT 01 0000 [.text] _DummyCailEventNotification 00000000000f2943 g 0f SECT 01 0000 [.text] _DummyCailExecuteDmaCopy 00000000000f2bf2 g 0f SECT 01 0000 [.text] _DummyCailExitRlcSafeMode 00000000000f2c12 g 0f SECT 01 0000 [.text] _DummyCailFillMetaData 00000000000f274c g 0f SECT 01 0000 [.text] _DummyCailFindAsicRevisionID 00000000000f2a06 g 0f SECT 01 0000 [.text] _DummyCailFormatSmuDramDataBuffer 00000000000f2ae4 g 0f SECT 01 0000 [.text] _DummyCailFunctionLevelReset 00000000000f29c5 g 0f SECT 01 0000 [.text] _DummyCailGetDoutScratch3 00000000000f2c1a g 0f SECT 01 0000 [.text] _DummyCailGetFbMcBaseAddress 00000000000f279c g 0f SECT 01 0000 [.text] _DummyCailGetFbMemorySize 00000000000f27d5 g 0f SECT 01 0000 [.text] _DummyCailGetGbMacroTileMode 00000000000f27cd g 0f SECT 01 0000 [.text] _DummyCailGetGbTileMode 00000000000f2bf8 g 0f SECT 01 0000 [.text] _DummyCailGetHungBlocks 00000000000f2a0e g 0f SECT 01 0000 [.text] _DummyCailGetIndRegPcie 00000000000f2754 g 0f SECT 01 0000 [.text] _DummyCailGetIndRegSmc 00000000000f293b g 0f SECT 01 0000 [.text] _DummyCailGetMaxDmaCopyLengthBytes 00000000000f2bbc g 0f SECT 01 0000 [.text] _DummyCailGetPaScRasterConfig 00000000000f2762 g 0f SECT 01 0000 [.text] _DummyCailGetPcieLinkSpeedSupport 00000000000f29d5 g 0f SECT 01 0000 [.text] _DummyCailGetPowerControlRegisterTable 00000000000f29cd g 0f SECT 01 0000 [.text] _DummyCailGetRlcSaveRestoreRegisterListInfo 00000000000f2a38 g 0f SECT 01 0000 [.text] _DummyCailGpioReadPin 00000000000f291a g 0f SECT 01 0000 [.text] _DummyCailHdpHideReservedBlock 00000000000f2925 g 0f SECT 01 0000 [.text] _DummyCailHdpUnhideReservedBlock 00000000000f2aaf g 0f SECT 01 0000 [.text] _DummyCailInitAcpClocks 00000000000f2b71 g 0f SECT 01 0000 [.text] _DummyCailInitCSBHeader 00000000000f27bd g 0f SECT 01 0000 [.text] _DummyCailInitEcc 00000000000f2b77 g 0f SECT 01 0000 [.text] _DummyCailInitMasterPacketHeader 00000000000f2a87 g 0f SECT 01 0000 [.text] _DummyCailInitNonsurfAperture 00000000000f2ab7 g 0f SECT 01 0000 [.text] _DummyCailInitSamuClocks 00000000000f2a9f g 0f SECT 01 0000 [.text] _DummyCailInitUvdClocks 00000000000f2aa7 g 0f SECT 01 0000 [.text] _DummyCailInitVceClocks 00000000000f27a7 g 0f SECT 01 0000 [.text] _DummyCailIntegratedAsicFbMcBaseAddr 00000000000f27f9 g 0f SECT 01 0000 [.text] _DummyCailIsDisplayBlockHung 00000000000f27c5 g 0f SECT 01 0000 [.text] _DummyCailIsFlrStrapped 00000000000f2859 g 0f SECT 01 0000 [.text] _DummyCailIsGuiIdle 00000000000f284b g 0f SECT 01 0000 [.text] _DummyCailIsNonEngineChipHung 00000000000f28bc g 0f SECT 01 0000 [.text] _DummyCailIsUvdIdle 00000000000f28e8 g 0f SECT 01 0000 [.text] _DummyCailIsVceIdle 00000000000f2b9d g 0f SECT 01 0000 [.text] _DummyCailLoadRlcUcode 00000000000f2b6b g 0f SECT 01 0000 [.text] _DummyCailLoadUcode 00000000000f2b03 g 0f SECT 01 0000 [.text] _DummyCailLocalHaltRlc 00000000000f2796 g 0f SECT 01 0000 [.text] _DummyCailMemoryConfigAndSize 00000000000f29fe g 0f SECT 01 0000 [.text] _DummyCailMicroEngineControl 00000000000f2b85 g 0f SECT 01 0000 [.text] _DummyCailMicroEngineControlCp 00000000000f2b8d g 0f SECT 01 0000 [.text] _DummyCailMicroEngineControlMec 00000000000f2b95 g 0f SECT 01 0000 [.text] _DummyCailMicroEngineControlSdma 00000000000f281f g 0f SECT 01 0000 [.text] _DummyCailMonitorEngineInternalState 00000000000f282d g 0f SECT 01 0000 [.text] _DummyCailMonitorPerformanceCounter 00000000000f2772 g 0f SECT 01 0000 [.text] _DummyCailPcieLaneSwitch 00000000000f2b5f g 0f SECT 01 0000 [.text] _DummyCailPostLiteReset 00000000000f2734 g 0f SECT 01 0000 [.text] _DummyCailPowerDown 00000000000f29e3 g 0f SECT 01 0000 [.text] _DummyCailPowerGatingControl 00000000000f2b65 g 0f SECT 01 0000 [.text] _DummyCailPreLiteReset 00000000000f2a97 g 0f SECT 01 0000 [.text] _DummyCailProgramAspm 00000000000f2a8f g 0f SECT 01 0000 [.text] _DummyCailProgramPcieGen3 00000000000f276a g 0f SECT 01 0000 [.text] _DummyCailProgramPcieLinkWidth 00000000000f2bb1 g 0f SECT 01 0000 [.text] _DummyCailQueryCuReservationRegisterInfo 00000000000f2843 g 0f SECT 01 0000 [.text] _DummyCailQueryEngineGroupDetails 00000000000f2801 g 0f SECT 01 0000 [.text] _DummyCailQueryGuiStatus 00000000000f2aef g 0f SECT 01 0000 [.text] _DummyCailRaiseSamuResetInterrupt 00000000000f2a2a g 0f SECT 01 0000 [.text] _DummyCailReadMmPciConfigRegister 00000000000f2957 g 0f SECT 01 0000 [.text] _DummyCailReadSamIndirectRegister 00000000000f2949 g 0f SECT 01 0000 [.text] _DummyCailReadSamSabIndirectRegister 00000000000f2a1c g 0f SECT 01 0000 [.text] _DummyCailReserveIgpuFbMcRange 00000000000f283b g 0f SECT 01 0000 [.text] _DummyCailResetEngine 00000000000f2a61 g 0f SECT 01 0000 [.text] _DummyCailResetRlc 00000000000f2744 g 0f SECT 01 0000 [.text] _DummyCailRestoreAdapterCfgRegisters 00000000000f2914 g 0f SECT 01 0000 [.text] _DummyCailSamuCheckDebugBoard 00000000000f28f3 g 0f SECT 01 0000 [.text] _DummyCailSamuInit 00000000000f2909 g 0f SECT 01 0000 [.text] _DummyCailSamuSetClk 00000000000f2acd g 0f SECT 01 0000 [.text] _DummyCailSamuSrbmSoftReset 00000000000f28fe g 0f SECT 01 0000 [.text] _DummyCailSamuSuspend 00000000000f2a24 g 0f SECT 01 0000 [.text] _DummyCailSelectSeSh 00000000000f2a16 g 0f SECT 01 0000 [.text] _DummyCailSetIndRegPcie 00000000000f275c g 0f SECT 01 0000 [.text] _DummyCailSetIndRegSmc 00000000000f2a49 g 0f SECT 01 0000 [.text] _DummyCailSetSmuDfsBypassMode 00000000000f28a6 g 0f SECT 01 0000 [.text] _DummyCailSetUvdVclkDclk 00000000000f28dd g 0f SECT 01 0000 [.text] _DummyCailSetVceEvclkEcclk 00000000000f273c g 0f SECT 01 0000 [.text] _DummyCailSetupAsic 00000000000f278e g 0f SECT 01 0000 [.text] _DummyCailSetupCgReferenceClock 00000000000f28b1 g 0f SECT 01 0000 [.text] _DummyCailSetupUvdCacheWindowAndFwv 00000000000f2ad3 g 0f SECT 01 0000 [.text] _DummyCailSetupUvdCacheWindows 00000000000f2ad9 g 0f SECT 01 0000 [.text] _DummyCailSoftResetMethod 00000000000f2bc2 g 0f SECT 01 0000 [.text] _DummyCailSwitchMcConfigContext 00000000000f2811 g 0f SECT 01 0000 [.text] _DummyCailTdrBegin 00000000000f2819 g 0f SECT 01 0000 [.text] _DummyCailTdrEnd 00000000000f2bc8 g 0f SECT 01 0000 [.text] _DummyCailUpdateAsicConfigRegisters 00000000000f2b3b g 0f SECT 01 0000 [.text] _DummyCailUpdateCoarseGrainClockGating 00000000000f2a69 g 0f SECT 01 0000 [.text] _DummyCailUpdateGfxClockGating 00000000000f2b47 g 0f SECT 01 0000 [.text] _DummyCailUpdateMediumGrainClockGating 00000000000f2a75 g 0f SECT 01 0000 [.text] _DummyCailUpdateMultimediaClockGating 00000000000f2bab g 0f SECT 01 0000 [.text] _DummyCailUpdateSamuLightSleep 00000000000f2ba5 g 0f SECT 01 0000 [.text] _DummyCailUpdateSamuSwClockGating 00000000000f277a g 0f SECT 01 0000 [.text] _DummyCailUpdateSwConstantForHwConfig 00000000000f2a6f g 0f SECT 01 0000 [.text] _DummyCailUpdateSystemClockGating 00000000000f2a7b g 0f SECT 01 0000 [.text] _DummyCailUpdateVceClockGating 00000000000f2a81 g 0f SECT 01 0000 [.text] _DummyCailUpdateVceLightSleep 00000000000f2b59 g 0f SECT 01 0000 [.text] _DummyCailUpdateXdmaSclkGating 00000000000f2890 g 0f SECT 01 0000 [.text] _DummyCailUvdInit 00000000000f289b g 0f SECT 01 0000 [.text] _DummyCailUvdSuspend 00000000000f28c7 g 0f SECT 01 0000 [.text] _DummyCailVceInit 00000000000f28d2 g 0f SECT 01 0000 [.text] _DummyCailVceSuspend 00000000000f2930 g 0f SECT 01 0000 [.text] _DummyCailWaitForDmaEngineIdle 00000000000f27e3 g 0f SECT 01 0000 [.text] _DummyCailWaitForIdle 00000000000f2864 g 0f SECT 01 0000 [.text] _DummyCailWaitForIdleCp 00000000000f27ee g 0f SECT 01 0000 [.text] _DummyCailWaitForIdleGui 00000000000f2885 g 0f SECT 01 0000 [.text] _DummyCailWaitForIdleSdma 00000000000f287a g 0f SECT 01 0000 [.text] _DummyCailWaitForIdleUvd 00000000000f286f g 0f SECT 01 0000 [.text] _DummyCailWaitForIdleVce 00000000000f2809 g 0f SECT 01 0000 [.text] _DummyCailWaitForMcIdleSetup 00000000000f2a32 g 0f SECT 01 0000 [.text] _DummyCailWriteMmPciConfigRegister 00000000000f295f g 0f SECT 01 0000 [.text] _DummyCailWriteSamIndirectRegister 00000000000f2951 g 0f SECT 01 0000 [.text] _DummyCailWriteSamSabIndirectRegister 00000000000f2b35 g 0f SECT 01 0000 [.text] _DummyCailZeroFbConfigAndSize 00000000000cd326 g 0f SECT 01 0000 [.text] _ElemFlt32ToColorPixel 00000000000cd2f3 g 0f SECT 01 0000 [.text] _ElemFlt32ToDepthPixel 00000000000cd359 g 0f SECT 01 0000 [.text] _ElemGetExportNorm 00000000004409d0 g 0f SECT 09 0000 [.data] _EnableElectricalIdleDetectorNonReversedRegTbl 0000000000440e80 g 0f SECT 09 0000 [.data] _EnableElectricalIdleDetectorReversedRegTbl 00000000000eb378 g 0f SECT 01 0000 [.text] _EnableViaAGPReadSyn 00000000000edc95 g 0f SECT 01 0000 [.text] _FillCAPTblInfo_In_CAIL_ADAPTER_INFO 00000000000f9ec9 g 0f SECT 01 0000 [.text] _FindASICSerialNumberFromString 00000000000f8688 g 0f SECT 01 0000 [.text] _FindMemTypeByMCAddress 0000000000444540 g 0f SECT 09 0000 [.data] _GODAVARI_GoldenSettings_A0_2411 00000000000f004c g 0f SECT 01 0000 [.text] _GetAcpClkDefault 00000000000ee237 g 0f SECT 01 0000 [.text] _GetActualClockGatingSupportFlags 00000000000ee143 g 0f SECT 01 0000 [.text] _GetActualPowerGatingSupportFlags 00000000000ee3d2 g 0f SECT 01 0000 [.text] _GetActualSpuRevision 000000000010e9c9 g 0f SECT 01 0000 [.text] _GetAsicName 00000000000ee0a8 g 0f SECT 01 0000 [.text] _GetAsicPcieLinkSpeedSupport 0000000000120356 g 0f SECT 01 0000 [.text] _GetByteDestIndex 0000000000120363 g 0f SECT 01 0000 [.text] _GetByteSrcIndex 00000000000ef437 g 0f SECT 01 0000 [.text] _GetCfGroupId 00000000000eed0a g 0f SECT 01 0000 [.text] _GetCfLbType 00000000000ef511 g 0f SECT 01 0000 [.text] _GetCfMemoryClientGroup 00000000000ef575 g 0f SECT 01 0000 [.text] _GetCfMemoryClientMailBox 00000000000ef48b g 0f SECT 01 0000 [.text] _GetCfP2PBarNumber 00000000000eed45 g 0f SECT 01 0000 [.text] _GetCfPeerBusNoBitmap 00000000000eeda5 g 0f SECT 01 0000 [.text] _GetCfPeerDeviceNoBitmap 00000000000eee19 g 0f SECT 01 0000 [.text] _GetCfPeerGupIdBitmap 00000000000ee682 g 0f SECT 01 0000 [.text] _GetCfPeerMcBaseAddr 00000000000eecef g 0f SECT 01 0000 [.text] _GetCfPeerVirtualIndex 00000000000ef536 g 0f SECT 01 0000 [.text] _GetCfWriteCombineNumber 00000000000ee997 g 0f SECT 01 0000 [.text] _GetCfXdmaPeerMcBaseAddr 000000000011fabf g 0f SECT 01 0000 [.text] _GetCommandMasterTablePointer 00000000001203d2 g 0f SECT 01 0000 [.text] _GetDWordSrcIndex 000000000011fae5 g 0f SECT 01 0000 [.text] _GetDataMasterTablePointer 00000000000f9e76 g 0f SECT 01 0000 [.text] _GetDeltaAfterAlignment 000000000052c660 g 0f SECT 09 0000 [.data] _GetDestination 00000000000edb1e g 0f SECT 01 0000 [.text] _GetEngineRunningStateRegInfoList 00000000000efdc9 g 0f SECT 01 0000 [.text] _GetEvclkEcclkDefault 00000000000f0010 g 0f SECT 01 0000 [.text] _GetEvclkEcclkInfo 000000000010eaf9 g 0f SECT 01 0000 [.text] _GetFakeAsicName 00000000000f879b g 0f SECT 01 0000 [.text] _GetFbMcBaseAddress 00000000000eb027 g 0f SECT 01 0000 [.text] _GetFbMemorySize 00000000000eda5f g 0f SECT 01 0000 [.text] _GetGpuGoldenSettings 00000000000eda79 g 0f SECT 01 0000 [.text] _GetGpuHwConstants 00000000000edac7 g 0f SECT 01 0000 [.text] _GetGpuMacroTileModeTbl 00000000000edaf5 g 0f SECT 01 0000 [.text] _GetGpuStateRegisterListInfo 00000000000eda99 g 0f SECT 01 0000 [.text] _GetGpuTileModeTbl 00000000000ec0b9 g 0f SECT 01 0000 [.text] _GetIntegrateAsicFbMcBaseAddr 00000000000f9e07 g 0f SECT 01 0000 [.text] _GetLog2 00000000000f7fd4 g 0f SECT 01 0000 [.text] _GetMCAddressRange 00000000000f8a64 g 0f SECT 01 0000 [.text] _GetMemoryChannelNumber 0000000000121f5b g 0f SECT 01 0000 [.text] _GetMemoryLocation 00000000000f9fa9 g 0f SECT 01 0000 [.text] _GetOnBitNumberInDword 0000000000120139 g 0f SECT 01 0000 [.text] _GetParametersDirect 000000000011fda4 g 0f SECT 01 0000 [.text] _GetParametersDirect16 000000000011fd88 g 0f SECT 01 0000 [.text] _GetParametersDirect32 000000000011fdc0 g 0f SECT 01 0000 [.text] _GetParametersDirect8 000000000052c5f0 g 0f SECT 09 0000 [.data] _GetParametersDirectArray 000000000012007c g 0f SECT 01 0000 [.text] _GetParametersFB 0000000000120113 g 0f SECT 01 0000 [.text] _GetParametersIndirect 00000000001200bd g 0f SECT 01 0000 [.text] _GetParametersMC 00000000001200a1 g 0f SECT 01 0000 [.text] _GetParametersPLL 000000000011ffb9 g 0f SECT 01 0000 [.text] _GetParametersPS 000000000011ff43 g 0f SECT 01 0000 [.text] _GetParametersRegister 000000000011ffda g 0f SECT 01 0000 [.text] _GetParametersWS 00000000000f18fe g 0f SECT 01 0000 [.text] _GetReservedBlockBaseOffset 00000000000f1f27 g 0f SECT 01 0000 [.text] _GetReservedFbBlock 00000000000efe73 g 0f SECT 01 0000 [.text] _GetSamclkDefault 000000000052c6c0 g 0f SECT 09 0000 [.data] _GetSource 00000000000f9c67 g 0f SECT 01 0000 [.text] _GetStringLength 000000000011fafd g 0f SECT 01 0000 [.text] _GetTrueIndexInMasterTable 00000000000efc55 g 0f SECT 01 0000 [.text] _GetUpllLockTime 00000000000efffd g 0f SECT 01 0000 [.text] _GetVcepllLockTime 00000000000efa38 g 0f SECT 01 0000 [.text] _GetVclkDclkDefault 00000000000efc68 g 0f SECT 01 0000 [.text] _GetVclkDclkInfo 000000000012039a g 0f SECT 01 0000 [.text] _GetWordSrcIndex 00000000004478d0 g 0f SECT 09 0000 [.data] _HAINAN_GoldenSettings_A0 000000000044ade8 g 0f SECT 09 0000 [.data] _HAWAII_GoldenSettings_A0 00000000004473a0 g 0f SECT 09 0000 [.data] _HainanFeatureSupport1 00000000004499b0 g 0f SECT 09 0000 [.data] _HawaiiFeatureSupport1 000000000044ae00 g 0f SECT 09 0000 [.data] _HawaiiRbRepaireRemappingTbl_SE0_1 000000000044ae40 g 0f SECT 09 0000 [.data] _HawaiiRbRepaireRemappingTbl_SE2_3 000000000045a4f8 g 0f SECT 09 0000 [.data] _ICELAND_GoldenSettings_A0 0000000000459d60 g 0f SECT 09 0000 [.data] _IcelandAsicStateRegInfo 0000000000459d70 g 0f SECT 09 0000 [.data] _IcelandEngineRunningStateRegInfo 0000000000459a90 g 0f SECT 09 0000 [.data] _IcelandFeatureSupport1 00000000004599b0 g 0f SECT 09 0000 [.data] _IcelandMicroEngineRegisters 0000000000120153 g 0f SECT 01 0000 [.text] _IndirectIOCommand 0000000000120159 g 0f SECT 01 0000 [.text] _IndirectIOCommand_CLEAR 00000000001201fe g 0f SECT 01 0000 [.text] _IndirectIOCommand_MOVE_ATTR 000000000012025a g 0f SECT 01 0000 [.text] _IndirectIOCommand_MOVE_DATA 00000000001201a3 g 0f SECT 01 0000 [.text] _IndirectIOCommand_MOVE_INDEX 000000000012017f g 0f SECT 01 0000 [.text] _IndirectIOCommand_SET 000000000052c730 g 0f SECT 09 0000 [.data] _IndirectIOParserCommands 00000000001202b5 g 0f SECT 01 0000 [.text] _IndirectInputOutput 00000000000ed88c g 0f SECT 01 0000 [.text] _InitializeCapTblManager 00000000000f1c17 g 0f SECT 01 0000 [.text] _InitializeRlcClearStateBuffer 00000000000f1960 g 0f SECT 01 0000 [.text] _InitializeRlcHistoryBuffer 00000000001232c5 g 0f SECT 01 0000 [.text] _InvMixColumns2 000000000010ea2f g 0f SECT 01 0000 [.text] _IsASICGenericName 00000000000ef46a g 0f SECT 01 0000 [.text] _IsCrossFireCapable 00000000000ebbc9 g 0f SECT 01 0000 [.text] _IsGuiIdle 00000000000ebd64 g 0f SECT 01 0000 [.text] _IsUVDIdle 00000000000ebdb2 g 0f SECT 01 0000 [.text] _IsVCEIdle 00000000000f1f9b g 0f SECT 01 0000 [.text] _IsVbiosReservedBlockUsedFor 00000000004aa240 g 0f SECT 09 0000 [.data] _JUNIPER_GoldenSettings_A11 00000000004aa978 g 0f SECT 09 0000 [.data] _JUNIPER_GoldenSettings_A12 00000000004aa990 g 0f SECT 09 0000 [.data] _JuniperHarvestRemapTbl 00000000004a9b00 g 0f SECT 09 0000 [.data] _Juniper_RLC 00000000004b7ee0 g 0f SECT 09 0000 [.data] _KALINDI_GoldenSettings_A0_4882 00000000004b7920 g 0f SECT 09 0000 [.data] _KalindiFeatureSupport1 00000000004b0e70 g 0f SECT 09 0000 [.data] _Kalindi_CE_UCODE 00000000004b71d0 g 0f SECT 09 0000 [.data] _Kalindi_MEC1_UCODE 00000000004b3020 g 0f SECT 09 0000 [.data] _Kalindi_ME_UCODE 00000000004aecc0 g 0f SECT 09 0000 [.data] _Kalindi_PFP_UCODE 00000000004aba88 g 0f SECT 09 0000 [.data] _Kalindi_SDMA0_UCODE 00000000004acb18 g 0f SECT 09 0000 [.data] _Kalindi_SDMA1_UCODE 00000000000f1fff g 0f SECT 01 0000 [.text] _LoadMicroEngineUcode 00000000004d3520 g 0f SECT 09 0000 [.data] _MAIL_BOX_TAHITI 00000000004d3b70 g 0f SECT 09 0000 [.data] _MC_XPB_CLG_CFGn_TAHITI 00000000004d3460 g 0f SECT 09 0000 [.data] _MEMORY_CLIENT_GROUP_TAHITI 00000000000f9e2a g 0f SECT 01 0000 [.text] _MemoryCopy 00000000003e2330 g 0f SECT 09 0000 [.data] _MobileAsicTbl 00000000000f97cd g 0f SECT 01 0000 [.text] _Nonregistered_Client_PowerControl 0000000000122252 g 0f SECT 01 0000 [.text] _NotSuportedRequest 00000000004bb2c8 g 0f SECT 09 0000 [.data] _OLAND_GoldenSettings_A0 00000000004bad50 g 0f SECT 09 0000 [.data] _OlandFeatureSupport1 00000000004d36a0 g 0f SECT 09 0000 [.data] _P2P_BAR_2_TAHITI 00000000004d3760 g 0f SECT 09 0000 [.data] _P2P_BAR_4_TAHITI 00000000004bdad0 g 0f SECT 09 0000 [.data] _PITCAIRN_GoldenSettings_A11 00000000004be100 g 0f SECT 09 0000 [.data] _PITCAIRN_GoldenSettings_A12 000000000012226c g 0f SECT 01 0000 [.text] _ParseRequest 000000000011fb45 g 0f SECT 01 0000 [.text] _ParseTable 00000000004bd480 g 0f SECT 09 0000 [.data] _PitcairnFeatureSupport1 00000000004be120 g 0f SECT 09 0000 [.data] _PitcairnRbRepaireRemappingTbl 00000000001210c8 g 0f SECT 01 0000 [.text] _PostCharOutput 00000000003e2ea0 g 0f SECT 09 0000 [.data] _PowerCtrlRegisterDefaultTbl 0000000000120902 g 0f SECT 01 0000 [.text] _ProcessADD 000000000012065a g 0f SECT 01 0000 [.text] _ProcessAnd 0000000000120b8f g 0f SECT 01 0000 [.text] _ProcessClear 000000000011f97f g 0f SECT 01 0000 [.text] _ProcessCommandProperties 0000000000120b0c g 0f SECT 01 0000 [.text] _ProcessCompare 0000000000120a8f g 0f SECT 01 0000 [.text] _ProcessDIV 0000000000120f6a g 0f SECT 01 0000 [.text] _ProcessDS 0000000000120f3d g 0f SECT 01 0000 [.text] _ProcessDebug 0000000000121007 g 0f SECT 01 0000 [.text] _ProcessJump 0000000000121037 g 0f SECT 01 0000 [.text] _ProcessJumpE 0000000000121067 g 0f SECT 01 0000 [.text] _ProcessJumpNE 0000000000120a18 g 0f SECT 01 0000 [.text] _ProcessMUL 000000000012058d g 0f SECT 01 0000 [.text] _ProcessMask 00000000001204dc g 0f SECT 01 0000 [.text] _ProcessMove 00000000001206e0 g 0f SECT 01 0000 [.text] _ProcessOr 0000000000120f10 g 0f SECT 01 0000 [.text] _ProcessPostChar 000000000012098d g 0f SECT 01 0000 [.text] _ProcessSUB 0000000000120cf0 g 0f SECT 01 0000 [.text] _ProcessSetFB_Base 0000000000120be1 g 0f SECT 01 0000 [.text] _ProcessShift 00000000001207e8 g 0f SECT 01 0000 [.text] _ProcessShl 0000000000120875 g 0f SECT 01 0000 [.text] _ProcessShr 0000000000120d34 g 0f SECT 01 0000 [.text] _ProcessSwitch 0000000000120c71 g 0f SECT 01 0000 [.text] _ProcessTest 0000000000120764 g 0f SECT 01 0000 [.text] _ProcessXor 000000000010e20c g 0f SECT 01 0000 [.text] _Program_AND_OR_Register 000000000010e1a7 g 0f SECT 01 0000 [.text] _Program_AND_Register 000000000010e1d7 g 0f SECT 01 0000 [.text] _Program_OR_And_Register 000000000010e177 g 0f SECT 01 0000 [.text] _Program_OR_Register 0000000000122200 g 0f SECT 01 0000 [.text] _ProvideVitalInfoRequest 000000000011ff08 g 0f SECT 01 0000 [.text] _PutDataFB 000000000052c630 g 0f SECT 09 0000 [.data] _PutDataFunctions 000000000011ff32 g 0f SECT 01 0000 [.text] _PutDataMC 000000000011ff21 g 0f SECT 01 0000 [.text] _PutDataPLL 000000000011fe58 g 0f SECT 01 0000 [.text] _PutDataPS 000000000011fddc g 0f SECT 01 0000 [.text] _PutDataRegister 000000000011fe6e g 0f SECT 01 0000 [.text] _PutDataWS 0000000000110258 g 0f SECT 01 0000 [.text] _QueryEngineGroupDetails 00000000000f8002 g 0f SECT 01 0000 [.text] _QueryMCAddressRange 00000000000f805a g 0f SECT 01 0000 [.text] _QueryMCAddressRangeInfo 00000000000f98ff g 0f SECT 01 0000 [.text] _QueryPowerControlRestoreAction 000000000010ee34 g 0f SECT 01 0000 [.text] _R6cail_ulWalkTable 00000000004c1580 g 0f SECT 09 0000 [.data] _REDWOOD_GoldenSettings_A11 00000000000db040 g 0f SECT 01 0000 [.text] _RadeonCheckAGPMaxIdlestatus 000000000010e408 g 0f SECT 01 0000 [.text] _RadeonCheckAdapterFireGLBoard 000000000010ee3c g 0f SECT 01 0000 [.text] _Radeoncail_GenerateDualGraphicsBrandingNameString 000000000010ed03 g 0f SECT 01 0000 [.text] _Radeoncail_GetAdapterString 000000000010eb73 g 0f SECT 01 0000 [.text] _Radeoncail_GetChipType 000000000010e997 g 0f SECT 01 0000 [.text] _Radeoncail_GetDeviceDescription 000000000012125c g 0f SECT 01 0000 [.text] _ReadFrameBuffer32 000000000052c5b0 g 0f SECT 09 0000 [.data] _ReadIOFunctions 000000000012219c g 0f SECT 01 0000 [.text] _ReadIORequest 000000000012120b g 0f SECT 01 0000 [.text] _ReadIndReg32 00000000001212c2 g 0f SECT 01 0000 [.text] _ReadMC32 000000000012209e g 0f SECT 01 0000 [.text] _ReadMemoryRequest 000000000052c570 g 0f SECT 09 0000 [.data] _ReadPCIFunctions 00000000001210fe g 0f SECT 01 0000 [.text] _ReadPCIReg16 0000000000121128 g 0f SECT 01 0000 [.text] _ReadPCIReg32 00000000001210d4 g 0f SECT 01 0000 [.text] _ReadPCIReg8 00000000001212ed g 0f SECT 01 0000 [.text] _ReadPLL32 0000000000121db6 g 0f SECT 01 0000 [.text] _ReadParserTempData 00000000001211db g 0f SECT 01 0000 [.text] _ReadReg32 000000000012124e g 0f SECT 01 0000 [.text] _ReadRegIO 00000000001211b9 g 0f SECT 01 0000 [.text] _ReadSysIOReg16 00000000001211c1 g 0f SECT 01 0000 [.text] _ReadSysIOReg32 00000000001211b1 g 0f SECT 01 0000 [.text] _ReadSysIOReg8 00000000004c0f80 g 0f SECT 09 0000 [.data] _Redwood_RLC 00000000000eda4c g 0f SECT 01 0000 [.text] _ReinitializeCapTblManager 00000000000f7c60 g 0f SECT 01 0000 [.text] _ReleaseMCAddressRange 00000000001212ad g 0f SECT 01 0000 [.text] _ReleaseMemory 0000000000122238 g 0f SECT 01 0000 [.text] _ReleaseRequest 00000000000ef5a0 g 0f SECT 01 0000 [.text] _RemapRenderBackend 00000000000f87ee g 0f SECT 01 0000 [.text] _ReserveFbMcAddressRange 00000000000f7d2a g 0f SECT 01 0000 [.text] _ReserveMCAddressRange 00000000000f1fd4 g 0f SECT 01 0000 [.text] _RestoreVbiosReservedBlockData 000000000052ecb0 g 0f SECT 0a 0000 [__DATA.__common] _RoundKey 0000000000442040 g 0f SECT 09 0000 [.data] _SCRAPPER_GoldenSettings_A0 0000000000094a7f g 0f SECT 01 0000 [.text] _SI_InitHwWorkAroundFlags 00000000004c1eb0 g 0f SECT 09 0000 [.data] _SPECTRE_GoldenSettings_A0_8812 0000000000125c41 g 0f SECT 01 0000 [.text] _SPUFWLib_GetKAPPImage 0000000000125c49 g 0f SECT 01 0000 [.text] _SPUFWLib_GetKernelImage 0000000000125c51 g 0f SECT 01 0000 [.text] _SPUFWLib_GetParameters 00000000003c6098 g 0f SECT 09 0000 [.data] _SQRT2 00000000004d2d80 g 0f SECT 09 0000 [.data] _SUMO_GoldenSettings_A11 00000000000f1fa9 g 0f SECT 01 0000 [.text] _SaveVbiosReservedBlockData 000000000010ed8d g 0f SECT 01 0000 [.text] _SetPostDividers 00000000000f1f81 g 0f SECT 01 0000 [.text] _SetVbiosReservedBlockFlag 00000000000eb3d2 g 0f SECT 01 0000 [.text] _SetViaReadWriteBurst 00000000000ec045 g 0f SECT 01 0000 [.text] _SetupActiveRbInformation 00000000000f17c0 g 0f SECT 01 0000 [.text] _SetupVbiosReservedBlockInfoForSaveRestore 00000000000dafb6 g 0f SECT 01 0000 [.text] _Setup_BUS_CNTL_CONFIG_CNTL 000000000012277d g 0f SECT 01 0000 [.text] _SiBuffer_GetBuffer 00000000001226cd g 0f SECT 01 0000 [.text] _SiBuffer_GetBufferSize 00000000004d5430 g 0f SECT 09 0000 [.data] _SiCpGfxResetRegisterSavingTbl 0000000000122d2e g 0f SECT 01 0000 [.text] _SiPacket_ClearState 0000000000122c7f g 0f SECT 01 0000 [.text] _SiPacket_ContextControl 0000000000122c20 g 0f SECT 01 0000 [.text] _SiPacket_PreambleCntl 0000000000122d0b g 0f SECT 01 0000 [.text] _SiPacket_SetOneContextReg 0000000000122cd9 g 0f SECT 01 0000 [.text] _SiPacket_SetSeqContextRegs 0000000000122d6f g 0f SECT 01 0000 [.text] _SiPacket_SizeClearState 0000000000122cce g 0f SECT 01 0000 [.text] _SiPacket_SizeContextControl 0000000000122c74 g 0f SECT 01 0000 [.text] _SiPacket_SizePreambleCntl 0000000000122d23 g 0f SECT 01 0000 [.text] _SiPacket_SizeSetOneContextReg 0000000000122d02 g 0f SECT 01 0000 [.text] _SiPacket_SizeSetSeqContextRegs 00000000004d53e0 g 0f SECT 09 0000 [.data] _SiTcpChanSteerLo 000000000052c690 g 0f SECT 09 0000 [.data] _SkipDestination 00000000001200d9 g 0f SECT 01 0000 [.text] _SkipParameters16 00000000001200f7 g 0f SECT 01 0000 [.text] _SkipParameters8 000000000052c720 g 0f SECT 09 0000 [.data] _SourceAlignmentShift 00000000004c1620 g 0f SECT 09 0000 [.data] _SpectreFeatureSupport1 0000000000110a9d g 0f SECT 01 0000 [.text] _Spectre_ResetEventNotificationManager 00000000000f9d85 g 0f SECT 01 0000 [.text] _StringCompare 00000000000f9d42 g 0f SECT 01 0000 [.text] _StringConcatenate 00000000000f9d0b g 0f SECT 01 0000 [.text] _StringCopy 00000000000f9db1 g 0f SECT 01 0000 [.text] _StringToUlong 00000000004d2d98 g 0f SECT 09 0000 [.data] _StrippedSUMO_GoldenSettings_A11 00000000004d3020 g 0f SECT 09 0000 [.data] _SumoHarvestRemapTbl 00000000004d25c0 g 0f SECT 09 0000 [.data] _Sumo_RLC 00000000004d29c0 g 0f SECT 09 0000 [.data] _SuperSUMO3Simd_GoldenSettings_A11 00000000004d29a8 g 0f SECT 09 0000 [.data] _SuperSUMO4Simd_GoldenSettings_A11 00000000004d2990 g 0f SECT 09 0000 [.data] _SuperSUMO_GoldenSettings_A11 00000000004d4bd8 g 0f SECT 09 0000 [.data] _TAHITI_GoldenSettings_A11 00000000004d53c8 g 0f SECT 09 0000 [.data] _TAHITI_GoldenSettings_A21 00000000004d8aa0 g 0f SECT 09 0000 [.data] _TONGA_GoldenSettings_A0 00000000004d8430 g 0f SECT 09 0000 [.data] _TONGA_GoldenSettings_A1 000000000052c470 g 0f SECT 09 0000 [.data] _TURKS_GoldenSettings_A11 00000000004d4130 g 0f SECT 09 0000 [.data] _TahitiAsicStateRegInfo 00000000004d4140 g 0f SECT 09 0000 [.data] _TahitiEngineRunningStateRegInfo 00000000004d43c0 g 0f SECT 09 0000 [.data] _TahitiFeatureSupport1 00000000004d7b48 g 0f SECT 09 0000 [.data] _TongaAsicStateRegInfo 00000000004d7b60 g 0f SECT 09 0000 [.data] _TongaEngineRunningStateRegInfo 00000000004d7800 g 0f SECT 09 0000 [.data] _TongaFeatureSupport1 00000000004d7740 g 0f SECT 09 0000 [.data] _TongaMicroEngineRegisters 000000000052c200 g 0f SECT 09 0000 [.data] _Turks_RLC 0000000000094e6e g 0f SECT 01 0000 [.text] _UBMAAResolve 0000000000094f3b g 0f SECT 01 0000 [.text] _UBMAATextOut 0000000000094e45 g 0f SECT 01 0000 [.text] _UBMClear 000000000009505a g 0f SECT 01 0000 [.text] _UBMClearStateInit 0000000000095031 g 0f SECT 01 0000 [.text] _UBMColorTransform 0000000000094ee9 g 0f SECT 01 0000 [.text] _UBMCompress 0000000000095071 g 0f SECT 01 0000 [.text] _UBMComputeStateInit 0000000000094bde g 0f SECT 01 0000 [.text] _UBMCreate 0000000000094fb6 g 0f SECT 01 0000 [.text] _UBMDesktopComposition 0000000000094d1f g 0f SECT 01 0000 [.text] _UBMDestroy 0000000000094d35 g 0f SECT 01 0000 [.text] _UBMDeviceCreate 0000000000094d62 g 0f SECT 01 0000 [.text] _UBMDeviceDestroy 0000000000094d4c g 0f SECT 01 0000 [.text] _UBMDeviceTrim 0000000000094ec0 g 0f SECT 01 0000 [.text] _UBMExpand 0000000000094d78 g 0f SECT 01 0000 [.text] _UBMGPULoadShaders 0000000000094dca g 0f SECT 01 0000 [.text] _UBMGenMips 0000000000094e1c g 0f SECT 01 0000 [.text] _UBMGenZRangeMip 0000000000094df3 g 0f SECT 01 0000 [.text] _UBMGenZRangeTex 0000000000094f12 g 0f SECT 01 0000 [.text] _UBMGradient 0000000000094f8d g 0f SECT 01 0000 [.text] _UBMMemcpy 0000000000094f64 g 0f SECT 01 0000 [.text] _UBMMemset 0000000000094e97 g 0f SECT 01 0000 [.text] _UBMMlaaResolve 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[.text] _WriteToFbOffsetByHdp 00000000000d59f8 g 0f SECT 01 0000 [.text] __Z13AddrCIHwlInitPK10AddrClient 00000000000d349c g 0f SECT 01 0000 [.text] __Z13AddrSIHwlInitPK10AddrClient 000000000009ffd4 g 0f SECT 01 0000 [.text] __Z14GetMonitorDesc22_UBM_PACKED_PIXEL_TYPE 00000000000d1a6c g 0f SECT 01 0000 [.text] __Z15AddrR800HwlInitPK10AddrClient 00000000000bc2d3 g 0f SECT 01 0000 [.text] __Z15SiBltResFmtInitv 0000000000025078 g 0f SECT 01 0000 [.text] __Z15klogSetLogLevel18_eLOG_LEVEL_MODULEj 00000000000a7660 g 0f SECT 01 0000 [.text] __Z17SurfAttributeInitv 0000000000025067 g 0f SECT 01 0000 [.text] __Z17klogFreeLogLevelsv 0000000000024f61 g 0f SECT 01 0000 [.text] __Z17klogInitLogLevelsP15IORegistryEntry 000000000002508a g 0f SECT 01 0000 [.text] __Z17klogUnsetLogLevel18_eLOG_LEVEL_MODULEj 00000000000cb244 g 0f SECT 01 0000 [.text] __Z19SiSurfAttributeInitv 00000000000b4694 g 0f SECT 01 0000 [.text] __Z9SiHwlInitv 00000000000cd65e g 0f SECT 01 0000 [.text] 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__ZN10AuxSurfMgr23HwlGenerateOffsetTexKeyEPK13_UBM_SURFINFO 0000000000095f26 g 0f SECT 01 0000 [.text] __ZN10AuxSurfMgr25GenerateHtileOffsetTexKeyEPK13_UBM_SURFINFOS2_ 0000000000096058 g 0f SECT 01 0000 [.text] __ZN10AuxSurfMgr26GenerateHtileMappingTexKeyEPK13_UBM_SURFINFOS2_ 0000000000095272 g 0f SECT 01 0000 [.text] __ZN10AuxSurfMgr4InitEP6BltMgr 0000000000096950 g 0f SECT 01 0000 [.text] __ZN10AuxSurfMgr9GrowArrayEPP13CachedAuxSurfPj 000000000009509e g 0f SECT 01 0000 [.text] __ZN10AuxSurfMgrC2Ev 000000000052e968 g 0f SECT 0a 0000 [__DATA.__common] __ZN11AMDVIHWGart10gMetaClassE 00000000003b9908 g 0f SECT 08 0000 [.const_data] __ZN11AMDVIHWGart10superClassE 00000000000872b2 g 0f SECT 01 0000 [.text] __ZN11AMDVIHWGart15updatePageTableEP18IOMemoryDescriptory15_eOP_ORIGINATOR9_eOP_TYPEbb 0000000000087120 g 0f SECT 01 0000 [.text] __ZN11AMDVIHWGart9MetaClassC1Ev 00000000000871e0 g 0f SECT 01 0000 [.text] __ZN11AMDVIHWGart9MetaClassC2Ev 00000000003b9900 g 0f SECT 08 0000 [.const_data] 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[.text] __ZN11SiBltDevice14WriteWriteDataEPv13LARGE_INTEGERPKjjjjjj 00000000000ac984 g 0f SECT 01 0000 [.text] __ZN11SiBltDevice15SetOneConfigRegEjj 00000000000adb08 g 0f SECT 01 0000 [.text] __ZN11SiBltDevice15WriteReleaseMemEPv13LARGE_INTEGERjj 00000000000b2082 g 0f SECT 01 0000 [.text] __ZN11SiBltDevice15WriteSdamNopCmdEv 00000000000b0c16 g 0f SECT 01 0000 [.text] __ZN11SiBltDevice15WriteSdmaKeyCmdEPKhS1_ 00000000000ad966 g 0f SECT 01 0000 [.text] __ZN11SiBltDevice15WriteWaitRegMemEPv13LARGE_INTEGERj 00000000000ade7c g 0f SECT 01 0000 [.text] __ZN11SiBltDevice16IsValidConfigRegEj 00000000000ae6c2 g 0f SECT 01 0000 [.text] __ZN11SiBltDevice16LoadShadowShRegsE13PM4ShaderType 00000000000adebe g 0f SECT 01 0000 [.text] __ZN11SiBltDevice16SetOneContextRegEjj 00000000000ac944 g 0f SECT 01 0000 [.text] __ZN11SiBltDevice16SetOneUConfigRegEjj 00000000000b0cee g 0f SECT 01 0000 [.text] __ZN11SiBltDevice16SizeDrmDmaKeyCmdEv 00000000000ae35c g 0f SECT 01 0000 [.text] __ZN11SiBltDevice16WriteCondExecCmdEPv13LARGE_INTEGERj 00000000000af200 g 0f SECT 01 0000 [.text] __ZN11SiBltDevice16WritePredExecCmdEjj 00000000000aec72 g 0f SECT 01 0000 [.text] __ZN11SiBltDevice16WriteSkipIfStartEPvjjj 00000000000adca8 g 0f SECT 01 0000 [.text] __ZN11SiBltDevice16WriteSurfaceSyncEPv13LARGE_INTEGER13CP_COHER_CNTLS1_ 00000000000ad518 g 0f SECT 01 0000 [.text] __ZN11SiBltDevice17Init3dDispatchBltEP7BltInfo 00000000000ade94 g 0f SECT 01 0000 [.text] __ZN11SiBltDevice17IsValidUConfigRegEj 00000000000adfa4 g 0f SECT 01 0000 [.text] __ZN11SiBltDevice17SetSeqContextRegsEjPKjj 00000000000ae42e g 0f SECT 01 0000 [.text] __ZN11SiBltDevice17WriteCondWriteCmdEPv13LARGE_INTEGERS1_jjjjjj 00000000000b0cfa g 0f SECT 01 0000 [.text] __ZN11SiBltDevice17WriteDrmDmaKeyCmdEPKhS1_ 00000000000ae996 g 0f SECT 01 0000 [.text] __ZN11SiBltDevice17WriteNumInstancesEj 00000000000ae8b0 g 0f SECT 01 0000 [.text] __ZN11SiBltDevice17WritePreambleCntlEj 00000000000ae7ee g 0f SECT 01 0000 [.text] __ZN11SiBltDevice18LoadUserConfigRegsEv 00000000000ae94c g 0f SECT 01 0000 [.text] __ZN11SiBltDevice18WriteClearStateCmdEv 00000000000ae29e g 0f SECT 01 0000 [.text] __ZN11SiBltDevice18WriteCondExecCmdCIEPv13LARGE_INTEGERj 00000000000b0e60 g 0f SECT 01 0000 [.text] __ZN11SiBltDevice18WriteSdmaOffsetCmdEj 00000000000b0eca g 0f SECT 01 0000 [.text] __ZN11SiBltDevice19SizeDrmDmaOffsetCmdEv 00000000000acac2 g 0f SECT 01 0000 [.text] __ZN11SiBltDevice19Write3dDrawPreambleEv 00000000000ac746 g 0f SECT 01 0000 [.text] __ZN11SiBltDevice19WriteCommonPreambleEv 00000000000aec0a g 0f SECT 01 0000 [.text] __ZN11SiBltDevice19WriteContextControlEjjjj 00000000000b0d7c g 0f SECT 01 0000 [.text] __ZN11SiBltDevice19WriteSdmaCounterCmdEPKh 00000000000b0df8 g 0f SECT 01 0000 [.text] __ZN11SiBltDevice20SizeDrmDmaCounterCmdEv 00000000000ae110 g 0f SECT 01 0000 [.text] __ZN11SiBltDevice20WriteDrawPreambleCmdE18VGT_PRIMITIVE_TYPE18IA_MULTI_VGT_PARAM 00000000000b0ed6 g 0f SECT 01 0000 [.text] __ZN11SiBltDevice20WriteDrmDmaOffsetCmdEj 00000000000b0f92 g 0f SECT 01 0000 [.text] __ZN11SiBltDevice20WriteSdmaCondExecCmdEPv13LARGE_INTEGERj 00000000000ac824 g 0f SECT 01 0000 [.text] __ZN11SiBltDevice21PreBltSynchronizationEPK7BltInfo 00000000000b1490 g 0f SECT 01 0000 [.text] __ZN11SiBltDevice21SetupCustomTileConfigEjj 00000000000b0f6a g 0f SECT 01 0000 [.text] __ZN11SiBltDevice21SizeDrmDmaCondExecCmdEv 00000000000aca34 g 0f SECT 01 0000 [.text] __ZN11SiBltDevice21WriteCustomTileConfigEv 00000000000ae194 g 0f SECT 01 0000 [.text] __ZN11SiBltDevice21WriteDrawIndexAutoCmdEj 00000000000b0e04 g 0f SECT 01 0000 [.text] __ZN11SiBltDevice21WriteDrmDmaCounterCmdEPKh 00000000000af934 g 0f SECT 01 0000 [.text] __ZN11SiBltDevice21WriteSdmaTiledCopyCmdEP13_UBM_SURFINFOjS1_13LARGE_INTEGERjj 00000000000af290 g 0f SECT 01 0000 [.text] __ZN11SiBltDevice22SizeDrmDmaTiledCopyCmdEv 00000000000ae212 g 0f SECT 01 0000 [.text] __ZN11SiBltDevice22WriteDispatchDirectCmdEjjj 00000000000b1118 g 0f SECT 01 0000 [.text] __ZN11SiBltDevice22WriteDrmDmaCondExecCmdEPv13LARGE_INTEGERj 00000000000ad544 g 0f SECT 01 0000 [.text] __ZN11SiBltDevice23Write3dDispatchPreambleEv 00000000000b08e0 g 0f SECT 01 0000 [.text] __ZN11SiBltDevice23WriteDrmDmaTiledCopyCmdEP13_UBM_SURFINFOjS1_13LARGE_INTEGERjj 00000000000b20d8 g 0f SECT 01 0000 [.text] __ZN11SiBltDevice23WritePreemptionPreambleE13PM4ShaderType 00000000000ae5cc g 0f SECT 01 0000 [.text] __ZN11SiBltDevice24LoadShadowGfxContextRegsEv 00000000000af2f4 g 0f SECT 01 0000 [.text] __ZN11SiBltDevice24SizeSdmaT2TSubWinCopyCmdEv 00000000000b124c g 0f SECT 01 0000 [.text] __ZN11SiBltDevice24WriteSdmaConstantFillCmdEPv13LARGE_INTEGERjjj26_UBM_ADDHANDLE_INPUT_FLAGS 00000000000ac59c g 0f SECT 01 0000 [.text] __ZN11SiBltDevice25HwlNotifyShadowMemoryInfoEP26_UBM_STATESHADOWMEMORYINFO 00000000000b1230 g 0f SECT 01 0000 [.text] __ZN11SiBltDevice25SizeDrmDmaConstantFillCmdEv 00000000000ae9f8 g 0f SECT 01 0000 [.text] __ZN11SiBltDevice25Write3dDispatchPreambleCiEv 00000000000aead0 g 0f SECT 01 0000 [.text] __ZN11SiBltDevice25Write3dDispatchPreambleSiEv 00000000000ad84e g 0f SECT 01 0000 [.text] __ZN11SiBltDevice25WriteFlushAndInvTimestampEPv13LARGE_INTEGERj 00000000000b03ec g 0f SECT 01 0000 [.text] __ZN11SiBltDevice25WriteSdmaT2TCopySubWinCmdEPK13_UBM_SURFINFOPK11_UBM_POINTLS2_S5_jj26_UBM_ADDHANDLE_INPUT_FLAGS 00000000000ad5d8 g 0f SECT 01 0000 [.text] __ZN11SiBltDevice26SetupAlignedEmbeddedBufferEjj 00000000000af2cc g 0f SECT 01 0000 [.text] __ZN11SiBltDevice26SizeSdmaTiledSubWinCopyCmdEv 00000000000ad688 g 0f SECT 01 0000 [.text] __ZN11SiBltDevice26WaitOnFlushAndInvTimestampEv 00000000000b1360 g 0f SECT 01 0000 [.text] __ZN11SiBltDevice26WriteDrmDmaConstantFillCmdEPv13LARGE_INTEGERjj26_UBM_ADDHANDLE_INPUT_FLAGS 00000000000af4a6 g 0f SECT 01 0000 [.text] __ZN11SiBltDevice26WriteSdmaLinearByteCopyCmdEPv13LARGE_INTEGERS0_S1_j26_UBM_ADDHANDLE_INPUT_FLAGS 00000000000af258 g 0f SECT 01 0000 [.text] __ZN11SiBltDevice27SizeDrmDmaLinearByteCopyCmdEv 00000000000af2d8 g 0f SECT 01 0000 [.text] __ZN11SiBltDevice27SizeDrmDmaT2TPartialCopyCmdEv 00000000000af31c g 0f SECT 01 0000 [.text] __ZN11SiBltDevice27SizeSdmaLinearSubWinCopyCmdEv 00000000000af604 g 0f SECT 01 0000 [.text] __ZN11SiBltDevice27WriteSdmaLinearDwordCopyCmdEPv13LARGE_INTEGERS0_S1_jj26_UBM_ADDHANDLE_INPUT_FLAGS 00000000000afcdc g 0f SECT 01 0000 [.text] __ZN11SiBltDevice27WriteSdmaTiledCopySubWinCmdEPK13_UBM_SURFINFOPK11_UBM_POINTLS2_S5_jjj26_UBM_ADDHANDLE_INPUT_FLAGS 00000000000adc14 g 0f SECT 01 0000 [.text] __ZN11SiBltDevice28Post3dDrawBltSynchronizationEPK7BltInfo 00000000000ad59c g 0f SECT 01 0000 [.text] __ZN11SiBltDevice28SetupAndCommitEmbeddedBufferEjjPm 00000000000af274 g 0f SECT 01 0000 [.text] __ZN11SiBltDevice28SizeDrmDmaLinearDwordCopyCmdEv 00000000000af328 g 0f SECT 01 0000 [.text] __ZN11SiBltDevice28WriteDrmDmaLinearByteCopyCmdEPv13LARGE_INTEGERS0_S1_j26_UBM_ADDHANDLE_INPUT_FLAGS 00000000000b1766 g 0f SECT 01 0000 [.text] __ZN11SiBltDevice28WriteDrmDmaT2TPartialCopyCmdEPK13_UBM_SURFINFOPK11_UBM_POINTLS2_S5_jj26_UBM_ADDHANDLE_INPUT_FLAGS 00000000000b0108 g 0f SECT 01 0000 [.text] __ZN11SiBltDevice28WriteSdmaLinearCopySubWinCmdEPK13_UBM_SURFINFOPK11_UBM_POINTLS2_S5_jj26_UBM_ADDHANDLE_INPUT_FLAGS 00000000000af2b0 g 0f SECT 01 0000 [.text] __ZN11SiBltDevice29SizeDrmDmaTiledPartialCopyCmdEv 00000000000af776 g 0f SECT 01 0000 [.text] __ZN11SiBltDevice29WriteDrmDmaLinearDwordCopyCmdEPv13LARGE_INTEGERS0_S1_jj26_UBM_ADDHANDLE_INPUT_FLAGS 00000000000ad58a g 0f SECT 01 0000 [.text] __ZN11SiBltDevice30EstimatedEmbeddedBufferEntriesEjj 00000000000ade40 g 0f SECT 01 0000 [.text] __ZN11SiBltDevice30PostDispatchBltSynchronizationEPK7BltInfo 00000000000af300 g 0f SECT 01 0000 [.text] __ZN11SiBltDevice30SizeDrmDmaLinearPartialCopyCmdEv 00000000000b1ba8 g 0f SECT 01 0000 [.text] __ZN11SiBltDevice30WriteDrmDmaTiledPartialCopyCmdEPK13_UBM_SURFINFOPK11_UBM_POINTLS2_S5_jjj26_UBM_ADDHANDLE_INPUT_FLAGS 00000000000b14b4 g 0f SECT 01 0000 [.text] __ZN11SiBltDevice31WriteDrmDmaLinearPartialCopyCmdEPK13_UBM_SURFINFOPK11_UBM_POINTLS2_S5_jj26_UBM_ADDHANDLE_INPUT_FLAGS 00000000000ac520 g 0f SECT 01 0000 [.text] __ZN11SiBltDevice7HwlInitEPK15_UBM_DEVICEINFO 00000000000ac532 g 0f SECT 01 0000 [.text] __ZN11SiBltDevice7HwlTrimEv 00000000000ac4fa g 0f SECT 01 0000 [.text] __ZN11SiBltDevice9CreateObjEv 00000000000b2048 g 0f SECT 01 0000 [.text] __ZN11SiBltDevice9GetNopCmdEj 00000000000ac4c0 g 0f SECT 01 0000 [.text] __ZN11SiBltDeviceC1Ev 00000000000ac458 g 0f SECT 01 0000 [.text] __ZN11SiBltDeviceC2Ev 00000000000ac4de g 0f SECT 01 0000 [.text] __ZN11SiBltDeviceD0Ev 00000000000ac4d4 g 0f SECT 01 0000 [.text] __ZN11SiBltDeviceD1Ev 00000000000ac4ca g 0f SECT 01 0000 [.text] __ZN11SiBltDeviceD2Ev 00000000000bc2a4 g 0f SECT 01 0000 [.text] __ZN11SiBltResFmt12CreateObjectEv 00000000000bc254 g 0f SECT 01 0000 [.text] __ZN11SiBltResFmtC1Ev 00000000000bc234 g 0f SECT 01 0000 [.text] __ZN11SiBltResFmtC2Ev 00000000000bc288 g 0f SECT 01 0000 [.text] __ZN11SiBltResFmtD0Ev 00000000000bc27e g 0f SECT 01 0000 [.text] __ZN11SiBltResFmtD1Ev 00000000000bc274 g 0f SECT 01 0000 [.text] __ZN11SiBltResFmtD2Ev 00000000000bdc5c g 0f SECT 01 0000 [.text] __ZN11SiBltShader17SetBltShaderInputEPK16SiBltShaderInput 00000000000bdca0 g 0f SECT 01 0000 [.text] __ZN11SiBltShader7GpuLoadEP9BltDevicePv13LARGE_INTEGER 000000000052e648 g 0f SECT 0a 0000 [__DATA.__common] __ZN12AMDCIDisplay10gMetaClassE 00000000003b4968 g 0f SECT 08 0000 [.const_data] __ZN12AMDCIDisplay10superClassE 000000000007b98e g 0f SECT 01 0000 [.text] __ZN12AMDCIDisplay12getPixelModeEjj 000000000007b87a g 0f SECT 01 0000 [.text] __ZN12AMDCIDisplay14getDisplayInfoEjbbPvP17_FRAMEBUFFER_INFO 000000000007b2bc g 0f SECT 01 0000 [.text] __ZN12AMDCIDisplay14getSurfaceMaskERKj 000000000007b2cc g 0f SECT 01 0000 [.text] __ZN12AMDCIDisplay15getSurfaceFlagsEv 000000000007b16e g 0f SECT 01 0000 [.text] __ZN12AMDCIDisplay17writeWaitForVLineEPjjRiS1_bb 000000000007ba06 g 0f SECT 01 0000 [.text] __ZN12AMDCIDisplay25writeFlipControlRegistersEjPjjyy 000000000007b962 g 0f SECT 01 0000 [.text] __ZN12AMDCIDisplay26isCurrentDisplayModeLinearEj 000000000007b0d2 g 0f SECT 01 0000 [.text] __ZN12AMDCIDisplay27initDisplayRegistersOffsetsEv 000000000007b9aa g 0f SECT 01 0000 [.text] __ZN12AMDCIDisplay34fedsWriteClearSurfaceApertureFlagsEPjj 000000000007c38e g 0f SECT 01 0000 [.text] __ZN12AMDCIDisplay34getDisplayModeViewportSpecificInfoERKjPjS2_ 000000000007af40 g 0f SECT 01 0000 [.text] __ZN12AMDCIDisplay9MetaClassC1Ev 000000000007b000 g 0f SECT 01 0000 [.text] __ZN12AMDCIDisplay9MetaClassC2Ev 00000000003b4960 g 0f SECT 08 0000 [.const_data] __ZN12AMDCIDisplay9metaClassE 000000000007b2e6 g 0f SECT 01 0000 [.text] __ZN12AMDCIDisplay9setStereoEjbb 000000000007af9c g 0f SECT 01 0000 [.text] __ZN12AMDCIDisplayC1EPK11OSMetaClass 000000000007b072 g 0f SECT 01 0000 [.text] __ZN12AMDCIDisplayC1Ev 000000000007af7c g 0f SECT 01 0000 [.text] __ZN12AMDCIDisplayC2EPK11OSMetaClass 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0000 [.text] __ZN12AMDSIDisplay14getDisplayInfoEjbbPvP17_FRAMEBUFFER_INFO 000000000006408a g 0f SECT 01 0000 [.text] __ZN12AMDSIDisplay14getPixelFormatEh 0000000000063ea4 g 0f SECT 01 0000 [.text] __ZN12AMDSIDisplay14getSurfaceMaskEj 0000000000063e8a g 0f SECT 01 0000 [.text] __ZN12AMDSIDisplay15getSurfaceFlagsEv 0000000000064960 g 0f SECT 01 0000 [.text] __ZN12AMDSIDisplay17writeWaitForVLineEPjjRiS1_bb 0000000000063b04 g 0f SECT 01 0000 [.text] __ZN12AMDSIDisplay19configCrtcRegistersEjP16IOAccelResource2P16IOAccelMemoryMap 0000000000064750 g 0f SECT 01 0000 [.text] __ZN12AMDSIDisplay22writeVblankFlipElementEP20AMD_VBLANK_FLIP_ELEMjyyj 00000000000640ec g 0f SECT 01 0000 [.text] __ZN12AMDSIDisplay25writeFlipControlRegistersEjPjjyy 0000000000064042 g 0f SECT 01 0000 [.text] __ZN12AMDSIDisplay26isCurrentDisplayModeLinearEj 0000000000064954 g 0f SECT 01 0000 [.text] __ZN12AMDSIDisplay27getSurfaceUpdatePendingMaskEv 0000000000063476 g 0f SECT 01 0000 [.text] __ZN12AMDSIDisplay27initDisplayRegistersOffsetsEv 0000000000063eb6 g 0f SECT 01 0000 [.text] __ZN12AMDSIDisplay34fedsWriteClearSurfaceApertureFlagsEPjj 0000000000063ee6 g 0f SECT 01 0000 [.text] __ZN12AMDSIDisplay34getDisplayModeViewportSpecificInfoEjPjS0_ 0000000000064a86 g 0f SECT 01 0000 [.text] __ZN12AMDSIDisplay34writeDrawBufferInformationCommandsEPK16IOAccelResource2Pj 0000000000063464 g 0f SECT 01 0000 [.text] __ZN12AMDSIDisplay4freeEv 0000000000063452 g 0f SECT 01 0000 [.text] __ZN12AMDSIDisplay4initEP30AMDRadeonX4000_IAMDHWInterfaceP14_FB_PARAMETERS 00000000000632c0 g 0f SECT 01 0000 [.text] __ZN12AMDSIDisplay9MetaClassC1Ev 0000000000063380 g 0f SECT 01 0000 [.text] __ZN12AMDSIDisplay9MetaClassC2Ev 00000000003aa9f0 g 0f SECT 08 0000 [.const_data] __ZN12AMDSIDisplay9metaClassE 0000000000063512 g 0f SECT 01 0000 [.text] __ZN12AMDSIDisplay9setStereoEjbb 000000000006331c g 0f SECT 01 0000 [.text] __ZN12AMDSIDisplayC1EPK11OSMetaClass 00000000000633f2 g 0f SECT 01 0000 [.text] __ZN12AMDSIDisplayC1Ev 00000000000632fc g 0f SECT 01 0000 [.text] __ZN12AMDSIDisplayC2EPK11OSMetaClass 0000000000063422 g 0f SECT 01 0000 [.text] __ZN12AMDSIDisplayC2Ev 0000000000063350 g 0f SECT 01 0000 [.text] __ZN12AMDSIDisplayD0Ev 0000000000063346 g 0f SECT 01 0000 [.text] __ZN12AMDSIDisplayD1Ev 000000000006333c g 0f SECT 01 0000 [.text] __ZN12AMDSIDisplayD2Ev 000000000052e490 g 0f SECT 0a 0000 [__DATA.__common] __ZN12AMDSISPURing10gMetaClassE 00000000003b19d8 g 0f SECT 08 0000 [.const_data] __ZN12AMDSISPURing10superClassE 0000000000073636 g 0f SECT 01 0000 [.text] __ZN12AMDSISPURing11commitBlockEj 000000000007350c g 0f SECT 01 0000 [.text] __ZN12AMDSISPURing16registerLocationEv 0000000000073654 g 0f SECT 01 0000 [.text] __ZN12AMDSISPURing17getSPUReadPointerEv 0000000000073696 g 0f SECT 01 0000 [.text] __ZN12AMDSISPURing18getSPUWritePointerEv 0000000000073530 g 0f SECT 01 0000 [.text] __ZN12AMDSISPURing26enableReadPointerWriteBackEv 0000000000073536 g 0f SECT 01 0000 [.text] __ZN12AMDSISPURing27disableReadPointerWriteBackEv 0000000000073592 g 0f SECT 01 0000 [.text] __ZN12AMDSISPURing27programReadAndWritePointersEj 00000000000734c2 g 0f SECT 01 0000 [.text] __ZN12AMDSISPURing4freeEv 0000000000073422 g 0f SECT 01 0000 [.text] __ZN12AMDSISPURing4initEP30AMDRadeonX4000_IAMDHWInterfacei20_eAMD_HW_ENGINE_TYPEjPKv 000000000007364e g 0f SECT 01 0000 [.text] __ZN12AMDSISPURing5alignEv 000000000007353c g 0f SECT 01 0000 [.text] __ZN12AMDSISPURing5resetEv 0000000000073612 g 0f SECT 01 0000 [.text] __ZN12AMDSISPURing5writeEj 00000000000734fe g 0f SECT 01 0000 [.text] __ZN12AMDSISPURing7getHeadEv 0000000000073290 g 0f SECT 01 0000 [.text] __ZN12AMDSISPURing9MetaClassC1Ev 0000000000073350 g 0f SECT 01 0000 [.text] __ZN12AMDSISPURing9MetaClassC2Ev 00000000003b19d0 g 0f SECT 08 0000 [.const_data] __ZN12AMDSISPURing9metaClassE 00000000000736d8 g 0f SECT 01 0000 [.text] __ZN12AMDSISPURing9writeTailEv 00000000000732ec g 0f SECT 01 0000 [.text] __ZN12AMDSISPURingC1EPK11OSMetaClass 00000000000733c2 g 0f SECT 01 0000 [.text] __ZN12AMDSISPURingC1Ev 00000000000732cc g 0f SECT 01 0000 [.text] __ZN12AMDSISPURingC2EPK11OSMetaClass 00000000000733f2 g 0f SECT 01 0000 [.text] __ZN12AMDSISPURingC2Ev 0000000000073320 g 0f SECT 01 0000 [.text] __ZN12AMDSISPURingD0Ev 0000000000073316 g 0f SECT 01 0000 [.text] __ZN12AMDSISPURingD1Ev 000000000007330c g 0f SECT 01 0000 [.text] __ZN12AMDSISPURingD2Ev 000000000052d658 g 0f SECT 0a 0000 [__DATA.__common] __ZN12AMDSISurface10gMetaClassE 00000000003976f8 g 0f SECT 08 0000 [.const_data] __ZN12AMDSISurface10superClassE 000000000002ab82 g 0f SECT 01 0000 [.text] __ZN12AMDSISurface25getSurfaceModeDepthFormatEv 000000000002a9f0 g 0f SECT 01 0000 [.text] __ZN12AMDSISurface9MetaClassC1Ev 000000000002aab0 g 0f SECT 01 0000 [.text] __ZN12AMDSISurface9MetaClassC2Ev 00000000003976f0 g 0f SECT 08 0000 [.const_data] __ZN12AMDSISurface9metaClassE 000000000002aa4c g 0f SECT 01 0000 [.text] __ZN12AMDSISurfaceC1EPK11OSMetaClass 000000000002ab22 g 0f SECT 01 0000 [.text] __ZN12AMDSISurfaceC1Ev 000000000002aa2c g 0f SECT 01 0000 [.text] __ZN12AMDSISurfaceC2EPK11OSMetaClass 000000000002ab52 g 0f SECT 01 0000 [.text] __ZN12AMDSISurfaceC2Ev 000000000002aa80 g 0f SECT 01 0000 [.text] __ZN12AMDSISurfaceD0Ev 000000000002aa76 g 0f SECT 01 0000 [.text] __ZN12AMDSISurfaceD1Ev 000000000002aa6c g 0f SECT 01 0000 [.text] __ZN12AMDSISurfaceD2Ev 000000000052e418 g 0f SECT 0a 0000 [__DATA.__common] __ZN12AMDSIUVDRing10gMetaClassE 00000000003b0f38 g 0f SECT 08 0000 [.const_data] __ZN12AMDSIUVDRing10superClassE 0000000000071e68 g 0f SECT 01 0000 [.text] __ZN12AMDSIUVDRing16registerLocationEv 0000000000071f46 g 0f SECT 01 0000 [.text] __ZN12AMDSIUVDRing26enableReadPointerWriteBackEv 0000000000071f4c g 0f SECT 01 0000 [.text] __ZN12AMDSIUVDRing27disableReadPointerWriteBackEv 0000000000071fb0 g 0f SECT 01 0000 [.text] __ZN12AMDSIUVDRing27programReadAndWritePointersEj 0000000000071dcc g 0f SECT 01 0000 [.text] __ZN12AMDSIUVDRing4freeEv 0000000000071d22 g 0f SECT 01 0000 [.text] __ZN12AMDSIUVDRing4initEP30AMDRadeonX4000_IAMDHWInterfacei20_eAMD_HW_ENGINE_TYPEjPKv 000000000007200e g 0f SECT 01 0000 [.text] __ZN12AMDSIUVDRing5alignEv 0000000000071f52 g 0f SECT 01 0000 [.text] __ZN12AMDSIUVDRing5resetEv 0000000000071dde g 0f SECT 01 0000 [.text] __ZN12AMDSIUVDRing7disableEv 0000000000071e36 g 0f SECT 01 0000 [.text] __ZN12AMDSIUVDRing7getHeadEv 0000000000071b90 g 0f SECT 01 0000 [.text] __ZN12AMDSIUVDRing9MetaClassC1Ev 0000000000071c50 g 0f SECT 01 0000 [.text] __ZN12AMDSIUVDRing9MetaClassC2Ev 00000000003b0f30 g 0f SECT 08 0000 [.const_data] __ZN12AMDSIUVDRing9metaClassE 0000000000071bec g 0f SECT 01 0000 [.text] __ZN12AMDSIUVDRingC1EPK11OSMetaClass 0000000000071cc2 g 0f SECT 01 0000 [.text] __ZN12AMDSIUVDRingC1Ev 0000000000071bcc g 0f SECT 01 0000 [.text] __ZN12AMDSIUVDRingC2EPK11OSMetaClass 0000000000071cf2 g 0f SECT 01 0000 [.text] __ZN12AMDSIUVDRingC2Ev 0000000000071c20 g 0f SECT 01 0000 [.text] __ZN12AMDSIUVDRingD0Ev 0000000000071c16 g 0f SECT 01 0000 [.text] __ZN12AMDSIUVDRingD1Ev 0000000000071c0c g 0f SECT 01 0000 [.text] __ZN12AMDSIUVDRingD2Ev 000000000052e378 g 0f SECT 0a 0000 [__DATA.__common] __ZN12AMDSIVCERing10gMetaClassE 00000000003b0098 g 0f SECT 08 0000 [.const_data] __ZN12AMDSIVCERing10superClassE 0000000000070740 g 0f SECT 01 0000 [.text] __ZN12AMDSIVCERing12writeEntriesEPjj 00000000000705e4 g 0f SECT 01 0000 [.text] __ZN12AMDSIVCERing16registerLocationEv 000000000007065a g 0f SECT 01 0000 [.text] __ZN12AMDSIVCERing26enableReadPointerWriteBackEv 0000000000070660 g 0f SECT 01 0000 [.text] __ZN12AMDSIVCERing27disableReadPointerWriteBackEv 00000000000706c4 g 0f SECT 01 0000 [.text] __ZN12AMDSIVCERing27programReadAndWritePointersEj 0000000000070582 g 0f SECT 01 0000 [.text] __ZN12AMDSIVCERing4freeEv 00000000000704e2 g 0f SECT 01 0000 [.text] __ZN12AMDSIVCERing4initEP30AMDRadeonX4000_IAMDHWInterfacei20_eAMD_HW_ENGINE_TYPEjPKv 000000000007077e g 0f SECT 01 0000 [.text] __ZN12AMDSIVCERing5alignEv 0000000000070666 g 0f SECT 01 0000 [.text] __ZN12AMDSIVCERing5resetEv 000000000007071c g 0f SECT 01 0000 [.text] __ZN12AMDSIVCERing5writeEj 00000000000705be g 0f SECT 01 0000 [.text] __ZN12AMDSIVCERing7getHeadEv 0000000000070350 g 0f SECT 01 0000 [.text] __ZN12AMDSIVCERing9MetaClassC1Ev 0000000000070410 g 0f SECT 01 0000 [.text] __ZN12AMDSIVCERing9MetaClassC2Ev 00000000003b0090 g 0f SECT 08 0000 [.const_data] __ZN12AMDSIVCERing9metaClassE 00000000000703ac g 0f SECT 01 0000 [.text] __ZN12AMDSIVCERingC1EPK11OSMetaClass 0000000000070482 g 0f SECT 01 0000 [.text] __ZN12AMDSIVCERingC1Ev 000000000007038c g 0f SECT 01 0000 [.text] __ZN12AMDSIVCERingC2EPK11OSMetaClass 00000000000704b2 g 0f SECT 01 0000 [.text] __ZN12AMDSIVCERingC2Ev 00000000000703e0 g 0f SECT 01 0000 [.text] __ZN12AMDSIVCERingD0Ev 00000000000703d6 g 0f SECT 01 0000 [.text] __ZN12AMDSIVCERingD1Ev 00000000000703cc g 0f SECT 01 0000 [.text] __ZN12AMDSIVCERingD2Ev 000000000052ea08 g 0f SECT 0a 0000 [__DATA.__common] __ZN12AMDVIDisplay10gMetaClassE 00000000003ba548 g 0f SECT 08 0000 [.const_data] __ZN12AMDVIDisplay10superClassE 000000000008a362 g 0f SECT 01 0000 [.text] __ZN12AMDVIDisplay12getPixelModeEjj 0000000000089c4e g 0f SECT 01 0000 [.text] __ZN12AMDVIDisplay14FEDSRevertCRTCEv 000000000008a386 g 0f SECT 01 0000 [.text] __ZN12AMDVIDisplay14getDisplayInfoEjbbPvP17_FRAMEBUFFER_INFO 000000000008a49a g 0f SECT 01 0000 [.text] __ZN12AMDVIDisplay14getPixelFormatEh 0000000000089da2 g 0f SECT 01 0000 [.text] __ZN12AMDVIDisplay14getSurfaceMaskEj 0000000000089db4 g 0f SECT 01 0000 [.text] __ZN12AMDVIDisplay15getSurfaceFlagsEv 0000000000089c54 g 0f SECT 01 0000 [.text] __ZN12AMDVIDisplay17writeWaitForVLineEPjjRiS1_bb 0000000000089992 g 0f SECT 01 0000 [.text] __ZN12AMDVIDisplay19configCrtcRegistersEjP16IOAccelResource2P16IOAccelMemoryMap 000000000008af6c g 0f SECT 01 0000 [.text] __ZN12AMDVIDisplay22writeVblankFlipElementEP20AMD_VBLANK_FLIP_ELEMjyyj 000000000008a4fc g 0f SECT 01 0000 [.text] __ZN12AMDVIDisplay25writeFlipControlRegistersEjPjjyy 000000000008a46e g 0f SECT 01 0000 [.text] __ZN12AMDVIDisplay26isCurrentDisplayModeLinearEj 000000000008b170 g 0f SECT 01 0000 [.text] __ZN12AMDVIDisplay27getSurfaceUpdatePendingMaskEv 00000000000898f6 g 0f SECT 01 0000 [.text] __ZN12AMDVIDisplay27initDisplayRegistersOffsetsEv 000000000008adca g 0f SECT 01 0000 [.text] __ZN12AMDVIDisplay27writeTilingControlRegistersEjPjj 000000000008a37e g 0f SECT 01 0000 [.text] __ZN12AMDVIDisplay34fedsWriteClearSurfaceApertureFlagsEPjj 000000000008aef8 g 0f SECT 01 0000 [.text] __ZN12AMDVIDisplay34getDisplayModeViewportSpecificInfoEjPjS0_ 000000000008b17c g 0f SECT 01 0000 [.text] __ZN12AMDVIDisplay34writeDrawBufferInformationCommandsEPK16IOAccelResource2Pj 00000000000898e4 g 0f SECT 01 0000 [.text] __ZN12AMDVIDisplay4freeEv 00000000000898d2 g 0f SECT 01 0000 [.text] __ZN12AMDVIDisplay4initEP30AMDRadeonX4000_IAMDHWInterfaceP14_FB_PARAMETERS 0000000000089740 g 0f SECT 01 0000 [.text] __ZN12AMDVIDisplay9MetaClassC1Ev 0000000000089800 g 0f SECT 01 0000 [.text] __ZN12AMDVIDisplay9MetaClassC2Ev 00000000003ba540 g 0f SECT 08 0000 [.const_data] __ZN12AMDVIDisplay9metaClassE 0000000000089dce g 0f SECT 01 0000 [.text] __ZN12AMDVIDisplay9setStereoEjbb 000000000008979c g 0f SECT 01 0000 [.text] __ZN12AMDVIDisplayC1EPK11OSMetaClass 0000000000089872 g 0f SECT 01 0000 [.text] __ZN12AMDVIDisplayC1Ev 000000000008977c g 0f SECT 01 0000 [.text] __ZN12AMDVIDisplayC2EPK11OSMetaClass 00000000000898a2 g 0f SECT 01 0000 [.text] __ZN12AMDVIDisplayC2Ev 00000000000897d0 g 0f SECT 01 0000 [.text] __ZN12AMDVIDisplayD0Ev 00000000000897c6 g 0f SECT 01 0000 [.text] __ZN12AMDVIDisplayD1Ev 00000000000897bc g 0f SECT 01 0000 [.text] __ZN12AMDVIDisplayD2Ev 000000000052e670 g 0f SECT 0a 0000 [__DATA.__common] __ZN13AMDCIHWMemory10gMetaClassE 00000000003b4de8 g 0f SECT 08 0000 [.const_data] __ZN13AMDCIHWMemory10superClassE 000000000007c856 g 0f SECT 01 0000 [.text] __ZN13AMDCIHWMemory15getHWMemorySizeEv 000000000007c888 g 0f SECT 01 0000 [.text] __ZN13AMDCIHWMemory23getHWMemoryApertureSizeEv 000000000007c842 g 0f SECT 01 0000 [.text] __ZN13AMDCIHWMemory4initEP30AMDRadeonX4000_IAMDHWInterface 000000000007c8ba g 0f SECT 01 0000 [.text] __ZN13AMDCIHWMemory7prepareEP31AMDRadeonX4000_AMDAccelResourceyyPy 000000000007cc2c g 0f SECT 01 0000 [.text] __ZN13AMDCIHWMemory8completeEP31AMDRadeonX4000_AMDAccelResource 000000000007c6b0 g 0f SECT 01 0000 [.text] __ZN13AMDCIHWMemory9MetaClassC1Ev 000000000007c770 g 0f SECT 01 0000 [.text] __ZN13AMDCIHWMemory9MetaClassC2Ev 00000000003b4de0 g 0f SECT 08 0000 [.const_data] __ZN13AMDCIHWMemory9metaClassE 000000000007c70c g 0f SECT 01 0000 [.text] __ZN13AMDCIHWMemoryC1EPK11OSMetaClass 000000000007c7e2 g 0f SECT 01 0000 [.text] __ZN13AMDCIHWMemoryC1Ev 000000000007c6ec g 0f SECT 01 0000 [.text] __ZN13AMDCIHWMemoryC2EPK11OSMetaClass 000000000007c812 g 0f SECT 01 0000 [.text] __ZN13AMDCIHWMemoryC2Ev 000000000007c740 g 0f SECT 01 0000 [.text] __ZN13AMDCIHWMemoryD0Ev 000000000007c736 g 0f SECT 01 0000 [.text] __ZN13AMDCIHWMemoryD1Ev 000000000007c72c g 0f SECT 01 0000 [.text] __ZN13AMDCIHWMemoryD2Ev 0000000000077126 g 0f SECT 01 0000 [.text] __ZN13AMDCIHardware10disableDPMEv 000000000052e508 g 0f SECT 0a 0000 [__DATA.__common] __ZN13AMDCIHardware10gMetaClassE 00000000000750fc g 0f SECT 01 0000 [.text] __ZN13AMDCIHardware10initHWInfoEv 00000000003b2418 g 0f SECT 08 0000 [.const_data] __ZN13AMDCIHardware10superClassE 0000000000074b6a g 0f SECT 01 0000 [.text] __ZN13AMDCIHardware11allocateSMLEv 000000000007711e g 0f SECT 01 0000 [.text] __ZN13AMDCIHardware12isDPMEnabledEv 0000000000075940 g 0f SECT 01 0000 [.text] __ZN13AMDCIHardware13enableContextEjb 0000000000074fe2 g 0f SECT 01 0000 [.text] __ZN13AMDCIHardware13flushHDPCacheEv 00000000000752f4 g 0f SECT 01 0000 [.text] __ZN13AMDCIHardware13initializeGUIEv 0000000000074b90 g 0f SECT 01 0000 [.text] __ZN13AMDCIHardware16allocateAMDHWVMMEv 0000000000074a38 g 0f SECT 01 0000 [.text] __ZN13AMDCIHardware16getOGLBundleNameEv 0000000000075024 g 0f SECT 01 0000 [.text] __ZN13AMDCIHardware16initMaskSettingsEv 00000000000757d6 g 0f SECT 01 0000 [.text] __ZN13AMDCIHardware16initializeVMRegsEv 0000000000074e3c g 0f SECT 01 0000 [.text] __ZN13AMDCIHardware17allocateHWEnginesEv 00000000000767b6 g 0f SECT 01 0000 [.text] __ZN13AMDCIHardware17dumpASICHangStateEb 00000000000750d2 g 0f SECT 01 0000 [.text] __ZN13AMDCIHardware17getCoherCntrValueEbbb 00000000000757ae g 0f SECT 01 0000 [.text] __ZN13AMDCIHardware17initializeTlbRegsEv 0000000000075362 g 0f SECT 01 0000 [.text] __ZN13AMDCIHardware18enableTransactionsEv 000000000007513a g 0f SECT 01 0000 [.text] __ZN13AMDCIHardware18getAMDHwInfoValuesEP24_sAMD_GET_HW_INFO_VALUES 0000000000074a84 g 0f SECT 01 0000 [.text] __ZN13AMDCIHardware18getMemSizeRegisterEv 0000000000074fc4 g 0f SECT 01 0000 [.text] __ZN13AMDCIHardware18readHWChipRevValueEv 0000000000074aaa g 0f SECT 01 0000 [.text] __ZN13AMDCIHardware18setMemSizeRegisterEj 00000000000755bc g 0f SECT 01 0000 [.text] __ZN13AMDCIHardware18setupInternalSpaceEv 0000000000074a0c g 0f SECT 01 0000 [.text] __ZN13AMDCIHardware18writeOCDBundleNameEv 0000000000074af8 g 0f SECT 01 0000 [.text] __ZN13AMDCIHardware19allocateAMDHWMemoryEv 0000000000075316 g 0f SECT 01 0000 [.text] __ZN13AMDCIHardware19disableTransactionsEv 00000000000753f2 g 0f SECT 01 0000 [.text] __ZN13AMDCIHardware19fillNDRVSurfaceInfoEP24_AMD_SURFACE_INFO_STRUCTP14_ADDR_TILEINFO 000000000007629a g 0f SECT 01 0000 [.text] __ZN13AMDCIHardware19freeWritebackMemoryEv 0000000000074ad2 g 0f SECT 01 0000 [.text] __ZN13AMDCIHardware19getRegisterAperSizeEv 0000000000075a48 g 0f SECT 01 0000 [.text] __ZN13AMDCIHardware19initializeCacheRegsEv 0000000000075014 g 0f SECT 01 0000 [.text] __ZN13AMDCIHardware19initializeGFXEngineEv 0000000000075c0c g 0f SECT 01 0000 [.text] __ZN13AMDCIHardware19verifyThreadsActiveEv 0000000000074b1e g 0f SECT 01 0000 [.text] __ZN13AMDCIHardware20allocateAMDHWDisplayEv 0000000000075004 g 0f SECT 01 0000 [.text] __ZN13AMDCIHardware20initializeFamilyTypeEv 0000000000074c94 g 0f SECT 01 0000 [.text] __ZN13AMDCIHardware20readHWGBTilingConfigEv 0000000000076afe g 0f SECT 01 0000 [.text] __ZN13AMDCIHardware20writeASICHangLogInfoEP23_AMD_ASIC_HANG_LOG_INFO 0000000000076d82 g 0f SECT 01 0000 [.text] __ZN13AMDCIHardware20writeDiagnosisReportERPcRj 0000000000077084 g 0f SECT 01 0000 [.text] __ZN13AMDCIHardware21writeQSCRegMemTimeoutEPjj 0000000000074bfc g 0f SECT 01 0000 [.text] __ZN13AMDCIHardware22allocateAMDHWUtilitiesEv 0000000000074a78 g 0f SECT 01 0000 [.text] __ZN13AMDCIHardware22getATIDisplayConfigBitEv 0000000000076216 g 0f SECT 01 0000 [.text] __ZN13AMDCIHardware23allocateWritebackMemoryEv 0000000000074a46 g 0f SECT 01 0000 [.text] __ZN13AMDCIHardware23createAtomicBlitManagerEv 0000000000074c22 g 0f SECT 01 0000 [.text] __ZN13AMDCIHardware23initializeHWWorkaroundsEv 000000000007564e g 0f SECT 01 0000 [.text] __ZN13AMDCIHardware23initializePageTableRegsEv 000000000007709e g 0f SECT 01 0000 [.text] __ZN13AMDCIHardware23setPerformanceLevelHighEv 0000000000074cb2 g 0f SECT 01 0000 [.text] __ZN13AMDCIHardware24getHardwareDefaultValuesEP23_sAMD_HW_DEFAULT_VALUES 0000000000074bd6 g 0f SECT 01 0000 [.text] __ZN13AMDCIHardware25allocateAMDHWAlignManagerEv 0000000000076742 g 0f SECT 01 0000 [.text] __ZN13AMDCIHardware25dumpAsicHangLogIntoSyslogEP23_AMD_ASIC_HANG_LOG_INFO 0000000000074950 g 0f SECT 01 0000 [.text] __ZN13AMDCIHardware25getFrameBufferBaseAddressEv 00000000000759ae g 0f SECT 01 0000 [.text] __ZN13AMDCIHardware25programPageTableRegistersEP22AMD_VM_PAGE_TABLE_INFOj 000000000007496e g 0f SECT 01 0000 [.text] __ZN13AMDCIHardware25writeWaitForRenderingPipeEPjb 0000000000074b44 g 0f SECT 01 0000 [.text] __ZN13AMDCIHardware26allocatePM4CommandsUtilityEv 0000000000075a70 g 0f SECT 01 0000 [.text] __ZN13AMDCIHardware26initializeGartApertureRegsEv 0000000000074f3e g 0f SECT 01 0000 [.text] __ZN13AMDCIHardware26invalidateAllTLBsAndCachesEbj 0000000000076678 g 0f SECT 01 0000 [.text] __ZN13AMDCIHardware27asicHangReadROQandMEQStatusER27amdAsicHangDumpROQMEQStatus 0000000000075bf6 g 0f SECT 01 0000 [.text] __ZN13AMDCIHardware27setMemoryAllocationsEnabledEb 0000000000076504 g 0f SECT 01 0000 [.text] __ZN13AMDCIHardware28asicHangLogDumpMeStateQueuesEP23_AMD_ASIC_HANG_LOG_INFO 0000000000076350 g 0f SECT 01 0000 [.text] __ZN13AMDCIHardware28asicHangLogDumpReorderQueuesEP23_AMD_ASIC_HANG_LOG_INFO 000000000007562c g 0f SECT 01 0000 [.text] __ZN13AMDCIHardware28initializeHDPPathWorkaroundsEv 0000000000075b12 g 0f SECT 01 0000 [.text] __ZN13AMDCIHardware28initializeSystemApertureRegsEv 00000000000762f8 g 0f SECT 01 0000 [.text] __ZN13AMDCIHardware30getChannelWritePointerPollAddrEi 00000000000762e0 g 0f SECT 01 0000 [.text] __ZN13AMDCIHardware32getChannelWritePointerPollOffsetEi 0000000000074a6c g 0f SECT 01 0000 [.text] __ZN13AMDCIHardware32getMMRPCIConfigBaseAddressOffsetEv 0000000000074cd6 g 0f SECT 01 0000 [.text] __ZN13AMDCIHardware32setupAndInitializeHWCapabilitiesEv 0000000000076f74 g 0f SECT 01 0000 [.text] __ZN13AMDCIHardware32stallGPUDuringScanLineRangeSetupEjjjjtt 0000000000076314 g 0f SECT 01 0000 [.text] __ZN13AMDCIHardware35getRequiredAsicHangLogDumpRegistersERj 000000000007633c g 0f SECT 01 0000 [.text] __ZN13AMDCIHardware47getRequiredAsicHangLogDumpMeStateQueueRegistersERj 0000000000076328 g 0f SECT 01 0000 [.text] __ZN13AMDCIHardware47getRequiredAsicHangLogDumpReorderQueueRegistersERj 0000000000074910 g 0f SECT 01 0000 [.text] __ZN13AMDCIHardware4freeEv 000000000007488a g 0f SECT 01 0000 [.text] __ZN13AMDCIHardware4initEP11IOPCIDeviceP28AMDRadeonX4000_IAMDHWHandlerRjjP16_GART_PARAMETERSP14_FB_PARAMETERS 0000000000075086 g 0f SECT 01 0000 [.text] __ZN13AMDCIHardware7powerUpEv 00000000000750c0 g 0f SECT 01 0000 [.text] __ZN13AMDCIHardware8powerOffEv 00000000000747b0 g 0f SECT 01 0000 [.text] __ZN13AMDCIHardware9MetaClassC1Ev 0000000000074850 g 0f SECT 01 0000 [.text] __ZN13AMDCIHardware9MetaClassC2Ev 000000000007712c g 0f SECT 01 0000 [.text] __ZN13AMDCIHardware9enableDPMEv 00000000003b2410 g 0f SECT 08 0000 [.const_data] __ZN13AMDCIHardware9metaClassE 00000000000747ec g 0f SECT 01 0000 [.text] __ZN13AMDCIHardwareC2EPK11OSMetaClass 0000000000074820 g 0f SECT 01 0000 [.text] __ZN13AMDCIHardwareD0Ev 0000000000074816 g 0f SECT 01 0000 [.text] __ZN13AMDCIHardwareD1Ev 000000000007480c g 0f SECT 01 0000 [.text] __ZN13AMDCIHardwareD2Ev 000000000052d770 g 0f SECT 0a 0000 [__DATA.__common] __ZN13AMDCIResource10gMetaClassE 000000000039d0d8 g 0f SECT 08 0000 [.const_data] __ZN13AMDCIResource10superClassE 000000000003e21a g 0f SECT 01 0000 [.text] __ZN13AMDCIResource16getPagingChannelEb 000000000003db5e g 0f SECT 01 0000 [.text] __ZN13AMDCIResource22pageOffMSAADepthBufferEP13_UBM_SURFINFOS1_P16IOAccelMemoryMapS3_P10_UBM_RECTLS5_jj 000000000003d818 g 0f SECT 01 0000 [.text] __ZN13AMDCIResource26fillUBMSurfaceInfoInternalEP13_UBM_SURFINFOP22_sMASK_MEMORY_SETTINGSP16IOAccelMemoryMapP31AMDRadeonX4000_AMDAccelResourcejjj 000000000003d7e2 g 0f SECT 01 0000 [.text] __ZN13AMDCIResource4initEP22IOGraphicsAccelerator2P14IOAccelShared2j 000000000003d650 g 0f SECT 01 0000 [.text] __ZN13AMDCIResource9MetaClassC1Ev 000000000003d710 g 0f SECT 01 0000 [.text] __ZN13AMDCIResource9MetaClassC2Ev 000000000039d0d0 g 0f SECT 08 0000 [.const_data] __ZN13AMDCIResource9metaClassE 000000000003d6ac g 0f SECT 01 0000 [.text] __ZN13AMDCIResourceC1EPK11OSMetaClass 000000000003d782 g 0f SECT 01 0000 [.text] __ZN13AMDCIResourceC1Ev 000000000003d68c g 0f SECT 01 0000 [.text] __ZN13AMDCIResourceC2EPK11OSMetaClass 000000000003d7b2 g 0f SECT 01 0000 [.text] __ZN13AMDCIResourceC2Ev 000000000003d6e0 g 0f SECT 01 0000 [.text] __ZN13AMDCIResourceD0Ev 000000000003d6d6 g 0f SECT 01 0000 [.text] __ZN13AMDCIResourceD1Ev 000000000003d6cc g 0f SECT 01 0000 [.text] __ZN13AMDCIResourceD2Ev 000000000052e5f8 g 0f SECT 0a 0000 [__DATA.__common] __ZN13AMDCIsDMARing10gMetaClassE 00000000003b4388 g 0f SECT 08 0000 [.const_data] __ZN13AMDCIsDMARing10superClassE 000000000007a7ba g 0f SECT 01 0000 [.text] __ZN13AMDCIsDMARing16registerLocationEv 000000000007a8f0 g 0f SECT 01 0000 [.text] __ZN13AMDCIsDMARing26enableReadPointerWriteBackEv 000000000007a8f6 g 0f SECT 01 0000 [.text] __ZN13AMDCIsDMARing27disableReadPointerWriteBackEv 000000000007a848 g 0f SECT 01 0000 [.text] __ZN13AMDCIsDMARing27programReadAndWritePointersEj 000000000007a6e8 g 0f SECT 01 0000 [.text] __ZN13AMDCIsDMARing4freeEv 000000000007a562 g 0f SECT 01 0000 [.text] __ZN13AMDCIsDMARing4initEP30AMDRadeonX4000_IAMDHWInterfacei20_eAMD_HW_ENGINE_TYPEjPKv 000000000007a8c2 g 0f SECT 01 0000 [.text] __ZN13AMDCIsDMARing5alignEv 000000000007a7e4 g 0f SECT 01 0000 [.text] __ZN13AMDCIsDMARing5resetEv 000000000007a6fa g 0f SECT 01 0000 [.text] __ZN13AMDCIsDMARing6enableEv 000000000007a774 g 0f SECT 01 0000 [.text] __ZN13AMDCIsDMARing7disableEv 000000000007a784 g 0f SECT 01 0000 [.text] __ZN13AMDCIsDMARing7getHeadEv 000000000007a3d0 g 0f SECT 01 0000 [.text] __ZN13AMDCIsDMARing9MetaClassC1Ev 000000000007a490 g 0f SECT 01 0000 [.text] __ZN13AMDCIsDMARing9MetaClassC2Ev 00000000003b4380 g 0f SECT 08 0000 [.const_data] __ZN13AMDCIsDMARing9metaClassE 000000000007a42c g 0f SECT 01 0000 [.text] __ZN13AMDCIsDMARingC1EPK11OSMetaClass 000000000007a502 g 0f SECT 01 0000 [.text] __ZN13AMDCIsDMARingC1Ev 000000000007a40c g 0f SECT 01 0000 [.text] __ZN13AMDCIsDMARingC2EPK11OSMetaClass 000000000007a532 g 0f SECT 01 0000 [.text] __ZN13AMDCIsDMARingC2Ev 000000000007a460 g 0f SECT 01 0000 [.text] __ZN13AMDCIsDMARingD0Ev 000000000007a456 g 0f SECT 01 0000 [.text] __ZN13AMDCIsDMARingD1Ev 000000000007a44c g 0f SECT 01 0000 [.text] __ZN13AMDCIsDMARingD2Ev 000000000052e008 g 0f SECT 0a 0000 [__DATA.__common] __ZN13AMDSIHWMemory10gMetaClassE 00000000003aa678 g 0f SECT 08 0000 [.const_data] __ZN13AMDSIHWMemory10superClassE 0000000000062cd6 g 0f SECT 01 0000 [.text] __ZN13AMDSIHWMemory15getHWMemorySizeEv 0000000000062d08 g 0f SECT 01 0000 [.text] __ZN13AMDSIHWMemory23getHWMemoryApertureSizeEv 0000000000062cc2 g 0f SECT 01 0000 [.text] __ZN13AMDSIHWMemory4initEP30AMDRadeonX4000_IAMDHWInterface 0000000000062d3a g 0f SECT 01 0000 [.text] __ZN13AMDSIHWMemory7prepareEP31AMDRadeonX4000_AMDAccelResourceyyPy 00000000000630ac g 0f SECT 01 0000 [.text] __ZN13AMDSIHWMemory8completeEP31AMDRadeonX4000_AMDAccelResource 0000000000062b30 g 0f SECT 01 0000 [.text] __ZN13AMDSIHWMemory9MetaClassC1Ev 0000000000062bf0 g 0f SECT 01 0000 [.text] __ZN13AMDSIHWMemory9MetaClassC2Ev 00000000003aa670 g 0f SECT 08 0000 [.const_data] __ZN13AMDSIHWMemory9metaClassE 0000000000062b8c g 0f SECT 01 0000 [.text] __ZN13AMDSIHWMemoryC1EPK11OSMetaClass 0000000000062c62 g 0f SECT 01 0000 [.text] __ZN13AMDSIHWMemoryC1Ev 0000000000062b6c g 0f SECT 01 0000 [.text] __ZN13AMDSIHWMemoryC2EPK11OSMetaClass 0000000000062c92 g 0f SECT 01 0000 [.text] __ZN13AMDSIHWMemoryC2Ev 0000000000062bc0 g 0f SECT 01 0000 [.text] __ZN13AMDSIHWMemoryD0Ev 0000000000062bb6 g 0f SECT 01 0000 [.text] __ZN13AMDSIHWMemoryD1Ev 0000000000062bac g 0f SECT 01 0000 [.text] __ZN13AMDSIHWMemoryD2Ev 0000000000069824 g 0f SECT 01 0000 [.text] __ZN13AMDSIHardware10disableDPMEv 000000000052e0d0 g 0f SECT 0a 0000 [__DATA.__common] __ZN13AMDSIHardware10gMetaClassE 00000000000673e6 g 0f SECT 01 0000 [.text] __ZN13AMDSIHardware10initHWInfoEv 00000000003ab6b8 g 0f SECT 08 0000 [.const_data] __ZN13AMDSIHardware10superClassE 0000000000066e8a g 0f SECT 01 0000 [.text] __ZN13AMDSIHardware11allocateSMLEv 0000000000069806 g 0f SECT 01 0000 [.text] __ZN13AMDSIHardware12isDPMEnabledEv 0000000000067bb6 g 0f SECT 01 0000 [.text] __ZN13AMDSIHardware13enableContextEjb 00000000000672cc g 0f SECT 01 0000 [.text] __ZN13AMDSIHardware13flushHDPCacheEv 00000000000675ae g 0f SECT 01 0000 [.text] __ZN13AMDSIHardware13initializeGUIEv 0000000000066eb0 g 0f SECT 01 0000 [.text] __ZN13AMDSIHardware16allocateAMDHWVMMEv 0000000000066d58 g 0f SECT 01 0000 [.text] __ZN13AMDSIHardware16getOGLBundleNameEv 000000000006730e g 0f SECT 01 0000 [.text] __ZN13AMDSIHardware16initMaskSettingsEv 0000000000067a4c g 0f SECT 01 0000 [.text] __ZN13AMDSIHardware16initializeVMRegsEv 000000000006713c g 0f SECT 01 0000 [.text] __ZN13AMDSIHardware17allocateHWEnginesEv 0000000000068a68 g 0f SECT 01 0000 [.text] __ZN13AMDSIHardware17dumpASICHangStateEb 00000000000673bc g 0f SECT 01 0000 [.text] __ZN13AMDSIHardware17getCoherCntrValueEbbb 0000000000067a24 g 0f SECT 01 0000 [.text] __ZN13AMDSIHardware17initializeTlbRegsEv 000000000006761c g 0f SECT 01 0000 [.text] __ZN13AMDSIHardware18enableTransactionsEv 0000000000067424 g 0f SECT 01 0000 [.text] __ZN13AMDSIHardware18getAMDHwInfoValuesEP24_sAMD_GET_HW_INFO_VALUES 0000000000066da4 g 0f SECT 01 0000 [.text] __ZN13AMDSIHardware18getMemSizeRegisterEv 00000000000672ae g 0f SECT 01 0000 [.text] __ZN13AMDSIHardware18readHWChipRevValueEv 0000000000066dca g 0f SECT 01 0000 [.text] __ZN13AMDSIHardware18setMemSizeRegisterEj 0000000000067876 g 0f SECT 01 0000 [.text] __ZN13AMDSIHardware18setupInternalSpaceEv 0000000000066d2c g 0f SECT 01 0000 [.text] __ZN13AMDSIHardware18writeOCDBundleNameEv 0000000000066e18 g 0f SECT 01 0000 [.text] __ZN13AMDSIHardware19allocateAMDHWMemoryEv 00000000000675d0 g 0f SECT 01 0000 [.text] __ZN13AMDSIHardware19disableTransactionsEv 00000000000676ac g 0f SECT 01 0000 [.text] __ZN13AMDSIHardware19fillNDRVSurfaceInfoEP24_AMD_SURFACE_INFO_STRUCTP14_ADDR_TILEINFO 0000000000066df2 g 0f SECT 01 0000 [.text] __ZN13AMDSIHardware19getRegisterAperSizeEv 0000000000067cbe g 0f SECT 01 0000 [.text] __ZN13AMDSIHardware19initializeCacheRegsEv 00000000000672fe g 0f SECT 01 0000 [.text] __ZN13AMDSIHardware19initializeGFXEngineEv 0000000000067f10 g 0f SECT 01 0000 [.text] __ZN13AMDSIHardware19verifyThreadsActiveEv 0000000000066e3e g 0f SECT 01 0000 [.text] __ZN13AMDSIHardware20allocateAMDHWDisplayEv 00000000000672ee g 0f SECT 01 0000 [.text] __ZN13AMDSIHardware20initializeFamilyTypeEv 0000000000066fb4 g 0f SECT 01 0000 [.text] __ZN13AMDSIHardware20readHWGBTilingConfigEv 0000000000068e62 g 0f SECT 01 0000 [.text] __ZN13AMDSIHardware20writeASICHangLogInfoEP23_AMD_ASIC_HANG_LOG_INFO 00000000000690e6 g 0f SECT 01 0000 [.text] __ZN13AMDSIHardware20writeDiagnosisReportERPcRj 0000000000069768 g 0f SECT 01 0000 [.text] __ZN13AMDSIHardware21writeQSCRegMemTimeoutEPjj 0000000000066f1c g 0f SECT 01 0000 [.text] __ZN13AMDSIHardware22allocateAMDHWUtilitiesEv 0000000000066d98 g 0f SECT 01 0000 [.text] __ZN13AMDSIHardware22getATIDisplayConfigBitEv 0000000000066d66 g 0f SECT 01 0000 [.text] __ZN13AMDSIHardware23createAtomicBlitManagerEv 0000000000066f42 g 0f SECT 01 0000 [.text] __ZN13AMDSIHardware23initializeHWWorkaroundsEv 0000000000067908 g 0f SECT 01 0000 [.text] __ZN13AMDSIHardware23initializePageTableRegsEv 0000000000069788 g 0f SECT 01 0000 [.text] __ZN13AMDSIHardware23setPerformanceLevelHighEv 0000000000066fd2 g 0f SECT 01 0000 [.text] __ZN13AMDSIHardware24getHardwareDefaultValuesEP23_sAMD_HW_DEFAULT_VALUES 0000000000066ef6 g 0f SECT 01 0000 [.text] __ZN13AMDSIHardware25allocateAMDHWAlignManagerEv 0000000000068930 g 0f SECT 01 0000 [.text] __ZN13AMDSIHardware25dumpASicHangLogIntoSyslogEP23_AMD_ASIC_HANG_LOG_INFO 0000000000066c90 g 0f SECT 01 0000 [.text] __ZN13AMDSIHardware25getFrameBufferBaseAddressEv 0000000000067c24 g 0f SECT 01 0000 [.text] __ZN13AMDSIHardware25programPageTableRegistersEP22AMD_VM_PAGE_TABLE_INFOj 0000000000066cae g 0f SECT 01 0000 [.text] __ZN13AMDSIHardware25writeWaitForRenderingPipeEPjb 0000000000066e64 g 0f SECT 01 0000 [.text] __ZN13AMDSIHardware26allocatePM4CommandsUtilityEv 0000000000067d74 g 0f SECT 01 0000 [.text] __ZN13AMDSIHardware26initializeGartApertureRegsEv 0000000000067228 g 0f SECT 01 0000 [.text] __ZN13AMDSIHardware26invalidateAllTLBsAndCachesEbj 000000000006886e g 0f SECT 01 0000 [.text] __ZN13AMDSIHardware27asicHangReadROQandMEQStatusER27amdAsicHangDumpROQMEQStatus 0000000000067efa g 0f SECT 01 0000 [.text] __ZN13AMDSIHardware27setMemoryAllocationsEnabledEb 000000000006872c g 0f SECT 01 0000 [.text] __ZN13AMDSIHardware28asicHangLogDumpMeStateQueuesEP23_AMD_ASIC_HANG_LOG_INFO 0000000000068558 g 0f SECT 01 0000 [.text] __ZN13AMDSIHardware28asicHangLogDumpReorderQueuesEP23_AMD_ASIC_HANG_LOG_INFO 00000000000678e6 g 0f SECT 01 0000 [.text] __ZN13AMDSIHardware28initializeHDPPathWorkaroundsEv 0000000000067e16 g 0f SECT 01 0000 [.text] __ZN13AMDSIHardware28initializeSystemApertureRegsEv 0000000000066d8c g 0f SECT 01 0000 [.text] __ZN13AMDSIHardware32getMMRPCIConfigBaseAddressOffsetEv 0000000000066ff6 g 0f SECT 01 0000 [.text] __ZN13AMDSIHardware32setupAndInitializeHWCapabilitiesEv 0000000000069658 g 0f SECT 01 0000 [.text] __ZN13AMDSIHardware32stallGPUDuringScanLineRangeSetupEjjjjtt 000000000006851c g 0f SECT 01 0000 [.text] __ZN13AMDSIHardware35getRequiredAsicHangLogDumpRegistersERj 0000000000068544 g 0f SECT 01 0000 [.text] __ZN13AMDSIHardware47getRequiredAsicHangLogDumpMeStateQueueRegistersERj 0000000000068530 g 0f SECT 01 0000 [.text] __ZN13AMDSIHardware47getRequiredAsicHangLogDumpReorderQueueRegistersERj 0000000000066c50 g 0f SECT 01 0000 [.text] __ZN13AMDSIHardware4freeEv 0000000000066bea g 0f SECT 01 0000 [.text] __ZN13AMDSIHardware4initEP11IOPCIDeviceP28AMDRadeonX4000_IAMDHWHandlerRjjP16_GART_PARAMETERSP14_FB_PARAMETERS 0000000000067370 g 0f SECT 01 0000 [.text] __ZN13AMDSIHardware7powerUpEv 00000000000673aa g 0f SECT 01 0000 [.text] __ZN13AMDSIHardware8powerOffEv 0000000000066b10 g 0f SECT 01 0000 [.text] __ZN13AMDSIHardware9MetaClassC1Ev 0000000000066bb0 g 0f SECT 01 0000 [.text] __ZN13AMDSIHardware9MetaClassC2Ev 00000000000698b6 g 0f SECT 01 0000 [.text] __ZN13AMDSIHardware9enableDPMEv 00000000003ab6b0 g 0f SECT 08 0000 [.const_data] __ZN13AMDSIHardware9metaClassE 0000000000066b4c g 0f SECT 01 0000 [.text] __ZN13AMDSIHardwareC2EPK11OSMetaClass 0000000000066b80 g 0f SECT 01 0000 [.text] __ZN13AMDSIHardwareD0Ev 0000000000066b76 g 0f SECT 01 0000 [.text] __ZN13AMDSIHardwareD1Ev 0000000000066b6c g 0f SECT 01 0000 [.text] __ZN13AMDSIHardwareD2Ev 000000000052d630 g 0f SECT 0a 0000 [__DATA.__common] __ZN13AMDSIResource10gMetaClassE 00000000003972b8 g 0f SECT 08 0000 [.const_data] __ZN13AMDSIResource10superClassE 000000000002a864 g 0f SECT 01 0000 [.text] __ZN13AMDSIResource16getPagingChannelEb 000000000002a41c g 0f SECT 01 0000 [.text] __ZN13AMDSIResource26fillUBMSurfaceInfoInternalEP13_UBM_SURFINFOP22_sMASK_MEMORY_SETTINGSP16IOAccelMemoryMapP31AMDRadeonX4000_AMDAccelResourcejjj 000000000002a3a2 g 0f SECT 01 0000 [.text] __ZN13AMDSIResource4initEP22IOGraphicsAccelerator2P14IOAccelShared2j 000000000002a210 g 0f SECT 01 0000 [.text] __ZN13AMDSIResource9MetaClassC1Ev 000000000002a2d0 g 0f SECT 01 0000 [.text] __ZN13AMDSIResource9MetaClassC2Ev 00000000003972b0 g 0f SECT 08 0000 [.const_data] __ZN13AMDSIResource9metaClassE 000000000002a26c g 0f SECT 01 0000 [.text] __ZN13AMDSIResourceC1EPK11OSMetaClass 000000000002a342 g 0f SECT 01 0000 [.text] __ZN13AMDSIResourceC1Ev 000000000002a24c g 0f SECT 01 0000 [.text] __ZN13AMDSIResourceC2EPK11OSMetaClass 000000000002a372 g 0f SECT 01 0000 [.text] __ZN13AMDSIResourceC2Ev 000000000002a2a0 g 0f SECT 01 0000 [.text] __ZN13AMDSIResourceD0Ev 000000000002a296 g 0f SECT 01 0000 [.text] __ZN13AMDSIResourceD1Ev 000000000002a28c g 0f SECT 01 0000 [.text] __ZN13AMDSIResourceD2Ev 000000000052e990 g 0f SECT 0a 0000 [__DATA.__common] __ZN13AMDVIHWMemory10gMetaClassE 00000000003b9be8 g 0f SECT 08 0000 [.const_data] __ZN13AMDVIHWMemory10superClassE 00000000000877d4 g 0f SECT 01 0000 [.text] __ZN13AMDVIHWMemory15getHWMemorySizeEv 0000000000087806 g 0f SECT 01 0000 [.text] __ZN13AMDVIHWMemory23getHWMemoryApertureSizeEv 00000000000877c2 g 0f SECT 01 0000 [.text] __ZN13AMDVIHWMemory4initEP30AMDRadeonX4000_IAMDHWInterface 0000000000087838 g 0f SECT 01 0000 [.text] __ZN13AMDVIHWMemory7prepareEP31AMDRadeonX4000_AMDAccelResourceyyPy 0000000000087b32 g 0f SECT 01 0000 [.text] __ZN13AMDVIHWMemory8completeEP31AMDRadeonX4000_AMDAccelResource 0000000000087630 g 0f SECT 01 0000 [.text] __ZN13AMDVIHWMemory9MetaClassC1Ev 00000000000876f0 g 0f SECT 01 0000 [.text] __ZN13AMDVIHWMemory9MetaClassC2Ev 00000000003b9be0 g 0f SECT 08 0000 [.const_data] __ZN13AMDVIHWMemory9metaClassE 000000000008768c g 0f SECT 01 0000 [.text] __ZN13AMDVIHWMemoryC1EPK11OSMetaClass 0000000000087762 g 0f SECT 01 0000 [.text] __ZN13AMDVIHWMemoryC1Ev 000000000008766c g 0f SECT 01 0000 [.text] __ZN13AMDVIHWMemoryC2EPK11OSMetaClass 0000000000087792 g 0f SECT 01 0000 [.text] __ZN13AMDVIHWMemoryC2Ev 00000000000876c0 g 0f SECT 01 0000 [.text] __ZN13AMDVIHWMemoryD0Ev 00000000000876b6 g 0f SECT 01 0000 [.text] __ZN13AMDVIHWMemoryD1Ev 00000000000876ac g 0f SECT 01 0000 [.text] __ZN13AMDVIHWMemoryD2Ev 0000000000086898 g 0f SECT 01 0000 [.text] __ZN13AMDVIHardware10disableDPMEv 000000000052e918 g 0f SECT 0a 0000 [__DATA.__common] __ZN13AMDVIHardware10gMetaClassE 0000000000084780 g 0f SECT 01 0000 [.text] __ZN13AMDVIHardware10initHWInfoEv 00000000003b8aa8 g 0f SECT 08 0000 [.const_data] __ZN13AMDVIHardware10superClassE 00000000000841ea g 0f SECT 01 0000 [.text] __ZN13AMDVIHardware11allocateSMLEv 0000000000086890 g 0f SECT 01 0000 [.text] __ZN13AMDVIHardware12isDPMEnabledEv 0000000000084f82 g 0f SECT 01 0000 [.text] __ZN13AMDVIHardware13enableContextEjb 000000000008468e g 0f SECT 01 0000 [.text] __ZN13AMDVIHardware13flushHDPCacheEv 0000000000084984 g 0f SECT 01 0000 [.text] __ZN13AMDVIHardware13initializeGUIEv 0000000000084210 g 0f SECT 01 0000 [.text] __ZN13AMDVIHardware16allocateAMDHWVMMEv 00000000000840b8 g 0f SECT 01 0000 [.text] __ZN13AMDVIHardware16getOGLBundleNameEv 00000000000846d0 g 0f SECT 01 0000 [.text] __ZN13AMDVIHardware16initMaskSettingsEv 0000000000084e18 g 0f SECT 01 0000 [.text] __ZN13AMDVIHardware16initializeVMRegsEv 00000000000842a2 g 0f SECT 01 0000 [.text] __ZN13AMDVIHardware17allocateAMDHWGartEv 00000000000844e8 g 0f SECT 01 0000 [.text] __ZN13AMDVIHardware17allocateHWEnginesEv 0000000000085ee8 g 0f SECT 01 0000 [.text] __ZN13AMDVIHardware17dumpASICHangStateEb 0000000000084756 g 0f SECT 01 0000 [.text] __ZN13AMDVIHardware17getCoherCntrValueEbbb 0000000000084df0 g 0f SECT 01 0000 [.text] __ZN13AMDVIHardware17initializeTlbRegsEv 00000000000849f2 g 0f SECT 01 0000 [.text] __ZN13AMDVIHardware18enableTransactionsEv 00000000000847be g 0f SECT 01 0000 [.text] __ZN13AMDVIHardware18getAMDHwInfoValuesEP24_sAMD_GET_HW_INFO_VALUES 0000000000084104 g 0f SECT 01 0000 [.text] __ZN13AMDVIHardware18getMemSizeRegisterEv 0000000000084670 g 0f SECT 01 0000 [.text] __ZN13AMDVIHardware18readHWChipRevValueEv 000000000008412a g 0f SECT 01 0000 [.text] __ZN13AMDVIHardware18setMemSizeRegisterEj 0000000000084c2c g 0f SECT 01 0000 [.text] __ZN13AMDVIHardware18setupInternalSpaceEv 000000000008408c g 0f SECT 01 0000 [.text] __ZN13AMDVIHardware18writeOCDBundleNameEv 0000000000084178 g 0f SECT 01 0000 [.text] __ZN13AMDVIHardware19allocateAMDHWMemoryEv 00000000000849a6 g 0f SECT 01 0000 [.text] __ZN13AMDVIHardware19disableTransactionsEv 0000000000084a82 g 0f SECT 01 0000 [.text] __ZN13AMDVIHardware19fillNDRVSurfaceInfoEP24_AMD_SURFACE_INFO_STRUCTP14_ADDR_TILEINFO 00000000000859cc g 0f SECT 01 0000 [.text] __ZN13AMDVIHardware19freeWritebackMemoryEv 0000000000084152 g 0f SECT 01 0000 [.text] __ZN13AMDVIHardware19getRegisterAperSizeEv 000000000008508a g 0f SECT 01 0000 [.text] __ZN13AMDVIHardware19initializeCacheRegsEv 00000000000846c0 g 0f SECT 01 0000 [.text] __ZN13AMDVIHardware19initializeGFXEngineEv 000000000008533e g 0f SECT 01 0000 [.text] __ZN13AMDVIHardware19verifyThreadsActiveEv 000000000008419e g 0f SECT 01 0000 [.text] __ZN13AMDVIHardware20allocateAMDHWDisplayEv 00000000000846b0 g 0f SECT 01 0000 [.text] __ZN13AMDVIHardware20initializeFamilyTypeEv 000000000008433a g 0f SECT 01 0000 [.text] __ZN13AMDVIHardware20readHWGBTilingConfigEv 0000000000086230 g 0f SECT 01 0000 [.text] __ZN13AMDVIHardware20writeASICHangLogInfoEP23_AMD_ASIC_HANG_LOG_INFO 00000000000864b4 g 0f SECT 01 0000 [.text] __ZN13AMDVIHardware20writeDiagnosisReportERPcRj 00000000000867b6 g 0f SECT 01 0000 [.text] __ZN13AMDVIHardware21writeQSCRegMemTimeoutEPjj 000000000008427c g 0f SECT 01 0000 [.text] __ZN13AMDVIHardware22allocateAMDHWUtilitiesEv 00000000000840f8 g 0f SECT 01 0000 [.text] __ZN13AMDVIHardware22getATIDisplayConfigBitEv 0000000000085948 g 0f SECT 01 0000 [.text] __ZN13AMDVIHardware23allocateWritebackMemoryEv 00000000000840c6 g 0f SECT 01 0000 [.text] __ZN13AMDVIHardware23createAtomicBlitManagerEv 00000000000842c8 g 0f SECT 01 0000 [.text] __ZN13AMDVIHardware23initializeHWWorkaroundsEv 0000000000084cbe g 0f SECT 01 0000 [.text] __ZN13AMDVIHardware23initializePageTableRegsEv 0000000000086810 g 0f SECT 01 0000 [.text] __ZN13AMDVIHardware23setPerformanceLevelHighEv 0000000000084358 g 0f SECT 01 0000 [.text] __ZN13AMDVIHardware24getHardwareDefaultValuesEP23_sAMD_HW_DEFAULT_VALUES 0000000000084256 g 0f SECT 01 0000 [.text] __ZN13AMDVIHardware25allocateAMDHWAlignManagerEv 0000000000085e74 g 0f SECT 01 0000 [.text] __ZN13AMDVIHardware25dumpASicHangLogIntoSyslogEP23_AMD_ASIC_HANG_LOG_INFO 0000000000083fd0 g 0f SECT 01 0000 [.text] __ZN13AMDVIHardware25getFrameBufferBaseAddressEv 0000000000084ff0 g 0f SECT 01 0000 [.text] __ZN13AMDVIHardware25programPageTableRegistersEP22AMD_VM_PAGE_TABLE_INFOj 0000000000083fee g 0f SECT 01 0000 [.text] __ZN13AMDVIHardware25writeWaitForRenderingPipeEPjb 00000000000841c4 g 0f SECT 01 0000 [.text] __ZN13AMDVIHardware26allocatePM4CommandsUtilityEv 0000000000085140 g 0f SECT 01 0000 [.text] __ZN13AMDVIHardware26initializeGartApertureRegsEv 00000000000845ea g 0f SECT 01 0000 [.text] __ZN13AMDVIHardware26invalidateAllTLBsAndCachesEbj 0000000000085daa g 0f SECT 01 0000 [.text] __ZN13AMDVIHardware27asicHangReadROQandMEQStatusER27amdAsicHangDumpROQMEQStatus 0000000000085328 g 0f SECT 01 0000 [.text] __ZN13AMDVIHardware27setMemoryAllocationsEnabledEb 0000000000085c36 g 0f SECT 01 0000 [.text] __ZN13AMDVIHardware28asicHangLogDumpMeStateQueuesEP23_AMD_ASIC_HANG_LOG_INFO 0000000000085a82 g 0f SECT 01 0000 [.text] __ZN13AMDVIHardware28asicHangLogDumpReorderQueuesEP23_AMD_ASIC_HANG_LOG_INFO 0000000000084c9c g 0f SECT 01 0000 [.text] __ZN13AMDVIHardware28initializeHDPPathWorkaroundsEv 0000000000085244 g 0f SECT 01 0000 [.text] __ZN13AMDVIHardware28initializeSystemApertureRegsEv 0000000000085a2a g 0f SECT 01 0000 [.text] __ZN13AMDVIHardware30getChannelWritePointerPollAddrEi 0000000000085a12 g 0f SECT 01 0000 [.text] __ZN13AMDVIHardware32getChannelWritePointerPollOffsetEi 00000000000840ec g 0f SECT 01 0000 [.text] __ZN13AMDVIHardware32getMMRPCIConfigBaseAddressOffsetEv 000000000008437c g 0f SECT 01 0000 [.text] __ZN13AMDVIHardware32setupAndInitializeHWCapabilitiesEv 00000000000866a6 g 0f SECT 01 0000 [.text] __ZN13AMDVIHardware32stallGPUDuringScanLineRangeSetupEjjjjtt 0000000000085a46 g 0f SECT 01 0000 [.text] __ZN13AMDVIHardware35getRequiredAsicHangLogDumpRegistersERj 0000000000085a6e g 0f SECT 01 0000 [.text] __ZN13AMDVIHardware47getRequiredAsicHangLogDumpMeStateQueueRegistersERj 0000000000085a5a g 0f SECT 01 0000 [.text] __ZN13AMDVIHardware47getRequiredAsicHangLogDumpReorderQueueRegistersERj 0000000000083f90 g 0f SECT 01 0000 [.text] __ZN13AMDVIHardware4freeEv 0000000000083f0a g 0f SECT 01 0000 [.text] __ZN13AMDVIHardware4initEP11IOPCIDeviceP28AMDRadeonX4000_IAMDHWHandlerRjjP16_GART_PARAMETERSP14_FB_PARAMETERS 0000000000084732 g 0f SECT 01 0000 [.text] __ZN13AMDVIHardware7powerUpEv 0000000000084744 g 0f SECT 01 0000 [.text] __ZN13AMDVIHardware8powerOffEv 0000000000083e30 g 0f SECT 01 0000 [.text] __ZN13AMDVIHardware9MetaClassC1Ev 0000000000083ed0 g 0f SECT 01 0000 [.text] __ZN13AMDVIHardware9MetaClassC2Ev 000000000008689e g 0f SECT 01 0000 [.text] __ZN13AMDVIHardware9enableDPMEv 00000000003b8aa0 g 0f SECT 08 0000 [.const_data] __ZN13AMDVIHardware9metaClassE 0000000000083e6c g 0f SECT 01 0000 [.text] __ZN13AMDVIHardwareC2EPK11OSMetaClass 0000000000083ea0 g 0f SECT 01 0000 [.text] __ZN13AMDVIHardwareD0Ev 0000000000083e96 g 0f SECT 01 0000 [.text] __ZN13AMDVIHardwareD1Ev 0000000000083e8c g 0f SECT 01 0000 [.text] __ZN13AMDVIHardwareD2Ev 000000000052d838 g 0f SECT 0a 0000 [__DATA.__common] __ZN13AMDVIResource10gMetaClassE 00000000003a0368 g 0f SECT 08 0000 [.const_data] __ZN13AMDVIResource10superClassE 0000000000047b3e g 0f SECT 01 0000 [.text] __ZN13AMDVIResource16getPagingChannelEb 0000000000047482 g 0f SECT 01 0000 [.text] __ZN13AMDVIResource22pageOffMSAADepthBufferEP13_UBM_SURFINFOS1_P16IOAccelMemoryMapS3_P10_UBM_RECTLS5_jj 0000000000047128 g 0f SECT 01 0000 [.text] __ZN13AMDVIResource26fillUBMSurfaceInfoInternalEP13_UBM_SURFINFOP22_sMASK_MEMORY_SETTINGSP16IOAccelMemoryMapP31AMDRadeonX4000_AMDAccelResourcejjj 00000000000470f2 g 0f SECT 01 0000 [.text] __ZN13AMDVIResource4initEP22IOGraphicsAccelerator2P14IOAccelShared2j 0000000000046f60 g 0f SECT 01 0000 [.text] __ZN13AMDVIResource9MetaClassC1Ev 0000000000047020 g 0f SECT 01 0000 [.text] __ZN13AMDVIResource9MetaClassC2Ev 00000000003a0360 g 0f SECT 08 0000 [.const_data] __ZN13AMDVIResource9metaClassE 0000000000046fbc g 0f SECT 01 0000 [.text] __ZN13AMDVIResourceC1EPK11OSMetaClass 0000000000047092 g 0f SECT 01 0000 [.text] __ZN13AMDVIResourceC1Ev 0000000000046f9c g 0f SECT 01 0000 [.text] __ZN13AMDVIResourceC2EPK11OSMetaClass 00000000000470c2 g 0f SECT 01 0000 [.text] __ZN13AMDVIResourceC2Ev 0000000000046ff0 g 0f SECT 01 0000 [.text] __ZN13AMDVIResourceD0Ev 0000000000046fe6 g 0f SECT 01 0000 [.text] __ZN13AMDVIResourceD1Ev 0000000000046fdc g 0f SECT 01 0000 [.text] __ZN13AMDVIResourceD2Ev 000000000052eaa8 g 0f SECT 0a 0000 [__DATA.__common] __ZN13AMDVIsDMARing10gMetaClassE 00000000003bb368 g 0f SECT 08 0000 [.const_data] __ZN13AMDVIsDMARing10superClassE 000000000008d1e0 g 0f SECT 01 0000 [.text] __ZN13AMDVIsDMARing16registerLocationEv 000000000008d1ce g 0f SECT 01 0000 [.text] __ZN13AMDVIsDMARing17allocateResourcesEv 000000000008d316 g 0f SECT 01 0000 [.text] __ZN13AMDVIsDMARing26enableReadPointerWriteBackEv 000000000008d31c g 0f SECT 01 0000 [.text] __ZN13AMDVIsDMARing27disableReadPointerWriteBackEv 000000000008d26e g 0f SECT 01 0000 [.text] __ZN13AMDVIsDMARing27programReadAndWritePointersEj 000000000008d0fc g 0f SECT 01 0000 [.text] __ZN13AMDVIsDMARing4freeEv 000000000008d012 g 0f SECT 01 0000 [.text] __ZN13AMDVIsDMARing4initEP30AMDRadeonX4000_IAMDHWInterfacei20_eAMD_HW_ENGINE_TYPEjPKv 000000000008d2e8 g 0f SECT 01 0000 [.text] __ZN13AMDVIsDMARing5alignEv 000000000008d20a g 0f SECT 01 0000 [.text] __ZN13AMDVIsDMARing5resetEv 000000000008d10e g 0f SECT 01 0000 [.text] __ZN13AMDVIsDMARing6enableEv 000000000008d188 g 0f SECT 01 0000 [.text] __ZN13AMDVIsDMARing7disableEv 000000000008d198 g 0f SECT 01 0000 [.text] __ZN13AMDVIsDMARing7getHeadEv 000000000008ce80 g 0f SECT 01 0000 [.text] __ZN13AMDVIsDMARing9MetaClassC1Ev 000000000008cf40 g 0f SECT 01 0000 [.text] __ZN13AMDVIsDMARing9MetaClassC2Ev 00000000003bb360 g 0f SECT 08 0000 [.const_data] __ZN13AMDVIsDMARing9metaClassE 000000000008d322 g 0f SECT 01 0000 [.text] __ZN13AMDVIsDMARing9writeTailEv 000000000008cedc g 0f SECT 01 0000 [.text] __ZN13AMDVIsDMARingC1EPK11OSMetaClass 000000000008cfb2 g 0f SECT 01 0000 [.text] __ZN13AMDVIsDMARingC1Ev 000000000008cebc g 0f SECT 01 0000 [.text] __ZN13AMDVIsDMARingC2EPK11OSMetaClass 000000000008cfe2 g 0f SECT 01 0000 [.text] __ZN13AMDVIsDMARingC2Ev 000000000008cf10 g 0f SECT 01 0000 [.text] __ZN13AMDVIsDMARingD0Ev 000000000008cf06 g 0f SECT 01 0000 [.text] __ZN13AMDVIsDMARingD1Ev 000000000008cefc g 0f SECT 01 0000 [.text] __ZN13AMDVIsDMARingD2Ev 00000000000ab2ba g 0f SECT 01 0000 [.text] __ZN13SiBltConstMgr15SetAluConstantsE16_UBM_SHADER_TYPEjjPK11_UBM_VECTORj 00000000000ab356 g 0f SECT 01 0000 [.text] __ZN13SiBltConstMgr15SetAluConstantsE16_UBM_SHADER_TYPEjjPK12_UBM_VECTORLj 00000000000abb3a g 0f SECT 01 0000 [.text] __ZN13SiBltConstMgr16SetupUavConstantEP11SiBltDevice16_UBM_SHADER_TYPEPK13_UBM_SURFINFOj 00000000000ab9f0 g 0f SECT 01 0000 [.text] __ZN13SiBltConstMgr17SetSamplerDeGammaE16_UBM_SHADER_TYPEj 00000000000ab360 g 0f SECT 01 0000 [.text] __ZN13SiBltConstMgr17SetupRsrcConstantEP11SiBltDevice16_UBM_SHADER_TYPEPK13_UBM_SURFINFOPK18SiBltRsrcConstInfoj 00000000000abbee g 0f SECT 01 0000 [.text] __ZN13SiBltConstMgr18WriteImmedAluConstEP11SiBltDevice16_UBM_SHADER_TYPEjjjj 00000000000abf20 g 0f SECT 01 0000 [.text] __ZN13SiBltConstMgr18WriteImmedUavConstEP11SiBltDevice16_UBM_SHADER_TYPEjjj 00000000000aba48 g 0f SECT 01 0000 [.text] __ZN13SiBltConstMgr19SetSamplerClampTypeE16_UBM_SHADER_TYPEj12SQ_TEX_CLAMP 00000000000abdac g 0f SECT 01 0000 [.text] __ZN13SiBltConstMgr19WriteImmedRsrcConstEP11SiBltDevice16_UBM_SHADER_TYPEjjj 00000000000ac000 g 0f SECT 01 0000 [.text] __ZN13SiBltConstMgr19WriteImmedSampConstEP11SiBltDevice16_UBM_SHADER_TYPEjjj 00000000000abab8 g 0f SECT 01 0000 [.text] __ZN13SiBltConstMgr20SetSamplerFilterModeE16_UBM_SHADER_TYPEjj16SQ_TEX_XY_FILTER 00000000000ab5a8 g 0f SECT 01 0000 [.text] __ZN13SiBltConstMgr20SetupBufRsrcConstantEP11SiBltDevicePK13_UBM_SURFINFOP9SqBufRsrc 00000000000ab6fc g 0f SECT 01 0000 [.text] __ZN13SiBltConstMgr20SetupImgRsrcConstantEP11SiBltDevicePK13_UBM_SURFINFOPK18SiBltRsrcConstInfoP9SqImgRsrcjPK16_UBM_MASKRAMINFO 00000000000ac2f8 g 0f SECT 01 0000 [.text] __ZN13SiBltConstMgr21WriteEmbeddedUavTableEP11SiBltDevice16_UBM_SHADER_TYPEjjj 00000000000abc7a g 0f SECT 01 0000 [.text] __ZN13SiBltConstMgr21WriteImmedConstBufferEP11SiBltDevice16_UBM_SHADER_TYPEjjj 00000000000ab50a g 0f SECT 01 0000 [.text] __ZN13SiBltConstMgr22GetTcCompatibleMaskRamEP11SiBltDevicePK13_UBM_SURFINFO 00000000000ac04c g 0f SECT 01 0000 [.text] __ZN13SiBltConstMgr22WriteEmbeddedRsrcTableEP11SiBltDevice16_UBM_SHADER_TYPEjjj 00000000000ac256 g 0f SECT 01 0000 [.text] __ZN13SiBltConstMgr22WriteEmbeddedSampTableEP11SiBltDevice16_UBM_SHADER_TYPEjjj 00000000000ab23e g 0f SECT 01 0000 [.text] __ZN13SiBltConstMgr25SetDefaultSamplerConstantE16_UBM_SHADER_TYPEj 00000000000ab128 g 0f SECT 01 0000 [.text] __ZN13SiBltConstMgr7InitBltEv 00000000000ab122 g 0f SECT 01 0000 [.text] __ZN13SiBltConstMgrC1Ev 00000000000ab11c g 0f SECT 01 0000 [.text] __ZN13SiBltConstMgrC2Ev 00000000000b4400 g 0f SECT 01 0000 [.text] __ZN13SiBltDrawRegs12SetupZExpandEPK7BltInfo 00000000000b449a g 0f SECT 01 0000 [.text] __ZN13SiBltDrawRegs12SetupZExportEPK7BltInfo 00000000000b41f6 g 0f SECT 01 0000 [.text] __ZN13SiBltDrawRegs13SetupRasterOpE8_UBM_ROP 00000000000b4010 g 0f SECT 01 0000 [.text] __ZN13SiBltDrawRegs14SetupCbResolveEPK7BltInfo 00000000000b4034 g 0f SECT 01 0000 [.text] __ZN13SiBltDrawRegs14SetupDccExpandEPK7BltInfo 00000000000b4458 g 0f SECT 01 0000 [.text] __ZN13SiBltDrawRegs14SetupTileZToCbEPK7BltInfo 00000000000b4586 g 0f SECT 01 0000 [.text] __ZN13SiBltDrawRegs15EnableHybridHiSEP7BltInfo 00000000000b21de g 0f SECT 01 0000 [.text] __ZN13SiBltDrawRegs15InitContextRegsEv 00000000000b40ce g 0f SECT 01 0000 [.text] __ZN13SiBltDrawRegs15SetupAlphaBlendEPK7BltInfo 00000000000b453c g 0f SECT 01 0000 [.text] __ZN13SiBltDrawRegs15SetupResumHTileEPK7BltInfo 00000000000b4610 g 0f SECT 01 0000 [.text] __ZN13SiBltDrawRegs15UpdateViewSliceEPK7BltInfoj 00000000000b422e g 0f SECT 01 0000 [.text] __ZN13SiBltDrawRegs16DbgEnableStencilEPK7BltInfo 00000000000b4022 g 0f SECT 01 0000 [.text] __ZN13SiBltDrawRegs16SetupColorExpandEPK7BltInfo 00000000000b2262 g 0f SECT 01 0000 [.text] __ZN13SiBltDrawRegs16WriteContextToHwEPK7BltInfo 00000000000b38cc g 0f SECT 01 0000 [.text] __ZN13SiBltDrawRegs17SetupHTileEnablesEjjjj 00000000000b3f4a g 0f SECT 01 0000 [.text] __ZN13SiBltDrawRegs17SetupStencilClearEPK7BltInfo 00000000000b23da g 0f SECT 01 0000 [.text] __ZN13SiBltDrawRegs18SetupAndWriteColorEPK7BltInfo 00000000000b2ec0 g 0f SECT 01 0000 [.text] __ZN13SiBltDrawRegs18SetupAndWriteDepthEPK7BltInfo 00000000000b4046 g 0f SECT 01 0000 [.text] __ZN13SiBltDrawRegs18SetupExpandTextureEPK7BltInfo 00000000000b4072 g 0f SECT 01 0000 [.text] __ZN13SiBltDrawRegs19SetupColorWriteMaskEPK7BltInfo 00000000000b23a4 g 0f SECT 01 0000 [.text] __ZN13SiBltDrawRegs20SetupDestSurfScissorEPK7BltInfoPK13_UBM_SURFINFO 00000000000b4060 g 0f SECT 01 0000 [.text] __ZN13SiBltDrawRegs20SetupFmaskDecompressEv 00000000000b41be g 0f SECT 01 0000 [.text] __ZN13SiBltDrawRegs21EnableGammaCorrectionEPK7BltInfo 00000000000b3924 g 0f SECT 01 0000 [.text] __ZN13SiBltDrawRegs22SetupAndWriteClipRectsEPK7BltInfoPK10_UBM_RECTLj 00000000000b3cc0 g 0f SECT 01 0000 [.text] __ZN13SiBltDrawRegs25SetupAndWriteAASampleLocsEPK7BltInfo 00000000000b43b2 g 0f SECT 01 0000 [.text] __ZN13SiBltDrawRegs30SetupDepthStencilClearDisablesEPK7BltInfo 00000000000b3e52 g 0f SECT 01 0000 [.text] __ZN13SiBltDrawRegs31SetupAndWriteCentroidPrioritiesEPK7BltInfo 00000000000b21d0 g 0f SECT 01 0000 [.text] __ZN13SiBltDrawRegs4InitEP11SiBltDevicePK7BltInfo 00000000000b3bb2 g 0f SECT 01 0000 [.text] __ZN13SiBltDrawRegs7EnableZEj11CompareFragj 00000000000b3be2 g 0f SECT 01 0000 [.text] __ZN13SiBltDrawRegs8EnableAAEPK7BltInfo 00000000000b2258 g 0f SECT 01 0000 [.text] __ZN13SiBltDrawRegs9WriteToHwEPK7BltInfo 00000000000b21ca g 0f SECT 01 0000 [.text] __ZN13SiBltDrawRegsC1Ev 00000000000b21c4 g 0f SECT 01 0000 [.text] __ZN13SiBltDrawRegsC2Ev 00000000000a7604 g 0f SECT 01 0000 [.text] __ZN13SurfAttribute12CreateObjectEv 00000000000a7722 g 0f SECT 01 0000 [.text] __ZN13SurfAttribute4InitEPK15_UBM_CREATEINFO 00000000000a75ac g 0f SECT 01 0000 [.text] __ZN13SurfAttribute6CreateEPK15_UBM_CREATEINFO 00000000000a75f2 g 0f SECT 01 0000 [.text] __ZN13SurfAttribute7DestroyEv 00000000000a763a g 0f SECT 01 0000 [.text] __ZN13SurfAttributeC1Ev 00000000000a7696 g 0f SECT 01 0000 [.text] __ZN13SurfAttributeC2Ev 00000000000a76f4 g 0f SECT 01 0000 [.text] __ZN13SurfAttributeD0Ev 00000000000a76d8 g 0f SECT 01 0000 [.text] __ZN13SurfAttributeD1Ev 00000000000a76bc g 0f SECT 01 0000 [.text] __ZN13SurfAttributeD2Ev 000000000052d798 g 0f SECT 0a 0000 [__DATA.__common] __ZN14AMDCICLContext10gMetaClassE 000000000039d5a8 g 0f SECT 08 0000 [.const_data] __ZN14AMDCICLContext10superClassE 0000000000043e8a g 0f SECT 01 0000 [.text] __ZN14AMDCICLContext11contextStopEv 000000000004574a g 0f SECT 01 0000 [.text] __ZN14AMDCICLContext11setRsrcRegsEP25SI_HwVertexBufRsrcDescRecyjj 00000000000443a8 g 0f SECT 01 0000 [.text] __ZN14AMDCICLContext11splitStreamER24IOAccelCommandStreamInfo 0000000000043c02 g 0f SECT 01 0000 [.text] __ZN14AMDCICLContext12contextStartEv 0000000000044b74 g 0f SECT 01 0000 [.text] __ZN14AMDCICLContext12remapBuffersEPKjP13_COMPUTE_INFOy 000000000004402a g 0f SECT 01 0000 [.text] __ZN14AMDCICLContext13enableContextEv 000000000004572e g 0f SECT 01 0000 [.text] __ZN14AMDCICLContext13getPixelBytesEjj 000000000039d510 g 0f SECT 08 0000 [.const_data] __ZN14AMDCICLContext13process_tableE 00000000000440fa g 0f SECT 01 0000 [.text] __ZN14AMDCICLContext14disableContextEv 0000000000045c60 g 0f SECT 01 0000 [.text] __ZN14AMDCICLContext14hasProxyBufferEP16IOAccelResource2 000000000003e47c g 0f SECT 01 0000 [.text] __ZN14AMDCICLContext15process_ComputeER24IOAccelCommandStreamInfo 00000000000456f6 g 0f SECT 01 0000 [.text] __ZN14AMDCICLContext15setConstBufRegsEP25SI_HwVertexBufRsrcDescRecyj 000000000003e400 g 0f SECT 01 0000 [.text] __ZN14AMDCICLContext16process_SetFenceER24IOAccelCommandStreamInfo 0000000000045cd2 g 0f SECT 01 0000 [.text] __ZN14AMDCICLContext16setupImageRecordEPKjP16IOAccelResource2P18ComputeImageRecordP16WriteImageRecordb 00000000000463a0 g 0f SECT 01 0000 [.text] __ZN14AMDCICLContext17commonLoadBuffersEP16IOAccelResource2S1_RyS2_ 00000000000429e4 g 0f SECT 01 0000 [.text] __ZN14AMDCICLContext17process_CopyImageER24IOAccelCommandStreamInfo 000000000003f9fc g 0f SECT 01 0000 [.text] __ZN14AMDCICLContext17process_RWCBufferER24IOAccelCommandStreamInfo 0000000000040416 g 0f SECT 01 0000 [.text] __ZN14AMDCICLContext17process_ReadImageER24IOAccelCommandStreamInfo 00000000000457b4 g 0f SECT 01 0000 [.text] __ZN14AMDCICLContext17syncWriteResourceEP16WriteImageRecordh 000000000004176c g 0f SECT 01 0000 [.text] __ZN14AMDCICLContext18process_WriteImageER24IOAccelCommandStreamInfo 0000000000045792 g 0f SECT 01 0000 [.text] __ZN14AMDCICLContext18setScratchRsrcRegsEP25SI_HwVertexBufRsrcDescRecyj 0000000000043f24 g 0f SECT 01 0000 [.text] __ZN14AMDCICLContext19getDataBufferLimitsEv 0000000000043f82 g 0f SECT 01 0000 [.text] __ZN14AMDCICLContext20processSidebandTokenER24IOAccelCommandStreamInfo 0000000000044584 g 0f SECT 01 0000 [.text] __ZN14AMDCICLContext20writeAtomicComputeOpEPjPK13_COMPUTE_INFOPK13_clKernelInfoP21SubmitRingBufferEntry 0000000000043f00 g 0f SECT 01 0000 [.text] __ZN14AMDCICLContext21populateContextConfigEP20IOAccelContextConfig 000000000004388a g 0f SECT 01 0000 [.text] __ZN14AMDCICLContext21process_QueuePriorityER24IOAccelCommandStreamInfo 0000000000044cd6 g 0f SECT 01 0000 [.text] __ZN14AMDCICLContext22getGlobalBasePatchArgsEPKjP21SubmitRingBufferEntryPK13_clKernelInfoP13_COMPUTE_INFOPyS9_ 0000000000043a6a g 0f SECT 01 0000 [.text] __ZN14AMDCICLContext22process_UnhandledTokenER24IOAccelCommandStreamInfo 0000000000046362 g 0f SECT 01 0000 [.text] __ZN14AMDCICLContext23commonProcessBufferInitER24IOAccelCommandStreamInfo 000000000004451a g 0f SECT 01 0000 [.text] __ZN14AMDCICLContext24getHardwareConfigurationEPjS0_S0_S0_ 0000000000043706 g 0f SECT 01 0000 [.text] __ZN14AMDCICLContext24process_LinearWriteFlushER24IOAccelCommandStreamInfo 00000000000441dc g 0f SECT 01 0000 [.text] __ZN14AMDCICLContext25freeSubmitRingBufferEntryEP21SubmitRingBufferEntry 0000000000043f44 g 0f SECT 01 0000 [.text] __ZN14AMDCICLContext26getTargetAndMethodForIndexEPP9IOServicej 00000000000442c4 g 0f SECT 01 0000 [.text] __ZN14AMDCICLContext29updateSubmitRingBufferEntriesEv 0000000000044216 g 0f SECT 01 0000 [.text] __ZN14AMDCICLContext37removeConsumedSubmitRingBufferEntriesEv 0000000000043dc2 g 0f SECT 01 0000 [.text] __ZN14AMDCICLContext6finishEv 0000000000043a70 g 0f SECT 01 0000 [.text] __ZN14AMDCICLContext9MetaClassC1Ev 0000000000043b30 g 0f SECT 01 0000 [.text] __ZN14AMDCICLContext9MetaClassC2Ev 000000000039d5a0 g 0f SECT 08 0000 [.const_data] __ZN14AMDCICLContext9metaClassE 0000000000043acc g 0f SECT 01 0000 [.text] __ZN14AMDCICLContextC1EPK11OSMetaClass 0000000000043ba2 g 0f SECT 01 0000 [.text] __ZN14AMDCICLContextC1Ev 0000000000043aac g 0f SECT 01 0000 [.text] __ZN14AMDCICLContextC2EPK11OSMetaClass 0000000000043bd2 g 0f SECT 01 0000 [.text] __ZN14AMDCICLContextC2Ev 0000000000043b00 g 0f SECT 01 0000 [.text] __ZN14AMDCICLContextD0Ev 0000000000043af6 g 0f SECT 01 0000 [.text] __ZN14AMDCICLContextD1Ev 0000000000043aec g 0f SECT 01 0000 [.text] __ZN14AMDCICLContextD2Ev 000000000052e580 g 0f SECT 0a 0000 [__DATA.__common] __ZN14AMDCIPM4Engine10gMetaClassE 00000000003b39a8 g 0f SECT 08 0000 [.const_data] __ZN14AMDCIPM4Engine10superClassE 00000000000794b4 g 0f SECT 01 0000 [.text] __ZN14AMDCIPM4Engine11cpSoftResetEv 000000000007930c g 0f SECT 01 0000 [.text] __ZN14AMDCIPM4Engine14gfxEngineResetEv 00000000000786fa g 0f SECT 01 0000 [.text] __ZN14AMDCIPM4Engine15MicroEngineStopE18_eAMD_HW_RING_TYPE 0000000000078ff2 g 0f SECT 01 0000 [.text] __ZN14AMDCIPM4Engine15allocateHWRingsEv 000000000007921c g 0f SECT 01 0000 [.text] __ZN14AMDCIPM4Engine15stopBeforeResetEv 0000000000078b06 g 0f SECT 01 0000 [.text] __ZN14AMDCIPM4Engine16MicroEngineStartE18_eAMD_HW_RING_TYPE 00000000000790a4 g 0f SECT 01 0000 [.text] __ZN14AMDCIPM4Engine18allocateHWChannelsEv 000000000007819a g 0f SECT 01 0000 [.text] __ZN14AMDCIPM4Engine20setVirtualSpaceReadyEb 00000000000788da g 0f SECT 01 0000 [.text] __ZN14AMDCIPM4Engine21MicroEngineInitializeE18_eAMD_HW_RING_TYPE 0000000000078d5c g 0f SECT 01 0000 [.text] __ZN14AMDCIPM4Engine21initializeMicroEngineEv 0000000000078eda g 0f SECT 01 0000 [.text] __ZN14AMDCIPM4Engine22allocateAndInitHWRingsEv 0000000000079204 g 0f SECT 01 0000 [.text] __ZN14AMDCIPM4Engine22getTimestampIRQSourcexE18_eAMD_HW_RING_TYPE 0000000000078ebe g 0f SECT 01 0000 [.text] __ZN14AMDCIPM4Engine23resetGRBMOnCommandStartEv 0000000000079546 g 0f SECT 01 0000 [.text] __ZN14AMDCIPM4Engine23toCailDetectHungEnginesEv 00000000000787ea g 0f SECT 01 0000 [.text] __ZN14AMDCIPM4Engine24MicroEngineLoadMicrocodeE18_eAMD_HW_RING_TYPE 000000000007822e g 0f SECT 01 0000 [.text] __ZN14AMDCIPM4Engine27setMemoryAllocationsEnabledEb 00000000000791fe g 0f SECT 01 0000 [.text] __ZN14AMDCIPM4Engine28initializeTimestampRegistersEj 0000000000078bf6 g 0f SECT 01 0000 [.text] __ZN14AMDCIPM4Engine32MicroEngineQueryMicrocodeVersionE18_eAMD_HW_RING_TYPE 0000000000078188 g 0f SECT 01 0000 [.text] __ZN14AMDCIPM4Engine4freeEv 00000000000780f2 g 0f SECT 01 0000 [.text] __ZN14AMDCIPM4Engine4initEP30AMDRadeonX4000_IAMDHWInterface20_eAMD_HW_ENGINE_TYPE 00000000000784f8 g 0f SECT 01 0000 [.text] __ZN14AMDCIPM4Engine4stopEv 0000000000079244 g 0f SECT 01 0000 [.text] __ZN14AMDCIPM4Engine5resetE18_eAMD_HW_RING_TYPE 00000000000784a4 g 0f SECT 01 0000 [.text] __ZN14AMDCIPM4Engine5startEv 000000000007859a g 0f SECT 01 0000 [.text] __ZN14AMDCIPM4Engine6haltMEEv 0000000000078e7c g 0f SECT 01 0000 [.text] __ZN14AMDCIPM4Engine6isIdleEv 0000000000078428 g 0f SECT 01 0000 [.text] __ZN14AMDCIPM4Engine7powerUpEv 0000000000078682 g 0f SECT 01 0000 [.text] __ZN14AMDCIPM4Engine7startMEEv 0000000000077f60 g 0f SECT 01 0000 [.text] __ZN14AMDCIPM4Engine9MetaClassC1Ev 0000000000078020 g 0f SECT 01 0000 [.text] __ZN14AMDCIPM4Engine9MetaClassC2Ev 00000000003b39a0 g 0f SECT 08 0000 [.const_data] __ZN14AMDCIPM4Engine9metaClassE 000000000007917a g 0f SECT 01 0000 [.text] __ZN14AMDCIPM4Engine9softResetEjj 0000000000077fbc g 0f SECT 01 0000 [.text] __ZN14AMDCIPM4EngineC1EPK11OSMetaClass 0000000000078092 g 0f SECT 01 0000 [.text] __ZN14AMDCIPM4EngineC1Ev 0000000000077f9c g 0f SECT 01 0000 [.text] __ZN14AMDCIPM4EngineC2EPK11OSMetaClass 00000000000780c2 g 0f SECT 01 0000 [.text] __ZN14AMDCIPM4EngineC2Ev 0000000000077ff0 g 0f SECT 01 0000 [.text] __ZN14AMDCIPM4EngineD0Ev 0000000000077fe6 g 0f SECT 01 0000 [.text] __ZN14AMDCIPM4EngineD1Ev 0000000000077fdc g 0f SECT 01 0000 [.text] __ZN14AMDCIPM4EngineD2Ev 000000000052d6d0 g 0f SECT 0a 0000 [__DATA.__common] __ZN14AMDSICLContext10gMetaClassE 000000000039a178 g 0f SECT 08 0000 [.const_data] __ZN14AMDSICLContext10superClassE 000000000003a778 g 0f SECT 01 0000 [.text] __ZN14AMDSICLContext11contextStopEv 000000000003befa g 0f SECT 01 0000 [.text] __ZN14AMDSICLContext11setRsrcRegsEP25SI_HwVertexBufRsrcDescRecyjj 000000000003ac96 g 0f SECT 01 0000 [.text] __ZN14AMDSICLContext11splitStreamER24IOAccelCommandStreamInfo 000000000003a54a g 0f SECT 01 0000 [.text] __ZN14AMDSICLContext12contextStartEv 000000000003b35c g 0f SECT 01 0000 [.text] __ZN14AMDSICLContext12remapBuffersEPKjP13_COMPUTE_INFOy 000000000003a918 g 0f SECT 01 0000 [.text] __ZN14AMDSICLContext13enableContextEv 000000000003bede g 0f SECT 01 0000 [.text] __ZN14AMDSICLContext13getPixelBytesEjj 000000000039a0e0 g 0f SECT 08 0000 [.const_data] __ZN14AMDSICLContext13process_tableE 000000000003a9e8 g 0f SECT 01 0000 [.text] __ZN14AMDSICLContext14disableContextEv 000000000003c406 g 0f SECT 01 0000 [.text] __ZN14AMDSICLContext14hasProxyBufferEP16IOAccelResource2 0000000000034efc g 0f SECT 01 0000 [.text] __ZN14AMDSICLContext15process_ComputeER24IOAccelCommandStreamInfo 000000000003bebc g 0f SECT 01 0000 [.text] __ZN14AMDSICLContext15setConstBufRegsEP25SI_HwVertexBufRsrcDescRecyj 0000000000034e80 g 0f SECT 01 0000 [.text] __ZN14AMDSICLContext16process_SetFenceER24IOAccelCommandStreamInfo 000000000003c478 g 0f SECT 01 0000 [.text] __ZN14AMDSICLContext16setupImageRecordEPKjP16IOAccelResource2P18ComputeImageRecordP16WriteImageRecordb 000000000003cb46 g 0f SECT 01 0000 [.text] __ZN14AMDSICLContext17commonLoadBuffersEP16IOAccelResource2S1_RyS2_ 000000000003932c g 0f SECT 01 0000 [.text] __ZN14AMDSICLContext17process_CopyImageER24IOAccelCommandStreamInfo 0000000000036344 g 0f SECT 01 0000 [.text] __ZN14AMDSICLContext17process_RWCBufferER24IOAccelCommandStreamInfo 0000000000036d5e g 0f SECT 01 0000 [.text] __ZN14AMDSICLContext17process_ReadImageER24IOAccelCommandStreamInfo 000000000003bf5a g 0f SECT 01 0000 [.text] __ZN14AMDSICLContext17syncWriteResourceEP16WriteImageRecordh 00000000000380b4 g 0f SECT 01 0000 [.text] __ZN14AMDSICLContext18process_WriteImageER24IOAccelCommandStreamInfo 000000000003bf38 g 0f SECT 01 0000 [.text] __ZN14AMDSICLContext18setScratchRsrcRegsEP25SI_HwVertexBufRsrcDescRecyj 000000000003a812 g 0f SECT 01 0000 [.text] __ZN14AMDSICLContext19getDataBufferLimitsEv 000000000003a870 g 0f SECT 01 0000 [.text] __ZN14AMDSICLContext20processSidebandTokenER24IOAccelCommandStreamInfo 000000000003addc g 0f SECT 01 0000 [.text] __ZN14AMDSICLContext20writeAtomicComputeOpEPjPK13_COMPUTE_INFOPK13_clKernelInfoP21SubmitRingBufferEntry 000000000003a7ee g 0f SECT 01 0000 [.text] __ZN14AMDSICLContext21populateContextConfigEP20IOAccelContextConfig 000000000003a1d2 g 0f SECT 01 0000 [.text] __ZN14AMDSICLContext21process_QueuePriorityER24IOAccelCommandStreamInfo 000000000003b4be g 0f SECT 01 0000 [.text] __ZN14AMDSICLContext22getGlobalBasePatchArgsEPKjP21SubmitRingBufferEntryPK13_clKernelInfoP13_COMPUTE_INFOPyS9_ 000000000003a3b2 g 0f SECT 01 0000 [.text] __ZN14AMDSICLContext22process_UnhandledTokenER24IOAccelCommandStreamInfo 000000000003cb08 g 0f SECT 01 0000 [.text] __ZN14AMDSICLContext23commonProcessBufferInitER24IOAccelCommandStreamInfo 000000000003ad72 g 0f SECT 01 0000 [.text] __ZN14AMDSICLContext24getHardwareConfigurationEPjS0_S0_S0_ 000000000003a04e g 0f SECT 01 0000 [.text] __ZN14AMDSICLContext24process_LinearWriteFlushER24IOAccelCommandStreamInfo 000000000003aaca g 0f SECT 01 0000 [.text] __ZN14AMDSICLContext25freeSubmitRingBufferEntryEP21SubmitRingBufferEntry 000000000003a832 g 0f SECT 01 0000 [.text] __ZN14AMDSICLContext26getTargetAndMethodForIndexEPP9IOServicej 000000000003abb2 g 0f SECT 01 0000 [.text] __ZN14AMDSICLContext29updateSubmitRingBufferEntriesEv 000000000003ab04 g 0f SECT 01 0000 [.text] __ZN14AMDSICLContext37removeConsumedSubmitRingBufferEntriesEv 000000000003a6b0 g 0f SECT 01 0000 [.text] __ZN14AMDSICLContext6finishEv 000000000003a3b8 g 0f SECT 01 0000 [.text] __ZN14AMDSICLContext9MetaClassC1Ev 000000000003a478 g 0f SECT 01 0000 [.text] __ZN14AMDSICLContext9MetaClassC2Ev 000000000039a170 g 0f SECT 08 0000 [.const_data] __ZN14AMDSICLContext9metaClassE 000000000003a414 g 0f SECT 01 0000 [.text] __ZN14AMDSICLContextC1EPK11OSMetaClass 000000000003a4ea g 0f SECT 01 0000 [.text] __ZN14AMDSICLContextC1Ev 000000000003a3f4 g 0f SECT 01 0000 [.text] __ZN14AMDSICLContextC2EPK11OSMetaClass 000000000003a51a g 0f SECT 01 0000 [.text] __ZN14AMDSICLContextC2Ev 000000000003a448 g 0f SECT 01 0000 [.text] __ZN14AMDSICLContextD0Ev 000000000003a43e g 0f SECT 01 0000 [.text] __ZN14AMDSICLContextD1Ev 000000000003a434 g 0f SECT 01 0000 [.text] __ZN14AMDSICLContextD2Ev 000000000052e288 g 0f SECT 0a 0000 [__DATA.__common] __ZN14AMDSIDMAEngine10gMetaClassE 00000000003aeae8 g 0f SECT 08 0000 [.const_data] __ZN14AMDSIDMAEngine10superClassE 000000000006d7fe g 0f SECT 01 0000 [.text] __ZN14AMDSIDMAEngine15allocateHWRingsEv 000000000006d83a g 0f SECT 01 0000 [.text] __ZN14AMDSIDMAEngine18allocateHWChannelsEv 000000000006d964 g 0f SECT 01 0000 [.text] __ZN14AMDSIDMAEngine19dumpEngineHangStateEb 000000000006d782 g 0f SECT 01 0000 [.text] __ZN14AMDSIDMAEngine4freeEv 000000000006d702 g 0f SECT 01 0000 [.text] __ZN14AMDSIDMAEngine4initEP30AMDRadeonX4000_IAMDHWInterface20_eAMD_HW_ENGINE_TYPE 000000000006d8fc g 0f SECT 01 0000 [.text] __ZN14AMDSIDMAEngine4stopEv 000000000006d886 g 0f SECT 01 0000 [.text] __ZN14AMDSIDMAEngine5startEv 000000000006d794 g 0f SECT 01 0000 [.text] __ZN14AMDSIDMAEngine6isIdleEv 000000000006d7c4 g 0f SECT 01 0000 [.text] __ZN14AMDSIDMAEngine7powerUpEv 000000000006d570 g 0f SECT 01 0000 [.text] __ZN14AMDSIDMAEngine9MetaClassC1Ev 000000000006d630 g 0f SECT 01 0000 [.text] __ZN14AMDSIDMAEngine9MetaClassC2Ev 00000000003aeae0 g 0f SECT 08 0000 [.const_data] __ZN14AMDSIDMAEngine9metaClassE 000000000006d5cc g 0f SECT 01 0000 [.text] __ZN14AMDSIDMAEngineC1EPK11OSMetaClass 000000000006d6a2 g 0f SECT 01 0000 [.text] __ZN14AMDSIDMAEngineC1Ev 000000000006d5ac g 0f SECT 01 0000 [.text] __ZN14AMDSIDMAEngineC2EPK11OSMetaClass 000000000006d6d2 g 0f SECT 01 0000 [.text] __ZN14AMDSIDMAEngineC2Ev 000000000006d600 g 0f SECT 01 0000 [.text] __ZN14AMDSIDMAEngineD0Ev 000000000006d5f6 g 0f SECT 01 0000 [.text] __ZN14AMDSIDMAEngineD1Ev 000000000006d5ec g 0f SECT 01 0000 [.text] __ZN14AMDSIDMAEngineD2Ev 000000000052d6a8 g 0f SECT 0a 0000 [__DATA.__common] __ZN14AMDSIGLContext10gMetaClassE 0000000000032444 g 0f SECT 01 0000 [.text] __ZN14AMDSIGLContext10invalidateEv 0000000000399468 g 0f SECT 08 0000 [.const_data] __ZN14AMDSIGLContext10superClassE 00000000000338cc g 0f SECT 01 0000 [.text] __ZN14AMDSIGLContext11SurfaceCopyEPjy 000000000003236c g 0f SECT 01 0000 [.text] __ZN14AMDSIGLContext11contextStopEv 0000000000032d64 g 0f SECT 01 0000 [.text] __ZN14AMDSIGLContext12bindResourceER24IOAccelCommandStreamInfoP16IOAccelResource2bP15IOAccelChannel2j 000000000003210c g 0f SECT 01 0000 [.text] __ZN14AMDSIGLContext12contextStartEv 00000000000339c0 g 0f SECT 01 0000 [.text] __ZN14AMDSIGLContext13build_scissorEv 000000000003327e g 0f SECT 01 0000 [.text] __ZN14AMDSIGLContext13readPixelsFBOEP30sATIGLContextReadPixelsFBODatay 0000000000032814 g 0f SECT 01 0000 [.text] __ZN14AMDSIGLContext13restore_stateER24IOAccelCommandStreamInfo 0000000000399230 g 0f SECT 08 0000 [.const_data] __ZN14AMDSIGLContext14prefetch_tableE 000000000003111a g 0f SECT 01 0000 [.text] __ZN14AMDSIGLContext14process_ExpandER24IOAccelCommandStreamInfo 0000000000033230 g 0f SECT 01 0000 [.text] __ZN14AMDSIGLContext14unbindResourceER24IOAccelCommandStreamInfoP16IOAccelResource2P15IOAccelChannel2 0000000000033b02 g 0f SECT 01 0000 [.text] __ZN14AMDSIGLContext15prefetch_objectER12PrefetchInfoP31AMDRadeonX4000_AMDAccelResource 0000000000031c92 g 0f SECT 01 0000 [.text] __ZN14AMDSIGLContext15process_KprintfER24IOAccelCommandStreamInfo 00000000000328ce g 0f SECT 01 0000 [.text] __ZN14AMDSIGLContext16endCommandStreamER24IOAccelCommandStreamInfo 0000000000033bc0 g 0f SECT 01 0000 [.text] __ZN14AMDSIGLContext16prefetch_BindFBOER24IOAccelCommandStreamInfoPj 0000000000030e04 g 0f SECT 01 0000 [.text] __ZN14AMDSIGLContext16process_CompressER24IOAccelCommandStreamInfo 0000000000031ce2 g 0f SECT 01 0000 [.text] __ZN14AMDSIGLContext16process_EndBlitsER24IOAccelCommandStreamInfo 000000000002f80c g 0f SECT 01 0000 [.text] __ZN14AMDSIGLContext16process_SetFenceER24IOAccelCommandStreamInfo 000000000002ce44 g 0f SECT 01 0000 [.text] __ZN14AMDSIGLContext17process_AAResolveER24IOAccelCommandStreamInfo 00000000000327f8 g 0f SECT 01 0000 [.text] __ZN14AMDSIGLContext18beginCommandStreamER24IOAccelCommandStreamInfo 000000000002b404 g 0f SECT 01 0000 [.text] __ZN14AMDSIGLContext18handle_BindObjectsER24IOAccelCommandStreamInfo 000000000002fa8a g 0f SECT 01 0000 [.text] __ZN14AMDSIGLContext18process_ClearColorER24IOAccelCommandStreamInfo 000000000002bd7c g 0f SECT 01 0000 [.text] __ZN14AMDSIGLContext18process_DrawBufferER24IOAccelCommandStreamInfo 0000000000031cc2 g 0f SECT 01 0000 [.text] __ZN14AMDSIGLContext18process_StartBlitsER24IOAccelCommandStreamInfo 0000000000031cf4 g 0f SECT 01 0000 [.text] __ZN14AMDSIGLContext19discard_SimpleTokenER24IOAccelCommandStreamInfo 0000000000032b92 g 0f SECT 01 0000 [.text] __ZN14AMDSIGLContext19getDataBufferLimitsEv 0000000000032cb2 g 0f SECT 01 0000 [.text] __ZN14AMDSIGLContext20addDrawableToChannelEP16IOAccelDrawable2 00000000000326cc g 0f SECT 01 0000 [.text] __ZN14AMDSIGLContext20discardSidebandTokenER24IOAccelCommandStreamInfo 0000000000031df4 g 0f SECT 01 0000 [.text] __ZN14AMDSIGLContext20discard_IgnoredTokenER24IOAccelCommandStreamInfo 000000000002afa4 g 0f SECT 01 0000 [.text] __ZN14AMDSIGLContext20free_scratch_textureEP31AMDRadeonX4000_AMDAccelResource 000000000002b6ba g 0f SECT 01 0000 [.text] __ZN14AMDSIGLContext20handle_UnbindObjectsER24IOAccelCommandStreamInfo 0000000000031ef2 g 0f SECT 01 0000 [.text] __ZN14AMDSIGLContext20prefetch_BindObjectsER24IOAccelCommandStreamInfoPj 0000000000031ec0 g 0f SECT 01 0000 [.text] __ZN14AMDSIGLContext20prefetch_SimpleTokenER24IOAccelCommandStreamInfoPj 000000000003258a g 0f SECT 01 0000 [.text] __ZN14AMDSIGLContext20processSidebandTokenER24IOAccelCommandStreamInfo 000000000002f8c8 g 0f SECT 01 0000 [.text] __ZN14AMDSIGLContext20process_BufferMemcpyER24IOAccelCommandStreamInfo 000000000002af5c g 0f SECT 01 0000 [.text] __ZN14AMDSIGLContext21alloc_scratch_textureEv 0000000000032566 g 0f SECT 01 0000 [.text] __ZN14AMDSIGLContext21populateContextConfigEP20IOAccelContextConfig 0000000000031eea g 0f SECT 01 0000 [.text] __ZN14AMDSIGLContext21prefetch_IgnoredTokenER24IOAccelCommandStreamInfoPj 0000000000032cee g 0f SECT 01 0000 [.text] __ZN14AMDSIGLContext21processSidebandBufferEP24IOAccelCommandDescriptorb 0000000000032c40 g 0f SECT 01 0000 [.text] __ZN14AMDSIGLContext22addDataBufferToChannelEP16IOAccelResource2j 0000000000031dfa g 0f SECT 01 0000 [.text] __ZN14AMDSIGLContext22discard_StretchTex2TexER24IOAccelCommandStreamInfo 0000000000031de4 g 0f SECT 01 0000 [.text] __ZN14AMDSIGLContext22discard_UnhandledTokenER24IOAccelCommandStreamInfo 000000000002c988 g 0f SECT 01 0000 [.text] __ZN14AMDSIGLContext22process_CopyColorScaleER24IOAccelCommandStreamInfo 000000000002bed4 g 0f SECT 01 0000 [.text] __ZN14AMDSIGLContext22process_StretchTex2TexER24IOAccelCommandStreamInfo 000000000002b7e4 g 0f SECT 01 0000 [.text] __ZN14AMDSIGLContext22process_UnhandledTokenER24IOAccelCommandStreamInfo 000000000002ae80 g 0f SECT 01 0000 [.text] __ZN14AMDSIGLContext23createStateShadowBufferEj 000000000002b7c8 g 0f SECT 01 0000 [.text] __ZN14AMDSIGLContext23handle_UnusedDataBufferER24IOAccelCommandStreamInfo 0000000000031f46 g 0f SECT 01 0000 [.text] __ZN14AMDSIGLContext23prefetch_StretchTex2TexER24IOAccelCommandStreamInfoPj 0000000000031f34 g 0f SECT 01 0000 [.text] __ZN14AMDSIGLContext23prefetch_UnhandledTokenER24IOAccelCommandStreamInfoPj 0000000000032e8a g 0f SECT 01 0000 [.text] __ZN14AMDSIGLContext23prefetch_command_bufferERK24IOAccelCommandStreamInfo 000000000002b1b8 g 0f SECT 01 0000 [.text] __ZN14AMDSIGLContext23process_StateShadowInfoER24IOAccelCommandStreamInfo 000000000002d9ea g 0f SECT 01 0000 [.text] __ZN14AMDSIGLContext23process_StretchSurf2TexER24IOAccelCommandStreamInfo 0000000000031d5c g 0f SECT 01 0000 [.text] __ZN14AMDSIGLContext24discard_InvalidateObjectER24IOAccelCommandStreamInfo 000000000003253a g 0f SECT 01 0000 [.text] __ZN14AMDSIGLContext24get_temp_allocation_infoEP16IOAccelDrawable2PjS2_ 000000000002b37a g 0f SECT 01 0000 [.text] __ZN14AMDSIGLContext24process_InvalidateObjectER24IOAccelCommandStreamInfo 000000000002afba g 0f SECT 01 0000 [.text] __ZN14AMDSIGLContext24reset_scratch_maskmemoryEv 000000000003244a g 0f SECT 01 0000 [.text] __ZN14AMDSIGLContext24setCompatibleSurfaceModeEPyyi 0000000000399010 g 0f SECT 08 0000 [.const_data] __ZN14AMDSIGLContext25ati_token_discard_methodsE 0000000000398df0 g 0f SECT 08 0000 [.const_data] __ZN14AMDSIGLContext25ati_token_process_methodsE 000000000002f080 g 0f SECT 01 0000 [.text] __ZN14AMDSIGLContext25process_ClearDepthStencilER24IOAccelCommandStreamInfo 000000000002b998 g 0f SECT 01 0000 [.text] __ZN14AMDSIGLContext25process_PatchStreamTexBufER24IOAccelCommandStreamInfo 0000000000032cd0 g 0f SECT 01 0000 [.text] __ZN14AMDSIGLContext25removeDrawableFromChannelEP16IOAccelDrawable2 0000000000033242 g 0f SECT 01 0000 [.text] __ZN14AMDSIGLContext26getTargetAndMethodForIndexEPP9IOServicej 000000000002b7f4 g 0f SECT 01 0000 [.text] __ZN14AMDSIGLContext26process_PatchStreamDataBufER24IOAccelCommandStreamInfo 000000000002b1b0 g 0f SECT 01 0000 [.text] __ZN14AMDSIGLContext26setup_temp_resolve_surfaceEP31AMDRadeonX4000_AMDAccelResource 0000000000032c60 g 0f SECT 01 0000 [.text] __ZN14AMDSIGLContext27removeDataBufferFromChannelEP16IOAccelResource2j 00000000000338e8 g 0f SECT 01 0000 [.text] __ZN14AMDSIGLContext29setup_scratch_maskmemory_infoEP31AMDRadeonX4000_AMDAccelResource 000000000002b01a g 0f SECT 01 0000 [.text] __ZN14AMDSIGLContext30update_scratch_maskmemory_infoEP31AMDRadeonX4000_AMDAccelResource 000000000003455e g 0f SECT 01 0000 [.text] __ZN14AMDSIGLContext31write_kernel_render_target_regsEPj 0000000000032c7e g 0f SECT 01 0000 [.text] __ZN14AMDSIGLContext32removeCurrentResourceFromChannelEP16IOAccelResource2j 000000000002fe82 g 0f SECT 01 0000 [.text] __ZN14AMDSIGLContext35process_FramebufferBlitDepthStencilER24IOAccelCommandStreamInfo 0000000000033c50 g 0f SECT 01 0000 [.text] __ZN14AMDSIGLContext37write_kernel_depth_render_target_regsEPj 0000000000031f7a g 0f SECT 01 0000 [.text] __ZN14AMDSIGLContext9MetaClassC1Ev 000000000003203a g 0f SECT 01 0000 [.text] __ZN14AMDSIGLContext9MetaClassC2Ev 0000000000399460 g 0f SECT 08 0000 [.const_data] __ZN14AMDSIGLContext9metaClassE 0000000000031fd6 g 0f SECT 01 0000 [.text] __ZN14AMDSIGLContextC1EPK11OSMetaClass 00000000000320ac g 0f SECT 01 0000 [.text] __ZN14AMDSIGLContextC1Ev 0000000000031fb6 g 0f SECT 01 0000 [.text] __ZN14AMDSIGLContextC2EPK11OSMetaClass 00000000000320dc g 0f SECT 01 0000 [.text] __ZN14AMDSIGLContextC2Ev 000000000003200a g 0f SECT 01 0000 [.text] __ZN14AMDSIGLContextD0Ev 0000000000032000 g 0f SECT 01 0000 [.text] __ZN14AMDSIGLContextD1Ev 0000000000031ff6 g 0f SECT 01 0000 [.text] __ZN14AMDSIGLContextD2Ev 000000000052e198 g 0f SECT 0a 0000 [__DATA.__common] __ZN14AMDSIPM4Engine10gMetaClassE 00000000003ad658 g 0f SECT 08 0000 [.const_data] __ZN14AMDSIPM4Engine10superClassE 000000000006b568 g 0f SECT 01 0000 [.text] __ZN14AMDSIPM4Engine15allocateHWRingsEv 000000000006b28a g 0f SECT 01 0000 [.text] __ZN14AMDSIPM4Engine16loadPM4MicrocodeEv 000000000006b5f4 g 0f SECT 01 0000 [.text] __ZN14AMDSIPM4Engine18allocateHWChannelsEv 000000000006b518 g 0f SECT 01 0000 [.text] __ZN14AMDSIPM4Engine19getRevVersionNumberEPKc 000000000006b4a0 g 0f SECT 01 0000 [.text] __ZN14AMDSIPM4Engine21initializeMicroEngineEv 000000000006b54c g 0f SECT 01 0000 [.text] __ZN14AMDSIPM4Engine23resetGRBMOnCommandStartEv 000000000006b91e g 0f SECT 01 0000 [.text] __ZN14AMDSIPM4Engine26systemWillChangeSpeedEventEv 000000000006b26c g 0f SECT 01 0000 [.text] __ZN14AMDSIPM4Engine28initializeTimestampRegistersEj 000000000006b816 g 0f SECT 01 0000 [.text] __ZN14AMDSIPM4Engine4stopEv 000000000006b782 g 0f SECT 01 0000 [.text] __ZN14AMDSIPM4Engine5startEv 000000000006b404 g 0f SECT 01 0000 [.text] __ZN14AMDSIPM4Engine6haltMEEv 000000000006b1ca g 0f SECT 01 0000 [.text] __ZN14AMDSIPM4Engine6isIdleEv 000000000006b698 g 0f SECT 01 0000 [.text] __ZN14AMDSIPM4Engine7powerUpEv 000000000006b464 g 0f SECT 01 0000 [.text] __ZN14AMDSIPM4Engine7startMEEv 000000000006b0d0 g 0f SECT 01 0000 [.text] __ZN14AMDSIPM4Engine9MetaClassC1Ev 000000000006b190 g 0f SECT 01 0000 [.text] __ZN14AMDSIPM4Engine9MetaClassC2Ev 00000000003ad650 g 0f SECT 08 0000 [.const_data] __ZN14AMDSIPM4Engine9metaClassE 000000000006b1e8 g 0f SECT 01 0000 [.text] __ZN14AMDSIPM4Engine9softResetEjj 000000000006b12c g 0f SECT 01 0000 [.text] __ZN14AMDSIPM4EngineC1EPK11OSMetaClass 000000000006b10c g 0f SECT 01 0000 [.text] __ZN14AMDSIPM4EngineC2EPK11OSMetaClass 000000000006b160 g 0f SECT 01 0000 [.text] __ZN14AMDSIPM4EngineD0Ev 000000000006b156 g 0f SECT 01 0000 [.text] __ZN14AMDSIPM4EngineD1Ev 000000000006b14c g 0f SECT 01 0000 [.text] __ZN14AMDSIPM4EngineD2Ev 000000000052e440 g 0f SECT 0a 0000 [__DATA.__common] __ZN14AMDSISPUEngine10gMetaClassE 00000000003b1258 g 0f SECT 08 0000 [.const_data] __ZN14AMDSISPUEngine10superClassE 0000000000072aa6 g 0f SECT 01 0000 [.text] __ZN14AMDSISPUEngine10suspendSPUEv 00000000000724ba g 0f SECT 01 0000 [.text] __ZN14AMDSISPUEngine11setUVDStateEb 00000000000725e4 g 0f SECT 01 0000 [.text] __ZN14AMDSISPUEngine12initHardwareEv 00000000000726de g 0f SECT 01 0000 [.text] __ZN14AMDSISPUEngine13initializeSPUEv 0000000000072b8c g 0f SECT 01 0000 [.text] __ZN14AMDSISPUEngine14prepareSuspendEv 0000000000072ca2 g 0f SECT 01 0000 [.text] __ZN14AMDSISPUEngine15allocateHWRingsEv 0000000000072bbc g 0f SECT 01 0000 [.text] __ZN14AMDSISPUEngine15enableSPUClocksEv 0000000000072668 g 0f SECT 01 0000 [.text] __ZN14AMDSISPUEngine15releaseHardwareEv 0000000000072c0e g 0f SECT 01 0000 [.text] __ZN14AMDSISPUEngine16disableSPUClocksEv 0000000000072594 g 0f SECT 01 0000 [.text] __ZN14AMDSISPUEngine17waitForKernelIdleEv 0000000000072cde g 0f SECT 01 0000 [.text] __ZN14AMDSISPUEngine18allocateHWChannelsEv 0000000000072d1a g 0f SECT 01 0000 [.text] __ZN14AMDSISPUEngine18readIndirectSPURegEj 0000000000072d9e g 0f SECT 01 0000 [.text] __ZN14AMDSISPUEngine19dumpEngineHangStateEb 0000000000072d5a g 0f SECT 01 0000 [.text] __ZN14AMDSISPUEngine19writeIndirectSPURegEjj 00000000000724a4 g 0f SECT 01 0000 [.text] __ZN14AMDSISPUEngine25setPowerRegistrationStateEb 0000000000072390 g 0f SECT 01 0000 [.text] __ZN14AMDSISPUEngine4freeEv 0000000000072312 g 0f SECT 01 0000 [.text] __ZN14AMDSISPUEngine4initEP30AMDRadeonX4000_IAMDHWInterface20_eAMD_HW_ENGINE_TYPE 000000000007246e g 0f SECT 01 0000 [.text] __ZN14AMDSISPUEngine4stopEv 0000000000072416 g 0f SECT 01 0000 [.text] __ZN14AMDSISPUEngine5startEv 00000000000723cc g 0f SECT 01 0000 [.text] __ZN14AMDSISPUEngine6isIdleEv 0000000000072180 g 0f SECT 01 0000 [.text] __ZN14AMDSISPUEngine9MetaClassC1Ev 0000000000072240 g 0f SECT 01 0000 [.text] __ZN14AMDSISPUEngine9MetaClassC2Ev 00000000003b1250 g 0f SECT 08 0000 [.const_data] __ZN14AMDSISPUEngine9metaClassE 00000000000721dc g 0f SECT 01 0000 [.text] __ZN14AMDSISPUEngineC1EPK11OSMetaClass 00000000000722b2 g 0f SECT 01 0000 [.text] __ZN14AMDSISPUEngineC1Ev 00000000000721bc g 0f SECT 01 0000 [.text] __ZN14AMDSISPUEngineC2EPK11OSMetaClass 00000000000722e2 g 0f SECT 01 0000 [.text] __ZN14AMDSISPUEngineC2Ev 0000000000072210 g 0f SECT 01 0000 [.text] __ZN14AMDSISPUEngineD0Ev 0000000000072206 g 0f SECT 01 0000 [.text] __ZN14AMDSISPUEngineD1Ev 00000000000721fc g 0f SECT 01 0000 [.text] __ZN14AMDSISPUEngineD2Ev 000000000052e080 g 0f SECT 0a 0000 [__DATA.__common] __ZN14AMDSIVMContext10gMetaClassE 00000000003ab0d8 g 0f SECT 08 0000 [.const_data] __ZN14AMDSIVMContext10superClassE 0000000000065292 g 0f SECT 01 0000 [.text] __ZN14AMDSIVMContext5mapVAEyyP18IOMemoryDescriptoryyb 0000000000066156 g 0f SECT 01 0000 [.text] __ZN14AMDSIVMContext7unmapVAEyy 0000000000065100 g 0f SECT 01 0000 [.text] __ZN14AMDSIVMContext9MetaClassC1Ev 00000000000651c0 g 0f SECT 01 0000 [.text] __ZN14AMDSIVMContext9MetaClassC2Ev 00000000003ab0d0 g 0f SECT 08 0000 [.const_data] __ZN14AMDSIVMContext9metaClassE 000000000006515c g 0f SECT 01 0000 [.text] __ZN14AMDSIVMContextC1EPK11OSMetaClass 0000000000065232 g 0f SECT 01 0000 [.text] __ZN14AMDSIVMContextC1Ev 000000000006513c g 0f SECT 01 0000 [.text] __ZN14AMDSIVMContextC2EPK11OSMetaClass 0000000000065262 g 0f SECT 01 0000 [.text] __ZN14AMDSIVMContextC2Ev 0000000000065190 g 0f SECT 01 0000 [.text] __ZN14AMDSIVMContextD0Ev 0000000000065186 g 0f SECT 01 0000 [.text] __ZN14AMDSIVMContextD1Ev 000000000006517c g 0f SECT 01 0000 [.text] __ZN14AMDSIVMContextD2Ev 000000000052eb70 g 0f SECT 0a 0000 [__DATA.__common] __ZN14AMDVIPM4Engine10gMetaClassE 00000000003bc398 g 0f SECT 08 0000 [.const_data] __ZN14AMDVIPM4Engine10superClassE 000000000009140c g 0f SECT 01 0000 [.text] __ZN14AMDVIPM4Engine11cpSoftResetEv 0000000000091138 g 0f SECT 01 0000 [.text] __ZN14AMDVIPM4Engine14gfxEngineResetEv 000000000008f650 g 0f SECT 01 0000 [.text] __ZN14AMDVIPM4Engine15InitMapQueueMQDE18_eAMD_HW_RING_TYPE 000000000008fdea g 0f SECT 01 0000 [.text] __ZN14AMDVIPM4Engine15MicroEngineStopE18_eAMD_HW_RING_TYPE 0000000000090d1a g 0f SECT 01 0000 [.text] __ZN14AMDVIPM4Engine15allocateHWRingsEv 000000000009103a g 0f SECT 01 0000 [.text] __ZN14AMDVIPM4Engine15stopBeforeResetEv 0000000000090494 g 0f SECT 01 0000 [.text] __ZN14AMDVIPM4Engine16MicroEngineStartE18_eAMD_HW_RING_TYPE 0000000000090dcc g 0f SECT 01 0000 [.text] __ZN14AMDVIPM4Engine18allocateHWChannelsEv 0000000000091392 g 0f SECT 01 0000 [.text] __ZN14AMDVIPM4Engine18computeEngineResetE18_eAMD_HW_RING_TYPE 000000000008f582 g 0f SECT 01 0000 [.text] __ZN14AMDVIPM4Engine20setVirtualSpaceReadyEb 0000000000090268 g 0f SECT 01 0000 [.text] __ZN14AMDVIPM4Engine21MicroEngineInitializeE18_eAMD_HW_RING_TYPE 0000000000090762 g 0f SECT 01 0000 [.text] __ZN14AMDVIPM4Engine21SubmitMapQueuesPacketE18_eAMD_HW_RING_TYPE 0000000000090878 g 0f SECT 01 0000 [.text] __ZN14AMDVIPM4Engine21initializeMicroEngineEv 0000000000090c02 g 0f SECT 01 0000 [.text] __ZN14AMDVIPM4Engine22allocateAndInitHWRingsEv 0000000000090f2c g 0f SECT 01 0000 [.text] __ZN14AMDVIPM4Engine22getTimestampIRQSourcexE18_eAMD_HW_RING_TYPE 00000000000914bc g 0f SECT 01 0000 [.text] __ZN14AMDVIPM4Engine22toCailDetectHungBlocksEv 0000000000090a1a g 0f SECT 01 0000 [.text] __ZN14AMDVIPM4Engine23QueryComputeQueueStatusE18_eAMD_HW_RING_TYPE 0000000000090f44 g 0f SECT 01 0000 [.text] __ZN14AMDVIPM4Engine23SubmitQueryStatusPacketE18_eAMD_HW_RING_TYPEy 000000000008fd2a g 0f SECT 01 0000 [.text] __ZN14AMDVIPM4Engine23SubmitUnmapQueuesPacketE18_eAMD_HW_RING_TYPE 0000000000090be6 g 0f SECT 01 0000 [.text] __ZN14AMDVIPM4Engine23resetGRBMOnCommandStartEv 0000000000090178 g 0f SECT 01 0000 [.text] __ZN14AMDVIPM4Engine24MicroEngineLoadMicrocodeE18_eAMD_HW_RING_TYPE 00000000000906ea g 0f SECT 01 0000 [.text] __ZN14AMDVIPM4Engine24SubmitSetResourcesPacketEv 000000000008f870 g 0f SECT 01 0000 [.text] __ZN14AMDVIPM4Engine27setMemoryAllocationsEnabledEb 0000000000090f26 g 0f SECT 01 0000 [.text] __ZN14AMDVIPM4Engine28initializeTimestampRegistersEj 00000000000912e0 g 0f SECT 01 0000 [.text] __ZN14AMDVIPM4Engine28isComputeQueueUnmapCompletedE18_eAMD_HW_RING_TYPE 0000000000090584 g 0f SECT 01 0000 [.text] __ZN14AMDVIPM4Engine32MicroEngineQueryMicrocodeVersionE18_eAMD_HW_RING_TYPE 000000000008f570 g 0f SECT 01 0000 [.text] __ZN14AMDVIPM4Engine4freeEv 000000000008f4d2 g 0f SECT 01 0000 [.text] __ZN14AMDVIPM4Engine4initEP30AMDRadeonX4000_IAMDHWInterface20_eAMD_HW_ENGINE_TYPE 000000000008faa2 g 0f SECT 01 0000 [.text] __ZN14AMDVIPM4Engine4stopEv 000000000009106c g 0f SECT 01 0000 [.text] __ZN14AMDVIPM4Engine5resetE18_eAMD_HW_RING_TYPE 000000000008fa30 g 0f SECT 01 0000 [.text] __ZN14AMDVIPM4Engine5startEv 000000000008fb44 g 0f SECT 01 0000 [.text] __ZN14AMDVIPM4Engine6haltMEEv 0000000000090998 g 0f SECT 01 0000 [.text] __ZN14AMDVIPM4Engine6isIdleEv 000000000008f9c0 g 0f SECT 01 0000 [.text] __ZN14AMDVIPM4Engine7powerUpEv 000000000008feda g 0f SECT 01 0000 [.text] __ZN14AMDVIPM4Engine7startMEEv 000000000008f340 g 0f SECT 01 0000 [.text] __ZN14AMDVIPM4Engine9MetaClassC1Ev 000000000008f400 g 0f SECT 01 0000 [.text] __ZN14AMDVIPM4Engine9MetaClassC2Ev 00000000003bc390 g 0f SECT 08 0000 [.const_data] __ZN14AMDVIPM4Engine9metaClassE 0000000000090ea2 g 0f SECT 01 0000 [.text] __ZN14AMDVIPM4Engine9softResetEjj 000000000008f39c g 0f SECT 01 0000 [.text] __ZN14AMDVIPM4EngineC1EPK11OSMetaClass 000000000008f472 g 0f SECT 01 0000 [.text] __ZN14AMDVIPM4EngineC1Ev 000000000008f37c g 0f SECT 01 0000 [.text] __ZN14AMDVIPM4EngineC2EPK11OSMetaClass 000000000008f4a2 g 0f SECT 01 0000 [.text] __ZN14AMDVIPM4EngineC2Ev 000000000008f3d0 g 0f SECT 01 0000 [.text] __ZN14AMDVIPM4EngineD0Ev 000000000008f3c6 g 0f SECT 01 0000 [.text] __ZN14AMDVIPM4EngineD1Ev 000000000008f3bc g 0f SECT 01 0000 [.text] __ZN14AMDVIPM4EngineD2Ev 000000000052e9b8 g 0f SECT 0a 0000 [__DATA.__common] __ZN14AMDVIVMContext10gMetaClassE 00000000003b9f68 g 0f SECT 08 0000 [.const_data] __ZN14AMDVIVMContext10superClassE 0000000000087ed2 g 0f SECT 01 0000 [.text] __ZN14AMDVIVMContext5mapVAEyyP18IOMemoryDescriptoryyb 0000000000088d90 g 0f SECT 01 0000 [.text] __ZN14AMDVIVMContext7unmapVAEyy 0000000000087d40 g 0f SECT 01 0000 [.text] __ZN14AMDVIVMContext9MetaClassC1Ev 0000000000087e00 g 0f SECT 01 0000 [.text] __ZN14AMDVIVMContext9MetaClassC2Ev 00000000003b9f60 g 0f SECT 08 0000 [.const_data] __ZN14AMDVIVMContext9metaClassE 0000000000087d9c g 0f SECT 01 0000 [.text] __ZN14AMDVIVMContextC1EPK11OSMetaClass 0000000000087e72 g 0f SECT 01 0000 [.text] __ZN14AMDVIVMContextC1Ev 0000000000087d7c g 0f SECT 01 0000 [.text] __ZN14AMDVIVMContextC2EPK11OSMetaClass 0000000000087ea2 g 0f SECT 01 0000 [.text] __ZN14AMDVIVMContextC2Ev 0000000000087dd0 g 0f SECT 01 0000 [.text] __ZN14AMDVIVMContextD0Ev 0000000000087dc6 g 0f SECT 01 0000 [.text] __ZN14AMDVIVMContextD1Ev 0000000000087dbc g 0f SECT 01 0000 [.text] __ZN14AMDVIVMContextD2Ev 00000000000da226 g 0f SECT 01 0000 [.text] __ZN14EgBasedAddrLib17IsTileInfoAllZeroEP14_ADDR_TILEINFO 00000000000da130 g 0f SECT 01 0000 [.text] __ZN14EgBasedAddrLib19HwlComputeFmaskInfoEPK30_ADDR_COMPUTE_FMASK_INFO_INPUTP31_ADDR_COMPUTE_FMASK_INFO_OUTPUT 00000000000d9f08 g 0f SECT 01 0000 [.text] __ZN14EgBasedAddrLib24DispatchComputeFmaskInfoEPK30_ADDR_COMPUTE_FMASK_INFO_INPUTP31_ADDR_COMPUTE_FMASK_INFO_OUTPUT 00000000000da1d8 g 0f SECT 01 0000 [.text] __ZN14EgBasedAddrLib35ComputeFmaskNumPlanesFromNumSamplesEj 00000000000da202 g 0f SECT 01 0000 [.text] __ZN14EgBasedAddrLib37ComputeFmaskResolvedBppFromNumSamplesEj 00000000000d7070 g 0f SECT 01 0000 [.text] __ZN14EgBasedAddrLibC2EPK10AddrClient 00000000000d709e g 0f SECT 01 0000 [.text] __ZN14EgBasedAddrLibD0Ev 00000000000d70ba g 0f SECT 01 0000 [.text] __ZN14EgBasedAddrLibD1Ev 00000000000d70c4 g 0f SECT 01 0000 [.text] __ZN14EgBasedAddrLibD2Ev 000000000052e6e8 g 0f SECT 0a 0000 [__DATA.__common] __ZN15AMDCIDMAChannel10gMetaClassE 00000000003b57e8 g 0f SECT 08 0000 [.const_data] __ZN15AMDCIDMAChannel10superClassE 000000000007ec8e g 0f SECT 01 0000 [.text] __ZN15AMDCIDMAChannel18submitVMInvalidateEjyj 000000000007eebe g 0f SECT 01 0000 [.text] __ZN15AMDCIDMAChannel20initializeDmaPktInfoEv 000000000007e7b2 g 0f SECT 01 0000 [.text] __ZN15AMDCIDMAChannel21writeProfilingCommandEPjyjb 000000000007eb2e g 0f SECT 01 0000 [.text] __ZN15AMDCIDMAChannel21writeSRBMWriteCommandEPjjjj 000000000007ee9a g 0f SECT 01 0000 [.text] __ZN15AMDCIDMAChannel22timeStampInterruptTypeEv 000000000007ea76 g 0f SECT 01 0000 [.text] __ZN15AMDCIDMAChannel22writeCopyLinearCommandEPjyyj 000000000007ebbe g 0f SECT 01 0000 [.text] __ZN15AMDCIDMAChannel22writePollRegMemCommandEPjbyjjjjj 000000000007e8ae g 0f SECT 01 0000 [.text] __ZN15AMDCIDMAChannel23writeWriteLinearCommandEPjyjS0_ 000000000007e99a g 0f SECT 01 0000 [.text] __ZN15AMDCIDMAChannel23writeWritePTEPDECommandEPjyjyyy 000000000007e808 g 0f SECT 01 0000 [.text] __ZN15AMDCIDMAChannel24writeConstantFillCommandEPjyjj 000000000007e436 g 0f SECT 01 0000 [.text] __ZN15AMDCIDMAChannel27commitIndirectCommandBufferEP30AMD_SUBMIT_COMMAND_BUFFER_INFO 000000000007e622 g 0f SECT 01 0000 [.text] __ZN15AMDCIDMAChannel27initializeVMInvalidateFrameEv 000000000007ee5e g 0f SECT 01 0000 [.text] __ZN15AMDCIDMAChannel33releaseIndirectCommandBufferFrameEv 000000000007edd6 g 0f SECT 01 0000 [.text] __ZN15AMDCIDMAChannel36initializeIndirectCommandBufferFrameEv 000000000007e3ea g 0f SECT 01 0000 [.text] __ZN15AMDCIDMAChannel4freeEv 000000000007e392 g 0f SECT 01 0000 [.text] __ZN15AMDCIDMAChannel4initEiP30AMDRadeonX4000_IAMDHWInterfaceP27AMDRadeonX4000_IAMDHWEngineP25AMDRadeonX4000_IAMDHWRingPKc 000000000007e200 g 0f SECT 01 0000 [.text] __ZN15AMDCIDMAChannel9MetaClassC1Ev 000000000007e2c0 g 0f SECT 01 0000 [.text] __ZN15AMDCIDMAChannel9MetaClassC2Ev 00000000003b57e0 g 0f SECT 08 0000 [.const_data] __ZN15AMDCIDMAChannel9metaClassE 000000000007e25c g 0f SECT 01 0000 [.text] __ZN15AMDCIDMAChannelC1EPK11OSMetaClass 000000000007e332 g 0f SECT 01 0000 [.text] __ZN15AMDCIDMAChannelC1Ev 000000000007e23c g 0f SECT 01 0000 [.text] __ZN15AMDCIDMAChannelC2EPK11OSMetaClass 000000000007e362 g 0f SECT 01 0000 [.text] __ZN15AMDCIDMAChannelC2Ev 000000000007e290 g 0f SECT 01 0000 [.text] __ZN15AMDCIDMAChannelD0Ev 000000000007e286 g 0f SECT 01 0000 [.text] __ZN15AMDCIDMAChannelD1Ev 000000000007e27c g 0f SECT 01 0000 [.text] __ZN15AMDCIDMAChannelD2Ev 000000000052e6c0 g 0f SECT 0a 0000 [__DATA.__common] __ZN15AMDCIPM4Channel10gMetaClassE 00000000003b53d8 g 0f SECT 08 0000 [.const_data] __ZN15AMDCIPM4Channel10superClassE 000000000007e068 g 0f SECT 01 0000 [.text] __ZN15AMDCIPM4Channel18clearResetEOPFenceEv 000000000007dbf4 g 0f SECT 01 0000 [.text] __ZN15AMDCIPM4Channel18initializeCSBFrameEv 000000000007d528 g 0f SECT 01 0000 [.text] __ZN15AMDCIPM4Channel18writeDataCmdPacketEP15_PM4_WRITE_DATA23WRITE_DATA_dst_sel_enum25WRITE_DATA_addr_incr_enum26WRITE_DATA_wr_confirm_enum28WRITE_DATA_cache_policy_enum26WRITE_DATA_engine_sel_enumyPKjj 000000000007debe g 0f SECT 01 0000 [.text] __ZN15AMDCIPM4Channel19eventWriteCmdPacketEP16_PM4_EVENT_WRITE28EVENT_WRITE_event_index_enumj 000000000007d880 g 0f SECT 01 0000 [.text] __ZN15AMDCIPM4Channel19releaseSubmitFramesEv 000000000007dede g 0f SECT 01 0000 [.text] __ZN15AMDCIPM4Channel20getIBAlignmentFactorEv 000000000007d5e0 g 0f SECT 01 0000 [.text] __ZN15AMDCIPM4Channel20surfaceSyncCmdPacketEP17_PM4_SURFACE_SYNCjyyj 000000000007dd42 g 0f SECT 01 0000 [.text] __ZN15AMDCIPM4Channel21writeProfilingCommandEPjyjb 000000000007d97e g 0f SECT 01 0000 [.text] __ZN15AMDCIPM4Channel22eventWriteEOPCmdPacketEP20_PM4_EVENT_WRITE_EOPj32EVENT_WRITE_EOP_event_index_enum33EVENT_WRITE_EOP_cache_policy_enum28EVENT_WRITE_EOP_dst_sel_enum28EVENT_WRITE_EOP_int_sel_enum29EVENT_WRITE_EOP_data_sel_enumyy 000000000007d832 g 0f SECT 01 0000 [.text] __ZN15AMDCIPM4Channel22initializeSubmitFramesEv 000000000007df4c g 0f SECT 01 0000 [.text] __ZN15AMDCIPM4Channel22writeEventWriteCommandEPjjj 000000000007e084 g 0f SECT 01 0000 [.text] __ZN15AMDCIPM4Channel23isResetEOPFenceFinishedEv 000000000007deea g 0f SECT 01 0000 [.text] __ZN15AMDCIPM4Channel23writeSurfaceSyncCommandEPjjyyj 000000000007d8bc g 0f SECT 01 0000 [.text] __ZN15AMDCIPM4Channel24initializeTimestampFrameEv 000000000007df6a g 0f SECT 01 0000 [.text] __ZN15AMDCIPM4Channel25writeEventWriteEOPCommandEPjjjyjjy 000000000007d642 g 0f SECT 01 0000 [.text] __ZN15AMDCIPM4Channel27commitIndirectCommandBufferEP30AMD_SUBMIT_COMMAND_BUFFER_INFO 000000000007dfa2 g 0f SECT 01 0000 [.text] __ZN15AMDCIPM4Channel28prepareAndFlushResetEOPFenceEv 000000000007da32 g 0f SECT 01 0000 [.text] __ZN15AMDCIPM4Channel36initializeIndirectCommandBufferFrameEv 000000000007d3e4 g 0f SECT 01 0000 [.text] __ZN15AMDCIPM4Channel48writeFlushAndInvalidateDestinationCachesCommandsEv 000000000007d3d2 g 0f SECT 01 0000 [.text] __ZN15AMDCIPM4Channel4freeEv 000000000007d362 g 0f SECT 01 0000 [.text] __ZN15AMDCIPM4Channel4initEiP30AMDRadeonX4000_IAMDHWInterfaceP27AMDRadeonX4000_IAMDHWEngineP25AMDRadeonX4000_IAMDHWRingPKc 000000000007d1d0 g 0f SECT 01 0000 [.text] __ZN15AMDCIPM4Channel9MetaClassC1Ev 000000000007d290 g 0f SECT 01 0000 [.text] __ZN15AMDCIPM4Channel9MetaClassC2Ev 00000000003b53d0 g 0f SECT 08 0000 [.const_data] __ZN15AMDCIPM4Channel9metaClassE 000000000007d22c g 0f SECT 01 0000 [.text] __ZN15AMDCIPM4ChannelC1EPK11OSMetaClass 000000000007d302 g 0f SECT 01 0000 [.text] __ZN15AMDCIPM4ChannelC1Ev 000000000007d20c g 0f SECT 01 0000 [.text] __ZN15AMDCIPM4ChannelC2EPK11OSMetaClass 000000000007d332 g 0f SECT 01 0000 [.text] __ZN15AMDCIPM4ChannelC2Ev 000000000007d260 g 0f SECT 01 0000 [.text] __ZN15AMDCIPM4ChannelD0Ev 000000000007d256 g 0f SECT 01 0000 [.text] __ZN15AMDCIPM4ChannelD1Ev 000000000007d24c g 0f SECT 01 0000 [.text] __ZN15AMDCIPM4ChannelD2Ev 000000000052e710 g 0f SECT 0a 0000 [__DATA.__common] __ZN15AMDCISAMUEngine10gMetaClassE 00000000003b5be8 g 0f SECT 08 0000 [.const_data] __ZN15AMDCISAMUEngine10superClassE 000000000007f630 g 0f SECT 01 0000 [.text] __ZN15AMDCISAMUEngine10suspendSPUEv 000000000007f36c g 0f SECT 01 0000 [.text] __ZN15AMDCISAMUEngine12initHardwareEv 000000000007f526 g 0f SECT 01 0000 [.text] __ZN15AMDCISAMUEngine13initializeSPUEv 000000000007f674 g 0f SECT 01 0000 [.text] __ZN15AMDCISAMUEngine15allocateHWRingsEv 000000000007f778 g 0f SECT 01 0000 [.text] __ZN15AMDCISAMUEngine15enableSPUClocksEv 000000000007f448 g 0f SECT 01 0000 [.text] __ZN15AMDCISAMUEngine15releaseHardwareEv 000000000007f77e g 0f SECT 01 0000 [.text] __ZN15AMDCISAMUEngine16disableSPUClocksEv 000000000007f6fa g 0f SECT 01 0000 [.text] __ZN15AMDCISAMUEngine18allocateHWChannelsEv 000000000007f784 g 0f SECT 01 0000 [.text] __ZN15AMDCISAMUEngine18readIndirectSPURegEj 000000000007f88c g 0f SECT 01 0000 [.text] __ZN15AMDCISAMUEngine19dumpEngineHangStateEb 000000000007f7c4 g 0f SECT 01 0000 [.text] __ZN15AMDCISAMUEngine19writeIndirectSPURegEjj 000000000007f2fa g 0f SECT 01 0000 [.text] __ZN15AMDCISAMUEngine20setMemoryAllocationsEb 000000000007f27a g 0f SECT 01 0000 [.text] __ZN15AMDCISAMUEngine21setSuspendResumeStateEb 000000000007f808 g 0f SECT 01 0000 [.text] __ZN15AMDCISAMUEngine22readIndirectSAMUSABRegEj 000000000007f848 g 0f SECT 01 0000 [.text] __ZN15AMDCISAMUEngine23writeIndirectSAMUSABRegEjj 000000000007f242 g 0f SECT 01 0000 [.text] __ZN15AMDCISAMUEngine4initEP30AMDRadeonX4000_IAMDHWInterface20_eAMD_HW_ENGINE_TYPE 000000000007f770 g 0f SECT 01 0000 [.text] __ZN15AMDCISAMUEngine6isIdleEv 000000000007f0b0 g 0f SECT 01 0000 [.text] __ZN15AMDCISAMUEngine9MetaClassC1Ev 000000000007f170 g 0f SECT 01 0000 [.text] __ZN15AMDCISAMUEngine9MetaClassC2Ev 00000000003b5be0 g 0f SECT 08 0000 [.const_data] __ZN15AMDCISAMUEngine9metaClassE 000000000007f10c g 0f SECT 01 0000 [.text] __ZN15AMDCISAMUEngineC1EPK11OSMetaClass 000000000007f1e2 g 0f SECT 01 0000 [.text] __ZN15AMDCISAMUEngineC1Ev 000000000007f0ec g 0f SECT 01 0000 [.text] __ZN15AMDCISAMUEngineC2EPK11OSMetaClass 000000000007f212 g 0f SECT 01 0000 [.text] __ZN15AMDCISAMUEngineC2Ev 000000000007f140 g 0f SECT 01 0000 [.text] __ZN15AMDCISAMUEngineD0Ev 000000000007f136 g 0f SECT 01 0000 [.text] __ZN15AMDCISAMUEngineD1Ev 000000000007f12c g 0f SECT 01 0000 [.text] __ZN15AMDCISAMUEngineD2Ev 000000000052e828 g 0f SECT 0a 0000 [__DATA.__common] __ZN15AMDCIVCEChannel10gMetaClassE 00000000003b75f8 g 0f SECT 08 0000 [.const_data] __ZN15AMDCIVCEChannel10superClassE 0000000000081d60 g 0f SECT 01 0000 [.text] __ZN15AMDCIVCEChannel22getIndirectCommandSizeEv 0000000000081e1c g 0f SECT 01 0000 [.text] __ZN15AMDCIVCEChannel27commitIndirectCommandBufferEP30AMD_SUBMIT_COMMAND_BUFFER_INFO 0000000000081db2 g 0f SECT 01 0000 [.text] __ZN15AMDCIVCEChannel36initializeIndirectCommandBufferFrameEv 0000000000081d4e g 0f SECT 01 0000 [.text] __ZN15AMDCIVCEChannel4freeEv 0000000000081d32 g 0f SECT 01 0000 [.text] __ZN15AMDCIVCEChannel4initEiP30AMDRadeonX4000_IAMDHWInterfaceP27AMDRadeonX4000_IAMDHWEngineP25AMDRadeonX4000_IAMDHWRingPKc 0000000000081ba0 g 0f SECT 01 0000 [.text] __ZN15AMDCIVCEChannel9MetaClassC1Ev 0000000000081c60 g 0f SECT 01 0000 [.text] __ZN15AMDCIVCEChannel9MetaClassC2Ev 00000000003b75f0 g 0f SECT 08 0000 [.const_data] __ZN15AMDCIVCEChannel9metaClassE 0000000000081bfc g 0f SECT 01 0000 [.text] __ZN15AMDCIVCEChannelC1EPK11OSMetaClass 0000000000081cd2 g 0f SECT 01 0000 [.text] __ZN15AMDCIVCEChannelC1Ev 0000000000081bdc g 0f SECT 01 0000 [.text] __ZN15AMDCIVCEChannelC2EPK11OSMetaClass 0000000000081d02 g 0f SECT 01 0000 [.text] __ZN15AMDCIVCEChannelC2Ev 0000000000081c30 g 0f SECT 01 0000 [.text] __ZN15AMDCIVCEChannelD0Ev 0000000000081c26 g 0f SECT 01 0000 [.text] __ZN15AMDCIVCEChannelD1Ev 0000000000081c1c g 0f SECT 01 0000 [.text] __ZN15AMDCIVCEChannelD2Ev 000000000052e8a0 g 0f SECT 0a 0000 [__DATA.__common] __ZN15AMDCIVCELLQRing10gMetaClassE 00000000003b8078 g 0f SECT 08 0000 [.const_data] __ZN15AMDCIVCELLQRing10superClassE 0000000000082b44 g 0f SECT 01 0000 [.text] __ZN15AMDCIVCELLQRing16registerLocationEv 0000000000082b32 g 0f SECT 01 0000 [.text] __ZN15AMDCIVCELLQRing4freeEv 0000000000082a92 g 0f SECT 01 0000 [.text] __ZN15AMDCIVCELLQRing4initEP30AMDRadeonX4000_IAMDHWInterfacei20_eAMD_HW_ENGINE_TYPEjPKv 0000000000082900 g 0f SECT 01 0000 [.text] __ZN15AMDCIVCELLQRing9MetaClassC1Ev 00000000000829c0 g 0f SECT 01 0000 [.text] __ZN15AMDCIVCELLQRing9MetaClassC2Ev 00000000003b8070 g 0f SECT 08 0000 [.const_data] __ZN15AMDCIVCELLQRing9metaClassE 000000000008295c g 0f SECT 01 0000 [.text] __ZN15AMDCIVCELLQRingC1EPK11OSMetaClass 0000000000082a32 g 0f SECT 01 0000 [.text] __ZN15AMDCIVCELLQRingC1Ev 000000000008293c g 0f SECT 01 0000 [.text] __ZN15AMDCIVCELLQRingC2EPK11OSMetaClass 0000000000082a62 g 0f SECT 01 0000 [.text] __ZN15AMDCIVCELLQRingC2Ev 0000000000082990 g 0f SECT 01 0000 [.text] __ZN15AMDCIVCELLQRingD0Ev 0000000000082986 g 0f SECT 01 0000 [.text] __ZN15AMDCIVCELLQRingD1Ev 000000000008297c g 0f SECT 01 0000 [.text] __ZN15AMDCIVCELLQRingD2Ev 000000000052e5d0 g 0f SECT 0a 0000 [__DATA.__common] __ZN15AMDCIsDMAEngine10gMetaClassE 00000000003b4048 g 0f SECT 08 0000 [.const_data] __ZN15AMDCIsDMAEngine10superClassE 0000000000079e0a g 0f SECT 01 0000 [.text] __ZN15AMDCIsDMAEngine15allocateHWRingsEv 0000000000079e46 g 0f SECT 01 0000 [.text] __ZN15AMDCIsDMAEngine18allocateHWChannelsEv 000000000007a2ce g 0f SECT 01 0000 [.text] __ZN15AMDCIsDMAEngine19dumpEngineHangStateEb 0000000000079d22 g 0f SECT 01 0000 [.text] __ZN15AMDCIsDMAEngine4initEP30AMDRadeonX4000_IAMDHWInterface20_eAMD_HW_ENGINE_TYPE 000000000007a164 g 0f SECT 01 0000 [.text] __ZN15AMDCIsDMAEngine4stopEv 0000000000079e92 g 0f SECT 01 0000 [.text] __ZN15AMDCIsDMAEngine5startEv 0000000000079dbe g 0f SECT 01 0000 [.text] __ZN15AMDCIsDMAEngine6isIdleEv 0000000000079b90 g 0f SECT 01 0000 [.text] __ZN15AMDCIsDMAEngine9MetaClassC1Ev 0000000000079c50 g 0f SECT 01 0000 [.text] __ZN15AMDCIsDMAEngine9MetaClassC2Ev 00000000003b4040 g 0f SECT 08 0000 [.const_data] __ZN15AMDCIsDMAEngine9metaClassE 0000000000079bec g 0f SECT 01 0000 [.text] __ZN15AMDCIsDMAEngineC1EPK11OSMetaClass 0000000000079cc2 g 0f SECT 01 0000 [.text] __ZN15AMDCIsDMAEngineC1Ev 0000000000079bcc g 0f SECT 01 0000 [.text] __ZN15AMDCIsDMAEngineC2EPK11OSMetaClass 0000000000079cf2 g 0f SECT 01 0000 [.text] __ZN15AMDCIsDMAEngineC2Ev 0000000000079c20 g 0f SECT 01 0000 [.text] __ZN15AMDCIsDMAEngineD0Ev 0000000000079c16 g 0f SECT 01 0000 [.text] __ZN15AMDCIsDMAEngineD1Ev 0000000000079c0c g 0f SECT 01 0000 [.text] __ZN15AMDCIsDMAEngineD2Ev 000000000052e2b0 g 0f SECT 0a 0000 [__DATA.__common] __ZN15AMDSIDMAChannel10gMetaClassE 00000000003aee18 g 0f SECT 08 0000 [.const_data] __ZN15AMDSIDMAChannel10superClassE 000000000006e170 g 0f SECT 01 0000 [.text] __ZN15AMDSIDMAChannel18submitVMInvalidateEjyj 000000000006e90e g 0f SECT 01 0000 [.text] __ZN15AMDSIDMAChannel20initializeDmaPktInfoEv 000000000006e89a g 0f SECT 01 0000 [.text] __ZN15AMDSIDMAChannel21writeProfilingCommandEPjyjb 000000000006dfb6 g 0f SECT 01 0000 [.text] __ZN15AMDSIDMAChannel21writeSRBMWriteCommandEPjjjj 000000000006e8ea g 0f SECT 01 0000 [.text] __ZN15AMDSIDMAChannel22timeStampInterruptTypeEv 000000000006df08 g 0f SECT 01 0000 [.text] __ZN15AMDSIDMAChannel22writeCopyLinearCommandEPjyyj 000000000006e066 g 0f SECT 01 0000 [.text] __ZN15AMDSIDMAChannel22writePollRegMemCommandEPjbyjjjjj 000000000006dd2c g 0f SECT 01 0000 [.text] __ZN15AMDSIDMAChannel23writeWriteLinearCommandEPjyjS0_ 000000000006de18 g 0f SECT 01 0000 [.text] __ZN15AMDSIDMAChannel23writeWritePTEPDECommandEPjyjyyy 000000000006dc92 g 0f SECT 01 0000 [.text] __ZN15AMDSIDMAChannel24writeConstantFillCommandEPjyjj 000000000006e2f2 g 0f SECT 01 0000 [.text] __ZN15AMDSIDMAChannel27commitIndirectCommandBufferEP30AMD_SUBMIT_COMMAND_BUFFER_INFO 000000000006e6c0 g 0f SECT 01 0000 [.text] __ZN15AMDSIDMAChannel27initializeVMInvalidateFrameEv 000000000006e684 g 0f SECT 01 0000 [.text] __ZN15AMDSIDMAChannel33releaseIndirectCommandBufferFrameEv 000000000006e55a g 0f SECT 01 0000 [.text] __ZN15AMDSIDMAChannel36initializeIndirectCommandBufferFrameEv 000000000006dc4a g 0f SECT 01 0000 [.text] __ZN15AMDSIDMAChannel4freeEv 000000000006dbf2 g 0f SECT 01 0000 [.text] __ZN15AMDSIDMAChannel4initEiP30AMDRadeonX4000_IAMDHWInterfaceP27AMDRadeonX4000_IAMDHWEngineP25AMDRadeonX4000_IAMDHWRingPKc 000000000006da60 g 0f SECT 01 0000 [.text] __ZN15AMDSIDMAChannel9MetaClassC1Ev 000000000006db20 g 0f SECT 01 0000 [.text] __ZN15AMDSIDMAChannel9MetaClassC2Ev 00000000003aee10 g 0f SECT 08 0000 [.const_data] __ZN15AMDSIDMAChannel9metaClassE 000000000006dabc g 0f SECT 01 0000 [.text] __ZN15AMDSIDMAChannelC1EPK11OSMetaClass 000000000006db92 g 0f SECT 01 0000 [.text] __ZN15AMDSIDMAChannelC1Ev 000000000006da9c g 0f SECT 01 0000 [.text] __ZN15AMDSIDMAChannelC2EPK11OSMetaClass 000000000006dbc2 g 0f SECT 01 0000 [.text] __ZN15AMDSIDMAChannelC2Ev 000000000006daf0 g 0f SECT 01 0000 [.text] __ZN15AMDSIDMAChannelD0Ev 000000000006dae6 g 0f SECT 01 0000 [.text] __ZN15AMDSIDMAChannelD1Ev 000000000006dadc g 0f SECT 01 0000 [.text] __ZN15AMDSIDMAChannelD2Ev 000000000052e238 g 0f SECT 0a 0000 [__DATA.__common] __ZN15AMDSIPM4Channel10gMetaClassE 00000000003ae3d8 g 0f SECT 08 0000 [.const_data] __ZN15AMDSIPM4Channel10superClassE 000000000006ca78 g 0f SECT 01 0000 [.text] __ZN15AMDSIPM4Channel19releaseSubmitFramesEv 000000000006cafe g 0f SECT 01 0000 [.text] __ZN15AMDSIPM4Channel19resetPerFramePacketEv 000000000006cab4 g 0f SECT 01 0000 [.text] __ZN15AMDSIPM4Channel19setupPerFramePacketEjjjj 000000000006cdb2 g 0f SECT 01 0000 [.text] __ZN15AMDSIPM4Channel20getIBAlignmentFactorEv 000000000006ccd6 g 0f SECT 01 0000 [.text] __ZN15AMDSIPM4Channel21writeProfilingCommandEPjyjb 000000000006c898 g 0f SECT 01 0000 [.text] __ZN15AMDSIPM4Channel22initializeSubmitFramesEv 000000000006c8da g 0f SECT 01 0000 [.text] __ZN15AMDSIPM4Channel24initializeTimestampFrameEv 000000000006c6fe g 0f SECT 01 0000 [.text] __ZN15AMDSIPM4Channel27commitIndirectCommandBufferEP30AMD_SUBMIT_COMMAND_BUFFER_INFO 000000000006cb98 g 0f SECT 01 0000 [.text] __ZN15AMDSIPM4Channel30enableScratchRegisterWritebackEv 000000000006cb1e g 0f SECT 01 0000 [.text] __ZN15AMDSIPM4Channel31disableScratchRegisterWritebackEv 000000000006c948 g 0f SECT 01 0000 [.text] __ZN15AMDSIPM4Channel36initializeIndirectCommandBufferFrameEv 000000000006c6b0 g 0f SECT 01 0000 [.text] __ZN15AMDSIPM4Channel48writeFlushAndInvalidateDestinationCachesCommandsEv 000000000006c69e g 0f SECT 01 0000 [.text] __ZN15AMDSIPM4Channel4freeEv 000000000006c682 g 0f SECT 01 0000 [.text] __ZN15AMDSIPM4Channel4initEiP30AMDRadeonX4000_IAMDHWInterfaceP27AMDRadeonX4000_IAMDHWEngineP25AMDRadeonX4000_IAMDHWRingPKc 000000000006c4f0 g 0f SECT 01 0000 [.text] __ZN15AMDSIPM4Channel9MetaClassC1Ev 000000000006c5b0 g 0f SECT 01 0000 [.text] __ZN15AMDSIPM4Channel9MetaClassC2Ev 00000000003ae3d0 g 0f SECT 08 0000 [.const_data] __ZN15AMDSIPM4Channel9metaClassE 000000000006c54c g 0f SECT 01 0000 [.text] __ZN15AMDSIPM4ChannelC1EPK11OSMetaClass 000000000006c622 g 0f SECT 01 0000 [.text] __ZN15AMDSIPM4ChannelC1Ev 000000000006c52c g 0f SECT 01 0000 [.text] __ZN15AMDSIPM4ChannelC2EPK11OSMetaClass 000000000006c652 g 0f SECT 01 0000 [.text] __ZN15AMDSIPM4ChannelC2Ev 000000000006c580 g 0f SECT 01 0000 [.text] __ZN15AMDSIPM4ChannelD0Ev 000000000006c576 g 0f SECT 01 0000 [.text] __ZN15AMDSIPM4ChannelD1Ev 000000000006c56c g 0f SECT 01 0000 [.text] __ZN15AMDSIPM4ChannelD2Ev 000000000052e468 g 0f SECT 0a 0000 [__DATA.__common] __ZN15AMDSISPUChannel10gMetaClassE 00000000003b1638 g 0f SECT 08 0000 [.const_data] __ZN15AMDSISPUChannel10superClassE 000000000007308c g 0f SECT 01 0000 [.text] __ZN15AMDSISPUChannel27commitIndirectCommandBufferEP30AMD_SUBMIT_COMMAND_BUFFER_INFO 000000000007307a g 0f SECT 01 0000 [.text] __ZN15AMDSISPUChannel4freeEv 0000000000073022 g 0f SECT 01 0000 [.text] __ZN15AMDSISPUChannel4initEiP30AMDRadeonX4000_IAMDHWInterfaceP27AMDRadeonX4000_IAMDHWEngineP25AMDRadeonX4000_IAMDHWRingPKc 0000000000072e90 g 0f SECT 01 0000 [.text] __ZN15AMDSISPUChannel9MetaClassC1Ev 0000000000072f50 g 0f SECT 01 0000 [.text] __ZN15AMDSISPUChannel9MetaClassC2Ev 00000000003b1630 g 0f SECT 08 0000 [.const_data] __ZN15AMDSISPUChannel9metaClassE 0000000000072eec g 0f SECT 01 0000 [.text] __ZN15AMDSISPUChannelC1EPK11OSMetaClass 0000000000072fc2 g 0f SECT 01 0000 [.text] __ZN15AMDSISPUChannelC1Ev 0000000000072ecc g 0f SECT 01 0000 [.text] __ZN15AMDSISPUChannelC2EPK11OSMetaClass 0000000000072ff2 g 0f SECT 01 0000 [.text] __ZN15AMDSISPUChannelC2Ev 0000000000072f20 g 0f SECT 01 0000 [.text] __ZN15AMDSISPUChannelD0Ev 0000000000072f16 g 0f SECT 01 0000 [.text] __ZN15AMDSISPUChannelD1Ev 0000000000072f0c g 0f SECT 01 0000 [.text] __ZN15AMDSISPUChannelD2Ev 000000000052e3c8 g 0f SECT 0a 0000 [__DATA.__common] __ZN15AMDSIUVDChannel10gMetaClassE 00000000003b06d8 g 0f SECT 08 0000 [.const_data] __ZN15AMDSIUVDChannel10superClassE 0000000000070fda g 0f SECT 01 0000 [.text] __ZN15AMDSIUVDChannel17initializeTrapCmdEv 0000000000070f92 g 0f SECT 01 0000 [.text] __ZN15AMDSIUVDChannel18initializeFenceCmdEv 000000000007112c g 0f SECT 01 0000 [.text] __ZN15AMDSIUVDChannel21getOneDwordNOPCommandEv 0000000000071138 g 0f SECT 01 0000 [.text] __ZN15AMDSIUVDChannel24capPerfTableStatesForUVDEb 0000000000071048 g 0f SECT 01 0000 [.text] __ZN15AMDSIUVDChannel27commitIndirectCommandBufferEP30AMD_SUBMIT_COMMAND_BUFFER_INFO 0000000000070f70 g 0f SECT 01 0000 [.text] __ZN15AMDSIUVDChannel27initializeIndirectBufferCmdEv 0000000000070ed8 g 0f SECT 01 0000 [.text] __ZN15AMDSIUVDChannel36initializeIndirectCommandBufferFrameEv 0000000000070ec6 g 0f SECT 01 0000 [.text] __ZN15AMDSIUVDChannel4freeEv 0000000000070e62 g 0f SECT 01 0000 [.text] __ZN15AMDSIUVDChannel4initEiP30AMDRadeonX4000_IAMDHWInterfaceP27AMDRadeonX4000_IAMDHWEngineP25AMDRadeonX4000_IAMDHWRingPKc 0000000000070cd0 g 0f SECT 01 0000 [.text] __ZN15AMDSIUVDChannel9MetaClassC1Ev 0000000000070d90 g 0f SECT 01 0000 [.text] __ZN15AMDSIUVDChannel9MetaClassC2Ev 00000000003b06d0 g 0f SECT 08 0000 [.const_data] __ZN15AMDSIUVDChannel9metaClassE 0000000000070d2c g 0f SECT 01 0000 [.text] __ZN15AMDSIUVDChannelC1EPK11OSMetaClass 0000000000070e02 g 0f SECT 01 0000 [.text] __ZN15AMDSIUVDChannelC1Ev 0000000000070d0c g 0f SECT 01 0000 [.text] __ZN15AMDSIUVDChannelC2EPK11OSMetaClass 0000000000070e32 g 0f SECT 01 0000 [.text] __ZN15AMDSIUVDChannelC2Ev 0000000000070d60 g 0f SECT 01 0000 [.text] __ZN15AMDSIUVDChannelD0Ev 0000000000070d56 g 0f SECT 01 0000 [.text] __ZN15AMDSIUVDChannelD1Ev 0000000000070d4c g 0f SECT 01 0000 [.text] __ZN15AMDSIUVDChannelD2Ev 000000000052e328 g 0f SECT 0a 0000 [__DATA.__common] __ZN15AMDSIVCEChannel10gMetaClassE 00000000003af938 g 0f SECT 08 0000 [.const_data] __ZN15AMDSIVCEChannel10superClassE 000000000006fd40 g 0f SECT 01 0000 [.text] __ZN15AMDSIVCEChannel22getIndirectCommandSizeEv 000000000006fdfc g 0f SECT 01 0000 [.text] __ZN15AMDSIVCEChannel27commitIndirectCommandBufferEP30AMD_SUBMIT_COMMAND_BUFFER_INFO 000000000006fd92 g 0f SECT 01 0000 [.text] __ZN15AMDSIVCEChannel36initializeIndirectCommandBufferFrameEv 000000000006fd2e g 0f SECT 01 0000 [.text] __ZN15AMDSIVCEChannel4freeEv 000000000006fd12 g 0f SECT 01 0000 [.text] __ZN15AMDSIVCEChannel4initEiP30AMDRadeonX4000_IAMDHWInterfaceP27AMDRadeonX4000_IAMDHWEngineP25AMDRadeonX4000_IAMDHWRingPKc 000000000006fb80 g 0f SECT 01 0000 [.text] __ZN15AMDSIVCEChannel9MetaClassC1Ev 000000000006fc40 g 0f SECT 01 0000 [.text] __ZN15AMDSIVCEChannel9MetaClassC2Ev 00000000003af930 g 0f SECT 08 0000 [.const_data] __ZN15AMDSIVCEChannel9metaClassE 000000000006fbdc g 0f SECT 01 0000 [.text] __ZN15AMDSIVCEChannelC1EPK11OSMetaClass 000000000006fcb2 g 0f SECT 01 0000 [.text] __ZN15AMDSIVCEChannelC1Ev 000000000006fbbc g 0f SECT 01 0000 [.text] __ZN15AMDSIVCEChannelC2EPK11OSMetaClass 000000000006fce2 g 0f SECT 01 0000 [.text] __ZN15AMDSIVCEChannelC2Ev 000000000006fc10 g 0f SECT 01 0000 [.text] __ZN15AMDSIVCEChannelD0Ev 000000000006fc06 g 0f SECT 01 0000 [.text] __ZN15AMDSIVCEChannelD1Ev 000000000006fbfc g 0f SECT 01 0000 [.text] __ZN15AMDSIVCEChannelD2Ev 000000000052e3a0 g 0f SECT 0a 0000 [__DATA.__common] __ZN15AMDSIVCELLQRing10gMetaClassE 00000000003b03b8 g 0f SECT 08 0000 [.const_data] __ZN15AMDSIVCELLQRing10superClassE 0000000000070b24 g 0f SECT 01 0000 [.text] __ZN15AMDSIVCELLQRing16registerLocationEv 0000000000070b12 g 0f SECT 01 0000 [.text] __ZN15AMDSIVCELLQRing4freeEv 0000000000070a72 g 0f SECT 01 0000 [.text] __ZN15AMDSIVCELLQRing4initEP30AMDRadeonX4000_IAMDHWInterfacei20_eAMD_HW_ENGINE_TYPEjPKv 00000000000708e0 g 0f SECT 01 0000 [.text] __ZN15AMDSIVCELLQRing9MetaClassC1Ev 00000000000709a0 g 0f SECT 01 0000 [.text] __ZN15AMDSIVCELLQRing9MetaClassC2Ev 00000000003b03b0 g 0f SECT 08 0000 [.const_data] __ZN15AMDSIVCELLQRing9metaClassE 000000000007093c g 0f SECT 01 0000 [.text] __ZN15AMDSIVCELLQRingC1EPK11OSMetaClass 0000000000070a12 g 0f SECT 01 0000 [.text] __ZN15AMDSIVCELLQRingC1Ev 000000000007091c g 0f SECT 01 0000 [.text] __ZN15AMDSIVCELLQRingC2EPK11OSMetaClass 0000000000070a42 g 0f SECT 01 0000 [.text] __ZN15AMDSIVCELLQRingC2Ev 0000000000070970 g 0f SECT 01 0000 [.text] __ZN15AMDSIVCELLQRingD0Ev 0000000000070966 g 0f SECT 01 0000 [.text] __ZN15AMDSIVCELLQRingD1Ev 000000000007095c g 0f SECT 01 0000 [.text] __ZN15AMDSIVCELLQRingD2Ev 000000000052eb20 g 0f SECT 0a 0000 [__DATA.__common] __ZN15AMDVIPM4Channel10gMetaClassE 00000000003bbcc8 g 0f SECT 08 0000 [.const_data] __ZN15AMDVIPM4Channel10superClassE 000000000008ed5a g 0f SECT 01 0000 [.text] __ZN15AMDVIPM4Channel18clearResetEOPFenceEv 000000000008e8e6 g 0f SECT 01 0000 [.text] __ZN15AMDVIPM4Channel18initializeCSBFrameEv 000000000008ebb0 g 0f SECT 01 0000 [.text] __ZN15AMDVIPM4Channel19eventWriteCmdPacketEP18PM4_ME_EVENT_WRITE31ME_EVENT_WRITE_event_index_enumj 000000000008e572 g 0f SECT 01 0000 [.text] __ZN15AMDVIPM4Channel19releaseSubmitFramesEv 000000000008ebd0 g 0f SECT 01 0000 [.text] __ZN15AMDVIPM4Channel20getIBAlignmentFactorEv 000000000008e2d2 g 0f SECT 01 0000 [.text] __ZN15AMDVIPM4Channel20surfaceSyncCmdPacketEP19PM4_ME_SURFACE_SYNCjyyj 000000000008ea34 g 0f SECT 01 0000 [.text] __ZN15AMDVIPM4Channel21writeProfilingCommandEPjyjb 000000000008e218 g 0f SECT 01 0000 [.text] __ZN15AMDVIPM4Channel21writeRegDataCmdPacketEP17PM4_ME_WRITE_DATA26ME_WRITE_DATA_dst_sel_enum28ME_WRITE_DATA_addr_incr_enum29ME_WRITE_DATA_wr_confirm_enum31ME_WRITE_DATA_cache_policy_enum29ME_WRITE_DATA_engine_sel_enumtPKjj 000000000008e670 g 0f SECT 01 0000 [.text] __ZN15AMDVIPM4Channel22eventWriteEOPCmdPacketEP22PM4_ME_EVENT_WRITE_EOPj35ME_EVENT_WRITE_EOP_event_index_enum36ME_EVENT_WRITE_EOP_cache_policy_enum31ME_EVENT_WRITE_EOP_dst_sel_enum31ME_EVENT_WRITE_EOP_int_sel_enum32ME_EVENT_WRITE_EOP_data_sel_enumyy 000000000008e524 g 0f SECT 01 0000 [.text] __ZN15AMDVIPM4Channel22initializeSubmitFramesEv 000000000008ec3e g 0f SECT 01 0000 [.text] __ZN15AMDVIPM4Channel22writeEventWriteCommandEPjjj 000000000008ed76 g 0f SECT 01 0000 [.text] __ZN15AMDVIPM4Channel23isResetEOPFenceFinishedEv 000000000008ebdc g 0f SECT 01 0000 [.text] __ZN15AMDVIPM4Channel23writeSurfaceSyncCommandEPjjyyj 000000000008e5ae g 0f SECT 01 0000 [.text] __ZN15AMDVIPM4Channel24initializeTimestampFrameEv 000000000008ec5c g 0f SECT 01 0000 [.text] __ZN15AMDVIPM4Channel25writeEventWriteEOPCommandEPjjjyjjy 000000000008e334 g 0f SECT 01 0000 [.text] __ZN15AMDVIPM4Channel27commitIndirectCommandBufferEP30AMD_SUBMIT_COMMAND_BUFFER_INFO 000000000008ec94 g 0f SECT 01 0000 [.text] __ZN15AMDVIPM4Channel28prepareAndFlushResetEOPFenceEv 000000000008e724 g 0f SECT 01 0000 [.text] __ZN15AMDVIPM4Channel36initializeIndirectCommandBufferFrameEv 000000000008e0d4 g 0f SECT 01 0000 [.text] __ZN15AMDVIPM4Channel48writeFlushAndInvalidateDestinationCachesCommandsEv 000000000008e0c2 g 0f SECT 01 0000 [.text] __ZN15AMDVIPM4Channel4freeEv 000000000008e052 g 0f SECT 01 0000 [.text] __ZN15AMDVIPM4Channel4initEiP30AMDRadeonX4000_IAMDHWInterfaceP27AMDRadeonX4000_IAMDHWEngineP25AMDRadeonX4000_IAMDHWRingPKc 000000000008dec0 g 0f SECT 01 0000 [.text] __ZN15AMDVIPM4Channel9MetaClassC1Ev 000000000008df80 g 0f SECT 01 0000 [.text] __ZN15AMDVIPM4Channel9MetaClassC2Ev 00000000003bbcc0 g 0f SECT 08 0000 [.const_data] __ZN15AMDVIPM4Channel9metaClassE 000000000008df1c g 0f SECT 01 0000 [.text] __ZN15AMDVIPM4ChannelC1EPK11OSMetaClass 000000000008dff2 g 0f SECT 01 0000 [.text] __ZN15AMDVIPM4ChannelC1Ev 000000000008defc g 0f SECT 01 0000 [.text] __ZN15AMDVIPM4ChannelC2EPK11OSMetaClass 000000000008e022 g 0f SECT 01 0000 [.text] __ZN15AMDVIPM4ChannelC2Ev 000000000008df50 g 0f SECT 01 0000 [.text] __ZN15AMDVIPM4ChannelD0Ev 000000000008df46 g 0f SECT 01 0000 [.text] __ZN15AMDVIPM4ChannelD1Ev 000000000008df3c g 0f SECT 01 0000 [.text] __ZN15AMDVIPM4ChannelD2Ev 000000000052ebc0 g 0f SECT 0a 0000 [__DATA.__common] __ZN15AMDVISAMUEngine10gMetaClassE 00000000003bcb18 g 0f SECT 08 0000 [.const_data] __ZN15AMDVISAMUEngine10superClassE 0000000000092464 g 0f SECT 01 0000 [.text] __ZN15AMDVISAMUEngine15allocateHWRingsEv 00000000000924ea g 0f SECT 01 0000 [.text] __ZN15AMDVISAMUEngine18allocateHWChannelsEv 0000000000092560 g 0f SECT 01 0000 [.text] __ZN15AMDVISAMUEngine18readIndirectSPURegEj 0000000000092668 g 0f SECT 01 0000 [.text] __ZN15AMDVISAMUEngine19dumpEngineHangStateEb 00000000000925a0 g 0f SECT 01 0000 [.text] __ZN15AMDVISAMUEngine19writeIndirectSPURegEjj 00000000000925e4 g 0f SECT 01 0000 [.text] __ZN15AMDVISAMUEngine22readIndirectSAMUSABRegEj 0000000000092624 g 0f SECT 01 0000 [.text] __ZN15AMDVISAMUEngine23writeIndirectSAMUSABRegEjj 0000000000092452 g 0f SECT 01 0000 [.text] __ZN15AMDVISAMUEngine4initEP30AMDRadeonX4000_IAMDHWInterface20_eAMD_HW_ENGINE_TYPE 00000000000922c0 g 0f SECT 01 0000 [.text] __ZN15AMDVISAMUEngine9MetaClassC1Ev 0000000000092380 g 0f SECT 01 0000 [.text] __ZN15AMDVISAMUEngine9MetaClassC2Ev 00000000003bcb10 g 0f SECT 08 0000 [.const_data] __ZN15AMDVISAMUEngine9metaClassE 000000000009231c g 0f SECT 01 0000 [.text] __ZN15AMDVISAMUEngineC1EPK11OSMetaClass 00000000000923f2 g 0f SECT 01 0000 [.text] __ZN15AMDVISAMUEngineC1Ev 00000000000922fc g 0f SECT 01 0000 [.text] __ZN15AMDVISAMUEngineC2EPK11OSMetaClass 0000000000092422 g 0f SECT 01 0000 [.text] __ZN15AMDVISAMUEngineC2Ev 0000000000092350 g 0f SECT 01 0000 [.text] __ZN15AMDVISAMUEngineD0Ev 0000000000092346 g 0f SECT 01 0000 [.text] __ZN15AMDVISAMUEngineD1Ev 000000000009233c g 0f SECT 01 0000 [.text] __ZN15AMDVISAMUEngineD2Ev 000000000052ea80 g 0f SECT 0a 0000 [__DATA.__common] __ZN15AMDVIsDMAEngine10gMetaClassE 00000000003bb028 g 0f SECT 08 0000 [.const_data] __ZN15AMDVIsDMAEngine10superClassE 000000000008c8b6 g 0f SECT 01 0000 [.text] __ZN15AMDVIsDMAEngine15allocateHWRingsEv 000000000008c8f2 g 0f SECT 01 0000 [.text] __ZN15AMDVIsDMAEngine18allocateHWChannelsEv 000000000008cd7a g 0f SECT 01 0000 [.text] __ZN15AMDVIsDMAEngine19dumpEngineHangStateEb 000000000008c7f2 g 0f SECT 01 0000 [.text] __ZN15AMDVIsDMAEngine4initEP30AMDRadeonX4000_IAMDHWInterface20_eAMD_HW_ENGINE_TYPE 000000000008cc10 g 0f SECT 01 0000 [.text] __ZN15AMDVIsDMAEngine4stopEv 000000000008c93e g 0f SECT 01 0000 [.text] __ZN15AMDVIsDMAEngine5startEv 000000000008c838 g 0f SECT 01 0000 [.text] __ZN15AMDVIsDMAEngine6isIdleEv 000000000008c660 g 0f SECT 01 0000 [.text] __ZN15AMDVIsDMAEngine9MetaClassC1Ev 000000000008c720 g 0f SECT 01 0000 [.text] __ZN15AMDVIsDMAEngine9MetaClassC2Ev 00000000003bb020 g 0f SECT 08 0000 [.const_data] __ZN15AMDVIsDMAEngine9metaClassE 000000000008c6bc g 0f SECT 01 0000 [.text] __ZN15AMDVIsDMAEngineC1EPK11OSMetaClass 000000000008c792 g 0f SECT 01 0000 [.text] __ZN15AMDVIsDMAEngineC1Ev 000000000008c69c g 0f SECT 01 0000 [.text] __ZN15AMDVIsDMAEngineC2EPK11OSMetaClass 000000000008c7c2 g 0f SECT 01 0000 [.text] __ZN15AMDVIsDMAEngineC2Ev 000000000008c6f0 g 0f SECT 01 0000 [.text] __ZN15AMDVIsDMAEngineD0Ev 000000000008c6e6 g 0f SECT 01 0000 [.text] __ZN15AMDVIsDMAEngineD1Ev 000000000008c6dc g 0f SECT 01 0000 [.text] __ZN15AMDVIsDMAEngineD2Ev 00000000000a7446 g 0f SECT 01 0000 [.text] __ZN15ShaderVidMemMgr19CpuLoadSingleShaderEP9BltShader 00000000000a7510 g 0f SECT 01 0000 [.text] __ZN15ShaderVidMemMgr21AllocVidMemForShadersEP23_UBM_ALLOCVIDMEM_OUTPUTjjP22_UBM_ALLOCVIDMEM_INPUT 00000000000a7324 g 0f SECT 01 0000 [.text] __ZN15ShaderVidMemMgrC2EP6BltMgr 00000000000a742a g 0f SECT 01 0000 [.text] __ZN15ShaderVidMemMgrD0Ev 00000000000a73ea g 0f SECT 01 0000 [.text] __ZN15ShaderVidMemMgrD1Ev 00000000000a73aa g 0f SECT 01 0000 [.text] __ZN15ShaderVidMemMgrD2Ev 00000000000aa82c g 0f SECT 01 0000 [.text] __ZN15SiBltAuxSurfMgr14HwlInitHiSSurfEPK13_UBM_SURFINFOP13CachedAuxSurf 00000000000aa0dc g 0f SECT 01 0000 [.text] __ZN15SiBltAuxSurfMgr15HwlInitGradSurfEPK13_UBM_SURFINFOP13CachedAuxSurf 00000000000aaac0 g 0f SECT 01 0000 [.text] __ZN15SiBltAuxSurfMgr17GetCmaskAsTexSizeEPK13_UBM_SURFINFOPjS3_ 00000000000a9ea2 g 0f SECT 01 0000 [.text] __ZN15SiBltAuxSurfMgr17HwlInitPixPreSurfEPK13_UBM_SURFINFOP13CachedAuxSurf 00000000000a84be g 0f SECT 01 0000 [.text] __ZN15SiBltAuxSurfMgr18SetupOffsetTexDataEPK13_UBM_SURFINFOjP13CachedAuxSurf 00000000000a7f36 g 0f SECT 01 0000 [.text] __ZN15SiBltAuxSurfMgr18UseHtileLinearModeEPK13_UBM_SURFINFO 00000000000a7f66 g 0f SECT 01 0000 [.text] __ZN15SiBltAuxSurfMgr19GetHtileActualWidthEP31_ADDR_COMPUTE_HTILE_INFO_OUTPUT 00000000000a7f88 g 0f SECT 01 0000 [.text] __ZN15SiBltAuxSurfMgr19GetHtileSizeInBytesEP31_ADDR_COMPUTE_HTILE_INFO_OUTPUT 00000000000a9c7a g 0f SECT 01 0000 [.text] __ZN15SiBltAuxSurfMgr19HwlInitEdgeMaskSurfEPK13_UBM_SURFINFOP13CachedAuxSurf 00000000000a7f72 g 0f SECT 01 0000 [.text] __ZN15SiBltAuxSurfMgr20GetHtileActualHeightEP31_ADDR_COMPUTE_HTILE_INFO_OUTPUT 00000000000a7f9c g 0f SECT 01 0000 [.text] __ZN15SiBltAuxSurfMgr20HwlInitOffsetTexSurfEPK13_UBM_SURFINFOP13CachedAuxSurf 00000000000aa2ce g 0f SECT 01 0000 [.text] __ZN15SiBltAuxSurfMgr21HwlInitAdvAaDepthSurfEPK13_UBM_SURFINFOP13CachedAuxSurf 00000000000a8ede g 0f SECT 01 0000 [.text] __ZN15SiBltAuxSurfMgr21HwlInitCmaskAsTexSurfEPK13_UBM_SURFINFOP13CachedAuxSurf 00000000000a9086 g 0f SECT 01 0000 [.text] __ZN15SiBltAuxSurfMgr21HwlInitFmaskAsTexSurfEPK13_UBM_SURFINFOP13CachedAuxSurf 00000000000a92b2 g 0f SECT 01 0000 [.text] __ZN15SiBltAuxSurfMgr22HwlGenerateFmaskTexKeyEPK13_UBM_SURFINFO 00000000000a978e g 0f SECT 01 0000 [.text] __ZN15SiBltAuxSurfMgr22HwlInitHTileOffsetSurfEPK13_UBM_SURFINFOS2_P13CachedAuxSurf 00000000000a9566 g 0f SECT 01 0000 [.text] __ZN15SiBltAuxSurfMgr22HwlInitMlaaSepEdgeSurfEPK13_UBM_SURFINFOP13CachedAuxSurf 00000000000a8c20 g 0f SECT 01 0000 [.text] __ZN15SiBltAuxSurfMgr23HwlDestroyOffsetTexSurfEP13CachedAuxSurf 00000000000aac54 g 0f SECT 01 0000 [.text] __ZN15SiBltAuxSurfMgr23HwlGenerateOffsetTexKeyEPK13_UBM_SURFINFO 00000000000a8c56 g 0f SECT 01 0000 [.text] __ZN15SiBltAuxSurfMgr23HwlInitHtileAsColorSurfEPK13_UBM_SURFINFOP13CachedAuxSurf 00000000000aa5fa g 0f SECT 01 0000 [.text] __ZN15SiBltAuxSurfMgr23HwlInitNeighborMaskSurfEPK13_UBM_SURFINFOP13CachedAuxSurf 00000000000a92f0 g 0f SECT 01 0000 [.text] __ZN15SiBltAuxSurfMgr24HwlInitMlaaEdgeCountSurfEPK13_UBM_SURFINFOP13CachedAuxSurf21MlaaEdgeCountSurfDesc 00000000000a82a6 g 0f SECT 01 0000 [.text] __ZN15SiBltAuxSurfMgr25DepthWidthHeightFromColorEPK13_UBM_SURFINFOPjS3_Pi 00000000000a9c44 g 0f SECT 01 0000 [.text] __ZN15SiBltAuxSurfMgr25HwlDestroyHTileOffsetSurfEP13CachedAuxSurf 00000000000a7ecc g 0f SECT 01 0000 [.text] __ZN15SiBltAuxSurfMgr6CreateEP8SiBltMgr 00000000000a7f24 g 0f SECT 01 0000 [.text] __ZN15SiBltAuxSurfMgr7DestroyEv 00000000000a7f1c g 0f SECT 01 0000 [.text] __ZN15SiBltAuxSurfMgr7HwlInitEv 00000000000a7eac g 0f SECT 01 0000 [.text] __ZN15SiBltAuxSurfMgrC1Ev 00000000000a7e8c g 0f SECT 01 0000 [.text] __ZN15SiBltAuxSurfMgrC2Ev 00000000000cbae6 g 0f SECT 01 0000 [.text] __ZN15SiSurfAttribute10GetPipeNumE10PipeConfig 00000000000cb18c g 0f SECT 01 0000 [.text] __ZN15SiSurfAttribute12CreateObjectEv 00000000000cb414 g 0f SECT 01 0000 [.text] __ZN15SiSurfAttribute4InitEPK15_UBM_CREATEINFO 00000000000cb1f0 g 0f SECT 01 0000 [.text] __ZN15SiSurfAttributeC1Ev 00000000000cb2a8 g 0f SECT 01 0000 [.text] __ZN15SiSurfAttributeC2Ev 00000000000cb3f8 g 0f SECT 01 0000 [.text] __ZN15SiSurfAttributeD0Ev 00000000000cb37a g 0f SECT 01 0000 [.text] __ZN15SiSurfAttributeD1Ev 00000000000cb2fc g 0f SECT 01 0000 [.text] __ZN15SiSurfAttributeD2Ev 000000000052e8c8 g 0f SECT 0a 0000 [__DATA.__common] __ZN16AMDCIComputeRing10gMetaClassE 00000000003b8398 g 0f SECT 08 0000 [.const_data] __ZN16AMDCIComputeRing10superClassE 0000000000082f68 g 0f SECT 01 0000 [.text] __ZN16AMDCIComputeRing16registerLocationEv 0000000000082f28 g 0f SECT 01 0000 [.text] __ZN16AMDCIComputeRing17allocateResourcesEv 0000000000082f70 g 0f SECT 01 0000 [.text] __ZN16AMDCIComputeRing26enableReadPointerWriteBackEv 0000000000082f76 g 0f SECT 01 0000 [.text] __ZN16AMDCIComputeRing27disableReadPointerWriteBackEv 0000000000082f90 g 0f SECT 01 0000 [.text] __ZN16AMDCIComputeRing27programReadAndWritePointersEj 0000000000082e82 g 0f SECT 01 0000 [.text] __ZN16AMDCIComputeRing4initEP30AMDRadeonX4000_IAMDHWInterfacei20_eAMD_HW_ENGINE_TYPEjPKv 00000000000830c4 g 0f SECT 01 0000 [.text] __ZN16AMDCIComputeRing5alignEv 0000000000082f7c g 0f SECT 01 0000 [.text] __ZN16AMDCIComputeRing5resetEv 0000000000082cf0 g 0f SECT 01 0000 [.text] __ZN16AMDCIComputeRing9MetaClassC1Ev 0000000000082db0 g 0f SECT 01 0000 [.text] __ZN16AMDCIComputeRing9MetaClassC2Ev 00000000003b8390 g 0f SECT 08 0000 [.const_data] __ZN16AMDCIComputeRing9metaClassE 00000000000830f4 g 0f SECT 01 0000 [.text] __ZN16AMDCIComputeRing9writeTailEv 0000000000082d4c g 0f SECT 01 0000 [.text] __ZN16AMDCIComputeRingC1EPK11OSMetaClass 0000000000082e22 g 0f SECT 01 0000 [.text] __ZN16AMDCIComputeRingC1Ev 0000000000082d2c g 0f SECT 01 0000 [.text] __ZN16AMDCIComputeRingC2EPK11OSMetaClass 0000000000082e52 g 0f SECT 01 0000 [.text] __ZN16AMDCIComputeRingC2Ev 0000000000082d80 g 0f SECT 01 0000 [.text] __ZN16AMDCIComputeRingD0Ev 0000000000082d76 g 0f SECT 01 0000 [.text] __ZN16AMDCIComputeRingD1Ev 0000000000082d6c g 0f SECT 01 0000 [.text] __ZN16AMDCIComputeRingD2Ev 000000000052e698 g 0f SECT 0a 0000 [__DATA.__common] __ZN16AMDCIHWUtilities10gMetaClassE 00000000003b5168 g 0f SECT 08 0000 [.const_data] __ZN16AMDCIHWUtilities10superClassE 000000000007cfd2 g 0f SECT 01 0000 [.text] __ZN16AMDCIHWUtilities16setupUBMChipInfoEP13_UBM_CHIPINFO 000000000007d06e g 0f SECT 01 0000 [.text] __ZN16AMDCIHWUtilities21filterUBMFormatForOCLE11_UBM_FORMAT 000000000007ce40 g 0f SECT 01 0000 [.text] __ZN16AMDCIHWUtilities9MetaClassC1Ev 000000000007cf00 g 0f SECT 01 0000 [.text] __ZN16AMDCIHWUtilities9MetaClassC2Ev 00000000003b5160 g 0f SECT 08 0000 [.const_data] __ZN16AMDCIHWUtilities9metaClassE 000000000007ce9c g 0f SECT 01 0000 [.text] __ZN16AMDCIHWUtilitiesC1EPK11OSMetaClass 000000000007cf72 g 0f SECT 01 0000 [.text] __ZN16AMDCIHWUtilitiesC1Ev 000000000007ce7c g 0f SECT 01 0000 [.text] __ZN16AMDCIHWUtilitiesC2EPK11OSMetaClass 000000000007cfa2 g 0f SECT 01 0000 [.text] __ZN16AMDCIHWUtilitiesC2Ev 000000000007ced0 g 0f SECT 01 0000 [.text] __ZN16AMDCIHWUtilitiesD0Ev 000000000007cec6 g 0f SECT 01 0000 [.text] __ZN16AMDCIHWUtilitiesD1Ev 000000000007cebc g 0f SECT 01 0000 [.text] __ZN16AMDCIHWUtilitiesD2Ev 000000000052e738 g 0f SECT 0a 0000 [__DATA.__common] __ZN16AMDCISAMURBIRing10gMetaClassE 00000000003b5fb8 g 0f SECT 08 0000 [.const_data] __ZN16AMDCISAMURBIRing10superClassE 000000000007fd6e g 0f SECT 01 0000 [.text] __ZN16AMDCISAMURBIRing11commitBlockEj 000000000007fc0c g 0f SECT 01 0000 [.text] __ZN16AMDCISAMURBIRing12getFreeSpaceEv 000000000007fd88 g 0f SECT 01 0000 [.text] __ZN16AMDCISAMURBIRing14getReadPointerEv 000000000007fda8 g 0f SECT 01 0000 [.text] __ZN16AMDCISAMURBIRing15getWritePointerEv 000000000007fc44 g 0f SECT 01 0000 [.text] __ZN16AMDCISAMURBIRing16registerLocationEv 000000000007fc68 g 0f SECT 01 0000 [.text] __ZN16AMDCISAMURBIRing26enableReadPointerWriteBackEv 000000000007fc6e g 0f SECT 01 0000 [.text] __ZN16AMDCISAMURBIRing27disableReadPointerWriteBackEv 000000000007fccc g 0f SECT 01 0000 [.text] __ZN16AMDCISAMURBIRing27programReadAndWritePointersEj 000000000007fbb2 g 0f SECT 01 0000 [.text] __ZN16AMDCISAMURBIRing4freeEv 000000000007fb12 g 0f SECT 01 0000 [.text] __ZN16AMDCISAMURBIRing4initEP30AMDRadeonX4000_IAMDHWInterfacei20_eAMD_HW_ENGINE_TYPEjPKv 000000000007fd82 g 0f SECT 01 0000 [.text] __ZN16AMDCISAMURBIRing5alignEv 000000000007fc74 g 0f SECT 01 0000 [.text] __ZN16AMDCISAMURBIRing5resetEv 000000000007fd4e g 0f SECT 01 0000 [.text] __ZN16AMDCISAMURBIRing5writeEj 000000000007fbee g 0f SECT 01 0000 [.text] __ZN16AMDCISAMURBIRing7getHeadEv 000000000007fbfc g 0f SECT 01 0000 [.text] __ZN16AMDCISAMURBIRing7getTailEv 000000000007f980 g 0f SECT 01 0000 [.text] __ZN16AMDCISAMURBIRing9MetaClassC1Ev 000000000007fa40 g 0f SECT 01 0000 [.text] __ZN16AMDCISAMURBIRing9MetaClassC2Ev 00000000003b5fb0 g 0f SECT 08 0000 [.const_data] __ZN16AMDCISAMURBIRing9metaClassE 000000000007fdc8 g 0f SECT 01 0000 [.text] __ZN16AMDCISAMURBIRing9writeTailEv 000000000007f9dc g 0f SECT 01 0000 [.text] __ZN16AMDCISAMURBIRingC1EPK11OSMetaClass 000000000007fab2 g 0f SECT 01 0000 [.text] __ZN16AMDCISAMURBIRingC1Ev 000000000007f9bc g 0f SECT 01 0000 [.text] __ZN16AMDCISAMURBIRingC2EPK11OSMetaClass 000000000007fae2 g 0f SECT 01 0000 [.text] __ZN16AMDCISAMURBIRingC2Ev 000000000007fa10 g 0f SECT 01 0000 [.text] __ZN16AMDCISAMURBIRingD0Ev 000000000007fa06 g 0f SECT 01 0000 [.text] __ZN16AMDCISAMURBIRingD1Ev 000000000007f9fc g 0f SECT 01 0000 [.text] __ZN16AMDCISAMURBIRingD2Ev 000000000052e7d8 g 0f SECT 0a 0000 [__DATA.__common] __ZN16AMDCIUVDHWEngine10gMetaClassE 0000000000081136 g 0f SECT 01 0000 [.text] __ZN16AMDCIUVDHWEngine10getUVDDclkEv 0000000000081108 g 0f SECT 01 0000 [.text] __ZN16AMDCIUVDHWEngine10getUVDVclkEv 00000000003b6d68 g 0f SECT 08 0000 [.const_data] __ZN16AMDCIUVDHWEngine10superClassE 0000000000081100 g 0f SECT 01 0000 [.text] __ZN16AMDCIUVDHWEngine11setVclkDclkEjj 000000000008105e g 0f SECT 01 0000 [.text] __ZN16AMDCIUVDHWEngine12initHardwareEv 0000000000081164 g 0f SECT 01 0000 [.text] __ZN16AMDCIUVDHWEngine14queryClockInfoEPjS0_S0_ 000000000008123c g 0f SECT 01 0000 [.text] __ZN16AMDCIUVDHWEngine16getActualDividerEj 0000000000081002 g 0f SECT 01 0000 [.text] __ZN16AMDCIUVDHWEngine4initEP30AMDRadeonX4000_IAMDHWInterface20_eAMD_HW_ENGINE_TYPE 0000000000080e70 g 0f SECT 01 0000 [.text] __ZN16AMDCIUVDHWEngine9MetaClassC1Ev 0000000000080f30 g 0f SECT 01 0000 [.text] __ZN16AMDCIUVDHWEngine9MetaClassC2Ev 00000000003b6d60 g 0f SECT 08 0000 [.const_data] __ZN16AMDCIUVDHWEngine9metaClassE 0000000000080ecc g 0f SECT 01 0000 [.text] __ZN16AMDCIUVDHWEngineC1EPK11OSMetaClass 0000000000080fa2 g 0f SECT 01 0000 [.text] __ZN16AMDCIUVDHWEngineC1Ev 0000000000080eac g 0f SECT 01 0000 [.text] __ZN16AMDCIUVDHWEngineC2EPK11OSMetaClass 0000000000080fd2 g 0f SECT 01 0000 [.text] __ZN16AMDCIUVDHWEngineC2Ev 0000000000080f00 g 0f SECT 01 0000 [.text] __ZN16AMDCIUVDHWEngineD0Ev 0000000000080ef6 g 0f SECT 01 0000 [.text] __ZN16AMDCIUVDHWEngineD1Ev 0000000000080eec g 0f SECT 01 0000 [.text] __ZN16AMDCIUVDHWEngineD2Ev 000000000052e800 g 0f SECT 0a 0000 [__DATA.__common] __ZN16AMDCIVCEHWEngine10gMetaClassE 0000000000081988 g 0f SECT 01 0000 [.text] __ZN16AMDCIVCEHWEngine10getVCECClkEv 00000000003b71f8 g 0f SECT 08 0000 [.const_data] __ZN16AMDCIVCEHWEngine10superClassE 00000000000815ce g 0f SECT 01 0000 [.text] __ZN16AMDCIVCEHWEngine12initHardwareEv 0000000000081980 g 0f SECT 01 0000 [.text] __ZN16AMDCIVCEHWEngine13setEVClkECClkEjj 00000000000819b6 g 0f SECT 01 0000 [.text] __ZN16AMDCIVCEHWEngine14queryClockInfoEPjS0_S0_ 000000000008179a g 0f SECT 01 0000 [.text] __ZN16AMDCIVCEHWEngine15allocateHWRingsEv 000000000008163a g 0f SECT 01 0000 [.text] __ZN16AMDCIVCEHWEngine15releaseHardwareEv 0000000000081a54 g 0f SECT 01 0000 [.text] __ZN16AMDCIVCEHWEngine16getActualDividerEj 0000000000081704 g 0f SECT 01 0000 [.text] __ZN16AMDCIVCEHWEngine17initHardwareRingsEv 0000000000081806 g 0f SECT 01 0000 [.text] __ZN16AMDCIVCEHWEngine18allocateHWChannelsEv 0000000000081886 g 0f SECT 01 0000 [.text] __ZN16AMDCIVCEHWEngine18configCacheWindowsEv 0000000000081a86 g 0f SECT 01 0000 [.text] __ZN16AMDCIVCEHWEngine19dumpEngineHangStateEb 0000000000081770 g 0f SECT 01 0000 [.text] __ZN16AMDCIVCEHWEngine20releaseHardwareRingsEv 00000000000815bc g 0f SECT 01 0000 [.text] __ZN16AMDCIVCEHWEngine4freeEv 0000000000081532 g 0f SECT 01 0000 [.text] __ZN16AMDCIVCEHWEngine4initEP30AMDRadeonX4000_IAMDHWInterface20_eAMD_HW_ENGINE_TYPE 000000000008157e g 0f SECT 01 0000 [.text] __ZN16AMDCIVCEHWEngine6isIdleEv 00000000000813a0 g 0f SECT 01 0000 [.text] __ZN16AMDCIVCEHWEngine9MetaClassC1Ev 0000000000081460 g 0f SECT 01 0000 [.text] __ZN16AMDCIVCEHWEngine9MetaClassC2Ev 00000000003b71f0 g 0f SECT 08 0000 [.const_data] __ZN16AMDCIVCEHWEngine9metaClassE 00000000000813fc g 0f SECT 01 0000 [.text] __ZN16AMDCIVCEHWEngineC1EPK11OSMetaClass 00000000000814d2 g 0f SECT 01 0000 [.text] __ZN16AMDCIVCEHWEngineC1Ev 00000000000813dc g 0f SECT 01 0000 [.text] __ZN16AMDCIVCEHWEngineC2EPK11OSMetaClass 0000000000081502 g 0f SECT 01 0000 [.text] __ZN16AMDCIVCEHWEngineC2Ev 0000000000081430 g 0f SECT 01 0000 [.text] __ZN16AMDCIVCEHWEngineD0Ev 0000000000081426 g 0f SECT 01 0000 [.text] __ZN16AMDCIVCEHWEngineD1Ev 000000000008141c g 0f SECT 01 0000 [.text] __ZN16AMDCIVCEHWEngineD2Ev 000000000052e4b8 g 0f SECT 0a 0000 [__DATA.__common] __ZN16AMDSIComputeRing10gMetaClassE 00000000003b1d08 g 0f SECT 08 0000 [.const_data] __ZN16AMDSIComputeRing10superClassE 0000000000073b06 g 0f SECT 01 0000 [.text] __ZN16AMDSIComputeRing16getCpRbCntlValueEv 0000000000073b18 g 0f SECT 01 0000 [.text] __ZN16AMDSIComputeRing16registerLocationEv 0000000000073c3a g 0f SECT 01 0000 [.text] __ZN16AMDSIComputeRing26enableReadPointerWriteBackEv 0000000000073cb2 g 0f SECT 01 0000 [.text] __ZN16AMDSIComputeRing27disableReadPointerWriteBackEv 0000000000073d46 g 0f SECT 01 0000 [.text] __ZN16AMDSIComputeRing27programReadAndWritePointersEj 00000000000739e2 g 0f SECT 01 0000 [.text] __ZN16AMDSIComputeRing4initEP30AMDRadeonX4000_IAMDHWInterfacei20_eAMD_HW_ENGINE_TYPEjPKv 0000000000073dde g 0f SECT 01 0000 [.text] __ZN16AMDSIComputeRing5alignEv 0000000000073ce8 g 0f SECT 01 0000 [.text] __ZN16AMDSIComputeRing5resetEv 0000000000073850 g 0f SECT 01 0000 [.text] __ZN16AMDSIComputeRing9MetaClassC1Ev 0000000000073910 g 0f SECT 01 0000 [.text] __ZN16AMDSIComputeRing9MetaClassC2Ev 00000000003b1d00 g 0f SECT 08 0000 [.const_data] __ZN16AMDSIComputeRing9metaClassE 00000000000738ac g 0f SECT 01 0000 [.text] __ZN16AMDSIComputeRingC1EPK11OSMetaClass 0000000000073982 g 0f SECT 01 0000 [.text] __ZN16AMDSIComputeRingC1Ev 000000000007388c g 0f SECT 01 0000 [.text] __ZN16AMDSIComputeRingC2EPK11OSMetaClass 00000000000739b2 g 0f SECT 01 0000 [.text] __ZN16AMDSIComputeRingC2Ev 00000000000738e0 g 0f SECT 01 0000 [.text] __ZN16AMDSIComputeRingD0Ev 00000000000738d6 g 0f SECT 01 0000 [.text] __ZN16AMDSIComputeRingD1Ev 00000000000738cc g 0f SECT 01 0000 [.text] __ZN16AMDSIComputeRingD2Ev 000000000052e058 g 0f SECT 0a 0000 [__DATA.__common] __ZN16AMDSIHWUtilities10gMetaClassE 00000000003aae68 g 0f SECT 08 0000 [.const_data] __ZN16AMDSIHWUtilities10superClassE 0000000000065058 g 0f SECT 01 0000 [.text] __ZN16AMDSIHWUtilities12getUBMEndianEj 0000000000064fa0 g 0f SECT 01 0000 [.text] __ZN16AMDSIHWUtilities16setupUBMChipInfoEP13_UBM_CHIPINFO 0000000000064ed2 g 0f SECT 01 0000 [.text] __ZN16AMDSIHWUtilities21filterUBMFormatForOCLE11_UBM_FORMAT 0000000000064d40 g 0f SECT 01 0000 [.text] __ZN16AMDSIHWUtilities9MetaClassC1Ev 0000000000064e00 g 0f SECT 01 0000 [.text] __ZN16AMDSIHWUtilities9MetaClassC2Ev 00000000003aae60 g 0f SECT 08 0000 [.const_data] __ZN16AMDSIHWUtilities9metaClassE 0000000000064d9c g 0f SECT 01 0000 [.text] __ZN16AMDSIHWUtilitiesC1EPK11OSMetaClass 0000000000064e72 g 0f SECT 01 0000 [.text] __ZN16AMDSIHWUtilitiesC1Ev 0000000000064d7c g 0f SECT 01 0000 [.text] __ZN16AMDSIHWUtilitiesC2EPK11OSMetaClass 0000000000064ea2 g 0f SECT 01 0000 [.text] __ZN16AMDSIHWUtilitiesC2Ev 0000000000064dd0 g 0f SECT 01 0000 [.text] __ZN16AMDSIHWUtilitiesD0Ev 0000000000064dc6 g 0f SECT 01 0000 [.text] __ZN16AMDSIHWUtilitiesD1Ev 0000000000064dbc g 0f SECT 01 0000 [.text] __ZN16AMDSIHWUtilitiesD2Ev 000000000052e3f0 g 0f SECT 0a 0000 [__DATA.__common] __ZN16AMDSIUVDHWEngine10gMetaClassE 00000000003b0aa8 g 0f SECT 08 0000 [.const_data] __ZN16AMDSIUVDHWEngine10superClassE 000000000007170e g 0f SECT 01 0000 [.text] __ZN16AMDSIUVDHWEngine12initHardwareEv 0000000000071842 g 0f SECT 01 0000 [.text] __ZN16AMDSIUVDHWEngine14commitUVDFWMsgEP12_SML_UVD_MSGyy 000000000007166c g 0f SECT 01 0000 [.text] __ZN16AMDSIUVDHWEngine14getFwvFunctionEv 00000000000715f4 g 0f SECT 01 0000 [.text] __ZN16AMDSIUVDHWEngine15allocateHWRingsEv 00000000000717aa g 0f SECT 01 0000 [.text] __ZN16AMDSIUVDHWEngine15releaseHardwareEv 0000000000071630 g 0f SECT 01 0000 [.text] __ZN16AMDSIUVDHWEngine18allocateHWChannelsEv 0000000000071a36 g 0f SECT 01 0000 [.text] __ZN16AMDSIUVDHWEngine19dumpEngineHangStateEb 00000000000719ea g 0f SECT 01 0000 [.text] __ZN16AMDSIUVDHWEngine22saveNONCACHE_SIZE1_valEv 000000000007167a g 0f SECT 01 0000 [.text] __ZN16AMDSIUVDHWEngine23startFirmwareValidationEPvP15_IRI_CALL_INPUTP16_IRI_CALL_OUTPUT 0000000000071a12 g 0f SECT 01 0000 [.text] __ZN16AMDSIUVDHWEngine25restoreNONCACHE_SIZE1_valEv 0000000000071512 g 0f SECT 01 0000 [.text] __ZN16AMDSIUVDHWEngine4initEP30AMDRadeonX4000_IAMDHWInterface20_eAMD_HW_ENGINE_TYPE 00000000000715ba g 0f SECT 01 0000 [.text] __ZN16AMDSIUVDHWEngine6isIdleEv 0000000000071380 g 0f SECT 01 0000 [.text] __ZN16AMDSIUVDHWEngine9MetaClassC1Ev 0000000000071440 g 0f SECT 01 0000 [.text] __ZN16AMDSIUVDHWEngine9MetaClassC2Ev 00000000003b0aa0 g 0f SECT 08 0000 [.const_data] __ZN16AMDSIUVDHWEngine9metaClassE 00000000000713dc g 0f SECT 01 0000 [.text] __ZN16AMDSIUVDHWEngineC1EPK11OSMetaClass 00000000000714b2 g 0f SECT 01 0000 [.text] __ZN16AMDSIUVDHWEngineC1Ev 00000000000713bc g 0f SECT 01 0000 [.text] __ZN16AMDSIUVDHWEngineC2EPK11OSMetaClass 00000000000714e2 g 0f SECT 01 0000 [.text] __ZN16AMDSIUVDHWEngineC2Ev 0000000000071410 g 0f SECT 01 0000 [.text] __ZN16AMDSIUVDHWEngineD0Ev 0000000000071406 g 0f SECT 01 0000 [.text] __ZN16AMDSIUVDHWEngineD1Ev 00000000000713fc g 0f SECT 01 0000 [.text] __ZN16AMDSIUVDHWEngineD2Ev 000000000052e300 g 0f SECT 0a 0000 [__DATA.__common] __ZN16AMDSIVCEHWEngine10gMetaClassE 00000000003af538 g 0f SECT 08 0000 [.const_data] __ZN16AMDSIVCEHWEngine10superClassE 000000000006f5ae g 0f SECT 01 0000 [.text] __ZN16AMDSIVCEHWEngine12initHardwareEv 000000000006f77a g 0f SECT 01 0000 [.text] __ZN16AMDSIVCEHWEngine15allocateHWRingsEv 000000000006f61a g 0f SECT 01 0000 [.text] __ZN16AMDSIVCEHWEngine15releaseHardwareEv 000000000006f6e4 g 0f SECT 01 0000 [.text] __ZN16AMDSIVCEHWEngine17initHardwareRingsEv 000000000006f7e6 g 0f SECT 01 0000 [.text] __ZN16AMDSIVCEHWEngine18allocateHWChannelsEv 000000000006f866 g 0f SECT 01 0000 [.text] __ZN16AMDSIVCEHWEngine18configCacheWindowsEv 000000000006fa54 g 0f SECT 01 0000 [.text] __ZN16AMDSIVCEHWEngine19dumpEngineHangStateEb 000000000006f750 g 0f SECT 01 0000 [.text] __ZN16AMDSIVCEHWEngine20releaseHardwareRingsEv 000000000006f59c g 0f SECT 01 0000 [.text] __ZN16AMDSIVCEHWEngine4freeEv 000000000006f512 g 0f SECT 01 0000 [.text] __ZN16AMDSIVCEHWEngine4initEP30AMDRadeonX4000_IAMDHWInterface20_eAMD_HW_ENGINE_TYPE 000000000006f55e g 0f SECT 01 0000 [.text] __ZN16AMDSIVCEHWEngine6isIdleEv 000000000006f380 g 0f SECT 01 0000 [.text] __ZN16AMDSIVCEHWEngine9MetaClassC1Ev 000000000006f440 g 0f SECT 01 0000 [.text] __ZN16AMDSIVCEHWEngine9MetaClassC2Ev 00000000003af530 g 0f SECT 08 0000 [.const_data] __ZN16AMDSIVCEHWEngine9metaClassE 000000000006f3dc g 0f SECT 01 0000 [.text] __ZN16AMDSIVCEHWEngineC1EPK11OSMetaClass 000000000006f4b2 g 0f SECT 01 0000 [.text] __ZN16AMDSIVCEHWEngineC1Ev 000000000006f3bc g 0f SECT 01 0000 [.text] __ZN16AMDSIVCEHWEngineC2EPK11OSMetaClass 000000000006f4e2 g 0f SECT 01 0000 [.text] __ZN16AMDSIVCEHWEngineC2Ev 000000000006f410 g 0f SECT 01 0000 [.text] __ZN16AMDSIVCEHWEngineD0Ev 000000000006f406 g 0f SECT 01 0000 [.text] __ZN16AMDSIVCEHWEngineD1Ev 000000000006f3fc g 0f SECT 01 0000 [.text] __ZN16AMDSIVCEHWEngineD2Ev 000000000052e940 g 0f SECT 0a 0000 [__DATA.__common] __ZN16AMDTongaHardware10gMetaClassE 00000000003b91d8 g 0f SECT 08 0000 [.const_data] __ZN16AMDTongaHardware10superClassE 0000000000086d48 g 0f SECT 01 0000 [.text] __ZN16AMDTongaHardware19getATIChipConfigBitEv 0000000000086d24 g 0f SECT 01 0000 [.text] __ZN16AMDTongaHardware23readChipRevFromRegisterEv 0000000000086e14 g 0f SECT 01 0000 [.text] __ZN16AMDTongaHardware32setupAndInitializeHWCapabilitiesEv 0000000000086d12 g 0f SECT 01 0000 [.text] __ZN16AMDTongaHardware4initEP11IOPCIDeviceP28AMDRadeonX4000_IAMDHWHandlerRjjP16_GART_PARAMETERSP14_FB_PARAMETERS 0000000000086d54 g 0f SECT 01 0000 [.text] __ZN16AMDTongaHardware7powerUpEv 0000000000086b80 g 0f SECT 01 0000 [.text] __ZN16AMDTongaHardware9MetaClassC1Ev 0000000000086c40 g 0f SECT 01 0000 [.text] __ZN16AMDTongaHardware9MetaClassC2Ev 00000000003b91d0 g 0f SECT 08 0000 [.const_data] __ZN16AMDTongaHardware9metaClassE 0000000000086bdc g 0f SECT 01 0000 [.text] __ZN16AMDTongaHardwareC1EPK11OSMetaClass 0000000000086cb2 g 0f SECT 01 0000 [.text] __ZN16AMDTongaHardwareC1Ev 0000000000086bbc g 0f SECT 01 0000 [.text] __ZN16AMDTongaHardwareC2EPK11OSMetaClass 0000000000086ce2 g 0f SECT 01 0000 [.text] __ZN16AMDTongaHardwareC2Ev 0000000000086c10 g 0f SECT 01 0000 [.text] __ZN16AMDTongaHardwareD0Ev 0000000000086c06 g 0f SECT 01 0000 [.text] __ZN16AMDTongaHardwareD1Ev 0000000000086bfc g 0f SECT 01 0000 [.text] __ZN16AMDTongaHardwareD2Ev 000000000052eaf8 g 0f SECT 0a 0000 [__DATA.__common] __ZN16AMDVIComputeRing10gMetaClassE 00000000003bb9a8 g 0f SECT 08 0000 [.const_data] __ZN16AMDVIComputeRing10superClassE 000000000008dbb8 g 0f SECT 01 0000 [.text] __ZN16AMDVIComputeRing16registerLocationEv 000000000008db78 g 0f SECT 01 0000 [.text] __ZN16AMDVIComputeRing17allocateResourcesEv 000000000008dbc0 g 0f SECT 01 0000 [.text] __ZN16AMDVIComputeRing26enableReadPointerWriteBackEv 000000000008dbc6 g 0f SECT 01 0000 [.text] __ZN16AMDVIComputeRing27disableReadPointerWriteBackEv 000000000008dbfe g 0f SECT 01 0000 [.text] __ZN16AMDVIComputeRing27programReadAndWritePointersEj 000000000008dad2 g 0f SECT 01 0000 [.text] __ZN16AMDVIComputeRing4initEP30AMDRadeonX4000_IAMDHWInterfacei20_eAMD_HW_ENGINE_TYPEjPKv 000000000008dd32 g 0f SECT 01 0000 [.text] __ZN16AMDVIComputeRing5alignEv 000000000008dbcc g 0f SECT 01 0000 [.text] __ZN16AMDVIComputeRing5resetEv 000000000008d940 g 0f SECT 01 0000 [.text] __ZN16AMDVIComputeRing9MetaClassC1Ev 000000000008da00 g 0f SECT 01 0000 [.text] __ZN16AMDVIComputeRing9MetaClassC2Ev 00000000003bb9a0 g 0f SECT 08 0000 [.const_data] __ZN16AMDVIComputeRing9metaClassE 000000000008dd62 g 0f SECT 01 0000 [.text] __ZN16AMDVIComputeRing9writeTailEv 000000000008d99c g 0f SECT 01 0000 [.text] __ZN16AMDVIComputeRingC1EPK11OSMetaClass 000000000008da72 g 0f SECT 01 0000 [.text] __ZN16AMDVIComputeRingC1Ev 000000000008d97c g 0f SECT 01 0000 [.text] __ZN16AMDVIComputeRingC2EPK11OSMetaClass 000000000008daa2 g 0f SECT 01 0000 [.text] __ZN16AMDVIComputeRingC2Ev 000000000008d9d0 g 0f SECT 01 0000 [.text] __ZN16AMDVIComputeRingD0Ev 000000000008d9c6 g 0f SECT 01 0000 [.text] __ZN16AMDVIComputeRingD1Ev 000000000008d9bc g 0f SECT 01 0000 [.text] __ZN16AMDVIComputeRingD2Ev 000000000052ea30 g 0f SECT 0a 0000 [__DATA.__common] __ZN16AMDVIHWUtilities10gMetaClassE 00000000003ba9b8 g 0f SECT 08 0000 [.const_data] __ZN16AMDVIHWUtilities10superClassE 000000000008b65e g 0f SECT 01 0000 [.text] __ZN16AMDVIHWUtilities12getUBMEndianEj 000000000008b5c2 g 0f SECT 01 0000 [.text] __ZN16AMDVIHWUtilities16setupUBMChipInfoEP13_UBM_CHIPINFO 000000000008b67c g 0f SECT 01 0000 [.text] __ZN16AMDVIHWUtilities21filterUBMFormatForOCLE11_UBM_FORMAT 000000000008b430 g 0f SECT 01 0000 [.text] __ZN16AMDVIHWUtilities9MetaClassC1Ev 000000000008b4f0 g 0f SECT 01 0000 [.text] __ZN16AMDVIHWUtilities9MetaClassC2Ev 00000000003ba9b0 g 0f SECT 08 0000 [.const_data] __ZN16AMDVIHWUtilities9metaClassE 000000000008b48c g 0f SECT 01 0000 [.text] __ZN16AMDVIHWUtilitiesC1EPK11OSMetaClass 000000000008b562 g 0f SECT 01 0000 [.text] __ZN16AMDVIHWUtilitiesC1Ev 000000000008b46c g 0f SECT 01 0000 [.text] __ZN16AMDVIHWUtilitiesC2EPK11OSMetaClass 000000000008b592 g 0f SECT 01 0000 [.text] __ZN16AMDVIHWUtilitiesC2Ev 000000000008b4c0 g 0f SECT 01 0000 [.text] __ZN16AMDVIHWUtilitiesD0Ev 000000000008b4b6 g 0f SECT 01 0000 [.text] __ZN16AMDVIHWUtilitiesD1Ev 000000000008b4ac g 0f SECT 01 0000 [.text] __ZN16AMDVIHWUtilitiesD2Ev 000000000052ebe8 g 0f SECT 0a 0000 [__DATA.__common] __ZN16AMDVISAMURBIRing10gMetaClassE 00000000003bcee8 g 0f SECT 08 0000 [.const_data] __ZN16AMDVISAMURBIRing10superClassE 00000000000929f0 g 0f SECT 01 0000 [.text] __ZN16AMDVISAMURBIRing14getReadPointerEv 0000000000092a10 g 0f SECT 01 0000 [.text] __ZN16AMDVISAMURBIRing15getWritePointerEv 000000000009296e g 0f SECT 01 0000 [.text] __ZN16AMDVISAMURBIRing27programReadAndWritePointersEj 0000000000092904 g 0f SECT 01 0000 [.text] __ZN16AMDVISAMURBIRing4freeEv 00000000000928f2 g 0f SECT 01 0000 [.text] __ZN16AMDVISAMURBIRing4initEP30AMDRadeonX4000_IAMDHWInterfacei20_eAMD_HW_ENGINE_TYPEjPKv 0000000000092916 g 0f SECT 01 0000 [.text] __ZN16AMDVISAMURBIRing5resetEv 0000000000092760 g 0f SECT 01 0000 [.text] __ZN16AMDVISAMURBIRing9MetaClassC1Ev 0000000000092820 g 0f SECT 01 0000 [.text] __ZN16AMDVISAMURBIRing9MetaClassC2Ev 00000000003bcee0 g 0f SECT 08 0000 [.const_data] __ZN16AMDVISAMURBIRing9metaClassE 0000000000092a30 g 0f SECT 01 0000 [.text] __ZN16AMDVISAMURBIRing9writeTailEv 00000000000927bc g 0f SECT 01 0000 [.text] __ZN16AMDVISAMURBIRingC1EPK11OSMetaClass 0000000000092892 g 0f SECT 01 0000 [.text] __ZN16AMDVISAMURBIRingC1Ev 000000000009279c g 0f SECT 01 0000 [.text] __ZN16AMDVISAMURBIRingC2EPK11OSMetaClass 00000000000928c2 g 0f SECT 01 0000 [.text] __ZN16AMDVISAMURBIRingC2Ev 00000000000927f0 g 0f SECT 01 0000 [.text] __ZN16AMDVISAMURBIRingD0Ev 00000000000927e6 g 0f SECT 01 0000 [.text] __ZN16AMDVISAMURBIRingD1Ev 00000000000927dc g 0f SECT 01 0000 [.text] __ZN16AMDVISAMURBIRingD2Ev 000000000052ea58 g 0f SECT 0a 0000 [__DATA.__common] __ZN16AMDVIsDMAChannel10gMetaClassE 00000000003bac28 g 0f SECT 08 0000 [.const_data] __ZN16AMDVIsDMAChannel10superClassE 000000000008c23e g 0f SECT 01 0000 [.text] __ZN16AMDVIsDMAChannel18submitVMInvalidateEjyj 000000000008c46e g 0f SECT 01 0000 [.text] __ZN16AMDVIsDMAChannel20initializeDmaPktInfoEv 000000000008bd62 g 0f SECT 01 0000 [.text] __ZN16AMDVIsDMAChannel21writeProfilingCommandEPjyjb 000000000008c0de g 0f SECT 01 0000 [.text] __ZN16AMDVIsDMAChannel21writeSRBMWriteCommandEPjjjj 000000000008c44a g 0f SECT 01 0000 [.text] __ZN16AMDVIsDMAChannel22timeStampInterruptTypeEv 000000000008c026 g 0f SECT 01 0000 [.text] __ZN16AMDVIsDMAChannel22writeCopyLinearCommandEPjyyj 000000000008c16e g 0f SECT 01 0000 [.text] __ZN16AMDVIsDMAChannel22writePollRegMemCommandEPjbyjjjjj 000000000008be5e g 0f SECT 01 0000 [.text] __ZN16AMDVIsDMAChannel23writeWriteLinearCommandEPjyjS0_ 000000000008bf4a g 0f SECT 01 0000 [.text] __ZN16AMDVIsDMAChannel23writeWritePTEPDECommandEPjyjyyy 000000000008bdb8 g 0f SECT 01 0000 [.text] __ZN16AMDVIsDMAChannel24writeConstantFillCommandEPjyjj 000000000008b9e6 g 0f SECT 01 0000 [.text] __ZN16AMDVIsDMAChannel27commitIndirectCommandBufferEP30AMD_SUBMIT_COMMAND_BUFFER_INFO 000000000008bbd2 g 0f SECT 01 0000 [.text] __ZN16AMDVIsDMAChannel27initializeVMInvalidateFrameEv 000000000008c40e g 0f SECT 01 0000 [.text] __ZN16AMDVIsDMAChannel33releaseIndirectCommandBufferFrameEv 000000000008c386 g 0f SECT 01 0000 [.text] __ZN16AMDVIsDMAChannel36initializeIndirectCommandBufferFrameEv 000000000008b99a g 0f SECT 01 0000 [.text] __ZN16AMDVIsDMAChannel4freeEv 000000000008b942 g 0f SECT 01 0000 [.text] __ZN16AMDVIsDMAChannel4initEiP30AMDRadeonX4000_IAMDHWInterfaceP27AMDRadeonX4000_IAMDHWEngineP25AMDRadeonX4000_IAMDHWRingPKc 000000000008b7b0 g 0f SECT 01 0000 [.text] __ZN16AMDVIsDMAChannel9MetaClassC1Ev 000000000008b870 g 0f SECT 01 0000 [.text] __ZN16AMDVIsDMAChannel9MetaClassC2Ev 00000000003bac20 g 0f SECT 08 0000 [.const_data] __ZN16AMDVIsDMAChannel9metaClassE 000000000008b80c g 0f SECT 01 0000 [.text] __ZN16AMDVIsDMAChannelC1EPK11OSMetaClass 000000000008b8e2 g 0f SECT 01 0000 [.text] __ZN16AMDVIsDMAChannelC1Ev 000000000008b7ec g 0f SECT 01 0000 [.text] __ZN16AMDVIsDMAChannelC2EPK11OSMetaClass 000000000008b912 g 0f SECT 01 0000 [.text] __ZN16AMDVIsDMAChannelC2Ev 000000000008b840 g 0f SECT 01 0000 [.text] __ZN16AMDVIsDMAChannelD0Ev 000000000008b836 g 0f SECT 01 0000 [.text] __ZN16AMDVIsDMAChannelD1Ev 000000000008b82c g 0f SECT 01 0000 [.text] __ZN16AMDVIsDMAChannelD2Ev 000000000052e148 g 0f SECT 0a 0000 [__DATA.__common] __ZN16AMDVerdeHardware10gMetaClassE 00000000003acc48 g 0f SECT 08 0000 [.const_data] __ZN16AMDVerdeHardware10superClassE 000000000006a9b4 g 0f SECT 01 0000 [.text] __ZN16AMDVerdeHardware11allocateSMLEv 000000000006aac4 g 0f SECT 01 0000 [.text] __ZN16AMDVerdeHardware17allocatePM4EngineEv 000000000006a9a8 g 0f SECT 01 0000 [.text] __ZN16AMDVerdeHardware19getATIChipConfigBitEv 000000000006a984 g 0f SECT 01 0000 [.text] __ZN16AMDVerdeHardware23readChipRevFromRegisterEv 000000000006aa9a g 0f SECT 01 0000 [.text] __ZN16AMDVerdeHardware32setupAndInitializeHWCapabilitiesEv 000000000006a972 g 0f SECT 01 0000 [.text] __ZN16AMDVerdeHardware4initEP11IOPCIDeviceP28AMDRadeonX4000_IAMDHWHandlerRjjP16_GART_PARAMETERSP14_FB_PARAMETERS 000000000006a9da g 0f SECT 01 0000 [.text] __ZN16AMDVerdeHardware7powerUpEv 000000000006a7e0 g 0f SECT 01 0000 [.text] __ZN16AMDVerdeHardware9MetaClassC1Ev 000000000006a8a0 g 0f SECT 01 0000 [.text] __ZN16AMDVerdeHardware9MetaClassC2Ev 00000000003acc40 g 0f SECT 08 0000 [.const_data] __ZN16AMDVerdeHardware9metaClassE 000000000006a83c g 0f SECT 01 0000 [.text] __ZN16AMDVerdeHardwareC1EPK11OSMetaClass 000000000006a912 g 0f SECT 01 0000 [.text] __ZN16AMDVerdeHardwareC1Ev 000000000006a81c g 0f SECT 01 0000 [.text] __ZN16AMDVerdeHardwareC2EPK11OSMetaClass 000000000006a942 g 0f SECT 01 0000 [.text] __ZN16AMDVerdeHardwareC2Ev 000000000006a870 g 0f SECT 01 0000 [.text] __ZN16AMDVerdeHardwareD0Ev 000000000006a866 g 0f SECT 01 0000 [.text] __ZN16AMDVerdeHardwareD1Ev 000000000006a85c g 0f SECT 01 0000 [.text] __ZN16AMDVerdeHardwareD2Ev 00000000000bb57c g 0f SECT 01 0000 [.text] __ZN16SiBltPixelShader14SetShaderInputEPK21SiBltPixelShaderInput 00000000000bb680 g 0f SECT 01 0000 [.text] __ZN16SiBltPixelShader7CpuLoadEPv13LARGE_INTEGERPh 00000000000bb7f6 g 0f SECT 01 0000 [.text] __ZN16SiBltPixelShader7GpuLoadEP9BltDevicePv13LARGE_INTEGER 000000000052e5a8 g 0f SECT 0a 0000 [__DATA.__common] __ZN17AMDCICommandsRing10gMetaClassE 00000000003b3d28 g 0f SECT 08 0000 [.const_data] __ZN17AMDCICommandsRing10superClassE 0000000000079902 g 0f SECT 01 0000 [.text] __ZN17AMDCICommandsRing16registerLocationEv 000000000007992a g 0f SECT 01 0000 [.text] __ZN17AMDCICommandsRing26enableReadPointerWriteBackEv 0000000000079930 g 0f SECT 01 0000 [.text] __ZN17AMDCICommandsRing27disableReadPointerWriteBackEv 0000000000079994 g 0f SECT 01 0000 [.text] __ZN17AMDCICommandsRing27programReadAndWritePointersEj 00000000000798f0 g 0f SECT 01 0000 [.text] __ZN17AMDCICommandsRing4freeEv 0000000000079852 g 0f SECT 01 0000 [.text] __ZN17AMDCICommandsRing4initEP30AMDRadeonX4000_IAMDHWInterfacei20_eAMD_HW_ENGINE_TYPEjPKv 0000000000079a1e g 0f SECT 01 0000 [.text] __ZN17AMDCICommandsRing5alignEv 0000000000079936 g 0f SECT 01 0000 [.text] __ZN17AMDCICommandsRing5resetEv 00000000000796c0 g 0f SECT 01 0000 [.text] __ZN17AMDCICommandsRing9MetaClassC1Ev 0000000000079780 g 0f SECT 01 0000 [.text] __ZN17AMDCICommandsRing9MetaClassC2Ev 00000000003b3d20 g 0f SECT 08 0000 [.const_data] __ZN17AMDCICommandsRing9metaClassE 000000000007971c g 0f SECT 01 0000 [.text] __ZN17AMDCICommandsRingC1EPK11OSMetaClass 00000000000797f2 g 0f SECT 01 0000 [.text] __ZN17AMDCICommandsRingC1Ev 00000000000796fc g 0f SECT 01 0000 [.text] __ZN17AMDCICommandsRingC2EPK11OSMetaClass 0000000000079822 g 0f SECT 01 0000 [.text] __ZN17AMDCICommandsRingC2Ev 0000000000079750 g 0f SECT 01 0000 [.text] __ZN17AMDCICommandsRingD0Ev 0000000000079746 g 0f SECT 01 0000 [.text] __ZN17AMDCICommandsRingD1Ev 000000000007973c g 0f SECT 01 0000 [.text] __ZN17AMDCICommandsRingD2Ev 000000000052e558 g 0f SECT 0a 0000 [__DATA.__common] __ZN17AMDHawaiiHardware10gMetaClassE 00000000003b3278 g 0f SECT 08 0000 [.const_data] __ZN17AMDHawaiiHardware10superClassE 0000000000077b80 g 0f SECT 01 0000 [.text] __ZN17AMDHawaiiHardware19getATIChipConfigBitEv 0000000000077b64 g 0f SECT 01 0000 [.text] __ZN17AMDHawaiiHardware23readChipRevFromRegisterEv 0000000000077c4c g 0f SECT 01 0000 [.text] __ZN17AMDHawaiiHardware32setupAndInitializeHWCapabilitiesEv 0000000000077b52 g 0f SECT 01 0000 [.text] __ZN17AMDHawaiiHardware4initEP11IOPCIDeviceP28AMDRadeonX4000_IAMDHWHandlerRjjP16_GART_PARAMETERSP14_FB_PARAMETERS 0000000000077b8c g 0f SECT 01 0000 [.text] __ZN17AMDHawaiiHardware7powerUpEv 00000000000779c0 g 0f SECT 01 0000 [.text] __ZN17AMDHawaiiHardware9MetaClassC1Ev 0000000000077a80 g 0f SECT 01 0000 [.text] __ZN17AMDHawaiiHardware9MetaClassC2Ev 00000000003b3270 g 0f SECT 08 0000 [.const_data] __ZN17AMDHawaiiHardware9metaClassE 0000000000077a1c g 0f SECT 01 0000 [.text] __ZN17AMDHawaiiHardwareC1EPK11OSMetaClass 0000000000077af2 g 0f SECT 01 0000 [.text] __ZN17AMDHawaiiHardwareC1Ev 00000000000779fc g 0f SECT 01 0000 [.text] __ZN17AMDHawaiiHardwareC2EPK11OSMetaClass 0000000000077b22 g 0f SECT 01 0000 [.text] __ZN17AMDHawaiiHardwareC2Ev 0000000000077a50 g 0f SECT 01 0000 [.text] __ZN17AMDHawaiiHardwareD0Ev 0000000000077a46 g 0f SECT 01 0000 [.text] __ZN17AMDHawaiiHardwareD1Ev 0000000000077a3c g 0f SECT 01 0000 [.text] __ZN17AMDHawaiiHardwareD2Ev 000000000052e260 g 0f SECT 0a 0000 [__DATA.__common] __ZN17AMDSICommandsRing10gMetaClassE 00000000003ae7c8 g 0f SECT 08 0000 [.const_data] __ZN17AMDSICommandsRing10superClassE 000000000006d152 g 0f SECT 01 0000 [.text] __ZN17AMDSICommandsRing16getCpRbCntlValueEv 000000000006d164 g 0f SECT 01 0000 [.text] __ZN17AMDSICommandsRing16registerLocationEv 000000000006d26a g 0f SECT 01 0000 [.text] __ZN17AMDSICommandsRing26enableReadPointerWriteBackEv 000000000006d2dc g 0f SECT 01 0000 [.text] __ZN17AMDSICommandsRing27disableReadPointerWriteBackEv 000000000006d366 g 0f SECT 01 0000 [.text] __ZN17AMDSICommandsRing27programReadAndWritePointersEj 000000000006d140 g 0f SECT 01 0000 [.text] __ZN17AMDSICommandsRing4freeEv 000000000006d0a2 g 0f SECT 01 0000 [.text] __ZN17AMDSICommandsRing4initEP30AMDRadeonX4000_IAMDHWInterfacei20_eAMD_HW_ENGINE_TYPEjPKv 000000000006d3f0 g 0f SECT 01 0000 [.text] __ZN17AMDSICommandsRing5alignEv 000000000006d308 g 0f SECT 01 0000 [.text] __ZN17AMDSICommandsRing5resetEv 000000000006cf10 g 0f SECT 01 0000 [.text] __ZN17AMDSICommandsRing9MetaClassC1Ev 000000000006cfd0 g 0f SECT 01 0000 [.text] __ZN17AMDSICommandsRing9MetaClassC2Ev 00000000003ae7c0 g 0f SECT 08 0000 [.const_data] __ZN17AMDSICommandsRing9metaClassE 000000000006cf6c g 0f SECT 01 0000 [.text] __ZN17AMDSICommandsRingC1EPK11OSMetaClass 000000000006d042 g 0f SECT 01 0000 [.text] __ZN17AMDSICommandsRingC1Ev 000000000006cf4c g 0f SECT 01 0000 [.text] __ZN17AMDSICommandsRingC2EPK11OSMetaClass 000000000006d072 g 0f SECT 01 0000 [.text] __ZN17AMDSICommandsRingC2Ev 000000000006cfa0 g 0f SECT 01 0000 [.text] __ZN17AMDSICommandsRingD0Ev 000000000006cf96 g 0f SECT 01 0000 [.text] __ZN17AMDSICommandsRingD1Ev 000000000006cf8c g 0f SECT 01 0000 [.text] __ZN17AMDSICommandsRingD2Ev 000000000052d680 g 0f SECT 0a 0000 [__DATA.__common] __ZN17AMDSIVideoContext10gMetaClassE 00000000003981f8 g 0f SECT 08 0000 [.const_data] __ZN17AMDSIVideoContext10superClassE 000000000002ac30 g 0f SECT 01 0000 [.text] __ZN17AMDSIVideoContext9MetaClassC1Ev 000000000002acf0 g 0f SECT 01 0000 [.text] __ZN17AMDSIVideoContext9MetaClassC2Ev 00000000003981f0 g 0f SECT 08 0000 [.const_data] __ZN17AMDSIVideoContext9metaClassE 000000000002ac8c g 0f SECT 01 0000 [.text] __ZN17AMDSIVideoContextC1EPK11OSMetaClass 000000000002ad62 g 0f SECT 01 0000 [.text] __ZN17AMDSIVideoContextC1Ev 000000000002ac6c g 0f SECT 01 0000 [.text] __ZN17AMDSIVideoContextC2EPK11OSMetaClass 000000000002ad92 g 0f SECT 01 0000 [.text] __ZN17AMDSIVideoContextC2Ev 000000000002acc0 g 0f SECT 01 0000 [.text] __ZN17AMDSIVideoContextD0Ev 000000000002acb6 g 0f SECT 01 0000 [.text] __ZN17AMDSIVideoContextD1Ev 000000000002acac g 0f SECT 01 0000 [.text] __ZN17AMDSIVideoContextD2Ev 000000000052e0f8 g 0f SECT 0a 0000 [__DATA.__common] __ZN17AMDTahitiHardware10gMetaClassE 00000000003abde8 g 0f SECT 08 0000 [.const_data] __ZN17AMDTahitiHardware10superClassE 0000000000069d90 g 0f SECT 01 0000 [.text] __ZN17AMDTahitiHardware11allocateSMLEv 0000000000069ea0 g 0f SECT 01 0000 [.text] __ZN17AMDTahitiHardware17allocatePM4EngineEv 0000000000069d84 g 0f SECT 01 0000 [.text] __ZN17AMDTahitiHardware19getATIChipConfigBitEv 0000000000069d64 g 0f SECT 01 0000 [.text] __ZN17AMDTahitiHardware23readChipRevFromRegisterEv 0000000000069e76 g 0f SECT 01 0000 [.text] __ZN17AMDTahitiHardware32setupAndInitializeHWCapabilitiesEv 0000000000069d52 g 0f SECT 01 0000 [.text] __ZN17AMDTahitiHardware4initEP11IOPCIDeviceP28AMDRadeonX4000_IAMDHWHandlerRjjP16_GART_PARAMETERSP14_FB_PARAMETERS 0000000000069db6 g 0f SECT 01 0000 [.text] __ZN17AMDTahitiHardware7powerUpEv 0000000000069bc0 g 0f SECT 01 0000 [.text] __ZN17AMDTahitiHardware9MetaClassC1Ev 0000000000069c80 g 0f SECT 01 0000 [.text] __ZN17AMDTahitiHardware9MetaClassC2Ev 00000000003abde0 g 0f SECT 08 0000 [.const_data] __ZN17AMDTahitiHardware9metaClassE 0000000000069c1c g 0f SECT 01 0000 [.text] __ZN17AMDTahitiHardwareC1EPK11OSMetaClass 0000000000069cf2 g 0f SECT 01 0000 [.text] __ZN17AMDTahitiHardwareC1Ev 0000000000069bfc g 0f SECT 01 0000 [.text] __ZN17AMDTahitiHardwareC2EPK11OSMetaClass 0000000000069d22 g 0f SECT 01 0000 [.text] __ZN17AMDTahitiHardwareC2Ev 0000000000069c50 g 0f SECT 01 0000 [.text] __ZN17AMDTahitiHardwareD0Ev 0000000000069c46 g 0f SECT 01 0000 [.text] __ZN17AMDTahitiHardwareD1Ev 0000000000069c3c g 0f SECT 01 0000 [.text] __ZN17AMDTahitiHardwareD2Ev 000000000052ead0 g 0f SECT 0a 0000 [__DATA.__common] __ZN17AMDVICommandsRing10gMetaClassE 00000000003bb688 g 0f SECT 08 0000 [.const_data] __ZN17AMDVICommandsRing10superClassE 000000000008d6b2 g 0f SECT 01 0000 [.text] __ZN17AMDVICommandsRing16registerLocationEv 000000000008d6da g 0f SECT 01 0000 [.text] __ZN17AMDVICommandsRing26enableReadPointerWriteBackEv 000000000008d6e0 g 0f SECT 01 0000 [.text] __ZN17AMDVICommandsRing27disableReadPointerWriteBackEv 000000000008d744 g 0f SECT 01 0000 [.text] __ZN17AMDVICommandsRing27programReadAndWritePointersEj 000000000008d6a0 g 0f SECT 01 0000 [.text] __ZN17AMDVICommandsRing4freeEv 000000000008d602 g 0f SECT 01 0000 [.text] __ZN17AMDVICommandsRing4initEP30AMDRadeonX4000_IAMDHWInterfacei20_eAMD_HW_ENGINE_TYPEjPKv 000000000008d7ce g 0f SECT 01 0000 [.text] __ZN17AMDVICommandsRing5alignEv 000000000008d6e6 g 0f SECT 01 0000 [.text] __ZN17AMDVICommandsRing5resetEv 000000000008d470 g 0f SECT 01 0000 [.text] __ZN17AMDVICommandsRing9MetaClassC1Ev 000000000008d530 g 0f SECT 01 0000 [.text] __ZN17AMDVICommandsRing9MetaClassC2Ev 00000000003bb680 g 0f SECT 08 0000 [.const_data] __ZN17AMDVICommandsRing9metaClassE 000000000008d4cc g 0f SECT 01 0000 [.text] __ZN17AMDVICommandsRingC1EPK11OSMetaClass 000000000008d5a2 g 0f SECT 01 0000 [.text] __ZN17AMDVICommandsRingC1Ev 000000000008d4ac g 0f SECT 01 0000 [.text] __ZN17AMDVICommandsRingC2EPK11OSMetaClass 000000000008d5d2 g 0f SECT 01 0000 [.text] __ZN17AMDVICommandsRingC2Ev 000000000008d500 g 0f SECT 01 0000 [.text] __ZN17AMDVICommandsRingD0Ev 000000000008d4f6 g 0f SECT 01 0000 [.text] __ZN17AMDVICommandsRingD1Ev 000000000008d4ec g 0f SECT 01 0000 [.text] __ZN17AMDVICommandsRingD2Ev 000000000052e210 g 0f SECT 0a 0000 [__DATA.__common] __ZN17AMDVerdePM4Engine10gMetaClassE 00000000003ae078 g 0f SECT 08 0000 [.const_data] __ZN17AMDVerdePM4Engine10superClassE 000000000006c322 g 0f SECT 01 0000 [.text] __ZN17AMDVerdePM4Engine4initEP30AMDRadeonX4000_IAMDHWInterface20_eAMD_HW_ENGINE_TYPE 000000000006c190 g 0f SECT 01 0000 [.text] __ZN17AMDVerdePM4Engine9MetaClassC1Ev 000000000006c250 g 0f SECT 01 0000 [.text] __ZN17AMDVerdePM4Engine9MetaClassC2Ev 00000000003ae070 g 0f SECT 08 0000 [.const_data] __ZN17AMDVerdePM4Engine9metaClassE 000000000006c1ec g 0f SECT 01 0000 [.text] __ZN17AMDVerdePM4EngineC1EPK11OSMetaClass 000000000006c2c2 g 0f SECT 01 0000 [.text] __ZN17AMDVerdePM4EngineC1Ev 000000000006c1cc g 0f SECT 01 0000 [.text] __ZN17AMDVerdePM4EngineC2EPK11OSMetaClass 000000000006c2f2 g 0f SECT 01 0000 [.text] __ZN17AMDVerdePM4EngineC2Ev 000000000006c220 g 0f SECT 01 0000 [.text] __ZN17AMDVerdePM4EngineD0Ev 000000000006c216 g 0f SECT 01 0000 [.text] __ZN17AMDVerdePM4EngineD1Ev 000000000006c20c g 0f SECT 01 0000 [.text] __ZN17AMDVerdePM4EngineD2Ev 00000000000ca2c0 g 0f SECT 01 0000 [.text] __ZN17SiBltVertexShader14SetShaderInputEPK22SiBltVertexShaderInput 00000000000ca320 g 0f SECT 01 0000 [.text] __ZN17SiBltVertexShader20GetImmVbRsrcRegCountEj 00000000000ca2e8 g 0f SECT 01 0000 [.text] __ZN17SiBltVertexShader20GetImmVbRsrcStartRegEj 00000000000caccc g 0f SECT 01 0000 [.text] __ZN17SiShaderVidMemMgr11SetupShaderEjP16SiBltShaderInput 00000000000cb0c4 g 0f SECT 01 0000 [.text] __ZN17SiShaderVidMemMgr14GetPixelShaderEj 00000000000cb098 g 0f SECT 01 0000 [.text] __ZN17SiShaderVidMemMgr15GetVertexShaderEj 00000000000cb0f8 g 0f SECT 01 0000 [.text] __ZN17SiShaderVidMemMgr16GetComputeShaderEj 00000000000caf30 g 0f SECT 01 0000 [.text] __ZN17SiShaderVidMemMgr17GpuLoadAllShadersEP9BltDevice 00000000000cad7c g 0f SECT 01 0000 [.text] __ZN17SiShaderVidMemMgr21CpuLoadInitialShadersEv 00000000000caf22 g 0f SECT 01 0000 [.text] __ZN17SiShaderVidMemMgr21GpuLoadInitialShadersEP9BltDevice 00000000000ca5ee g 0f SECT 01 0000 [.text] __ZN17SiShaderVidMemMgr28InitializeShaderGroupMappingEv 00000000000caa32 g 0f SECT 01 0000 [.text] __ZN17SiShaderVidMemMgrC1EP8SiBltMgr 00000000000ca93a g 0f SECT 01 0000 [.text] __ZN17SiShaderVidMemMgrC2EP8SiBltMgr 00000000000cacb0 g 0f SECT 01 0000 [.text] __ZN17SiShaderVidMemMgrD0Ev 00000000000cab76 g 0f SECT 01 0000 [.text] __ZN17SiShaderVidMemMgrD1Ev 00000000000caa3c g 0f SECT 01 0000 [.text] __ZN17SiShaderVidMemMgrD2Ev 000000000052e530 g 0f SECT 0a 0000 [__DATA.__common] __ZN18AMDBonaireHardware10gMetaClassE 00000000003b2b48 g 0f SECT 08 0000 [.const_data] __ZN18AMDBonaireHardware10superClassE 00000000000775d8 g 0f SECT 01 0000 [.text] __ZN18AMDBonaireHardware19getATIChipConfigBitEv 00000000000775b4 g 0f SECT 01 0000 [.text] __ZN18AMDBonaireHardware23readChipRevFromRegisterEv 00000000000776a4 g 0f SECT 01 0000 [.text] __ZN18AMDBonaireHardware32setupAndInitializeHWCapabilitiesEv 00000000000775a2 g 0f SECT 01 0000 [.text] __ZN18AMDBonaireHardware4initEP11IOPCIDeviceP28AMDRadeonX4000_IAMDHWHandlerRjjP16_GART_PARAMETERSP14_FB_PARAMETERS 00000000000775e4 g 0f SECT 01 0000 [.text] __ZN18AMDBonaireHardware7powerUpEv 0000000000077410 g 0f SECT 01 0000 [.text] __ZN18AMDBonaireHardware9MetaClassC1Ev 00000000000774d0 g 0f SECT 01 0000 [.text] __ZN18AMDBonaireHardware9MetaClassC2Ev 00000000003b2b40 g 0f SECT 08 0000 [.const_data] __ZN18AMDBonaireHardware9metaClassE 000000000007746c g 0f SECT 01 0000 [.text] __ZN18AMDBonaireHardwareC1EPK11OSMetaClass 0000000000077542 g 0f SECT 01 0000 [.text] __ZN18AMDBonaireHardwareC1Ev 000000000007744c g 0f SECT 01 0000 [.text] __ZN18AMDBonaireHardwareC2EPK11OSMetaClass 0000000000077572 g 0f SECT 01 0000 [.text] __ZN18AMDBonaireHardwareC2Ev 00000000000774a0 g 0f SECT 01 0000 [.text] __ZN18AMDBonaireHardwareD0Ev 0000000000077496 g 0f SECT 01 0000 [.text] __ZN18AMDBonaireHardwareD1Ev 000000000007748c g 0f SECT 01 0000 [.text] __ZN18AMDBonaireHardwareD2Ev 000000000052e788 g 0f SECT 0a 0000 [__DATA.__common] __ZN18AMDCISAMUGPCOMRing10gMetaClassE 00000000003b6688 g 0f SECT 08 0000 [.const_data] __ZN18AMDCISAMUGPCOMRing10superClassE 000000000008072a g 0f SECT 01 0000 [.text] __ZN18AMDCISAMUGPCOMRing11commitBlockEj 0000000000080654 g 0f SECT 01 0000 [.text] __ZN18AMDCISAMUGPCOMRing13freeResourcesEv 0000000000080744 g 0f SECT 01 0000 [.text] __ZN18AMDCISAMUGPCOMRing14getReadPointerEv 00000000000807cc g 0f SECT 01 0000 [.text] __ZN18AMDCISAMUGPCOMRing15getWritePointerEv 00000000000806cc g 0f SECT 01 0000 [.text] __ZN18AMDCISAMUGPCOMRing16registerLocationEv 000000000008056e g 0f SECT 01 0000 [.text] __ZN18AMDCISAMUGPCOMRing17allocateResourcesEv 0000000000080786 g 0f SECT 01 0000 [.text] __ZN18AMDCISAMUGPCOMRing22readIndirectSAMUSABRegEj 00000000000808ec g 0f SECT 01 0000 [.text] __ZN18AMDCISAMUGPCOMRing23writeIndirectSAMUSABRegEjj 00000000000806f0 g 0f SECT 01 0000 [.text] __ZN18AMDCISAMUGPCOMRing26enableReadPointerWriteBackEv 00000000000806f6 g 0f SECT 01 0000 [.text] __ZN18AMDCISAMUGPCOMRing27disableReadPointerWriteBackEv 0000000000080702 g 0f SECT 01 0000 [.text] __ZN18AMDCISAMUGPCOMRing27programReadAndWritePointersEj 0000000000080532 g 0f SECT 01 0000 [.text] __ZN18AMDCISAMUGPCOMRing4freeEv 0000000000080492 g 0f SECT 01 0000 [.text] __ZN18AMDCISAMUGPCOMRing4initEP30AMDRadeonX4000_IAMDHWInterfacei20_eAMD_HW_ENGINE_TYPEjPKv 000000000008073e g 0f SECT 01 0000 [.text] __ZN18AMDCISAMUGPCOMRing5alignEv 00000000000806fc g 0f SECT 01 0000 [.text] __ZN18AMDCISAMUGPCOMRing5resetEv 000000000008070a g 0f SECT 01 0000 [.text] __ZN18AMDCISAMUGPCOMRing5writeEj 00000000000806be g 0f SECT 01 0000 [.text] __ZN18AMDCISAMUGPCOMRing7getHeadEv 0000000000080300 g 0f SECT 01 0000 [.text] __ZN18AMDCISAMUGPCOMRing9MetaClassC1Ev 00000000000803c0 g 0f SECT 01 0000 [.text] __ZN18AMDCISAMUGPCOMRing9MetaClassC2Ev 00000000003b6680 g 0f SECT 08 0000 [.const_data] __ZN18AMDCISAMUGPCOMRing9metaClassE 000000000008080e g 0f SECT 01 0000 [.text] __ZN18AMDCISAMUGPCOMRing9writeTailEv 000000000008035c g 0f SECT 01 0000 [.text] __ZN18AMDCISAMUGPCOMRingC1EPK11OSMetaClass 0000000000080432 g 0f SECT 01 0000 [.text] __ZN18AMDCISAMUGPCOMRingC1Ev 000000000008033c g 0f SECT 01 0000 [.text] __ZN18AMDCISAMUGPCOMRingC2EPK11OSMetaClass 0000000000080462 g 0f SECT 01 0000 [.text] __ZN18AMDCISAMUGPCOMRingC2Ev 0000000000080390 g 0f SECT 01 0000 [.text] __ZN18AMDCISAMUGPCOMRingD0Ev 0000000000080386 g 0f SECT 01 0000 [.text] __ZN18AMDCISAMUGPCOMRingD1Ev 000000000008037c g 0f SECT 01 0000 [.text] __ZN18AMDCISAMUGPCOMRingD2Ev 000000000052e850 g 0f SECT 0a 0000 [__DATA.__common] __ZN18AMDCIVCELLQChannel10gMetaClassE 00000000003b79a8 g 0f SECT 08 0000 [.const_data] __ZN18AMDCIVCELLQChannel10superClassE 0000000000082206 g 0f SECT 01 0000 [.text] __ZN18AMDCIVCELLQChannel22timeStampInterruptTypeEv 00000000000821f4 g 0f SECT 01 0000 [.text] __ZN18AMDCIVCELLQChannel4freeEv 00000000000821e2 g 0f SECT 01 0000 [.text] __ZN18AMDCIVCELLQChannel4initEiP30AMDRadeonX4000_IAMDHWInterfaceP27AMDRadeonX4000_IAMDHWEngineP25AMDRadeonX4000_IAMDHWRingPKc 0000000000082050 g 0f SECT 01 0000 [.text] __ZN18AMDCIVCELLQChannel9MetaClassC1Ev 0000000000082110 g 0f SECT 01 0000 [.text] __ZN18AMDCIVCELLQChannel9MetaClassC2Ev 00000000003b79a0 g 0f SECT 08 0000 [.const_data] __ZN18AMDCIVCELLQChannel9metaClassE 00000000000820ac g 0f SECT 01 0000 [.text] __ZN18AMDCIVCELLQChannelC1EPK11OSMetaClass 0000000000082182 g 0f SECT 01 0000 [.text] __ZN18AMDCIVCELLQChannelC1Ev 000000000008208c g 0f SECT 01 0000 [.text] __ZN18AMDCIVCELLQChannelC2EPK11OSMetaClass 00000000000821b2 g 0f SECT 01 0000 [.text] __ZN18AMDCIVCELLQChannelC2Ev 00000000000820e0 g 0f SECT 01 0000 [.text] __ZN18AMDCIVCELLQChannelD0Ev 00000000000820d6 g 0f SECT 01 0000 [.text] __ZN18AMDCIVCELLQChannelD1Ev 00000000000820cc g 0f SECT 01 0000 [.text] __ZN18AMDCIVCELLQChannelD2Ev 000000000052e350 g 0f SECT 0a 0000 [__DATA.__common] __ZN18AMDSIVCELLQChannel10gMetaClassE 00000000003afce8 g 0f SECT 08 0000 [.const_data] __ZN18AMDSIVCELLQChannel10superClassE 00000000000701e6 g 0f SECT 01 0000 [.text] __ZN18AMDSIVCELLQChannel22timeStampInterruptTypeEv 00000000000701d4 g 0f SECT 01 0000 [.text] __ZN18AMDSIVCELLQChannel4freeEv 00000000000701c2 g 0f SECT 01 0000 [.text] __ZN18AMDSIVCELLQChannel4initEiP30AMDRadeonX4000_IAMDHWInterfaceP27AMDRadeonX4000_IAMDHWEngineP25AMDRadeonX4000_IAMDHWRingPKc 0000000000070030 g 0f SECT 01 0000 [.text] __ZN18AMDSIVCELLQChannel9MetaClassC1Ev 00000000000700f0 g 0f SECT 01 0000 [.text] __ZN18AMDSIVCELLQChannel9MetaClassC2Ev 00000000003afce0 g 0f SECT 08 0000 [.const_data] __ZN18AMDSIVCELLQChannel9metaClassE 000000000007008c g 0f SECT 01 0000 [.text] __ZN18AMDSIVCELLQChannelC1EPK11OSMetaClass 0000000000070162 g 0f SECT 01 0000 [.text] __ZN18AMDSIVCELLQChannelC1Ev 000000000007006c g 0f SECT 01 0000 [.text] __ZN18AMDSIVCELLQChannelC2EPK11OSMetaClass 0000000000070192 g 0f SECT 01 0000 [.text] __ZN18AMDSIVCELLQChannelC2Ev 00000000000700c0 g 0f SECT 01 0000 [.text] __ZN18AMDSIVCELLQChannelD0Ev 00000000000700b6 g 0f SECT 01 0000 [.text] __ZN18AMDSIVCELLQChannelD1Ev 00000000000700ac g 0f SECT 01 0000 [.text] __ZN18AMDSIVCELLQChannelD2Ev 000000000052e1c0 g 0f SECT 0a 0000 [__DATA.__common] __ZN18AMDTahitiPM4Engine10gMetaClassE 00000000003ad9b8 g 0f SECT 08 0000 [.const_data] __ZN18AMDTahitiPM4Engine10superClassE 000000000006bc62 g 0f SECT 01 0000 [.text] __ZN18AMDTahitiPM4Engine4initEP30AMDRadeonX4000_IAMDHWInterface20_eAMD_HW_ENGINE_TYPE 000000000006bad0 g 0f SECT 01 0000 [.text] __ZN18AMDTahitiPM4Engine9MetaClassC1Ev 000000000006bb90 g 0f SECT 01 0000 [.text] __ZN18AMDTahitiPM4Engine9MetaClassC2Ev 00000000003ad9b0 g 0f SECT 08 0000 [.const_data] __ZN18AMDTahitiPM4Engine9metaClassE 000000000006bb2c g 0f SECT 01 0000 [.text] __ZN18AMDTahitiPM4EngineC1EPK11OSMetaClass 000000000006bc02 g 0f SECT 01 0000 [.text] __ZN18AMDTahitiPM4EngineC1Ev 000000000006bb0c g 0f SECT 01 0000 [.text] __ZN18AMDTahitiPM4EngineC2EPK11OSMetaClass 000000000006bc32 g 0f SECT 01 0000 [.text] __ZN18AMDTahitiPM4EngineC2Ev 000000000006bb60 g 0f SECT 01 0000 [.text] __ZN18AMDTahitiPM4EngineD0Ev 000000000006bb56 g 0f SECT 01 0000 [.text] __ZN18AMDTahitiPM4EngineD1Ev 000000000006bb4c g 0f SECT 01 0000 [.text] __ZN18AMDTahitiPM4EngineD2Ev 000000000052ec38 g 0f SECT 0a 0000 [__DATA.__common] __ZN18AMDVISAMUGPCOMRing10gMetaClassE 00000000003bd5b8 g 0f SECT 08 0000 [.const_data] __ZN18AMDVISAMUGPCOMRing10superClassE 0000000000093056 g 0f SECT 01 0000 [.text] __ZN18AMDVISAMUGPCOMRing14getReadPointerEv 00000000000930de g 0f SECT 01 0000 [.text] __ZN18AMDVISAMUGPCOMRing15getWritePointerEv 0000000000093098 g 0f SECT 01 0000 [.text] __ZN18AMDVISAMUGPCOMRing22readIndirectSAMUSABRegEj 00000000000931fe g 0f SECT 01 0000 [.text] __ZN18AMDVISAMUGPCOMRing23writeIndirectSAMUSABRegEjj 0000000000093044 g 0f SECT 01 0000 [.text] __ZN18AMDVISAMUGPCOMRing4freeEv 0000000000093032 g 0f SECT 01 0000 [.text] __ZN18AMDVISAMUGPCOMRing4initEP30AMDRadeonX4000_IAMDHWInterfacei20_eAMD_HW_ENGINE_TYPEjPKv 0000000000092ea0 g 0f SECT 01 0000 [.text] __ZN18AMDVISAMUGPCOMRing9MetaClassC1Ev 0000000000092f60 g 0f SECT 01 0000 [.text] __ZN18AMDVISAMUGPCOMRing9MetaClassC2Ev 00000000003bd5b0 g 0f SECT 08 0000 [.const_data] __ZN18AMDVISAMUGPCOMRing9metaClassE 0000000000093120 g 0f SECT 01 0000 [.text] __ZN18AMDVISAMUGPCOMRing9writeTailEv 0000000000092efc g 0f SECT 01 0000 [.text] __ZN18AMDVISAMUGPCOMRingC1EPK11OSMetaClass 0000000000092fd2 g 0f SECT 01 0000 [.text] __ZN18AMDVISAMUGPCOMRingC1Ev 0000000000092edc g 0f SECT 01 0000 [.text] __ZN18AMDVISAMUGPCOMRingC2EPK11OSMetaClass 0000000000093002 g 0f SECT 01 0000 [.text] __ZN18AMDVISAMUGPCOMRingC2Ev 0000000000092f30 g 0f SECT 01 0000 [.text] __ZN18AMDVISAMUGPCOMRingD0Ev 0000000000092f26 g 0f SECT 01 0000 [.text] __ZN18AMDVISAMUGPCOMRingD1Ev 0000000000092f1c g 0f SECT 01 0000 [.text] __ZN18AMDVISAMUGPCOMRingD2Ev 00000000000aad38 g 0f SECT 01 0000 [.text] __ZN18SiBltComputeShader14SetShaderInputEPK23SiBltComputeShaderInput 00000000000aad46 g 0f SECT 01 0000 [.text] __ZN18SiBltComputeShader18GetThreadGroupSizeEPjS0_S0_ 00000000000bddec g 0f SECT 01 0000 [.text] __ZN18SiBltShaderLibrary12SetupShadersEv 00000000000bde14 g 0f SECT 01 0000 [.text] __ZN18SiBltShaderLibrary14CpuLoadShadersEv 00000000000bde24 g 0f SECT 01 0000 [.text] __ZN18SiBltShaderLibrary14GpuLoadShadersEP11SiBltDevice 00000000000c26d0 g 0f SECT 01 0000 [.text] __ZN18SiBltShaderLibrary14SetupCiShadersEv 00000000000be8d8 g 0f SECT 01 0000 [.text] __ZN18SiBltShaderLibrary14SetupSiShadersEv 00000000000c64c8 g 0f SECT 01 0000 [.text] __ZN18SiBltShaderLibrary14SetupViShadersEv 00000000000be8ca g 0f SECT 01 0000 [.text] __ZN18SiBltShaderLibrary18PsPatchingDisabledE6PsType 00000000000bdda8 g 0f SECT 01 0000 [.text] __ZN18SiBltShaderLibrary4InitEP8SiBltMgr 00000000000bdd6e g 0f SECT 01 0000 [.text] __ZN18SiBltShaderLibraryC1Ev 00000000000bdd60 g 0f SECT 01 0000 [.text] __ZN18SiBltShaderLibraryC2Ev 00000000000bdd92 g 0f SECT 01 0000 [.text] __ZN18SiBltShaderLibraryD1Ev 00000000000bdd7c g 0f SECT 01 0000 [.text] __ZN18SiBltShaderLibraryD2Ev 000000000052e760 g 0f SECT 0a 0000 [__DATA.__common] __ZN19AMDCISAMURBIChannel10gMetaClassE 00000000003b62e8 g 0f SECT 08 0000 [.const_data] __ZN19AMDCISAMURBIChannel10superClassE 00000000000800fc g 0f SECT 01 0000 [.text] __ZN19AMDCISAMURBIChannel27commitIndirectCommandBufferEP30AMD_SUBMIT_COMMAND_BUFFER_INFO 00000000000800ea g 0f SECT 01 0000 [.text] __ZN19AMDCISAMURBIChannel4freeEv 0000000000080092 g 0f SECT 01 0000 [.text] __ZN19AMDCISAMURBIChannel4initEiP30AMDRadeonX4000_IAMDHWInterfaceP27AMDRadeonX4000_IAMDHWEngineP25AMDRadeonX4000_IAMDHWRingPKc 000000000007ff00 g 0f SECT 01 0000 [.text] __ZN19AMDCISAMURBIChannel9MetaClassC1Ev 000000000007ffc0 g 0f SECT 01 0000 [.text] __ZN19AMDCISAMURBIChannel9MetaClassC2Ev 00000000003b62e0 g 0f SECT 08 0000 [.const_data] __ZN19AMDCISAMURBIChannel9metaClassE 000000000007ff5c g 0f SECT 01 0000 [.text] __ZN19AMDCISAMURBIChannelC1EPK11OSMetaClass 0000000000080032 g 0f SECT 01 0000 [.text] __ZN19AMDCISAMURBIChannelC1Ev 000000000007ff3c g 0f SECT 01 0000 [.text] __ZN19AMDCISAMURBIChannelC2EPK11OSMetaClass 0000000000080062 g 0f SECT 01 0000 [.text] __ZN19AMDCISAMURBIChannelC2Ev 000000000007ff90 g 0f SECT 01 0000 [.text] __ZN19AMDCISAMURBIChannelD0Ev 000000000007ff86 g 0f SECT 01 0000 [.text] __ZN19AMDCISAMURBIChannelD1Ev 000000000007ff7c g 0f SECT 01 0000 [.text] __ZN19AMDCISAMURBIChannelD2Ev 000000000052e120 g 0f SECT 0a 0000 [__DATA.__common] __ZN19AMDPitcairnHardware10gMetaClassE 00000000003ac518 g 0f SECT 08 0000 [.const_data] __ZN19AMDPitcairnHardware10superClassE 000000000006a3a4 g 0f SECT 01 0000 [.text] __ZN19AMDPitcairnHardware11allocateSMLEv 000000000006a4b4 g 0f SECT 01 0000 [.text] __ZN19AMDPitcairnHardware17allocatePM4EngineEv 000000000006a398 g 0f SECT 01 0000 [.text] __ZN19AMDPitcairnHardware19getATIChipConfigBitEv 000000000006a374 g 0f SECT 01 0000 [.text] __ZN19AMDPitcairnHardware23readChipRevFromRegisterEv 000000000006a48a g 0f SECT 01 0000 [.text] __ZN19AMDPitcairnHardware32setupAndInitializeHWCapabilitiesEv 000000000006a362 g 0f SECT 01 0000 [.text] __ZN19AMDPitcairnHardware4initEP11IOPCIDeviceP28AMDRadeonX4000_IAMDHWHandlerRjjP16_GART_PARAMETERSP14_FB_PARAMETERS 000000000006a3ca g 0f SECT 01 0000 [.text] __ZN19AMDPitcairnHardware7powerUpEv 000000000006a1d0 g 0f SECT 01 0000 [.text] __ZN19AMDPitcairnHardware9MetaClassC1Ev 000000000006a290 g 0f SECT 01 0000 [.text] __ZN19AMDPitcairnHardware9MetaClassC2Ev 00000000003ac510 g 0f SECT 08 0000 [.const_data] __ZN19AMDPitcairnHardware9metaClassE 000000000006a22c g 0f SECT 01 0000 [.text] __ZN19AMDPitcairnHardwareC1EPK11OSMetaClass 000000000006a302 g 0f SECT 01 0000 [.text] __ZN19AMDPitcairnHardwareC1Ev 000000000006a20c g 0f SECT 01 0000 [.text] __ZN19AMDPitcairnHardwareC2EPK11OSMetaClass 000000000006a332 g 0f SECT 01 0000 [.text] __ZN19AMDPitcairnHardwareC2Ev 000000000006a260 g 0f SECT 01 0000 [.text] __ZN19AMDPitcairnHardwareD0Ev 000000000006a256 g 0f SECT 01 0000 [.text] __ZN19AMDPitcairnHardwareD1Ev 000000000006a24c g 0f SECT 01 0000 [.text] __ZN19AMDPitcairnHardwareD2Ev 000000000052d608 g 0f SECT 0a 0000 [__DATA.__common] __ZN19AMDSIDisplayMachine10gMetaClassE 0000000000396898 g 0f SECT 08 0000 [.const_data] __ZN19AMDSIDisplayMachine10superClassE 000000000002a010 g 0f SECT 01 0000 [.text] __ZN19AMDSIDisplayMachine9MetaClassC1Ev 000000000002a0d0 g 0f SECT 01 0000 [.text] __ZN19AMDSIDisplayMachine9MetaClassC2Ev 0000000000396890 g 0f SECT 08 0000 [.const_data] __ZN19AMDSIDisplayMachine9metaClassE 000000000002a06c g 0f SECT 01 0000 [.text] __ZN19AMDSIDisplayMachineC1EPK11OSMetaClass 000000000002a142 g 0f SECT 01 0000 [.text] __ZN19AMDSIDisplayMachineC1Ev 000000000002a04c g 0f SECT 01 0000 [.text] __ZN19AMDSIDisplayMachineC2EPK11OSMetaClass 000000000002a172 g 0f SECT 01 0000 [.text] __ZN19AMDSIDisplayMachineC2Ev 000000000002a0a0 g 0f SECT 01 0000 [.text] __ZN19AMDSIDisplayMachineD0Ev 000000000002a096 g 0f SECT 01 0000 [.text] __ZN19AMDSIDisplayMachineD1Ev 000000000002a08c g 0f SECT 01 0000 [.text] __ZN19AMDSIDisplayMachineD2Ev 000000000052e170 g 0f SECT 0a 0000 [__DATA.__common] __ZN19AMDSIHWAlignManager10gMetaClassE 00000000003ad378 g 0f SECT 08 0000 [.const_data] __ZN19AMDSIHWAlignManager10superClassE 000000000006af82 g 0f SECT 01 0000 [.text] __ZN19AMDSIHWAlignManager13getAddrFormatEj 000000000006adf0 g 0f SECT 01 0000 [.text] __ZN19AMDSIHWAlignManager9MetaClassC1Ev 000000000006aeb0 g 0f SECT 01 0000 [.text] __ZN19AMDSIHWAlignManager9MetaClassC2Ev 00000000003ad370 g 0f SECT 08 0000 [.const_data] __ZN19AMDSIHWAlignManager9metaClassE 000000000006ae4c g 0f SECT 01 0000 [.text] __ZN19AMDSIHWAlignManagerC1EPK11OSMetaClass 000000000006af22 g 0f SECT 01 0000 [.text] __ZN19AMDSIHWAlignManagerC1Ev 000000000006ae2c g 0f SECT 01 0000 [.text] __ZN19AMDSIHWAlignManagerC2EPK11OSMetaClass 000000000006af52 g 0f SECT 01 0000 [.text] __ZN19AMDSIHWAlignManagerC2Ev 000000000006ae80 g 0f SECT 01 0000 [.text] __ZN19AMDSIHWAlignManagerD0Ev 000000000006ae76 g 0f SECT 01 0000 [.text] __ZN19AMDSIHWAlignManagerD1Ev 000000000006ae6c g 0f SECT 01 0000 [.text] __ZN19AMDSIHWAlignManagerD2Ev 000000000052d810 g 0f SECT 0a 0000 [__DATA.__common] __ZN19AMDVIDisplayMachine10gMetaClassE 000000000039f948 g 0f SECT 08 0000 [.const_data] __ZN19AMDVIDisplayMachine10superClassE 0000000000046d60 g 0f SECT 01 0000 [.text] __ZN19AMDVIDisplayMachine9MetaClassC1Ev 0000000000046e20 g 0f SECT 01 0000 [.text] __ZN19AMDVIDisplayMachine9MetaClassC2Ev 000000000039f940 g 0f SECT 08 0000 [.const_data] __ZN19AMDVIDisplayMachine9metaClassE 0000000000046dbc g 0f SECT 01 0000 [.text] __ZN19AMDVIDisplayMachineC1EPK11OSMetaClass 0000000000046e92 g 0f SECT 01 0000 [.text] __ZN19AMDVIDisplayMachineC1Ev 0000000000046d9c g 0f SECT 01 0000 [.text] __ZN19AMDVIDisplayMachineC2EPK11OSMetaClass 0000000000046ec2 g 0f SECT 01 0000 [.text] __ZN19AMDVIDisplayMachineC2Ev 0000000000046df0 g 0f SECT 01 0000 [.text] __ZN19AMDVIDisplayMachineD0Ev 0000000000046de6 g 0f SECT 01 0000 [.text] __ZN19AMDVIDisplayMachineD1Ev 0000000000046ddc g 0f SECT 01 0000 [.text] __ZN19AMDVIDisplayMachineD2Ev 000000000052ec10 g 0f SECT 0a 0000 [__DATA.__common] __ZN19AMDVISAMURBIChannel10gMetaClassE 00000000003bd218 g 0f SECT 08 0000 [.const_data] __ZN19AMDVISAMURBIChannel10superClassE 0000000000092d14 g 0f SECT 01 0000 [.text] __ZN19AMDVISAMURBIChannel4freeEv 0000000000092d02 g 0f SECT 01 0000 [.text] __ZN19AMDVISAMURBIChannel4initEiP30AMDRadeonX4000_IAMDHWInterfaceP27AMDRadeonX4000_IAMDHWEngineP25AMDRadeonX4000_IAMDHWRingPKc 0000000000092b70 g 0f SECT 01 0000 [.text] __ZN19AMDVISAMURBIChannel9MetaClassC1Ev 0000000000092c30 g 0f SECT 01 0000 [.text] __ZN19AMDVISAMURBIChannel9MetaClassC2Ev 00000000003bd210 g 0f SECT 08 0000 [.const_data] __ZN19AMDVISAMURBIChannel9metaClassE 0000000000092bcc g 0f SECT 01 0000 [.text] __ZN19AMDVISAMURBIChannelC1EPK11OSMetaClass 0000000000092ca2 g 0f SECT 01 0000 [.text] __ZN19AMDVISAMURBIChannelC1Ev 0000000000092bac g 0f SECT 01 0000 [.text] __ZN19AMDVISAMURBIChannelC2EPK11OSMetaClass 0000000000092cd2 g 0f SECT 01 0000 [.text] __ZN19AMDVISAMURBIChannelC2Ev 0000000000092c00 g 0f SECT 01 0000 [.text] __ZN19AMDVISAMURBIChannelD0Ev 0000000000092bf6 g 0f SECT 01 0000 [.text] __ZN19AMDVISAMURBIChannelD1Ev 0000000000092bec g 0f SECT 01 0000 [.text] __ZN19AMDVISAMURBIChannelD2Ev 000000000052e1e8 g 0f SECT 0a 0000 [__DATA.__common] __ZN20AMDPitcairnPM4Engine10gMetaClassE 00000000003add18 g 0f SECT 08 0000 [.const_data] __ZN20AMDPitcairnPM4Engine10superClassE 000000000006bfc2 g 0f SECT 01 0000 [.text] __ZN20AMDPitcairnPM4Engine4initEP30AMDRadeonX4000_IAMDHWInterface20_eAMD_HW_ENGINE_TYPE 000000000006be30 g 0f SECT 01 0000 [.text] __ZN20AMDPitcairnPM4Engine9MetaClassC1Ev 000000000006bef0 g 0f SECT 01 0000 [.text] __ZN20AMDPitcairnPM4Engine9MetaClassC2Ev 00000000003add10 g 0f SECT 08 0000 [.const_data] __ZN20AMDPitcairnPM4Engine9metaClassE 000000000006be8c g 0f SECT 01 0000 [.text] __ZN20AMDPitcairnPM4EngineC1EPK11OSMetaClass 000000000006bf62 g 0f SECT 01 0000 [.text] __ZN20AMDPitcairnPM4EngineC1Ev 000000000006be6c g 0f SECT 01 0000 [.text] __ZN20AMDPitcairnPM4EngineC2EPK11OSMetaClass 000000000006bf92 g 0f SECT 01 0000 [.text] __ZN20AMDPitcairnPM4EngineC2Ev 000000000006bec0 g 0f SECT 01 0000 [.text] __ZN20AMDPitcairnPM4EngineD0Ev 000000000006beb6 g 0f SECT 01 0000 [.text] __ZN20AMDPitcairnPM4EngineD1Ev 000000000006beac g 0f SECT 01 0000 [.text] __ZN20AMDPitcairnPM4EngineD2Ev 000000000052e7b0 g 0f SECT 0a 0000 [__DATA.__common] __ZN21AMDCISAMUGPCOMChannel10gMetaClassE 00000000003b69c8 g 0f SECT 08 0000 [.const_data] __ZN21AMDCISAMUGPCOMChannel10superClassE 0000000000080c6e g 0f SECT 01 0000 [.text] __ZN21AMDCISAMUGPCOMChannel27commitIndirectCommandBufferEP30AMD_SUBMIT_COMMAND_BUFFER_INFO 0000000000080c5c g 0f SECT 01 0000 [.text] __ZN21AMDCISAMUGPCOMChannel4freeEv 0000000000080c12 g 0f SECT 01 0000 [.text] __ZN21AMDCISAMUGPCOMChannel4initEiP30AMDRadeonX4000_IAMDHWInterfaceP27AMDRadeonX4000_IAMDHWEngineP25AMDRadeonX4000_IAMDHWRingPKc 0000000000080a80 g 0f SECT 01 0000 [.text] __ZN21AMDCISAMUGPCOMChannel9MetaClassC1Ev 0000000000080b40 g 0f SECT 01 0000 [.text] __ZN21AMDCISAMUGPCOMChannel9MetaClassC2Ev 00000000003b69c0 g 0f SECT 08 0000 [.const_data] __ZN21AMDCISAMUGPCOMChannel9metaClassE 0000000000080adc g 0f SECT 01 0000 [.text] __ZN21AMDCISAMUGPCOMChannelC1EPK11OSMetaClass 0000000000080bb2 g 0f SECT 01 0000 [.text] __ZN21AMDCISAMUGPCOMChannelC1Ev 0000000000080abc g 0f SECT 01 0000 [.text] __ZN21AMDCISAMUGPCOMChannelC2EPK11OSMetaClass 0000000000080be2 g 0f SECT 01 0000 [.text] __ZN21AMDCISAMUGPCOMChannelC2Ev 0000000000080b10 g 0f SECT 01 0000 [.text] __ZN21AMDCISAMUGPCOMChannelD0Ev 0000000000080b06 g 0f SECT 01 0000 [.text] __ZN21AMDCISAMUGPCOMChannelD1Ev 0000000000080afc g 0f SECT 01 0000 [.text] __ZN21AMDCISAMUGPCOMChannelD2Ev 000000000052ec60 g 0f SECT 0a 0000 [__DATA.__common] __ZN21AMDVISAMUGPCOMChannel10gMetaClassE 00000000003bd8f8 g 0f SECT 08 0000 [.const_data] __ZN21AMDVISAMUGPCOMChannel10superClassE 0000000000093534 g 0f SECT 01 0000 [.text] __ZN21AMDVISAMUGPCOMChannel4freeEv 0000000000093522 g 0f SECT 01 0000 [.text] __ZN21AMDVISAMUGPCOMChannel4initEiP30AMDRadeonX4000_IAMDHWInterfaceP27AMDRadeonX4000_IAMDHWEngineP25AMDRadeonX4000_IAMDHWRingPKc 0000000000093390 g 0f SECT 01 0000 [.text] __ZN21AMDVISAMUGPCOMChannel9MetaClassC1Ev 0000000000093450 g 0f SECT 01 0000 [.text] __ZN21AMDVISAMUGPCOMChannel9MetaClassC2Ev 00000000003bd8f0 g 0f SECT 08 0000 [.const_data] __ZN21AMDVISAMUGPCOMChannel9metaClassE 00000000000933ec g 0f SECT 01 0000 [.text] __ZN21AMDVISAMUGPCOMChannelC1EPK11OSMetaClass 00000000000934c2 g 0f SECT 01 0000 [.text] __ZN21AMDVISAMUGPCOMChannelC1Ev 00000000000933cc g 0f SECT 01 0000 [.text] __ZN21AMDVISAMUGPCOMChannelC2EPK11OSMetaClass 00000000000934f2 g 0f SECT 01 0000 [.text] __ZN21AMDVISAMUGPCOMChannelC2Ev 0000000000093420 g 0f SECT 01 0000 [.text] __ZN21AMDVISAMUGPCOMChannelD0Ev 0000000000093416 g 0f SECT 01 0000 [.text] __ZN21AMDVISAMUGPCOMChannelD1Ev 000000000009340c g 0f SECT 01 0000 [.text] __ZN21AMDVISAMUGPCOMChannelD2Ev 000000000052e8f0 g 0f SECT 0a 0000 [__DATA.__common] __ZN22AMDCIPM4ComputeChannel10gMetaClassE 00000000003b86b8 g 0f SECT 08 0000 [.const_data] __ZN22AMDCIPM4ComputeChannel10superClassE 000000000008354e g 0f SECT 01 0000 [.text] __ZN22AMDCIPM4ComputeChannel18writeDataCmdPacketEP19_PM4_MEC_WRITE_DATA27MEC_WRITE_DATA_dst_sel_enum29MEC_WRITE_DATA_addr_incr_enum30MEC_WRITE_DATA_wr_confirm_enum32MEC_WRITE_DATA_cache_policy_enumyPKjj 000000000008360a g 0f SECT 01 0000 [.text] __ZN22AMDCIPM4ComputeChannel19acquireMemCmdPacketEP20_PM4_MEC_ACQUIRE_MEMjyyt 0000000000083c4e g 0f SECT 01 0000 [.text] __ZN22AMDCIPM4ComputeChannel19eventWriteCmdPacketEP20_PM4_MEC_EVENT_WRITE32MEC_EVENT_WRITE_event_index_enumj 00000000000839d2 g 0f SECT 01 0000 [.text] __ZN22AMDCIPM4ComputeChannel19releaseMemCmdPacketEP20_PM4_MEC_RELEASE_MEMj32MEC_RELEASE_MEM_event_index_enum33MEC_RELEASE_MEM_cache_policy_enum28MEC_RELEASE_MEM_dst_sel_enum28MEC_RELEASE_MEM_int_sel_enum29MEC_RELEASE_MEM_data_sel_enumyy 0000000000083ba6 g 0f SECT 01 0000 [.text] __ZN22AMDCIPM4ComputeChannel19releaseSubmitFramesEv 0000000000083a9e g 0f SECT 01 0000 [.text] __ZN22AMDCIPM4ComputeChannel22initializeSubmitFramesEv 0000000000083be2 g 0f SECT 01 0000 [.text] __ZN22AMDCIPM4ComputeChannel22timeStampInterruptTypeEv 0000000000083c30 g 0f SECT 01 0000 [.text] __ZN22AMDCIPM4ComputeChannel22writeEventWriteCommandEPjjj 00000000000837d0 g 0f SECT 01 0000 [.text] __ZN22AMDCIPM4ComputeChannel23indirectBufferCmdPacketEP24_PM4_MEC_INDIRECT_BUFFERyjjb 0000000000083c12 g 0f SECT 01 0000 [.text] __ZN22AMDCIPM4ComputeChannel23writeSurfaceSyncCommandEPjjyyj 0000000000083ae0 g 0f SECT 01 0000 [.text] __ZN22AMDCIPM4ComputeChannel24initializeTimestampFrameEv 0000000000083c6e g 0f SECT 01 0000 [.text] __ZN22AMDCIPM4ComputeChannel25writeEventWriteEOPCommandEPjjjyjjy 0000000000083698 g 0f SECT 01 0000 [.text] __ZN22AMDCIPM4ComputeChannel27commitIndirectCommandBufferEP30AMD_SUBMIT_COMMAND_BUFFER_INFO 0000000000083866 g 0f SECT 01 0000 [.text] __ZN22AMDCIPM4ComputeChannel36initializeIndirectCommandBufferFrameEv 0000000000083410 g 0f SECT 01 0000 [.text] __ZN22AMDCIPM4ComputeChannel48writeFlushAndInvalidateDestinationCachesCommandsEv 00000000000833fe g 0f SECT 01 0000 [.text] __ZN22AMDCIPM4ComputeChannel4freeEv 00000000000833e2 g 0f SECT 01 0000 [.text] __ZN22AMDCIPM4ComputeChannel4initEiP30AMDRadeonX4000_IAMDHWInterfaceP27AMDRadeonX4000_IAMDHWEngineP25AMDRadeonX4000_IAMDHWRingPKc 0000000000083250 g 0f SECT 01 0000 [.text] __ZN22AMDCIPM4ComputeChannel9MetaClassC1Ev 0000000000083310 g 0f SECT 01 0000 [.text] __ZN22AMDCIPM4ComputeChannel9MetaClassC2Ev 00000000003b86b0 g 0f SECT 08 0000 [.const_data] __ZN22AMDCIPM4ComputeChannel9metaClassE 00000000000832ac g 0f SECT 01 0000 [.text] __ZN22AMDCIPM4ComputeChannelC1EPK11OSMetaClass 0000000000083382 g 0f SECT 01 0000 [.text] __ZN22AMDCIPM4ComputeChannelC1Ev 000000000008328c g 0f SECT 01 0000 [.text] __ZN22AMDCIPM4ComputeChannelC2EPK11OSMetaClass 00000000000833b2 g 0f SECT 01 0000 [.text] __ZN22AMDCIPM4ComputeChannelC2Ev 00000000000832e0 g 0f SECT 01 0000 [.text] __ZN22AMDCIPM4ComputeChannelD0Ev 00000000000832d6 g 0f SECT 01 0000 [.text] __ZN22AMDCIPM4ComputeChannelD1Ev 00000000000832cc g 0f SECT 01 0000 [.text] __ZN22AMDCIPM4ComputeChannelD2Ev 000000000052d5e0 g 0f SECT 0a 0000 [__DATA.__common] __ZN22AMDSIAtomicBlitManager10gMetaClassE 00000000003965d8 g 0f SECT 08 0000 [.const_data] __ZN22AMDSIAtomicBlitManager10superClassE 0000000000029cdc g 0f SECT 01 0000 [.text] __ZN22AMDSIAtomicBlitManager17profilingWriteEndEPjj13LARGE_INTEGER11_UBM_ENGINE 0000000000029c82 g 0f SECT 01 0000 [.text] __ZN22AMDSIAtomicBlitManager19profilingWriteStartEPjj13LARGE_INTEGER11_UBM_ENGINE 0000000000029d34 g 0f SECT 01 0000 [.text] __ZN22AMDSIAtomicBlitManager20handlePreBlitOptionsEPK11ABM_OPTIONSRN35AMDRadeonX4000_AMDAtomicBlitManager17CommandBufferInfoE 0000000000029e5e g 0f SECT 01 0000 [.text] __ZN22AMDSIAtomicBlitManager21handlePostBlitOptionsEPK11ABM_OPTIONSRN35AMDRadeonX4000_AMDAtomicBlitManager17CommandBufferInfoE 0000000000029af0 g 0f SECT 01 0000 [.text] __ZN22AMDSIAtomicBlitManager9MetaClassC1Ev 0000000000029bb0 g 0f SECT 01 0000 [.text] __ZN22AMDSIAtomicBlitManager9MetaClassC2Ev 00000000003965d0 g 0f SECT 08 0000 [.const_data] __ZN22AMDSIAtomicBlitManager9metaClassE 0000000000029b4c g 0f SECT 01 0000 [.text] __ZN22AMDSIAtomicBlitManagerC1EPK11OSMetaClass 0000000000029c22 g 0f SECT 01 0000 [.text] __ZN22AMDSIAtomicBlitManagerC1Ev 0000000000029b2c g 0f SECT 01 0000 [.text] __ZN22AMDSIAtomicBlitManagerC2EPK11OSMetaClass 0000000000029c52 g 0f SECT 01 0000 [.text] __ZN22AMDSIAtomicBlitManagerC2Ev 0000000000029b80 g 0f SECT 01 0000 [.text] __ZN22AMDSIAtomicBlitManagerD0Ev 0000000000029b76 g 0f SECT 01 0000 [.text] __ZN22AMDSIAtomicBlitManagerD1Ev 0000000000029b6c g 0f SECT 01 0000 [.text] __ZN22AMDSIAtomicBlitManagerD2Ev 000000000052e4e0 g 0f SECT 0a 0000 [__DATA.__common] __ZN22AMDSIPM4ComputeChannel10gMetaClassE 00000000003b2028 g 0f SECT 08 0000 [.const_data] __ZN22AMDSIPM4ComputeChannel10superClassE 00000000000745e4 g 0f SECT 01 0000 [.text] __ZN22AMDSIPM4ComputeChannel19releaseSubmitFramesEv 0000000000074626 g 0f SECT 01 0000 [.text] __ZN22AMDSIPM4ComputeChannel19resetPerFramePacketEv 0000000000074620 g 0f SECT 01 0000 [.text] __ZN22AMDSIPM4ComputeChannel19setupPerFramePacketEjjjj 0000000000074658 g 0f SECT 01 0000 [.text] __ZN22AMDSIPM4ComputeChannel20getIBAlignmentFactorEv 000000000007462c g 0f SECT 01 0000 [.text] __ZN22AMDSIPM4ComputeChannel21writeProfilingCommandEPjyjb 0000000000074534 g 0f SECT 01 0000 [.text] __ZN22AMDSIPM4ComputeChannel22initializeSubmitFramesEv 0000000000074634 g 0f SECT 01 0000 [.text] __ZN22AMDSIPM4ComputeChannel22timeStampInterruptTypeEv 0000000000074576 g 0f SECT 01 0000 [.text] __ZN22AMDSIPM4ComputeChannel24initializeTimestampFrameEv 0000000000074286 g 0f SECT 01 0000 [.text] __ZN22AMDSIPM4ComputeChannel27commitIndirectCommandBufferEP30AMD_SUBMIT_COMMAND_BUFFER_INFO 00000000000741d8 g 0f SECT 01 0000 [.text] __ZN22AMDSIPM4ComputeChannel30enableScratchRegisterWritebackEv 00000000000741de g 0f SECT 01 0000 [.text] __ZN22AMDSIPM4ComputeChannel31disableScratchRegisterWritebackEv 00000000000743f4 g 0f SECT 01 0000 [.text] __ZN22AMDSIPM4ComputeChannel36initializeIndirectCommandBufferFrameEv 00000000000741e4 g 0f SECT 01 0000 [.text] __ZN22AMDSIPM4ComputeChannel48writeFlushAndInvalidateDestinationCachesCommandsEv 00000000000740e2 g 0f SECT 01 0000 [.text] __ZN22AMDSIPM4ComputeChannel4initEiP30AMDRadeonX4000_IAMDHWInterfaceP27AMDRadeonX4000_IAMDHWEngineP25AMDRadeonX4000_IAMDHWRingPKc 00000000000740fe g 0f SECT 01 0000 [.text] __ZN22AMDSIPM4ComputeChannel6isIdleEv 0000000000073f50 g 0f SECT 01 0000 [.text] __ZN22AMDSIPM4ComputeChannel9MetaClassC1Ev 0000000000074010 g 0f SECT 01 0000 [.text] __ZN22AMDSIPM4ComputeChannel9MetaClassC2Ev 00000000003b2020 g 0f SECT 08 0000 [.const_data] __ZN22AMDSIPM4ComputeChannel9metaClassE 0000000000073fac g 0f SECT 01 0000 [.text] __ZN22AMDSIPM4ComputeChannelC1EPK11OSMetaClass 0000000000074082 g 0f SECT 01 0000 [.text] __ZN22AMDSIPM4ComputeChannelC1Ev 0000000000073f8c g 0f SECT 01 0000 [.text] __ZN22AMDSIPM4ComputeChannelC2EPK11OSMetaClass 00000000000740b2 g 0f SECT 01 0000 [.text] __ZN22AMDSIPM4ComputeChannelC2Ev 0000000000073fe0 g 0f SECT 01 0000 [.text] __ZN22AMDSIPM4ComputeChannelD0Ev 0000000000073fd6 g 0f SECT 01 0000 [.text] __ZN22AMDSIPM4ComputeChannelD1Ev 0000000000073fcc g 0f SECT 01 0000 [.text] __ZN22AMDSIPM4ComputeChannelD2Ev 000000000052eb98 g 0f SECT 0a 0000 [__DATA.__common] __ZN22AMDVIPM4ComputeChannel10gMetaClassE 00000000003bc728 g 0f SECT 08 0000 [.const_data] __ZN22AMDVIPM4ComputeChannel10superClassE 000000000009190e g 0f SECT 01 0000 [.text] __ZN22AMDVIPM4ComputeChannel18writeDataCmdPacketEP18PM4_MEC_WRITE_DATA27MEC_WRITE_DATA_dst_sel_enum29MEC_WRITE_DATA_addr_incr_enum30MEC_WRITE_DATA_wr_confirm_enum32MEC_WRITE_DATA_cache_policy_enumyPKjj 0000000000091a06 g 0f SECT 01 0000 [.text] __ZN22AMDVIPM4ComputeChannel19acquireMemCmdPacketEP19PM4_MEC_ACQUIRE_MEMjyyt 00000000000920d6 g 0f SECT 01 0000 [.text] __ZN22AMDVIPM4ComputeChannel19eventWriteCmdPacketEP19PM4_MEC_EVENT_WRITE32MEC_EVENT_WRITE_event_index_enumj 0000000000091dce g 0f SECT 01 0000 [.text] __ZN22AMDVIPM4ComputeChannel19releaseMemCmdPacketEP19PM4_MEC_RELEASE_MEMj32MEC_RELEASE_MEM_event_index_enum33MEC_RELEASE_MEM_cache_policy_enum28MEC_RELEASE_MEM_dst_sel_enum28MEC_RELEASE_MEM_int_sel_enum29MEC_RELEASE_MEM_data_sel_enumyy 0000000000091fa2 g 0f SECT 01 0000 [.text] __ZN22AMDVIPM4ComputeChannel19releaseSubmitFramesEv 0000000000091e9a g 0f SECT 01 0000 [.text] __ZN22AMDVIPM4ComputeChannel22initializeSubmitFramesEv 0000000000091fde g 0f SECT 01 0000 [.text] __ZN22AMDVIPM4ComputeChannel22timeStampInterruptTypeEv 00000000000920b8 g 0f SECT 01 0000 [.text] __ZN22AMDVIPM4ComputeChannel22writeEventWriteCommandEPjjj 0000000000091bcc g 0f SECT 01 0000 [.text] __ZN22AMDVIPM4ComputeChannel23indirectBufferCmdPacketEP23PM4_MEC_INDIRECT_BUFFERyjjb 000000000009209a g 0f SECT 01 0000 [.text] __ZN22AMDVIPM4ComputeChannel23writeSurfaceSyncCommandEPjjyyj 0000000000091edc g 0f SECT 01 0000 [.text] __ZN22AMDVIPM4ComputeChannel24initializeTimestampFrameEv 00000000000920f6 g 0f SECT 01 0000 [.text] __ZN22AMDVIPM4ComputeChannel25writeEventWriteEOPCommandEPjjjyjjy 0000000000091a94 g 0f SECT 01 0000 [.text] __ZN22AMDVIPM4ComputeChannel27commitIndirectCommandBufferEP30AMD_SUBMIT_COMMAND_BUFFER_INFO 0000000000091c62 g 0f SECT 01 0000 [.text] __ZN22AMDVIPM4ComputeChannel36initializeIndirectCommandBufferFrameEv 00000000000917d0 g 0f SECT 01 0000 [.text] __ZN22AMDVIPM4ComputeChannel48writeFlushAndInvalidateDestinationCachesCommandsEv 00000000000917be g 0f SECT 01 0000 [.text] __ZN22AMDVIPM4ComputeChannel4freeEv 00000000000917a2 g 0f SECT 01 0000 [.text] __ZN22AMDVIPM4ComputeChannel4initEiP30AMDRadeonX4000_IAMDHWInterfaceP27AMDRadeonX4000_IAMDHWEngineP25AMDRadeonX4000_IAMDHWRingPKc 0000000000091610 g 0f SECT 01 0000 [.text] __ZN22AMDVIPM4ComputeChannel9MetaClassC1Ev 00000000000916d0 g 0f SECT 01 0000 [.text] __ZN22AMDVIPM4ComputeChannel9MetaClassC2Ev 00000000003bc720 g 0f SECT 08 0000 [.const_data] __ZN22AMDVIPM4ComputeChannel9metaClassE 000000000009166c g 0f SECT 01 0000 [.text] __ZN22AMDVIPM4ComputeChannelC1EPK11OSMetaClass 0000000000091742 g 0f SECT 01 0000 [.text] __ZN22AMDVIPM4ComputeChannelC1Ev 000000000009164c g 0f SECT 01 0000 [.text] __ZN22AMDVIPM4ComputeChannelC2EPK11OSMetaClass 0000000000091772 g 0f SECT 01 0000 [.text] __ZN22AMDVIPM4ComputeChannelC2Ev 00000000000916a0 g 0f SECT 01 0000 [.text] __ZN22AMDVIPM4ComputeChannelD0Ev 0000000000091696 g 0f SECT 01 0000 [.text] __ZN22AMDVIPM4ComputeChannelD1Ev 000000000009168c g 0f SECT 01 0000 [.text] __ZN22AMDVIPM4ComputeChannelD2Ev 000000000052e620 g 0f SECT 0a 0000 [__DATA.__common] __ZN23AMDCIPM4CommandsUtility10gMetaClassE 00000000003b46a8 g 0f SECT 08 0000 [.const_data] __ZN23AMDCIPM4CommandsUtility10superClassE 000000000007abc2 g 0f SECT 01 0000 [.text] __ZN23AMDCIPM4CommandsUtility16buildPM4Type0CmdEPjjj 000000000007ae74 g 0f SECT 01 0000 [.text] __ZN23AMDCIPM4CommandsUtility20buildMemWriteCommandEPjyjj 000000000007ae7c g 0f SECT 01 0000 [.text] __ZN23AMDCIPM4CommandsUtility21buildPFPSyncMECommandEPj 000000000007abd2 g 0f SECT 01 0000 [.text] __ZN23AMDCIPM4CommandsUtility22buildWaitRegMemCommandEPjjjjjjj 000000000007abca g 0f SECT 01 0000 [.text] __ZN23AMDCIPM4CommandsUtility22writePM4Type0CmdToRingEP25AMDRadeonX4000_IAMDHWRingjj 000000000007ac54 g 0f SECT 01 0000 [.text] __ZN23AMDCIPM4CommandsUtility23buildSurfaceSyncCommandEPjjj 000000000007ad1c g 0f SECT 01 0000 [.text] __ZN23AMDCIPM4CommandsUtility25buildEventWriteEOPCommandEPjjyyjbj 000000000007add6 g 0f SECT 01 0000 [.text] __ZN23AMDCIPM4CommandsUtility26buildIndirectBufferCommandEPjyj26_eAMD_INDIRECT_BUFFER_TYPEjbj 000000000007aca4 g 0f SECT 01 0000 [.text] __ZN23AMDCIPM4CommandsUtility29writeSurfaceSyncCommandToRingEP25AMDRadeonX4000_IAMDHWRingj 000000000007aa30 g 0f SECT 01 0000 [.text] __ZN23AMDCIPM4CommandsUtility9MetaClassC1Ev 000000000007aaf0 g 0f SECT 01 0000 [.text] __ZN23AMDCIPM4CommandsUtility9MetaClassC2Ev 00000000003b46a0 g 0f SECT 08 0000 [.const_data] __ZN23AMDCIPM4CommandsUtility9metaClassE 000000000007aa8c g 0f SECT 01 0000 [.text] __ZN23AMDCIPM4CommandsUtilityC1EPK11OSMetaClass 000000000007ab62 g 0f SECT 01 0000 [.text] __ZN23AMDCIPM4CommandsUtilityC1Ev 000000000007aa6c g 0f SECT 01 0000 [.text] __ZN23AMDCIPM4CommandsUtilityC2EPK11OSMetaClass 000000000007ab92 g 0f SECT 01 0000 [.text] __ZN23AMDCIPM4CommandsUtilityC2Ev 000000000007aac0 g 0f SECT 01 0000 [.text] __ZN23AMDCIPM4CommandsUtilityD0Ev 000000000007aab6 g 0f SECT 01 0000 [.text] __ZN23AMDCIPM4CommandsUtilityD1Ev 000000000007aaac g 0f SECT 01 0000 [.text] __ZN23AMDCIPM4CommandsUtilityD2Ev 0000000000059476 g 0f SECT 01 0000 [.text] __ZN23AMDRadeonX4000_AMDHWVMM10allocVMPTBEP16GLKMemoryElement 0000000000059590 g 0f SECT 01 0000 [.text] __ZN23AMDRadeonX4000_AMDHWVMM10assignVMIDEP30AMDRadeonX4000_IAMDHWVMContextRjP28AMDRadeonX4000_IAMDHWChannelPP12IOAccelEventPb 000000000052de50 g 0f SECT 0a 0000 [__DATA.__common] __ZN23AMDRadeonX4000_AMDHWVMM10gMetaClassE 00000000003a7c28 g 0f SECT 08 0000 [.const_data] __ZN23AMDRadeonX4000_AMDHWVMM10superClassE 000000000005978e g 0f SECT 01 0000 [.text] __ZN23AMDRadeonX4000_AMDHWVMM14getCurrentVMIDEP30AMDRadeonX4000_IAMDHWVMContext 00000000000597d0 g 0f SECT 01 0000 [.text] __ZN23AMDRadeonX4000_AMDHWVMM15createVMContextEv 0000000000059842 g 0f SECT 01 0000 [.text] __ZN23AMDRadeonX4000_AMDHWVMM16releaseVMContextEP30AMDRadeonX4000_IAMDHWVMContext 00000000000597b0 g 0f SECT 01 0000 [.text] __ZN23AMDRadeonX4000_AMDHWVMM18isInVMReservedPoolEy 0000000000059338 g 0f SECT 01 0000 [.text] __ZN23AMDRadeonX4000_AMDHWVMM18removeFromVMIDListEP30AMDRadeonX4000_IAMDHWVMContext 0000000000058f84 g 0f SECT 01 0000 [.text] __ZN23AMDRadeonX4000_AMDHWVMM20setVirtualSpaceReadyEb 0000000000058fcc g 0f SECT 01 0000 [.text] __ZN23AMDRadeonX4000_AMDHWVMM27setMemoryAllocationsEnabledEb 0000000000058eb0 g 0f SECT 01 0000 [.text] __ZN23AMDRadeonX4000_AMDHWVMM4freeEv 0000000000058d3a g 0f SECT 01 0000 [.text] __ZN23AMDRadeonX4000_AMDHWVMM4initEP30AMDRadeonX4000_IAMDHWInterface 0000000000059420 g 0f SECT 01 0000 [.text] __ZN23AMDRadeonX4000_AMDHWVMM8freeVMPDEP16GLKMemoryElement 0000000000058c60 g 0f SECT 01 0000 [.text] __ZN23AMDRadeonX4000_AMDHWVMM9MetaClassC1Ev 0000000000058d00 g 0f SECT 01 0000 [.text] __ZN23AMDRadeonX4000_AMDHWVMM9MetaClassC2Ev 000000000005935c g 0f SECT 01 0000 [.text] __ZN23AMDRadeonX4000_AMDHWVMM9allocVMPDEP16GLKMemoryElement 000000000005953a g 0f SECT 01 0000 [.text] __ZN23AMDRadeonX4000_AMDHWVMM9freeVMPTBEP16GLKMemoryElement 00000000003a7c20 g 0f SECT 08 0000 [.const_data] __ZN23AMDRadeonX4000_AMDHWVMM9metaClassE 0000000000058c9c g 0f SECT 01 0000 [.text] __ZN23AMDRadeonX4000_AMDHWVMMC2EPK11OSMetaClass 0000000000058cd0 g 0f SECT 01 0000 [.text] __ZN23AMDRadeonX4000_AMDHWVMMD0Ev 0000000000058cc6 g 0f SECT 01 0000 [.text] __ZN23AMDRadeonX4000_AMDHWVMMD1Ev 0000000000058cbc g 0f SECT 01 0000 [.text] __ZN23AMDRadeonX4000_AMDHWVMMD2Ev 000000000052f110 g 0f SECT 0a 0000 [__DATA.__common] __ZN23AMDRadeonX4000_AMDSIDRM10gMetaClassE 00000000003c3a88 g 0f SECT 08 0000 [.const_data] __ZN23AMDRadeonX4000_AMDSIDRM10superClassE 00000000001284a2 g 0f SECT 01 0000 [.text] __ZN23AMDRadeonX4000_AMDSIDRM11writeAESCmdEPjS0_yyjP11_DRMDMA_AESj 00000000001288e8 g 0f SECT 01 0000 [.text] __ZN23AMDRadeonX4000_AMDSIDRM12writeCBCCmdsEPjjyyjP11_DRMDMA_AESb 00000000001286cc g 0f SECT 01 0000 [.text] __ZN23AMDRadeonX4000_AMDSIDRM12writeCTRCmdsEPjjyyjP11_DRMDMA_AESb 0000000000128b04 g 0f SECT 01 0000 [.text] __ZN23AMDRadeonX4000_AMDSIDRM15writeCBCCTRCmdsEPjjyyjP11_DRMDMA_AES 0000000000128490 g 0f SECT 01 0000 [.text] __ZN23AMDRadeonX4000_AMDSIDRM4freeEv 0000000000128462 g 0f SECT 01 0000 [.text] __ZN23AMDRadeonX4000_AMDSIDRM4initEv 00000000001282d0 g 0f SECT 01 0000 [.text] __ZN23AMDRadeonX4000_AMDSIDRM9MetaClassC1Ev 0000000000128390 g 0f SECT 01 0000 [.text] __ZN23AMDRadeonX4000_AMDSIDRM9MetaClassC2Ev 00000000003c3a80 g 0f SECT 08 0000 [.const_data] __ZN23AMDRadeonX4000_AMDSIDRM9metaClassE 000000000012832c g 0f SECT 01 0000 [.text] __ZN23AMDRadeonX4000_AMDSIDRMC1EPK11OSMetaClass 0000000000128402 g 0f SECT 01 0000 [.text] __ZN23AMDRadeonX4000_AMDSIDRMC1Ev 000000000012830c g 0f SECT 01 0000 [.text] __ZN23AMDRadeonX4000_AMDSIDRMC2EPK11OSMetaClass 0000000000128432 g 0f SECT 01 0000 [.text] __ZN23AMDRadeonX4000_AMDSIDRMC2Ev 0000000000128360 g 0f SECT 01 0000 [.text] __ZN23AMDRadeonX4000_AMDSIDRMD0Ev 0000000000128356 g 0f SECT 01 0000 [.text] __ZN23AMDRadeonX4000_AMDSIDRMD1Ev 000000000012834c g 0f SECT 01 0000 [.text] __ZN23AMDRadeonX4000_AMDSIDRMD2Ev 000000000052f138 g 0f SECT 0a 0000 [__DATA.__common] __ZN23AMDRadeonX4000_AMDSISPU10gMetaClassE 0000000000128eda g 0f SECT 01 0000 [.text] __ZN23AMDRadeonX4000_AMDSISPU10getAppSizeE17_AMD_SPU_APP_TYPEPjS1_ 00000000003c3ce8 g 0f SECT 08 0000 [.const_data] __ZN23AMDRadeonX4000_AMDSISPU10superClassE 00000000001290f4 g 0f SECT 01 0000 [.text] __ZN23AMDRadeonX4000_AMDSISPU11writeAppCmdEP12_SML_SPU_CMDb 000000000012906a g 0f SECT 01 0000 [.text] __ZN23AMDRadeonX4000_AMDSISPU12writeInitCmdEP12_SML_SPU_CMD 000000000012922c g 0f SECT 01 0000 [.text] __ZN23AMDRadeonX4000_AMDSISPU14writeAppMsgCmdEP12_SML_SPU_CMD 0000000000128ecc g 0f SECT 01 0000 [.text] __ZN23AMDRadeonX4000_AMDSISPU15getFeedBackSizeEPj 0000000000128e66 g 0f SECT 01 0000 [.text] __ZN23AMDRadeonX4000_AMDSISPU15getKernelMemReqEPjS0_S0_ 0000000000128e54 g 0f SECT 01 0000 [.text] __ZN23AMDRadeonX4000_AMDSISPU4freeEv 0000000000128e42 g 0f SECT 01 0000 [.text] __ZN23AMDRadeonX4000_AMDSISPU4initEv 000000000012902c g 0f SECT 01 0000 [.text] __ZN23AMDRadeonX4000_AMDSISPU6getAppE17_AMD_SPU_APP_TYPEPjS1_ 0000000000128cb0 g 0f SECT 01 0000 [.text] __ZN23AMDRadeonX4000_AMDSISPU9MetaClassC1Ev 0000000000128d70 g 0f SECT 01 0000 [.text] __ZN23AMDRadeonX4000_AMDSISPU9MetaClassC2Ev 0000000000128f02 g 0f SECT 01 0000 [.text] __ZN23AMDRadeonX4000_AMDSISPU9getAppMsgE17_AMD_SPU_MSG_TYPE 0000000000128e80 g 0f SECT 01 0000 [.text] __ZN23AMDRadeonX4000_AMDSISPU9getKernelEPjS0_S0_S0_ 00000000003c3ce0 g 0f SECT 08 0000 [.const_data] __ZN23AMDRadeonX4000_AMDSISPU9metaClassE 0000000000128d0c g 0f SECT 01 0000 [.text] __ZN23AMDRadeonX4000_AMDSISPUC1EPK11OSMetaClass 0000000000128de2 g 0f SECT 01 0000 [.text] __ZN23AMDRadeonX4000_AMDSISPUC1Ev 0000000000128cec g 0f SECT 01 0000 [.text] __ZN23AMDRadeonX4000_AMDSISPUC2EPK11OSMetaClass 0000000000128e12 g 0f SECT 01 0000 [.text] __ZN23AMDRadeonX4000_AMDSISPUC2Ev 0000000000128d40 g 0f SECT 01 0000 [.text] __ZN23AMDRadeonX4000_AMDSISPUD0Ev 0000000000128d36 g 0f SECT 01 0000 [.text] __ZN23AMDRadeonX4000_AMDSISPUD1Ev 0000000000128d2c g 0f SECT 01 0000 [.text] __ZN23AMDRadeonX4000_AMDSISPUD2Ev 000000000052f160 g 0f SECT 0a 0000 [__DATA.__common] __ZN23AMDRadeonX4000_AMDSIVCE10gMetaClassE 0000000000129630 g 0f SECT 01 0000 [.text] __ZN23AMDRadeonX4000_AMDSIVCE10roundupValEjj 00000000003c3f78 g 0f SECT 08 0000 [.const_data] __ZN23AMDRadeonX4000_AMDSIVCE10superClassE 00000000001295fc g 0f SECT 01 0000 [.text] __ZN23AMDRadeonX4000_AMDSIVCE11getFWMemReqEPjS0_ 0000000000129660 g 0f SECT 01 0000 [.text] __ZN23AMDRadeonX4000_AMDSIVCE14getFWCacheInfoEP14_SML_VCEFWINFO 000000000012964c g 0f SECT 01 0000 [.text] __ZN23AMDRadeonX4000_AMDSIVCE14getFWMemConfigEPjS0_ 00000000001295ea g 0f SECT 01 0000 [.text] __ZN23AMDRadeonX4000_AMDSIVCE4freeEv 0000000000129582 g 0f SECT 01 0000 [.text] __ZN23AMDRadeonX4000_AMDSIVCE4initEj 000000000012969c g 0f SECT 01 0000 [.text] __ZN23AMDRadeonX4000_AMDSIVCE5getFWEP10_SML_VCEFW 00000000001293f0 g 0f SECT 01 0000 [.text] __ZN23AMDRadeonX4000_AMDSIVCE9MetaClassC1Ev 00000000001294b0 g 0f SECT 01 0000 [.text] __ZN23AMDRadeonX4000_AMDSIVCE9MetaClassC2Ev 00000000003c3f70 g 0f SECT 08 0000 [.const_data] __ZN23AMDRadeonX4000_AMDSIVCE9metaClassE 000000000012944c g 0f SECT 01 0000 [.text] __ZN23AMDRadeonX4000_AMDSIVCEC1EPK11OSMetaClass 0000000000129522 g 0f SECT 01 0000 [.text] __ZN23AMDRadeonX4000_AMDSIVCEC1Ev 000000000012942c g 0f SECT 01 0000 [.text] __ZN23AMDRadeonX4000_AMDSIVCEC2EPK11OSMetaClass 0000000000129552 g 0f SECT 01 0000 [.text] __ZN23AMDRadeonX4000_AMDSIVCEC2Ev 0000000000129480 g 0f SECT 01 0000 [.text] __ZN23AMDRadeonX4000_AMDSIVCED0Ev 0000000000129476 g 0f SECT 01 0000 [.text] __ZN23AMDRadeonX4000_AMDSIVCED1Ev 000000000012946c g 0f SECT 01 0000 [.text] __ZN23AMDRadeonX4000_AMDSIVCED2Ev 000000000052f278 g 0f SECT 0a 0000 [__DATA.__common] __ZN23AMDRadeonX4000_AMDUVDVI10gMetaClassE 00000000003c52a8 g 0f SECT 08 0000 [.const_data] __ZN23AMDRadeonX4000_AMDUVDVI10superClassE 000000000012b8d2 g 0f SECT 01 0000 [.text] __ZN23AMDRadeonX4000_AMDUVDVI4initEj 000000000012b740 g 0f SECT 01 0000 [.text] __ZN23AMDRadeonX4000_AMDUVDVI9MetaClassC1Ev 000000000012b800 g 0f SECT 01 0000 [.text] __ZN23AMDRadeonX4000_AMDUVDVI9MetaClassC2Ev 00000000003c52a0 g 0f SECT 08 0000 [.const_data] __ZN23AMDRadeonX4000_AMDUVDVI9metaClassE 000000000012b79c g 0f SECT 01 0000 [.text] __ZN23AMDRadeonX4000_AMDUVDVIC1EPK11OSMetaClass 000000000012b872 g 0f SECT 01 0000 [.text] __ZN23AMDRadeonX4000_AMDUVDVIC1Ev 000000000012b77c g 0f SECT 01 0000 [.text] __ZN23AMDRadeonX4000_AMDUVDVIC2EPK11OSMetaClass 000000000012b8a2 g 0f SECT 01 0000 [.text] __ZN23AMDRadeonX4000_AMDUVDVIC2Ev 000000000012b7d0 g 0f SECT 01 0000 [.text] __ZN23AMDRadeonX4000_AMDUVDVID0Ev 000000000012b7c6 g 0f SECT 01 0000 [.text] __ZN23AMDRadeonX4000_AMDUVDVID1Ev 000000000012b7bc g 0f SECT 01 0000 [.text] __ZN23AMDRadeonX4000_AMDUVDVID2Ev 000000000052f2a0 g 0f SECT 0a 0000 [__DATA.__common] __ZN23AMDRadeonX4000_AMDVIDRM10gMetaClassE 00000000003c5528 g 0f SECT 08 0000 [.const_data] __ZN23AMDRadeonX4000_AMDVIDRM10superClassE 000000000012bb62 g 0f SECT 01 0000 [.text] __ZN23AMDRadeonX4000_AMDVIDRM11writeAESCmdEPjS0_yyjP11_DRMDMA_AESj 000000000012bfe4 g 0f SECT 01 0000 [.text] __ZN23AMDRadeonX4000_AMDVIDRM12writeCBCCmdsEPjjyyjP11_DRMDMA_AESb 000000000012bd72 g 0f SECT 01 0000 [.text] __ZN23AMDRadeonX4000_AMDVIDRM12writeCTRCmdsEPjjyyjP11_DRMDMA_AESb 000000000012c26a g 0f SECT 01 0000 [.text] __ZN23AMDRadeonX4000_AMDVIDRM15writeCBCCTRCmdsEPjjyyjP11_DRMDMA_AES 000000000012bb50 g 0f SECT 01 0000 [.text] __ZN23AMDRadeonX4000_AMDVIDRM4freeEv 000000000012bb22 g 0f SECT 01 0000 [.text] __ZN23AMDRadeonX4000_AMDVIDRM4initEv 000000000012b990 g 0f SECT 01 0000 [.text] __ZN23AMDRadeonX4000_AMDVIDRM9MetaClassC1Ev 000000000012ba50 g 0f SECT 01 0000 [.text] __ZN23AMDRadeonX4000_AMDVIDRM9MetaClassC2Ev 00000000003c5520 g 0f SECT 08 0000 [.const_data] __ZN23AMDRadeonX4000_AMDVIDRM9metaClassE 000000000012b9ec g 0f SECT 01 0000 [.text] __ZN23AMDRadeonX4000_AMDVIDRMC1EPK11OSMetaClass 000000000012bac2 g 0f SECT 01 0000 [.text] __ZN23AMDRadeonX4000_AMDVIDRMC1Ev 000000000012b9cc g 0f SECT 01 0000 [.text] __ZN23AMDRadeonX4000_AMDVIDRMC2EPK11OSMetaClass 000000000012baf2 g 0f SECT 01 0000 [.text] __ZN23AMDRadeonX4000_AMDVIDRMC2Ev 000000000012ba20 g 0f SECT 01 0000 [.text] __ZN23AMDRadeonX4000_AMDVIDRMD0Ev 000000000012ba16 g 0f SECT 01 0000 [.text] __ZN23AMDRadeonX4000_AMDVIDRMD1Ev 000000000012ba0c g 0f SECT 01 0000 [.text] __ZN23AMDRadeonX4000_AMDVIDRMD2Ev 000000000052f2c8 g 0f SECT 0a 0000 [__DATA.__common] __ZN23AMDRadeonX4000_AMDVISPU10gMetaClassE 00000000003c5788 g 0f SECT 08 0000 [.const_data] __ZN23AMDRadeonX4000_AMDVISPU10superClassE 000000000012c5b6 g 0f SECT 01 0000 [.text] __ZN23AMDRadeonX4000_AMDVISPU15getKernelMemReqEPjS0_S0_ 000000000012c5a4 g 0f SECT 01 0000 [.text] __ZN23AMDRadeonX4000_AMDVISPU4freeEv 000000000012c592 g 0f SECT 01 0000 [.text] __ZN23AMDRadeonX4000_AMDVISPU4initEv 000000000012c400 g 0f SECT 01 0000 [.text] __ZN23AMDRadeonX4000_AMDVISPU9MetaClassC1Ev 000000000012c4c0 g 0f SECT 01 0000 [.text] __ZN23AMDRadeonX4000_AMDVISPU9MetaClassC2Ev 000000000012c5d0 g 0f SECT 01 0000 [.text] __ZN23AMDRadeonX4000_AMDVISPU9getKernelEPjS0_S0_S0_ 00000000003c5780 g 0f SECT 08 0000 [.const_data] __ZN23AMDRadeonX4000_AMDVISPU9metaClassE 000000000012c45c g 0f SECT 01 0000 [.text] __ZN23AMDRadeonX4000_AMDVISPUC1EPK11OSMetaClass 000000000012c532 g 0f SECT 01 0000 [.text] __ZN23AMDRadeonX4000_AMDVISPUC1Ev 000000000012c43c g 0f SECT 01 0000 [.text] __ZN23AMDRadeonX4000_AMDVISPUC2EPK11OSMetaClass 000000000012c562 g 0f SECT 01 0000 [.text] __ZN23AMDRadeonX4000_AMDVISPUC2Ev 000000000012c490 g 0f SECT 01 0000 [.text] __ZN23AMDRadeonX4000_AMDVISPUD0Ev 000000000012c486 g 0f SECT 01 0000 [.text] __ZN23AMDRadeonX4000_AMDVISPUD1Ev 000000000012c47c g 0f SECT 01 0000 [.text] __ZN23AMDRadeonX4000_AMDVISPUD2Ev 000000000052f2f0 g 0f SECT 0a 0000 [__DATA.__common] __ZN23AMDRadeonX4000_AMDVIVCE10gMetaClassE 00000000003c5a18 g 0f SECT 08 0000 [.const_data] __ZN23AMDRadeonX4000_AMDVIVCE10superClassE 000000000012c874 g 0f SECT 01 0000 [.text] __ZN23AMDRadeonX4000_AMDVIVCE11getFWMemReqEPjS0_ 000000000012c8b2 g 0f SECT 01 0000 [.text] __ZN23AMDRadeonX4000_AMDVIVCE14getFWCacheInfoEP14_SML_VCEFWINFO 000000000012c89e g 0f SECT 01 0000 [.text] __ZN23AMDRadeonX4000_AMDVIVCE14getFWMemConfigEPjS0_ 000000000012c862 g 0f SECT 01 0000 [.text] __ZN23AMDRadeonX4000_AMDVIVCE4freeEv 000000000012c822 g 0f SECT 01 0000 [.text] __ZN23AMDRadeonX4000_AMDVIVCE4initEj 000000000012c690 g 0f SECT 01 0000 [.text] __ZN23AMDRadeonX4000_AMDVIVCE9MetaClassC1Ev 000000000012c750 g 0f SECT 01 0000 [.text] __ZN23AMDRadeonX4000_AMDVIVCE9MetaClassC2Ev 00000000003c5a10 g 0f SECT 08 0000 [.const_data] __ZN23AMDRadeonX4000_AMDVIVCE9metaClassE 000000000012c6ec g 0f SECT 01 0000 [.text] __ZN23AMDRadeonX4000_AMDVIVCEC1EPK11OSMetaClass 000000000012c7c2 g 0f SECT 01 0000 [.text] __ZN23AMDRadeonX4000_AMDVIVCEC1Ev 000000000012c6cc g 0f SECT 01 0000 [.text] __ZN23AMDRadeonX4000_AMDVIVCEC2EPK11OSMetaClass 000000000012c7f2 g 0f SECT 01 0000 [.text] __ZN23AMDRadeonX4000_AMDVIVCEC2Ev 000000000012c720 g 0f SECT 01 0000 [.text] __ZN23AMDRadeonX4000_AMDVIVCED0Ev 000000000012c716 g 0f SECT 01 0000 [.text] __ZN23AMDRadeonX4000_AMDVIVCED1Ev 000000000012c70c g 0f SECT 01 0000 [.text] __ZN23AMDRadeonX4000_AMDVIVCED2Ev 000000000052eb48 g 0f SECT 0a 0000 [__DATA.__common] __ZN23AMDVIPM4CommandsUtility10gMetaClassE 00000000003bc0d8 g 0f SECT 08 0000 [.const_data] __ZN23AMDVIPM4CommandsUtility10superClassE 000000000008f0a4 g 0f SECT 01 0000 [.text] __ZN23AMDVIPM4CommandsUtility16buildPM4Type0CmdEPjjj 000000000008f284 g 0f SECT 01 0000 [.text] __ZN23AMDVIPM4CommandsUtility20buildMemWriteCommandEPjyjj 000000000008f28c g 0f SECT 01 0000 [.text] __ZN23AMDVIPM4CommandsUtility21buildPFPSyncMECommandEPj 000000000008f0b4 g 0f SECT 01 0000 [.text] __ZN23AMDVIPM4CommandsUtility22buildWaitRegMemCommandEPjjjjjjj 000000000008f0ac g 0f SECT 01 0000 [.text] __ZN23AMDVIPM4CommandsUtility22writePM4Type0CmdToRingEP25AMDRadeonX4000_IAMDHWRingjj 000000000008f136 g 0f SECT 01 0000 [.text] __ZN23AMDVIPM4CommandsUtility23buildSurfaceSyncCommandEPjjj 000000000008f146 g 0f SECT 01 0000 [.text] __ZN23AMDVIPM4CommandsUtility25buildEventWriteEOPCommandEPjjyyjbj 000000000008f1f2 g 0f SECT 01 0000 [.text] __ZN23AMDVIPM4CommandsUtility26buildIndirectBufferCommandEPjyj26_eAMD_INDIRECT_BUFFER_TYPEjbj 000000000008f13e g 0f SECT 01 0000 [.text] __ZN23AMDVIPM4CommandsUtility29writeSurfaceSyncCommandToRingEP25AMDRadeonX4000_IAMDHWRingj 000000000008f092 g 0f SECT 01 0000 [.text] __ZN23AMDVIPM4CommandsUtility4initEv 000000000008ef00 g 0f SECT 01 0000 [.text] __ZN23AMDVIPM4CommandsUtility9MetaClassC1Ev 000000000008efc0 g 0f SECT 01 0000 [.text] __ZN23AMDVIPM4CommandsUtility9MetaClassC2Ev 00000000003bc0d0 g 0f SECT 08 0000 [.const_data] __ZN23AMDVIPM4CommandsUtility9metaClassE 000000000008ef5c g 0f SECT 01 0000 [.text] __ZN23AMDVIPM4CommandsUtilityC1EPK11OSMetaClass 000000000008f032 g 0f SECT 01 0000 [.text] __ZN23AMDVIPM4CommandsUtilityC1Ev 000000000008ef3c g 0f SECT 01 0000 [.text] __ZN23AMDVIPM4CommandsUtilityC2EPK11OSMetaClass 000000000008f062 g 0f SECT 01 0000 [.text] __ZN23AMDVIPM4CommandsUtilityC2Ev 000000000008ef90 g 0f SECT 01 0000 [.text] __ZN23AMDVIPM4CommandsUtilityD0Ev 000000000008ef86 g 0f SECT 01 0000 [.text] __ZN23AMDVIPM4CommandsUtilityD1Ev 000000000008ef7c g 0f SECT 01 0000 [.text] __ZN23AMDVIPM4CommandsUtilityD2Ev 000000000052d6f8 g 0f SECT 0a 0000 [__DATA.__common] __ZN24AMDCIGraphicsAccelerator10gMetaClassE 000000000003cf8c g 0f SECT 01 0000 [.text] __ZN24AMDCIGraphicsAccelerator10newSurfaceEv 000000000039ad98 g 0f SECT 08 0000 [.const_data] __ZN24AMDCIGraphicsAccelerator10superClassE 000000000003cfec g 0f SECT 01 0000 [.text] __ZN24AMDCIGraphicsAccelerator11newResourceEv 000000000003cf5c g 0f SECT 01 0000 [.text] __ZN24AMDCIGraphicsAccelerator12newCLContextEv 000000000003cf20 g 0f SECT 01 0000 [.text] __ZN24AMDCIGraphicsAccelerator12newGLContextEv 000000000003cfbc g 0f SECT 01 0000 [.text] __ZN24AMDCIGraphicsAccelerator15newVideoContextEv 000000000003cefa g 0f SECT 01 0000 [.text] __ZN24AMDCIGraphicsAccelerator17newDisplayMachineEv 000000000003d012 g 0f SECT 01 0000 [.text] __ZN24AMDCIGraphicsAccelerator21initCommandBufferPoolEP25IOAccelCommandBufferPool2P11IOAccelTaskP15IOAccelChannel2 000000000003ce20 g 0f SECT 01 0000 [.text] __ZN24AMDCIGraphicsAccelerator9MetaClassC1Ev 000000000003cec0 g 0f SECT 01 0000 [.text] __ZN24AMDCIGraphicsAccelerator9MetaClassC2Ev 000000000039ad90 g 0f SECT 08 0000 [.const_data] __ZN24AMDCIGraphicsAccelerator9metaClassE 000000000003ce5c g 0f SECT 01 0000 [.text] __ZN24AMDCIGraphicsAcceleratorC2EPK11OSMetaClass 000000000003ce90 g 0f SECT 01 0000 [.text] __ZN24AMDCIGraphicsAcceleratorD0Ev 000000000003ce86 g 0f SECT 01 0000 [.text] __ZN24AMDCIGraphicsAcceleratorD1Ev 000000000003ce7c g 0f SECT 01 0000 [.text] __ZN24AMDCIGraphicsAcceleratorD2Ev 000000000002363e g 0f SECT 01 0000 [.text] __ZN24AMDRadeonX4000_AMDBltMgr10FreeSysMemEPv 0000000000023834 g 0f SECT 01 0000 [.text] __ZN24AMDRadeonX4000_AMDBltMgr10FreeVidMemEPvS0_ 00000000000238ec g 0f SECT 01 0000 [.text] __ZN24AMDRadeonX4000_AMDBltMgr10LockVidMemEPvPK21_UBM_LOCKVIDMEM_INPUT 000000000052d1d8 g 0f SECT 0a 0000 [__DATA.__common] __ZN24AMDRadeonX4000_AMDBltMgr10gMetaClassE 0000000000390af8 g 0f SECT 08 0000 [.const_data] __ZN24AMDRadeonX4000_AMDBltMgr10superClassE 00000000000235f6 g 0f SECT 01 0000 [.text] __ZN24AMDRadeonX4000_AMDBltMgr11AllocSysMemEPK22_UBM_ALLOCSYSMEM_INPUT 0000000000023658 g 0f SECT 01 0000 [.text] __ZN24AMDRadeonX4000_AMDBltMgr11AllocVidMemEPvPK22_UBM_ALLOCVIDMEM_INPUTP23_UBM_ALLOCVIDMEM_OUTPUT 0000000000023aae g 0f SECT 01 0000 [.text] __ZN24AMDRadeonX4000_AMDBltMgr11GetCmdSpaceEPvj 0000000000023fda g 0f SECT 01 0000 [.text] __ZN24AMDRadeonX4000_AMDBltMgr11SurfaceCopyEP20_UBM_SURFACECOPYINFOP17_UBM_E_RETURNCODE 0000000000023996 g 0f SECT 01 0000 [.text] __ZN24AMDRadeonX4000_AMDBltMgr12UnlockVidMemEPvS0_ 0000000000024318 g 0f SECT 01 0000 [.text] __ZN24AMDRadeonX4000_AMDBltMgr12addPatchDataEjj 0000000000023a5e g 0f SECT 01 0000 [.text] __ZN24AMDRadeonX4000_AMDBltMgr13AddWideHandleEPvPK24_UBM_ADDWIDEHANDLE_INPUT 0000000000023acc g 0f SECT 01 0000 [.text] __ZN24AMDRadeonX4000_AMDBltMgr13GetCmdBufBaseEPv 0000000000024028 g 0f SECT 01 0000 [.text] __ZN24AMDRadeonX4000_AMDBltMgr13processHandleEPvbj19_VCOP_RESOURCE_TYPEjjS1_j 00000000000239ee g 0f SECT 01 0000 [.text] __ZN24AMDRadeonX4000_AMDBltMgr14VerifyCmdSpaceEPvPK25_UBM_VERIFYCMDSPACE_INPUT 0000000000023b7c g 0f SECT 01 0000 [.text] __ZN24AMDRadeonX4000_AMDBltMgr14clearPatchDataEv 0000000000023be2 g 0f SECT 01 0000 [.text] __ZN24AMDRadeonX4000_AMDBltMgr14clearStateInitEv 0000000000024422 g 0f SECT 01 0000 [.text] __ZN24AMDRadeonX4000_AMDBltMgr15releaseMappingsEP11IOAccelTask 00000000000243b8 g 0f SECT 01 0000 [.text] __ZN24AMDRadeonX4000_AMDBltMgr18patchCommandBufferEP15IOAccelChannel2 0000000000023ade g 0f SECT 01 0000 [.text] __ZN24AMDRadeonX4000_AMDBltMgr20GetCmdBufFreeEntriesEPv 0000000000023af2 g 0f SECT 01 0000 [.text] __ZN24AMDRadeonX4000_AMDBltMgr4freeEv 0000000000023222 g 0f SECT 01 0000 [.text] __ZN24AMDRadeonX4000_AMDBltMgr4initEP37AMDRadeonX4000_AMDGraphicsAccelerator 0000000000023d48 g 0f SECT 01 0000 [.text] __ZN24AMDRadeonX4000_AMDBltMgr5ClearEP14_UBM_CLEARINFOP17_UBM_E_RETURNCODE 0000000000023e3c g 0f SECT 01 0000 [.text] __ZN24AMDRadeonX4000_AMDBltMgr6ExpandEP15_UBM_EXPANDINFOP17_UBM_E_RETURNCODE 0000000000023f4c g 0f SECT 01 0000 [.text] __ZN24AMDRadeonX4000_AMDBltMgr6MemcpyEP15_UBM_MEMCPYINFOP17_UBM_E_RETURNCODE 0000000000023ed8 g 0f SECT 01 0000 [.text] __ZN24AMDRadeonX4000_AMDBltMgr6MemsetEP15_UBM_MEMSETINFOP17_UBM_E_RETURNCODE 0000000000023c7e g 0f SECT 01 0000 [.text] __ZN24AMDRadeonX4000_AMDBltMgr7StretchEP16_UBM_STRETCHINFOP17_UBM_E_RETURNCODE 0000000000023dee g 0f SECT 01 0000 [.text] __ZN24AMDRadeonX4000_AMDBltMgr9AAResolveEP18_UBM_AARESOLVEINFOP17_UBM_E_RETURNCODE 0000000000023a10 g 0f SECT 01 0000 [.text] __ZN24AMDRadeonX4000_AMDBltMgr9AddHandleEPvPK20_UBM_ADDHANDLE_INPUT 0000000000023090 g 0f SECT 01 0000 [.text] __ZN24AMDRadeonX4000_AMDBltMgr9MetaClassC1Ev 0000000000023150 g 0f SECT 01 0000 [.text] __ZN24AMDRadeonX4000_AMDBltMgr9MetaClassC2Ev 0000000000023c20 g 0f SECT 01 0000 [.text] __ZN24AMDRadeonX4000_AMDBltMgr9SetPM4BufEPjjjP11IOAccelTask 0000000000023e8a g 0f SECT 01 0000 [.text] __ZN24AMDRadeonX4000_AMDBltMgr9TileCBToZEP17_UBM_COMPRESSINFOP17_UBM_E_RETURNCODE 0000000000390af0 g 0f SECT 08 0000 [.const_data] __ZN24AMDRadeonX4000_AMDBltMgr9metaClassE 00000000000230ec g 0f SECT 01 0000 [.text] __ZN24AMDRadeonX4000_AMDBltMgrC1EPK11OSMetaClass 00000000000231c2 g 0f SECT 01 0000 [.text] __ZN24AMDRadeonX4000_AMDBltMgrC1Ev 00000000000230cc g 0f SECT 01 0000 [.text] __ZN24AMDRadeonX4000_AMDBltMgrC2EPK11OSMetaClass 00000000000231f2 g 0f SECT 01 0000 [.text] __ZN24AMDRadeonX4000_AMDBltMgrC2Ev 0000000000023120 g 0f SECT 01 0000 [.text] __ZN24AMDRadeonX4000_AMDBltMgrD0Ev 0000000000023116 g 0f SECT 01 0000 [.text] __ZN24AMDRadeonX4000_AMDBltMgrD1Ev 000000000002310c g 0f SECT 01 0000 [.text] __ZN24AMDRadeonX4000_AMDBltMgrD2Ev 000000000052f1d8 g 0f SECT 0a 0000 [__DATA.__common] __ZN24AMDRadeonX4000_AMDCIKDRM10gMetaClassE 00000000003c47f8 g 0f SECT 08 0000 [.const_data] __ZN24AMDRadeonX4000_AMDCIKDRM10superClassE 000000000012a102 g 0f SECT 01 0000 [.text] __ZN24AMDRadeonX4000_AMDCIKDRM11writeAESCmdEPjS0_yyjP11_DRMDMA_AESj 000000000012a584 g 0f SECT 01 0000 [.text] __ZN24AMDRadeonX4000_AMDCIKDRM12writeCBCCmdsEPjjyyjP11_DRMDMA_AESb 000000000012a312 g 0f SECT 01 0000 [.text] __ZN24AMDRadeonX4000_AMDCIKDRM12writeCTRCmdsEPjjyyjP11_DRMDMA_AESb 000000000012a80a g 0f SECT 01 0000 [.text] __ZN24AMDRadeonX4000_AMDCIKDRM15writeCBCCTRCmdsEPjjyyjP11_DRMDMA_AES 000000000012a0f0 g 0f SECT 01 0000 [.text] __ZN24AMDRadeonX4000_AMDCIKDRM4freeEv 000000000012a0c2 g 0f SECT 01 0000 [.text] __ZN24AMDRadeonX4000_AMDCIKDRM4initEv 0000000000129f30 g 0f SECT 01 0000 [.text] __ZN24AMDRadeonX4000_AMDCIKDRM9MetaClassC1Ev 0000000000129ff0 g 0f SECT 01 0000 [.text] __ZN24AMDRadeonX4000_AMDCIKDRM9MetaClassC2Ev 00000000003c47f0 g 0f SECT 08 0000 [.const_data] __ZN24AMDRadeonX4000_AMDCIKDRM9metaClassE 0000000000129f8c g 0f SECT 01 0000 [.text] __ZN24AMDRadeonX4000_AMDCIKDRMC1EPK11OSMetaClass 000000000012a062 g 0f SECT 01 0000 [.text] __ZN24AMDRadeonX4000_AMDCIKDRMC1Ev 0000000000129f6c g 0f SECT 01 0000 [.text] __ZN24AMDRadeonX4000_AMDCIKDRMC2EPK11OSMetaClass 000000000012a092 g 0f SECT 01 0000 [.text] __ZN24AMDRadeonX4000_AMDCIKDRMC2Ev 0000000000129fc0 g 0f SECT 01 0000 [.text] __ZN24AMDRadeonX4000_AMDCIKDRMD0Ev 0000000000129fb6 g 0f SECT 01 0000 [.text] __ZN24AMDRadeonX4000_AMDCIKDRMD1Ev 0000000000129fac g 0f SECT 01 0000 [.text] __ZN24AMDRadeonX4000_AMDCIKDRMD2Ev 000000000052f200 g 0f SECT 0a 0000 [__DATA.__common] __ZN24AMDRadeonX4000_AMDCIKSPU10gMetaClassE 000000000012ac04 g 0f SECT 01 0000 [.text] __ZN24AMDRadeonX4000_AMDCIKSPU10getAppSizeE17_AMD_SPU_APP_TYPEPjS1_ 00000000003c4a58 g 0f SECT 08 0000 [.const_data] __ZN24AMDRadeonX4000_AMDCIKSPU10superClassE 000000000012abca g 0f SECT 01 0000 [.text] __ZN24AMDRadeonX4000_AMDCIKSPU11getKappSizeEPjS0_ 000000000012adf6 g 0f SECT 01 0000 [.text] __ZN24AMDRadeonX4000_AMDCIKSPU11writeAppCmdEP12_SML_SPU_CMDb 000000000012ad6c g 0f SECT 01 0000 [.text] __ZN24AMDRadeonX4000_AMDCIKSPU12writeInitCmdEP12_SML_SPU_CMD 000000000012af2e g 0f SECT 01 0000 [.text] __ZN24AMDRadeonX4000_AMDCIKSPU14writeAppMsgCmdEP12_SML_SPU_CMD 000000000012abbc g 0f SECT 01 0000 [.text] __ZN24AMDRadeonX4000_AMDCIKSPU15getFeedBackSizeEPj 000000000012ab56 g 0f SECT 01 0000 [.text] __ZN24AMDRadeonX4000_AMDCIKSPU15getKernelMemReqEPjS0_S0_ 000000000012b080 g 0f SECT 01 0000 [.text] __ZN24AMDRadeonX4000_AMDCIKSPU22writeSetPremContentCmdEP15_SAMU_GPCOM_CMD 000000000012ab44 g 0f SECT 01 0000 [.text] __ZN24AMDRadeonX4000_AMDCIKSPU4freeEv 000000000012ab32 g 0f SECT 01 0000 [.text] __ZN24AMDRadeonX4000_AMDCIKSPU4initEv 000000000012ac24 g 0f SECT 01 0000 [.text] __ZN24AMDRadeonX4000_AMDCIKSPU6getAppE17_AMD_SPU_APP_TYPEPjS1_ 000000000012abde g 0f SECT 01 0000 [.text] __ZN24AMDRadeonX4000_AMDCIKSPU7getKappEPjS0_ 000000000012a9a0 g 0f SECT 01 0000 [.text] __ZN24AMDRadeonX4000_AMDCIKSPU9MetaClassC1Ev 000000000012aa60 g 0f SECT 01 0000 [.text] __ZN24AMDRadeonX4000_AMDCIKSPU9MetaClassC2Ev 000000000012ac60 g 0f SECT 01 0000 [.text] __ZN24AMDRadeonX4000_AMDCIKSPU9getAppMsgE17_AMD_SPU_MSG_TYPE 000000000012ab70 g 0f SECT 01 0000 [.text] __ZN24AMDRadeonX4000_AMDCIKSPU9getKernelEPjS0_S0_S0_ 00000000003c4a50 g 0f SECT 08 0000 [.const_data] __ZN24AMDRadeonX4000_AMDCIKSPU9metaClassE 000000000012a9fc g 0f SECT 01 0000 [.text] __ZN24AMDRadeonX4000_AMDCIKSPUC1EPK11OSMetaClass 000000000012aad2 g 0f SECT 01 0000 [.text] __ZN24AMDRadeonX4000_AMDCIKSPUC1Ev 000000000012a9dc g 0f SECT 01 0000 [.text] __ZN24AMDRadeonX4000_AMDCIKSPUC2EPK11OSMetaClass 000000000012ab02 g 0f SECT 01 0000 [.text] __ZN24AMDRadeonX4000_AMDCIKSPUC2Ev 000000000012aa30 g 0f SECT 01 0000 [.text] __ZN24AMDRadeonX4000_AMDCIKSPUD0Ev 000000000012aa26 g 0f SECT 01 0000 [.text] __ZN24AMDRadeonX4000_AMDCIKSPUD1Ev 000000000012aa1c g 0f SECT 01 0000 [.text] __ZN24AMDRadeonX4000_AMDCIKSPUD2Ev 000000000052f228 g 0f SECT 0a 0000 [__DATA.__common] __ZN24AMDRadeonX4000_AMDCIKVCE10gMetaClassE 00000000003c4ce8 g 0f SECT 08 0000 [.const_data] __ZN24AMDRadeonX4000_AMDCIKVCE10superClassE 000000000012b34e g 0f SECT 01 0000 [.text] __ZN24AMDRadeonX4000_AMDCIKVCE11getFWMemReqEPjS0_ 000000000012b384 g 0f SECT 01 0000 [.text] __ZN24AMDRadeonX4000_AMDCIKVCE14getFWCacheInfoEP14_SML_VCEFWINFO 000000000012b370 g 0f SECT 01 0000 [.text] __ZN24AMDRadeonX4000_AMDCIKVCE14getFWMemConfigEPjS0_ 000000000012b33c g 0f SECT 01 0000 [.text] __ZN24AMDRadeonX4000_AMDCIKVCE4freeEv 000000000012b302 g 0f SECT 01 0000 [.text] __ZN24AMDRadeonX4000_AMDCIKVCE4initEj 000000000012b170 g 0f SECT 01 0000 [.text] __ZN24AMDRadeonX4000_AMDCIKVCE9MetaClassC1Ev 000000000012b230 g 0f SECT 01 0000 [.text] __ZN24AMDRadeonX4000_AMDCIKVCE9MetaClassC2Ev 00000000003c4ce0 g 0f SECT 08 0000 [.const_data] __ZN24AMDRadeonX4000_AMDCIKVCE9metaClassE 000000000012b1cc g 0f SECT 01 0000 [.text] __ZN24AMDRadeonX4000_AMDCIKVCEC1EPK11OSMetaClass 000000000012b2a2 g 0f SECT 01 0000 [.text] __ZN24AMDRadeonX4000_AMDCIKVCEC1Ev 000000000012b1ac g 0f SECT 01 0000 [.text] __ZN24AMDRadeonX4000_AMDCIKVCEC2EPK11OSMetaClass 000000000012b2d2 g 0f SECT 01 0000 [.text] __ZN24AMDRadeonX4000_AMDCIKVCEC2Ev 000000000012b200 g 0f SECT 01 0000 [.text] __ZN24AMDRadeonX4000_AMDCIKVCED0Ev 000000000012b1f6 g 0f SECT 01 0000 [.text] __ZN24AMDRadeonX4000_AMDCIKVCED1Ev 000000000012b1ec g 0f SECT 01 0000 [.text] __ZN24AMDRadeonX4000_AMDCIKVCED2Ev 000000000052da40 g 0f SECT 0a 0000 [__DATA.__common] __ZN24AMDRadeonX4000_AMDHWGart10gMetaClassE 00000000003a3068 g 0f SECT 08 0000 [.const_data] __ZN24AMDRadeonX4000_AMDHWGart10superClassE 0000000000051fa0 g 0f SECT 01 0000 [.text] __ZN24AMDRadeonX4000_AMDHWGart13mapGartMemoryEv 00000000000515ea g 0f SECT 01 0000 [.text] __ZN24AMDRadeonX4000_AMDHWGart13setParametersEP16_GART_PARAMETERS 0000000000051e38 g 0f SECT 01 0000 [.text] __ZN24AMDRadeonX4000_AMDHWGart14clearPageTableEyy 000000000005208c g 0f SECT 01 0000 [.text] __ZN24AMDRadeonX4000_AMDHWGart15unmapGartMemoryEv 0000000000051b1a g 0f SECT 01 0000 [.text] __ZN24AMDRadeonX4000_AMDHWGart15updatePageTableEP18IOMemoryDescriptory15_eOP_ORIGINATOR9_eOP_TYPEbb 0000000000052342 g 0f SECT 01 0000 [.text] __ZN24AMDRadeonX4000_AMDHWGart20setVirtualSpaceReadyEb 00000000000516fc g 0f SECT 01 0000 [.text] __ZN24AMDRadeonX4000_AMDHWGart24fillMemoryWithEmptyValueEPyyj 0000000000051de4 g 0f SECT 01 0000 [.text] __ZN24AMDRadeonX4000_AMDHWGart24flushAndInvalidateCachesEj 0000000000052360 g 0f SECT 01 0000 [.text] __ZN24AMDRadeonX4000_AMDHWGart27setMemoryAllocationsEnabledEb 00000000000520d4 g 0f SECT 01 0000 [.text] __ZN24AMDRadeonX4000_AMDHWGart3addEP18IOMemoryDescriptorPyj15_eOP_ORIGINATOR9_eOP_TYPEbb 000000000005172c g 0f SECT 01 0000 [.text] __ZN24AMDRadeonX4000_AMDHWGart4freeEv 0000000000051a22 g 0f SECT 01 0000 [.text] __ZN24AMDRadeonX4000_AMDHWGart4freeEyy 0000000000051442 g 0f SECT 01 0000 [.text] __ZN24AMDRadeonX4000_AMDHWGart4initEP30AMDRadeonX4000_IAMDHWInterfaceP16_GART_PARAMETERS 00000000000522de g 0f SECT 01 0000 [.text] __ZN24AMDRadeonX4000_AMDHWGart5clearEy 0000000000052446 g 0f SECT 01 0000 [.text] __ZN24AMDRadeonX4000_AMDHWGart6pageOnEv 00000000000521dc g 0f SECT 01 0000 [.text] __ZN24AMDRadeonX4000_AMDHWGart6removeEP18IOMemoryDescriptory 0000000000052410 g 0f SECT 01 0000 [.text] __ZN24AMDRadeonX4000_AMDHWGart7pageOffEv 0000000000052268 g 0f SECT 01 0000 [.text] __ZN24AMDRadeonX4000_AMDHWGart7reserveEy 00000000000518f4 g 0f SECT 01 0000 [.text] __ZN24AMDRadeonX4000_AMDHWGart7reserveEyy15_eOP_ORIGINATOR9_eOP_TYPE 00000000000517b6 g 0f SECT 01 0000 [.text] __ZN24AMDRadeonX4000_AMDHWGart8allocateERyyj15_eOP_ORIGINATOR9_eOP_TYPE 00000000000512b0 g 0f SECT 01 0000 [.text] __ZN24AMDRadeonX4000_AMDHWGart9MetaClassC1Ev 0000000000051370 g 0f SECT 01 0000 [.text] __ZN24AMDRadeonX4000_AMDHWGart9MetaClassC2Ev 00000000003a3060 g 0f SECT 08 0000 [.const_data] __ZN24AMDRadeonX4000_AMDHWGart9metaClassE 000000000005130c g 0f SECT 01 0000 [.text] __ZN24AMDRadeonX4000_AMDHWGartC1EPK11OSMetaClass 00000000000513e2 g 0f SECT 01 0000 [.text] __ZN24AMDRadeonX4000_AMDHWGartC1Ev 00000000000512ec g 0f SECT 01 0000 [.text] __ZN24AMDRadeonX4000_AMDHWGartC2EPK11OSMetaClass 0000000000051412 g 0f SECT 01 0000 [.text] __ZN24AMDRadeonX4000_AMDHWGartC2Ev 0000000000051340 g 0f SECT 01 0000 [.text] __ZN24AMDRadeonX4000_AMDHWGartD0Ev 0000000000051336 g 0f SECT 01 0000 [.text] __ZN24AMDRadeonX4000_AMDHWGartD1Ev 000000000005132c g 0f SECT 01 0000 [.text] __ZN24AMDRadeonX4000_AMDHWGartD2Ev 000000000052dd60 g 0f SECT 0a 0000 [__DATA.__common] __ZN24AMDRadeonX4000_AMDHWRing10gMetaClassE 0000000000055cba g 0f SECT 01 0000 [.text] __ZN24AMDRadeonX4000_AMDHWRing10initializeEP30AMDRadeonX4000_IAMDHWInterfaceRK13_HW_RING_INFOi20_eAMD_HW_ENGINE_TYPEj 00000000003a6c48 g 0f SECT 08 0000 [.const_data] __ZN24AMDRadeonX4000_AMDHWRing10superClassE 0000000000056050 g 0f SECT 01 0000 [.text] __ZN24AMDRadeonX4000_AMDHWRing12writeEntriesEPjj 0000000000055f3a g 0f SECT 01 0000 [.text] __ZN24AMDRadeonX4000_AMDHWRing13freeResourcesEv 0000000000055e12 g 0f SECT 01 0000 [.text] __ZN24AMDRadeonX4000_AMDHWRing17allocateResourcesEv 0000000000056200 g 0f SECT 01 0000 [.text] __ZN24AMDRadeonX4000_AMDHWRing17syncTailWritebackEv 00000000000560c8 g 0f SECT 01 0000 [.text] __ZN24AMDRadeonX4000_AMDHWRing18flushWithoutSubmitEv 000000000005622a g 0f SECT 01 0000 [.text] __ZN24AMDRadeonX4000_AMDHWRing20writeDiagnosisReportERPcRj 0000000000055dbc g 0f SECT 01 0000 [.text] __ZN24AMDRadeonX4000_AMDHWRing4freeEv 0000000000056032 g 0f SECT 01 0000 [.text] __ZN24AMDRadeonX4000_AMDHWRing5writeEj 0000000000055fb2 g 0f SECT 01 0000 [.text] __ZN24AMDRadeonX4000_AMDHWRing6enableEv 0000000000056160 g 0f SECT 01 0000 [.text] __ZN24AMDRadeonX4000_AMDHWRing6submitEv 0000000000055ffe g 0f SECT 01 0000 [.text] __ZN24AMDRadeonX4000_AMDHWRing7disableEv 0000000000055be0 g 0f SECT 01 0000 [.text] __ZN24AMDRadeonX4000_AMDHWRing9MetaClassC1Ev 0000000000055c80 g 0f SECT 01 0000 [.text] __ZN24AMDRadeonX4000_AMDHWRing9MetaClassC2Ev 00000000003a6c40 g 0f SECT 08 0000 [.const_data] __ZN24AMDRadeonX4000_AMDHWRing9metaClassE 000000000005608e g 0f SECT 01 0000 [.text] __ZN24AMDRadeonX4000_AMDHWRing9writeTailEv 0000000000055c1c g 0f SECT 01 0000 [.text] __ZN24AMDRadeonX4000_AMDHWRingC2EPK11OSMetaClass 0000000000055c50 g 0f SECT 01 0000 [.text] __ZN24AMDRadeonX4000_AMDHWRingD0Ev 0000000000055c46 g 0f SECT 01 0000 [.text] __ZN24AMDRadeonX4000_AMDHWRingD1Ev 0000000000055c3c g 0f SECT 01 0000 [.text] __ZN24AMDRadeonX4000_AMDHWRingD2Ev 000000000052eeb8 g 0f SECT 0a 0000 [__DATA.__common] __ZN24AMDRadeonX4000_AMDSMLDRM10gMetaClassE 00000000003c13d8 g 0f SECT 08 0000 [.const_data] __ZN24AMDRadeonX4000_AMDSMLDRM10superClassE 000000000012560e g 0f SECT 01 0000 [.text] __ZN24AMDRadeonX4000_AMDSMLDRM11writeAESCmdEPjS0_yyjP11_DRMDMA_AESj 00000000001255fc g 0f SECT 01 0000 [.text] __ZN24AMDRadeonX4000_AMDSMLDRM4freeEv 00000000001255ea g 0f SECT 01 0000 [.text] __ZN24AMDRadeonX4000_AMDSMLDRM4initEv 0000000000125616 g 0f SECT 01 0000 [.text] __ZN24AMDRadeonX4000_AMDSMLDRM8inc_cntrEPhj 00000000001254f0 g 0f SECT 01 0000 [.text] __ZN24AMDRadeonX4000_AMDSMLDRM9MetaClassC1Ev 00000000001255b0 g 0f SECT 01 0000 [.text] __ZN24AMDRadeonX4000_AMDSMLDRM9MetaClassC2Ev 00000000003c13d0 g 0f SECT 08 0000 [.const_data] __ZN24AMDRadeonX4000_AMDSMLDRM9metaClassE 000000000012554c g 0f SECT 01 0000 [.text] __ZN24AMDRadeonX4000_AMDSMLDRMC1EPK11OSMetaClass 000000000012552c g 0f SECT 01 0000 [.text] __ZN24AMDRadeonX4000_AMDSMLDRMC2EPK11OSMetaClass 0000000000125580 g 0f SECT 01 0000 [.text] __ZN24AMDRadeonX4000_AMDSMLDRMD0Ev 0000000000125576 g 0f SECT 01 0000 [.text] __ZN24AMDRadeonX4000_AMDSMLDRMD1Ev 000000000012556c g 0f SECT 01 0000 [.text] __ZN24AMDRadeonX4000_AMDSMLDRMD2Ev 000000000052eee0 g 0f SECT 0a 0000 [__DATA.__common] __ZN24AMDRadeonX4000_AMDSMLSPU10gMetaClassE 0000000000125896 g 0f SECT 01 0000 [.text] __ZN24AMDRadeonX4000_AMDSMLSPU10getAppSizeE17_AMD_SPU_APP_TYPEPjS1_ 00000000003c1618 g 0f SECT 08 0000 [.const_data] __ZN24AMDRadeonX4000_AMDSMLSPU10superClassE 0000000000125886 g 0f SECT 01 0000 [.text] __ZN24AMDRadeonX4000_AMDSMLSPU11getKappSizeEPjS0_ 00000000001258b6 g 0f SECT 01 0000 [.text] __ZN24AMDRadeonX4000_AMDSMLSPU11writeAppCmdEP12_SML_SPU_CMDb 00000000001258ae g 0f SECT 01 0000 [.text] __ZN24AMDRadeonX4000_AMDSMLSPU12writeInitCmdEP12_SML_SPU_CMD 00000000001258be g 0f SECT 01 0000 [.text] __ZN24AMDRadeonX4000_AMDSMLSPU14writeAppMsgCmdEP12_SML_SPU_CMD 000000000012587e g 0f SECT 01 0000 [.text] __ZN24AMDRadeonX4000_AMDSMLSPU15getFeedBackSizeEPj 000000000012586e g 0f SECT 01 0000 [.text] __ZN24AMDRadeonX4000_AMDSMLSPU15getKernelMemReqEPjS0_S0_ 000000000012585c g 0f SECT 01 0000 [.text] __ZN24AMDRadeonX4000_AMDSMLSPU4freeEv 000000000012584a g 0f SECT 01 0000 [.text] __ZN24AMDRadeonX4000_AMDSMLSPU4initEv 000000000012589e g 0f SECT 01 0000 [.text] __ZN24AMDRadeonX4000_AMDSMLSPU6getAppE17_AMD_SPU_APP_TYPEPjS1_ 000000000012588e g 0f SECT 01 0000 [.text] __ZN24AMDRadeonX4000_AMDSMLSPU7getKappEPjS0_ 0000000000125750 g 0f SECT 01 0000 [.text] __ZN24AMDRadeonX4000_AMDSMLSPU9MetaClassC1Ev 0000000000125810 g 0f SECT 01 0000 [.text] __ZN24AMDRadeonX4000_AMDSMLSPU9MetaClassC2Ev 00000000001258a6 g 0f SECT 01 0000 [.text] __ZN24AMDRadeonX4000_AMDSMLSPU9getAppMsgE17_AMD_SPU_MSG_TYPE 0000000000125876 g 0f SECT 01 0000 [.text] __ZN24AMDRadeonX4000_AMDSMLSPU9getKernelEPjS0_S0_S0_ 00000000003c1610 g 0f SECT 08 0000 [.const_data] __ZN24AMDRadeonX4000_AMDSMLSPU9metaClassE 00000000001257ac g 0f SECT 01 0000 [.text] __ZN24AMDRadeonX4000_AMDSMLSPUC1EPK11OSMetaClass 000000000012578c g 0f SECT 01 0000 [.text] __ZN24AMDRadeonX4000_AMDSMLSPUC2EPK11OSMetaClass 00000000001257e0 g 0f SECT 01 0000 [.text] __ZN24AMDRadeonX4000_AMDSMLSPUD0Ev 00000000001257d6 g 0f SECT 01 0000 [.text] __ZN24AMDRadeonX4000_AMDSMLSPUD1Ev 00000000001257cc g 0f SECT 01 0000 [.text] __ZN24AMDRadeonX4000_AMDSMLSPUD2Ev 000000000052ee90 g 0f SECT 0a 0000 [__DATA.__common] __ZN24AMDRadeonX4000_AMDSMLUVD10gMetaClassE 00000000003c1158 g 0f SECT 08 0000 [.const_data] __ZN24AMDRadeonX4000_AMDSMLUVD10superClassE 0000000000124e20 g 0f SECT 01 0000 [.text] __ZN24AMDRadeonX4000_AMDSMLUVD11getFWMemReqEPjS0_S0_ 0000000000124e40 g 0f SECT 01 0000 [.text] __ZN24AMDRadeonX4000_AMDSMLUVD14getFWCacheInfoEP14_SML_UVDFWInfo 0000000000125430 g 0f SECT 01 0000 [.text] __ZN24AMDRadeonX4000_AMDSMLUVD15writeDestroyMsgEjP12_SML_UVD_MSG 000000000012539c g 0f SECT 01 0000 [.text] __ZN24AMDRadeonX4000_AMDSMLUVD17writeUVDSaveStateEjP12_SML_UVD_MSG 00000000001253fc g 0f SECT 01 0000 [.text] __ZN24AMDRadeonX4000_AMDSMLUVD20writeUVDRestoreStateEjP12_SML_UVD_MSG 0000000000124e0e g 0f SECT 01 0000 [.text] __ZN24AMDRadeonX4000_AMDSMLUVD4freeEv 0000000000124dba g 0f SECT 01 0000 [.text] __ZN24AMDRadeonX4000_AMDSMLUVD4initEj 000000000012546c g 0f SECT 01 0000 [.text] __ZN24AMDRadeonX4000_AMDSMLUVD6doTestEjjj 0000000000124cc0 g 0f SECT 01 0000 [.text] __ZN24AMDRadeonX4000_AMDSMLUVD9MetaClassC1Ev 0000000000124d80 g 0f SECT 01 0000 [.text] __ZN24AMDRadeonX4000_AMDSMLUVD9MetaClassC2Ev 0000000000124e8a g 0f SECT 01 0000 [.text] __ZN24AMDRadeonX4000_AMDSMLUVD9loadUVDFWEP10_SML_UVDFW 00000000003c1150 g 0f SECT 08 0000 [.const_data] __ZN24AMDRadeonX4000_AMDSMLUVD9metaClassE 00000000001250d8 g 0f SECT 01 0000 [.text] __ZN24AMDRadeonX4000_AMDSMLUVD9prepUVDFWEP10_SML_UVDFW 0000000000124d1c g 0f SECT 01 0000 [.text] __ZN24AMDRadeonX4000_AMDSMLUVDC1EPK11OSMetaClass 0000000000124cfc g 0f SECT 01 0000 [.text] __ZN24AMDRadeonX4000_AMDSMLUVDC2EPK11OSMetaClass 0000000000124d50 g 0f SECT 01 0000 [.text] __ZN24AMDRadeonX4000_AMDSMLUVDD0Ev 0000000000124d46 g 0f SECT 01 0000 [.text] __ZN24AMDRadeonX4000_AMDSMLUVDD1Ev 0000000000124d3c g 0f SECT 01 0000 [.text] __ZN24AMDRadeonX4000_AMDSMLUVDD2Ev 000000000052ef30 g 0f SECT 0a 0000 [__DATA.__common] __ZN24AMDRadeonX4000_AMDSMLVCE10gMetaClassE 0000000000125fcc g 0f SECT 01 0000 [.text] __ZN24AMDRadeonX4000_AMDSMLVCE10getCmdSizeEPj17_SML_VCE_CMD_TYPE 00000000003c1b38 g 0f SECT 08 0000 [.const_data] __ZN24AMDRadeonX4000_AMDSMLVCE10superClassE 0000000000125da2 g 0f SECT 01 0000 [.text] __ZN24AMDRadeonX4000_AMDSMLVCE11getFWMemReqEPjS0_ 0000000000125db2 g 0f SECT 01 0000 [.text] __ZN24AMDRadeonX4000_AMDSMLVCE14getFWCacheInfoEP14_SML_VCEFWINFO 0000000000125daa g 0f SECT 01 0000 [.text] __ZN24AMDRadeonX4000_AMDSMLVCE14getFWMemConfigEPjS0_ 0000000000125e8e g 0f SECT 01 0000 [.text] __ZN24AMDRadeonX4000_AMDSMLVCE14writeCreateCmdEPjPv 0000000000125fee g 0f SECT 01 0000 [.text] __ZN24AMDRadeonX4000_AMDSMLVCE15getFeedbackSizeEPj 0000000000125fa0 g 0f SECT 01 0000 [.text] __ZN24AMDRadeonX4000_AMDSMLVCE15writeDestroyCmdEPjPv 0000000000125d90 g 0f SECT 01 0000 [.text] __ZN24AMDRadeonX4000_AMDSMLVCE4freeEv 0000000000125d5a g 0f SECT 01 0000 [.text] __ZN24AMDRadeonX4000_AMDSMLVCE4initEj 0000000000125dba g 0f SECT 01 0000 [.text] __ZN24AMDRadeonX4000_AMDSMLVCE5getFWEP10_SML_VCEFW 0000000000125e38 g 0f SECT 01 0000 [.text] __ZN24AMDRadeonX4000_AMDSMLVCE8writeCmdEPjS0_17_SML_VCE_CMD_TYPEPv 0000000000125c60 g 0f SECT 01 0000 [.text] __ZN24AMDRadeonX4000_AMDSMLVCE9MetaClassC1Ev 0000000000125d20 g 0f SECT 01 0000 [.text] __ZN24AMDRadeonX4000_AMDSMLVCE9MetaClassC2Ev 00000000003c1b30 g 0f SECT 08 0000 [.const_data] __ZN24AMDRadeonX4000_AMDSMLVCE9metaClassE 0000000000125cbc g 0f SECT 01 0000 [.text] __ZN24AMDRadeonX4000_AMDSMLVCEC1EPK11OSMetaClass 0000000000125c9c g 0f SECT 01 0000 [.text] __ZN24AMDRadeonX4000_AMDSMLVCEC2EPK11OSMetaClass 0000000000125cf0 g 0f SECT 01 0000 [.text] __ZN24AMDRadeonX4000_AMDSMLVCED0Ev 0000000000125ce6 g 0f SECT 01 0000 [.text] __ZN24AMDRadeonX4000_AMDSMLVCED1Ev 0000000000125cdc g 0f SECT 01 0000 [.text] __ZN24AMDRadeonX4000_AMDSMLVCED2Ev 000000000052f1b0 g 0f SECT 0a 0000 [__DATA.__common] __ZN24AMDRadeonX4000_AMDUVDCIK10gMetaClassE 00000000003c4578 g 0f SECT 08 0000 [.const_data] __ZN24AMDRadeonX4000_AMDUVDCIK10superClassE 0000000000129cb0 g 0f SECT 01 0000 [.text] __ZN24AMDRadeonX4000_AMDUVDCIK11getFWMemReqEPjS0_S0_ 0000000000129cd0 g 0f SECT 01 0000 [.text] __ZN24AMDRadeonX4000_AMDUVDCIK14getFWCacheInfoEP14_SML_UVDFWInfo 0000000000129c72 g 0f SECT 01 0000 [.text] __ZN24AMDRadeonX4000_AMDUVDCIK4initEj 0000000000129ae0 g 0f SECT 01 0000 [.text] __ZN24AMDRadeonX4000_AMDUVDCIK9MetaClassC1Ev 0000000000129ba0 g 0f SECT 01 0000 [.text] __ZN24AMDRadeonX4000_AMDUVDCIK9MetaClassC2Ev 0000000000129d1a g 0f SECT 01 0000 [.text] __ZN24AMDRadeonX4000_AMDUVDCIK9loadUVDFWEP10_SML_UVDFW 00000000003c4570 g 0f SECT 08 0000 [.const_data] __ZN24AMDRadeonX4000_AMDUVDCIK9metaClassE 0000000000129b3c g 0f SECT 01 0000 [.text] __ZN24AMDRadeonX4000_AMDUVDCIKC1EPK11OSMetaClass 0000000000129c12 g 0f SECT 01 0000 [.text] __ZN24AMDRadeonX4000_AMDUVDCIKC1Ev 0000000000129b1c g 0f SECT 01 0000 [.text] __ZN24AMDRadeonX4000_AMDUVDCIKC2EPK11OSMetaClass 0000000000129c42 g 0f SECT 01 0000 [.text] __ZN24AMDRadeonX4000_AMDUVDCIKC2Ev 0000000000129b70 g 0f SECT 01 0000 [.text] __ZN24AMDRadeonX4000_AMDUVDCIKD0Ev 0000000000129b66 g 0f SECT 01 0000 [.text] __ZN24AMDRadeonX4000_AMDUVDCIKD1Ev 0000000000129b5c g 0f SECT 01 0000 [.text] __ZN24AMDRadeonX4000_AMDUVDCIKD2Ev 000000000052dcc0 g 0f SECT 0a 0000 [__DATA.__common] __ZN24AMDRadeonX4000_IAMDHWVMM10gMetaClassE 00000000003a6070 g 0f SECT 08 0000 [.const_data] __ZN24AMDRadeonX4000_IAMDHWVMM10superClassE 0000000000053226 g 0f SECT 01 0000 [.text] __ZN24AMDRadeonX4000_IAMDHWVMM9MetaClassC1Ev 00000000000532c6 g 0f SECT 01 0000 [.text] __ZN24AMDRadeonX4000_IAMDHWVMM9MetaClassC2Ev 00000000003a6068 g 0f SECT 08 0000 [.const_data] __ZN24AMDRadeonX4000_IAMDHWVMM9metaClassE 0000000000053262 g 0f SECT 01 0000 [.text] __ZN24AMDRadeonX4000_IAMDHWVMMC2EPK11OSMetaClass 0000000000053296 g 0f SECT 01 0000 [.text] __ZN24AMDRadeonX4000_IAMDHWVMMD0Ev 000000000005328c g 0f SECT 01 0000 [.text] __ZN24AMDRadeonX4000_IAMDHWVMMD1Ev 0000000000053282 g 0f SECT 01 0000 [.text] __ZN24AMDRadeonX4000_IAMDHWVMMD2Ev 000000000052d540 g 0f SECT 0a 0000 [__DATA.__common] __ZN24AMDSIGraphicsAccelerator10gMetaClassE 000000000002900c g 0f SECT 01 0000 [.text] __ZN24AMDSIGraphicsAccelerator10newSurfaceEv 00000000003936d8 g 0f SECT 08 0000 [.const_data] __ZN24AMDSIGraphicsAccelerator10superClassE 000000000002906c g 0f SECT 01 0000 [.text] __ZN24AMDSIGraphicsAccelerator11newResourceEv 0000000000028fdc g 0f SECT 01 0000 [.text] __ZN24AMDSIGraphicsAccelerator12newCLContextEv 0000000000028fa0 g 0f SECT 01 0000 [.text] __ZN24AMDSIGraphicsAccelerator12newGLContextEv 000000000002903c g 0f SECT 01 0000 [.text] __ZN24AMDSIGraphicsAccelerator15newVideoContextEv 0000000000028f7a g 0f SECT 01 0000 [.text] __ZN24AMDSIGraphicsAccelerator17newDisplayMachineEv 0000000000029092 g 0f SECT 01 0000 [.text] __ZN24AMDSIGraphicsAccelerator21initCommandBufferPoolEP25IOAccelCommandBufferPool2P11IOAccelTaskP15IOAccelChannel2 0000000000028ea0 g 0f SECT 01 0000 [.text] __ZN24AMDSIGraphicsAccelerator9MetaClassC1Ev 0000000000028f40 g 0f SECT 01 0000 [.text] __ZN24AMDSIGraphicsAccelerator9MetaClassC2Ev 00000000003936d0 g 0f SECT 08 0000 [.const_data] __ZN24AMDSIGraphicsAccelerator9metaClassE 0000000000028edc g 0f SECT 01 0000 [.text] __ZN24AMDSIGraphicsAcceleratorC2EPK11OSMetaClass 0000000000028f10 g 0f SECT 01 0000 [.text] __ZN24AMDSIGraphicsAcceleratorD0Ev 0000000000028f06 g 0f SECT 01 0000 [.text] __ZN24AMDSIGraphicsAcceleratorD1Ev 0000000000028efc g 0f SECT 01 0000 [.text] __ZN24AMDSIGraphicsAcceleratorD2Ev 000000000052d7c0 g 0f SECT 0a 0000 [__DATA.__common] __ZN24AMDVIGraphicsAccelerator10gMetaClassE 00000000000467ec g 0f SECT 01 0000 [.text] __ZN24AMDVIGraphicsAccelerator10newSurfaceEv 000000000039e1c8 g 0f SECT 08 0000 [.const_data] __ZN24AMDVIGraphicsAccelerator10superClassE 000000000004684c g 0f SECT 01 0000 [.text] __ZN24AMDVIGraphicsAccelerator11newResourceEv 00000000000467bc g 0f SECT 01 0000 [.text] __ZN24AMDVIGraphicsAccelerator12newCLContextEv 0000000000046780 g 0f SECT 01 0000 [.text] __ZN24AMDVIGraphicsAccelerator12newGLContextEv 000000000004681c g 0f SECT 01 0000 [.text] __ZN24AMDVIGraphicsAccelerator15newVideoContextEv 000000000004675a g 0f SECT 01 0000 [.text] __ZN24AMDVIGraphicsAccelerator17newDisplayMachineEv 0000000000046872 g 0f SECT 01 0000 [.text] __ZN24AMDVIGraphicsAccelerator21initCommandBufferPoolEP25IOAccelCommandBufferPool2P11IOAccelTaskP15IOAccelChannel2 0000000000046680 g 0f SECT 01 0000 [.text] __ZN24AMDVIGraphicsAccelerator9MetaClassC1Ev 0000000000046720 g 0f SECT 01 0000 [.text] __ZN24AMDVIGraphicsAccelerator9MetaClassC2Ev 000000000039e1c0 g 0f SECT 08 0000 [.const_data] __ZN24AMDVIGraphicsAccelerator9metaClassE 00000000000466bc g 0f SECT 01 0000 [.text] __ZN24AMDVIGraphicsAcceleratorC2EPK11OSMetaClass 00000000000466f0 g 0f SECT 01 0000 [.text] __ZN24AMDVIGraphicsAcceleratorD0Ev 00000000000466e6 g 0f SECT 01 0000 [.text] __ZN24AMDVIGraphicsAcceleratorD1Ev 00000000000466dc g 0f SECT 01 0000 [.text] __ZN24AMDVIGraphicsAcceleratorD2Ev 000000000052de78 g 0f SECT 0a 0000 [__DATA.__common] __ZN25AMDRadeonX4000_AMDNULLVMM10gMetaClassE 00000000003a7f58 g 0f SECT 08 0000 [.const_data] __ZN25AMDRadeonX4000_AMDNULLVMM10superClassE 0000000000059a00 g 0f SECT 01 0000 [.text] __ZN25AMDRadeonX4000_AMDNULLVMM9MetaClassC1Ev 0000000000059ac0 g 0f SECT 01 0000 [.text] __ZN25AMDRadeonX4000_AMDNULLVMM9MetaClassC2Ev 00000000003a7f50 g 0f SECT 08 0000 [.const_data] __ZN25AMDRadeonX4000_AMDNULLVMM9metaClassE 0000000000059a5c g 0f SECT 01 0000 [.text] __ZN25AMDRadeonX4000_AMDNULLVMMC1EPK11OSMetaClass 0000000000059b32 g 0f SECT 01 0000 [.text] __ZN25AMDRadeonX4000_AMDNULLVMMC1Ev 0000000000059a3c g 0f SECT 01 0000 [.text] __ZN25AMDRadeonX4000_AMDNULLVMMC2EPK11OSMetaClass 0000000000059b62 g 0f SECT 01 0000 [.text] __ZN25AMDRadeonX4000_AMDNULLVMMC2Ev 0000000000059a90 g 0f SECT 01 0000 [.text] __ZN25AMDRadeonX4000_AMDNULLVMMD0Ev 0000000000059a86 g 0f SECT 01 0000 [.text] __ZN25AMDRadeonX4000_AMDNULLVMMD1Ev 0000000000059a7c g 0f SECT 01 0000 [.text] __ZN25AMDRadeonX4000_AMDNULLVMMD2Ev 000000000052db58 g 0f SECT 0a 0000 [__DATA.__common] __ZN25AMDRadeonX4000_IAMDHWGart10gMetaClassE 00000000003a4870 g 0f SECT 08 0000 [.const_data] __ZN25AMDRadeonX4000_IAMDHWGart10superClassE 0000000000052a7c g 0f SECT 01 0000 [.text] __ZN25AMDRadeonX4000_IAMDHWGart9MetaClassC1Ev 0000000000052b1c g 0f SECT 01 0000 [.text] __ZN25AMDRadeonX4000_IAMDHWGart9MetaClassC2Ev 00000000003a4868 g 0f SECT 08 0000 [.const_data] __ZN25AMDRadeonX4000_IAMDHWGart9metaClassE 0000000000052ab8 g 0f SECT 01 0000 [.text] __ZN25AMDRadeonX4000_IAMDHWGartC2EPK11OSMetaClass 0000000000052aec g 0f SECT 01 0000 [.text] __ZN25AMDRadeonX4000_IAMDHWGartD0Ev 0000000000052ae2 g 0f SECT 01 0000 [.text] __ZN25AMDRadeonX4000_IAMDHWGartD1Ev 0000000000052ad8 g 0f SECT 01 0000 [.text] __ZN25AMDRadeonX4000_IAMDHWGartD2Ev 000000000052db80 g 0f SECT 0a 0000 [__DATA.__common] __ZN25AMDRadeonX4000_IAMDHWRing10gMetaClassE 00000000003a4b20 g 0f SECT 08 0000 [.const_data] __ZN25AMDRadeonX4000_IAMDHWRing10superClassE 0000000000052b56 g 0f SECT 01 0000 [.text] __ZN25AMDRadeonX4000_IAMDHWRing9MetaClassC1Ev 0000000000052bf6 g 0f SECT 01 0000 [.text] __ZN25AMDRadeonX4000_IAMDHWRing9MetaClassC2Ev 00000000003a4b18 g 0f SECT 08 0000 [.const_data] __ZN25AMDRadeonX4000_IAMDHWRing9metaClassE 0000000000052b92 g 0f SECT 01 0000 [.text] __ZN25AMDRadeonX4000_IAMDHWRingC2EPK11OSMetaClass 0000000000052bc6 g 0f SECT 01 0000 [.text] __ZN25AMDRadeonX4000_IAMDHWRingD0Ev 0000000000052bbc g 0f SECT 01 0000 [.text] __ZN25AMDRadeonX4000_IAMDHWRingD1Ev 0000000000052bb2 g 0f SECT 01 0000 [.text] __ZN25AMDRadeonX4000_IAMDHWRingD2Ev 000000000052edc8 g 0f SECT 0a 0000 [__DATA.__common] __ZN25AMDRadeonX4000_IAMDSMLDRM10gMetaClassE 00000000003c0440 g 0f SECT 08 0000 [.const_data] __ZN25AMDRadeonX4000_IAMDSMLDRM10superClassE 0000000000123f9a g 0f SECT 01 0000 [.text] __ZN25AMDRadeonX4000_IAMDSMLDRM9MetaClassC1Ev 000000000012405a g 0f SECT 01 0000 [.text] __ZN25AMDRadeonX4000_IAMDSMLDRM9MetaClassC2Ev 00000000003c0438 g 0f SECT 08 0000 [.const_data] __ZN25AMDRadeonX4000_IAMDSMLDRM9metaClassE 0000000000123ff6 g 0f SECT 01 0000 [.text] __ZN25AMDRadeonX4000_IAMDSMLDRMC1EPK11OSMetaClass 0000000000123fd6 g 0f SECT 01 0000 [.text] __ZN25AMDRadeonX4000_IAMDSMLDRMC2EPK11OSMetaClass 000000000012402a g 0f SECT 01 0000 [.text] __ZN25AMDRadeonX4000_IAMDSMLDRMD0Ev 0000000000124020 g 0f SECT 01 0000 [.text] __ZN25AMDRadeonX4000_IAMDSMLDRMD1Ev 0000000000124016 g 0f SECT 01 0000 [.text] __ZN25AMDRadeonX4000_IAMDSMLDRMD2Ev 000000000052edf0 g 0f SECT 0a 0000 [__DATA.__common] __ZN25AMDRadeonX4000_IAMDSMLSPU10gMetaClassE 00000000003c0670 g 0f SECT 08 0000 [.const_data] __ZN25AMDRadeonX4000_IAMDSMLSPU10superClassE 0000000000124094 g 0f SECT 01 0000 [.text] __ZN25AMDRadeonX4000_IAMDSMLSPU9MetaClassC1Ev 0000000000124154 g 0f SECT 01 0000 [.text] __ZN25AMDRadeonX4000_IAMDSMLSPU9MetaClassC2Ev 00000000003c0668 g 0f SECT 08 0000 [.const_data] __ZN25AMDRadeonX4000_IAMDSMLSPU9metaClassE 00000000001240f0 g 0f SECT 01 0000 [.text] __ZN25AMDRadeonX4000_IAMDSMLSPUC1EPK11OSMetaClass 00000000001240d0 g 0f SECT 01 0000 [.text] __ZN25AMDRadeonX4000_IAMDSMLSPUC2EPK11OSMetaClass 0000000000124124 g 0f SECT 01 0000 [.text] __ZN25AMDRadeonX4000_IAMDSMLSPUD0Ev 000000000012411a g 0f SECT 01 0000 [.text] __ZN25AMDRadeonX4000_IAMDSMLSPUD1Ev 0000000000124110 g 0f SECT 01 0000 [.text] __ZN25AMDRadeonX4000_IAMDSMLSPUD2Ev 000000000052eda0 g 0f SECT 0a 0000 [__DATA.__common] __ZN25AMDRadeonX4000_IAMDSMLUVD10gMetaClassE 00000000003c0218 g 0f SECT 08 0000 [.const_data] __ZN25AMDRadeonX4000_IAMDSMLUVD10superClassE 0000000000123ea0 g 0f SECT 01 0000 [.text] __ZN25AMDRadeonX4000_IAMDSMLUVD9MetaClassC1Ev 0000000000123f60 g 0f SECT 01 0000 [.text] __ZN25AMDRadeonX4000_IAMDSMLUVD9MetaClassC2Ev 00000000003c0210 g 0f SECT 08 0000 [.const_data] __ZN25AMDRadeonX4000_IAMDSMLUVD9metaClassE 0000000000123efc g 0f SECT 01 0000 [.text] __ZN25AMDRadeonX4000_IAMDSMLUVDC1EPK11OSMetaClass 0000000000123edc g 0f SECT 01 0000 [.text] __ZN25AMDRadeonX4000_IAMDSMLUVDC2EPK11OSMetaClass 0000000000123f30 g 0f SECT 01 0000 [.text] __ZN25AMDRadeonX4000_IAMDSMLUVDD0Ev 0000000000123f26 g 0f SECT 01 0000 [.text] __ZN25AMDRadeonX4000_IAMDSMLUVDD1Ev 0000000000123f1c g 0f SECT 01 0000 [.text] __ZN25AMDRadeonX4000_IAMDSMLUVDD2Ev 000000000052ee18 g 0f SECT 0a 0000 [__DATA.__common] __ZN25AMDRadeonX4000_IAMDSMLVCE10gMetaClassE 00000000003c08a0 g 0f SECT 08 0000 [.const_data] __ZN25AMDRadeonX4000_IAMDSMLVCE10superClassE 000000000012418e g 0f SECT 01 0000 [.text] __ZN25AMDRadeonX4000_IAMDSMLVCE9MetaClassC1Ev 000000000012424e g 0f SECT 01 0000 [.text] __ZN25AMDRadeonX4000_IAMDSMLVCE9MetaClassC2Ev 00000000003c0898 g 0f SECT 08 0000 [.const_data] __ZN25AMDRadeonX4000_IAMDSMLVCE9metaClassE 00000000001241ea g 0f SECT 01 0000 [.text] __ZN25AMDRadeonX4000_IAMDSMLVCEC1EPK11OSMetaClass 00000000001241ca g 0f SECT 01 0000 [.text] __ZN25AMDRadeonX4000_IAMDSMLVCEC2EPK11OSMetaClass 000000000012421e g 0f SECT 01 0000 [.text] __ZN25AMDRadeonX4000_IAMDSMLVCED0Ev 0000000000124214 g 0f SECT 01 0000 [.text] __ZN25AMDRadeonX4000_IAMDSMLVCED1Ev 000000000012420a g 0f SECT 01 0000 [.text] __ZN25AMDRadeonX4000_IAMDSMLVCED2Ev 000000000052d200 g 0f SECT 0a 0000 [__DATA.__common] __ZN25AMDRadeonX4000_VendorGart10gMetaClassE 0000000000390d38 g 0f SECT 08 0000 [.const_data] __ZN25AMDRadeonX4000_VendorGart10superClassE 0000000000024896 g 0f SECT 01 0000 [.text] __ZN25AMDRadeonX4000_VendorGart19freeVendorGartEntryEP18_VENDOR_GART_ENTRY 0000000000024818 g 0f SECT 01 0000 [.text] __ZN25AMDRadeonX4000_VendorGart20allocVendorGartEntryEv 00000000000246c6 g 0f SECT 01 0000 [.text] __ZN25AMDRadeonX4000_VendorGart4freeEv 0000000000024672 g 0f SECT 01 0000 [.text] __ZN25AMDRadeonX4000_VendorGart4initEv 0000000000024792 g 0f SECT 01 0000 [.text] __ZN25AMDRadeonX4000_VendorGart5allocEPyyj 00000000000248d2 g 0f SECT 01 0000 [.text] __ZN25AMDRadeonX4000_VendorGart7deallocEyj 0000000000024926 g 0f SECT 01 0000 [.text] __ZN25AMDRadeonX4000_VendorGart7reserveEyy 00000000000244e0 g 0f SECT 01 0000 [.text] __ZN25AMDRadeonX4000_VendorGart9MetaClassC1Ev 00000000000245a0 g 0f SECT 01 0000 [.text] __ZN25AMDRadeonX4000_VendorGart9MetaClassC2Ev 0000000000024736 g 0f SECT 01 0000 [.text] __ZN25AMDRadeonX4000_VendorGart9init_poolEy 0000000000390d30 g 0f SECT 08 0000 [.const_data] __ZN25AMDRadeonX4000_VendorGart9metaClassE 000000000002453c g 0f SECT 01 0000 [.text] __ZN25AMDRadeonX4000_VendorGartC1EPK11OSMetaClass 0000000000024612 g 0f SECT 01 0000 [.text] __ZN25AMDRadeonX4000_VendorGartC1Ev 000000000002451c g 0f SECT 01 0000 [.text] __ZN25AMDRadeonX4000_VendorGartC2EPK11OSMetaClass 0000000000024642 g 0f SECT 01 0000 [.text] __ZN25AMDRadeonX4000_VendorGartC2Ev 0000000000024570 g 0f SECT 01 0000 [.text] __ZN25AMDRadeonX4000_VendorGartD0Ev 0000000000024566 g 0f SECT 01 0000 [.text] __ZN25AMDRadeonX4000_VendorGartD1Ev 000000000002455c g 0f SECT 01 0000 [.text] __ZN25AMDRadeonX4000_VendorGartD2Ev 000000000052d9f0 g 0f SECT 0a 0000 [__DATA.__common] __ZN26AMDRadeonX4000_AMDHWEngine10gMetaClassE 00000000003a2a38 g 0f SECT 08 0000 [.const_data] __ZN26AMDRadeonX4000_AMDHWEngine10superClassE 00000000000508ba g 0f SECT 01 0000 [.text] __ZN26AMDRadeonX4000_AMDHWEngine11waitForIdleEv 0000000000050992 g 0f SECT 01 0000 [.text] __ZN26AMDRadeonX4000_AMDHWEngine12getHWChannelE18_eAMD_HW_RING_TYPE 0000000000050b1a g 0f SECT 01 0000 [.text] __ZN26AMDRadeonX4000_AMDHWEngine14releaseHWRingsEv 0000000000050a3c g 0f SECT 01 0000 [.text] __ZN26AMDRadeonX4000_AMDHWEngine17releaseHWChannelsEv 00000000000508da g 0f SECT 01 0000 [.text] __ZN26AMDRadeonX4000_AMDHWEngine18limitedWaitForIdleEjj 0000000000050b70 g 0f SECT 01 0000 [.text] __ZN26AMDRadeonX4000_AMDHWEngine20writeDiagnosisReportERPcRj 0000000000050a7a g 0f SECT 01 0000 [.text] __ZN26AMDRadeonX4000_AMDHWEngine22allocateAndInitHWRingsEv 00000000000509a0 g 0f SECT 01 0000 [.text] __ZN26AMDRadeonX4000_AMDHWEngine25allocateAndInitHWChannelsEv 0000000000050b58 g 0f SECT 01 0000 [.text] __ZN26AMDRadeonX4000_AMDHWEngine33initializeSubmitCommandBufferInfoEP30AMD_SUBMIT_COMMAND_BUFFER_INFO 0000000000050812 g 0f SECT 01 0000 [.text] __ZN26AMDRadeonX4000_AMDHWEngine4freeEv 00000000000506fa g 0f SECT 01 0000 [.text] __ZN26AMDRadeonX4000_AMDHWEngine4initEP30AMDRadeonX4000_IAMDHWInterface20_eAMD_HW_ENGINE_TYPE 0000000000050d9e g 0f SECT 01 0000 [.text] __ZN26AMDRadeonX4000_AMDHWEngine5resetE18_eAMD_HW_RING_TYPE 0000000000050620 g 0f SECT 01 0000 [.text] __ZN26AMDRadeonX4000_AMDHWEngine9MetaClassC1Ev 00000000000506c0 g 0f SECT 01 0000 [.text] __ZN26AMDRadeonX4000_AMDHWEngine9MetaClassC2Ev 00000000003a2a30 g 0f SECT 08 0000 [.const_data] __ZN26AMDRadeonX4000_AMDHWEngine9metaClassE 000000000005065c g 0f SECT 01 0000 [.text] __ZN26AMDRadeonX4000_AMDHWEngineC2EPK11OSMetaClass 0000000000050690 g 0f SECT 01 0000 [.text] __ZN26AMDRadeonX4000_AMDHWEngineD0Ev 0000000000050686 g 0f SECT 01 0000 [.text] __ZN26AMDRadeonX4000_AMDHWEngineD1Ev 000000000005067c g 0f SECT 01 0000 [.text] __ZN26AMDRadeonX4000_AMDHWEngineD2Ev 000000000052dd10 g 0f SECT 0a 0000 [__DATA.__common] __ZN26AMDRadeonX4000_AMDHWMemory10gMetaClassE 00000000003a6648 g 0f SECT 08 0000 [.const_data] __ZN26AMDRadeonX4000_AMDHWMemory10superClassE 000000000005482a g 0f SECT 01 0000 [.text] __ZN26AMDRadeonX4000_AMDHWMemory11canAllocateEyyb 00000000000547a2 g 0f SECT 01 0000 [.text] __ZN26AMDRadeonX4000_AMDHWMemory11free_legacyEP16GLKMemoryElementP12IOAccelEvent 0000000000055526 g 0f SECT 01 0000 [.text] __ZN26AMDRadeonX4000_AMDHWMemory11waitForIdleEv 00000000000545cc g 0f SECT 01 0000 [.text] __ZN26AMDRadeonX4000_AMDHWMemory12getRangeInfoE22eAMD_MEMORY_RANGE_TYPEP21AMD_MEMORY_RANGE_INFO 00000000000548fa g 0f SECT 01 0000 [.text] __ZN26AMDRadeonX4000_AMDHWMemory13getAllocBytesEP16GLKMemoryElement 00000000000548a6 g 0f SECT 01 0000 [.text] __ZN26AMDRadeonX4000_AMDHWMemory13getAllocBytesEPK16AMDMemoryElement 000000000005491a g 0f SECT 01 0000 [.text] __ZN26AMDRadeonX4000_AMDHWMemory13hasAllocationEPK16AMDMemoryElement 0000000000054552 g 0f SECT 01 0000 [.text] __ZN26AMDRadeonX4000_AMDHWMemory13initRangeInfoEv 000000000005474e g 0f SECT 01 0000 [.text] __ZN26AMDRadeonX4000_AMDHWMemory14reserve_legacyEP16GLKMemoryElementyyb15_eOP_ORIGINATOR 00000000000546ec g 0f SECT 01 0000 [.text] __ZN26AMDRadeonX4000_AMDHWMemory15allocate_legacyEP16GLKMemoryElementyy28_eAMD_MEMORY_ALLOCATION_TYPEb15_eOP_ORIGINATOR9_eOP_TYPE 0000000000054682 g 0f SECT 01 0000 [.text] __ZN26AMDRadeonX4000_AMDHWMemory15allocate_legacyEP16GLKMemoryElementyyyyb15_eOP_ORIGINATOR9_eOP_TYPE 0000000000053ff4 g 0f SECT 01 0000 [.text] __ZN26AMDRadeonX4000_AMDHWMemory15setVirtualSpaceEP18IOMemoryDescriptor 0000000000054fe2 g 0f SECT 01 0000 [.text] __ZN26AMDRadeonX4000_AMDHWMemory15totalFreeMemoryEv 000000000005409e g 0f SECT 01 0000 [.text] __ZN26AMDRadeonX4000_AMDHWMemory17enableAllocationsEv 000000000005460c g 0f SECT 01 0000 [.text] __ZN26AMDRadeonX4000_AMDHWMemory17getRangeStartSizeE22eAMD_MEMORY_RANGE_TYPEPyS1_ 000000000005464c g 0f SECT 01 0000 [.text] __ZN26AMDRadeonX4000_AMDHWMemory18configureRangeInfoE22eAMD_MEMORY_RANGE_TYPEPK21AMD_MEMORY_RANGE_INFO 0000000000054190 g 0f SECT 01 0000 [.text] __ZN26AMDRadeonX4000_AMDHWMemory18disableAllocationsEb 00000000000550b4 g 0f SECT 01 0000 [.text] __ZN26AMDRadeonX4000_AMDHWMemory18freeUnusedApertureEj 0000000000054546 g 0f SECT 01 0000 [.text] __ZN26AMDRadeonX4000_AMDHWMemory20setVirtualSpaceReadyEb 0000000000054fb8 g 0f SECT 01 0000 [.text] __ZN26AMDRadeonX4000_AMDHWMemory20totalFreeFixedMemoryEv 0000000000054b9a g 0f SECT 01 0000 [.text] __ZN26AMDRadeonX4000_AMDHWMemory20tryWaitForAllocationEP16GLKMemoryElementyyyy 0000000000054ff0 g 0f SECT 01 0000 [.text] __ZN26AMDRadeonX4000_AMDHWMemory22allocateUnusedApertureEPyy 0000000000054fc6 g 0f SECT 01 0000 [.text] __ZN26AMDRadeonX4000_AMDHWMemory22computeTotalFreeMemoryEb 0000000000054434 g 0f SECT 01 0000 [.text] __ZN26AMDRadeonX4000_AMDHWMemory22freeInUseMemoryElementEP33_sAMD_IN_USE_HW_MEMORY_DESCRIPTORj 00000000000547e6 g 0f SECT 01 0000 [.text] __ZN26AMDRadeonX4000_AMDHWMemory25findInUseMemoryDescriptorEyPj 00000000000544aa g 0f SECT 01 0000 [.text] __ZN26AMDRadeonX4000_AMDHWMemory25freeInUseMemoryDescriptorEP33_sAMD_IN_USE_HW_MEMORY_DESCRIPTOR 00000000000554f2 g 0f SECT 01 0000 [.text] __ZN26AMDRadeonX4000_AMDHWMemory25handlepCleanupThreadTimerEP8OSObjectP18IOTimerEventSource 00000000000552f8 g 0f SECT 01 0000 [.text] __ZN26AMDRadeonX4000_AMDHWMemory25initInUseMemoryDescriptorEP33_sAMD_IN_USE_HW_MEMORY_DESCRIPTOR 000000000005538a g 0f SECT 01 0000 [.text] __ZN26AMDRadeonX4000_AMDHWMemory26waitForFreedMemoryToFinishEyy 000000000005454c g 0f SECT 01 0000 [.text] __ZN26AMDRadeonX4000_AMDHWMemory27setMemoryAllocationsEnabledEb 0000000000054acc g 0f SECT 01 0000 [.text] __ZN26AMDRadeonX4000_AMDHWMemory29allocateInUseMemoryDescriptorEv 0000000000053fb2 g 0f SECT 01 0000 [.text] __ZN26AMDRadeonX4000_AMDHWMemory29freeInUseMemoryDataStructuresEv 0000000000053e4e g 0f SECT 01 0000 [.text] __ZN26AMDRadeonX4000_AMDHWMemory29initInUseMemoryDataStructuresEv 00000000000543a6 g 0f SECT 01 0000 [.text] __ZN26AMDRadeonX4000_AMDHWMemory34cleanupFinishedInUseMemoryElementsEv 0000000000054c44 g 0f SECT 01 0000 [.text] __ZN26AMDRadeonX4000_AMDHWMemory35addInUseMemoryDescriptorToHashTableEP33_sAMD_IN_USE_HW_MEMORY_DESCRIPTOR 0000000000055100 g 0f SECT 01 0000 [.text] __ZN26AMDRadeonX4000_AMDHWMemory3mapEyyPP11IOMemoryMapj 0000000000054e2e g 0f SECT 01 0000 [.text] __ZN26AMDRadeonX4000_AMDHWMemory4freeEPK16AMDMemoryElementP12IOAccelEvent 0000000000053e8a g 0f SECT 01 0000 [.text] __ZN26AMDRadeonX4000_AMDHWMemory4freeEv 0000000000053b6a g 0f SECT 01 0000 [.text] __ZN26AMDRadeonX4000_AMDHWMemory4initEP30AMDRadeonX4000_IAMDHWInterfacejj 00000000000551cc g 0f SECT 01 0000 [.text] __ZN26AMDRadeonX4000_AMDHWMemory4readEyyPh23_eAMD_MEMORY_HDP_CLIENT 00000000000551a2 g 0f SECT 01 0000 [.text] __ZN26AMDRadeonX4000_AMDHWMemory5unmapEPP11IOMemoryMap 00000000000552b2 g 0f SECT 01 0000 [.text] __ZN26AMDRadeonX4000_AMDHWMemory5writeEyyPh 0000000000054d44 g 0f SECT 01 0000 [.text] __ZN26AMDRadeonX4000_AMDHWMemory7reserveEP16AMDMemoryElementyyb15_eOP_ORIGINATOR 0000000000054c8a g 0f SECT 01 0000 [.text] __ZN26AMDRadeonX4000_AMDHWMemory8allocateEP16AMDMemoryElementyy28_eAMD_MEMORY_ALLOCATION_TYPEb15_eOP_ORIGINATOR9_eOP_TYPE 000000000005495c g 0f SECT 01 0000 [.text] __ZN26AMDRadeonX4000_AMDHWMemory8allocateEP16AMDMemoryElementyyyyb15_eOP_ORIGINATOR9_eOP_TYPE 0000000000053a90 g 0f SECT 01 0000 [.text] __ZN26AMDRadeonX4000_AMDHWMemory9MetaClassC1Ev 0000000000053b30 g 0f SECT 01 0000 [.text] __ZN26AMDRadeonX4000_AMDHWMemory9MetaClassC2Ev 00000000003a6640 g 0f SECT 08 0000 [.const_data] __ZN26AMDRadeonX4000_AMDHWMemory9metaClassE 0000000000053acc g 0f SECT 01 0000 [.text] __ZN26AMDRadeonX4000_AMDHWMemoryC2EPK11OSMetaClass 0000000000053b00 g 0f SECT 01 0000 [.text] __ZN26AMDRadeonX4000_AMDHWMemoryD0Ev 0000000000053af6 g 0f SECT 01 0000 [.text] __ZN26AMDRadeonX4000_AMDHWMemoryD1Ev 0000000000053aec g 0f SECT 01 0000 [.text] __ZN26AMDRadeonX4000_AMDHWMemoryD2Ev 000000000052dea0 g 0f SECT 0a 0000 [__DATA.__common] __ZN26AMDRadeonX4000_AMDHardware10gMetaClassE 000000000005d0d6 g 0f SECT 01 0000 [.text] __ZN26AMDRadeonX4000_AMDHardware10releaseIriEPvP18_IRI_RELEASE_INPUT 00000000003a8278 g 0f SECT 08 0000 [.const_data] __ZN26AMDRadeonX4000_AMDHardware10superClassE 000000000005bf2e g 0f SECT 01 0000 [.text] __ZN26AMDRadeonX4000_AMDHardware11powerUpCAILEv 000000000005d2c8 g 0f SECT 01 0000 [.text] __ZN26AMDRadeonX4000_AMDHardware11setRefClockEj 000000000005ce86 g 0f SECT 01 0000 [.text] __ZN26AMDRadeonX4000_AMDHardware12MCIL_WaitForEPvP18_MCIL_WAITFOR_INFO 000000000005b2bc g 0f SECT 01 0000 [.text] __ZN26AMDRadeonX4000_AMDHardware12getHWChannelE20_eAMD_HW_ENGINE_TYPE18_eAMD_HW_RING_TYPE 000000000005b2f2 g 0f SECT 01 0000 [.text] __ZN26AMDRadeonX4000_AMDHardware12getHWChannelEi 000000000005bdba g 0f SECT 01 0000 [.text] __ZN26AMDRadeonX4000_AMDHardware13cailIRIObtainEv 000000000005c0c4 g 0f SECT 01 0000 [.text] __ZN26AMDRadeonX4000_AMDHardware13postVBIOSCAILEv 000000000005bef6 g 0f SECT 01 0000 [.text] __ZN26AMDRadeonX4000_AMDHardware13powerDownCAILEv 000000000005b3b6 g 0f SECT 01 0000 [.text] __ZN26AMDRadeonX4000_AMDHardware13resetHardwareEj 000000000005ab84 g 0f SECT 01 0000 [.text] __ZN26AMDRadeonX4000_AMDHardware13stopHWEnginesEv 000000000005d0ce g 0f SECT 01 0000 [.text] __ZN26AMDRadeonX4000_AMDHardware14MCIL_DebugPostEPvj 000000000005ab4a g 0f SECT 01 0000 [.text] __ZN26AMDRadeonX4000_AMDHardware14startHWEnginesEv 000000000005d3ae g 0f SECT 01 0000 [.text] __ZN26AMDRadeonX4000_AMDHardware14uvdControlCailEmPvS0_ 000000000005d3c0 g 0f SECT 01 0000 [.text] __ZN26AMDRadeonX4000_AMDHardware14vceControlCailEmPvS0_ 000000000005ccc2 g 0f SECT 01 0000 [.text] __ZN26AMDRadeonX4000_AMDHardware15MCIL_CopyMemoryEPvP18_MCIL_COPYMEM_INFO 000000000005cf66 g 0f SECT 01 0000 [.text] __ZN26AMDRadeonX4000_AMDHardware15MCIL_IRI_ObtainEPvP22_MCIL_IRI_OBTAIN_INPUTP23_MCIL_IRI_OBTAIN_OUTPUT 000000000005b796 g 0f SECT 01 0000 [.text] __ZN26AMDRadeonX4000_AMDHardware15MCIL_InitializeEP23_MCIL_SERVICE_CALLBACKS 000000000005ccfc g 0f SECT 01 0000 [.text] __ZN26AMDRadeonX4000_AMDHardware15MCIL_ZeroMemoryEPvP18_MCIL_ZEROMEM_INFO 000000000005c10e g 0f SECT 01 0000 [.text] __ZN26AMDRadeonX4000_AMDHardware15getOSObjectDataEP8OSObjectPvj 000000000005be6a g 0f SECT 01 0000 [.text] __ZN26AMDRadeonX4000_AMDHardware15initAdapterCAILEv 000000000005b304 g 0f SECT 01 0000 [.text] __ZN26AMDRadeonX4000_AMDHardware15registerChannelEP28AMDRadeonX4000_IAMDHWChannel 000000000005d3d2 g 0f SECT 01 0000 [.text] __ZN26AMDRadeonX4000_AMDHardware15samuControlCailEmPvS0_ 000000000005aa14 g 0f SECT 01 0000 [.text] __ZN26AMDRadeonX4000_AMDHardware16allocateAMDHWVMMEv 000000000005b516 g 0f SECT 01 0000 [.text] __ZN26AMDRadeonX4000_AMDHardware16getASICHangStateEv 000000000005aad6 g 0f SECT 01 0000 [.text] __ZN26AMDRadeonX4000_AMDHardware16powerUpHWEnginesEv 000000000005d0f8 g 0f SECT 01 0000 [.text] __ZN26AMDRadeonX4000_AMDHardware16pplibIriFunctionEPvP15_IRI_CALL_INPUTP16_IRI_CALL_OUTPUT 000000000005c73a g 0f SECT 01 0000 [.text] __ZN26AMDRadeonX4000_AMDHardware17MCIL_ReadRomImageEPvP15_MCIL_DATA_INFO 000000000005a9ee g 0f SECT 01 0000 [.text] __ZN26AMDRadeonX4000_AMDHardware17allocateAMDHWGartEv 000000000005d730 g 0f SECT 01 0000 [.text] __ZN26AMDRadeonX4000_AMDHardware17flushSystemCachesEPKvj 000000000005b39a g 0f SECT 01 0000 [.text] __ZN26AMDRadeonX4000_AMDHardware17getCailEngineTypeE20_eAMD_HW_ENGINE_TYPE 000000000005bb08 g 0f SECT 01 0000 [.text] __ZN26AMDRadeonX4000_AMDHardware17initCAILParameterEmx 000000000005ab10 g 0f SECT 01 0000 [.text] __ZN26AMDRadeonX4000_AMDHardware17powerOffHWEnginesEv 000000000005a91a g 0f SECT 01 0000 [.text] __ZN26AMDRadeonX4000_AMDHardware17releaseHWChannelsEv 000000000005cb9a g 0f SECT 01 0000 [.text] __ZN26AMDRadeonX4000_AMDHardware18MCIL_ReleaseMemoryEPvP19_MCIL_MEMBLOCK_INFO 000000000005ca30 g 0f SECT 01 0000 [.text] __ZN26AMDRadeonX4000_AMDHardware18MCIL_SyncExecutionEPvP23_MCIL_SYNEXECUTION_INFO 000000000005cc86 g 0f SECT 01 0000 [.text] __ZN26AMDRadeonX4000_AMDHardware18MCIL_WaitForMCIdleEPv 000000000005d644 g 0f SECT 01 0000 [.text] __ZN26AMDRadeonX4000_AMDHardware18engineEnabledEventEP27AMDRadeonX4000_IAMDHWEngine 000000000005d23a g 0f SECT 01 0000 [.text] __ZN26AMDRadeonX4000_AMDHardware18setStallParametersEjj 000000000005ca5e g 0f SECT 01 0000 [.text] __ZN26AMDRadeonX4000_AMDHardware19MCIL_AllocateMemoryEPvP19_MCIL_MEMBLOCK_INFO 000000000005c7f6 g 0f SECT 01 0000 [.text] __ZN26AMDRadeonX4000_AMDHardware19MCIL_GetRegistrykeyEPvP19_MCIL_REGISTRY_INFO 000000000005ccaa g 0f SECT 01 0000 [.text] __ZN26AMDRadeonX4000_AMDHardware19MCIL_MapToGartSpaceEPvP19_MCIL_MEMBLOCK_INFO 000000000005cd3a g 0f SECT 01 0000 [.text] __ZN26AMDRadeonX4000_AMDHardware19MCIL_ModifyRegisterEPvP25_MCIL_MODIFYREGISTER_INFO 000000000005c998 g 0f SECT 01 0000 [.text] __ZN26AMDRadeonX4000_AMDHardware19MCIL_SetRegistrykeyEPvP19_MCIL_REGISTRY_INFO 000000000005cc36 g 0f SECT 01 0000 [.text] __ZN26AMDRadeonX4000_AMDHardware19MCIL_WaitForGUIIdleEPv 000000000005aa3a g 0f SECT 01 0000 [.text] __ZN26AMDRadeonX4000_AMDHardware19allocateNullEnginesEv 000000000005d67e g 0f SECT 01 0000 [.text] __ZN26AMDRadeonX4000_AMDHardware19engineDisabledEventEP27AMDRadeonX4000_IAMDHWEngine 000000000005d1c0 g 0f SECT 01 0000 [.text] __ZN26AMDRadeonX4000_AMDHardware19enterDiagnosticModeEv 000000000005ac8a g 0f SECT 01 0000 [.text] __ZN26AMDRadeonX4000_AMDHardware19freeWritebackMemoryEv 000000000005aa98 g 0f SECT 01 0000 [.text] __ZN26AMDRadeonX4000_AMDHardware19initializeHWEnginesEv 000000000005b1d0 g 0f SECT 01 0000 [.text] __ZN26AMDRadeonX4000_AMDHardware20freeCailReservationsEv 000000000005af72 g 0f SECT 01 0000 [.text] __ZN26AMDRadeonX4000_AMDHardware20setVirtualSpaceReadyEb 000000000005d94a g 0f SECT 01 0000 [.text] __ZN26AMDRadeonX4000_AMDHardware20writeDiagnosisReportERPcRj 000000000005c36c g 0f SECT 01 0000 [.text] __ZN26AMDRadeonX4000_AMDHardware21MCIL_GetPciConfigDataEPvP20_MCIL_PCICONFIG_DATA 000000000005c47c g 0f SECT 01 0000 [.text] __ZN26AMDRadeonX4000_AMDHardware21MCIL_SetPciConfigDataEPvP20_MCIL_PCICONFIG_DATA 000000000005d6b8 g 0f SECT 01 0000 [.text] __ZN26AMDRadeonX4000_AMDHardware21enableMultiEngineSyncEv 000000000005d604 g 0f SECT 01 0000 [.text] __ZN26AMDRadeonX4000_AMDHardware21getEnabledEngineCountEv 000000000005d3f8 g 0f SECT 01 0000 [.text] __ZN26AMDRadeonX4000_AMDHardware21setReservedVRAMOffsetEyy 000000000005a9c8 g 0f SECT 01 0000 [.text] __ZN26AMDRadeonX4000_AMDHardware22allocateAMDHWRegistersEv 000000000005a48a g 0f SECT 01 0000 [.text] __ZN26AMDRadeonX4000_AMDHardware22allocateNullHWChannelsEv 000000000005d6ec g 0f SECT 01 0000 [.text] __ZN26AMDRadeonX4000_AMDHardware22disableMultiEngineSyncEv 000000000005c0cc g 0f SECT 01 0000 [.text] __ZN26AMDRadeonX4000_AMDHardware22getAMDHardwareFromCailEPv 000000000005a5c6 g 0f SECT 01 0000 [.text] __ZN26AMDRadeonX4000_AMDHardware22getAllCailReservationsEjP23CAIL_BIOS_RESERVE_BLOCK 000000000005d3e4 g 0f SECT 01 0000 [.text] __ZN26AMDRadeonX4000_AMDHardware22isValidCailReservationEj 000000000005ccb6 g 0f SECT 01 0000 [.text] __ZN26AMDRadeonX4000_AMDHardware23MCIL_UnmapFromGartSpaceEPvP19_MCIL_MEMBLOCK_INFO 000000000005abbe g 0f SECT 01 0000 [.text] __ZN26AMDRadeonX4000_AMDHardware23allocateWritebackMemoryEv 000000000005b108 g 0f SECT 01 0000 [.text] __ZN26AMDRadeonX4000_AMDHardware23reserveCailReservationsEv 000000000005c782 g 0f SECT 01 0000 [.text] __ZN26AMDRadeonX4000_AMDHardware24MCIL_DelayInMicrosecondsEPvj 000000000005c7ea g 0f SECT 01 0000 [.text] __ZN26AMDRadeonX4000_AMDHardware24MCIL_SleepInMillisecondsEPvj 000000000005a95e g 0f SECT 01 0000 [.text] __ZN26AMDRadeonX4000_AMDHardware24allocateDiagReportBufferEv 000000000005a50a g 0f SECT 01 0000 [.text] __ZN26AMDRadeonX4000_AMDHardware24getNumOfCailReservationsEv 000000000005c560 g 0f SECT 01 0000 [.text] __ZN26AMDRadeonX4000_AMDHardware25MCIL_GetAISCPciConfigDataEPvP20_MCIL_PCICONFIG_DATA 000000000005c64c g 0f SECT 01 0000 [.text] __ZN26AMDRadeonX4000_AMDHardware25MCIL_SetAISCPciConfigDataEPvP20_MCIL_PCICONFIG_DATA 000000000005a9a2 g 0f SECT 01 0000 [.text] __ZN26AMDRadeonX4000_AMDHardware25allocateAMDHWAlignManagerEv 000000000005d5a2 g 0f SECT 01 0000 [.text] __ZN26AMDRadeonX4000_AMDHardware25getReservedVRAMBaseOffsetE28_eAMD_MEMORY_ALLOCATION_TYPE 000000000005b28c g 0f SECT 01 0000 [.text] __ZN26AMDRadeonX4000_AMDHardware25systemDidChangeSpeedEventEv 000000000005d4b4 g 0f SECT 01 0000 [.text] __ZN26AMDRadeonX4000_AMDHardware26appendToReservedVRAMOffsetE28_eAMD_MEMORY_ALLOCATION_TYPEyj 000000000005b252 g 0f SECT 01 0000 [.text] __ZN26AMDRadeonX4000_AMDHardware26systemWillChangeSpeedEventEv 000000000005aef2 g 0f SECT 01 0000 [.text] __ZN26AMDRadeonX4000_AMDHardware27initializeHardwareRegistersEv 000000000005b078 g 0f SECT 01 0000 [.text] __ZN26AMDRadeonX4000_AMDHardware27setMemoryAllocationsEnabledEb 000000000005b37a g 0f SECT 01 0000 [.text] __ZN26AMDRadeonX4000_AMDHardware28getChannelWriteBackFrameAddrEi 000000000005d2d4 g 0f SECT 01 0000 [.text] __ZN26AMDRadeonX4000_AMDHardware28updateStallDisplayParametersEv 000000000005b35a g 0f SECT 01 0000 [.text] __ZN26AMDRadeonX4000_AMDHardware30getChannelWriteBackFrameOffsetEi 000000000005bf66 g 0f SECT 01 0000 [.text] __ZN26AMDRadeonX4000_AMDHardware32setupAndInitializeHWCapabilitiesEv 000000000005d746 g 0f SECT 01 0000 [.text] __ZN26AMDRadeonX4000_AMDHardware37writeASICHangLogInfoToDiagnosisReportERPcRj 000000000005a6a0 g 0f SECT 01 0000 [.text] __ZN26AMDRadeonX4000_AMDHardware4freeEv 0000000000059dea g 0f SECT 01 0000 [.text] __ZN26AMDRadeonX4000_AMDHardware4initEP11IOPCIDeviceP28AMDRadeonX4000_IAMDHWHandlerRjjP16_GART_PARAMETERSP14_FB_PARAMETERS 000000000005d20c g 0f SECT 01 0000 [.text] __ZN26AMDRadeonX4000_AMDHardware7initQSCEv 000000000005acf8 g 0f SECT 01 0000 [.text] __ZN26AMDRadeonX4000_AMDHardware7powerUpEv 000000000005bb3c g 0f SECT 01 0000 [.text] __ZN26AMDRadeonX4000_AMDHardware8initCAILEv 000000000005ae32 g 0f SECT 01 0000 [.text] __ZN26AMDRadeonX4000_AMDHardware8powerOffEv 000000000005af34 g 0f SECT 01 0000 [.text] __ZN26AMDRadeonX4000_AMDHardware8willWakeEv 0000000000059d10 g 0f SECT 01 0000 [.text] __ZN26AMDRadeonX4000_AMDHardware9MetaClassC1Ev 0000000000059db0 g 0f SECT 01 0000 [.text] __ZN26AMDRadeonX4000_AMDHardware9MetaClassC2Ev 00000000003a8270 g 0f SECT 08 0000 [.const_data] __ZN26AMDRadeonX4000_AMDHardware9metaClassE 000000000005b61e g 0f SECT 01 0000 [.text] __ZN26AMDRadeonX4000_AMDHardware9setupCAILEv 0000000000059d4c g 0f SECT 01 0000 [.text] __ZN26AMDRadeonX4000_AMDHardwareC2EPK11OSMetaClass 0000000000059d80 g 0f SECT 01 0000 [.text] __ZN26AMDRadeonX4000_AMDHardwareD0Ev 0000000000059d76 g 0f SECT 01 0000 [.text] __ZN26AMDRadeonX4000_AMDHardwareD1Ev 0000000000059d6c g 0f SECT 01 0000 [.text] __ZN26AMDRadeonX4000_AMDHardwareD2Ev 000000000052d0e8 g 0f SECT 0a 0000 [__DATA.__common] __ZN26AMDRadeonX4000_AMDSPUEvent10gMetaClassE 000000000038fb60 g 0f SECT 08 0000 [.const_data] __ZN26AMDRadeonX4000_AMDSPUEvent10superClassE 000000000001b9b0 g 0f SECT 01 0000 [.text] __ZN26AMDRadeonX4000_AMDSPUEvent12timerHandlerEP8OSObjectP18IOTimerEventSource 000000000001ba20 g 0f SECT 01 0000 [.text] __ZN26AMDRadeonX4000_AMDSPUEvent13addTimedEventEPFvP8OSObjectPvES2_j 000000000001ba62 g 0f SECT 01 0000 [.text] __ZN26AMDRadeonX4000_AMDSPUEvent16removeTimedEventEv 000000000001b9d4 g 0f SECT 01 0000 [.text] __ZN26AMDRadeonX4000_AMDSPUEvent4freeEv 000000000001b96c g 0f SECT 01 0000 [.text] __ZN26AMDRadeonX4000_AMDSPUEvent4initEP10IOWorkLoop 000000000001b7da g 0f SECT 01 0000 [.text] __ZN26AMDRadeonX4000_AMDSPUEvent9MetaClassC1Ev 000000000001b89a g 0f SECT 01 0000 [.text] __ZN26AMDRadeonX4000_AMDSPUEvent9MetaClassC2Ev 000000000038fb58 g 0f SECT 08 0000 [.const_data] __ZN26AMDRadeonX4000_AMDSPUEvent9metaClassE 000000000001b836 g 0f SECT 01 0000 [.text] __ZN26AMDRadeonX4000_AMDSPUEventC1EPK11OSMetaClass 000000000001b90c g 0f SECT 01 0000 [.text] __ZN26AMDRadeonX4000_AMDSPUEventC1Ev 000000000001b816 g 0f SECT 01 0000 [.text] __ZN26AMDRadeonX4000_AMDSPUEventC2EPK11OSMetaClass 000000000001b93c g 0f SECT 01 0000 [.text] __ZN26AMDRadeonX4000_AMDSPUEventC2Ev 000000000001b86a g 0f SECT 01 0000 [.text] __ZN26AMDRadeonX4000_AMDSPUEventD0Ev 000000000001b860 g 0f SECT 01 0000 [.text] __ZN26AMDRadeonX4000_AMDSPUEventD1Ev 000000000001b856 g 0f SECT 01 0000 [.text] __ZN26AMDRadeonX4000_AMDSPUEventD2Ev 00000000000277a4 g 0f SECT 01 0000 [.text] __ZN27AMDRadeonX4000_AMDAccelTask10deallocateEPK16IOAccelMemoryMapy 000000000052d4a0 g 0f SECT 0a 0000 [__DATA.__common] __ZN27AMDRadeonX4000_AMDAccelTask10gMetaClassE 0000000000392c08 g 0f SECT 08 0000 [.const_data] __ZN27AMDRadeonX4000_AMDAccelTask10superClassE 00000000000278fa g 0f SECT 01 0000 [.text] __ZN27AMDRadeonX4000_AMDAccelTask13remapMappingsEPP16IOAccelMemoryMapjy 00000000000278b2 g 0f SECT 01 0000 [.text] __ZN27AMDRadeonX4000_AMDAccelTask18freeAllGPUMappingsEv 0000000000027870 g 0f SECT 01 0000 [.text] __ZN27AMDRadeonX4000_AMDAccelTask20getCommandBufferPoolEP15IOAccelChannel2 000000000002767c g 0f SECT 01 0000 [.text] __ZN27AMDRadeonX4000_AMDAccelTask25releaseCommandBufferPoolsEv 000000000002759a g 0f SECT 01 0000 [.text] __ZN27AMDRadeonX4000_AMDAccelTask4freeEv 0000000000027432 g 0f SECT 01 0000 [.text] __ZN27AMDRadeonX4000_AMDAccelTask4initEP22IOGraphicsAccelerator2b 0000000000027844 g 0f SECT 01 0000 [.text] __ZN27AMDRadeonX4000_AMDAccelTask7reserveEjyy 00000000000276b6 g 0f SECT 01 0000 [.text] __ZN27AMDRadeonX4000_AMDAccelTask8allocateEPK16IOAccelMemoryMap 00000000000272a0 g 0f SECT 01 0000 [.text] __ZN27AMDRadeonX4000_AMDAccelTask9MetaClassC1Ev 0000000000027360 g 0f SECT 01 0000 [.text] __ZN27AMDRadeonX4000_AMDAccelTask9MetaClassC2Ev 0000000000392c00 g 0f SECT 08 0000 [.const_data] __ZN27AMDRadeonX4000_AMDAccelTask9metaClassE 00000000000272fc g 0f SECT 01 0000 [.text] __ZN27AMDRadeonX4000_AMDAccelTaskC1EPK11OSMetaClass 00000000000273d2 g 0f SECT 01 0000 [.text] __ZN27AMDRadeonX4000_AMDAccelTaskC1Ev 00000000000272dc g 0f SECT 01 0000 [.text] __ZN27AMDRadeonX4000_AMDAccelTaskC2EPK11OSMetaClass 0000000000027402 g 0f SECT 01 0000 [.text] __ZN27AMDRadeonX4000_AMDAccelTaskC2Ev 0000000000027330 g 0f SECT 01 0000 [.text] __ZN27AMDRadeonX4000_AMDAccelTaskD0Ev 0000000000027326 g 0f SECT 01 0000 [.text] __ZN27AMDRadeonX4000_AMDAccelTaskD1Ev 000000000002731c g 0f SECT 01 0000 [.text] __ZN27AMDRadeonX4000_AMDAccelTaskD2Ev 000000000052d888 g 0f SECT 0a 0000 [__DATA.__common] __ZN27AMDRadeonX4000_AMDHWChannel10gMetaClassE 00000000003a0b28 g 0f SECT 08 0000 [.const_data] __ZN27AMDRadeonX4000_AMDHWChannel10superClassE 0000000000049272 g 0f SECT 01 0000 [.text] __ZN27AMDRadeonX4000_AMDHWChannel11waitForIdleEv 000000000004a09c g 0f SECT 01 0000 [.text] __ZN27AMDRadeonX4000_AMDHWChannel13setDebugFlagsEj 000000000004a0a8 g 0f SECT 01 0000 [.text] __ZN27AMDRadeonX4000_AMDHWChannel15clearDebugFlagsEj 0000000000049d02 g 0f SECT 01 0000 [.text] __ZN27AMDRadeonX4000_AMDHWChannel15processAllWaitsEjP17vendevtBarrierRecjPjj 000000000004909a g 0f SECT 01 0000 [.text] __ZN27AMDRadeonX4000_AMDHWChannel15setEventMachineEP20IOAccelEventMachine2 0000000000049a58 g 0f SECT 01 0000 [.text] __ZN27AMDRadeonX4000_AMDHWChannel16getSemaphoreDataEj 0000000000049318 g 0f SECT 01 0000 [.text] __ZN27AMDRadeonX4000_AMDHWChannel16waitForTimestampEjPyb 000000000004963c g 0f SECT 01 0000 [.text] __ZN27AMDRadeonX4000_AMDHWChannel17checkForTimestampEj 0000000000049bc8 g 0f SECT 01 0000 [.text] __ZN27AMDRadeonX4000_AMDHWChannel17writeWaitCommandsEijPjj 000000000004a1ac g 0f SECT 01 0000 [.text] __ZN27AMDRadeonX4000_AMDHWChannel18isTimeStampExpiredEj 0000000000049118 g 0f SECT 01 0000 [.text] __ZN27AMDRadeonX4000_AMDHWChannel18limitedWaitForIdleEjj 000000000004a1de g 0f SECT 01 0000 [.text] __ZN27AMDRadeonX4000_AMDHWChannel18vblEnableInterruptEv 0000000000049702 g 0f SECT 01 0000 [.text] __ZN27AMDRadeonX4000_AMDHWChannel19submitCommandBufferEP30AMD_SUBMIT_COMMAND_BUFFER_INFOPj 000000000004a264 g 0f SECT 01 0000 [.text] __ZN27AMDRadeonX4000_AMDHWChannel19vblDisableInterruptEv 000000000004904e g 0f SECT 01 0000 [.text] __ZN27AMDRadeonX4000_AMDHWChannel20alignIBCommandBufferEPjj 0000000000048c96 g 0f SECT 01 0000 [.text] __ZN27AMDRadeonX4000_AMDHWChannel20getWaitSemaphoreDataEj 0000000000048cbc g 0f SECT 01 0000 [.text] __ZN27AMDRadeonX4000_AMDHWChannel20initStatisticsGroupsEv 000000000004a6b6 g 0f SECT 01 0000 [.text] __ZN27AMDRadeonX4000_AMDHWChannel20writeDiagnosisReportERPcRj 000000000004a60a g 0f SECT 01 0000 [.text] __ZN27AMDRadeonX4000_AMDHWChannel22hasPendingWaitCommandsEj 000000000004a58c g 0f SECT 01 0000 [.text] __ZN27AMDRadeonX4000_AMDHWChannel22timeStampInterruptTypeEv 000000000004a088 g 0f SECT 01 0000 [.text] __ZN27AMDRadeonX4000_AMDHWChannel22writeEventWriteCommandEPjjj 0000000000049e76 g 0f SECT 01 0000 [.text] __ZN27AMDRadeonX4000_AMDHWChannel23waitForCommandRingSpaceEjj 000000000004a07e g 0f SECT 01 0000 [.text] __ZN27AMDRadeonX4000_AMDHWChannel23writeSurfaceSyncCommandEPjjyyj 00000000000496ca g 0f SECT 01 0000 [.text] __ZN27AMDRadeonX4000_AMDHWChannel24setCommandTimestampPairsEPjS0_ 00000000000496a2 g 0f SECT 01 0000 [.text] __ZN27AMDRadeonX4000_AMDHWChannel25getCommandSubmitTimestampEv 000000000004a4ae g 0f SECT 01 0000 [.text] __ZN27AMDRadeonX4000_AMDHWChannel25timeStampDisableInterruptEv 000000000004a092 g 0f SECT 01 0000 [.text] __ZN27AMDRadeonX4000_AMDHWChannel25writeEventWriteEOPCommandEPjjjyjjy 000000000004a594 g 0f SECT 01 0000 [.text] __ZN27AMDRadeonX4000_AMDHWChannel26registerTimestampInterruptEv 000000000004a0b6 g 0f SECT 01 0000 [.text] __ZN27AMDRadeonX4000_AMDHWChannel26timeStampInterruptCallbackEP8OSObjectPv 00000000000496b2 g 0f SECT 01 0000 [.text] __ZN27AMDRadeonX4000_AMDHWChannel27getCommandLastReadTimestampEv 0000000000049a72 g 0f SECT 01 0000 [.text] __ZN27AMDRadeonX4000_AMDHWChannel27recordAndWriteChannelSignalEjPjj 0000000000049672 g 0f SECT 01 0000 [.text] __ZN27AMDRadeonX4000_AMDHWChannel29waitForLastSubmittedTimestampEv 000000000004a2da g 0f SECT 01 0000 [.text] __ZN27AMDRadeonX4000_AMDHWChannel32timeStampEnableInterruptAndSleepEj 0000000000048db6 g 0f SECT 01 0000 [.text] __ZN27AMDRadeonX4000_AMDHWChannel4freeEv 00000000000488fa g 0f SECT 01 0000 [.text] __ZN27AMDRadeonX4000_AMDHWChannel4initEiP30AMDRadeonX4000_IAMDHWInterfaceP27AMDRadeonX4000_IAMDHWEngineP25AMDRadeonX4000_IAMDHWRingPKc 0000000000049106 g 0f SECT 01 0000 [.text] __ZN27AMDRadeonX4000_AMDHWChannel6isIdleEv 00000000000490f4 g 0f SECT 01 0000 [.text] __ZN27AMDRadeonX4000_AMDHWChannel7isEmptyEv 0000000000048820 g 0f SECT 01 0000 [.text] __ZN27AMDRadeonX4000_AMDHWChannel9MetaClassC1Ev 00000000000488c0 g 0f SECT 01 0000 [.text] __ZN27AMDRadeonX4000_AMDHWChannel9MetaClassC2Ev 00000000000490e2 g 0f SECT 01 0000 [.text] __ZN27AMDRadeonX4000_AMDHWChannel9isEnabledEv 00000000003a0b20 g 0f SECT 08 0000 [.const_data] __ZN27AMDRadeonX4000_AMDHWChannel9metaClassE 000000000004885c g 0f SECT 01 0000 [.text] __ZN27AMDRadeonX4000_AMDHWChannelC2EPK11OSMetaClass 0000000000048890 g 0f SECT 01 0000 [.text] __ZN27AMDRadeonX4000_AMDHWChannelD0Ev 0000000000048886 g 0f SECT 01 0000 [.text] __ZN27AMDRadeonX4000_AMDHWChannelD1Ev 000000000004887c g 0f SECT 01 0000 [.text] __ZN27AMDRadeonX4000_AMDHWChannelD2Ev 000000000052d8b0 g 0f SECT 0a 0000 [__DATA.__common] __ZN27AMDRadeonX4000_AMDHWDisplay10gMetaClassE 00000000003a0ec8 g 0f SECT 08 0000 [.const_data] __ZN27AMDRadeonX4000_AMDHWDisplay10superClassE 000000000004c52c g 0f SECT 01 0000 [.text] __ZN27AMDRadeonX4000_AMDHWDisplay12FEDSShutdownEv 000000000004d278 g 0f SECT 01 0000 [.text] __ZN27AMDRadeonX4000_AMDHWDisplay13addVblankFlipEjP16IOAccelResource2S1_j 000000000004ce06 g 0f SECT 01 0000 [.text] __ZN27AMDRadeonX4000_AMDHWDisplay13canVblankFlipEj 000000000004be5c g 0f SECT 01 0000 [.text] __ZN27AMDRadeonX4000_AMDHWDisplay13detectBuiltInEv 000000000004dc0e g 0f SECT 01 0000 [.text] __ZN27AMDRadeonX4000_AMDHWDisplay14getDesktopSizeEv 000000000004b29a g 0f SECT 01 0000 [.text] __ZN27AMDRadeonX4000_AMDHWDisplay14getDisplayInfoEjbbPvP17_FRAMEBUFFER_INFO 000000000004d9ee g 0f SECT 01 0000 [.text] __ZN27AMDRadeonX4000_AMDHWDisplay14setFrameBufferEj 000000000004da4c g 0f SECT 01 0000 [.text] __ZN27AMDRadeonX4000_AMDHWDisplay15resetDisplayMapEv 000000000004bd02 g 0f SECT 01 0000 [.text] __ZN27AMDRadeonX4000_AMDHWDisplay16configureDisplayEjjP17_FRAMEBUFFER_INFOP16IOAccelResource2 000000000004b250 g 0f SECT 01 0000 [.text] __ZN27AMDRadeonX4000_AMDHWDisplay16isDisplayEnabledEj 000000000004b0c8 g 0f SECT 01 0000 [.text] __ZN27AMDRadeonX4000_AMDHWDisplay16restoreRegistersEjy 000000000004c10a g 0f SECT 01 0000 [.text] __ZN27AMDRadeonX4000_AMDHWDisplay16setAMDBltManagerEP24AMDRadeonX4000_AMDBltMgr 000000000004ceca g 0f SECT 01 0000 [.text] __ZN27AMDRadeonX4000_AMDHWDisplay16submitVblankFlipEj 000000000004c5bc g 0f SECT 01 0000 [.text] __ZN27AMDRadeonX4000_AMDHWDisplay17FEDSUpdateDisplayEv 000000000004c14e g 0f SECT 01 0000 [.text] __ZN27AMDRadeonX4000_AMDHWDisplay17allocateScanoutFBEjP16IOAccelResource2S1_Py 000000000004d9a6 g 0f SECT 01 0000 [.text] __ZN27AMDRadeonX4000_AMDHWDisplay18setDisplayMirroredEjj 000000000004c980 g 0f SECT 01 0000 [.text] __ZN27AMDRadeonX4000_AMDHWDisplay19FEDSResetFullScreenEj 000000000004c7be g 0f SECT 01 0000 [.text] __ZN27AMDRadeonX4000_AMDHWDisplay19FEDSSetupFullScreenEjj 000000000004da78 g 0f SECT 01 0000 [.text] __ZN27AMDRadeonX4000_AMDHWDisplay19getMirroredDisplaysEjPj 000000000004b01a g 0f SECT 01 0000 [.text] __ZN27AMDRadeonX4000_AMDHWDisplay19initializeRegistersEv 000000000004d608 g 0f SECT 01 0000 [.text] __ZN27AMDRadeonX4000_AMDHWDisplay20clearVblankFlipQueueEj 000000000004cb58 g 0f SECT 01 0000 [.text] __ZN27AMDRadeonX4000_AMDHWDisplay20updateCombinedStatusEv 000000000004d7da g 0f SECT 01 0000 [.text] __ZN27AMDRadeonX4000_AMDHWDisplay21addVblankFlipRegisterEP20AMD_VBLANK_FLIP_ELEMjjj 000000000004c772 g 0f SECT 01 0000 [.text] __ZN27AMDRadeonX4000_AMDHWDisplay23FEDSUpdateSwapTimestampEjj 000000000004d950 g 0f SECT 01 0000 [.text] __ZN27AMDRadeonX4000_AMDHWDisplay23getCurrentDisplayOffsetEj 000000000004c792 g 0f SECT 01 0000 [.text] __ZN27AMDRadeonX4000_AMDHWDisplay24FEDSUpdateBufferDirtyBitEjb 000000000004c5b4 g 0f SECT 01 0000 [.text] __ZN27AMDRadeonX4000_AMDHWDisplay24FEDSWriteUBMBlitToCmdBufEPjjbjP16IOAccelResource2 000000000004d814 g 0f SECT 01 0000 [.text] __ZN27AMDRadeonX4000_AMDHWDisplay25savePrimarySurfaceOffsetsEv 000000000004cdf0 g 0f SECT 01 0000 [.text] __ZN27AMDRadeonX4000_AMDHWDisplay26getNumScheduledVblankFlipsEj 000000000004dae2 g 0f SECT 01 0000 [.text] __ZN27AMDRadeonX4000_AMDHWDisplay26getTimingDisplayParametersEjPjS0_S0_ 000000000004d7f6 g 0f SECT 01 0000 [.text] __ZN27AMDRadeonX4000_AMDHWDisplay27isBufferScheduledForDisplayEjy 000000000004d8cc g 0f SECT 01 0000 [.text] __ZN27AMDRadeonX4000_AMDHWDisplay28restorePrimarySurfaceOffsetsEv 000000000004cd1e g 0f SECT 01 0000 [.text] __ZN27AMDRadeonX4000_AMDHWDisplay33writeUpdateTilingControlRegistersEjPjjP16IOAccelResource2b 000000000004cb86 g 0f SECT 01 0000 [.text] __ZN27AMDRadeonX4000_AMDHWDisplay36writeUpdateFrameBufferOffsetCommandsEjPjjjP16IOAccelResource2S2_S2_ 000000000004ae28 g 0f SECT 01 0000 [.text] __ZN27AMDRadeonX4000_AMDHWDisplay4freeEv 000000000004aaaa g 0f SECT 01 0000 [.text] __ZN27AMDRadeonX4000_AMDHWDisplay4initEP30AMDRadeonX4000_IAMDHWInterfaceP14_FB_PARAMETERS 000000000004a9d0 g 0f SECT 01 0000 [.text] __ZN27AMDRadeonX4000_AMDHWDisplay9MetaClassC1Ev 000000000004aa70 g 0f SECT 01 0000 [.text] __ZN27AMDRadeonX4000_AMDHWDisplay9MetaClassC2Ev 00000000003a0ec0 g 0f SECT 08 0000 [.const_data] __ZN27AMDRadeonX4000_AMDHWDisplay9metaClassE 000000000004aa0c g 0f SECT 01 0000 [.text] __ZN27AMDRadeonX4000_AMDHWDisplayC2EPK11OSMetaClass 000000000004aa40 g 0f SECT 01 0000 [.text] __ZN27AMDRadeonX4000_AMDHWDisplayD0Ev 000000000004aa36 g 0f SECT 01 0000 [.text] __ZN27AMDRadeonX4000_AMDHWDisplayD1Ev 000000000004aa2c g 0f SECT 01 0000 [.text] __ZN27AMDRadeonX4000_AMDHWDisplayD2Ev 000000000052d860 g 0f SECT 0a 0000 [__DATA.__common] __ZN27AMDRadeonX4000_AMDHWHandler10gMetaClassE 00000000003a07a8 g 0f SECT 08 0000 [.const_data] __ZN27AMDRadeonX4000_AMDHWHandler10superClassE 0000000000048546 g 0f SECT 01 0000 [.text] __ZN27AMDRadeonX4000_AMDHWHandler13addStatsGroupEP38AMDRadeonX4000_AMDAccelStatisticsGroup 0000000000048020 g 0f SECT 01 0000 [.text] __ZN27AMDRadeonX4000_AMDHWHandler13sendPMCommandEPv 000000000004809a g 0f SECT 01 0000 [.text] __ZN27AMDRadeonX4000_AMDHWHandler14doAtomicMemcpyEyyjbb 00000000000482a6 g 0f SECT 01 0000 [.text] __ZN27AMDRadeonX4000_AMDHWHandler14doAtomicMemsetEyjjb 0000000000048562 g 0f SECT 01 0000 [.text] __ZN27AMDRadeonX4000_AMDHWHandler14freeStatsGroupEP38AMDRadeonX4000_AMDAccelStatisticsGroup 00000000000484e2 g 0f SECT 01 0000 [.text] __ZN27AMDRadeonX4000_AMDHWHandler18setupWritebackSyncEiPj 000000000004852a g 0f SECT 01 0000 [.text] __ZN27AMDRadeonX4000_AMDHWHandler18validateStatsGroupEPKc 00000000000484d4 g 0f SECT 01 0000 [.text] __ZN27AMDRadeonX4000_AMDHWHandler19initPlistPropertiesEPKc 0000000000047f0a g 0f SECT 01 0000 [.text] __ZN27AMDRadeonX4000_AMDHWHandler21resetRenderingContextEv 0000000000047f10 g 0f SECT 01 0000 [.text] __ZN27AMDRadeonX4000_AMDHWHandler23createCommandBufferPoolEP28AMDRadeonX4000_IAMDHWChannelii 0000000000048494 g 0f SECT 01 0000 [.text] __ZN27AMDRadeonX4000_AMDHWHandler24hasTripleBufferedSurfaceEj 000000000004802e g 0f SECT 01 0000 [.text] __ZN27AMDRadeonX4000_AMDHWHandler25getUVDReservedAreaAddressEv 0000000000048004 g 0f SECT 01 0000 [.text] __ZN27AMDRadeonX4000_AMDHWHandler26setTimestampInterruptStateEPvj 0000000000048012 g 0f SECT 01 0000 [.text] __ZN27AMDRadeonX4000_AMDHWHandler28unregisterTimestampInterruptEPv 0000000000047ff6 g 0f SECT 01 0000 [.text] __ZN27AMDRadeonX4000_AMDHWHandler29registerForTimestampInterruptEjPFvP8OSObjectPvES1_S2_PS2_ 0000000000047ef8 g 0f SECT 01 0000 [.text] __ZN27AMDRadeonX4000_AMDHWHandler4freeEv 0000000000047ec2 g 0f SECT 01 0000 [.text] __ZN27AMDRadeonX4000_AMDHWHandler4initEP37AMDRadeonX4000_AMDGraphicsAccelerator 0000000000047d30 g 0f SECT 01 0000 [.text] __ZN27AMDRadeonX4000_AMDHWHandler9MetaClassC1Ev 0000000000047df0 g 0f SECT 01 0000 [.text] __ZN27AMDRadeonX4000_AMDHWHandler9MetaClassC2Ev 00000000003a07a0 g 0f SECT 08 0000 [.const_data] __ZN27AMDRadeonX4000_AMDHWHandler9metaClassE 0000000000047d8c g 0f SECT 01 0000 [.text] __ZN27AMDRadeonX4000_AMDHWHandlerC1EPK11OSMetaClass 0000000000047e62 g 0f SECT 01 0000 [.text] __ZN27AMDRadeonX4000_AMDHWHandlerC1Ev 0000000000047d6c g 0f SECT 01 0000 [.text] __ZN27AMDRadeonX4000_AMDHWHandlerC2EPK11OSMetaClass 0000000000047e92 g 0f SECT 01 0000 [.text] __ZN27AMDRadeonX4000_AMDHWHandlerC2Ev 0000000000047dc0 g 0f SECT 01 0000 [.text] __ZN27AMDRadeonX4000_AMDHWHandlerD0Ev 0000000000047db6 g 0f SECT 01 0000 [.text] __ZN27AMDRadeonX4000_AMDHWHandlerD1Ev 0000000000047dac g 0f SECT 01 0000 [.text] __ZN27AMDRadeonX4000_AMDHWHandlerD2Ev 000000000052d228 g 0f SECT 0a 0000 [__DATA.__common] __ZN27AMDRadeonX4000_AMDHashTable10gMetaClassE 0000000000390f68 g 0f SECT 08 0000 [.const_data] __ZN27AMDRadeonX4000_AMDHashTable10superClassE 0000000000024e5e g 0f SECT 01 0000 [.text] __ZN27AMDRadeonX4000_AMDHashTable13startIteratorEv 0000000000024ea8 g 0f SECT 01 0000 [.text] __ZN27AMDRadeonX4000_AMDHashTable15getNextIteratorEv 0000000000024e32 g 0f SECT 01 0000 [.text] __ZN27AMDRadeonX4000_AMDHashTable16freeTableElementEP24_sAMD_HASH_TABLE_ELEMENT 0000000000024d20 g 0f SECT 01 0000 [.text] __ZN27AMDRadeonX4000_AMDHashTable20allocateTableElementEv 0000000000024cc6 g 0f SECT 01 0000 [.text] __ZN27AMDRadeonX4000_AMDHashTable3addEjPvj 0000000000024bf0 g 0f SECT 01 0000 [.text] __ZN27AMDRadeonX4000_AMDHashTable4freeEv 0000000000024b92 g 0f SECT 01 0000 [.text] __ZN27AMDRadeonX4000_AMDHashTable4initEv 0000000000024c3e g 0f SECT 01 0000 [.text] __ZN27AMDRadeonX4000_AMDHashTable5clearEv 0000000000024d78 g 0f SECT 01 0000 [.text] __ZN27AMDRadeonX4000_AMDHashTable6removeEj 0000000000024a00 g 0f SECT 01 0000 [.text] __ZN27AMDRadeonX4000_AMDHashTable9MetaClassC1Ev 0000000000024ac0 g 0f SECT 01 0000 [.text] __ZN27AMDRadeonX4000_AMDHashTable9MetaClassC2Ev 0000000000390f60 g 0f SECT 08 0000 [.const_data] __ZN27AMDRadeonX4000_AMDHashTable9metaClassE 0000000000024a5c g 0f SECT 01 0000 [.text] __ZN27AMDRadeonX4000_AMDHashTableC1EPK11OSMetaClass 0000000000024b32 g 0f SECT 01 0000 [.text] __ZN27AMDRadeonX4000_AMDHashTableC1Ev 0000000000024a3c g 0f SECT 01 0000 [.text] __ZN27AMDRadeonX4000_AMDHashTableC2EPK11OSMetaClass 0000000000024b62 g 0f SECT 01 0000 [.text] __ZN27AMDRadeonX4000_AMDHashTableC2Ev 0000000000024a90 g 0f SECT 01 0000 [.text] __ZN27AMDRadeonX4000_AMDHashTableD0Ev 0000000000024a86 g 0f SECT 01 0000 [.text] __ZN27AMDRadeonX4000_AMDHashTableD1Ev 0000000000024a7c g 0f SECT 01 0000 [.text] __ZN27AMDRadeonX4000_AMDHashTableD2Ev 000000000052ef08 g 0f SECT 0a 0000 [__DATA.__common] __ZN27AMDRadeonX4000_AMDSMLSPUMsg10gMetaClassE 00000000003c18a8 g 0f SECT 08 0000 [.const_data] __ZN27AMDRadeonX4000_AMDSMLSPUMsg10superClassE 0000000000125b52 g 0f SECT 01 0000 [.text] __ZN27AMDRadeonX4000_AMDSMLSPUMsg4freeEv 0000000000125ad2 g 0f SECT 01 0000 [.text] __ZN27AMDRadeonX4000_AMDSMLSPUMsg4initEPv 0000000000125b64 g 0f SECT 01 0000 [.text] __ZN27AMDRadeonX4000_AMDSMLSPUMsg8getEventEv 0000000000125940 g 0f SECT 01 0000 [.text] __ZN27AMDRadeonX4000_AMDSMLSPUMsg9MetaClassC1Ev 0000000000125a00 g 0f SECT 01 0000 [.text] __ZN27AMDRadeonX4000_AMDSMLSPUMsg9MetaClassC2Ev 00000000003c18a0 g 0f SECT 08 0000 [.const_data] __ZN27AMDRadeonX4000_AMDSMLSPUMsg9metaClassE 000000000012599c g 0f SECT 01 0000 [.text] __ZN27AMDRadeonX4000_AMDSMLSPUMsgC1EPK11OSMetaClass 0000000000125a72 g 0f SECT 01 0000 [.text] __ZN27AMDRadeonX4000_AMDSMLSPUMsgC1Ev 000000000012597c g 0f SECT 01 0000 [.text] __ZN27AMDRadeonX4000_AMDSMLSPUMsgC2EPK11OSMetaClass 0000000000125aa2 g 0f SECT 01 0000 [.text] __ZN27AMDRadeonX4000_AMDSMLSPUMsgC2Ev 00000000001259d0 g 0f SECT 01 0000 [.text] __ZN27AMDRadeonX4000_AMDSMLSPUMsgD0Ev 00000000001259c6 g 0f SECT 01 0000 [.text] __ZN27AMDRadeonX4000_AMDSMLSPUMsgD1Ev 00000000001259bc g 0f SECT 01 0000 [.text] __ZN27AMDRadeonX4000_AMDSMLSPUMsgD2Ev 000000000052dc70 g 0f SECT 0a 0000 [__DATA.__common] __ZN27AMDRadeonX4000_IAMDHWEngine10gMetaClassE 00000000003a5a20 g 0f SECT 08 0000 [.const_data] __ZN27AMDRadeonX4000_IAMDHWEngine10superClassE 0000000000053072 g 0f SECT 01 0000 [.text] __ZN27AMDRadeonX4000_IAMDHWEngine9MetaClassC1Ev 0000000000053112 g 0f SECT 01 0000 [.text] __ZN27AMDRadeonX4000_IAMDHWEngine9MetaClassC2Ev 00000000003a5a18 g 0f SECT 08 0000 [.const_data] __ZN27AMDRadeonX4000_IAMDHWEngine9metaClassE 00000000000530ae g 0f SECT 01 0000 [.text] __ZN27AMDRadeonX4000_IAMDHWEngineC2EPK11OSMetaClass 00000000000530e2 g 0f SECT 01 0000 [.text] __ZN27AMDRadeonX4000_IAMDHWEngineD0Ev 00000000000530d8 g 0f SECT 01 0000 [.text] __ZN27AMDRadeonX4000_IAMDHWEngineD1Ev 00000000000530ce g 0f SECT 01 0000 [.text] __ZN27AMDRadeonX4000_IAMDHWEngineD2Ev 000000000052db30 g 0f SECT 0a 0000 [__DATA.__common] __ZN27AMDRadeonX4000_IAMDHWMemory10gMetaClassE 00000000003a4530 g 0f SECT 08 0000 [.const_data] __ZN27AMDRadeonX4000_IAMDHWMemory10superClassE 00000000000529a2 g 0f SECT 01 0000 [.text] __ZN27AMDRadeonX4000_IAMDHWMemory9MetaClassC1Ev 0000000000052a42 g 0f SECT 01 0000 [.text] __ZN27AMDRadeonX4000_IAMDHWMemory9MetaClassC2Ev 00000000003a4528 g 0f SECT 08 0000 [.const_data] __ZN27AMDRadeonX4000_IAMDHWMemory9metaClassE 00000000000529de g 0f SECT 01 0000 [.text] __ZN27AMDRadeonX4000_IAMDHWMemoryC2EPK11OSMetaClass 0000000000052a12 g 0f SECT 01 0000 [.text] __ZN27AMDRadeonX4000_IAMDHWMemoryD0Ev 0000000000052a08 g 0f SECT 01 0000 [.text] __ZN27AMDRadeonX4000_IAMDHWMemoryD1Ev 00000000000529fe g 0f SECT 01 0000 [.text] __ZN27AMDRadeonX4000_IAMDHWMemoryD2Ev 000000000052d7e8 g 0f SECT 0a 0000 [__DATA.__common] __ZN27AMDTongaGraphicsAccelerator10gMetaClassE 000000000039ed88 g 0f SECT 08 0000 [.const_data] __ZN27AMDTongaGraphicsAccelerator10superClassE 0000000000046c08 g 0f SECT 01 0000 [.text] __ZN27AMDTongaGraphicsAccelerator13setDeviceTypeEP11IOPCIDevice 0000000000046be2 g 0f SECT 01 0000 [.text] __ZN27AMDTongaGraphicsAccelerator14newHWInterfaceEv 0000000000046a50 g 0f SECT 01 0000 [.text] __ZN27AMDTongaGraphicsAccelerator9MetaClassC1Ev 0000000000046b10 g 0f SECT 01 0000 [.text] __ZN27AMDTongaGraphicsAccelerator9MetaClassC2Ev 000000000039ed80 g 0f SECT 08 0000 [.const_data] __ZN27AMDTongaGraphicsAccelerator9metaClassE 0000000000046aac g 0f SECT 01 0000 [.text] __ZN27AMDTongaGraphicsAcceleratorC1EPK11OSMetaClass 0000000000046b82 g 0f SECT 01 0000 [.text] __ZN27AMDTongaGraphicsAcceleratorC1Ev 0000000000046a8c g 0f SECT 01 0000 [.text] __ZN27AMDTongaGraphicsAcceleratorC2EPK11OSMetaClass 0000000000046bb2 g 0f SECT 01 0000 [.text] __ZN27AMDTongaGraphicsAcceleratorC2Ev 0000000000046ae0 g 0f SECT 01 0000 [.text] __ZN27AMDTongaGraphicsAcceleratorD0Ev 0000000000046ad6 g 0f SECT 01 0000 [.text] __ZN27AMDTongaGraphicsAcceleratorD1Ev 0000000000046acc g 0f SECT 01 0000 [.text] __ZN27AMDTongaGraphicsAcceleratorD2Ev 000000000052d5b8 g 0f SECT 0a 0000 [__DATA.__common] __ZN27AMDVerdeGraphicsAccelerator10gMetaClassE 0000000000395a18 g 0f SECT 08 0000 [.const_data] __ZN27AMDVerdeGraphicsAccelerator10superClassE 0000000000029a52 g 0f SECT 01 0000 [.text] __ZN27AMDVerdeGraphicsAccelerator14newHWInterfaceEv 00000000000298c0 g 0f SECT 01 0000 [.text] __ZN27AMDVerdeGraphicsAccelerator9MetaClassC1Ev 0000000000029980 g 0f SECT 01 0000 [.text] __ZN27AMDVerdeGraphicsAccelerator9MetaClassC2Ev 0000000000395a10 g 0f SECT 08 0000 [.const_data] __ZN27AMDVerdeGraphicsAccelerator9metaClassE 000000000002991c g 0f SECT 01 0000 [.text] __ZN27AMDVerdeGraphicsAcceleratorC1EPK11OSMetaClass 00000000000299f2 g 0f SECT 01 0000 [.text] __ZN27AMDVerdeGraphicsAcceleratorC1Ev 00000000000298fc g 0f SECT 01 0000 [.text] __ZN27AMDVerdeGraphicsAcceleratorC2EPK11OSMetaClass 0000000000029a22 g 0f SECT 01 0000 [.text] __ZN27AMDVerdeGraphicsAcceleratorC2Ev 0000000000029950 g 0f SECT 01 0000 [.text] __ZN27AMDVerdeGraphicsAcceleratorD0Ev 0000000000029946 g 0f SECT 01 0000 [.text] __ZN27AMDVerdeGraphicsAcceleratorD1Ev 000000000002993c g 0f SECT 01 0000 [.text] __ZN27AMDVerdeGraphicsAcceleratorD2Ev 000000000052d748 g 0f SECT 0a 0000 [__DATA.__common] __ZN28AMDHawaiiGraphicsAccelerator10gMetaClassE 000000000039c518 g 0f SECT 08 0000 [.const_data] __ZN28AMDHawaiiGraphicsAccelerator10superClassE 000000000003d5b2 g 0f SECT 01 0000 [.text] __ZN28AMDHawaiiGraphicsAccelerator14newHWInterfaceEv 000000000003d420 g 0f SECT 01 0000 [.text] __ZN28AMDHawaiiGraphicsAccelerator9MetaClassC1Ev 000000000003d4e0 g 0f SECT 01 0000 [.text] __ZN28AMDHawaiiGraphicsAccelerator9MetaClassC2Ev 000000000039c510 g 0f SECT 08 0000 [.const_data] __ZN28AMDHawaiiGraphicsAccelerator9metaClassE 000000000003d47c g 0f SECT 01 0000 [.text] __ZN28AMDHawaiiGraphicsAcceleratorC1EPK11OSMetaClass 000000000003d552 g 0f SECT 01 0000 [.text] __ZN28AMDHawaiiGraphicsAcceleratorC1Ev 000000000003d45c g 0f SECT 01 0000 [.text] __ZN28AMDHawaiiGraphicsAcceleratorC2EPK11OSMetaClass 000000000003d582 g 0f SECT 01 0000 [.text] __ZN28AMDHawaiiGraphicsAcceleratorC2Ev 000000000003d4b0 g 0f SECT 01 0000 [.text] __ZN28AMDHawaiiGraphicsAcceleratorD0Ev 000000000003d4a6 g 0f SECT 01 0000 [.text] __ZN28AMDHawaiiGraphicsAcceleratorD1Ev 000000000003d49c g 0f SECT 01 0000 [.text] __ZN28AMDHawaiiGraphicsAcceleratorD2Ev 000000000052d388 g 0f SECT 0a 0000 [__DATA.__common] __ZN28AMDRadeonX4000_AMDLinkedList10gMetaClassE 0000000000391198 g 0f SECT 08 0000 [.const_data] __ZN28AMDRadeonX4000_AMDLinkedList10superClassE 0000000000025488 g 0f SECT 01 0000 [.text] __ZN28AMDRadeonX4000_AMDLinkedList13startIteratorEv 00000000000254aa g 0f SECT 01 0000 [.text] __ZN28AMDRadeonX4000_AMDLinkedList14fini{censored}eratorEv 0000000000025456 g 0f SECT 01 0000 [.text] __ZN28AMDRadeonX4000_AMDLinkedList15freeListElementEP25_sAMD_LINKED_LIST_ELEMENT 00000000000254c0 g 0f SECT 01 0000 [.text] __ZN28AMDRadeonX4000_AMDLinkedList15getNextIteratorEv 0000000000025396 g 0f SECT 01 0000 [.text] __ZN28AMDRadeonX4000_AMDLinkedList19allocateListElementEPKv 00000000000254dc g 0f SECT 01 0000 [.text] __ZN28AMDRadeonX4000_AMDLinkedList21deleteCurrentIteratorEv 000000000002531a g 0f SECT 01 0000 [.text] __ZN28AMDRadeonX4000_AMDLinkedList3addEPv 000000000002528c g 0f SECT 01 0000 [.text] __ZN28AMDRadeonX4000_AMDLinkedList4freeEv 0000000000025232 g 0f SECT 01 0000 [.text] __ZN28AMDRadeonX4000_AMDLinkedList4initEv 00000000000253c8 g 0f SECT 01 0000 [.text] __ZN28AMDRadeonX4000_AMDLinkedList4pushEPv 00000000000252ba g 0f SECT 01 0000 [.text] __ZN28AMDRadeonX4000_AMDLinkedList5clearEv 00000000000250a0 g 0f SECT 01 0000 [.text] __ZN28AMDRadeonX4000_AMDLinkedList9MetaClassC1Ev 0000000000025160 g 0f SECT 01 0000 [.text] __ZN28AMDRadeonX4000_AMDLinkedList9MetaClassC2Ev 0000000000391190 g 0f SECT 08 0000 [.const_data] __ZN28AMDRadeonX4000_AMDLinkedList9metaClassE 00000000000250fc g 0f SECT 01 0000 [.text] __ZN28AMDRadeonX4000_AMDLinkedListC1EPK11OSMetaClass 00000000000251d2 g 0f SECT 01 0000 [.text] __ZN28AMDRadeonX4000_AMDLinkedListC1Ev 00000000000250dc g 0f SECT 01 0000 [.text] __ZN28AMDRadeonX4000_AMDLinkedListC2EPK11OSMetaClass 0000000000025202 g 0f SECT 01 0000 [.text] __ZN28AMDRadeonX4000_AMDLinkedListC2Ev 0000000000025130 g 0f SECT 01 0000 [.text] __ZN28AMDRadeonX4000_AMDLinkedListD0Ev 0000000000025126 g 0f SECT 01 0000 [.text] __ZN28AMDRadeonX4000_AMDLinkedListD1Ev 000000000002511c g 0f SECT 01 0000 [.text] __ZN28AMDRadeonX4000_AMDLinkedListD2Ev 000000000052d110 g 0f SECT 0a 0000 [__DATA.__common] __ZN28AMDRadeonX4000_AMDSPUContext10gMetaClassE 000000000001d77a g 0f SECT 01 0000 [.text] __ZN28AMDRadeonX4000_AMDSPUContext10hdcpUnLoadEj 000000000001d1a4 g 0f SECT 01 0000 [.text] __ZN28AMDRadeonX4000_AMDSPUContext10sendAppMsgEP31AMDRadeonX4000_AMDSPUAppContextP27AMDRadeonX4000_AMDSMLSPUMsg 000000000038fda0 g 0f SECT 08 0000 [.const_data] __ZN28AMDRadeonX4000_AMDSPUContext10superClassE 000000000001ccf2 g 0f SECT 01 0000 [.text] __ZN28AMDRadeonX4000_AMDSPUContext11loadAppCodeE17_AMD_SPU_APP_TYPEyj 000000000001d09c g 0f SECT 01 0000 [.text] __ZN28AMDRadeonX4000_AMDSPUContext12createAppMsgE17_AMD_SPU_MSG_TYPEPv 000000000001e168 g 0f SECT 01 0000 [.text] __ZN28AMDRadeonX4000_AMDSPUContext12fairplayLoadEPj 000000000001d104 g 0f SECT 01 0000 [.text] __ZN28AMDRadeonX4000_AMDSPUContext13destroyAppMsgEP27AMDRadeonX4000_AMDSMLSPUMsg 000000000001c758 g 0f SECT 01 0000 [.text] __ZN28AMDRadeonX4000_AMDSPUContext13getAppContextEj 000000000001bf8c g 0f SECT 01 0000 [.text] __ZN28AMDRadeonX4000_AMDSPUContext13initSPUThreadEv 000000000001d1dc g 0f SECT 01 0000 [.text] __ZN28AMDRadeonX4000_AMDSPUContext13processAppMsgEP31AMDRadeonX4000_AMDSPUAppContextP27AMDRadeonX4000_AMDSMLSPUMsg 000000000001dce4 g 0f SECT 01 0000 [.text] __ZN28AMDRadeonX4000_AMDSPUContext13processFPInitEP19sAMDSPUContextMsgInP20sAMDSPUContextMsgOut 000000000001cb4a g 0f SECT 01 0000 [.text] __ZN28AMDRadeonX4000_AMDSPUContext13processSPUMsgEP13IOFramebufferPv 000000000001d416 g 0f SECT 01 0000 [.text] __ZN28AMDRadeonX4000_AMDSPUContext13setTimedEventEP26AMDRadeonX4000_AMDSPUEventPv13_SPUEventTypej 000000000001d172 g 0f SECT 01 0000 [.text] __ZN28AMDRadeonX4000_AMDSPUContext13waitForAppMsgEP27AMDRadeonX4000_AMDSMLSPUMsg 000000000001c568 g 0f SECT 01 0000 [.text] __ZN28AMDRadeonX4000_AMDSPUContext14checkStatusErrEv 000000000001e1fa g 0f SECT 01 0000 [.text] __ZN28AMDRadeonX4000_AMDSPUContext14fairplayUnloadEj 000000000001ccc2 g 0f SECT 01 0000 [.text] __ZN28AMDRadeonX4000_AMDSPUContext14findAppContextE17_AMD_SPU_APP_TYPEPj 000000000001daa4 g 0f SECT 01 0000 [.text] __ZN28AMDRadeonX4000_AMDSPUContext14hdcpLinkStatusEP18_AmdHdcpMessageSPU 000000000001e7dc g 0f SECT 01 0000 [.text] __ZN28AMDRadeonX4000_AMDSPUContext14processMailboxEP19sAMDSPUContextMsgIn 000000000001e054 g 0f SECT 01 0000 [.text] __ZN28AMDRadeonX4000_AMDSPUContext14releaseMailboxEv 000000000001e7f6 g 0f SECT 01 0000 [.text] __ZN28AMDRadeonX4000_AMDSPUContext15allocateMailboxEj 000000000001c3c6 g 0f SECT 01 0000 [.text] __ZN28AMDRadeonX4000_AMDSPUContext15enableSPUThreadEv 000000000001e698 g 0f SECT 01 0000 [.text] __ZN28AMDRadeonX4000_AMDSPUContext15fairplayEncryptEP23_SPUCMDPARAM_FP_ENCRYPT 000000000001e21e g 0f SECT 01 0000 [.text] __ZN28AMDRadeonX4000_AMDSPUContext15fairplayGetCertEP24_SPUCMDPARAM_FP_GET_CERT 000000000001d468 g 0f SECT 01 0000 [.text] __ZN28AMDRadeonX4000_AMDSPUContext15processhdcpInitEP18_SPUHDCPEventParam 000000000001cbc2 g 0f SECT 01 0000 [.text] __ZN28AMDRadeonX4000_AMDSPUContext16createAppContextE17_AMD_SPU_APP_TYPEPjPP31AMDRadeonX4000_AMDSPUAppContext 000000000001c4a6 g 0f SECT 01 0000 [.text] __ZN28AMDRadeonX4000_AMDSPUContext16disableSPUThreadEv 000000000001c9bc g 0f SECT 01 0000 [.text] __ZN28AMDRadeonX4000_AMDSPUContext16getCommandBufferEv 000000000001d9c8 g 0f SECT 01 0000 [.text] __ZN28AMDRadeonX4000_AMDSPUContext16hdcpCloseSessionEP31_SPUCMDPARAM_HDCP_CLOSE_SESSION 000000000001e094 g 0f SECT 01 0000 [.text] __ZN28AMDRadeonX4000_AMDSPUContext16processFPEncryptEP19sAMDSPUContextMsgInyyPy 000000000001dd4c g 0f SECT 01 0000 [.text] __ZN28AMDRadeonX4000_AMDSPUContext16processFPGetCertEP19sAMDSPUContextMsgIny 000000000001dfd0 g 0f SECT 01 0000 [.text] __ZN28AMDRadeonX4000_AMDSPUContext16processFPReleaseEv 000000000001c2b0 g 0f SECT 01 0000 [.text] __ZN28AMDRadeonX4000_AMDSPUContext16releaseSPUThreadEv 000000000001c686 g 0f SECT 01 0000 [.text] __ZN28AMDRadeonX4000_AMDSPUContext17handleSPUMsgEventEP8OSObjectPv 000000000001cc8c g 0f SECT 01 0000 [.text] __ZN28AMDRadeonX4000_AMDSPUContext17releaseAppContextEj 000000000001e866 g 0f SECT 01 0000 [.text] __ZN28AMDRadeonX4000_AMDSPUContext17setPremiumContentEb 000000000001e366 g 0f SECT 01 0000 [.text] __ZN28AMDRadeonX4000_AMDSPUContext18fairplayGenASMFKeyEP28_SPUCMDPARAM_FP_GEN_ASMF_KEY 000000000001c770 g 0f SECT 01 0000 [.text] __ZN28AMDRadeonX4000_AMDSPUContext18handleSPUHDCPEventEP8OSObjectPv 000000000001c976 g 0f SECT 01 0000 [.text] __ZN28AMDRadeonX4000_AMDSPUContext19clientMemoryForTypeEjPjPP18IOMemoryDescriptor 000000000001e554 g 0f SECT 01 0000 [.text] __ZN28AMDRadeonX4000_AMDSPUContext19fairplayTestASMFKeyEP29_SPUCMDPARAM_FP_TEST_ASMF_KEY 000000000001d79e g 0f SECT 01 0000 [.text] __ZN28AMDRadeonX4000_AMDSPUContext19hdcpOpenSessionInitEP27AMDRadeonX4000_AMDSMLSPUMsgP18_AmdHdcpMessageSPU 000000000001de0c g 0f SECT 01 0000 [.text] __ZN28AMDRadeonX4000_AMDSPUContext19processFPGenASMFKeyEP19sAMDSPUContextMsgInyyPy 000000000001caa6 g 0f SECT 01 0000 [.text] __ZN28AMDRadeonX4000_AMDSPUContext19submitCommandBufferEP14_SPUCmdBuffers 000000000001c588 g 0f SECT 01 0000 [.text] __ZN28AMDRadeonX4000_AMDSPUContext20handleSPUThreadTimerEP8OSObjectP18IOTimerEventSource 000000000001defc g 0f SECT 01 0000 [.text] __ZN28AMDRadeonX4000_AMDSPUContext20processFPTestASMFKeyEP19sAMDSPUContextMsgInyyPy 000000000001ca2e g 0f SECT 01 0000 [.text] __ZN28AMDRadeonX4000_AMDSPUContext21getGPCOMCommandBufferEv 000000000001d664 g 0f SECT 01 0000 [.text] __ZN28AMDRadeonX4000_AMDSPUContext21processhdcpLinkStatusEP18_SPUHDCPEventParam 000000000001c52a g 0f SECT 01 0000 [.text] __ZN28AMDRadeonX4000_AMDSPUContext21setSuspendResumeStateEb 000000000001e4ae g 0f SECT 01 0000 [.text] __ZN28AMDRadeonX4000_AMDSPUContext22fairplayReleaseSessionEP34_SPUCMDPARAM_FP_RELEASE_HW_SESSION 000000000001d936 g 0f SECT 01 0000 [.text] __ZN28AMDRadeonX4000_AMDSPUContext23hdcpOpenSessionCompleteEP27AMDRadeonX4000_AMDSMLSPUMsg 000000000001cafc g 0f SECT 01 0000 [.text] __ZN28AMDRadeonX4000_AMDSPUContext24submitGPCOMCommandBufferEP14_SPUCmdBuffers 000000000001c83e g 0f SECT 01 0000 [.text] __ZN28AMDRadeonX4000_AMDSPUContext27setMemoryAllocationsEnabledEb 000000000001c060 g 0f SECT 01 0000 [.text] __ZN28AMDRadeonX4000_AMDSPUContext4freeEv 000000000001bc28 g 0f SECT 01 0000 [.text] __ZN28AMDRadeonX4000_AMDSPUContext4initEP37AMDRadeonX4000_AMDGraphicsAcceleratorP30AMDRadeonX4000_IAMDHWInterface 000000000001c40a g 0f SECT 01 0000 [.text] __ZN28AMDRadeonX4000_AMDSPUContext4stopEb 000000000001c360 g 0f SECT 01 0000 [.text] __ZN28AMDRadeonX4000_AMDSPUContext5startEv 000000000001ce3e g 0f SECT 01 0000 [.text] __ZN28AMDRadeonX4000_AMDSPUContext7loadAppEP31AMDRadeonX4000_AMDSPUAppContext 000000000001d6f6 g 0f SECT 01 0000 [.text] __ZN28AMDRadeonX4000_AMDSPUContext8hdcpLoadEPj 000000000001d368 g 0f SECT 01 0000 [.text] __ZN28AMDRadeonX4000_AMDSPUContext8setEventEPv13_SPUEventType 000000000001ba96 g 0f SECT 01 0000 [.text] __ZN28AMDRadeonX4000_AMDSPUContext9MetaClassC1Ev 000000000001bb56 g 0f SECT 01 0000 [.text] __ZN28AMDRadeonX4000_AMDSPUContext9MetaClassC2Ev 000000000038fd98 g 0f SECT 08 0000 [.const_data] __ZN28AMDRadeonX4000_AMDSPUContext9metaClassE 000000000001cfbc g 0f SECT 01 0000 [.text] __ZN28AMDRadeonX4000_AMDSPUContext9unloadAppEP31AMDRadeonX4000_AMDSPUAppContext 000000000001baf2 g 0f SECT 01 0000 [.text] __ZN28AMDRadeonX4000_AMDSPUContextC1EPK11OSMetaClass 000000000001bbc8 g 0f SECT 01 0000 [.text] __ZN28AMDRadeonX4000_AMDSPUContextC1Ev 000000000001bad2 g 0f SECT 01 0000 [.text] __ZN28AMDRadeonX4000_AMDSPUContextC2EPK11OSMetaClass 000000000001bbf8 g 0f SECT 01 0000 [.text] __ZN28AMDRadeonX4000_AMDSPUContextC2Ev 000000000001bb26 g 0f SECT 01 0000 [.text] __ZN28AMDRadeonX4000_AMDSPUContextD0Ev 000000000001bb1c g 0f SECT 01 0000 [.text] __ZN28AMDRadeonX4000_AMDSPUContextD1Ev 000000000001bb12 g 0f SECT 01 0000 [.text] __ZN28AMDRadeonX4000_AMDSPUContextD2Ev 000000000001fb4c g 0f SECT 01 0000 [.text] __ZN28AMDRadeonX4000_AMDTPTManager10fillBufferEyjj 000000000052d160 g 0f SECT 0a 0000 [__DATA.__common] __ZN28AMDRadeonX4000_AMDTPTManager10gMetaClassE 0000000000390378 g 0f SECT 08 0000 [.const_data] __ZN28AMDRadeonX4000_AMDTPTManager10superClassE 000000000001fb96 g 0f SECT 01 0000 [.text] __ZN28AMDRadeonX4000_AMDTPTManager13doSurfaceCopyEP16sDTCParametersInP17sDTCParametersOutP13_AMDTPTMemoryS5_ 000000000001faae g 0f SECT 01 0000 [.text] __ZN28AMDRadeonX4000_AMDTPTManager13releaseBufferEP13_AMDTPTMemoryj 00000000000211f0 g 0f SECT 01 0000 [.text] __ZN28AMDRadeonX4000_AMDTPTManager14doBiDirMemCopyEP16sDTCParametersInP17sDTCParametersOutP13_AMDTPTMemoryS5_ 000000000002160c g 0f SECT 01 0000 [.text] __ZN28AMDRadeonX4000_AMDTPTManager14doDRMDMAMemcpyEP16sDTCParametersInP17sDTCParametersOutP13_AMDTPTMemoryS5_P11_DRMDMA_AES 000000000001f394 g 0f SECT 01 0000 [.text] __ZN28AMDRadeonX4000_AMDTPTManager16processDTCVectorEP16sDTCParametersInP17sDTCParametersOut 000000000001f978 g 0f SECT 01 0000 [.text] __ZN28AMDRadeonX4000_AMDTPTManager17allocateSysBufferEP13_AMDTPTMemoryj 000000000001fa54 g 0f SECT 01 0000 [.text] __ZN28AMDRadeonX4000_AMDTPTManager18allocateVRAMBufferEP13_AMDTPTMemoryj 00000000000204a8 g 0f SECT 01 0000 [.text] __ZN28AMDRadeonX4000_AMDTPTManager18doBiDirSurfaceCopyEP16sDTCParametersInP17sDTCParametersOutP13_AMDTPTMemoryS5_ 000000000001f328 g 0f SECT 01 0000 [.text] __ZN28AMDRadeonX4000_AMDTPTManager4freeEv 000000000001f2b2 g 0f SECT 01 0000 [.text] __ZN28AMDRadeonX4000_AMDTPTManager4initEP37AMDRadeonX4000_AMDGraphicsAccelerator 000000000001f120 g 0f SECT 01 0000 [.text] __ZN28AMDRadeonX4000_AMDTPTManager9MetaClassC1Ev 000000000001f1e0 g 0f SECT 01 0000 [.text] __ZN28AMDRadeonX4000_AMDTPTManager9MetaClassC2Ev 0000000000020df4 g 0f SECT 01 0000 [.text] __ZN28AMDRadeonX4000_AMDTPTManager9doMemCopyEP16sDTCParametersInP17sDTCParametersOutP13_AMDTPTMemoryS5_ 0000000000390370 g 0f SECT 08 0000 [.const_data] __ZN28AMDRadeonX4000_AMDTPTManager9metaClassE 000000000001f17c g 0f SECT 01 0000 [.text] __ZN28AMDRadeonX4000_AMDTPTManagerC1EPK11OSMetaClass 000000000001f252 g 0f SECT 01 0000 [.text] __ZN28AMDRadeonX4000_AMDTPTManagerC1Ev 000000000001f15c g 0f SECT 01 0000 [.text] __ZN28AMDRadeonX4000_AMDTPTManagerC2EPK11OSMetaClass 000000000001f282 g 0f SECT 01 0000 [.text] __ZN28AMDRadeonX4000_AMDTPTManagerC2Ev 000000000001f1b0 g 0f SECT 01 0000 [.text] __ZN28AMDRadeonX4000_AMDTPTManagerD0Ev 000000000001f1a6 g 0f SECT 01 0000 [.text] __ZN28AMDRadeonX4000_AMDTPTManagerD1Ev 000000000001f19c g 0f SECT 01 0000 [.text] __ZN28AMDRadeonX4000_AMDTPTManagerD2Ev 000000000052f0e8 g 0f SECT 0a 0000 [__DATA.__common] __ZN28AMDRadeonX4000_AMDUVDTrinity10gMetaClassE 00000000003c3808 g 0f SECT 08 0000 [.const_data] __ZN28AMDRadeonX4000_AMDUVDTrinity10superClassE 0000000000128236 g 0f SECT 01 0000 [.text] __ZN28AMDRadeonX4000_AMDUVDTrinity4freeEv 00000000001281c2 g 0f SECT 01 0000 [.text] __ZN28AMDRadeonX4000_AMDUVDTrinity4initEj 0000000000128030 g 0f SECT 01 0000 [.text] __ZN28AMDRadeonX4000_AMDUVDTrinity9MetaClassC1Ev 00000000001280f0 g 0f SECT 01 0000 [.text] __ZN28AMDRadeonX4000_AMDUVDTrinity9MetaClassC2Ev 00000000003c3800 g 0f SECT 08 0000 [.const_data] __ZN28AMDRadeonX4000_AMDUVDTrinity9metaClassE 000000000012808c g 0f SECT 01 0000 [.text] __ZN28AMDRadeonX4000_AMDUVDTrinityC1EPK11OSMetaClass 0000000000128162 g 0f SECT 01 0000 [.text] __ZN28AMDRadeonX4000_AMDUVDTrinityC1Ev 000000000012806c g 0f SECT 01 0000 [.text] __ZN28AMDRadeonX4000_AMDUVDTrinityC2EPK11OSMetaClass 0000000000128192 g 0f SECT 01 0000 [.text] __ZN28AMDRadeonX4000_AMDUVDTrinityC2Ev 00000000001280c0 g 0f SECT 01 0000 [.text] __ZN28AMDRadeonX4000_AMDUVDTrinityD0Ev 00000000001280b6 g 0f SECT 01 0000 [.text] __ZN28AMDRadeonX4000_AMDUVDTrinityD1Ev 00000000001280ac g 0f SECT 01 0000 [.text] __ZN28AMDRadeonX4000_AMDUVDTrinityD2Ev 000000000052dc98 g 0f SECT 0a 0000 [__DATA.__common] __ZN28AMDRadeonX4000_IAMDHWChannel10gMetaClassE 00000000003a5d10 g 0f SECT 08 0000 [.const_data] __ZN28AMDRadeonX4000_IAMDHWChannel10superClassE 000000000005314c g 0f SECT 01 0000 [.text] __ZN28AMDRadeonX4000_IAMDHWChannel9MetaClassC1Ev 00000000000531ec g 0f SECT 01 0000 [.text] __ZN28AMDRadeonX4000_IAMDHWChannel9MetaClassC2Ev 00000000003a5d08 g 0f SECT 08 0000 [.const_data] __ZN28AMDRadeonX4000_IAMDHWChannel9metaClassE 0000000000053188 g 0f SECT 01 0000 [.text] __ZN28AMDRadeonX4000_IAMDHWChannelC2EPK11OSMetaClass 00000000000531bc g 0f SECT 01 0000 [.text] __ZN28AMDRadeonX4000_IAMDHWChannelD0Ev 00000000000531b2 g 0f SECT 01 0000 [.text] __ZN28AMDRadeonX4000_IAMDHWChannelD1Ev 00000000000531a8 g 0f SECT 01 0000 [.text] __ZN28AMDRadeonX4000_IAMDHWChannelD2Ev 000000000052da90 g 0f SECT 0a 0000 [__DATA.__common] __ZN28AMDRadeonX4000_IAMDHWDisplay10gMetaClassE 00000000003a3860 g 0f SECT 08 0000 [.const_data] __ZN28AMDRadeonX4000_IAMDHWDisplay10superClassE 000000000005263a g 0f SECT 01 0000 [.text] __ZN28AMDRadeonX4000_IAMDHWDisplay9MetaClassC1Ev 00000000000526da g 0f SECT 01 0000 [.text] __ZN28AMDRadeonX4000_IAMDHWDisplay9MetaClassC2Ev 00000000003a3858 g 0f SECT 08 0000 [.const_data] __ZN28AMDRadeonX4000_IAMDHWDisplay9metaClassE 0000000000052676 g 0f SECT 01 0000 [.text] __ZN28AMDRadeonX4000_IAMDHWDisplayC2EPK11OSMetaClass 00000000000526aa g 0f SECT 01 0000 [.text] __ZN28AMDRadeonX4000_IAMDHWDisplayD0Ev 00000000000526a0 g 0f SECT 01 0000 [.text] __ZN28AMDRadeonX4000_IAMDHWDisplayD1Ev 0000000000052696 g 0f SECT 01 0000 [.text] __ZN28AMDRadeonX4000_IAMDHWDisplayD2Ev 000000000052dab8 g 0f SECT 0a 0000 [__DATA.__common] __ZN28AMDRadeonX4000_IAMDHWHandler10gMetaClassE 00000000003a3c70 g 0f SECT 08 0000 [.const_data] __ZN28AMDRadeonX4000_IAMDHWHandler10superClassE 0000000000052714 g 0f SECT 01 0000 [.text] __ZN28AMDRadeonX4000_IAMDHWHandler9MetaClassC1Ev 00000000000527b4 g 0f SECT 01 0000 [.text] __ZN28AMDRadeonX4000_IAMDHWHandler9MetaClassC2Ev 00000000003a3c68 g 0f SECT 08 0000 [.const_data] __ZN28AMDRadeonX4000_IAMDHWHandler9metaClassE 0000000000052750 g 0f SECT 01 0000 [.text] __ZN28AMDRadeonX4000_IAMDHWHandlerC2EPK11OSMetaClass 0000000000052784 g 0f SECT 01 0000 [.text] __ZN28AMDRadeonX4000_IAMDHWHandlerD0Ev 000000000005277a g 0f SECT 01 0000 [.text] __ZN28AMDRadeonX4000_IAMDHWHandlerD1Ev 0000000000052770 g 0f SECT 01 0000 [.text] __ZN28AMDRadeonX4000_IAMDHWHandlerD2Ev 000000000052d590 g 0f SECT 0a 0000 [__DATA.__common] __ZN28AMDTahitiGraphicsAccelerator10gMetaClassE 0000000000394e58 g 0f SECT 08 0000 [.const_data] __ZN28AMDTahitiGraphicsAccelerator10superClassE 0000000000029768 g 0f SECT 01 0000 [.text] __ZN28AMDTahitiGraphicsAccelerator13setDeviceTypeEP11IOPCIDevice 0000000000029742 g 0f SECT 01 0000 [.text] __ZN28AMDTahitiGraphicsAccelerator14newHWInterfaceEv 00000000000295b0 g 0f SECT 01 0000 [.text] __ZN28AMDTahitiGraphicsAccelerator9MetaClassC1Ev 0000000000029670 g 0f SECT 01 0000 [.text] __ZN28AMDTahitiGraphicsAccelerator9MetaClassC2Ev 0000000000394e50 g 0f SECT 08 0000 [.const_data] __ZN28AMDTahitiGraphicsAccelerator9metaClassE 000000000002960c g 0f SECT 01 0000 [.text] __ZN28AMDTahitiGraphicsAcceleratorC1EPK11OSMetaClass 00000000000296e2 g 0f SECT 01 0000 [.text] __ZN28AMDTahitiGraphicsAcceleratorC1Ev 00000000000295ec g 0f SECT 01 0000 [.text] __ZN28AMDTahitiGraphicsAcceleratorC2EPK11OSMetaClass 0000000000029712 g 0f SECT 01 0000 [.text] __ZN28AMDTahitiGraphicsAcceleratorC2Ev 0000000000029640 g 0f SECT 01 0000 [.text] __ZN28AMDTahitiGraphicsAcceleratorD0Ev 0000000000029636 g 0f SECT 01 0000 [.text] __ZN28AMDTahitiGraphicsAcceleratorD1Ev 000000000002962c g 0f SECT 01 0000 [.text] __ZN28AMDTahitiGraphicsAcceleratorD2Ev 000000000052d720 g 0f SECT 0a 0000 [__DATA.__common] __ZN29AMDBonaireGraphicsAccelerator10gMetaClassE 000000000039b958 g 0f SECT 08 0000 [.const_data] __ZN29AMDBonaireGraphicsAccelerator10superClassE 000000000003d382 g 0f SECT 01 0000 [.text] __ZN29AMDBonaireGraphicsAccelerator14newHWInterfaceEv 000000000003d1f0 g 0f SECT 01 0000 [.text] __ZN29AMDBonaireGraphicsAccelerator9MetaClassC1Ev 000000000003d2b0 g 0f SECT 01 0000 [.text] __ZN29AMDBonaireGraphicsAccelerator9MetaClassC2Ev 000000000039b950 g 0f SECT 08 0000 [.const_data] __ZN29AMDBonaireGraphicsAccelerator9metaClassE 000000000003d24c g 0f SECT 01 0000 [.text] __ZN29AMDBonaireGraphicsAcceleratorC1EPK11OSMetaClass 000000000003d322 g 0f SECT 01 0000 [.text] __ZN29AMDBonaireGraphicsAcceleratorC1Ev 000000000003d22c g 0f SECT 01 0000 [.text] __ZN29AMDBonaireGraphicsAcceleratorC2EPK11OSMetaClass 000000000003d352 g 0f SECT 01 0000 [.text] __ZN29AMDBonaireGraphicsAcceleratorC2Ev 000000000003d280 g 0f SECT 01 0000 [.text] __ZN29AMDBonaireGraphicsAcceleratorD0Ev 000000000003d276 g 0f SECT 01 0000 [.text] __ZN29AMDBonaireGraphicsAcceleratorD1Ev 000000000003d26c g 0f SECT 01 0000 [.text] __ZN29AMDBonaireGraphicsAcceleratorD2Ev 000000000000580c g 0f SECT 01 0000 [.text] __ZN29AMDRadeonX4000_AMDAccelDevice10deviceStopEv 000000000052ceb8 g 0f SECT 0a 0000 [__DATA.__common] __ZN29AMDRadeonX4000_AMDAccelDevice10gMetaClassE 0000000000389d28 g 0f SECT 08 0000 [.const_data] __ZN29AMDRadeonX4000_AMDAccelDevice10superClassE 00000000000056b2 g 0f SECT 01 0000 [.text] __ZN29AMDRadeonX4000_AMDAccelDevice11deviceStartEv 00000000000056e8 g 0f SECT 01 0000 [.text] __ZN29AMDRadeonX4000_AMDAccelDevice15getHardwareInfoEP24_sAMD_GET_HW_INFO_VALUES 000000000000581e g 0f SECT 01 0000 [.text] __ZN29AMDRadeonX4000_AMDAccelDevice26getTargetAndMethodForIndexEPP9IOServicej 0000000000005520 g 0f SECT 01 0000 [.text] __ZN29AMDRadeonX4000_AMDAccelDevice9MetaClassC1Ev 00000000000055e0 g 0f SECT 01 0000 [.text] __ZN29AMDRadeonX4000_AMDAccelDevice9MetaClassC2Ev 0000000000389d20 g 0f SECT 08 0000 [.const_data] __ZN29AMDRadeonX4000_AMDAccelDevice9metaClassE 000000000000557c g 0f SECT 01 0000 [.text] __ZN29AMDRadeonX4000_AMDAccelDeviceC1EPK11OSMetaClass 0000000000005652 g 0f SECT 01 0000 [.text] __ZN29AMDRadeonX4000_AMDAccelDeviceC1Ev 000000000000555c g 0f SECT 01 0000 [.text] __ZN29AMDRadeonX4000_AMDAccelDeviceC2EPK11OSMetaClass 0000000000005682 g 0f SECT 01 0000 [.text] __ZN29AMDRadeonX4000_AMDAccelDeviceC2Ev 00000000000055b0 g 0f SECT 01 0000 [.text] __ZN29AMDRadeonX4000_AMDAccelDeviceD0Ev 00000000000055a6 g 0f SECT 01 0000 [.text] __ZN29AMDRadeonX4000_AMDAccelDeviceD1Ev 000000000000559c g 0f SECT 01 0000 [.text] __ZN29AMDRadeonX4000_AMDAccelDeviceD2Ev 000000000052cf58 g 0f SECT 0a 0000 [__DATA.__common] __ZN29AMDRadeonX4000_AMDAccelShared10gMetaClassE 000000000038ba38 g 0f SECT 08 0000 [.const_data] __ZN29AMDRadeonX4000_AMDAccelShared10superClassE 0000000000011b06 g 0f SECT 01 0000 [.text] __ZN29AMDRadeonX4000_AMDAccelShared11SurfaceCopyEPjyP12IOAccelEvent 0000000000011af4 g 0f SECT 01 0000 [.text] __ZN29AMDRadeonX4000_AMDAccelShared4freeEv 0000000000011ae2 g 0f SECT 01 0000 [.text] __ZN29AMDRadeonX4000_AMDAccelShared4initEP22IOGraphicsAccelerator2P4task 0000000000011950 g 0f SECT 01 0000 [.text] __ZN29AMDRadeonX4000_AMDAccelShared9MetaClassC1Ev 0000000000011a10 g 0f SECT 01 0000 [.text] __ZN29AMDRadeonX4000_AMDAccelShared9MetaClassC2Ev 000000000038ba30 g 0f SECT 08 0000 [.const_data] __ZN29AMDRadeonX4000_AMDAccelShared9metaClassE 00000000000119ac g 0f SECT 01 0000 [.text] __ZN29AMDRadeonX4000_AMDAccelSharedC1EPK11OSMetaClass 0000000000011a82 g 0f SECT 01 0000 [.text] __ZN29AMDRadeonX4000_AMDAccelSharedC1Ev 000000000001198c g 0f SECT 01 0000 [.text] __ZN29AMDRadeonX4000_AMDAccelSharedC2EPK11OSMetaClass 0000000000011ab2 g 0f SECT 01 0000 [.text] __ZN29AMDRadeonX4000_AMDAccelSharedC2Ev 00000000000119e0 g 0f SECT 01 0000 [.text] __ZN29AMDRadeonX4000_AMDAccelSharedD0Ev 00000000000119d6 g 0f SECT 01 0000 [.text] __ZN29AMDRadeonX4000_AMDAccelSharedD1Ev 00000000000119cc g 0f SECT 01 0000 [.text] __ZN29AMDRadeonX4000_AMDAccelSharedD2Ev 000000000052d978 g 0f SECT 0a 0000 [__DATA.__common] __ZN29AMDRadeonX4000_AMDDMAHWEngine10gMetaClassE 00000000003a20c8 g 0f SECT 08 0000 [.const_data] __ZN29AMDRadeonX4000_AMDDMAHWEngine10superClassE 000000000004f21c g 0f SECT 01 0000 [.text] __ZN29AMDRadeonX4000_AMDDMAHWEngine4freeEv 000000000004f17a g 0f SECT 01 0000 [.text] __ZN29AMDRadeonX4000_AMDDMAHWEngine4initEP30AMDRadeonX4000_IAMDHWInterface20_eAMD_HW_ENGINE_TYPE 000000000004f292 g 0f SECT 01 0000 [.text] __ZN29AMDRadeonX4000_AMDDMAHWEngine7powerUpEv 000000000004f2bc g 0f SECT 01 0000 [.text] __ZN29AMDRadeonX4000_AMDDMAHWEngine8doMemcpyEyyjP11_DRMDMA_AES 000000000004f29a g 0f SECT 01 0000 [.text] __ZN29AMDRadeonX4000_AMDDMAHWEngine8powerOffEv 000000000004f0a0 g 0f SECT 01 0000 [.text] __ZN29AMDRadeonX4000_AMDDMAHWEngine9MetaClassC1Ev 000000000004f140 g 0f SECT 01 0000 [.text] __ZN29AMDRadeonX4000_AMDDMAHWEngine9MetaClassC2Ev 00000000003a20c0 g 0f SECT 08 0000 [.const_data] __ZN29AMDRadeonX4000_AMDDMAHWEngine9metaClassE 000000000004f0dc g 0f SECT 01 0000 [.text] __ZN29AMDRadeonX4000_AMDDMAHWEngineC2EPK11OSMetaClass 000000000004f110 g 0f SECT 01 0000 [.text] __ZN29AMDRadeonX4000_AMDDMAHWEngineD0Ev 000000000004f106 g 0f SECT 01 0000 [.text] __ZN29AMDRadeonX4000_AMDDMAHWEngineD1Ev 000000000004f0fc g 0f SECT 01 0000 [.text] __ZN29AMDRadeonX4000_AMDDMAHWEngineD2Ev 000000000052f020 g 0f SECT 0a 0000 [__DATA.__common] __ZN29AMDRadeonX4000_AMDFPGenKeyMsg10gMetaClassE 00000000003c2a70 g 0f SECT 08 0000 [.const_data] __ZN29AMDRadeonX4000_AMDFPGenKeyMsg10superClassE 00000000001270f2 g 0f SECT 01 0000 [.text] __ZN29AMDRadeonX4000_AMDFPGenKeyMsg12setOutBufferEiyPh 00000000001270e0 g 0f SECT 01 0000 [.text] __ZN29AMDRadeonX4000_AMDFPGenKeyMsg4freeEv 0000000000126fca g 0f SECT 01 0000 [.text] __ZN29AMDRadeonX4000_AMDFPGenKeyMsg4initEPv 0000000000126e38 g 0f SECT 01 0000 [.text] __ZN29AMDRadeonX4000_AMDFPGenKeyMsg9MetaClassC1Ev 0000000000126ef8 g 0f SECT 01 0000 [.text] __ZN29AMDRadeonX4000_AMDFPGenKeyMsg9MetaClassC2Ev 0000000000127132 g 0f SECT 01 0000 [.text] __ZN29AMDRadeonX4000_AMDFPGenKeyMsg9getOutputEv 00000000003c2a68 g 0f SECT 08 0000 [.const_data] __ZN29AMDRadeonX4000_AMDFPGenKeyMsg9metaClassE 0000000000126e94 g 0f SECT 01 0000 [.text] __ZN29AMDRadeonX4000_AMDFPGenKeyMsgC1EPK11OSMetaClass 0000000000126f6a g 0f SECT 01 0000 [.text] __ZN29AMDRadeonX4000_AMDFPGenKeyMsgC1Ev 0000000000126e74 g 0f SECT 01 0000 [.text] __ZN29AMDRadeonX4000_AMDFPGenKeyMsgC2EPK11OSMetaClass 0000000000126f9a g 0f SECT 01 0000 [.text] __ZN29AMDRadeonX4000_AMDFPGenKeyMsgC2Ev 0000000000126ec8 g 0f SECT 01 0000 [.text] __ZN29AMDRadeonX4000_AMDFPGenKeyMsgD0Ev 0000000000126ebe g 0f SECT 01 0000 [.text] __ZN29AMDRadeonX4000_AMDFPGenKeyMsgD1Ev 0000000000126eb4 g 0f SECT 01 0000 [.text] __ZN29AMDRadeonX4000_AMDFPGenKeyMsgD2Ev 000000000052dd38 g 0f SECT 0a 0000 [__DATA.__common] __ZN29AMDRadeonX4000_AMDHWRegisters10gMetaClassE 00000000003a69c8 g 0f SECT 08 0000 [.const_data] __ZN29AMDRadeonX4000_AMDHWRegisters10superClassE 0000000000055a28 g 0f SECT 01 0000 [.text] __ZN29AMDRadeonX4000_AMDHWRegisters17readOrModifyWriteEjj 0000000000055a66 g 0f SECT 01 0000 [.text] __ZN29AMDRadeonX4000_AMDHWRegisters18readAndModifyWriteEjj 0000000000055aa4 g 0f SECT 01 0000 [.text] __ZN29AMDRadeonX4000_AMDHWRegisters20readAndOrModifyWriteEjjj 0000000000055ae6 g 0f SECT 01 0000 [.text] __ZN29AMDRadeonX4000_AMDHWRegisters20readOrAndModifyWriteEjjj 0000000000055882 g 0f SECT 01 0000 [.text] __ZN29AMDRadeonX4000_AMDHWRegisters4freeEv 00000000000557a2 g 0f SECT 01 0000 [.text] __ZN29AMDRadeonX4000_AMDHWRegisters4initEP11IOPCIDeviceP30AMDRadeonX4000_IAMDHWInterface 00000000000558ee g 0f SECT 01 0000 [.text] __ZN29AMDRadeonX4000_AMDHWRegisters4readEj 0000000000055980 g 0f SECT 01 0000 [.text] __ZN29AMDRadeonX4000_AMDHWRegisters5writeEjj 0000000000055b28 g 0f SECT 01 0000 [.text] __ZN29AMDRadeonX4000_AMDHWRegisters6enableEv 0000000000055b40 g 0f SECT 01 0000 [.text] __ZN29AMDRadeonX4000_AMDHWRegisters7disableEv 0000000000055610 g 0f SECT 01 0000 [.text] __ZN29AMDRadeonX4000_AMDHWRegisters9MetaClassC1Ev 00000000000556d0 g 0f SECT 01 0000 [.text] __ZN29AMDRadeonX4000_AMDHWRegisters9MetaClassC2Ev 00000000003a69c0 g 0f SECT 08 0000 [.const_data] __ZN29AMDRadeonX4000_AMDHWRegisters9metaClassE 000000000005566c g 0f SECT 01 0000 [.text] __ZN29AMDRadeonX4000_AMDHWRegistersC1EPK11OSMetaClass 0000000000055742 g 0f SECT 01 0000 [.text] __ZN29AMDRadeonX4000_AMDHWRegistersC1Ev 000000000005564c g 0f SECT 01 0000 [.text] __ZN29AMDRadeonX4000_AMDHWRegistersC2EPK11OSMetaClass 0000000000055772 g 0f SECT 01 0000 [.text] __ZN29AMDRadeonX4000_AMDHWRegistersC2Ev 00000000000556a0 g 0f SECT 01 0000 [.text] __ZN29AMDRadeonX4000_AMDHWRegistersD0Ev 0000000000055696 g 0f SECT 01 0000 [.text] __ZN29AMDRadeonX4000_AMDHWRegistersD1Ev 000000000005568c g 0f SECT 01 0000 [.text] __ZN29AMDRadeonX4000_AMDHWRegistersD2Ev 000000000052dd88 g 0f SECT 0a 0000 [__DATA.__common] __ZN29AMDRadeonX4000_AMDHWSemaphore10gMetaClassE 00000000003a6f68 g 0f SECT 08 0000 [.const_data] __ZN29AMDRadeonX4000_AMDHWSemaphore10superClassE 0000000000056bd0 g 0f SECT 01 0000 [.text] __ZN29AMDRadeonX4000_AMDHWSemaphore4doneEv 00000000000569ca g 0f SECT 01 0000 [.text] __ZN29AMDRadeonX4000_AMDHWSemaphore4freeEv 00000000000568f2 g 0f SECT 01 0000 [.text] __ZN29AMDRadeonX4000_AMDHWSemaphore4initEP30AMDRadeonX4000_IAMDHWInterfaceyPyy 0000000000056a9a g 0f SECT 01 0000 [.text] __ZN29AMDRadeonX4000_AMDHWSemaphore4waitEP12IOAccelEventiPjRj 0000000000056c08 g 0f SECT 01 0000 [.text] __ZN29AMDRadeonX4000_AMDHWSemaphore5resetEv 0000000000056b1a g 0f SECT 01 0000 [.text] __ZN29AMDRadeonX4000_AMDHWSemaphore6signalEP12IOAccelEventiPjRj 0000000000056c4a g 0f SECT 01 0000 [.text] __ZN29AMDRadeonX4000_AMDHWSemaphore8setStateEb 0000000000056760 g 0f SECT 01 0000 [.text] __ZN29AMDRadeonX4000_AMDHWSemaphore9MetaClassC1Ev 0000000000056820 g 0f SECT 01 0000 [.text] __ZN29AMDRadeonX4000_AMDHWSemaphore9MetaClassC2Ev 00000000003a6f60 g 0f SECT 08 0000 [.const_data] __ZN29AMDRadeonX4000_AMDHWSemaphore9metaClassE 00000000000567bc g 0f SECT 01 0000 [.text] __ZN29AMDRadeonX4000_AMDHWSemaphoreC1EPK11OSMetaClass 0000000000056892 g 0f SECT 01 0000 [.text] __ZN29AMDRadeonX4000_AMDHWSemaphoreC1Ev 000000000005679c g 0f SECT 01 0000 [.text] __ZN29AMDRadeonX4000_AMDHWSemaphoreC2EPK11OSMetaClass 00000000000568c2 g 0f SECT 01 0000 [.text] __ZN29AMDRadeonX4000_AMDHWSemaphoreC2Ev 00000000000567f0 g 0f SECT 01 0000 [.text] __ZN29AMDRadeonX4000_AMDHWSemaphoreD0Ev 00000000000567e6 g 0f SECT 01 0000 [.text] __ZN29AMDRadeonX4000_AMDHWSemaphoreD1Ev 00000000000567dc g 0f SECT 01 0000 [.text] __ZN29AMDRadeonX4000_AMDHWSemaphoreD2Ev 000000000052d8d8 g 0f SECT 0a 0000 [__DATA.__common] __ZN29AMDRadeonX4000_AMDHWUtilities10gMetaClassE 00000000003a1338 g 0f SECT 08 0000 [.const_data] __ZN29AMDRadeonX4000_AMDHWUtilities10superClassE 000000000004e1f4 g 0f SECT 01 0000 [.text] __ZN29AMDRadeonX4000_AMDHWUtilities16setupUBMChipInfoEP13_UBM_CHIPINFO 000000000004e1da g 0f SECT 01 0000 [.text] __ZN29AMDRadeonX4000_AMDHWUtilities17validateMemCpyDMAEP15_UBM_MEMCPYINFO 000000000004e130 g 0f SECT 01 0000 [.text] __ZN29AMDRadeonX4000_AMDHWUtilities22validateSurfaceCopyDMAEP20_UBM_SURFACECOPYINFOj 000000000004e0fa g 0f SECT 01 0000 [.text] __ZN29AMDRadeonX4000_AMDHWUtilities4freeEv 000000000004e0ba g 0f SECT 01 0000 [.text] __ZN29AMDRadeonX4000_AMDHWUtilities4initEP30AMDRadeonX4000_IAMDHWInterface 000000000004dfe0 g 0f SECT 01 0000 [.text] __ZN29AMDRadeonX4000_AMDHWUtilities9MetaClassC1Ev 000000000004e080 g 0f SECT 01 0000 [.text] __ZN29AMDRadeonX4000_AMDHWUtilities9MetaClassC2Ev 00000000003a1330 g 0f SECT 08 0000 [.const_data] __ZN29AMDRadeonX4000_AMDHWUtilities9metaClassE 000000000004e01c g 0f SECT 01 0000 [.text] __ZN29AMDRadeonX4000_AMDHWUtilitiesC2EPK11OSMetaClass 000000000004e050 g 0f SECT 01 0000 [.text] __ZN29AMDRadeonX4000_AMDHWUtilitiesD0Ev 000000000004e046 g 0f SECT 01 0000 [.text] __ZN29AMDRadeonX4000_AMDHWUtilitiesD1Ev 000000000004e03c g 0f SECT 01 0000 [.text] __ZN29AMDRadeonX4000_AMDHWUtilitiesD2Ev 00000000000580aa g 0f SECT 01 0000 [.text] __ZN29AMDRadeonX4000_AMDHWVMContext10assignVMIDERjP28AMDRadeonX4000_IAMDHWChannelPP12IOAccelEventPb 000000000052de28 g 0f SECT 0a 0000 [__DATA.__common] __ZN29AMDRadeonX4000_AMDHWVMContext10gMetaClassE 00000000003a7978 g 0f SECT 08 0000 [.const_data] __ZN29AMDRadeonX4000_AMDHWVMContext10superClassE 0000000000058526 g 0f SECT 01 0000 [.text] __ZN29AMDRadeonX4000_AMDHWVMContext12clearWithDMAEyy 0000000000058414 g 0f SECT 01 0000 [.text] __ZN29AMDRadeonX4000_AMDHWVMContext13endDMAUpdatesEv 0000000000058154 g 0f SECT 01 0000 [.text] __ZN29AMDRadeonX4000_AMDHWVMContext13setDMAUpdatesEbP20IOAccelEventMachine2PP25IOAccelCommandBufferPool2 00000000000583fa g 0f SECT 01 0000 [.text] __ZN29AMDRadeonX4000_AMDHWVMContext15beginDMAUpdatesEv 000000000005862c g 0f SECT 01 0000 [.text] __ZN29AMDRadeonX4000_AMDHWVMContext15clearPDEWithDMAEy 0000000000058646 g 0f SECT 01 0000 [.text] __ZN29AMDRadeonX4000_AMDHWVMContext16clearPTEsWithDMAEyyy 0000000000058676 g 0f SECT 01 0000 [.text] __ZN29AMDRadeonX4000_AMDHWVMContext16updatePDEWithDMAEyPy 000000000005844c g 0f SECT 01 0000 [.text] __ZN29AMDRadeonX4000_AMDHWVMContext19invalidateVMWithDMAEjb 00000000000584cc g 0f SECT 01 0000 [.text] __ZN29AMDRadeonX4000_AMDHWVMContext20getDMABufferPtrNoIncEj 00000000000581f6 g 0f SECT 01 0000 [.text] __ZN29AMDRadeonX4000_AMDHWVMContext21preparePDForCPUAccessEPP11IOMemoryMap 00000000000586f6 g 0f SECT 01 0000 [.text] __ZN29AMDRadeonX4000_AMDHWVMContext21updateLocalPTEWithDMAEyyyyy 0000000000058296 g 0f SECT 01 0000 [.text] __ZN29AMDRadeonX4000_AMDHWVMContext22completePDForCPUAccessEPP11IOMemoryMap 00000000000582e4 g 0f SECT 01 0000 [.text] __ZN29AMDRadeonX4000_AMDHWVMContext22preparePTBForCPUAccessEPP11IOMemoryMapy 000000000005888e g 0f SECT 01 0000 [.text] __ZN29AMDRadeonX4000_AMDHWVMContext22updateSystemPTEWithDMAEyyyy 00000000000583a4 g 0f SECT 01 0000 [.text] __ZN29AMDRadeonX4000_AMDHWVMContext23completePTBForCPUAccessEPP11IOMemoryMapy 00000000000581ec g 0f SECT 01 0000 [.text] __ZN29AMDRadeonX4000_AMDHWVMContext23getPageTableUpdateEventEv 0000000000057f32 g 0f SECT 01 0000 [.text] __ZN29AMDRadeonX4000_AMDHWVMContext4freeEv 0000000000057dca g 0f SECT 01 0000 [.text] __ZN29AMDRadeonX4000_AMDHWVMContext4initEP30AMDRadeonX4000_IAMDHWInterfaceP24AMDRadeonX4000_IAMDHWVMM 0000000000058b1e g 0f SECT 01 0000 [.text] __ZN29AMDRadeonX4000_AMDHWVMContext8pageOnPDEv 0000000000057cf0 g 0f SECT 01 0000 [.text] __ZN29AMDRadeonX4000_AMDHWVMContext9MetaClassC1Ev 0000000000057d90 g 0f SECT 01 0000 [.text] __ZN29AMDRadeonX4000_AMDHWVMContext9MetaClassC2Ev 00000000003a7970 g 0f SECT 08 0000 [.const_data] __ZN29AMDRadeonX4000_AMDHWVMContext9metaClassE 00000000000589e0 g 0f SECT 01 0000 [.text] __ZN29AMDRadeonX4000_AMDHWVMContext9pageOffPDEv 0000000000057d2c g 0f SECT 01 0000 [.text] __ZN29AMDRadeonX4000_AMDHWVMContextC2EPK11OSMetaClass 0000000000057d60 g 0f SECT 01 0000 [.text] __ZN29AMDRadeonX4000_AMDHWVMContextD0Ev 0000000000057d56 g 0f SECT 01 0000 [.text] __ZN29AMDRadeonX4000_AMDHWVMContextD1Ev 0000000000057d4c g 0f SECT 01 0000 [.text] __ZN29AMDRadeonX4000_AMDHWVMContextD2Ev 000000000052def0 g 0f SECT 0a 0000 [__DATA.__common] __ZN29AMDRadeonX4000_AMDPM4HWEngine10gMetaClassE 00000000003a8b98 g 0f SECT 08 0000 [.const_data] __ZN29AMDRadeonX4000_AMDPM4HWEngine10superClassE 000000000005eaf0 g 0f SECT 01 0000 [.text] __ZN29AMDRadeonX4000_AMDPM4HWEngine26systemWillChangeSpeedEventEv 000000000005eb1c g 0f SECT 01 0000 [.text] __ZN29AMDRadeonX4000_AMDPM4HWEngine33initializeSubmitCommandBufferInfoEP30AMD_SUBMIT_COMMAND_BUFFER_INFO 000000000005e8fc g 0f SECT 01 0000 [.text] __ZN29AMDRadeonX4000_AMDPM4HWEngine4freeEv 000000000005e8da g 0f SECT 01 0000 [.text] __ZN29AMDRadeonX4000_AMDPM4HWEngine4initEP30AMDRadeonX4000_IAMDHWInterface20_eAMD_HW_ENGINE_TYPE 000000000005ea3c g 0f SECT 01 0000 [.text] __ZN29AMDRadeonX4000_AMDPM4HWEngine4stopEv 000000000005e9c2 g 0f SECT 01 0000 [.text] __ZN29AMDRadeonX4000_AMDPM4HWEngine5startEv 000000000005e90e g 0f SECT 01 0000 [.text] __ZN29AMDRadeonX4000_AMDPM4HWEngine7powerUpEv 000000000005e9b4 g 0f SECT 01 0000 [.text] __ZN29AMDRadeonX4000_AMDPM4HWEngine8powerOffEv 000000000005e800 g 0f SECT 01 0000 [.text] __ZN29AMDRadeonX4000_AMDPM4HWEngine9MetaClassC1Ev 000000000005e8a0 g 0f SECT 01 0000 [.text] __ZN29AMDRadeonX4000_AMDPM4HWEngine9MetaClassC2Ev 00000000003a8b90 g 0f SECT 08 0000 [.const_data] __ZN29AMDRadeonX4000_AMDPM4HWEngine9metaClassE 000000000005e83c g 0f SECT 01 0000 [.text] __ZN29AMDRadeonX4000_AMDPM4HWEngineC2EPK11OSMetaClass 000000000005e870 g 0f SECT 01 0000 [.text] __ZN29AMDRadeonX4000_AMDPM4HWEngineD0Ev 000000000005e866 g 0f SECT 01 0000 [.text] __ZN29AMDRadeonX4000_AMDPM4HWEngineD1Ev 000000000005e85c g 0f SECT 01 0000 [.text] __ZN29AMDRadeonX4000_AMDPM4HWEngineD2Ev 000000000052df40 g 0f SECT 0a 0000 [__DATA.__common] __ZN29AMDRadeonX4000_AMDSPUHWEngine10gMetaClassE 00000000003a92d8 g 0f SECT 08 0000 [.const_data] __ZN29AMDRadeonX4000_AMDSPUHWEngine10superClassE 000000000005f92a g 0f SECT 01 0000 [.text] __ZN29AMDRadeonX4000_AMDSPUHWEngine13initSPUMemoryEv 000000000005f972 g 0f SECT 01 0000 [.text] __ZN29AMDRadeonX4000_AMDSPUHWEngine13loadSPUKernelEv 000000000005f8e8 g 0f SECT 01 0000 [.text] __ZN29AMDRadeonX4000_AMDSPUHWEngine16releaseSPUMemoryEv 000000000005f654 g 0f SECT 01 0000 [.text] __ZN29AMDRadeonX4000_AMDSPUHWEngine17allocateSPUMemoryEv 000000000005f9d8 g 0f SECT 01 0000 [.text] __ZN29AMDRadeonX4000_AMDSPUHWEngine18initSPUBootControlEv 000000000005f54c g 0f SECT 01 0000 [.text] __ZN29AMDRadeonX4000_AMDSPUHWEngine19pageSPUReservedAreaEbj 000000000005f4a0 g 0f SECT 01 0000 [.text] __ZN29AMDRadeonX4000_AMDSPUHWEngine20setMemoryAllocationsEb 000000000005f4be g 0f SECT 01 0000 [.text] __ZN29AMDRadeonX4000_AMDSPUHWEngine20setupSPUReservedAreaEv 000000000005f402 g 0f SECT 01 0000 [.text] __ZN29AMDRadeonX4000_AMDSPUHWEngine21setSuspendResumeStateEb 000000000005f50a g 0f SECT 01 0000 [.text] __ZN29AMDRadeonX4000_AMDSPUHWEngine22releaseSPUReservedAreaEv 000000000005f370 g 0f SECT 01 0000 [.text] __ZN29AMDRadeonX4000_AMDSPUHWEngine25setPowerRegistrationStateEb 000000000005f49a g 0f SECT 01 0000 [.text] __ZN29AMDRadeonX4000_AMDSPUHWEngine27setMemoryAllocationsEnabledEb 000000000005f228 g 0f SECT 01 0000 [.text] __ZN29AMDRadeonX4000_AMDSPUHWEngine4freeEv 000000000005f12a g 0f SECT 01 0000 [.text] __ZN29AMDRadeonX4000_AMDSPUHWEngine4initEP30AMDRadeonX4000_IAMDHWInterface20_eAMD_HW_ENGINE_TYPE 000000000005f324 g 0f SECT 01 0000 [.text] __ZN29AMDRadeonX4000_AMDSPUHWEngine4stopEv 000000000005f2d0 g 0f SECT 01 0000 [.text] __ZN29AMDRadeonX4000_AMDSPUHWEngine5startEv 000000000005f2c0 g 0f SECT 01 0000 [.text] __ZN29AMDRadeonX4000_AMDSPUHWEngine7powerUpEv 000000000005f2c8 g 0f SECT 01 0000 [.text] __ZN29AMDRadeonX4000_AMDSPUHWEngine8powerOffEv 000000000005f050 g 0f SECT 01 0000 [.text] __ZN29AMDRadeonX4000_AMDSPUHWEngine9MetaClassC1Ev 000000000005f0f0 g 0f SECT 01 0000 [.text] __ZN29AMDRadeonX4000_AMDSPUHWEngine9MetaClassC2Ev 00000000003a92d0 g 0f SECT 08 0000 [.const_data] __ZN29AMDRadeonX4000_AMDSPUHWEngine9metaClassE 000000000005f08c g 0f SECT 01 0000 [.text] __ZN29AMDRadeonX4000_AMDSPUHWEngineC2EPK11OSMetaClass 000000000005f0c0 g 0f SECT 01 0000 [.text] __ZN29AMDRadeonX4000_AMDSPUHWEngineD0Ev 000000000005f0b6 g 0f SECT 01 0000 [.text] __ZN29AMDRadeonX4000_AMDSPUHWEngineD1Ev 000000000005f0ac g 0f SECT 01 0000 [.text] __ZN29AMDRadeonX4000_AMDSPUHWEngineD2Ev 0000000000061bf6 g 0f SECT 01 0000 [.text] __ZN29AMDRadeonX4000_AMDUVDHWEngine10findClientEj 000000000052dfe0 g 0f SECT 0a 0000 [__DATA.__common] __ZN29AMDRadeonX4000_AMDUVDHWEngine10gMetaClassE 00000000003aa1e8 g 0f SECT 08 0000 [.const_data] __ZN29AMDRadeonX4000_AMDUVDHWEngine10superClassE 0000000000062656 g 0f SECT 01 0000 [.text] __ZN29AMDRadeonX4000_AMDUVDHWEngine11setVclkDclkEjj 0000000000061b9a g 0f SECT 01 0000 [.text] __ZN29AMDRadeonX4000_AMDUVDHWEngine12removeClientEj 000000000006229a g 0f SECT 01 0000 [.text] __ZN29AMDRadeonX4000_AMDUVDHWEngine12restoreStateEjP12_SML_UVD_MSGb 000000000006132c g 0f SECT 01 0000 [.text] __ZN29AMDRadeonX4000_AMDUVDHWEngine12start_EngineEv 000000000006157c g 0f SECT 01 0000 [.text] __ZN29AMDRadeonX4000_AMDUVDHWEngine12stopRBEngineEv 00000000000619d0 g 0f SECT 01 0000 [.text] __ZN29AMDRadeonX4000_AMDUVDHWEngine13hasCapabilityEP16_sUVD_CAPABILITY 0000000000062856 g 0f SECT 01 0000 [.text] __ZN29AMDRadeonX4000_AMDUVDHWEngine13setPowerStateEj 0000000000061528 g 0f SECT 01 0000 [.text] __ZN29AMDRadeonX4000_AMDUVDHWEngine13startRBEngineEv 00000000000626c6 g 0f SECT 01 0000 [.text] __ZN29AMDRadeonX4000_AMDUVDHWEngine14queryClockInfoEPjS0_S0_ 000000000006238c g 0f SECT 01 0000 [.text] __ZN29AMDRadeonX4000_AMDUVDHWEngine14submitUVDFWMsgEP12_SML_UVD_MSGb 0000000000061778 g 0f SECT 01 0000 [.text] __ZN29AMDRadeonX4000_AMDUVDHWEngine15releaseFWMemoryEv 0000000000061684 g 0f SECT 01 0000 [.text] __ZN29AMDRadeonX4000_AMDUVDHWEngine16allocateFWMemoryEv 0000000000061fb4 g 0f SECT 01 0000 [.text] __ZN29AMDRadeonX4000_AMDUVDHWEngine16copyCacheWindowsEv 000000000006259e g 0f SECT 01 0000 [.text] __ZN29AMDRadeonX4000_AMDUVDHWEngine16initHardwareCailEv 0000000000061b22 g 0f SECT 01 0000 [.text] __ZN29AMDRadeonX4000_AMDUVDHWEngine16updateCapabilityEP16_sUVD_CAPABILITY 000000000006275e g 0f SECT 01 0000 [.text] __ZN29AMDRadeonX4000_AMDUVDHWEngine16updatePowerStateEv 0000000000061a94 g 0f SECT 01 0000 [.text] __ZN29AMDRadeonX4000_AMDUVDHWEngine17releaseCapabilityEj 00000000000619f4 g 0f SECT 01 0000 [.text] __ZN29AMDRadeonX4000_AMDUVDHWEngine17requestCapabilityEP16_sUVD_CAPABILITYPj 00000000000617d8 g 0f SECT 01 0000 [.text] __ZN29AMDRadeonX4000_AMDUVDHWEngine17setupFirmwareAreaEv 00000000000615d6 g 0f SECT 01 0000 [.text] __ZN29AMDRadeonX4000_AMDUVDHWEngine18setFWMemoryAddressEv 0000000000062634 g 0f SECT 01 0000 [.text] __ZN29AMDRadeonX4000_AMDUVDHWEngine19releaseHardwareCailEv 00000000000620f2 g 0f SECT 01 0000 [.text] __ZN29AMDRadeonX4000_AMDUVDHWEngine19restoreCacheWindowsEb 000000000006296a g 0f SECT 01 0000 [.text] __ZN29AMDRadeonX4000_AMDUVDHWEngine19setUVDSPUPowerStateEj 00000000000615b6 g 0f SECT 01 0000 [.text] __ZN29AMDRadeonX4000_AMDUVDHWEngine20setVirtualSpaceReadyEb 0000000000062350 g 0f SECT 01 0000 [.text] __ZN29AMDRadeonX4000_AMDUVDHWEngine20submitDestroyCommandEjP12_SML_UVD_MSG 00000000000628f2 g 0f SECT 01 0000 [.text] __ZN29AMDRadeonX4000_AMDUVDHWEngine24setHighPerformanceDecodeEj 0000000000061652 g 0f SECT 01 0000 [.text] __ZN29AMDRadeonX4000_AMDUVDHWEngine27setMemoryAllocationsEnabledEb 0000000000061856 g 0f SECT 01 0000 [.text] __ZN29AMDRadeonX4000_AMDUVDHWEngine27setTimestampWritebackMemoryEb 0000000000062508 g 0f SECT 01 0000 [.text] __ZN29AMDRadeonX4000_AMDUVDHWEngine27setupCacheWindowsAndFwvCailEv 0000000000061250 g 0f SECT 01 0000 [.text] __ZN29AMDRadeonX4000_AMDUVDHWEngine4freeEv 000000000006114a g 0f SECT 01 0000 [.text] __ZN29AMDRadeonX4000_AMDUVDHWEngine4initEP30AMDRadeonX4000_IAMDHWInterface20_eAMD_HW_ENGINE_TYPE 000000000006142a g 0f SECT 01 0000 [.text] __ZN29AMDRadeonX4000_AMDUVDHWEngine4stopEv 00000000000612b8 g 0f SECT 01 0000 [.text] __ZN29AMDRadeonX4000_AMDUVDHWEngine5startEv 000000000006128c g 0f SECT 01 0000 [.text] __ZN29AMDRadeonX4000_AMDUVDHWEngine7powerUpEv 0000000000061294 g 0f SECT 01 0000 [.text] __ZN29AMDRadeonX4000_AMDUVDHWEngine8powerOffEv 0000000000061070 g 0f SECT 01 0000 [.text] __ZN29AMDRadeonX4000_AMDUVDHWEngine9MetaClassC1Ev 0000000000061110 g 0f SECT 01 0000 [.text] __ZN29AMDRadeonX4000_AMDUVDHWEngine9MetaClassC2Ev 0000000000061b7c g 0f SECT 01 0000 [.text] __ZN29AMDRadeonX4000_AMDUVDHWEngine9addClientEP14AMDHWUVDClient 000000000006141a g 0f SECT 01 0000 [.text] __ZN29AMDRadeonX4000_AMDUVDHWEngine9isEnabledEv 0000000000061c1e g 0f SECT 01 0000 [.text] __ZN29AMDRadeonX4000_AMDUVDHWEngine9loadUVDFWEv 00000000003aa1e0 g 0f SECT 08 0000 [.const_data] __ZN29AMDRadeonX4000_AMDUVDHWEngine9metaClassE 0000000000062242 g 0f SECT 01 0000 [.text] __ZN29AMDRadeonX4000_AMDUVDHWEngine9saveStateEjP12_SML_UVD_MSG 00000000000612fc g 0f SECT 01 0000 [.text] __ZN29AMDRadeonX4000_AMDUVDHWEngine9start_DMAEv 00000000000610ac g 0f SECT 01 0000 [.text] __ZN29AMDRadeonX4000_AMDUVDHWEngineC2EPK11OSMetaClass 00000000000610e0 g 0f SECT 01 0000 [.text] __ZN29AMDRadeonX4000_AMDUVDHWEngineD0Ev 00000000000610d6 g 0f SECT 01 0000 [.text] __ZN29AMDRadeonX4000_AMDUVDHWEngineD1Ev 00000000000610cc g 0f SECT 01 0000 [.text] __ZN29AMDRadeonX4000_AMDUVDHWEngineD2Ev 000000000052df90 g 0f SECT 0a 0000 [__DATA.__common] __ZN29AMDRadeonX4000_AMDVCEHWEngine10gMetaClassE 0000000000060b58 g 0f SECT 01 0000 [.text] __ZN29AMDRadeonX4000_AMDVCEHWEngine10powerOnOffEb 00000000003a9a38 g 0f SECT 08 0000 [.const_data] __ZN29AMDRadeonX4000_AMDVCEHWEngine10superClassE 0000000000060a50 g 0f SECT 01 0000 [.text] __ZN29AMDRadeonX4000_AMDVCEHWEngine13setEVClkECClkEjj 0000000000060ac0 g 0f SECT 01 0000 [.text] __ZN29AMDRadeonX4000_AMDVCEHWEngine14queryClockInfoEPjS0_S0_ 0000000000060380 g 0f SECT 01 0000 [.text] __ZN29AMDRadeonX4000_AMDVCEHWEngine15releaseFWMemoryEv 00000000000605fc g 0f SECT 01 0000 [.text] __ZN29AMDRadeonX4000_AMDVCEHWEngine15releaseFeedBackEv 00000000000601f2 g 0f SECT 01 0000 [.text] __ZN29AMDRadeonX4000_AMDVCEHWEngine16allocateFWMemoryEv 00000000000604f6 g 0f SECT 01 0000 [.text] __ZN29AMDRadeonX4000_AMDVCEHWEngine16allocateFeedBackEv 000000000006087a g 0f SECT 01 0000 [.text] __ZN29AMDRadeonX4000_AMDVCEHWEngine16initHardwareCailEv 00000000000606ec g 0f SECT 01 0000 [.text] __ZN29AMDRadeonX4000_AMDVCEHWEngine17releaseCapabilityEj 000000000006066a g 0f SECT 01 0000 [.text] __ZN29AMDRadeonX4000_AMDVCEHWEngine17requestCapabilityEP16_sVCE_CAPABILITYPj 000000000006094e g 0f SECT 01 0000 [.text] __ZN29AMDRadeonX4000_AMDVCEHWEngine19pageVCEReservedAreaEb 000000000006092c g 0f SECT 01 0000 [.text] __ZN29AMDRadeonX4000_AMDVCEHWEngine19releaseHardwareCailEv 0000000000060ba0 g 0f SECT 01 0000 [.text] __ZN29AMDRadeonX4000_AMDVCEHWEngine19setSaveRestoreStateEb 0000000000060a22 g 0f SECT 01 0000 [.text] __ZN29AMDRadeonX4000_AMDVCEHWEngine20setupVCEReservedAreaEv 0000000000060bc0 g 0f SECT 01 0000 [.text] __ZN29AMDRadeonX4000_AMDVCEHWEngine21setSuspendResumeStateEb 0000000000060a3e g 0f SECT 01 0000 [.text] __ZN29AMDRadeonX4000_AMDVCEHWEngine22releaseVCEReservedAreaEv 00000000000601d8 g 0f SECT 01 0000 [.text] __ZN29AMDRadeonX4000_AMDVCEHWEngine27setMemoryAllocationsEnabledEb 000000000006001a g 0f SECT 01 0000 [.text] __ZN29AMDRadeonX4000_AMDVCEHWEngine4freeEv 000000000005feea g 0f SECT 01 0000 [.text] __ZN29AMDRadeonX4000_AMDVCEHWEngine4initEP30AMDRadeonX4000_IAMDHWInterface20_eAMD_HW_ENGINE_TYPE 000000000006016e g 0f SECT 01 0000 [.text] __ZN29AMDRadeonX4000_AMDVCEHWEngine4stopEv 00000000000600e0 g 0f SECT 01 0000 [.text] __ZN29AMDRadeonX4000_AMDVCEHWEngine5startEv 00000000000603c2 g 0f SECT 01 0000 [.text] __ZN29AMDRadeonX4000_AMDVCEHWEngine6loadFWEv 00000000000600d0 g 0f SECT 01 0000 [.text] __ZN29AMDRadeonX4000_AMDVCEHWEngine7powerUpEv 00000000000600d8 g 0f SECT 01 0000 [.text] __ZN29AMDRadeonX4000_AMDVCEHWEngine8powerOffEv 000000000005fe10 g 0f SECT 01 0000 [.text] __ZN29AMDRadeonX4000_AMDVCEHWEngine9MetaClassC1Ev 000000000005feb0 g 0f SECT 01 0000 [.text] __ZN29AMDRadeonX4000_AMDVCEHWEngine9MetaClassC2Ev 00000000003a9a30 g 0f SECT 08 0000 [.const_data] __ZN29AMDRadeonX4000_AMDVCEHWEngine9metaClassE 0000000000060738 g 0f SECT 01 0000 [.text] __ZN29AMDRadeonX4000_AMDVCEHWEngine9submitCmdE17_SML_VCE_CMD_TYPEPv18_eAMD_HW_RING_TYPE 000000000005fe4c g 0f SECT 01 0000 [.text] __ZN29AMDRadeonX4000_AMDVCEHWEngineC2EPK11OSMetaClass 000000000005fe80 g 0f SECT 01 0000 [.text] __ZN29AMDRadeonX4000_AMDVCEHWEngineD0Ev 000000000005fe76 g 0f SECT 01 0000 [.text] __ZN29AMDRadeonX4000_AMDVCEHWEngineD1Ev 000000000005fe6c g 0f SECT 01 0000 [.text] __ZN29AMDRadeonX4000_AMDVCEHWEngineD2Ev 000000000052d568 g 0f SECT 0a 0000 [__DATA.__common] __ZN30AMDPitcairnGraphicsAccelerator10gMetaClassE 0000000000394298 g 0f SECT 08 0000 [.const_data] __ZN30AMDPitcairnGraphicsAccelerator10superClassE 0000000000029458 g 0f SECT 01 0000 [.text] __ZN30AMDPitcairnGraphicsAccelerator13setDeviceTypeEP11IOPCIDevice 0000000000029432 g 0f SECT 01 0000 [.text] __ZN30AMDPitcairnGraphicsAccelerator14newHWInterfaceEv 00000000000292a0 g 0f SECT 01 0000 [.text] __ZN30AMDPitcairnGraphicsAccelerator9MetaClassC1Ev 0000000000029360 g 0f SECT 01 0000 [.text] __ZN30AMDPitcairnGraphicsAccelerator9MetaClassC2Ev 0000000000394290 g 0f SECT 08 0000 [.const_data] __ZN30AMDPitcairnGraphicsAccelerator9metaClassE 00000000000292fc g 0f SECT 01 0000 [.text] __ZN30AMDPitcairnGraphicsAcceleratorC1EPK11OSMetaClass 00000000000293d2 g 0f SECT 01 0000 [.text] __ZN30AMDPitcairnGraphicsAcceleratorC1Ev 00000000000292dc g 0f SECT 01 0000 [.text] __ZN30AMDPitcairnGraphicsAcceleratorC2EPK11OSMetaClass 0000000000029402 g 0f SECT 01 0000 [.text] __ZN30AMDPitcairnGraphicsAcceleratorC2Ev 0000000000029330 g 0f SECT 01 0000 [.text] __ZN30AMDPitcairnGraphicsAcceleratorD0Ev 0000000000029326 g 0f SECT 01 0000 [.text] __ZN30AMDPitcairnGraphicsAcceleratorD1Ev 000000000002931c g 0f SECT 01 0000 [.text] __ZN30AMDPitcairnGraphicsAcceleratorD2Ev 000000000052ce90 g 0f SECT 0a 0000 [__DATA.__common] __ZN30AMDRadeonX4000_AMDAccelChannel10gMetaClassE 00000000003899f8 g 0f SECT 08 0000 [.const_data] __ZN30AMDRadeonX4000_AMDAccelChannel10superClassE 0000000000004b40 g 0f SECT 01 0000 [.text] __ZN30AMDRadeonX4000_AMDAccelChannel11submitFlushEv 00000000000052e0 g 0f SECT 01 0000 [.text] __ZN30AMDRadeonX4000_AMDAccelChannel12addToBarrierEP12IOAccelEvent 00000000000048d2 g 0f SECT 01 0000 [.text] __ZN30AMDRadeonX4000_AMDAccelChannel12submitBufferEP24IOAccelCommandDescriptor 0000000000004be8 g 0f SECT 01 0000 [.text] __ZN30AMDRadeonX4000_AMDAccelChannel13replayBuffersEv 00000000000052ae g 0f SECT 01 0000 [.text] __ZN30AMDRadeonX4000_AMDAccelChannel15initBarrierDataEv 000000000000534e g 0f SECT 01 0000 [.text] __ZN30AMDRadeonX4000_AMDAccelChannel16SubmitClearStateEv 0000000000004b9e g 0f SECT 01 0000 [.text] __ZN30AMDRadeonX4000_AMDAccelChannel18submitVMInvalidateEjy 000000000000532a g 0f SECT 01 0000 [.text] __ZN30AMDRadeonX4000_AMDAccelChannel18vblEnableInterruptEv 000000000000533c g 0f SECT 01 0000 [.text] __ZN30AMDRadeonX4000_AMDAccelChannel19vblDisableInterruptEv 0000000000004eea g 0f SECT 01 0000 [.text] __ZN30AMDRadeonX4000_AMDAccelChannel20writeDiagnosisReportEv 0000000000004dae g 0f SECT 01 0000 [.text] __ZN30AMDRadeonX4000_AMDAccelChannel22resetHardwareAndReplayEv 0000000000004e52 g 0f SECT 01 0000 [.text] __ZN30AMDRadeonX4000_AMDAccelChannel26getHardwareDiagnosisReportEPj 0000000000004840 g 0f SECT 01 0000 [.text] __ZN30AMDRadeonX4000_AMDAccelChannel4freeEv 0000000000004732 g 0f SECT 01 0000 [.text] __ZN30AMDRadeonX4000_AMDAccelChannel4initEP22IOGraphicsAccelerator2P28AMDRadeonX4000_IAMDHWChannel 00000000000045a0 g 0f SECT 01 0000 [.text] __ZN30AMDRadeonX4000_AMDAccelChannel9MetaClassC1Ev 0000000000004660 g 0f SECT 01 0000 [.text] __ZN30AMDRadeonX4000_AMDAccelChannel9MetaClassC2Ev 00000000003899f0 g 0f SECT 08 0000 [.const_data] __ZN30AMDRadeonX4000_AMDAccelChannel9metaClassE 00000000000045fc g 0f SECT 01 0000 [.text] __ZN30AMDRadeonX4000_AMDAccelChannelC1EPK11OSMetaClass 00000000000046d2 g 0f SECT 01 0000 [.text] __ZN30AMDRadeonX4000_AMDAccelChannelC1Ev 00000000000045dc g 0f SECT 01 0000 [.text] __ZN30AMDRadeonX4000_AMDAccelChannelC2EPK11OSMetaClass 0000000000004702 g 0f SECT 01 0000 [.text] __ZN30AMDRadeonX4000_AMDAccelChannelC2Ev 0000000000004630 g 0f SECT 01 0000 [.text] __ZN30AMDRadeonX4000_AMDAccelChannelD0Ev 0000000000004626 g 0f SECT 01 0000 [.text] __ZN30AMDRadeonX4000_AMDAccelChannelD1Ev 000000000000461c g 0f SECT 01 0000 [.text] __ZN30AMDRadeonX4000_AMDAccelChannelD2Ev 000000000052cfd0 g 0f SECT 0a 0000 [__DATA.__common] __ZN30AMDRadeonX4000_AMDAccelSurface10gMetaClassE 000000000038c9b8 g 0f SECT 08 0000 [.const_data] __ZN30AMDRadeonX4000_AMDAccelSurface10superClassE 0000000000014706 g 0f SECT 01 0000 [.text] __ZN30AMDRadeonX4000_AMDAccelSurface11canTmpAllocEj 0000000000014692 g 0f SECT 01 0000 [.text] __ZN30AMDRadeonX4000_AMDAccelSurface11surfaceStopEv 0000000000013442 g 0f SECT 01 0000 [.text] __ZN30AMDRadeonX4000_AMDAccelSurface12copyToBufferEiiiijjP12IOAccelEventP16IOAccelResource2P16IOAccelSysMemoryjyj 0000000000014748 g 0f SECT 01 0000 [.text] __ZN30AMDRadeonX4000_AMDAccelSurface12shapeSurfaceEjtt 00000000000142fc g 0f SECT 01 0000 [.text] __ZN30AMDRadeonX4000_AMDAccelSurface12submitUpdateEjP13IOAccelBoundsj 0000000000014604 g 0f SECT 01 0000 [.text] __ZN30AMDRadeonX4000_AMDAccelSurface12surfaceStartEv 0000000000014308 g 0f SECT 01 0000 [.text] __ZN30AMDRadeonX4000_AMDAccelSurface13didSubmitSwapEjj 00000000000129da g 0f SECT 01 0000 [.text] __ZN30AMDRadeonX4000_AMDAccelSurface14copyFromBufferEiiiijjP12IOAccelEventP16IOAccelResource2P16IOAccelSysMemoryjyj 00000000000134de g 0f SECT 01 0000 [.text] __ZN30AMDRadeonX4000_AMDAccelSurface14submitSwapCopyEP12IOAccelEventP16IOAccelResource2S3_ 0000000000012ac8 g 0f SECT 01 0000 [.text] __ZN30AMDRadeonX4000_AMDAccelSurface15copy_buffer_gpuEiiiijjP12IOAccelEventP16IOAccelResource2P16IOAccelSysMemoryyyjj 000000000001398c g 0f SECT 01 0000 [.text] __ZN30AMDRadeonX4000_AMDAccelSurface15submitSwapFlushEP12IOAccelEventP16IOAccelResource2S3_PK19IOAccelSwapFlushRecjjjPK13IOAccelBounds 0000000000015dae g 0f SECT 01 0000 [.text] __ZN30AMDRadeonX4000_AMDAccelSurface17isBackBufferReadyEj 0000000000013e5c g 0f SECT 01 0000 [.text] __ZN30AMDRadeonX4000_AMDAccelSurface17submitCopyForwardEP12IOAccelEventjP16IOAccelResource2S3_PK13IOAccelBoundsj 00000000000150ae g 0f SECT 01 0000 [.text] __ZN30AMDRadeonX4000_AMDAccelSurface19getMultisampleCountEv 0000000000015142 g 0f SECT 01 0000 [.text] __ZN30AMDRadeonX4000_AMDAccelSurface19shapeSurfaceBuffersEhPhPvhbjtt 0000000000015d7a g 0f SECT 01 0000 [.text] __ZN30AMDRadeonX4000_AMDAccelSurface37getDirtyBufferBitsFromPrivateModeBitsEy 0000000000012900 g 0f SECT 01 0000 [.text] __ZN30AMDRadeonX4000_AMDAccelSurface9MetaClassC1Ev 00000000000129a0 g 0f SECT 01 0000 [.text] __ZN30AMDRadeonX4000_AMDAccelSurface9MetaClassC2Ev 000000000038c9b0 g 0f SECT 08 0000 [.const_data] __ZN30AMDRadeonX4000_AMDAccelSurface9metaClassE 000000000001293c g 0f SECT 01 0000 [.text] __ZN30AMDRadeonX4000_AMDAccelSurfaceC2EPK11OSMetaClass 0000000000012970 g 0f SECT 01 0000 [.text] __ZN30AMDRadeonX4000_AMDAccelSurfaceD0Ev 0000000000012966 g 0f SECT 01 0000 [.text] __ZN30AMDRadeonX4000_AMDAccelSurfaceD1Ev 000000000001295c g 0f SECT 01 0000 [.text] __ZN30AMDRadeonX4000_AMDAccelSurfaceD2Ev 000000000052d950 g 0f SECT 0a 0000 [__DATA.__common] __ZN30AMDRadeonX4000_AMDDMAHWChannel10gMetaClassE 00000000003a1cc8 g 0f SECT 08 0000 [.const_data] __ZN30AMDRadeonX4000_AMDDMAHWChannel10superClassE 000000000004ef16 g 0f SECT 01 0000 [.text] __ZN30AMDRadeonX4000_AMDDMAHWChannel19submitCommandBufferEP30AMD_SUBMIT_COMMAND_BUFFER_INFOPj 000000000004ef28 g 0f SECT 01 0000 [.text] __ZN30AMDRadeonX4000_AMDDMAHWChannel22timeStampInterruptTypeEv 000000000004eeee g 0f SECT 01 0000 [.text] __ZN30AMDRadeonX4000_AMDDMAHWChannel4freeEv 000000000004eeba g 0f SECT 01 0000 [.text] __ZN30AMDRadeonX4000_AMDDMAHWChannel4initEiP30AMDRadeonX4000_IAMDHWInterfaceP27AMDRadeonX4000_IAMDHWEngineP25AMDRadeonX4000_IAMDHWRingPKc 000000000004ede0 g 0f SECT 01 0000 [.text] __ZN30AMDRadeonX4000_AMDDMAHWChannel9MetaClassC1Ev 000000000004ee80 g 0f SECT 01 0000 [.text] __ZN30AMDRadeonX4000_AMDDMAHWChannel9MetaClassC2Ev 00000000003a1cc0 g 0f SECT 08 0000 [.const_data] __ZN30AMDRadeonX4000_AMDDMAHWChannel9metaClassE 000000000004ee1c g 0f SECT 01 0000 [.text] __ZN30AMDRadeonX4000_AMDDMAHWChannelC2EPK11OSMetaClass 000000000004ee50 g 0f SECT 01 0000 [.text] __ZN30AMDRadeonX4000_AMDDMAHWChannelD0Ev 000000000004ee46 g 0f SECT 01 0000 [.text] __ZN30AMDRadeonX4000_AMDDMAHWChannelD1Ev 000000000004ee3c g 0f SECT 01 0000 [.text] __ZN30AMDRadeonX4000_AMDDMAHWChannelD2Ev 000000000052f098 g 0f SECT 0a 0000 [__DATA.__common] __ZN30AMDRadeonX4000_AMDFPEncryptMsg10gMetaClassE 00000000003c3220 g 0f SECT 08 0000 [.const_data] __ZN30AMDRadeonX4000_AMDFPEncryptMsg10superClassE 0000000000127984 g 0f SECT 01 0000 [.text] __ZN30AMDRadeonX4000_AMDFPEncryptMsg12setOutBufferEiyPh 0000000000127972 g 0f SECT 01 0000 [.text] __ZN30AMDRadeonX4000_AMDFPEncryptMsg4freeEv 000000000012782e g 0f SECT 01 0000 [.text] __ZN30AMDRadeonX4000_AMDFPEncryptMsg4initEPv 000000000012769c g 0f SECT 01 0000 [.text] __ZN30AMDRadeonX4000_AMDFPEncryptMsg9MetaClassC1Ev 000000000012775c g 0f SECT 01 0000 [.text] __ZN30AMDRadeonX4000_AMDFPEncryptMsg9MetaClassC2Ev 00000000001279c4 g 0f SECT 01 0000 [.text] __ZN30AMDRadeonX4000_AMDFPEncryptMsg9getOutputEv 00000000003c3218 g 0f SECT 08 0000 [.const_data] __ZN30AMDRadeonX4000_AMDFPEncryptMsg9metaClassE 00000000001276f8 g 0f SECT 01 0000 [.text] __ZN30AMDRadeonX4000_AMDFPEncryptMsgC1EPK11OSMetaClass 00000000001277ce g 0f SECT 01 0000 [.text] __ZN30AMDRadeonX4000_AMDFPEncryptMsgC1Ev 00000000001276d8 g 0f SECT 01 0000 [.text] __ZN30AMDRadeonX4000_AMDFPEncryptMsgC2EPK11OSMetaClass 00000000001277fe g 0f SECT 01 0000 [.text] __ZN30AMDRadeonX4000_AMDFPEncryptMsgC2Ev 000000000012772c g 0f SECT 01 0000 [.text] __ZN30AMDRadeonX4000_AMDFPEncryptMsgD0Ev 0000000000127722 g 0f SECT 01 0000 [.text] __ZN30AMDRadeonX4000_AMDFPEncryptMsgD1Ev 0000000000127718 g 0f SECT 01 0000 [.text] __ZN30AMDRadeonX4000_AMDFPEncryptMsgD2Ev 000000000052eff8 g 0f SECT 0a 0000 [__DATA.__common] __ZN30AMDRadeonX4000_AMDFPGetCertMsg10gMetaClassE 00000000003c27e0 g 0f SECT 08 0000 [.const_data] __ZN30AMDRadeonX4000_AMDFPGetCertMsg10superClassE 0000000000126dce g 0f SECT 01 0000 [.text] __ZN30AMDRadeonX4000_AMDFPGetCertMsg12setOutBufferEiyPh 0000000000126dbc g 0f SECT 01 0000 [.text] __ZN30AMDRadeonX4000_AMDFPGetCertMsg4freeEv 0000000000126ce8 g 0f SECT 01 0000 [.text] __ZN30AMDRadeonX4000_AMDFPGetCertMsg4initEPv 0000000000126b56 g 0f SECT 01 0000 [.text] __ZN30AMDRadeonX4000_AMDFPGetCertMsg9MetaClassC1Ev 0000000000126c16 g 0f SECT 01 0000 [.text] __ZN30AMDRadeonX4000_AMDFPGetCertMsg9MetaClassC2Ev 0000000000126e06 g 0f SECT 01 0000 [.text] __ZN30AMDRadeonX4000_AMDFPGetCertMsg9getOutputEv 00000000003c27d8 g 0f SECT 08 0000 [.const_data] __ZN30AMDRadeonX4000_AMDFPGetCertMsg9metaClassE 0000000000126bb2 g 0f SECT 01 0000 [.text] __ZN30AMDRadeonX4000_AMDFPGetCertMsgC1EPK11OSMetaClass 0000000000126c88 g 0f SECT 01 0000 [.text] __ZN30AMDRadeonX4000_AMDFPGetCertMsgC1Ev 0000000000126b92 g 0f SECT 01 0000 [.text] __ZN30AMDRadeonX4000_AMDFPGetCertMsgC2EPK11OSMetaClass 0000000000126cb8 g 0f SECT 01 0000 [.text] __ZN30AMDRadeonX4000_AMDFPGetCertMsgC2Ev 0000000000126be6 g 0f SECT 01 0000 [.text] __ZN30AMDRadeonX4000_AMDFPGetCertMsgD0Ev 0000000000126bdc g 0f SECT 01 0000 [.text] __ZN30AMDRadeonX4000_AMDFPGetCertMsgD1Ev 0000000000126bd2 g 0f SECT 01 0000 [.text] __ZN30AMDRadeonX4000_AMDFPGetCertMsgD2Ev 000000000052f048 g 0f SECT 0a 0000 [__DATA.__common] __ZN30AMDRadeonX4000_AMDFPTestKeyMsg10gMetaClassE 00000000003c2d00 g 0f SECT 08 0000 [.const_data] __ZN30AMDRadeonX4000_AMDFPTestKeyMsg10superClassE 00000000001273fc g 0f SECT 01 0000 [.text] __ZN30AMDRadeonX4000_AMDFPTestKeyMsg12setOutBufferEiyPh 00000000001273ea g 0f SECT 01 0000 [.text] __ZN30AMDRadeonX4000_AMDFPTestKeyMsg4freeEv 0000000000127310 g 0f SECT 01 0000 [.text] __ZN30AMDRadeonX4000_AMDFPTestKeyMsg4initEPv 000000000012717e g 0f SECT 01 0000 [.text] __ZN30AMDRadeonX4000_AMDFPTestKeyMsg9MetaClassC1Ev 000000000012723e g 0f SECT 01 0000 [.text] __ZN30AMDRadeonX4000_AMDFPTestKeyMsg9MetaClassC2Ev 000000000012743c g 0f SECT 01 0000 [.text] __ZN30AMDRadeonX4000_AMDFPTestKeyMsg9getOutputEv 00000000003c2cf8 g 0f SECT 08 0000 [.const_data] __ZN30AMDRadeonX4000_AMDFPTestKeyMsg9metaClassE 00000000001271da g 0f SECT 01 0000 [.text] __ZN30AMDRadeonX4000_AMDFPTestKeyMsgC1EPK11OSMetaClass 00000000001272b0 g 0f SECT 01 0000 [.text] __ZN30AMDRadeonX4000_AMDFPTestKeyMsgC1Ev 00000000001271ba g 0f SECT 01 0000 [.text] __ZN30AMDRadeonX4000_AMDFPTestKeyMsgC2EPK11OSMetaClass 00000000001272e0 g 0f SECT 01 0000 [.text] __ZN30AMDRadeonX4000_AMDFPTestKeyMsgC2Ev 000000000012720e g 0f SECT 01 0000 [.text] __ZN30AMDRadeonX4000_AMDFPTestKeyMsgD0Ev 0000000000127204 g 0f SECT 01 0000 [.text] __ZN30AMDRadeonX4000_AMDFPTestKeyMsgD1Ev 00000000001271fa g 0f SECT 01 0000 [.text] __ZN30AMDRadeonX4000_AMDFPTestKeyMsgD2Ev 000000000052da18 g 0f SECT 0a 0000 [__DATA.__common] __ZN30AMDRadeonX4000_AMDNullHWEngine10gMetaClassE 00000000003a2d68 g 0f SECT 08 0000 [.const_data] __ZN30AMDRadeonX4000_AMDNullHWEngine10superClassE 0000000000050fc0 g 0f SECT 01 0000 [.text] __ZN30AMDRadeonX4000_AMDNullHWEngine9MetaClassC1Ev 0000000000051080 g 0f SECT 01 0000 [.text] __ZN30AMDRadeonX4000_AMDNullHWEngine9MetaClassC2Ev 00000000003a2d60 g 0f SECT 08 0000 [.const_data] __ZN30AMDRadeonX4000_AMDNullHWEngine9metaClassE 000000000005101c g 0f SECT 01 0000 [.text] __ZN30AMDRadeonX4000_AMDNullHWEngineC1EPK11OSMetaClass 00000000000510f2 g 0f SECT 01 0000 [.text] __ZN30AMDRadeonX4000_AMDNullHWEngineC1Ev 0000000000050ffc g 0f SECT 01 0000 [.text] __ZN30AMDRadeonX4000_AMDNullHWEngineC2EPK11OSMetaClass 0000000000051122 g 0f SECT 01 0000 [.text] __ZN30AMDRadeonX4000_AMDNullHWEngineC2Ev 0000000000051050 g 0f SECT 01 0000 [.text] __ZN30AMDRadeonX4000_AMDNullHWEngineD0Ev 0000000000051046 g 0f SECT 01 0000 [.text] __ZN30AMDRadeonX4000_AMDNullHWEngineD1Ev 000000000005103c g 0f SECT 01 0000 [.text] __ZN30AMDRadeonX4000_AMDNullHWEngineD2Ev 000000000052df18 g 0f SECT 0a 0000 [__DATA.__common] __ZN30AMDRadeonX4000_AMDPM4HWChannel10gMetaClassE 00000000003a8ef8 g 0f SECT 08 0000 [.const_data] __ZN30AMDRadeonX4000_AMDPM4HWChannel10superClassE 000000000005ee50 g 0f SECT 01 0000 [.text] __ZN30AMDRadeonX4000_AMDPM4HWChannel19submitCommandBufferEP30AMD_SUBMIT_COMMAND_BUFFER_INFOPj 000000000005eeea g 0f SECT 01 0000 [.text] __ZN30AMDRadeonX4000_AMDPM4HWChannel21getOneDwordNOPCommandEv 000000000005eede g 0f SECT 01 0000 [.text] __ZN30AMDRadeonX4000_AMDPM4HWChannel22timeStampInterruptTypeEv 000000000005ee7c g 0f SECT 01 0000 [.text] __ZN30AMDRadeonX4000_AMDPM4HWChannel42executeFlushAndInvalidateDestinationCachesEv 000000000005ed72 g 0f SECT 01 0000 [.text] __ZN30AMDRadeonX4000_AMDPM4HWChannel4freeEv 000000000005ed1a g 0f SECT 01 0000 [.text] __ZN30AMDRadeonX4000_AMDPM4HWChannel4initEiP30AMDRadeonX4000_IAMDHWInterfaceP27AMDRadeonX4000_IAMDHWEngineP25AMDRadeonX4000_IAMDHWRingPKc 000000000005ec40 g 0f SECT 01 0000 [.text] __ZN30AMDRadeonX4000_AMDPM4HWChannel9MetaClassC1Ev 000000000005ece0 g 0f SECT 01 0000 [.text] __ZN30AMDRadeonX4000_AMDPM4HWChannel9MetaClassC2Ev 00000000003a8ef0 g 0f SECT 08 0000 [.const_data] __ZN30AMDRadeonX4000_AMDPM4HWChannel9metaClassE 000000000005ec7c g 0f SECT 01 0000 [.text] __ZN30AMDRadeonX4000_AMDPM4HWChannelC2EPK11OSMetaClass 000000000005ecb0 g 0f SECT 01 0000 [.text] __ZN30AMDRadeonX4000_AMDPM4HWChannelD0Ev 000000000005eca6 g 0f SECT 01 0000 [.text] __ZN30AMDRadeonX4000_AMDPM4HWChannelD1Ev 000000000005ec9c g 0f SECT 01 0000 [.text] __ZN30AMDRadeonX4000_AMDPM4HWChannelD2Ev 000000000052ee68 g 0f SECT 0a 0000 [__DATA.__common] __ZN30AMDRadeonX4000_AMDSMLInterface10gMetaClassE 00000000001249f8 g 0f SECT 01 0000 [.text] __ZN30AMDRadeonX4000_AMDSMLInterface10getSPUKappEPjS0_ 00000000003c0e08 g 0f SECT 08 0000 [.const_data] __ZN30AMDRadeonX4000_AMDSMLInterface10superClassE 0000000000124934 g 0f SECT 01 0000 [.text] __ZN30AMDRadeonX4000_AMDSMLInterface11writeAESCmdEPjS0_yyjP11_DRMDMA_AESj 0000000000124b80 g 0f SECT 01 0000 [.text] __ZN30AMDRadeonX4000_AMDSMLInterface11writeVCECmdEPjS0_17_SML_VCE_CMD_TYPEPv 0000000000124a64 g 0f SECT 01 0000 [.text] __ZN30AMDRadeonX4000_AMDSMLInterface12getSPUAppMsgE17_AMD_SPU_MSG_TYPE 0000000000124986 g 0f SECT 01 0000 [.text] __ZN30AMDRadeonX4000_AMDSMLInterface12getSPUKernelEPjS0_S0_S0_ 00000000001248d4 g 0f SECT 01 0000 [.text] __ZN30AMDRadeonX4000_AMDSMLInterface12saveUVDStateEjP12_SML_UVD_MSG 0000000000124a1c g 0f SECT 01 0000 [.text] __ZN30AMDRadeonX4000_AMDSMLInterface13getSPUAppSizeE17_AMD_SPU_APP_TYPEPjS1_ 0000000000124ba4 g 0f SECT 01 0000 [.text] __ZN30AMDRadeonX4000_AMDSMLInterface13getVCECmdSizeEPj17_SML_VCE_CMD_TYPE 00000000001249d4 g 0f SECT 01 0000 [.text] __ZN30AMDRadeonX4000_AMDSMLInterface14getSPUKappSizeEPjS0_ 0000000000124870 g 0f SECT 01 0000 [.text] __ZN30AMDRadeonX4000_AMDSMLInterface14getUVDFWMemReqEPjS0_S0_ 0000000000124b08 g 0f SECT 01 0000 [.text] __ZN30AMDRadeonX4000_AMDSMLInterface14getVCEFWMemReqEPjS0_ 0000000000124aa6 g 0f SECT 01 0000 [.text] __ZN30AMDRadeonX4000_AMDSMLInterface14writeSPUAppCmdEP12_SML_SPU_CMDb 00000000001248f4 g 0f SECT 01 0000 [.text] __ZN30AMDRadeonX4000_AMDSMLInterface15restoreUVDStateEjP12_SML_UVD_MSG 0000000000124a86 g 0f SECT 01 0000 [.text] __ZN30AMDRadeonX4000_AMDSMLInterface15writeSPUInitCmdEP12_SML_SPU_CMD 0000000000124894 g 0f SECT 01 0000 [.text] __ZN30AMDRadeonX4000_AMDSMLInterface17getUVDFWCacheInfoEP14_SML_UVDFWInfo 0000000000124b40 g 0f SECT 01 0000 [.text] __ZN30AMDRadeonX4000_AMDSMLInterface17getVCEFWCacheInfoEP14_SML_VCEFWINFO 0000000000124b24 g 0f SECT 01 0000 [.text] __ZN30AMDRadeonX4000_AMDSMLInterface17getVCEFWMemConfigEPjS0_ 0000000000124ac8 g 0f SECT 01 0000 [.text] __ZN30AMDRadeonX4000_AMDSMLInterface17writeSPUAppMsgCmdEP12_SML_SPU_CMD 00000000001249b4 g 0f SECT 01 0000 [.text] __ZN30AMDRadeonX4000_AMDSMLInterface18getSPUFeedBackSizeEPj 000000000012496a g 0f SECT 01 0000 [.text] __ZN30AMDRadeonX4000_AMDSMLInterface18getSPUKernelMemReqEPjS0_S0_ 0000000000124bc0 g 0f SECT 01 0000 [.text] __ZN30AMDRadeonX4000_AMDSMLInterface18getVCEFeedbackSizeEPj 0000000000124914 g 0f SECT 01 0000 [.text] __ZN30AMDRadeonX4000_AMDSMLInterface18writeUVDDestroyMsgEjP12_SML_UVD_MSG 0000000000124ae8 g 0f SECT 01 0000 [.text] __ZN30AMDRadeonX4000_AMDSMLInterface26writeSAMUSetPremContentCmdEP15_SAMU_GPCOM_CMD 00000000001247f4 g 0f SECT 01 0000 [.text] __ZN30AMDRadeonX4000_AMDSMLInterface4freeEv 0000000000124722 g 0f SECT 01 0000 [.text] __ZN30AMDRadeonX4000_AMDSMLInterface4initEj 0000000000124be6 g 0f SECT 01 0000 [.text] __ZN30AMDRadeonX4000_AMDSMLInterface6getDRMEv 0000000000124bf0 g 0f SECT 01 0000 [.text] __ZN30AMDRadeonX4000_AMDSMLInterface6getSPUEv 0000000000124bdc g 0f SECT 01 0000 [.text] __ZN30AMDRadeonX4000_AMDSMLInterface6getUVDEv 0000000000124bfa g 0f SECT 01 0000 [.text] __ZN30AMDRadeonX4000_AMDSMLInterface6getVCEEv 00000000001248b4 g 0f SECT 01 0000 [.text] __ZN30AMDRadeonX4000_AMDSMLInterface8getUVDFWEP10_SML_UVDFW 0000000000124b60 g 0f SECT 01 0000 [.text] __ZN30AMDRadeonX4000_AMDSMLInterface8getVCEFWEP10_SML_VCEFW 0000000000124590 g 0f SECT 01 0000 [.text] __ZN30AMDRadeonX4000_AMDSMLInterface9MetaClassC1Ev 0000000000124650 g 0f SECT 01 0000 [.text] __ZN30AMDRadeonX4000_AMDSMLInterface9MetaClassC2Ev 0000000000124c04 g 0f SECT 01 0000 [.text] __ZN30AMDRadeonX4000_AMDSMLInterface9doUVDTestEjjj 0000000000124a40 g 0f SECT 01 0000 [.text] __ZN30AMDRadeonX4000_AMDSMLInterface9getSPUAppE17_AMD_SPU_APP_TYPEPjS1_ 00000000003c0e00 g 0f SECT 08 0000 [.const_data] __ZN30AMDRadeonX4000_AMDSMLInterface9metaClassE 00000000001245ec g 0f SECT 01 0000 [.text] __ZN30AMDRadeonX4000_AMDSMLInterfaceC1EPK11OSMetaClass 00000000001246c2 g 0f SECT 01 0000 [.text] __ZN30AMDRadeonX4000_AMDSMLInterfaceC1Ev 00000000001245cc g 0f SECT 01 0000 [.text] __ZN30AMDRadeonX4000_AMDSMLInterfaceC2EPK11OSMetaClass 00000000001246f2 g 0f SECT 01 0000 [.text] __ZN30AMDRadeonX4000_AMDSMLInterfaceC2Ev 0000000000124620 g 0f SECT 01 0000 [.text] __ZN30AMDRadeonX4000_AMDSMLInterfaceD0Ev 0000000000124616 g 0f SECT 01 0000 [.text] __ZN30AMDRadeonX4000_AMDSMLInterfaceD1Ev 000000000012460c g 0f SECT 01 0000 [.text] __ZN30AMDRadeonX4000_AMDSMLInterfaceD2Ev 000000000052df68 g 0f SECT 0a 0000 [__DATA.__common] __ZN30AMDRadeonX4000_AMDSPUHWChannel10gMetaClassE 00000000003a9698 g 0f SECT 08 0000 [.const_data] __ZN30AMDRadeonX4000_AMDSPUHWChannel10superClassE 000000000005fc8a g 0f SECT 01 0000 [.text] __ZN30AMDRadeonX4000_AMDSPUHWChannel19submitCommandBufferEP30AMD_SUBMIT_COMMAND_BUFFER_INFOPj 000000000005fc7e g 0f SECT 01 0000 [.text] __ZN30AMDRadeonX4000_AMDSPUHWChannel22timeStampInterruptTypeEv 000000000005fc6c g 0f SECT 01 0000 [.text] __ZN30AMDRadeonX4000_AMDSPUHWChannel4freeEv 000000000005fc3a g 0f SECT 01 0000 [.text] __ZN30AMDRadeonX4000_AMDSPUHWChannel4initEiP30AMDRadeonX4000_IAMDHWInterfaceP27AMDRadeonX4000_IAMDHWEngineP25AMDRadeonX4000_IAMDHWRingPKc 000000000005fb60 g 0f SECT 01 0000 [.text] __ZN30AMDRadeonX4000_AMDSPUHWChannel9MetaClassC1Ev 000000000005fc00 g 0f SECT 01 0000 [.text] __ZN30AMDRadeonX4000_AMDSPUHWChannel9MetaClassC2Ev 00000000003a9690 g 0f SECT 08 0000 [.const_data] __ZN30AMDRadeonX4000_AMDSPUHWChannel9metaClassE 000000000005fb9c g 0f SECT 01 0000 [.text] __ZN30AMDRadeonX4000_AMDSPUHWChannelC2EPK11OSMetaClass 000000000005fbd0 g 0f SECT 01 0000 [.text] __ZN30AMDRadeonX4000_AMDSPUHWChannelD0Ev 000000000005fbc6 g 0f SECT 01 0000 [.text] __ZN30AMDRadeonX4000_AMDSPUHWChannelD1Ev 000000000005fbbc g 0f SECT 01 0000 [.text] __ZN30AMDRadeonX4000_AMDSPUHWChannelD2Ev 000000000052d928 g 0f SECT 0a 0000 [__DATA.__common] __ZN30AMDRadeonX4000_AMDUVDHWChannel10gMetaClassE 00000000003a18f0 g 0f SECT 08 0000 [.const_data] __ZN30AMDRadeonX4000_AMDUVDHWChannel10superClassE 000000000004e6d2 g 0f SECT 01 0000 [.text] __ZN30AMDRadeonX4000_AMDUVDHWChannel13initUVDThreadEv 000000000004e7d4 g 0f SECT 01 0000 [.text] __ZN30AMDRadeonX4000_AMDUVDHWChannel13setPowerStateEj 000000000004e7a8 g 0f SECT 01 0000 [.text] __ZN30AMDRadeonX4000_AMDUVDHWChannel15enableUVDThreadEv 000000000004e77c g 0f SECT 01 0000 [.text] __ZN30AMDRadeonX4000_AMDUVDHWChannel16disableUVDThreadEv 000000000004e644 g 0f SECT 01 0000 [.text] __ZN30AMDRadeonX4000_AMDUVDHWChannel16releaseUVDThreadEv 000000000004e882 g 0f SECT 01 0000 [.text] __ZN30AMDRadeonX4000_AMDUVDHWChannel16waitForTimestampEjjPyb 000000000004e5f6 g 0f SECT 01 0000 [.text] __ZN30AMDRadeonX4000_AMDUVDHWChannel18setPollingIntervalEj 000000000004e924 g 0f SECT 01 0000 [.text] __ZN30AMDRadeonX4000_AMDUVDHWChannel19submitCommandBufferEP30AMD_SUBMIT_COMMAND_BUFFER_INFOPj 000000000004e8c4 g 0f SECT 01 0000 [.text] __ZN30AMDRadeonX4000_AMDUVDHWChannel21setTimestampWritebackEPjy 000000000004e876 g 0f SECT 01 0000 [.text] __ZN30AMDRadeonX4000_AMDUVDHWChannel22timeStampInterruptTypeEv 000000000004eb4e g 0f SECT 01 0000 [.text] __ZN30AMDRadeonX4000_AMDUVDHWChannel25timeStampDisableInterruptEv 000000000004e728 g 0f SECT 01 0000 [.text] __ZN30AMDRadeonX4000_AMDUVDHWChannel26handleUVDThreadPMInterruptEP8OSObjectP22IOInterruptEventSourcei 000000000004ead8 g 0f SECT 01 0000 [.text] __ZN30AMDRadeonX4000_AMDUVDHWChannel26registerTimestampInterruptEv 000000000004ec0e g 0f SECT 01 0000 [.text] __ZN30AMDRadeonX4000_AMDUVDHWChannel28uvdTimestampDisableInterruptEv 000000000004e990 g 0f SECT 01 0000 [.text] __ZN30AMDRadeonX4000_AMDUVDHWChannel29uvdtimeStampInterruptCallbackEP8OSObjectPv 000000000004e620 g 0f SECT 01 0000 [.text] __ZN30AMDRadeonX4000_AMDUVDHWChannel4freeEv 000000000004e55e g 0f SECT 01 0000 [.text] __ZN30AMDRadeonX4000_AMDUVDHWChannel4initEiP30AMDRadeonX4000_IAMDHWInterfaceP27AMDRadeonX4000_IAMDHWEngineP25AMDRadeonX4000_IAMDHWRingPKc 000000000004e484 g 0f SECT 01 0000 [.text] __ZN30AMDRadeonX4000_AMDUVDHWChannel9MetaClassC1Ev 000000000004e524 g 0f SECT 01 0000 [.text] __ZN30AMDRadeonX4000_AMDUVDHWChannel9MetaClassC2Ev 00000000003a18e8 g 0f SECT 08 0000 [.const_data] __ZN30AMDRadeonX4000_AMDUVDHWChannel9metaClassE 000000000004e4c0 g 0f SECT 01 0000 [.text] __ZN30AMDRadeonX4000_AMDUVDHWChannelC2EPK11OSMetaClass 000000000004e4f4 g 0f SECT 01 0000 [.text] __ZN30AMDRadeonX4000_AMDUVDHWChannelD0Ev 000000000004e4ea g 0f SECT 01 0000 [.text] __ZN30AMDRadeonX4000_AMDUVDHWChannelD1Ev 000000000004e4e0 g 0f SECT 01 0000 [.text] __ZN30AMDRadeonX4000_AMDUVDHWChannelD2Ev 000000000052dfb8 g 0f SECT 0a 0000 [__DATA.__common] __ZN30AMDRadeonX4000_AMDVCEHWChannel10gMetaClassE 00000000003a9e38 g 0f SECT 08 0000 [.const_data] __ZN30AMDRadeonX4000_AMDVCEHWChannel10superClassE 0000000000060eec g 0f SECT 01 0000 [.text] __ZN30AMDRadeonX4000_AMDVCEHWChannel19submitCommandBufferEP30AMD_SUBMIT_COMMAND_BUFFER_INFOPj 0000000000060ed8 g 0f SECT 01 0000 [.text] __ZN30AMDRadeonX4000_AMDVCEHWChannel20alignIBCommandBufferEPjj 0000000000060ee0 g 0f SECT 01 0000 [.text] __ZN30AMDRadeonX4000_AMDVCEHWChannel22timeStampInterruptTypeEv 0000000000060e9c g 0f SECT 01 0000 [.text] __ZN30AMDRadeonX4000_AMDVCEHWChannel4freeEv 0000000000060e3a g 0f SECT 01 0000 [.text] __ZN30AMDRadeonX4000_AMDVCEHWChannel4initEiP30AMDRadeonX4000_IAMDHWInterfaceP27AMDRadeonX4000_IAMDHWEngineP25AMDRadeonX4000_IAMDHWRingPKc 0000000000060d60 g 0f SECT 01 0000 [.text] __ZN30AMDRadeonX4000_AMDVCEHWChannel9MetaClassC1Ev 0000000000060e00 g 0f SECT 01 0000 [.text] __ZN30AMDRadeonX4000_AMDVCEHWChannel9MetaClassC2Ev 00000000003a9e30 g 0f SECT 08 0000 [.const_data] __ZN30AMDRadeonX4000_AMDVCEHWChannel9metaClassE 0000000000060d9c g 0f SECT 01 0000 [.text] __ZN30AMDRadeonX4000_AMDVCEHWChannelC2EPK11OSMetaClass 0000000000060dd0 g 0f SECT 01 0000 [.text] __ZN30AMDRadeonX4000_AMDVCEHWChannelD0Ev 0000000000060dc6 g 0f SECT 01 0000 [.text] __ZN30AMDRadeonX4000_AMDVCEHWChannelD1Ev 0000000000060dbc g 0f SECT 01 0000 [.text] __ZN30AMDRadeonX4000_AMDVCEHWChannelD2Ev 000000000052da68 g 0f SECT 0a 0000 [__DATA.__common] __ZN30AMDRadeonX4000_IAMDHWInterface10gMetaClassE 00000000003a3348 g 0f SECT 08 0000 [.const_data] __ZN30AMDRadeonX4000_IAMDHWInterface10superClassE 0000000000052560 g 0f SECT 01 0000 [.text] __ZN30AMDRadeonX4000_IAMDHWInterface9MetaClassC1Ev 0000000000052600 g 0f SECT 01 0000 [.text] __ZN30AMDRadeonX4000_IAMDHWInterface9MetaClassC2Ev 00000000003a3340 g 0f SECT 08 0000 [.const_data] __ZN30AMDRadeonX4000_IAMDHWInterface9metaClassE 000000000005259c g 0f SECT 01 0000 [.text] __ZN30AMDRadeonX4000_IAMDHWInterfaceC2EPK11OSMetaClass 00000000000525d0 g 0f SECT 01 0000 [.text] __ZN30AMDRadeonX4000_IAMDHWInterfaceD0Ev 00000000000525c6 g 0f SECT 01 0000 [.text] __ZN30AMDRadeonX4000_IAMDHWInterfaceD1Ev 00000000000525bc g 0f SECT 01 0000 [.text] __ZN30AMDRadeonX4000_IAMDHWInterfaceD2Ev 000000000052db08 g 0f SECT 0a 0000 [__DATA.__common] __ZN30AMDRadeonX4000_IAMDHWRegisters10gMetaClassE 00000000003a42b0 g 0f SECT 08 0000 [.const_data] __ZN30AMDRadeonX4000_IAMDHWRegisters10superClassE 00000000000528c8 g 0f SECT 01 0000 [.text] __ZN30AMDRadeonX4000_IAMDHWRegisters9MetaClassC1Ev 0000000000052968 g 0f SECT 01 0000 [.text] __ZN30AMDRadeonX4000_IAMDHWRegisters9MetaClassC2Ev 00000000003a42a8 g 0f SECT 08 0000 [.const_data] __ZN30AMDRadeonX4000_IAMDHWRegisters9metaClassE 0000000000052904 g 0f SECT 01 0000 [.text] __ZN30AMDRadeonX4000_IAMDHWRegistersC2EPK11OSMetaClass 0000000000052938 g 0f SECT 01 0000 [.text] __ZN30AMDRadeonX4000_IAMDHWRegistersD0Ev 000000000005292e g 0f SECT 01 0000 [.text] __ZN30AMDRadeonX4000_IAMDHWRegistersD1Ev 0000000000052924 g 0f SECT 01 0000 [.text] __ZN30AMDRadeonX4000_IAMDHWRegistersD2Ev 000000000052dba8 g 0f SECT 0a 0000 [__DATA.__common] __ZN30AMDRadeonX4000_IAMDHWSemaphore10gMetaClassE 00000000003a4df0 g 0f SECT 08 0000 [.const_data] __ZN30AMDRadeonX4000_IAMDHWSemaphore10superClassE 0000000000052c30 g 0f SECT 01 0000 [.text] __ZN30AMDRadeonX4000_IAMDHWSemaphore9MetaClassC1Ev 0000000000052cd0 g 0f SECT 01 0000 [.text] __ZN30AMDRadeonX4000_IAMDHWSemaphore9MetaClassC2Ev 00000000003a4de8 g 0f SECT 08 0000 [.const_data] __ZN30AMDRadeonX4000_IAMDHWSemaphore9metaClassE 0000000000052c6c g 0f SECT 01 0000 [.text] __ZN30AMDRadeonX4000_IAMDHWSemaphoreC2EPK11OSMetaClass 0000000000052ca0 g 0f SECT 01 0000 [.text] __ZN30AMDRadeonX4000_IAMDHWSemaphoreD0Ev 0000000000052c96 g 0f SECT 01 0000 [.text] __ZN30AMDRadeonX4000_IAMDHWSemaphoreD1Ev 0000000000052c8c g 0f SECT 01 0000 [.text] __ZN30AMDRadeonX4000_IAMDHWSemaphoreD2Ev 000000000052dc20 g 0f SECT 0a 0000 [__DATA.__common] __ZN30AMDRadeonX4000_IAMDHWUtilities10gMetaClassE 00000000003a5520 g 0f SECT 08 0000 [.const_data] __ZN30AMDRadeonX4000_IAMDHWUtilities10superClassE 0000000000052ebe g 0f SECT 01 0000 [.text] __ZN30AMDRadeonX4000_IAMDHWUtilities9MetaClassC1Ev 0000000000052f5e g 0f SECT 01 0000 [.text] __ZN30AMDRadeonX4000_IAMDHWUtilities9MetaClassC2Ev 00000000003a5518 g 0f SECT 08 0000 [.const_data] __ZN30AMDRadeonX4000_IAMDHWUtilities9metaClassE 0000000000052efa g 0f SECT 01 0000 [.text] __ZN30AMDRadeonX4000_IAMDHWUtilitiesC2EPK11OSMetaClass 0000000000052f2e g 0f SECT 01 0000 [.text] __ZN30AMDRadeonX4000_IAMDHWUtilitiesD0Ev 0000000000052f24 g 0f SECT 01 0000 [.text] __ZN30AMDRadeonX4000_IAMDHWUtilitiesD1Ev 0000000000052f1a g 0f SECT 01 0000 [.text] __ZN30AMDRadeonX4000_IAMDHWUtilitiesD2Ev 000000000052dce8 g 0f SECT 0a 0000 [__DATA.__common] __ZN30AMDRadeonX4000_IAMDHWVMContext10gMetaClassE 00000000003a6390 g 0f SECT 08 0000 [.const_data] __ZN30AMDRadeonX4000_IAMDHWVMContext10superClassE 0000000000053300 g 0f SECT 01 0000 [.text] __ZN30AMDRadeonX4000_IAMDHWVMContext9MetaClassC1Ev 00000000000533a0 g 0f SECT 01 0000 [.text] __ZN30AMDRadeonX4000_IAMDHWVMContext9MetaClassC2Ev 00000000003a6388 g 0f SECT 08 0000 [.const_data] __ZN30AMDRadeonX4000_IAMDHWVMContext9metaClassE 000000000005333c g 0f SECT 01 0000 [.text] __ZN30AMDRadeonX4000_IAMDHWVMContextC2EPK11OSMetaClass 0000000000053370 g 0f SECT 01 0000 [.text] __ZN30AMDRadeonX4000_IAMDHWVMContextD0Ev 0000000000053366 g 0f SECT 01 0000 [.text] __ZN30AMDRadeonX4000_IAMDHWVMContextD1Ev 000000000005335c g 0f SECT 01 0000 [.text] __ZN30AMDRadeonX4000_IAMDHWVMContextD2Ev 000000000052cf30 g 0f SECT 0a 0000 [__DATA.__common] __ZN31AMDRadeonX4000_AMDAccelResource10gMetaClassE 000000000000a914 g 0f SECT 01 0000 [.text] __ZN31AMDRadeonX4000_AMDAccelResource10initializeEP22IOAccelNewResourceArgsy 000000000038b5f8 g 0f SECT 08 0000 [.const_data] __ZN31AMDRadeonX4000_AMDAccelResource10superClassE 000000000000b4dc g 0f SECT 01 0000 [.text] __ZN31AMDRadeonX4000_AMDAccelResource11allocMemoryEP14IOAccelShared2 000000000000fac6 g 0f SECT 01 0000 [.text] __ZN31AMDRadeonX4000_AMDAccelResource11pageTextureEbP16IOAccelMemoryMapS1_ 000000000000ff0c g 0f SECT 01 0000 [.text] __ZN31AMDRadeonX4000_AMDAccelResource12addToChannelEP15IOAccelChannel2j 000000000000a738 g 0f SECT 01 0000 [.text] __ZN31AMDRadeonX4000_AMDAccelResource13addToApertureEv 000000000000c836 g 0f SECT 01 0000 [.text] __ZN31AMDRadeonX4000_AMDAccelResource13updateRefInfoEv 000000000000bd00 g 0f SECT 01 0000 [.text] __ZN31AMDRadeonX4000_AMDAccelResource14getLevelOffsetEhhPi 000000000000f2b8 g 0f SECT 01 0000 [.text] __ZN31AMDRadeonX4000_AMDAccelResource15MSAATextureReadEP26AMDTextureMSAAPagingPacketP16IOAccelMemoryMapy 000000000000de38 g 0f SECT 01 0000 [.text] __ZN31AMDRadeonX4000_AMDAccelResource15allocMaskMemoryEv 000000000000dfbe g 0f SECT 01 0000 [.text] __ZN31AMDRadeonX4000_AMDAccelResource15pageOnOffBufferEP13_UBM_SURFINFOS1_P16IOAccelMemoryMapS3_jP10_UBM_RECTLS5_ 000000000000f820 g 0f SECT 01 0000 [.text] __ZN31AMDRadeonX4000_AMDAccelResource16MSAATextureWriteEP26AMDTextureMSAAPagingPacketP16IOAccelMemoryMapy 000000000000a316 g 0f SECT 01 0000 [.text] __ZN31AMDRadeonX4000_AMDAccelResource16getVRAMMemoryMapEv 000000000000c9d4 g 0f SECT 01 0000 [.text] __ZN31AMDRadeonX4000_AMDAccelResource17prepareMaskMemoryE16_eMaskMemoryTypeP11IOAccelTask 000000000000cac2 g 0f SECT 01 0000 [.text] __ZN31AMDRadeonX4000_AMDAccelResource18completeMaskMemoryE16_eMaskMemoryType 000000000000ea62 g 0f SECT 01 0000 [.text] __ZN31AMDRadeonX4000_AMDAccelResource18createTempResourceEPK13_UBM_SURFINFO18eAMDTempBufferType 000000000000bf1a g 0f SECT 01 0000 [.text] __ZN31AMDRadeonX4000_AMDAccelResource18fillUBMSurfaceInfoEP13_UBM_SURFINFOP22_sMASK_MEMORY_SETTINGSjjj 000000000000cd20 g 0f SECT 01 0000 [.text] __ZN31AMDRadeonX4000_AMDAccelResource18freeVramMaskMemoryE16_eMaskMemoryType 000000000000c82e g 0f SECT 01 0000 [.text] __ZN31AMDRadeonX4000_AMDAccelResource18get_texture_offsetEy 000000000000a58a g 0f SECT 01 0000 [.text] __ZN31AMDRadeonX4000_AMDAccelResource18initMaskMemoryDataEv 000000000000e21c g 0f SECT 01 0000 [.text] __ZN31AMDRadeonX4000_AMDAccelResource18pageOff24d8sBufferEP13_UBM_SURFINFOS1_P16IOAccelMemoryMapS3_P10_UBM_RECTLS5_ 000000000000ee58 g 0f SECT 01 0000 [.text] __ZN31AMDRadeonX4000_AMDAccelResource18pageOffDepthBufferEP13_UBM_SURFINFOS1_P16IOAccelMemoryMapS3_P10_UBM_RECTLS5_ 000000000000a844 g 0f SECT 01 0000 [.text] __ZN31AMDRadeonX4000_AMDAccelResource18removeFromApertureEv 000000000000cbd6 g 0f SECT 01 0000 [.text] __ZN31AMDRadeonX4000_AMDAccelResource19allocVramMaskMemoryE16_eMaskMemoryTypejj15_eOP_ORIGINATOR 000000000000bcfa g 0f SECT 01 0000 [.text] __ZN31AMDRadeonX4000_AMDAccelResource19rebuildPagingBufferEv 000000000000c6f0 g 0f SECT 01 0000 [.text] __ZN31AMDRadeonX4000_AMDAccelResource20getGPUVirtualAddressEjjj 000000000000b876 g 0f SECT 01 0000 [.text] __ZN31AMDRadeonX4000_AMDAccelResource20prepareAllMaskMemoryEP11IOAccelTask 000000000000b916 g 0f SECT 01 0000 [.text] __ZN31AMDRadeonX4000_AMDAccelResource21completeAllMaskMemoryEv 000000000000bd9a g 0f SECT 01 0000 [.text] __ZN31AMDRadeonX4000_AMDAccelResource21getBackingLevelOffsetEhhPi 000000000001010a g 0f SECT 01 0000 [.text] __ZN31AMDRadeonX4000_AMDAccelResource21pageTextureWithMemcpyEbP16IOAccelMemoryMapS1_ 000000000000b4c4 g 0f SECT 01 0000 [.text] __ZN31AMDRadeonX4000_AMDAccelResource21setAllocMappingOptionEj 0000000000010014 g 0f SECT 01 0000 [.text] __ZN31AMDRadeonX4000_AMDAccelResource21switchToPagingChannelERNS_23switchPagingChannelInfoEb 000000000000d20a g 0f SECT 01 0000 [.text] __ZN31AMDRadeonX4000_AMDAccelResource22generateTextureMipMapsEP16IOAccelMemoryMap 000000000000c518 g 0f SECT 01 0000 [.text] __ZN31AMDRadeonX4000_AMDAccelResource22getMaskMemoryUBMHandleE16_eMaskMemoryType 000000000000e520 g 0f SECT 01 0000 [.text] __ZN31AMDRadeonX4000_AMDAccelResource22pageOffMSAADepthBufferEP13_UBM_SURFINFOS1_P16IOAccelMemoryMapS3_P10_UBM_RECTLS5_jj 0000000000010c1e g 0f SECT 01 0000 [.text] __ZN31AMDRadeonX4000_AMDAccelResource22pageTextureWithStretchEbP16IOAccelMemoryMapS1_ 000000000000de58 g 0f SECT 01 0000 [.text] __ZN31AMDRadeonX4000_AMDAccelResource23copyTheProvidedResourceEPKS_ 000000000000cd94 g 0f SECT 01 0000 [.text] __ZN31AMDRadeonX4000_AMDAccelResource23freeMaskMemoryResourcesEb 000000000000a55e g 0f SECT 01 0000 [.text] __ZN31AMDRadeonX4000_AMDAccelResource23getMemoryAllocParameterEv 0000000000011434 g 0f SECT 01 0000 [.text] __ZN31AMDRadeonX4000_AMDAccelResource23pageTextureDepthStencilEbP16IOAccelMemoryMapS1_ 000000000000ce10 g 0f SECT 01 0000 [.text] __ZN31AMDRadeonX4000_AMDAccelResource24expandMaskMemoryIfNeededE16_eMaskMemoryTypeP16IOAccelMemoryMap 000000000000cb96 g 0f SECT 01 0000 [.text] __ZN31AMDRadeonX4000_AMDAccelResource24freeMaskMemoryDescriptorE16_eMaskMemoryType 000000000000cff0 g 0f SECT 01 0000 [.text] __ZN31AMDRadeonX4000_AMDAccelResource24getAlignmentRequirementsEPjPy 00000000000100b6 g 0f SECT 01 0000 [.text] __ZN31AMDRadeonX4000_AMDAccelResource24restoreFromPagingChannelERNS_23switchPagingChannelInfoE 000000000000cae6 g 0f SECT 01 0000 [.text] __ZN31AMDRadeonX4000_AMDAccelResource25allocMaskMemoryDescriptorE16_eMaskMemoryType 000000000000b63a g 0f SECT 01 0000 [.text] __ZN31AMDRadeonX4000_AMDAccelResource25isBackingAllocationLinearEv 000000000000dace g 0f SECT 01 0000 [.text] __ZN31AMDRadeonX4000_AMDAccelResource26allocColorBufferMaskMemoryEv 000000000000a41c g 0f SECT 01 0000 [.text] __ZN31AMDRadeonX4000_AMDAccelResource26configureAllocationOptionsEv 000000000000bfb6 g 0f SECT 01 0000 [.text] __ZN31AMDRadeonX4000_AMDAccelResource26fillUBMSurfaceInfoInternalEP13_UBM_SURFINFOP22_sMASK_MEMORY_SETTINGSP16IOAccelMemoryMapPS_jjj 0000000000010824 g 0f SECT 01 0000 [.text] __ZN31AMDRadeonX4000_AMDAccelResource26pageTextureWithSurfaceCopyEbP16IOAccelMemoryMapS1_ 000000000000a8ce g 0f SECT 01 0000 [.text] __ZN31AMDRadeonX4000_AMDAccelResource27getApertureMemoryDescriptorEPy 000000000000cfb0 g 0f SECT 01 0000 [.text] __ZN31AMDRadeonX4000_AMDAccelResource29determineMaskMemoryAllocBytesEjRjPK31_AMD_MASK_SURFACE_BUFFER_PARAMS 000000000000a6f2 g 0f SECT 01 0000 [.text] __ZN31AMDRadeonX4000_AMDAccelResource30getMaskMemoryGPUVirtualAddressE16_eMaskMemoryType 000000000001053c g 0f SECT 01 0000 [.text] __ZN31AMDRadeonX4000_AMDAccelResource30pageTextureWithMemcpyNoVendBufEbP16IOAccelMemoryMapS1_ 0000000000011036 g 0f SECT 01 0000 [.text] __ZN31AMDRadeonX4000_AMDAccelResource31pageTextureWithStretchNoVendBufEbP16IOAccelMemoryMapS1_ 000000000000dd6e g 0f SECT 01 0000 [.text] __ZN31AMDRadeonX4000_AMDAccelResource33allocDepthStencilBufferMaskMemoryEv 000000000000be34 g 0f SECT 01 0000 [.text] __ZN31AMDRadeonX4000_AMDAccelResource38calculateIOSurfaceDeviceCacheVRAMBytesEPyPj 000000000000d486 g 0f SECT 01 0000 [.text] __ZN31AMDRadeonX4000_AMDAccelResource43determineMaskMemoryAllocBytesForColorBufferEjRjbPK31_AMD_MASK_SURFACE_BUFFER_PARAMS 000000000000a31e g 0f SECT 01 0000 [.text] __ZN31AMDRadeonX4000_AMDAccelResource4freeEv 000000000000a1ba g 0f SECT 01 0000 [.text] __ZN31AMDRadeonX4000_AMDAccelResource4initEP22IOGraphicsAccelerator2P14IOAccelShared2j 000000000000d8f0 g 0f SECT 01 0000 [.text] __ZN31AMDRadeonX4000_AMDAccelResource50determineMaskMemoryAllocBytesForDepthStencilBufferEjRjPK31_AMD_MASK_SURFACE_BUFFER_PARAMS 000000000000b642 g 0f SECT 01 0000 [.text] __ZN31AMDRadeonX4000_AMDAccelResource6pageonEP12IOAccelEventb 000000000000b95a g 0f SECT 01 0000 [.text] __ZN31AMDRadeonX4000_AMDAccelResource7pageoffEP12IOAccelEventbPb 000000000000fe88 g 0f SECT 01 0000 [.text] __ZN31AMDRadeonX4000_AMDAccelResource7prepareEv 000000000000fee8 g 0f SECT 01 0000 [.text] __ZN31AMDRadeonX4000_AMDAccelResource8completeEv 000000000000b59c g 0f SECT 01 0000 [.text] __ZN31AMDRadeonX4000_AMDAccelResource8fallbackEv 000000000000a0e0 g 0f SECT 01 0000 [.text] __ZN31AMDRadeonX4000_AMDAccelResource9MetaClassC1Ev 000000000000a180 g 0f SECT 01 0000 [.text] __ZN31AMDRadeonX4000_AMDAccelResource9MetaClassC2Ev 000000000038b5f0 g 0f SECT 08 0000 [.const_data] __ZN31AMDRadeonX4000_AMDAccelResource9metaClassE 000000000000a11c g 0f SECT 01 0000 [.text] __ZN31AMDRadeonX4000_AMDAccelResourceC2EPK11OSMetaClass 000000000000a150 g 0f SECT 01 0000 [.text] __ZN31AMDRadeonX4000_AMDAccelResourceD0Ev 000000000000a146 g 0f SECT 01 0000 [.text] __ZN31AMDRadeonX4000_AMDAccelResourceD1Ev 000000000000a13c g 0f SECT 01 0000 [.text] __ZN31AMDRadeonX4000_AMDAccelResourceD2Ev 000000000052d9c8 g 0f SECT 0a 0000 [__DATA.__common] __ZN31AMDRadeonX4000_AMDNullHWChannel10gMetaClassE 00000000003a26d8 g 0f SECT 08 0000 [.const_data] __ZN31AMDRadeonX4000_AMDNullHWChannel10superClassE 00000000000502c0 g 0f SECT 01 0000 [.text] __ZN31AMDRadeonX4000_AMDNullHWChannel9MetaClassC1Ev 0000000000050380 g 0f SECT 01 0000 [.text] __ZN31AMDRadeonX4000_AMDNullHWChannel9MetaClassC2Ev 00000000003a26d0 g 0f SECT 08 0000 [.const_data] __ZN31AMDRadeonX4000_AMDNullHWChannel9metaClassE 000000000005031c g 0f SECT 01 0000 [.text] __ZN31AMDRadeonX4000_AMDNullHWChannelC1EPK11OSMetaClass 00000000000503f2 g 0f SECT 01 0000 [.text] __ZN31AMDRadeonX4000_AMDNullHWChannelC1Ev 00000000000502fc g 0f SECT 01 0000 [.text] __ZN31AMDRadeonX4000_AMDNullHWChannelC2EPK11OSMetaClass 0000000000050422 g 0f SECT 01 0000 [.text] __ZN31AMDRadeonX4000_AMDNullHWChannelC2Ev 0000000000050350 g 0f SECT 01 0000 [.text] __ZN31AMDRadeonX4000_AMDNullHWChannelD0Ev 0000000000050346 g 0f SECT 01 0000 [.text] __ZN31AMDRadeonX4000_AMDNullHWChannelD1Ev 000000000005033c g 0f SECT 01 0000 [.text] __ZN31AMDRadeonX4000_AMDNullHWChannelD2Ev 000000000052d0c0 g 0f SECT 0a 0000 [__DATA.__common] __ZN31AMDRadeonX4000_AMDSPUAppContext10gMetaClassE 000000000001b5b6 g 0f SECT 01 0000 [.text] __ZN31AMDRadeonX4000_AMDSPUAppContext10pageBufferEP13_AMDSPUMemoryb 000000000001b1be g 0f SECT 01 0000 [.text] __ZN31AMDRadeonX4000_AMDSPUAppContext10setSessionEjjj 000000000038f8e8 g 0f SECT 08 0000 [.const_data] __ZN31AMDRadeonX4000_AMDSPUAppContext10superClassE 000000000001b20c g 0f SECT 01 0000 [.text] __ZN31AMDRadeonX4000_AMDSPUAppContext11findSessionEjPj 000000000001b240 g 0f SECT 01 0000 [.text] __ZN31AMDRadeonX4000_AMDSPUAppContext13createSessionEPj 000000000001b67e g 0f SECT 01 0000 [.text] __ZN31AMDRadeonX4000_AMDSPUAppContext13releaseBufferE17_AMDSPUMemoryTypeb 000000000001b298 g 0f SECT 01 0000 [.text] __ZN31AMDRadeonX4000_AMDSPUAppContext14allocateBufferE17_AMDSPUMemoryTypejjb 000000000001b1e6 g 0f SECT 01 0000 [.text] __ZN31AMDRadeonX4000_AMDSPUAppContext14releaseSessionEj 000000000001b150 g 0f SECT 01 0000 [.text] __ZN31AMDRadeonX4000_AMDSPUAppContext15releaseFeedbackEv 000000000001b020 g 0f SECT 01 0000 [.text] __ZN31AMDRadeonX4000_AMDSPUAppContext16allocateFeedbackEv 000000000001b7bc g 0f SECT 01 0000 [.text] __ZN31AMDRadeonX4000_AMDSPUAppContext17getFeedBackStatusEv 000000000001b770 g 0f SECT 01 0000 [.text] __ZN31AMDRadeonX4000_AMDSPUAppContext18releaseStateBufferEP13_AMDSPUMemory 000000000001b550 g 0f SECT 01 0000 [.text] __ZN31AMDRadeonX4000_AMDSPUAppContext19allocateStateBufferEP13_AMDSPUMemory 000000000001b110 g 0f SECT 01 0000 [.text] __ZN31AMDRadeonX4000_AMDSPUAppContext4freeEv 000000000001ade2 g 0f SECT 01 0000 [.text] __ZN31AMDRadeonX4000_AMDSPUAppContext4initEP30AMDRadeonX4000_IAMDHWInterfacej17_AMD_SPU_APP_TYPE 000000000001ac50 g 0f SECT 01 0000 [.text] __ZN31AMDRadeonX4000_AMDSPUAppContext9MetaClassC1Ev 000000000001ad10 g 0f SECT 01 0000 [.text] __ZN31AMDRadeonX4000_AMDSPUAppContext9MetaClassC2Ev 000000000038f8e0 g 0f SECT 08 0000 [.const_data] __ZN31AMDRadeonX4000_AMDSPUAppContext9metaClassE 000000000001acac g 0f SECT 01 0000 [.text] __ZN31AMDRadeonX4000_AMDSPUAppContextC1EPK11OSMetaClass 000000000001ad82 g 0f SECT 01 0000 [.text] __ZN31AMDRadeonX4000_AMDSPUAppContextC1Ev 000000000001ac8c g 0f SECT 01 0000 [.text] __ZN31AMDRadeonX4000_AMDSPUAppContextC2EPK11OSMetaClass 000000000001adb2 g 0f SECT 01 0000 [.text] __ZN31AMDRadeonX4000_AMDSPUAppContextC2Ev 000000000001ace0 g 0f SECT 01 0000 [.text] __ZN31AMDRadeonX4000_AMDSPUAppContextD0Ev 000000000001acd6 g 0f SECT 01 0000 [.text] __ZN31AMDRadeonX4000_AMDSPUAppContextD1Ev 000000000001accc g 0f SECT 01 0000 [.text] __ZN31AMDRadeonX4000_AMDSPUAppContextD2Ev 000000000052ee40 g 0f SECT 0a 0000 [__DATA.__common] __ZN31AMDRadeonX4000_IAMDSMLInterface10gMetaClassE 00000000003c0ad0 g 0f SECT 08 0000 [.const_data] __ZN31AMDRadeonX4000_IAMDSMLInterface10superClassE 0000000000124288 g 0f SECT 01 0000 [.text] __ZN31AMDRadeonX4000_IAMDSMLInterface9MetaClassC1Ev 0000000000124328 g 0f SECT 01 0000 [.text] __ZN31AMDRadeonX4000_IAMDSMLInterface9MetaClassC2Ev 00000000003c0ac8 g 0f SECT 08 0000 [.const_data] __ZN31AMDRadeonX4000_IAMDSMLInterface9metaClassE 00000000001242c4 g 0f SECT 01 0000 [.text] __ZN31AMDRadeonX4000_IAMDSMLInterfaceC2EPK11OSMetaClass 00000000001242f8 g 0f SECT 01 0000 [.text] __ZN31AMDRadeonX4000_IAMDSMLInterfaceD0Ev 00000000001242ee g 0f SECT 01 0000 [.text] __ZN31AMDRadeonX4000_IAMDSMLInterfaceD1Ev 00000000001242e4 g 0f SECT 01 0000 [.text] __ZN31AMDRadeonX4000_IAMDSMLInterfaceD2Ev 000000000052cff8 g 0f SECT 0a 0000 [__DATA.__common] __ZN32AMDRadeonX4000_AMDAccel2DContext10gMetaClassE 000000000038d4b8 g 0f SECT 08 0000 [.const_data] __ZN32AMDRadeonX4000_AMDAccel2DContext10superClassE 00000000000160a4 g 0f SECT 01 0000 [.text] __ZN32AMDRadeonX4000_AMDAccel2DContext11contextStopEv 0000000000016092 g 0f SECT 01 0000 [.text] __ZN32AMDRadeonX4000_AMDAccel2DContext12contextStartEv 00000000000167ba g 0f SECT 01 0000 [.text] __ZN32AMDRadeonX4000_AMDAccel2DContext23isCopyOfSourceNecessaryEP16_UBM_STRETCHINFO 00000000000160b6 g 0f SECT 01 0000 [.text] __ZN32AMDRadeonX4000_AMDAccel2DContext8blitCopyEP12IOAccelEventP16IOAccelResource2S3_P22IOAccel2DBlitRectStrucj 0000000000016826 g 0f SECT 01 0000 [.text] __ZN32AMDRadeonX4000_AMDAccel2DContext8blitFillEP12IOAccelEventjP16IOAccelResource2P22IOAccel2DBlitRectStrucj 0000000000015f00 g 0f SECT 01 0000 [.text] __ZN32AMDRadeonX4000_AMDAccel2DContext9MetaClassC1Ev 0000000000015fc0 g 0f SECT 01 0000 [.text] __ZN32AMDRadeonX4000_AMDAccel2DContext9MetaClassC2Ev 000000000038d4b0 g 0f SECT 08 0000 [.const_data] __ZN32AMDRadeonX4000_AMDAccel2DContext9metaClassE 0000000000015f5c g 0f SECT 01 0000 [.text] __ZN32AMDRadeonX4000_AMDAccel2DContextC1EPK11OSMetaClass 0000000000016032 g 0f SECT 01 0000 [.text] __ZN32AMDRadeonX4000_AMDAccel2DContextC1Ev 0000000000015f3c g 0f SECT 01 0000 [.text] __ZN32AMDRadeonX4000_AMDAccel2DContextC2EPK11OSMetaClass 0000000000016062 g 0f SECT 01 0000 [.text] __ZN32AMDRadeonX4000_AMDAccel2DContextC2Ev 0000000000015f90 g 0f SECT 01 0000 [.text] __ZN32AMDRadeonX4000_AMDAccel2DContextD0Ev 0000000000015f86 g 0f SECT 01 0000 [.text] __ZN32AMDRadeonX4000_AMDAccel2DContextD1Ev 0000000000015f7c g 0f SECT 01 0000 [.text] __ZN32AMDRadeonX4000_AMDAccel2DContextD2Ev 000000000052d478 g 0f SECT 0a 0000 [__DATA.__common] __ZN32AMDRadeonX4000_AMDAccelCLContext10gMetaClassE 0000000000392018 g 0f SECT 08 0000 [.const_data] __ZN32AMDRadeonX4000_AMDAccelCLContext10superClassE 0000000000026846 g 0f SECT 01 0000 [.text] __ZN32AMDRadeonX4000_AMDAccelCLContext11contextStopEv 000000000002664a g 0f SECT 01 0000 [.text] __ZN32AMDRadeonX4000_AMDAccelCLContext12contextStartEv 0000000000026b20 g 0f SECT 01 0000 [.text] __ZN32AMDRadeonX4000_AMDAccelCLContext13enableContextEv 0000000000026bde g 0f SECT 01 0000 [.text] __ZN32AMDRadeonX4000_AMDAccelCLContext14disableContextEv 000000000002696e g 0f SECT 01 0000 [.text] __ZN32AMDRadeonX4000_AMDAccelCLContext16endCommandStreamER24IOAccelCommandStreamInfo 0000000000026950 g 0f SECT 01 0000 [.text] __ZN32AMDRadeonX4000_AMDAccelCLContext18beginCommandStreamER24IOAccelCommandStreamInfo 0000000000026ec2 g 0f SECT 01 0000 [.text] __ZN32AMDRadeonX4000_AMDAccelCLContext21allocAndLoadResourcesEv 0000000000026abe g 0f SECT 01 0000 [.text] __ZN32AMDRadeonX4000_AMDAccelCLContext22addDataBufferToChannelEP16IOAccelResource2j 0000000000026e4e g 0f SECT 01 0000 [.text] __ZN32AMDRadeonX4000_AMDAccelCLContext22addToKeepResourcesListEP16IOAccelResource2j 0000000000026c86 g 0f SECT 01 0000 [.text] __ZN32AMDRadeonX4000_AMDAccelCLContext22remapComputeRingBufferEv 000000000012f690 g 0f SECT 03 0000 [.const] __ZN32AMDRadeonX4000_AMDAccelCLContext23submitRingBufferEntriesE 0000000000026d94 g 0f SECT 01 0000 [.text] __ZN32AMDRadeonX4000_AMDAccelCLContext25checkSubmitRingBufferFullEv 0000000000026be8 g 0f SECT 01 0000 [.text] __ZN32AMDRadeonX4000_AMDAccelCLContext25teardownComputeRingBufferEv 0000000000026dc4 g 0f SECT 01 0000 [.text] __ZN32AMDRadeonX4000_AMDAccelCLContext27finishAndCleanupAllContextsEv 0000000000026b2a g 0f SECT 01 0000 [.text] __ZN32AMDRadeonX4000_AMDAccelCLContext27reallocateComputeRingBufferEv 0000000000026af4 g 0f SECT 01 0000 [.text] __ZN32AMDRadeonX4000_AMDAccelCLContext27removeDataBufferFromChannelEP16IOAccelResource2j 000000000002713a g 0f SECT 01 0000 [.text] __ZN32AMDRadeonX4000_AMDAccelCLContext33pageOffAndDeallocateKeepResourcesEv 0000000000026570 g 0f SECT 01 0000 [.text] __ZN32AMDRadeonX4000_AMDAccelCLContext9MetaClassC1Ev 0000000000026610 g 0f SECT 01 0000 [.text] __ZN32AMDRadeonX4000_AMDAccelCLContext9MetaClassC2Ev 0000000000392010 g 0f SECT 08 0000 [.const_data] __ZN32AMDRadeonX4000_AMDAccelCLContext9metaClassE 00000000000265ac g 0f SECT 01 0000 [.text] __ZN32AMDRadeonX4000_AMDAccelCLContextC2EPK11OSMetaClass 00000000000265e0 g 0f SECT 01 0000 [.text] __ZN32AMDRadeonX4000_AMDAccelCLContextD0Ev 00000000000265d6 g 0f SECT 01 0000 [.text] __ZN32AMDRadeonX4000_AMDAccelCLContextD1Ev 00000000000265cc g 0f SECT 01 0000 [.text] __ZN32AMDRadeonX4000_AMDAccelCLContextD2Ev 000000000052d518 g 0f SECT 0a 0000 [__DATA.__common] __ZN32AMDRadeonX4000_AMDAccelMemoryMap10gMetaClassE 0000000000393438 g 0f SECT 08 0000 [.const_data] __ZN32AMDRadeonX4000_AMDAccelMemoryMap10superClassE 0000000000028d2a g 0f SECT 01 0000 [.text] __ZN32AMDRadeonX4000_AMDAccelMemoryMap18updateGPUPageTableEv 00000000000289f0 g 0f SECT 01 0000 [.text] __ZN32AMDRadeonX4000_AMDAccelMemoryMap20getGPUVirtualAddressEv 0000000000028a26 g 0f SECT 01 0000 [.text] __ZN32AMDRadeonX4000_AMDAccelMemoryMap21getGPUPhysicalAddressEv 0000000000028a9a g 0f SECT 01 0000 [.text] __ZN32AMDRadeonX4000_AMDAccelMemoryMap22commitIntoGPUPageTableEv 0000000000028c74 g 0f SECT 01 0000 [.text] __ZN32AMDRadeonX4000_AMDAccelMemoryMap23releaseFromGPUPageTableEv 000000000002889e g 0f SECT 01 0000 [.text] __ZN32AMDRadeonX4000_AMDAccelMemoryMap24initWithVidMemoryOptionsEP22IOGraphicsAccelerator2P14IOAccelShared2P11IOAccelTaskjyy15_eOP_ORIGINATOR9_eOP_TYPE 000000000002884e g 0f SECT 01 0000 [.text] __ZN32AMDRadeonX4000_AMDAccelMemoryMap4freeEv 00000000000286a2 g 0f SECT 01 0000 [.text] __ZN32AMDRadeonX4000_AMDAccelMemoryMap4initEP22IOGraphicsAccelerator2P11IOAccelTaskP13IOAccelMemoryj 0000000000028d38 g 0f SECT 01 0000 [.text] __ZN32AMDRadeonX4000_AMDAccelMemoryMap5remapEy 0000000000028958 g 0f SECT 01 0000 [.text] __ZN32AMDRadeonX4000_AMDAccelMemoryMap7prepareEv 0000000000028510 g 0f SECT 01 0000 [.text] __ZN32AMDRadeonX4000_AMDAccelMemoryMap9MetaClassC1Ev 00000000000285d0 g 0f SECT 01 0000 [.text] __ZN32AMDRadeonX4000_AMDAccelMemoryMap9MetaClassC2Ev 0000000000393430 g 0f SECT 08 0000 [.const_data] __ZN32AMDRadeonX4000_AMDAccelMemoryMap9metaClassE 000000000002856c g 0f SECT 01 0000 [.text] __ZN32AMDRadeonX4000_AMDAccelMemoryMapC1EPK11OSMetaClass 0000000000028642 g 0f SECT 01 0000 [.text] __ZN32AMDRadeonX4000_AMDAccelMemoryMapC1Ev 000000000002854c g 0f SECT 01 0000 [.text] __ZN32AMDRadeonX4000_AMDAccelMemoryMapC2EPK11OSMetaClass 0000000000028672 g 0f SECT 01 0000 [.text] __ZN32AMDRadeonX4000_AMDAccelMemoryMapC2Ev 00000000000285a0 g 0f SECT 01 0000 [.text] __ZN32AMDRadeonX4000_AMDAccelMemoryMapD0Ev 0000000000028596 g 0f SECT 01 0000 [.text] __ZN32AMDRadeonX4000_AMDAccelMemoryMapD1Ev 000000000002858c g 0f SECT 01 0000 [.text] __ZN32AMDRadeonX4000_AMDAccelMemoryMapD2Ev 000000000052d4c8 g 0f SECT 0a 0000 [__DATA.__common] __ZN32AMDRadeonX4000_AMDAccelSysMemory10gMetaClassE 0000000000392e98 g 0f SECT 08 0000 [.const_data] __ZN32AMDRadeonX4000_AMDAccelSysMemory10superClassE 0000000000027c88 g 0f SECT 01 0000 [.text] __ZN32AMDRadeonX4000_AMDAccelSysMemory4freeEv 0000000000027c62 g 0f SECT 01 0000 [.text] __ZN32AMDRadeonX4000_AMDAccelSysMemory4initEP22IOGraphicsAccelerator2 0000000000027ad0 g 0f SECT 01 0000 [.text] __ZN32AMDRadeonX4000_AMDAccelSysMemory9MetaClassC1Ev 0000000000027b90 g 0f SECT 01 0000 [.text] __ZN32AMDRadeonX4000_AMDAccelSysMemory9MetaClassC2Ev 0000000000392e90 g 0f SECT 08 0000 [.const_data] __ZN32AMDRadeonX4000_AMDAccelSysMemory9metaClassE 0000000000027b2c g 0f SECT 01 0000 [.text] __ZN32AMDRadeonX4000_AMDAccelSysMemoryC1EPK11OSMetaClass 0000000000027c02 g 0f SECT 01 0000 [.text] __ZN32AMDRadeonX4000_AMDAccelSysMemoryC1Ev 0000000000027b0c g 0f SECT 01 0000 [.text] __ZN32AMDRadeonX4000_AMDAccelSysMemoryC2EPK11OSMetaClass 0000000000027c32 g 0f SECT 01 0000 [.text] __ZN32AMDRadeonX4000_AMDAccelSysMemoryC2Ev 0000000000027b60 g 0f SECT 01 0000 [.text] __ZN32AMDRadeonX4000_AMDAccelSysMemoryD0Ev 0000000000027b56 g 0f SECT 01 0000 [.text] __ZN32AMDRadeonX4000_AMDAccelSysMemoryD1Ev 0000000000027b4c g 0f SECT 01 0000 [.text] __ZN32AMDRadeonX4000_AMDAccelSysMemoryD2Ev 000000000052d4f0 g 0f SECT 0a 0000 [__DATA.__common] __ZN32AMDRadeonX4000_AMDAccelVidMemory10gMetaClassE 0000000000393158 g 0f SECT 08 0000 [.const_data] __ZN32AMDRadeonX4000_AMDAccelVidMemory10superClassE 0000000000028144 g 0f SECT 01 0000 [.text] __ZN32AMDRadeonX4000_AMDAccelVidMemory13allocPhysicalEv 00000000000280b0 g 0f SECT 01 0000 [.text] __ZN32AMDRadeonX4000_AMDAccelVidMemory13matchForReuseEPvy 00000000000283e6 g 0f SECT 01 0000 [.text] __ZN32AMDRadeonX4000_AMDAccelVidMemory15deallocPhysicalEv 0000000000028074 g 0f SECT 01 0000 [.text] __ZN32AMDRadeonX4000_AMDAccelVidMemory18getPhysicalSegmentEyPy 000000000002802a g 0f SECT 01 0000 [.text] __ZN32AMDRadeonX4000_AMDAccelVidMemory19withPhysicalAddressEP22IOGraphicsAccelerator2yyP25_AMD_VID_MEM_ALLOC_PARAMS 0000000000028470 g 0f SECT 01 0000 [.text] __ZN32AMDRadeonX4000_AMDAccelVidMemory21setAllocMappingOptionEj 0000000000027fee g 0f SECT 01 0000 [.text] __ZN32AMDRadeonX4000_AMDAccelVidMemory4freeEv 0000000000027ed2 g 0f SECT 01 0000 [.text] __ZN32AMDRadeonX4000_AMDAccelVidMemory4initEP22IOGraphicsAccelerator2P14IOAccelShared2P16IOAccelResource2yPv 0000000000027d40 g 0f SECT 01 0000 [.text] __ZN32AMDRadeonX4000_AMDAccelVidMemory9MetaClassC1Ev 0000000000027e00 g 0f SECT 01 0000 [.text] __ZN32AMDRadeonX4000_AMDAccelVidMemory9MetaClassC2Ev 0000000000393150 g 0f SECT 08 0000 [.const_data] __ZN32AMDRadeonX4000_AMDAccelVidMemory9metaClassE 0000000000027d9c g 0f SECT 01 0000 [.text] __ZN32AMDRadeonX4000_AMDAccelVidMemoryC1EPK11OSMetaClass 0000000000027e72 g 0f SECT 01 0000 [.text] __ZN32AMDRadeonX4000_AMDAccelVidMemoryC1Ev 0000000000027d7c g 0f SECT 01 0000 [.text] __ZN32AMDRadeonX4000_AMDAccelVidMemoryC2EPK11OSMetaClass 0000000000027ea2 g 0f SECT 01 0000 [.text] __ZN32AMDRadeonX4000_AMDAccelVidMemoryC2Ev 0000000000027dd0 g 0f SECT 01 0000 [.text] __ZN32AMDRadeonX4000_AMDAccelVidMemoryD0Ev 0000000000027dc6 g 0f SECT 01 0000 [.text] __ZN32AMDRadeonX4000_AMDAccelVidMemoryD1Ev 0000000000027dbc g 0f SECT 01 0000 [.text] __ZN32AMDRadeonX4000_AMDAccelVidMemoryD2Ev 000000000052efd0 g 0f SECT 0a 0000 [__DATA.__common] __ZN32AMDRadeonX4000_AMDHDCPGetCertMsg10gMetaClassE 00000000003c2550 g 0f SECT 08 0000 [.const_data] __ZN32AMDRadeonX4000_AMDHDCPGetCertMsg10superClassE 0000000000126b06 g 0f SECT 01 0000 [.text] __ZN32AMDRadeonX4000_AMDHDCPGetCertMsg12setOutBufferEiyPh 0000000000126af4 g 0f SECT 01 0000 [.text] __ZN32AMDRadeonX4000_AMDHDCPGetCertMsg4freeEv 0000000000126a48 g 0f SECT 01 0000 [.text] __ZN32AMDRadeonX4000_AMDHDCPGetCertMsg4initEPv 00000000001268b6 g 0f SECT 01 0000 [.text] __ZN32AMDRadeonX4000_AMDHDCPGetCertMsg9MetaClassC1Ev 0000000000126976 g 0f SECT 01 0000 [.text] __ZN32AMDRadeonX4000_AMDHDCPGetCertMsg9MetaClassC2Ev 0000000000126b2a g 0f SECT 01 0000 [.text] __ZN32AMDRadeonX4000_AMDHDCPGetCertMsg9getOutputEv 00000000003c2548 g 0f SECT 08 0000 [.const_data] __ZN32AMDRadeonX4000_AMDHDCPGetCertMsg9metaClassE 0000000000126912 g 0f SECT 01 0000 [.text] __ZN32AMDRadeonX4000_AMDHDCPGetCertMsgC1EPK11OSMetaClass 00000000001269e8 g 0f SECT 01 0000 [.text] __ZN32AMDRadeonX4000_AMDHDCPGetCertMsgC1Ev 00000000001268f2 g 0f SECT 01 0000 [.text] __ZN32AMDRadeonX4000_AMDHDCPGetCertMsgC2EPK11OSMetaClass 0000000000126a18 g 0f SECT 01 0000 [.text] __ZN32AMDRadeonX4000_AMDHDCPGetCertMsgC2Ev 0000000000126946 g 0f SECT 01 0000 [.text] __ZN32AMDRadeonX4000_AMDHDCPGetCertMsgD0Ev 000000000012693c g 0f SECT 01 0000 [.text] __ZN32AMDRadeonX4000_AMDHDCPGetCertMsgD1Ev 0000000000126932 g 0f SECT 01 0000 [.text] __ZN32AMDRadeonX4000_AMDHDCPGetCertMsgD2Ev 000000000052d9a0 g 0f SECT 0a 0000 [__DATA.__common] __ZN32AMDRadeonX4000_AMDHWAlignManager10gMetaClassE 00000000003a23f8 g 0f SECT 08 0000 [.const_data] __ZN32AMDRadeonX4000_AMDHWAlignManager10superClassE 000000000004fdf4 g 0f SECT 01 0000 [.text] __ZN32AMDRadeonX4000_AMDHWAlignManager12getCMaskInfoEP29_ADDR_COMPUTE_CMASKINFO_INPUTP31_ADDR_COMPUTE_CMASK_INFO_OUTPUT 000000000004fe4e g 0f SECT 01 0000 [.text] __ZN32AMDRadeonX4000_AMDHWAlignManager12getFMaskInfoEP30_ADDR_COMPUTE_FMASK_INFO_INPUTP31_ADDR_COMPUTE_FMASK_INFO_OUTPUTP14_ADDR_TILEINFOS5_ 000000000004fd9a g 0f SECT 01 0000 [.text] __ZN32AMDRadeonX4000_AMDHWAlignManager12getHTileInfoEP30_ADDR_COMPUTE_HTILE_INFO_INPUTP31_ADDR_COMPUTE_HTILE_INFO_OUTPUT 0000000000050002 g 0f SECT 01 0000 [.text] __ZN32AMDRadeonX4000_AMDHWAlignManager12getTileIndexE13_AddrTileMode13_AddrTileTypeP14_ADDR_TILEINFO 000000000004ff7e g 0f SECT 01 0000 [.text] __ZN32AMDRadeonX4000_AMDHWAlignManager13getAddrFormatEj 000000000005009e g 0f SECT 01 0000 [.text] __ZN32AMDRadeonX4000_AMDHWAlignManager14fillTilingInfoEP15AMD_TILING_INFOPK14_ADDR_TILEINFO13_AddrTileModei13_AddrTileType 000000000004fa3e g 0f SECT 01 0000 [.text] __ZN32AMDRadeonX4000_AMDHWAlignManager14getStencilInfoEP32_ADDR_COMPUTE_SURFACE_INFO_INPUTP33_ADDR_COMPUTE_SURFACE_INFO_OUTPUTP14_ADDR_TILEINFOS5_ 000000000004f97c g 0f SECT 01 0000 [.text] __ZN32AMDRadeonX4000_AMDHWAlignManager14getSurfaceInfoEP32_ADDR_COMPUTE_SURFACE_INFO_INPUTP33_ADDR_COMPUTE_SURFACE_INFO_OUTPUTP14_ADDR_TILEINFO 0000000000050060 g 0f SECT 01 0000 [.text] __ZN32AMDRadeonX4000_AMDHWAlignManager15fillSurfaceInfoEP30_ADDR_COMPUTE_HTILE_INFO_INPUT 00000000000501a4 g 0f SECT 01 0000 [.text] __ZN32AMDRadeonX4000_AMDHWAlignManager16fillAddrTileInfoEP14_ADDR_TILEINFOPK15AMD_TILING_INFO 000000000004ff68 g 0f SECT 01 0000 [.text] __ZN32AMDRadeonX4000_AMDHWAlignManager16isTileModeLinearEj 000000000004f924 g 0f SECT 01 0000 [.text] __ZN32AMDRadeonX4000_AMDHWAlignManager17AddrLibDebugPrintEPK22_ADDR_DEBUGPRINT_INPUT 000000000004f90a g 0f SECT 01 0000 [.text] __ZN32AMDRadeonX4000_AMDHWAlignManager17AddrLibFreeSysMemEPK22_ADDR_FREESYSMEM_INPUT 000000000004f8c2 g 0f SECT 01 0000 [.text] __ZN32AMDRadeonX4000_AMDHWAlignManager18AddrLibAllocSysMemEPK23_ADDR_ALLOCSYSMEM_INPUT 000000000004fb6e g 0f SECT 01 0000 [.text] __ZN32AMDRadeonX4000_AMDHWAlignManager20getMipMapSurfaceInfoEP32_ADDR_COMPUTE_SURFACE_INFO_INPUTP33_ADDR_COMPUTE_SURFACE_INFO_OUTPUTjPjP14_ADDR_TILEINFO 000000000004ff98 g 0f SECT 01 0000 [.text] __ZN32AMDRadeonX4000_AMDHWAlignManager22convertSurfaceTileInfoEP14_ADDR_TILEINFOS1_b 000000000004f92c g 0f SECT 01 0000 [.text] __ZN32AMDRadeonX4000_AMDHWAlignManager4freeEv 000000000004f6a2 g 0f SECT 01 0000 [.text] __ZN32AMDRadeonX4000_AMDHWAlignManager4initEP30AMDRadeonX4000_IAMDHWInterface 000000000004f510 g 0f SECT 01 0000 [.text] __ZN32AMDRadeonX4000_AMDHWAlignManager9MetaClassC1Ev 000000000004f5d0 g 0f SECT 01 0000 [.text] __ZN32AMDRadeonX4000_AMDHWAlignManager9MetaClassC2Ev 00000000003a23f0 g 0f SECT 08 0000 [.const_data] __ZN32AMDRadeonX4000_AMDHWAlignManager9metaClassE 000000000004f56c g 0f SECT 01 0000 [.text] __ZN32AMDRadeonX4000_AMDHWAlignManagerC1EPK11OSMetaClass 000000000004f642 g 0f SECT 01 0000 [.text] __ZN32AMDRadeonX4000_AMDHWAlignManagerC1Ev 000000000004f54c g 0f SECT 01 0000 [.text] __ZN32AMDRadeonX4000_AMDHWAlignManagerC2EPK11OSMetaClass 000000000004f672 g 0f SECT 01 0000 [.text] __ZN32AMDRadeonX4000_AMDHWAlignManagerC2Ev 000000000004f5a0 g 0f SECT 01 0000 [.text] __ZN32AMDRadeonX4000_AMDHWAlignManagerD0Ev 000000000004f596 g 0f SECT 01 0000 [.text] __ZN32AMDRadeonX4000_AMDHWAlignManagerD1Ev 000000000004f58c g 0f SECT 01 0000 [.text] __ZN32AMDRadeonX4000_AMDHWAlignManagerD2Ev 000000000052f0c0 g 0f SECT 0a 0000 [__DATA.__common] __ZN32AMDRadeonX4000_AMDSMLSIInterface10gMetaClassE 00000000003c34b8 g 0f SECT 08 0000 [.const_data] __ZN32AMDRadeonX4000_AMDSMLSIInterface10superClassE 0000000000127ef4 g 0f SECT 01 0000 [.text] __ZN32AMDRadeonX4000_AMDSMLSIInterface4freeEv 0000000000127ee2 g 0f SECT 01 0000 [.text] __ZN32AMDRadeonX4000_AMDSMLSIInterface4initEj 0000000000127d50 g 0f SECT 01 0000 [.text] __ZN32AMDRadeonX4000_AMDSMLSIInterface9MetaClassC1Ev 0000000000127e10 g 0f SECT 01 0000 [.text] __ZN32AMDRadeonX4000_AMDSMLSIInterface9MetaClassC2Ev 0000000000127f2e g 0f SECT 01 0000 [.text] __ZN32AMDRadeonX4000_AMDSMLSIInterface9createDRMEv 0000000000127f56 g 0f SECT 01 0000 [.text] __ZN32AMDRadeonX4000_AMDSMLSIInterface9createSPUEv 0000000000127f06 g 0f SECT 01 0000 [.text] __ZN32AMDRadeonX4000_AMDSMLSIInterface9createUVDEv 0000000000127f7e g 0f SECT 01 0000 [.text] __ZN32AMDRadeonX4000_AMDSMLSIInterface9createVCEEv 00000000003c34b0 g 0f SECT 08 0000 [.const_data] __ZN32AMDRadeonX4000_AMDSMLSIInterface9metaClassE 0000000000127dac g 0f SECT 01 0000 [.text] __ZN32AMDRadeonX4000_AMDSMLSIInterfaceC1EPK11OSMetaClass 0000000000127e82 g 0f SECT 01 0000 [.text] __ZN32AMDRadeonX4000_AMDSMLSIInterfaceC1Ev 0000000000127d8c g 0f SECT 01 0000 [.text] __ZN32AMDRadeonX4000_AMDSMLSIInterfaceC2EPK11OSMetaClass 0000000000127eb2 g 0f SECT 01 0000 [.text] __ZN32AMDRadeonX4000_AMDSMLSIInterfaceC2Ev 0000000000127de0 g 0f SECT 01 0000 [.text] __ZN32AMDRadeonX4000_AMDSMLSIInterfaceD0Ev 0000000000127dd6 g 0f SECT 01 0000 [.text] __ZN32AMDRadeonX4000_AMDSMLSIInterfaceD1Ev 0000000000127dcc g 0f SECT 01 0000 [.text] __ZN32AMDRadeonX4000_AMDSMLSIInterfaceD2Ev 000000000052f250 g 0f SECT 0a 0000 [__DATA.__common] __ZN32AMDRadeonX4000_AMDSMLVIInterface10gMetaClassE 00000000003c4f58 g 0f SECT 08 0000 [.const_data] __ZN32AMDRadeonX4000_AMDSMLVIInterface10superClassE 000000000012b604 g 0f SECT 01 0000 [.text] __ZN32AMDRadeonX4000_AMDSMLVIInterface4freeEv 000000000012b5f2 g 0f SECT 01 0000 [.text] __ZN32AMDRadeonX4000_AMDSMLVIInterface4initEj 000000000012b460 g 0f SECT 01 0000 [.text] __ZN32AMDRadeonX4000_AMDSMLVIInterface9MetaClassC1Ev 000000000012b520 g 0f SECT 01 0000 [.text] __ZN32AMDRadeonX4000_AMDSMLVIInterface9MetaClassC2Ev 000000000012b63e g 0f SECT 01 0000 [.text] __ZN32AMDRadeonX4000_AMDSMLVIInterface9createDRMEv 000000000012b666 g 0f SECT 01 0000 [.text] __ZN32AMDRadeonX4000_AMDSMLVIInterface9createSPUEv 000000000012b616 g 0f SECT 01 0000 [.text] __ZN32AMDRadeonX4000_AMDSMLVIInterface9createUVDEv 000000000012b68e g 0f SECT 01 0000 [.text] __ZN32AMDRadeonX4000_AMDSMLVIInterface9createVCEEv 00000000003c4f50 g 0f SECT 08 0000 [.const_data] __ZN32AMDRadeonX4000_AMDSMLVIInterface9metaClassE 000000000012b4bc g 0f SECT 01 0000 [.text] __ZN32AMDRadeonX4000_AMDSMLVIInterfaceC1EPK11OSMetaClass 000000000012b592 g 0f SECT 01 0000 [.text] __ZN32AMDRadeonX4000_AMDSMLVIInterfaceC1Ev 000000000012b49c g 0f SECT 01 0000 [.text] __ZN32AMDRadeonX4000_AMDSMLVIInterfaceC2EPK11OSMetaClass 000000000012b5c2 g 0f SECT 01 0000 [.text] __ZN32AMDRadeonX4000_AMDSMLVIInterfaceC2Ev 000000000012b4f0 g 0f SECT 01 0000 [.text] __ZN32AMDRadeonX4000_AMDSMLVIInterfaceD0Ev 000000000012b4e6 g 0f SECT 01 0000 [.text] __ZN32AMDRadeonX4000_AMDSMLVIInterfaceD1Ev 000000000012b4dc g 0f SECT 01 0000 [.text] __ZN32AMDRadeonX4000_AMDSMLVIInterfaceD2Ev 000000000052cfa8 g 0f SECT 0a 0000 [__DATA.__common] __ZN33AMDRadeonX4000_AMDAccelStatistics10gMetaClassE 000000000038c768 g 0f SECT 08 0000 [.const_data] __ZN33AMDRadeonX4000_AMDAccelStatistics10superClassE 0000000000012764 g 0f SECT 01 0000 [.text] __ZN33AMDRadeonX4000_AMDAccelStatistics18writeInternalStatsEP12OSDictionaryb 000000000001287e g 0f SECT 01 0000 [.text] __ZN33AMDRadeonX4000_AMDAccelStatistics21writePerformanceStatsEP12OSDictionaryb 0000000000012752 g 0f SECT 01 0000 [.text] __ZN33AMDRadeonX4000_AMDAccelStatistics4initEP22IOGraphicsAccelerator2 00000000000125c0 g 0f SECT 01 0000 [.text] __ZN33AMDRadeonX4000_AMDAccelStatistics9MetaClassC1Ev 0000000000012680 g 0f SECT 01 0000 [.text] __ZN33AMDRadeonX4000_AMDAccelStatistics9MetaClassC2Ev 000000000038c760 g 0f SECT 08 0000 [.const_data] __ZN33AMDRadeonX4000_AMDAccelStatistics9metaClassE 000000000001261c g 0f SECT 01 0000 [.text] __ZN33AMDRadeonX4000_AMDAccelStatisticsC1EPK11OSMetaClass 00000000000126f2 g 0f SECT 01 0000 [.text] __ZN33AMDRadeonX4000_AMDAccelStatisticsC1Ev 00000000000125fc g 0f SECT 01 0000 [.text] __ZN33AMDRadeonX4000_AMDAccelStatisticsC2EPK11OSMetaClass 0000000000012722 g 0f SECT 01 0000 [.text] __ZN33AMDRadeonX4000_AMDAccelStatisticsC2Ev 0000000000012650 g 0f SECT 01 0000 [.text] __ZN33AMDRadeonX4000_AMDAccelStatisticsD0Ev 0000000000012646 g 0f SECT 01 0000 [.text] __ZN33AMDRadeonX4000_AMDAccelStatisticsD1Ev 000000000001263c g 0f SECT 01 0000 [.text] __ZN33AMDRadeonX4000_AMDAccelStatisticsD2Ev 000000000052d098 g 0f SECT 0a 0000 [__DATA.__common] __ZN33AMDRadeonX4000_AMDAccelUVDContext10gMetaClassE 000000000038f6a8 g 0f SECT 08 0000 [.const_data] __ZN33AMDRadeonX4000_AMDAccelUVDContext10superClassE 000000000001ab5a g 0f SECT 01 0000 [.text] __ZN33AMDRadeonX4000_AMDAccelUVDContext14saveUVDSessionEv 000000000001ab38 g 0f SECT 01 0000 [.text] __ZN33AMDRadeonX4000_AMDAccelUVDContext17releaseCapabilityEv 000000000001aac8 g 0f SECT 01 0000 [.text] __ZN33AMDRadeonX4000_AMDAccelUVDContext17requestCapabilityEP21sUvdContextReturnInfo 000000000001ab84 g 0f SECT 01 0000 [.text] __ZN33AMDRadeonX4000_AMDAccelUVDContext17restoreUVDSessionEb 000000000001abb4 g 0f SECT 01 0000 [.text] __ZN33AMDRadeonX4000_AMDAccelUVDContext18destroyUVDSSessionEv 000000000001aa0a g 0f SECT 01 0000 [.text] __ZN33AMDRadeonX4000_AMDAccelUVDContext4freeEv 000000000001a8a2 g 0f SECT 01 0000 [.text] __ZN33AMDRadeonX4000_AMDAccelUVDContext4initEP37AMDRadeonX4000_AMDGraphicsAcceleratorP35AMDRadeonX4000_AMDAccelVideoContextP21sUvdContextCreateInfo 000000000001aa86 g 0f SECT 01 0000 [.text] __ZN33AMDRadeonX4000_AMDAccelUVDContext4stopEv 000000000001a710 g 0f SECT 01 0000 [.text] __ZN33AMDRadeonX4000_AMDAccelUVDContext9MetaClassC1Ev 000000000001a7d0 g 0f SECT 01 0000 [.text] __ZN33AMDRadeonX4000_AMDAccelUVDContext9MetaClassC2Ev 000000000038f6a0 g 0f SECT 08 0000 [.const_data] __ZN33AMDRadeonX4000_AMDAccelUVDContext9metaClassE 000000000001a76c g 0f SECT 01 0000 [.text] __ZN33AMDRadeonX4000_AMDAccelUVDContextC1EPK11OSMetaClass 000000000001a842 g 0f SECT 01 0000 [.text] __ZN33AMDRadeonX4000_AMDAccelUVDContextC1Ev 000000000001a74c g 0f SECT 01 0000 [.text] __ZN33AMDRadeonX4000_AMDAccelUVDContextC2EPK11OSMetaClass 000000000001a872 g 0f SECT 01 0000 [.text] __ZN33AMDRadeonX4000_AMDAccelUVDContextC2Ev 000000000001a7a0 g 0f SECT 01 0000 [.text] __ZN33AMDRadeonX4000_AMDAccelUVDContextD0Ev 000000000001a796 g 0f SECT 01 0000 [.text] __ZN33AMDRadeonX4000_AMDAccelUVDContextD1Ev 000000000001a78c g 0f SECT 01 0000 [.text] __ZN33AMDRadeonX4000_AMDAccelUVDContextD2Ev 000000000052d138 g 0f SECT 0a 0000 [__DATA.__common] __ZN33AMDRadeonX4000_AMDAccelVCEContext10gMetaClassE 0000000000390138 g 0f SECT 08 0000 [.const_data] __ZN33AMDRadeonX4000_AMDAccelVCEContext10superClassE 000000000001efcc g 0f SECT 01 0000 [.text] __ZN33AMDRadeonX4000_AMDAccelVCEContext16setEncPropertiesEP22encode_properties_info 000000000001ee88 g 0f SECT 01 0000 [.text] __ZN33AMDRadeonX4000_AMDAccelVCEContext17releaseCapabilityEv 000000000001ee18 g 0f SECT 01 0000 [.text] __ZN33AMDRadeonX4000_AMDAccelVCEContext17requestCapabilityEP21sVceContextReturnInfo 000000000001eeaa g 0f SECT 01 0000 [.text] __ZN33AMDRadeonX4000_AMDAccelVCEContext17restorePowerStateEv 000000000001ed40 g 0f SECT 01 0000 [.text] __ZN33AMDRadeonX4000_AMDAccelVCEContext4freeEv 000000000001eb92 g 0f SECT 01 0000 [.text] __ZN33AMDRadeonX4000_AMDAccelVCEContext4initEP37AMDRadeonX4000_AMDGraphicsAcceleratorP35AMDRadeonX4000_AMDAccelVideoContextP21sVceContextCreateInfo 000000000001edb8 g 0f SECT 01 0000 [.text] __ZN33AMDRadeonX4000_AMDAccelVCEContext4stopEv 000000000001ea00 g 0f SECT 01 0000 [.text] __ZN33AMDRadeonX4000_AMDAccelVCEContext9MetaClassC1Ev 000000000001eac0 g 0f SECT 01 0000 [.text] __ZN33AMDRadeonX4000_AMDAccelVCEContext9MetaClassC2Ev 0000000000390130 g 0f SECT 08 0000 [.const_data] __ZN33AMDRadeonX4000_AMDAccelVCEContext9metaClassE 000000000001ea5c g 0f SECT 01 0000 [.text] __ZN33AMDRadeonX4000_AMDAccelVCEContextC1EPK11OSMetaClass 000000000001eb32 g 0f SECT 01 0000 [.text] __ZN33AMDRadeonX4000_AMDAccelVCEContextC1Ev 000000000001ea3c g 0f SECT 01 0000 [.text] __ZN33AMDRadeonX4000_AMDAccelVCEContextC2EPK11OSMetaClass 000000000001eb62 g 0f SECT 01 0000 [.text] __ZN33AMDRadeonX4000_AMDAccelVCEContextC2Ev 000000000001ea90 g 0f SECT 01 0000 [.text] __ZN33AMDRadeonX4000_AMDAccelVCEContextD0Ev 000000000001ea86 g 0f SECT 01 0000 [.text] __ZN33AMDRadeonX4000_AMDAccelVCEContextD1Ev 000000000001ea7c g 0f SECT 01 0000 [.text] __ZN33AMDRadeonX4000_AMDAccelVCEContextD2Ev 000000000052ddd8 g 0f SECT 0a 0000 [__DATA.__common] __ZN33AMDRadeonX4000_AMDHWSemaphorePool10gMetaClassE 00000000003a74b8 g 0f SECT 08 0000 [.const_data] __ZN33AMDRadeonX4000_AMDHWSemaphorePool10superClassE 0000000000057398 g 0f SECT 01 0000 [.text] __ZN33AMDRadeonX4000_AMDHWSemaphorePool14allocSemaphoreEb 00000000000575e8 g 0f SECT 01 0000 [.text] __ZN33AMDRadeonX4000_AMDHWSemaphorePool14initializePoolEv 0000000000057524 g 0f SECT 01 0000 [.text] __ZN33AMDRadeonX4000_AMDHWSemaphorePool16releaseSemaphoreEP30AMDRadeonX4000_IAMDHWSemaphore 000000000005759c g 0f SECT 01 0000 [.text] __ZN33AMDRadeonX4000_AMDHWSemaphorePool18addSemaphoreToPoolEP30AMDRadeonX4000_IAMDHWSemaphore 0000000000057312 g 0f SECT 01 0000 [.text] __ZN33AMDRadeonX4000_AMDHWSemaphorePool4freeEv 00000000000571b2 g 0f SECT 01 0000 [.text] __ZN33AMDRadeonX4000_AMDHWSemaphorePool4initEP30AMDRadeonX4000_IAMDHWInterface 00000000000576d8 g 0f SECT 01 0000 [.text] __ZN33AMDRadeonX4000_AMDHWSemaphorePool8freePoolEv 0000000000057020 g 0f SECT 01 0000 [.text] __ZN33AMDRadeonX4000_AMDHWSemaphorePool9MetaClassC1Ev 00000000000570e0 g 0f SECT 01 0000 [.text] __ZN33AMDRadeonX4000_AMDHWSemaphorePool9MetaClassC2Ev 00000000003a74b0 g 0f SECT 08 0000 [.const_data] __ZN33AMDRadeonX4000_AMDHWSemaphorePool9metaClassE 000000000005707c g 0f SECT 01 0000 [.text] __ZN33AMDRadeonX4000_AMDHWSemaphorePoolC1EPK11OSMetaClass 0000000000057152 g 0f SECT 01 0000 [.text] __ZN33AMDRadeonX4000_AMDHWSemaphorePoolC1Ev 000000000005705c g 0f SECT 01 0000 [.text] __ZN33AMDRadeonX4000_AMDHWSemaphorePoolC2EPK11OSMetaClass 0000000000057182 g 0f SECT 01 0000 [.text] __ZN33AMDRadeonX4000_AMDHWSemaphorePoolC2Ev 00000000000570b0 g 0f SECT 01 0000 [.text] __ZN33AMDRadeonX4000_AMDHWSemaphorePoolD0Ev 00000000000570a6 g 0f SECT 01 0000 [.text] __ZN33AMDRadeonX4000_AMDHWSemaphorePoolD1Ev 000000000005709c g 0f SECT 01 0000 [.text] __ZN33AMDRadeonX4000_AMDHWSemaphorePoolD2Ev 000000000052ddb0 g 0f SECT 0a 0000 [__DATA.__common] __ZN33AMDRadeonX4000_AMDNullHWSemaphore10gMetaClassE 00000000003a7208 g 0f SECT 08 0000 [.const_data] __ZN33AMDRadeonX4000_AMDNullHWSemaphore10superClassE 0000000000056d90 g 0f SECT 01 0000 [.text] __ZN33AMDRadeonX4000_AMDNullHWSemaphore9MetaClassC1Ev 0000000000056e50 g 0f SECT 01 0000 [.text] __ZN33AMDRadeonX4000_AMDNullHWSemaphore9MetaClassC2Ev 00000000003a7200 g 0f SECT 08 0000 [.const_data] __ZN33AMDRadeonX4000_AMDNullHWSemaphore9metaClassE 0000000000056dec g 0f SECT 01 0000 [.text] __ZN33AMDRadeonX4000_AMDNullHWSemaphoreC1EPK11OSMetaClass 0000000000056ec2 g 0f SECT 01 0000 [.text] __ZN33AMDRadeonX4000_AMDNullHWSemaphoreC1Ev 0000000000056dcc g 0f SECT 01 0000 [.text] __ZN33AMDRadeonX4000_AMDNullHWSemaphoreC2EPK11OSMetaClass 0000000000056ef2 g 0f SECT 01 0000 [.text] __ZN33AMDRadeonX4000_AMDNullHWSemaphoreC2Ev 0000000000056e20 g 0f SECT 01 0000 [.text] __ZN33AMDRadeonX4000_AMDNullHWSemaphoreD0Ev 0000000000056e16 g 0f SECT 01 0000 [.text] __ZN33AMDRadeonX4000_AMDNullHWSemaphoreD1Ev 0000000000056e0c g 0f SECT 01 0000 [.text] __ZN33AMDRadeonX4000_AMDNullHWSemaphoreD2Ev 000000000052f188 g 0f SECT 0a 0000 [__DATA.__common] __ZN33AMDRadeonX4000_AMDSMLCIKInterface10gMetaClassE 00000000003c4228 g 0f SECT 08 0000 [.const_data] __ZN33AMDRadeonX4000_AMDSMLCIKInterface10superClassE 00000000001299a4 g 0f SECT 01 0000 [.text] __ZN33AMDRadeonX4000_AMDSMLCIKInterface4freeEv 0000000000129992 g 0f SECT 01 0000 [.text] __ZN33AMDRadeonX4000_AMDSMLCIKInterface4initEj 0000000000129800 g 0f SECT 01 0000 [.text] __ZN33AMDRadeonX4000_AMDSMLCIKInterface9MetaClassC1Ev 00000000001298c0 g 0f SECT 01 0000 [.text] __ZN33AMDRadeonX4000_AMDSMLCIKInterface9MetaClassC2Ev 00000000001299de g 0f SECT 01 0000 [.text] __ZN33AMDRadeonX4000_AMDSMLCIKInterface9createDRMEv 0000000000129a06 g 0f SECT 01 0000 [.text] __ZN33AMDRadeonX4000_AMDSMLCIKInterface9createSPUEv 00000000001299b6 g 0f SECT 01 0000 [.text] __ZN33AMDRadeonX4000_AMDSMLCIKInterface9createUVDEv 0000000000129a2e g 0f SECT 01 0000 [.text] __ZN33AMDRadeonX4000_AMDSMLCIKInterface9createVCEEv 00000000003c4220 g 0f SECT 08 0000 [.const_data] __ZN33AMDRadeonX4000_AMDSMLCIKInterface9metaClassE 000000000012985c g 0f SECT 01 0000 [.text] __ZN33AMDRadeonX4000_AMDSMLCIKInterfaceC1EPK11OSMetaClass 0000000000129932 g 0f SECT 01 0000 [.text] __ZN33AMDRadeonX4000_AMDSMLCIKInterfaceC1Ev 000000000012983c g 0f SECT 01 0000 [.text] __ZN33AMDRadeonX4000_AMDSMLCIKInterfaceC2EPK11OSMetaClass 0000000000129962 g 0f SECT 01 0000 [.text] __ZN33AMDRadeonX4000_AMDSMLCIKInterfaceC2Ev 0000000000129890 g 0f SECT 01 0000 [.text] __ZN33AMDRadeonX4000_AMDSMLCIKInterfaceD0Ev 0000000000129886 g 0f SECT 01 0000 [.text] __ZN33AMDRadeonX4000_AMDSMLCIKInterfaceD1Ev 000000000012987c g 0f SECT 01 0000 [.text] __ZN33AMDRadeonX4000_AMDSMLCIKInterfaceD2Ev 000000000052dae0 g 0f SECT 0a 0000 [__DATA.__common] __ZN33AMDRadeonX4000_IAMDHWAlignManager10gMetaClassE 00000000003a3fe0 g 0f SECT 08 0000 [.const_data] __ZN33AMDRadeonX4000_IAMDHWAlignManager10superClassE 00000000000527ee g 0f SECT 01 0000 [.text] __ZN33AMDRadeonX4000_IAMDHWAlignManager9MetaClassC1Ev 000000000005288e g 0f SECT 01 0000 [.text] __ZN33AMDRadeonX4000_IAMDHWAlignManager9MetaClassC2Ev 00000000003a3fd8 g 0f SECT 08 0000 [.const_data] __ZN33AMDRadeonX4000_IAMDHWAlignManager9metaClassE 000000000005282a g 0f SECT 01 0000 [.text] __ZN33AMDRadeonX4000_IAMDHWAlignManagerC2EPK11OSMetaClass 000000000005285e g 0f SECT 01 0000 [.text] __ZN33AMDRadeonX4000_IAMDHWAlignManagerD0Ev 0000000000052854 g 0f SECT 01 0000 [.text] __ZN33AMDRadeonX4000_IAMDHWAlignManagerD1Ev 000000000005284a g 0f SECT 01 0000 [.text] __ZN33AMDRadeonX4000_IAMDHWAlignManagerD2Ev 000000000052efa8 g 0f SECT 0a 0000 [__DATA.__common] __ZN34AMDRadeonX4000_AMDHDCPGetStatusMsg10gMetaClassE 00000000003c22c0 g 0f SECT 08 0000 [.const_data] __ZN34AMDRadeonX4000_AMDHDCPGetStatusMsg10superClassE 000000000012685a g 0f SECT 01 0000 [.text] __ZN34AMDRadeonX4000_AMDHDCPGetStatusMsg12setOutBufferEiyPh 0000000000126848 g 0f SECT 01 0000 [.text] __ZN34AMDRadeonX4000_AMDHDCPGetStatusMsg4freeEv 000000000012673a g 0f SECT 01 0000 [.text] __ZN34AMDRadeonX4000_AMDHDCPGetStatusMsg4initEPv 00000000001265a8 g 0f SECT 01 0000 [.text] __ZN34AMDRadeonX4000_AMDHDCPGetStatusMsg9MetaClassC1Ev 0000000000126668 g 0f SECT 01 0000 [.text] __ZN34AMDRadeonX4000_AMDHDCPGetStatusMsg9MetaClassC2Ev 000000000012688a g 0f SECT 01 0000 [.text] __ZN34AMDRadeonX4000_AMDHDCPGetStatusMsg9getOutputEv 00000000003c22b8 g 0f SECT 08 0000 [.const_data] __ZN34AMDRadeonX4000_AMDHDCPGetStatusMsg9metaClassE 0000000000126604 g 0f SECT 01 0000 [.text] __ZN34AMDRadeonX4000_AMDHDCPGetStatusMsgC1EPK11OSMetaClass 00000000001266da g 0f SECT 01 0000 [.text] __ZN34AMDRadeonX4000_AMDHDCPGetStatusMsgC1Ev 00000000001265e4 g 0f SECT 01 0000 [.text] __ZN34AMDRadeonX4000_AMDHDCPGetStatusMsgC2EPK11OSMetaClass 000000000012670a g 0f SECT 01 0000 [.text] __ZN34AMDRadeonX4000_AMDHDCPGetStatusMsgC2Ev 0000000000126638 g 0f SECT 01 0000 [.text] __ZN34AMDRadeonX4000_AMDHDCPGetStatusMsgD0Ev 000000000012662e g 0f SECT 01 0000 [.text] __ZN34AMDRadeonX4000_AMDHDCPGetStatusMsgD1Ev 0000000000126624 g 0f SECT 01 0000 [.text] __ZN34AMDRadeonX4000_AMDHDCPGetStatusMsgD2Ev 000000000052dbd0 g 0f SECT 0a 0000 [__DATA.__common] __ZN34AMDRadeonX4000_IAMDHWSemaphorePool10gMetaClassE 00000000003a5080 g 0f SECT 08 0000 [.const_data] __ZN34AMDRadeonX4000_IAMDHWSemaphorePool10superClassE 0000000000052d0a g 0f SECT 01 0000 [.text] __ZN34AMDRadeonX4000_IAMDHWSemaphorePool9MetaClassC1Ev 0000000000052daa g 0f SECT 01 0000 [.text] __ZN34AMDRadeonX4000_IAMDHWSemaphorePool9MetaClassC2Ev 00000000003a5078 g 0f SECT 08 0000 [.const_data] __ZN34AMDRadeonX4000_IAMDHWSemaphorePool9metaClassE 0000000000052d46 g 0f SECT 01 0000 [.text] __ZN34AMDRadeonX4000_IAMDHWSemaphorePoolC2EPK11OSMetaClass 0000000000052d7a g 0f SECT 01 0000 [.text] __ZN34AMDRadeonX4000_IAMDHWSemaphorePoolD0Ev 0000000000052d70 g 0f SECT 01 0000 [.text] __ZN34AMDRadeonX4000_IAMDHWSemaphorePoolD1Ev 0000000000052d66 g 0f SECT 01 0000 [.text] __ZN34AMDRadeonX4000_IAMDHWSemaphorePoolD2Ev 000000000052d400 g 0f SECT 0a 0000 [__DATA.__common] __ZN34AMDRadeonX4000_IAMDStatisticsGroup10gMetaClassE 00000000003918c8 g 0f SECT 08 0000 [.const_data] __ZN34AMDRadeonX4000_IAMDStatisticsGroup10superClassE 0000000000025cf0 g 0f SECT 01 0000 [.text] __ZN34AMDRadeonX4000_IAMDStatisticsGroup9MetaClassC1Ev 0000000000025d90 g 0f SECT 01 0000 [.text] __ZN34AMDRadeonX4000_IAMDStatisticsGroup9MetaClassC2Ev 00000000003918c0 g 0f SECT 08 0000 [.const_data] __ZN34AMDRadeonX4000_IAMDStatisticsGroup9metaClassE 0000000000025d2c g 0f SECT 01 0000 [.text] __ZN34AMDRadeonX4000_IAMDStatisticsGroupC2EPK11OSMetaClass 0000000000025d60 g 0f SECT 01 0000 [.text] __ZN34AMDRadeonX4000_IAMDStatisticsGroupD0Ev 0000000000025d56 g 0f SECT 01 0000 [.text] __ZN34AMDRadeonX4000_IAMDStatisticsGroupD1Ev 0000000000025d4c g 0f SECT 01 0000 [.text] __ZN34AMDRadeonX4000_IAMDStatisticsGroupD2Ev 000000000052cf08 g 0f SECT 0a 0000 [__DATA.__common] __ZN35AMDRadeonX4000_AMDAccelEventMachine10gMetaClassE 000000000038b228 g 0f SECT 08 0000 [.const_data] __ZN35AMDRadeonX4000_AMDAccelEventMachine10superClassE 0000000000009c4a g 0f SECT 01 0000 [.text] __ZN35AMDRadeonX4000_AMDAccelEventMachine10writeStampEiP17vendevtCommandRecj 000000000000986e g 0f SECT 01 0000 [.text] __ZN35AMDRadeonX4000_AMDAccelEventMachine11finishEventEP12IOAccelEvent 000000000000973a g 0f SECT 01 0000 [.text] __ZN35AMDRadeonX4000_AMDAccelEventMachine11finishStampEi 0000000000009c8c g 0f SECT 01 0000 [.text] __ZN35AMDRadeonX4000_AMDAccelEventMachine12eventTimeoutEi 00000000000099a0 g 0f SECT 01 0000 [.text] __ZN35AMDRadeonX4000_AMDAccelEventMachine12waitForStampEijPj 0000000000009710 g 0f SECT 01 0000 [.text] __ZN35AMDRadeonX4000_AMDAccelEventMachine14getStampOffsetEi 0000000000009c58 g 0f SECT 01 0000 [.text] __ZN35AMDRadeonX4000_AMDAccelEventMachine14prepareBarrierEP17vendevtBarrierRec 0000000000009c66 g 0f SECT 01 0000 [.text] __ZN35AMDRadeonX4000_AMDAccelEventMachine15completeBarrierEP17vendevtBarrierRec 000000000000974c g 0f SECT 01 0000 [.text] __ZN35AMDRadeonX4000_AMDAccelEventMachine15finishAllStampsEv 0000000000009fb2 g 0f SECT 01 0000 [.text] __ZN35AMDRadeonX4000_AMDAccelEventMachine18setupWritebackSyncEiPj 00000000000097d8 g 0f SECT 01 0000 [.text] __ZN35AMDRadeonX4000_AMDAccelEventMachine19finishEventUnlockedEP12IOAccelEvent 0000000000009c72 g 0f SECT 01 0000 [.text] __ZN35AMDRadeonX4000_AMDAccelEventMachine19writeBarrierElementEP17vendevtBarrierRecij 0000000000009904 g 0f SECT 01 0000 [.text] __ZN35AMDRadeonX4000_AMDAccelEventMachine20finishEventExcludingEP12IOAccelEventi 000000000000a01e g 0f SECT 01 0000 [.text] __ZN35AMDRadeonX4000_AMDAccelEventMachine21isEventEmptyExcludingEPK12IOAccelEventi 00000000000096b4 g 0f SECT 01 0000 [.text] __ZN35AMDRadeonX4000_AMDAccelEventMachine4freeEv 0000000000009622 g 0f SECT 01 0000 [.text] __ZN35AMDRadeonX4000_AMDAccelEventMachine4initEP22IOGraphicsAccelerator2ji 0000000000009490 g 0f SECT 01 0000 [.text] __ZN35AMDRadeonX4000_AMDAccelEventMachine9MetaClassC1Ev 0000000000009550 g 0f SECT 01 0000 [.text] __ZN35AMDRadeonX4000_AMDAccelEventMachine9MetaClassC2Ev 000000000038b220 g 0f SECT 08 0000 [.const_data] __ZN35AMDRadeonX4000_AMDAccelEventMachine9metaClassE 00000000000094ec g 0f SECT 01 0000 [.text] __ZN35AMDRadeonX4000_AMDAccelEventMachineC1EPK11OSMetaClass 00000000000095c2 g 0f SECT 01 0000 [.text] __ZN35AMDRadeonX4000_AMDAccelEventMachineC1Ev 00000000000094cc g 0f SECT 01 0000 [.text] __ZN35AMDRadeonX4000_AMDAccelEventMachineC2EPK11OSMetaClass 00000000000095f2 g 0f SECT 01 0000 [.text] __ZN35AMDRadeonX4000_AMDAccelEventMachineC2Ev 0000000000009520 g 0f SECT 01 0000 [.text] __ZN35AMDRadeonX4000_AMDAccelEventMachineD0Ev 0000000000009516 g 0f SECT 01 0000 [.text] __ZN35AMDRadeonX4000_AMDAccelEventMachineD1Ev 000000000000950c g 0f SECT 01 0000 [.text] __ZN35AMDRadeonX4000_AMDAccelEventMachineD2Ev 000000000052d070 g 0f SECT 0a 0000 [__DATA.__common] __ZN35AMDRadeonX4000_AMDAccelVideoContext10gMetaClassE 0000000000016fd0 g 0f SECT 01 0000 [.text] __ZN35AMDRadeonX4000_AMDAccelVideoContext10setChannelER24IOAccelCommandStreamInfo 000000000038e658 g 0f SECT 08 0000 [.const_data] __ZN35AMDRadeonX4000_AMDAccelVideoContext10superClassE 0000000000019364 g 0f SECT 01 0000 [.text] __ZN35AMDRadeonX4000_AMDAccelVideoContext11contextStopEv 0000000000019aa8 g 0f SECT 01 0000 [.text] __ZN35AMDRadeonX4000_AMDAccelVideoContext12bindResourceER24IOAccelCommandStreamInfoP16IOAccelResource2bP15IOAccelChannel2j 0000000000017f76 g 0f SECT 01 0000 [.text] __ZN35AMDRadeonX4000_AMDAccelVideoContext12contextStartEv 00000000000190ca g 0f SECT 01 0000 [.text] __ZN35AMDRadeonX4000_AMDAccelVideoContext12getVCEPSInfoEPvS0_yPy 0000000000018884 g 0f SECT 01 0000 [.text] __ZN35AMDRadeonX4000_AMDAccelVideoContext12submitSPUMsgEP19sAMDSPUContextMsgInP20sAMDSPUContextMsgOutyPy 000000000001a3fa g 0f SECT 01 0000 [.text] __ZN35AMDRadeonX4000_AMDAccelVideoContext13enableContextEv 0000000000019d86 g 0f SECT 01 0000 [.text] __ZN35AMDRadeonX4000_AMDAccelVideoContext13fetchResourceEP22_AMDVideoResourceParamP21_AMDVideoResourceInfo 00000000000182a8 g 0f SECT 01 0000 [.text] __ZN35AMDRadeonX4000_AMDAccelVideoContext13newUVDContextEP21sUvdContextCreateInfoP21sUvdContextReturnInfoyPy 0000000000018d4c g 0f SECT 01 0000 [.text] __ZN35AMDRadeonX4000_AMDAccelVideoContext13newVCEContextEP21sVceContextCreateInfoP21sVceContextReturnInfoyPy 000000000001a294 g 0f SECT 01 0000 [.text] __ZN35AMDRadeonX4000_AMDAccelVideoContext13sendPMCommandEPvS0_yPy 000000000001a49c g 0f SECT 01 0000 [.text] __ZN35AMDRadeonX4000_AMDAccelVideoContext14disableContextEv 0000000000019b50 g 0f SECT 01 0000 [.text] __ZN35AMDRadeonX4000_AMDAccelVideoContext14processCommandER24IOAccelCommandStreamInfoPj 000000000001914c g 0f SECT 01 0000 [.text] __ZN35AMDRadeonX4000_AMDAccelVideoContext14setEncCroppingEP13cropping_infoy 000000000001852a g 0f SECT 01 0000 [.text] __ZN35AMDRadeonX4000_AMDAccelVideoContext14startUVDEngineEj 0000000000018fd8 g 0f SECT 01 0000 [.text] __ZN35AMDRadeonX4000_AMDAccelVideoContext14startVCEEngineEv 0000000000019abe g 0f SECT 01 0000 [.text] __ZN35AMDRadeonX4000_AMDAccelVideoContext14unbindResourceER24IOAccelCommandStreamInfoP16IOAccelResource2P15IOAccelChannel2 000000000001a62c g 0f SECT 01 0000 [.text] __ZN35AMDRadeonX4000_AMDAccelVideoContext15find_uvd_for_idEj 0000000000019f30 g 0f SECT 01 0000 [.text] __ZN35AMDRadeonX4000_AMDAccelVideoContext15find_vce_for_idEj 000000000001a302 g 0f SECT 01 0000 [.text] __ZN35AMDRadeonX4000_AMDAccelVideoContext15notifyPMContextEjjj 00000000000186be g 0f SECT 01 0000 [.text] __ZN35AMDRadeonX4000_AMDAccelVideoContext16createSPUSessionEv 00000000000197d8 g 0f SECT 01 0000 [.text] __ZN35AMDRadeonX4000_AMDAccelVideoContext16endCommandStreamER24IOAccelCommandStreamInfo 000000000001a21c g 0f SECT 01 0000 [.text] __ZN35AMDRadeonX4000_AMDAccelVideoContext16getUVDCapabilityEP17sAMDUVDCapabilityPy 000000000001a258 g 0f SECT 01 0000 [.text] __ZN35AMDRadeonX4000_AMDAccelVideoContext16getVCECapabilityEP17sAMDVCECapabilityPy 00000000000183c0 g 0f SECT 01 0000 [.text] __ZN35AMDRadeonX4000_AMDAccelVideoContext16removeUVDContextEj 0000000000018e88 g 0f SECT 01 0000 [.text] __ZN35AMDRadeonX4000_AMDAccelVideoContext16removeVCEContextEj 0000000000019190 g 0f SECT 01 0000 [.text] __ZN35AMDRadeonX4000_AMDAccelVideoContext16setEncPropertiesEP22encode_properties_infoy 00000000000187a4 g 0f SECT 01 0000 [.text] __ZN35AMDRadeonX4000_AMDAccelVideoContext17destroySPUSessionEv 000000000001702c g 0f SECT 01 0000 [.text] __ZN35AMDRadeonX4000_AMDAccelVideoContext17processUVDCommandER24IOAccelCommandStreamInfo 0000000000017130 g 0f SECT 01 0000 [.text] __ZN35AMDRadeonX4000_AMDAccelVideoContext17processVCECommandER24IOAccelCommandStreamInfo 0000000000019756 g 0f SECT 01 0000 [.text] __ZN35AMDRadeonX4000_AMDAccelVideoContext18beginCommandStreamER24IOAccelCommandStreamInfo 000000000001a524 g 0f SECT 01 0000 [.text] __ZN35AMDRadeonX4000_AMDAccelVideoContext19clientMemoryForTypeEjPjPP18IOMemoryDescriptor 00000000000196a8 g 0f SECT 01 0000 [.text] __ZN35AMDRadeonX4000_AMDAccelVideoContext19getDataBufferLimitsEv 000000000001a204 g 0f SECT 01 0000 [.text] __ZN35AMDRadeonX4000_AMDAccelVideoContext19getIOSurfaceAccelIdEP21sIOSurfaceAccelIdInfo 0000000000018690 g 0f SECT 01 0000 [.text] __ZN35AMDRadeonX4000_AMDAccelVideoContext20getUVDBandwidthLimitEP21sAMDUVDBandwidthLimit 00000000000199d8 g 0f SECT 01 0000 [.text] __ZN35AMDRadeonX4000_AMDAccelVideoContext20processSidebandTokenER24IOAccelCommandStreamInfo 000000000001863a g 0f SECT 01 0000 [.text] __ZN35AMDRadeonX4000_AMDAccelVideoContext20setUVDBandwidthLimitEP21sAMDUVDBandwidthLimity 0000000000019638 g 0f SECT 01 0000 [.text] __ZN35AMDRadeonX4000_AMDAccelVideoContext21populateContextConfigEP20IOAccelContextConfig 000000000001a3c4 g 0f SECT 01 0000 [.text] __ZN35AMDRadeonX4000_AMDAccelVideoContext21setSuspendResumeStateEb 000000000038e610 g 0f SECT 08 0000 [.const_data] __ZN35AMDRadeonX4000_AMDAccelVideoContext21token_process_methodsE 0000000000019ad0 g 0f SECT 01 0000 [.text] __ZN35AMDRadeonX4000_AMDAccelVideoContext22addDataBufferToChannelEP16IOAccelResource2j 0000000000017598 g 0f SECT 01 0000 [.text] __ZN35AMDRadeonX4000_AMDAccelVideoContext22processGraphicsCommandER24IOAccelCommandStreamInfo 0000000000018246 g 0f SECT 01 0000 [.text] __ZN35AMDRadeonX4000_AMDAccelVideoContext22setMaxPerformanceLevelEj 00000000000185dc g 0f SECT 01 0000 [.text] __ZN35AMDRadeonX4000_AMDAccelVideoContext24setHighPerformanceDecodeEj 000000000001965c g 0f SECT 01 0000 [.text] __ZN35AMDRadeonX4000_AMDAccelVideoContext26getTargetAndMethodForIndexEPP9IOServicej 0000000000019b16 g 0f SECT 01 0000 [.text] __ZN35AMDRadeonX4000_AMDAccelVideoContext27removeDataBufferFromChannelEP16IOAccelResource2j 00000000000191c0 g 0f SECT 01 0000 [.text] __ZN35AMDRadeonX4000_AMDAccelVideoContext8startTPTEP16sDTCParametersInP17sDTCParametersOutyPy 0000000000017e7c g 0f SECT 01 0000 [.text] __ZN35AMDRadeonX4000_AMDAccelVideoContext9MetaClassC1Ev 0000000000017f3c g 0f SECT 01 0000 [.text] __ZN35AMDRadeonX4000_AMDAccelVideoContext9MetaClassC2Ev 0000000000019f5a g 0f SECT 01 0000 [.text] __ZN35AMDRadeonX4000_AMDAccelVideoContext9getHWInfoEP13sHardwareInfo 000000000038e650 g 0f SECT 08 0000 [.const_data] __ZN35AMDRadeonX4000_AMDAccelVideoContext9metaClassE 000000000001a130 g 0f SECT 01 0000 [.text] __ZN35AMDRadeonX4000_AMDAccelVideoContext9setClocksEP14set_clock_infoy 0000000000017ed8 g 0f SECT 01 0000 [.text] __ZN35AMDRadeonX4000_AMDAccelVideoContextC1EPK11OSMetaClass 0000000000017eb8 g 0f SECT 01 0000 [.text] __ZN35AMDRadeonX4000_AMDAccelVideoContextC2EPK11OSMetaClass 0000000000017f0c g 0f SECT 01 0000 [.text] __ZN35AMDRadeonX4000_AMDAccelVideoContextD0Ev 0000000000017f02 g 0f SECT 01 0000 [.text] __ZN35AMDRadeonX4000_AMDAccelVideoContextD1Ev 0000000000017ef8 g 0f SECT 01 0000 [.text] __ZN35AMDRadeonX4000_AMDAccelVideoContextD2Ev 0000000000022732 g 0f SECT 01 0000 [.text] __ZN35AMDRadeonX4000_AMDAtomicBlitManager10doCompressEP17_UBM_COMPRESSINFOPK11ABM_OPTIONS 000000000052d1b0 g 0f SECT 0a 0000 [__DATA.__common] __ZN35AMDRadeonX4000_AMDAtomicBlitManager10gMetaClassE 0000000000390830 g 0f SECT 08 0000 [.const_data] __ZN35AMDRadeonX4000_AMDAtomicBlitManager10superClassE 0000000000021ffa g 0f SECT 01 0000 [.text] __ZN35AMDRadeonX4000_AMDAtomicBlitManager11doAAResolveEP18_UBM_AARESOLVEINFOPK11ABM_OPTIONS 0000000000022f12 g 0f SECT 01 0000 [.text] __ZN35AMDRadeonX4000_AMDAtomicBlitManager12SubmitBufferERNS_17CommandBufferInfoEPK11ABM_OPTIONS 0000000000022c1a g 0f SECT 01 0000 [.text] __ZN35AMDRadeonX4000_AMDAtomicBlitManager13doSurfaceCopyEP20_UBM_SURFACECOPYINFOPK11ABM_OPTIONS 0000000000021c9a g 0f SECT 01 0000 [.text] __ZN35AMDRadeonX4000_AMDAtomicBlitManager13preBlitUpdateEPK11ABM_OPTIONSP30AMDRadeonX4000_AMDAccelChannel 0000000000021d6a g 0f SECT 01 0000 [.text] __ZN35AMDRadeonX4000_AMDAtomicBlitManager14postBlitUpdateEPK11ABM_OPTIONSP30AMDRadeonX4000_AMDAccelChannel 0000000000022db2 g 0f SECT 01 0000 [.text] __ZN35AMDRadeonX4000_AMDAtomicBlitManager16GetCommandBufferERNS_17CommandBufferInfoE11_UBM_ENGINEPK11ABM_OPTIONS 0000000000022172 g 0f SECT 01 0000 [.text] __ZN35AMDRadeonX4000_AMDAtomicBlitManager24doWaitForVLineAndStretchEP16_UBM_STRETCHINFOPK11ABM_OPTIONSPK30AMDRadeonX4000_AMDAccelSurfaceRK26_AMDSurfaceSwapSyncOptions 0000000000021c4c g 0f SECT 01 0000 [.text] __ZN35AMDRadeonX4000_AMDAtomicBlitManager4freeEv 0000000000021b44 g 0f SECT 01 0000 [.text] __ZN35AMDRadeonX4000_AMDAtomicBlitManager4initEP37AMDRadeonX4000_AMDGraphicsAccelerator 0000000000021e82 g 0f SECT 01 0000 [.text] __ZN35AMDRadeonX4000_AMDAtomicBlitManager7doClearEP14_UBM_CLEARINFOPK11ABM_OPTIONS 00000000000225ba g 0f SECT 01 0000 [.text] __ZN35AMDRadeonX4000_AMDAtomicBlitManager8doExpandEP15_UBM_EXPANDINFOPK11ABM_OPTIONS 0000000000022a40 g 0f SECT 01 0000 [.text] __ZN35AMDRadeonX4000_AMDAtomicBlitManager8doMemcpyEP15_UBM_MEMCPYINFOPK11ABM_OPTIONS 00000000000228aa g 0f SECT 01 0000 [.text] __ZN35AMDRadeonX4000_AMDAtomicBlitManager8doMemsetEP15_UBM_MEMSETINFOPK11ABM_OPTIONS 0000000000021a6a g 0f SECT 01 0000 [.text] __ZN35AMDRadeonX4000_AMDAtomicBlitManager9MetaClassC1Ev 0000000000021b0a g 0f SECT 01 0000 [.text] __ZN35AMDRadeonX4000_AMDAtomicBlitManager9MetaClassC2Ev 000000000002231e g 0f SECT 01 0000 [.text] __ZN35AMDRadeonX4000_AMDAtomicBlitManager9doStretchEP16_UBM_STRETCHINFOPK11ABM_OPTIONS 0000000000390828 g 0f SECT 08 0000 [.const_data] __ZN35AMDRadeonX4000_AMDAtomicBlitManager9metaClassE 0000000000021aa6 g 0f SECT 01 0000 [.text] __ZN35AMDRadeonX4000_AMDAtomicBlitManagerC2EPK11OSMetaClass 0000000000021ada g 0f SECT 01 0000 [.text] __ZN35AMDRadeonX4000_AMDAtomicBlitManagerD0Ev 0000000000021ad0 g 0f SECT 01 0000 [.text] __ZN35AMDRadeonX4000_AMDAtomicBlitManagerD1Ev 0000000000021ac6 g 0f SECT 01 0000 [.text] __ZN35AMDRadeonX4000_AMDAtomicBlitManagerD2Ev 000000000052de00 g 0f SECT 0a 0000 [__DATA.__common] __ZN35AMDRadeonX4000_AMDHWSemaphoreMemMgr10gMetaClassE 00000000003a7728 g 0f SECT 08 0000 [.const_data] __ZN35AMDRadeonX4000_AMDHWSemaphoreMemMgr10superClassE 0000000000057c40 g 0f SECT 01 0000 [.text] __ZN35AMDRadeonX4000_AMDHWSemaphoreMemMgr17getVirtualAddressEy 0000000000057c10 g 0f SECT 01 0000 [.text] __ZN35AMDRadeonX4000_AMDHWSemaphoreMemMgr20releaseSemaphoreDataEy 0000000000057bc4 g 0f SECT 01 0000 [.text] __ZN35AMDRadeonX4000_AMDHWSemaphoreMemMgr21allocateSemaphoreDataEPPyS0_ 0000000000057b30 g 0f SECT 01 0000 [.text] __ZN35AMDRadeonX4000_AMDHWSemaphoreMemMgr4freeEv 0000000000057962 g 0f SECT 01 0000 [.text] __ZN35AMDRadeonX4000_AMDHWSemaphoreMemMgr4initEP30AMDRadeonX4000_IAMDHWInterfacej 00000000000577d0 g 0f SECT 01 0000 [.text] __ZN35AMDRadeonX4000_AMDHWSemaphoreMemMgr9MetaClassC1Ev 0000000000057890 g 0f SECT 01 0000 [.text] __ZN35AMDRadeonX4000_AMDHWSemaphoreMemMgr9MetaClassC2Ev 00000000003a7720 g 0f SECT 08 0000 [.const_data] __ZN35AMDRadeonX4000_AMDHWSemaphoreMemMgr9metaClassE 000000000005782c g 0f SECT 01 0000 [.text] __ZN35AMDRadeonX4000_AMDHWSemaphoreMemMgrC1EPK11OSMetaClass 0000000000057902 g 0f SECT 01 0000 [.text] __ZN35AMDRadeonX4000_AMDHWSemaphoreMemMgrC1Ev 000000000005780c g 0f SECT 01 0000 [.text] __ZN35AMDRadeonX4000_AMDHWSemaphoreMemMgrC2EPK11OSMetaClass 0000000000057932 g 0f SECT 01 0000 [.text] __ZN35AMDRadeonX4000_AMDHWSemaphoreMemMgrC2Ev 0000000000057860 g 0f SECT 01 0000 [.text] __ZN35AMDRadeonX4000_AMDHWSemaphoreMemMgrD0Ev 0000000000057856 g 0f SECT 01 0000 [.text] __ZN35AMDRadeonX4000_AMDHWSemaphoreMemMgrD1Ev 000000000005784c g 0f SECT 01 0000 [.text] __ZN35AMDRadeonX4000_AMDHWSemaphoreMemMgrD2Ev 000000000052ef58 g 0f SECT 0a 0000 [__DATA.__common] __ZN36AMDRadeonX4000_AMDHDCPOpenSessionMsg10gMetaClassE 00000000003c1da8 g 0f SECT 08 0000 [.const_data] __ZN36AMDRadeonX4000_AMDHDCPOpenSessionMsg10superClassE 00000000001262ea g 0f SECT 01 0000 [.text] __ZN36AMDRadeonX4000_AMDHDCPOpenSessionMsg12setOutBufferEiyPh 00000000001262d8 g 0f SECT 01 0000 [.text] __ZN36AMDRadeonX4000_AMDHDCPOpenSessionMsg4freeEv 0000000000126212 g 0f SECT 01 0000 [.text] __ZN36AMDRadeonX4000_AMDHDCPOpenSessionMsg4initEPv 0000000000126080 g 0f SECT 01 0000 [.text] __ZN36AMDRadeonX4000_AMDHDCPOpenSessionMsg9MetaClassC1Ev 0000000000126140 g 0f SECT 01 0000 [.text] __ZN36AMDRadeonX4000_AMDHDCPOpenSessionMsg9MetaClassC2Ev 000000000012630e g 0f SECT 01 0000 [.text] __ZN36AMDRadeonX4000_AMDHDCPOpenSessionMsg9getOutputEv 00000000003c1da0 g 0f SECT 08 0000 [.const_data] __ZN36AMDRadeonX4000_AMDHDCPOpenSessionMsg9metaClassE 00000000001260dc g 0f SECT 01 0000 [.text] __ZN36AMDRadeonX4000_AMDHDCPOpenSessionMsgC1EPK11OSMetaClass 00000000001261b2 g 0f SECT 01 0000 [.text] __ZN36AMDRadeonX4000_AMDHDCPOpenSessionMsgC1Ev 00000000001260bc g 0f SECT 01 0000 [.text] __ZN36AMDRadeonX4000_AMDHDCPOpenSessionMsgC2EPK11OSMetaClass 00000000001261e2 g 0f SECT 01 0000 [.text] __ZN36AMDRadeonX4000_AMDHDCPOpenSessionMsgC2Ev 0000000000126110 g 0f SECT 01 0000 [.text] __ZN36AMDRadeonX4000_AMDHDCPOpenSessionMsgD0Ev 0000000000126106 g 0f SECT 01 0000 [.text] __ZN36AMDRadeonX4000_AMDHDCPOpenSessionMsgD1Ev 00000000001260fc g 0f SECT 01 0000 [.text] __ZN36AMDRadeonX4000_AMDHDCPOpenSessionMsgD2Ev 000000000052dec8 g 0f SECT 0a 0000 [__DATA.__common] __ZN36AMDRadeonX4000_AMDPM4CommandsUtility10gMetaClassE 00000000003a88f8 g 0f SECT 08 0000 [.const_data] __ZN36AMDRadeonX4000_AMDPM4CommandsUtility10superClassE 000000000005e166 g 0f SECT 01 0000 [.text] __ZN36AMDRadeonX4000_AMDPM4CommandsUtility16buildPM4Type0CmdEPjjj 000000000005e3a8 g 0f SECT 01 0000 [.text] __ZN36AMDRadeonX4000_AMDPM4CommandsUtility19buildSetDataCommandEPjjjjjj 000000000005e56e g 0f SECT 01 0000 [.text] __ZN36AMDRadeonX4000_AMDPM4CommandsUtility20buildMemWriteCommandEPjyjj 000000000005e502 g 0f SECT 01 0000 [.text] __ZN36AMDRadeonX4000_AMDPM4CommandsUtility20buildPerFrameCommandEPjjjjj 000000000005e762 g 0f SECT 01 0000 [.text] __ZN36AMDRadeonX4000_AMDPM4CommandsUtility21buildPFPSyncMECommandEPj 000000000005e5dc g 0f SECT 01 0000 [.text] __ZN36AMDRadeonX4000_AMDPM4CommandsUtility21buildWriteDataCommandEPjyjjjjPKjjj 000000000005e28e g 0f SECT 01 0000 [.text] __ZN36AMDRadeonX4000_AMDPM4CommandsUtility22buildEventWriteCommandEPjjj 000000000005e3d0 g 0f SECT 01 0000 [.text] __ZN36AMDRadeonX4000_AMDPM4CommandsUtility22buildWaitRegMemCommandEPjjjjjjjj 000000000005e176 g 0f SECT 01 0000 [.text] __ZN36AMDRadeonX4000_AMDPM4CommandsUtility22writePM4Type0CmdToRingEP25AMDRadeonX4000_IAMDHWRingjj 000000000005e1aa g 0f SECT 01 0000 [.text] __ZN36AMDRadeonX4000_AMDPM4CommandsUtility23buildSurfaceSyncCommandEPjjj 000000000005e2e2 g 0f SECT 01 0000 [.text] __ZN36AMDRadeonX4000_AMDPM4CommandsUtility25buildEventWriteEOPCommandEPjjyyjbjj 000000000005e458 g 0f SECT 01 0000 [.text] __ZN36AMDRadeonX4000_AMDPM4CommandsUtility26buildIndirectBufferCommandEPjyj26_eAMD_INDIRECT_BUFFER_TYPEjbj 000000000005e6a6 g 0f SECT 01 0000 [.text] __ZN36AMDRadeonX4000_AMDPM4CommandsUtility27writeWriteDataCommandToRingEP25AMDRadeonX4000_IAMDHWRingyjjjjPKjjj 000000000005e218 g 0f SECT 01 0000 [.text] __ZN36AMDRadeonX4000_AMDPM4CommandsUtility29writeSurfaceSyncCommandToRingEP25AMDRadeonX4000_IAMDHWRingjj 000000000005e154 g 0f SECT 01 0000 [.text] __ZN36AMDRadeonX4000_AMDPM4CommandsUtility4freeEv 000000000005e142 g 0f SECT 01 0000 [.text] __ZN36AMDRadeonX4000_AMDPM4CommandsUtility4initEv 000000000005dfb0 g 0f SECT 01 0000 [.text] __ZN36AMDRadeonX4000_AMDPM4CommandsUtility9MetaClassC1Ev 000000000005e070 g 0f SECT 01 0000 [.text] __ZN36AMDRadeonX4000_AMDPM4CommandsUtility9MetaClassC2Ev 00000000003a88f0 g 0f SECT 08 0000 [.const_data] __ZN36AMDRadeonX4000_AMDPM4CommandsUtility9metaClassE 000000000005e00c g 0f SECT 01 0000 [.text] __ZN36AMDRadeonX4000_AMDPM4CommandsUtilityC1EPK11OSMetaClass 000000000005e0e2 g 0f SECT 01 0000 [.text] __ZN36AMDRadeonX4000_AMDPM4CommandsUtilityC1Ev 000000000005dfec g 0f SECT 01 0000 [.text] __ZN36AMDRadeonX4000_AMDPM4CommandsUtilityC2EPK11OSMetaClass 000000000005e112 g 0f SECT 01 0000 [.text] __ZN36AMDRadeonX4000_AMDPM4CommandsUtilityC2Ev 000000000005e040 g 0f SECT 01 0000 [.text] __ZN36AMDRadeonX4000_AMDPM4CommandsUtilityD0Ev 000000000005e036 g 0f SECT 01 0000 [.text] __ZN36AMDRadeonX4000_AMDPM4CommandsUtilityD1Ev 000000000005e02c g 0f SECT 01 0000 [.text] __ZN36AMDRadeonX4000_AMDPM4CommandsUtilityD2Ev 000000000052d188 g 0f SECT 0a 0000 [__DATA.__common] __ZN36AMDRadeonX4000_IAMDAtomicBlitManager10gMetaClassE 00000000003905a8 g 0f SECT 08 0000 [.const_data] __ZN36AMDRadeonX4000_IAMDAtomicBlitManager10superClassE 0000000000021990 g 0f SECT 01 0000 [.text] __ZN36AMDRadeonX4000_IAMDAtomicBlitManager9MetaClassC1Ev 0000000000021a30 g 0f SECT 01 0000 [.text] __ZN36AMDRadeonX4000_IAMDAtomicBlitManager9MetaClassC2Ev 00000000003905a0 g 0f SECT 08 0000 [.const_data] __ZN36AMDRadeonX4000_IAMDAtomicBlitManager9metaClassE 00000000000219cc g 0f SECT 01 0000 [.text] __ZN36AMDRadeonX4000_IAMDAtomicBlitManagerC2EPK11OSMetaClass 0000000000021a00 g 0f SECT 01 0000 [.text] __ZN36AMDRadeonX4000_IAMDAtomicBlitManagerD0Ev 00000000000219f6 g 0f SECT 01 0000 [.text] __ZN36AMDRadeonX4000_IAMDAtomicBlitManagerD1Ev 00000000000219ec g 0f SECT 01 0000 [.text] __ZN36AMDRadeonX4000_IAMDAtomicBlitManagerD2Ev 000000000052dbf8 g 0f SECT 0a 0000 [__DATA.__common] __ZN36AMDRadeonX4000_IAMDHWSemaphoreMemMgr10gMetaClassE 00000000003a52d0 g 0f SECT 08 0000 [.const_data] __ZN36AMDRadeonX4000_IAMDHWSemaphoreMemMgr10superClassE 0000000000052de4 g 0f SECT 01 0000 [.text] __ZN36AMDRadeonX4000_IAMDHWSemaphoreMemMgr9MetaClassC1Ev 0000000000052e84 g 0f SECT 01 0000 [.text] __ZN36AMDRadeonX4000_IAMDHWSemaphoreMemMgr9MetaClassC2Ev 00000000003a52c8 g 0f SECT 08 0000 [.const_data] __ZN36AMDRadeonX4000_IAMDHWSemaphoreMemMgr9metaClassE 0000000000052e20 g 0f SECT 01 0000 [.text] __ZN36AMDRadeonX4000_IAMDHWSemaphoreMemMgrC2EPK11OSMetaClass 0000000000052e54 g 0f SECT 01 0000 [.text] __ZN36AMDRadeonX4000_IAMDHWSemaphoreMemMgrD0Ev 0000000000052e4a g 0f SECT 01 0000 [.text] __ZN36AMDRadeonX4000_IAMDHWSemaphoreMemMgrD1Ev 0000000000052e40 g 0f SECT 01 0000 [.text] __ZN36AMDRadeonX4000_IAMDHWSemaphoreMemMgrD2Ev 000000000052d3b0 g 0f SECT 0a 0000 [__DATA.__common] __ZN36AMDRadeonX4000_IAMDStatisticsManager10gMetaClassE 00000000003913c8 g 0f SECT 08 0000 [.const_data] __ZN36AMDRadeonX4000_IAMDStatisticsManager10superClassE 00000000000255c0 g 0f SECT 01 0000 [.text] __ZN36AMDRadeonX4000_IAMDStatisticsManager9MetaClassC1Ev 0000000000025660 g 0f SECT 01 0000 [.text] __ZN36AMDRadeonX4000_IAMDStatisticsManager9MetaClassC2Ev 00000000003913c0 g 0f SECT 08 0000 [.const_data] __ZN36AMDRadeonX4000_IAMDStatisticsManager9metaClassE 00000000000255fc g 0f SECT 01 0000 [.text] __ZN36AMDRadeonX4000_IAMDStatisticsManagerC2EPK11OSMetaClass 0000000000025630 g 0f SECT 01 0000 [.text] __ZN36AMDRadeonX4000_IAMDStatisticsManagerD0Ev 0000000000025626 g 0f SECT 01 0000 [.text] __ZN36AMDRadeonX4000_IAMDStatisticsManagerD1Ev 000000000002561c g 0f SECT 01 0000 [.text] __ZN36AMDRadeonX4000_IAMDStatisticsManagerD2Ev 0000000000005d48 g 0f SECT 01 0000 [.text] __ZN37AMDRadeonX4000_AMDAccelDisplayMachine10VblankFuncEP8OSObjectP22IOInterruptEventSourcei 000000000052cee0 g 0f SECT 0a 0000 [__DATA.__common] __ZN37AMDRadeonX4000_AMDAccelDisplayMachine10gMetaClassE 000000000038a7e8 g 0f SECT 08 0000 [.const_data] __ZN37AMDRadeonX4000_AMDAccelDisplayMachine10superClassE 0000000000006304 g 0f SECT 01 0000 [.text] __ZN37AMDRadeonX4000_AMDAccelDisplayMachine12FEDSShutdownEv 0000000000005f34 g 0f SECT 01 0000 [.text] __ZN37AMDRadeonX4000_AMDAccelDisplayMachine12idleVBLQueueEj 0000000000008704 g 0f SECT 01 0000 [.text] __ZN37AMDRadeonX4000_AMDAccelDisplayMachine12resetScanoutEP12IOAccelEventjP16IOAccelResource2S3_ 0000000000008698 g 0f SECT 01 0000 [.text] __ZN37AMDRadeonX4000_AMDAccelDisplayMachine12setupScanoutEjP16IOAccelResource2S1_ 0000000000006fda g 0f SECT 01 0000 [.text] __ZN37AMDRadeonX4000_AMDAccelDisplayMachine13FEDSConfigureEv 0000000000008778 g 0f SECT 01 0000 [.text] __ZN37AMDRadeonX4000_AMDAccelDisplayMachine14isTripleBufferEj 00000000000083e4 g 0f SECT 01 0000 [.text] __ZN37AMDRadeonX4000_AMDAccelDisplayMachine15resetFullScreenEP12IOAccelEventjP16IOAccelResource2S3_ 00000000000080ac g 0f SECT 01 0000 [.text] __ZN37AMDRadeonX4000_AMDAccelDisplayMachine15setupFullScreenEjP16IOAccelResource2S1_ 0000000000007124 g 0f SECT 01 0000 [.text] __ZN37AMDRadeonX4000_AMDAccelDisplayMachine16reserveNDRVSpaceEv 000000000000868e g 0f SECT 01 0000 [.text] __ZN37AMDRadeonX4000_AMDAccelDisplayMachine16submitFlipBufferEP12IOAccelEventjjP16IOAccelResource2S3_ 0000000000007252 g 0f SECT 01 0000 [.text] __ZN37AMDRadeonX4000_AMDAccelDisplayMachine18reserveFrameBufferEjyjP16IOAccelResource2 0000000000009058 g 0f SECT 01 0000 [.text] __ZN37AMDRadeonX4000_AMDAccelDisplayMachine18scheduleVblankFlipEjP16IOAccelResource2S1_j 00000000000092bc g 0f SECT 01 0000 [.text] __ZN37AMDRadeonX4000_AMDAccelDisplayMachine19getScanoutTransformEjP22IOAccelAffineTransform 000000000000708a g 0f SECT 01 0000 [.text] __ZN37AMDRadeonX4000_AMDAccelDisplayMachine19initAffineTransformEj 000000000000797a g 0f SECT 01 0000 [.text] __ZN37AMDRadeonX4000_AMDAccelDisplayMachine19initScanoutResourceEjjP13IOFramebufferP16IOAccelResource2 0000000000006338 g 0f SECT 01 0000 [.text] __ZN37AMDRadeonX4000_AMDAccelDisplayMachine20displayModeDidChangeEv 000000000000850c g 0f SECT 01 0000 [.text] __ZN37AMDRadeonX4000_AMDAccelDisplayMachine21clearFramebufferImageEjP16IOAccelResource2 0000000000005f96 g 0f SECT 01 0000 [.text] __ZN37AMDRadeonX4000_AMDAccelDisplayMachine21displayModeWillChangeEv 000000000000800e g 0f SECT 01 0000 [.text] __ZN37AMDRadeonX4000_AMDAccelDisplayMachine22destroyScanoutResourceEjjP13IOFramebufferP16IOAccelResource2 000000000000932a g 0f SECT 01 0000 [.text] __ZN37AMDRadeonX4000_AMDAccelDisplayMachine22getScanoutInvTransformEjP22IOAccelAffineTransform 00000000000091dc g 0f SECT 01 0000 [.text] __ZN37AMDRadeonX4000_AMDAccelDisplayMachine22isBufferReadyForRenderEjy 00000000000071e4 g 0f SECT 01 0000 [.text] __ZN37AMDRadeonX4000_AMDAccelDisplayMachine23VblankInterruptCallbackEP8OSObjectPv 0000000000008a1a g 0f SECT 01 0000 [.text] __ZN37AMDRadeonX4000_AMDAccelDisplayMachine23convertFramebufferImageEjP16IOAccelResource2b 000000000000741c g 0f SECT 01 0000 [.text] __ZN37AMDRadeonX4000_AMDAccelDisplayMachine23initFramebufferResourceEjjP13IOFramebufferP16IOAccelResource2 0000000000008766 g 0f SECT 01 0000 [.text] __ZN37AMDRadeonX4000_AMDAccelDisplayMachine23submitScanoutFlipBufferEP12IOAccelEventjjP16IOAccelResource2S3_ 0000000000008146 g 0f SECT 01 0000 [.text] __ZN37AMDRadeonX4000_AMDAccelDisplayMachine23updateFrameBufferOffsetEP12IOAccelEventjjP16IOAccelResource2S3_ 00000000000091a8 g 0f SECT 01 0000 [.text] __ZN37AMDRadeonX4000_AMDAccelDisplayMachine25enableVBLChannelInterruptEv 00000000000069b6 g 0f SECT 01 0000 [.text] __ZN37AMDRadeonX4000_AMDAccelDisplayMachine25set_display_mode_and_vramEv 00000000000078ae g 0f SECT 01 0000 [.text] __ZN37AMDRadeonX4000_AMDAccelDisplayMachine26destroyFramebufferResourceEjjP13IOFramebufferP16IOAccelResource2 00000000000091c2 g 0f SECT 01 0000 [.text] __ZN37AMDRadeonX4000_AMDAccelDisplayMachine26disableVBLChannelInterruptEv 0000000000008798 g 0f SECT 01 0000 [.text] __ZN37AMDRadeonX4000_AMDAccelDisplayMachine30freeNextPreAllocatedTempBufferEj 000000000000628c g 0f SECT 01 0000 [.text] __ZN37AMDRadeonX4000_AMDAccelDisplayMachine31cleanAllPreAllocatedTempBuffersEv 00000000000088d8 g 0f SECT 01 0000 [.text] __ZN37AMDRadeonX4000_AMDAccelDisplayMachine34allocateNextPreAllocatedTempBufferEj 0000000000008770 g 0f SECT 01 0000 [.text] __ZN37AMDRadeonX4000_AMDAccelDisplayMachine34needsSecondaryFramebufferResourcesEv 0000000000005a62 g 0f SECT 01 0000 [.text] __ZN37AMDRadeonX4000_AMDAccelDisplayMachine4initEP22IOGraphicsAccelerator2 0000000000005e38 g 0f SECT 01 0000 [.text] __ZN37AMDRadeonX4000_AMDAccelDisplayMachine4stopEv 0000000000005c56 g 0f SECT 01 0000 [.text] __ZN37AMDRadeonX4000_AMDAccelDisplayMachine8FEDSFuncEP8OSObjectP18IOTimerEventSource 00000000000058d0 g 0f SECT 01 0000 [.text] __ZN37AMDRadeonX4000_AMDAccelDisplayMachine9MetaClassC1Ev 0000000000005990 g 0f SECT 01 0000 [.text] __ZN37AMDRadeonX4000_AMDAccelDisplayMachine9MetaClassC2Ev 000000000038a7e0 g 0f SECT 08 0000 [.const_data] __ZN37AMDRadeonX4000_AMDAccelDisplayMachine9metaClassE 0000000000008070 g 0f SECT 01 0000 [.text] __ZN37AMDRadeonX4000_AMDAccelDisplayMachine9setStereoEj17IOAccelStereoMode 0000000000009398 g 0f SECT 01 0000 [.text] __ZN37AMDRadeonX4000_AMDAccelDisplayMachine9signalVBLEv 000000000000592c g 0f SECT 01 0000 [.text] __ZN37AMDRadeonX4000_AMDAccelDisplayMachineC1EPK11OSMetaClass 0000000000005a02 g 0f SECT 01 0000 [.text] __ZN37AMDRadeonX4000_AMDAccelDisplayMachineC1Ev 000000000000590c g 0f SECT 01 0000 [.text] __ZN37AMDRadeonX4000_AMDAccelDisplayMachineC2EPK11OSMetaClass 0000000000005a32 g 0f SECT 01 0000 [.text] __ZN37AMDRadeonX4000_AMDAccelDisplayMachineC2Ev 0000000000005960 g 0f SECT 01 0000 [.text] __ZN37AMDRadeonX4000_AMDAccelDisplayMachineD0Ev 0000000000005956 g 0f SECT 01 0000 [.text] __ZN37AMDRadeonX4000_AMDAccelDisplayMachineD1Ev 000000000000594c g 0f SECT 01 0000 [.text] __ZN37AMDRadeonX4000_AMDAccelDisplayMachineD2Ev 000000000052f070 g 0f SECT 0a 0000 [__DATA.__common] __ZN37AMDRadeonX4000_AMDFPReleaseSessionMsg10gMetaClassE 00000000003c2f90 g 0f SECT 08 0000 [.const_data] __ZN37AMDRadeonX4000_AMDFPReleaseSessionMsg10superClassE 000000000012768a g 0f SECT 01 0000 [.text] __ZN37AMDRadeonX4000_AMDFPReleaseSessionMsg4freeEv 00000000001275fc g 0f SECT 01 0000 [.text] __ZN37AMDRadeonX4000_AMDFPReleaseSessionMsg4initEPv 000000000012746a g 0f SECT 01 0000 [.text] __ZN37AMDRadeonX4000_AMDFPReleaseSessionMsg9MetaClassC1Ev 000000000012752a g 0f SECT 01 0000 [.text] __ZN37AMDRadeonX4000_AMDFPReleaseSessionMsg9MetaClassC2Ev 00000000003c2f88 g 0f SECT 08 0000 [.const_data] __ZN37AMDRadeonX4000_AMDFPReleaseSessionMsg9metaClassE 00000000001274c6 g 0f SECT 01 0000 [.text] __ZN37AMDRadeonX4000_AMDFPReleaseSessionMsgC1EPK11OSMetaClass 000000000012759c g 0f SECT 01 0000 [.text] __ZN37AMDRadeonX4000_AMDFPReleaseSessionMsgC1Ev 00000000001274a6 g 0f SECT 01 0000 [.text] __ZN37AMDRadeonX4000_AMDFPReleaseSessionMsgC2EPK11OSMetaClass 00000000001275cc g 0f SECT 01 0000 [.text] __ZN37AMDRadeonX4000_AMDFPReleaseSessionMsgC2Ev 00000000001274fa g 0f SECT 01 0000 [.text] __ZN37AMDRadeonX4000_AMDFPReleaseSessionMsgD0Ev 00000000001274f0 g 0f SECT 01 0000 [.text] __ZN37AMDRadeonX4000_AMDFPReleaseSessionMsgD1Ev 00000000001274e6 g 0f SECT 01 0000 [.text] __ZN37AMDRadeonX4000_AMDFPReleaseSessionMsgD2Ev 000000000052ce68 g 0f SECT 0a 0000 [__DATA.__common] __ZN37AMDRadeonX4000_AMDGraphicsAccelerator10gMetaClassE 0000000000388dc8 g 0f SECT 08 0000 [.const_data] __ZN37AMDRadeonX4000_AMDGraphicsAccelerator10superClassE 0000000000003612 g 0f SECT 01 0000 [.text] __ZN37AMDRadeonX4000_AMDGraphicsAccelerator11QSCCallbackEP8OSObjectPv 000000000000352e g 0f SECT 01 0000 [.text] __ZN37AMDRadeonX4000_AMDGraphicsAccelerator11setQSCStateEPvj 0000000000003e9e g 0f SECT 01 0000 [.text] __ZN37AMDRadeonX4000_AMDGraphicsAccelerator12createBltMgrEv 0000000000003f2e g 0f SECT 01 0000 [.text] __ZN37AMDRadeonX4000_AMDGraphicsAccelerator12deleteBltMgrEv 0000000000003028 g 0f SECT 01 0000 [.text] __ZN37AMDRadeonX4000_AMDGraphicsAccelerator12new2DContextEv 00000000000030a4 g 0f SECT 01 0000 [.text] __ZN37AMDRadeonX4000_AMDGraphicsAccelerator12newMemoryMapEv 0000000000003058 g 0f SECT 01 0000 [.text] __ZN37AMDRadeonX4000_AMDGraphicsAccelerator12newSysMemoryEv 000000000000307e g 0f SECT 01 0000 [.text] __ZN37AMDRadeonX4000_AMDGraphicsAccelerator12newVidMemoryEv 00000000000021ca g 0f SECT 01 0000 [.text] __ZN37AMDRadeonX4000_AMDGraphicsAccelerator12tmpTotalVRAMEv 00000000000030f2 g 0f SECT 01 0000 [.text] __ZN37AMDRadeonX4000_AMDGraphicsAccelerator13newStatisticsEv 000000000000416a g 0f SECT 01 0000 [.text] __ZN37AMDRadeonX4000_AMDGraphicsAccelerator13sendPMCommandEPv 0000000000003ca4 g 0f SECT 01 0000 [.text] __ZN37AMDRadeonX4000_AMDGraphicsAccelerator13setDeviceTypeEP11IOPCIDevice 0000000000002c68 g 0f SECT 01 0000 [.text] __ZN37AMDRadeonX4000_AMDGraphicsAccelerator13systemDidWakeEv 00000000000030ca g 0f SECT 01 0000 [.text] __ZN37AMDRadeonX4000_AMDGraphicsAccelerator14createResourceEv 000000000000220a g 0f SECT 01 0000 [.text] __ZN37AMDRadeonX4000_AMDGraphicsAccelerator14getStampMemoryEPj 00000000000027dc g 0f SECT 01 0000 [.text] __ZN37AMDRadeonX4000_AMDGraphicsAccelerator14initLinkToPeerEPKc 0000000000001976 g 0f SECT 01 0000 [.text] __ZN37AMDRadeonX4000_AMDGraphicsAccelerator14loadSlotNumberEv 00000000000029d0 g 0f SECT 01 0000 [.text] __ZN37AMDRadeonX4000_AMDGraphicsAccelerator14teardownDeviceEP11IOPCIDevice 000000000000245e g 0f SECT 01 0000 [.text] __ZN37AMDRadeonX4000_AMDGraphicsAccelerator15configureDeviceEP11IOPCIDevice 0000000000003a72 g 0f SECT 01 0000 [.text] __ZN37AMDRadeonX4000_AMDGraphicsAccelerator15createHWHandlerEv 000000000000223c g 0f SECT 01 0000 [.text] __ZN37AMDRadeonX4000_AMDGraphicsAccelerator15newEventMachineEv 0000000000003118 g 0f SECT 01 0000 [.text] __ZN37AMDRadeonX4000_AMDGraphicsAccelerator15printSlotNumberEv 0000000000002ad8 g 0f SECT 01 0000 [.text] __ZN37AMDRadeonX4000_AMDGraphicsAccelerator15systemWillSleepEv 0000000000003abc g 0f SECT 01 0000 [.text] __ZN37AMDRadeonX4000_AMDGraphicsAccelerator17createHWInterfaceEP11IOPCIDevice 0000000000002262 g 0f SECT 01 0000 [.text] __ZN37AMDRadeonX4000_AMDGraphicsAccelerator17createUserGPUTaskEv 0000000000003d48 g 0f SECT 01 0000 [.text] __ZN37AMDRadeonX4000_AMDGraphicsAccelerator17getMaxGartEntriesEv 00000000000028d0 g 0f SECT 01 0000 [.text] __ZN37AMDRadeonX4000_AMDGraphicsAccelerator18NDRVGetSurfaceInfoEPvP24_AMD_SURFACE_INFO_STRUCT 0000000000003b92 g 0f SECT 01 0000 [.text] __ZN37AMDRadeonX4000_AMDGraphicsAccelerator18fillGartParametersER16_GART_PARAMETERS 0000000000003226 g 0f SECT 01 0000 [.text] __ZN37AMDRadeonX4000_AMDGraphicsAccelerator18getNumericPropertyEPKc 000000000000325c g 0f SECT 01 0000 [.text] __ZN37AMDRadeonX4000_AMDGraphicsAccelerator18getNumericPropertyEPKcPj 00000000000021ec g 0f SECT 01 0000 [.text] __ZN37AMDRadeonX4000_AMDGraphicsAccelerator18totalTextureMemoryEv 0000000000001a02 g 0f SECT 01 0000 [.text] __ZN37AMDRadeonX4000_AMDGraphicsAccelerator19createAccelChannelsEv 0000000000002a72 g 0f SECT 01 0000 [.text] __ZN37AMDRadeonX4000_AMDGraphicsAccelerator19createKernelGPUTaskEv 0000000000003d7e g 0f SECT 01 0000 [.text] __ZN37AMDRadeonX4000_AMDGraphicsAccelerator19initialize_hardwareEv 0000000000002fb6 g 0f SECT 01 0000 [.text] __ZN37AMDRadeonX4000_AMDGraphicsAccelerator19newSharedUserClientEv 0000000000002318 g 0f SECT 01 0000 [.text] __ZN37AMDRadeonX4000_AMDGraphicsAccelerator19populateAccelConfigEP13IOAccelConfig 0000000000004382 g 0f SECT 01 0000 [.text] __ZN37AMDRadeonX4000_AMDGraphicsAccelerator20callPlatformFunctionEPK8OSSymbolbPvS3_S3_S3_ 0000000000001b94 g 0f SECT 01 0000 [.text] __ZN37AMDRadeonX4000_AMDGraphicsAccelerator20newCommandBufferPoolEP11IOAccelTaskP15IOAccelChannel2 0000000000002f0e g 0f SECT 01 0000 [.text] __ZN37AMDRadeonX4000_AMDGraphicsAccelerator20systemDidChangeSpeedEv 0000000000004200 g 0f SECT 01 0000 [.text] __ZN37AMDRadeonX4000_AMDGraphicsAccelerator20writeDiagnosisReportERPcRj 0000000000003f9c g 0f SECT 01 0000 [.text] __ZN37AMDRadeonX4000_AMDGraphicsAccelerator21enableInterruptHubAgpEv 00000000000041b0 g 0f SECT 01 0000 [.text] __ZN37AMDRadeonX4000_AMDGraphicsAccelerator21getUVDFirmwareReserveEP10_SRAMInfo_ 0000000000001c00 g 0f SECT 01 0000 [.text] __ZN37AMDRadeonX4000_AMDGraphicsAccelerator21initCommandBufferPoolEP25IOAccelCommandBufferPool2P11IOAccelTaskP15IOAccelChannel2 0000000000002e5c g 0f SECT 01 0000 [.text] __ZN37AMDRadeonX4000_AMDGraphicsAccelerator21systemWillChangeSpeedEv 00000000000020fc g 0f SECT 01 0000 [.text] __ZN37AMDRadeonX4000_AMDGraphicsAccelerator22disableInterruptHubAgpEv 00000000000034c8 g 0f SECT 01 0000 [.text] __ZN37AMDRadeonX4000_AMDGraphicsAccelerator22registerForQSCcallbackEPFvP8OSObjectPvES1_S2_PS2_ 0000000000003a28 g 0f SECT 01 0000 [.text] __ZN37AMDRadeonX4000_AMDGraphicsAccelerator23createStatisticsManagerEv 0000000000003738 g 0f SECT 01 0000 [.text] __ZN37AMDRadeonX4000_AMDGraphicsAccelerator23iofbNotificationHandlerEP8OSObjectPvP13IOFramebufferiS2_ 00000000000036c0 g 0f SECT 01 0000 [.text] __ZN37AMDRadeonX4000_AMDGraphicsAccelerator23registerForIOFBCallbackEv 0000000000002888 g 0f SECT 01 0000 [.text] __ZN37AMDRadeonX4000_AMDGraphicsAccelerator23sendRequestToControllerE25_eAMDAccelIOFBRequestTypePvS1_S1_ 0000000000003444 g 0f SECT 01 0000 [.text] __ZN37AMDRadeonX4000_AMDGraphicsAccelerator23setVblankInterruptStateEjPvj 0000000000003792 g 0f SECT 01 0000 [.text] __ZN37AMDRadeonX4000_AMDGraphicsAccelerator24allocateGlobalTempBufferEP11IOAccelTaskP14IOAccelShared227eAMDAccGLobalBlitTempBufferjj 000000000000348a g 0f SECT 01 0000 [.text] __ZN37AMDRadeonX4000_AMDGraphicsAccelerator25unregisterVblankInterruptEjPv 000000000000392a g 0f SECT 01 0000 [.text] __ZN37AMDRadeonX4000_AMDGraphicsAccelerator26deallocateGlobalTempBufferE27eAMDAccGLobalBlitTempBuffer 00000000000033a4 g 0f SECT 01 0000 [.text] __ZN37AMDRadeonX4000_AMDGraphicsAccelerator26registerForVblankInterruptEjPFvP8OSObjectPvES1_S2_PS2_ 000000000000331c g 0f SECT 01 0000 [.text] __ZN37AMDRadeonX4000_AMDGraphicsAccelerator26setTimestampInterruptStateEPvj 0000000000003962 g 0f SECT 01 0000 [.text] __ZN37AMDRadeonX4000_AMDGraphicsAccelerator27deallocateGlobalTempBuffersEv 000000000000399e g 0f SECT 01 0000 [.text] __ZN37AMDRadeonX4000_AMDGraphicsAccelerator27enableHWMemoryCleanupThreadEj 00000000000039ec g 0f SECT 01 0000 [.text] __ZN37AMDRadeonX4000_AMDGraphicsAccelerator28disableHWMemoryCleanupThreadEv 0000000000003364 g 0f SECT 01 0000 [.text] __ZN37AMDRadeonX4000_AMDGraphicsAccelerator28unregisterTimestampInterruptEPv 0000000000003150 g 0f SECT 01 0000 [.text] __ZN37AMDRadeonX4000_AMDGraphicsAccelerator29addPlistPropertiesToPCIDeviceEPKc 000000000000244c g 0f SECT 01 0000 [.text] __ZN37AMDRadeonX4000_AMDGraphicsAccelerator29calcMaxGPUPhysicalMemoryBytesEy 00000000000032a8 g 0f SECT 01 0000 [.text] __ZN37AMDRadeonX4000_AMDGraphicsAccelerator29registerForTimestampInterruptEjPFvP8OSObjectPvES1_S2_PS2_ 0000000000001b0e g 0f SECT 01 0000 [.text] __ZN37AMDRadeonX4000_AMDGraphicsAccelerator33executeHWMemoryCleanupThreadTimerEP8OSObjectP18IOTimerEventSource 0000000000001dea g 0f SECT 01 0000 [.text] __ZN37AMDRadeonX4000_AMDGraphicsAccelerator4stopEP9IOService 00000000000014aa g 0f SECT 01 0000 [.text] __ZN37AMDRadeonX4000_AMDGraphicsAccelerator5startEP9IOService 00000000000013d0 g 0f SECT 01 0000 [.text] __ZN37AMDRadeonX4000_AMDGraphicsAccelerator9MetaClassC1Ev 0000000000001470 g 0f SECT 01 0000 [.text] __ZN37AMDRadeonX4000_AMDGraphicsAccelerator9MetaClassC2Ev 0000000000388dc0 g 0f SECT 08 0000 [.const_data] __ZN37AMDRadeonX4000_AMDGraphicsAccelerator9metaClassE 0000000000003002 g 0f SECT 01 0000 [.text] __ZN37AMDRadeonX4000_AMDGraphicsAccelerator9newDeviceEv 0000000000002fdc g 0f SECT 01 0000 [.text] __ZN37AMDRadeonX4000_AMDGraphicsAccelerator9newSharedEv 0000000000003d54 g 0f SECT 01 0000 [.text] __ZN37AMDRadeonX4000_AMDGraphicsAccelerator9signalVBLEv 000000000000140c g 0f SECT 01 0000 [.text] __ZN37AMDRadeonX4000_AMDGraphicsAcceleratorC2EPK11OSMetaClass 0000000000001440 g 0f SECT 01 0000 [.text] __ZN37AMDRadeonX4000_AMDGraphicsAcceleratorD0Ev 0000000000001436 g 0f SECT 01 0000 [.text] __ZN37AMDRadeonX4000_AMDGraphicsAcceleratorD1Ev 000000000000142c g 0f SECT 01 0000 [.text] __ZN37AMDRadeonX4000_AMDGraphicsAcceleratorD2Ev 000000000052ef80 g 0f SECT 0a 0000 [__DATA.__common] __ZN37AMDRadeonX4000_AMDHDCPCloseSessionMsg10gMetaClassE 00000000003c2030 g 0f SECT 08 0000 [.const_data] __ZN37AMDRadeonX4000_AMDHDCPCloseSessionMsg10superClassE 0000000000126596 g 0f SECT 01 0000 [.text] __ZN37AMDRadeonX4000_AMDHDCPCloseSessionMsg4freeEv 0000000000126508 g 0f SECT 01 0000 [.text] __ZN37AMDRadeonX4000_AMDHDCPCloseSessionMsg4initEPv 0000000000126376 g 0f SECT 01 0000 [.text] __ZN37AMDRadeonX4000_AMDHDCPCloseSessionMsg9MetaClassC1Ev 0000000000126436 g 0f SECT 01 0000 [.text] __ZN37AMDRadeonX4000_AMDHDCPCloseSessionMsg9MetaClassC2Ev 00000000003c2028 g 0f SECT 08 0000 [.const_data] __ZN37AMDRadeonX4000_AMDHDCPCloseSessionMsg9metaClassE 00000000001263d2 g 0f SECT 01 0000 [.text] __ZN37AMDRadeonX4000_AMDHDCPCloseSessionMsgC1EPK11OSMetaClass 00000000001264a8 g 0f SECT 01 0000 [.text] __ZN37AMDRadeonX4000_AMDHDCPCloseSessionMsgC1Ev 00000000001263b2 g 0f SECT 01 0000 [.text] __ZN37AMDRadeonX4000_AMDHDCPCloseSessionMsgC2EPK11OSMetaClass 00000000001264d8 g 0f SECT 01 0000 [.text] __ZN37AMDRadeonX4000_AMDHDCPCloseSessionMsgC2Ev 0000000000126406 g 0f SECT 01 0000 [.text] __ZN37AMDRadeonX4000_AMDHDCPCloseSessionMsgD0Ev 00000000001263fc g 0f SECT 01 0000 [.text] __ZN37AMDRadeonX4000_AMDHDCPCloseSessionMsgD1Ev 00000000001263f2 g 0f SECT 01 0000 [.text] __ZN37AMDRadeonX4000_AMDHDCPCloseSessionMsgD2Ev 000000000052d450 g 0f SECT 0a 0000 [__DATA.__common] __ZN37AMDRadeonX4000_AMDHWChannelStatsGroup10gMetaClassE 0000000000391da8 g 0f SECT 08 0000 [.const_data] __ZN37AMDRadeonX4000_AMDHWChannelStatsGroup10superClassE 0000000000026480 g 0f SECT 01 0000 [.text] __ZN37AMDRadeonX4000_AMDHWChannelStatsGroup14dumpGroupStatsEP12OSDictionaryb 000000000002644a g 0f SECT 01 0000 [.text] __ZN37AMDRadeonX4000_AMDHWChannelStatsGroup4freeEv 00000000000263c2 g 0f SECT 01 0000 [.text] __ZN37AMDRadeonX4000_AMDHWChannelStatsGroup4initEP27AMDRadeonX4000_AMDHWChannelPKcS3_jPS3_S4_j 0000000000026230 g 0f SECT 01 0000 [.text] __ZN37AMDRadeonX4000_AMDHWChannelStatsGroup9MetaClassC1Ev 00000000000262f0 g 0f SECT 01 0000 [.text] __ZN37AMDRadeonX4000_AMDHWChannelStatsGroup9MetaClassC2Ev 0000000000391da0 g 0f SECT 08 0000 [.const_data] __ZN37AMDRadeonX4000_AMDHWChannelStatsGroup9metaClassE 000000000002628c g 0f SECT 01 0000 [.text] __ZN37AMDRadeonX4000_AMDHWChannelStatsGroupC1EPK11OSMetaClass 0000000000026362 g 0f SECT 01 0000 [.text] __ZN37AMDRadeonX4000_AMDHWChannelStatsGroupC1Ev 000000000002626c g 0f SECT 01 0000 [.text] __ZN37AMDRadeonX4000_AMDHWChannelStatsGroupC2EPK11OSMetaClass 0000000000026392 g 0f SECT 01 0000 [.text] __ZN37AMDRadeonX4000_AMDHWChannelStatsGroupC2Ev 00000000000262c0 g 0f SECT 01 0000 [.text] __ZN37AMDRadeonX4000_AMDHWChannelStatsGroupD0Ev 00000000000262b6 g 0f SECT 01 0000 [.text] __ZN37AMDRadeonX4000_AMDHWChannelStatsGroupD1Ev 00000000000262ac g 0f SECT 01 0000 [.text] __ZN37AMDRadeonX4000_AMDHWChannelStatsGroupD2Ev 000000000052dc48 g 0f SECT 0a 0000 [__DATA.__common] __ZN37AMDRadeonX4000_IAMDPM4CommandsUtility10gMetaClassE 00000000003a5780 g 0f SECT 08 0000 [.const_data] __ZN37AMDRadeonX4000_IAMDPM4CommandsUtility10superClassE 0000000000052f98 g 0f SECT 01 0000 [.text] __ZN37AMDRadeonX4000_IAMDPM4CommandsUtility9MetaClassC1Ev 0000000000053038 g 0f SECT 01 0000 [.text] __ZN37AMDRadeonX4000_IAMDPM4CommandsUtility9MetaClassC2Ev 00000000003a5778 g 0f SECT 08 0000 [.const_data] __ZN37AMDRadeonX4000_IAMDPM4CommandsUtility9metaClassE 0000000000052fd4 g 0f SECT 01 0000 [.text] __ZN37AMDRadeonX4000_IAMDPM4CommandsUtilityC2EPK11OSMetaClass 0000000000053008 g 0f SECT 01 0000 [.text] __ZN37AMDRadeonX4000_IAMDPM4CommandsUtilityD0Ev 0000000000052ffe g 0f SECT 01 0000 [.text] __ZN37AMDRadeonX4000_IAMDPM4CommandsUtilityD1Ev 0000000000052ff4 g 0f SECT 01 0000 [.text] __ZN37AMDRadeonX4000_IAMDPM4CommandsUtilityD2Ev 000000000052d428 g 0f SECT 0a 0000 [__DATA.__common] __ZN38AMDRadeonX4000_AMDAccelStatisticsGroup10gMetaClassE 0000000000391b30 g 0f SECT 08 0000 [.const_data] __ZN38AMDRadeonX4000_AMDAccelStatisticsGroup10superClassE 0000000000026004 g 0f SECT 01 0000 [.text] __ZN38AMDRadeonX4000_AMDAccelStatisticsGroup14dumpGroupStatsEP12OSDictionaryb 000000000002610a g 0f SECT 01 0000 [.text] __ZN38AMDRadeonX4000_AMDAccelStatisticsGroup15resetGroupStatsEv 0000000000025ff2 g 0f SECT 01 0000 [.text] __ZN38AMDRadeonX4000_AMDAccelStatisticsGroup4freeEv 0000000000025f5c g 0f SECT 01 0000 [.text] __ZN38AMDRadeonX4000_AMDAccelStatisticsGroup4initEPK11OSMetaClassPKcS4_jPS4_S5_j 0000000000025dca g 0f SECT 01 0000 [.text] __ZN38AMDRadeonX4000_AMDAccelStatisticsGroup9MetaClassC1Ev 0000000000025e8a g 0f SECT 01 0000 [.text] __ZN38AMDRadeonX4000_AMDAccelStatisticsGroup9MetaClassC2Ev 0000000000391b28 g 0f SECT 08 0000 [.const_data] __ZN38AMDRadeonX4000_AMDAccelStatisticsGroup9metaClassE 0000000000025e26 g 0f SECT 01 0000 [.text] __ZN38AMDRadeonX4000_AMDAccelStatisticsGroupC1EPK11OSMetaClass 0000000000025efc g 0f SECT 01 0000 [.text] __ZN38AMDRadeonX4000_AMDAccelStatisticsGroupC1Ev 0000000000025e06 g 0f SECT 01 0000 [.text] __ZN38AMDRadeonX4000_AMDAccelStatisticsGroupC2EPK11OSMetaClass 0000000000025f2c g 0f SECT 01 0000 [.text] __ZN38AMDRadeonX4000_AMDAccelStatisticsGroupC2Ev 0000000000025e5a g 0f SECT 01 0000 [.text] __ZN38AMDRadeonX4000_AMDAccelStatisticsGroupD0Ev 0000000000025e50 g 0f SECT 01 0000 [.text] __ZN38AMDRadeonX4000_AMDAccelStatisticsGroupD1Ev 0000000000025e46 g 0f SECT 01 0000 [.text] __ZN38AMDRadeonX4000_AMDAccelStatisticsGroupD2Ev 000000000052d048 g 0f SECT 0a 0000 [__DATA.__common] __ZN38AMDRadeonX4000_AMDInterruptEventSource10gMetaClassE 000000000038e2c8 g 0f SECT 08 0000 [.const_data] __ZN38AMDRadeonX4000_AMDInterruptEventSource10superClassE 0000000000016f56 g 0f SECT 01 0000 [.text] __ZN38AMDRadeonX4000_AMDInterruptEventSource15setDisplayIndexEj 0000000000016f32 g 0f SECT 01 0000 [.text] __ZN38AMDRadeonX4000_AMDInterruptEventSource4initEP8OSObjectPFvS1_P22IOInterruptEventSourceiEP9IOServicei 0000000000016da0 g 0f SECT 01 0000 [.text] __ZN38AMDRadeonX4000_AMDInterruptEventSource9MetaClassC1Ev 0000000000016e60 g 0f SECT 01 0000 [.text] __ZN38AMDRadeonX4000_AMDInterruptEventSource9MetaClassC2Ev 000000000038e2c0 g 0f SECT 08 0000 [.const_data] __ZN38AMDRadeonX4000_AMDInterruptEventSource9metaClassE 0000000000016dfc g 0f SECT 01 0000 [.text] __ZN38AMDRadeonX4000_AMDInterruptEventSourceC1EPK11OSMetaClass 0000000000016ed2 g 0f SECT 01 0000 [.text] __ZN38AMDRadeonX4000_AMDInterruptEventSourceC1Ev 0000000000016ddc g 0f SECT 01 0000 [.text] __ZN38AMDRadeonX4000_AMDInterruptEventSourceC2EPK11OSMetaClass 0000000000016f02 g 0f SECT 01 0000 [.text] __ZN38AMDRadeonX4000_AMDInterruptEventSourceC2Ev 0000000000016e30 g 0f SECT 01 0000 [.text] __ZN38AMDRadeonX4000_AMDInterruptEventSourceD0Ev 0000000000016e26 g 0f SECT 01 0000 [.text] __ZN38AMDRadeonX4000_AMDInterruptEventSourceD1Ev 0000000000016e1c g 0f SECT 01 0000 [.text] __ZN38AMDRadeonX4000_AMDInterruptEventSourceD2Ev 000000000052cf80 g 0f SECT 0a 0000 [__DATA.__common] __ZN39AMDRadeonX4000_AMDAccelSharedUserClient10gMetaClassE 000000000001226e g 0f SECT 01 0000 [.text] __ZN39AMDRadeonX4000_AMDAccelSharedUserClient10sharedStopEv 000000000038bc70 g 0f SECT 08 0000 [.const_data] __ZN39AMDRadeonX4000_AMDAccelSharedUserClient10superClassE 0000000000012512 g 0f SECT 01 0000 [.text] __ZN39AMDRadeonX4000_AMDAccelSharedUserClient11SurfaceCopyEPjy 000000000001225c g 0f SECT 01 0000 [.text] __ZN39AMDRadeonX4000_AMDAccelSharedUserClient11sharedStartEv 00000000000122e0 g 0f SECT 01 0000 [.text] __ZN39AMDRadeonX4000_AMDAccelSharedUserClient20MSAATextureReadWriteEP26AMDTextureMSAAPagingPacket 00000000000122a4 g 0f SECT 01 0000 [.text] __ZN39AMDRadeonX4000_AMDAccelSharedUserClient26getTargetAndMethodForIndexEPP9IOServicej 0000000000012280 g 0f SECT 01 0000 [.text] __ZN39AMDRadeonX4000_AMDAccelSharedUserClient4stopEP9IOService 0000000000012292 g 0f SECT 01 0000 [.text] __ZN39AMDRadeonX4000_AMDAccelSharedUserClient5startEP9IOService 00000000000120ca g 0f SECT 01 0000 [.text] __ZN39AMDRadeonX4000_AMDAccelSharedUserClient9MetaClassC1Ev 000000000001218a g 0f SECT 01 0000 [.text] __ZN39AMDRadeonX4000_AMDAccelSharedUserClient9MetaClassC2Ev 000000000038bc68 g 0f SECT 08 0000 [.const_data] __ZN39AMDRadeonX4000_AMDAccelSharedUserClient9metaClassE 0000000000012126 g 0f SECT 01 0000 [.text] __ZN39AMDRadeonX4000_AMDAccelSharedUserClientC1EPK11OSMetaClass 00000000000121fc g 0f SECT 01 0000 [.text] __ZN39AMDRadeonX4000_AMDAccelSharedUserClientC1Ev 0000000000012106 g 0f SECT 01 0000 [.text] __ZN39AMDRadeonX4000_AMDAccelSharedUserClientC2EPK11OSMetaClass 000000000001222c g 0f SECT 01 0000 [.text] __ZN39AMDRadeonX4000_AMDAccelSharedUserClientC2Ev 000000000001215a g 0f SECT 01 0000 [.text] __ZN39AMDRadeonX4000_AMDAccelSharedUserClientD0Ev 0000000000012150 g 0f SECT 01 0000 [.text] __ZN39AMDRadeonX4000_AMDAccelSharedUserClientD1Ev 0000000000012146 g 0f SECT 01 0000 [.text] __ZN39AMDRadeonX4000_AMDAccelSharedUserClientD2Ev 000000000052d020 g 0f SECT 0a 0000 [__DATA.__common] __ZN40AMDRadeonX4000_AMDAccelCommandBufferPool10gMetaClassE 000000000038e088 g 0f SECT 08 0000 [.const_data] __ZN40AMDRadeonX4000_AMDAccelCommandBufferPool10superClassE 0000000000016d24 g 0f SECT 01 0000 [.text] __ZN40AMDRadeonX4000_AMDAccelCommandBufferPool4freeEv 0000000000016d12 g 0f SECT 01 0000 [.text] __ZN40AMDRadeonX4000_AMDAccelCommandBufferPool4initEP22IOGraphicsAccelerator2P15IOAccelChannel2P11IOAccelTaskiijjjj 0000000000016b80 g 0f SECT 01 0000 [.text] __ZN40AMDRadeonX4000_AMDAccelCommandBufferPool9MetaClassC1Ev 0000000000016c40 g 0f SECT 01 0000 [.text] __ZN40AMDRadeonX4000_AMDAccelCommandBufferPool9MetaClassC2Ev 000000000038e080 g 0f SECT 08 0000 [.const_data] __ZN40AMDRadeonX4000_AMDAccelCommandBufferPool9metaClassE 0000000000016bdc g 0f SECT 01 0000 [.text] __ZN40AMDRadeonX4000_AMDAccelCommandBufferPoolC1EPK11OSMetaClass 0000000000016cb2 g 0f SECT 01 0000 [.text] __ZN40AMDRadeonX4000_AMDAccelCommandBufferPoolC1Ev 0000000000016bbc g 0f SECT 01 0000 [.text] __ZN40AMDRadeonX4000_AMDAccelCommandBufferPoolC2EPK11OSMetaClass 0000000000016ce2 g 0f SECT 01 0000 [.text] __ZN40AMDRadeonX4000_AMDAccelCommandBufferPoolC2Ev 0000000000016c10 g 0f SECT 01 0000 [.text] __ZN40AMDRadeonX4000_AMDAccelCommandBufferPoolD0Ev 0000000000016c06 g 0f SECT 01 0000 [.text] __ZN40AMDRadeonX4000_AMDAccelCommandBufferPoolD1Ev 0000000000016bfc g 0f SECT 01 0000 [.text] __ZN40AMDRadeonX4000_AMDAccelCommandBufferPoolD2Ev 000000000052d3d8 g 0f SECT 0a 0000 [__DATA.__common] __ZN40AMDRadeonX4000_AMDAccelStatisticsManager10gMetaClassE 0000000000391640 g 0f SECT 08 0000 [.const_data] __ZN40AMDRadeonX4000_AMDAccelStatisticsManager10superClassE 0000000000025a74 g 0f SECT 01 0000 [.text] __ZN40AMDRadeonX4000_AMDAccelStatisticsManager12dumpAllStatsEP12OSDictionaryb 000000000002595c g 0f SECT 01 0000 [.text] __ZN40AMDRadeonX4000_AMDAccelStatisticsManager13addStatsGroupEP38AMDRadeonX4000_AMDAccelStatisticsGroup 0000000000025bda g 0f SECT 01 0000 [.text] __ZN40AMDRadeonX4000_AMDAccelStatisticsManager13allocDataPageEv 0000000000025b7e g 0f SECT 01 0000 [.text] __ZN40AMDRadeonX4000_AMDAccelStatisticsManager13dumpGroupInfoEP22AMDStatisticsGroupInfoj 0000000000025b56 g 0f SECT 01 0000 [.text] __ZN40AMDRadeonX4000_AMDAccelStatisticsManager13resetAllStatsEv 0000000000025a5e g 0f SECT 01 0000 [.text] __ZN40AMDRadeonX4000_AMDAccelStatisticsManager14freeStatsGroupEP38AMDRadeonX4000_AMDAccelStatisticsGroup 0000000000025aba g 0f SECT 01 0000 [.text] __ZN40AMDRadeonX4000_AMDAccelStatisticsManager18dumpStatsByGroupIdEP12OSDictionaryjb 00000000000258fe g 0f SECT 01 0000 [.text] __ZN40AMDRadeonX4000_AMDAccelStatisticsManager18validateStatsGroupEPKc 0000000000025b16 g 0f SECT 01 0000 [.text] __ZN40AMDRadeonX4000_AMDAccelStatisticsManager19resetStatsByGroupIdEj 0000000000025882 g 0f SECT 01 0000 [.text] __ZN40AMDRadeonX4000_AMDAccelStatisticsManager4freeEv 000000000002582c g 0f SECT 01 0000 [.text] __ZN40AMDRadeonX4000_AMDAccelStatisticsManager4initEP37AMDRadeonX4000_AMDGraphicsAccelerator 000000000002569a g 0f SECT 01 0000 [.text] __ZN40AMDRadeonX4000_AMDAccelStatisticsManager9MetaClassC1Ev 000000000002575a g 0f SECT 01 0000 [.text] __ZN40AMDRadeonX4000_AMDAccelStatisticsManager9MetaClassC2Ev 0000000000391638 g 0f SECT 08 0000 [.const_data] __ZN40AMDRadeonX4000_AMDAccelStatisticsManager9metaClassE 00000000000256f6 g 0f SECT 01 0000 [.text] __ZN40AMDRadeonX4000_AMDAccelStatisticsManagerC1EPK11OSMetaClass 00000000000257cc g 0f SECT 01 0000 [.text] __ZN40AMDRadeonX4000_AMDAccelStatisticsManagerC1Ev 00000000000256d6 g 0f SECT 01 0000 [.text] __ZN40AMDRadeonX4000_AMDAccelStatisticsManagerC2EPK11OSMetaClass 00000000000257fc g 0f SECT 01 0000 [.text] __ZN40AMDRadeonX4000_AMDAccelStatisticsManagerC2Ev 000000000002572a g 0f SECT 01 0000 [.text] __ZN40AMDRadeonX4000_AMDAccelStatisticsManagerD0Ev 0000000000025720 g 0f SECT 01 0000 [.text] __ZN40AMDRadeonX4000_AMDAccelStatisticsManagerD1Ev 0000000000025716 g 0f SECT 01 0000 [.text] __ZN40AMDRadeonX4000_AMDAccelStatisticsManagerD2Ev 000000000052d900 g 0f SECT 0a 0000 [__DATA.__common] __ZN41AMDRadeonX4000_AMDUVDInterruptEventSource10gMetaClassE 00000000003a15a8 g 0f SECT 08 0000 [.const_data] __ZN41AMDRadeonX4000_AMDUVDInterruptEventSource10superClassE 000000000004e472 g 0f SECT 01 0000 [.text] __ZN41AMDRadeonX4000_AMDUVDInterruptEventSource4initEP8OSObjectPFvS1_P22IOInterruptEventSourceiEP9IOServicei 000000000004e2e0 g 0f SECT 01 0000 [.text] __ZN41AMDRadeonX4000_AMDUVDInterruptEventSource9MetaClassC1Ev 000000000004e3a0 g 0f SECT 01 0000 [.text] __ZN41AMDRadeonX4000_AMDUVDInterruptEventSource9MetaClassC2Ev 00000000003a15a0 g 0f SECT 08 0000 [.const_data] __ZN41AMDRadeonX4000_AMDUVDInterruptEventSource9metaClassE 000000000004e33c g 0f SECT 01 0000 [.text] __ZN41AMDRadeonX4000_AMDUVDInterruptEventSourceC1EPK11OSMetaClass 000000000004e412 g 0f SECT 01 0000 [.text] __ZN41AMDRadeonX4000_AMDUVDInterruptEventSourceC1Ev 000000000004e31c g 0f SECT 01 0000 [.text] __ZN41AMDRadeonX4000_AMDUVDInterruptEventSourceC2EPK11OSMetaClass 000000000004e442 g 0f SECT 01 0000 [.text] __ZN41AMDRadeonX4000_AMDUVDInterruptEventSourceC2Ev 000000000004e370 g 0f SECT 01 0000 [.text] __ZN41AMDRadeonX4000_AMDUVDInterruptEventSourceD0Ev 000000000004e366 g 0f SECT 01 0000 [.text] __ZN41AMDRadeonX4000_AMDUVDInterruptEventSourceD1Ev 000000000004e35c g 0f SECT 01 0000 [.text] __ZN41AMDRadeonX4000_AMDUVDInterruptEventSourceD2Ev 000000000009fe9a g 0f SECT 01 0000 [.text] __ZN6BltMgr10DegammaSrcEPK7BltInfoj 000000000009d95a g 0f SECT 01 0000 [.text] __ZN6BltMgr11AllocVidMemEPK22_UBM_ALLOCVIDMEM_INPUTP23_UBM_ALLOCVIDMEM_OUTPUT 000000000009fb14 g 0f SECT 01 0000 [.text] __ZN6BltMgr11DbgDrawPrimEP9BltDeviceP20_UBMDBG_DRAWPRIMINFO 000000000009de26 g 0f SECT 01 0000 [.text] __ZN6BltMgr11GetCmdSpaceEPvj 0000000000098d34 g 0f SECT 01 0000 [.text] __ZN6BltMgr11InitBltInfoEP7BltInfoP9BltDevice 000000000009ca3a g 0f SECT 01 0000 [.text] __ZN6BltMgr11MlaaResolveEP9BltDeviceP20_UBM_MLAARESOLVEINFO 000000000009f31a g 0f SECT 01 0000 [.text] __ZN6BltMgr11SurfaceCopyEP9BltDeviceP20_UBM_SURFACECOPYINFO 000000000009a3aa g 0f SECT 01 0000 [.text] __ZN6BltMgr11YuvToRgbBltEP7BltInfo13LARGE_INTEGER 0000000000099026 g 0f SECT 01 0000 [.text] __ZN6BltMgr12CreateDeviceEP15_UBM_DEVICEINFO 000000000009c16c g 0f SECT 01 0000 [.text] __ZN6BltMgr12GenZRangeMipEP9BltDeviceP21_UBM_GENZRANGEMIPINFO 000000000009bc68 g 0f SECT 01 0000 [.text] __ZN6BltMgr12GenZRangeTexEP9BltDeviceP21_UBM_GENZRANGETEXINFO 000000000009dc9c g 0f SECT 01 0000 [.text] __ZN6BltMgr13AddWideHandleEPvS0_j19_VCOP_RESOURCE_TYPEjjjS1_j26_UBM_ADDHANDLE_INPUT_FLAGS 000000000009de70 g 0f SECT 01 0000 [.text] __ZN6BltMgr13GetCmdBufBaseEPv 000000000009fde6 g 0f SECT 01 0000 [.text] __ZN6BltMgr13IsAdjustedBltEPK7BltInfo 000000000009f6a8 g 0f SECT 01 0000 [.text] __ZN6BltMgr13PartialUploadEP9BltDeviceP22_UBM_PARTIALUPLOADINFO 000000000009f914 g 0f SECT 01 0000 [.text] __ZN6BltMgr14ColorTransformEP9BltDeviceP23_UBM_COLORTRANSFORMINFO 0000000000098d16 g 0f SECT 01 0000 [.text] __ZN6BltMgr14GpuLoadShadersEP9BltDeviceP23_UBM_GPULOADSHADERSINFO 0000000000098df2 g 0f SECT 01 0000 [.text] __ZN6BltMgr14SetupBltEngineEP15_UBM_BLT_ENGINE11_UBM_ENGINE 00000000000996a6 g 0f SECT 01 0000 [.text] __ZN6BltMgr14YuvPackedClearEP7BltInfo 0000000000099110 g 0f SECT 01 0000 [.text] __ZN6BltMgr14YuvPlanarClearEP7BltInfo 0000000000099904 g 0f SECT 01 0000 [.text] __ZN6BltMgr15SetupYuvSurfaceE11_UBM_FORMAT13LARGE_INTEGERP13_UBM_SURFINFOj 000000000009ab3c g 0f SECT 01 0000 [.text] __ZN6BltMgr15StretchToMemcpyEP7BltInfo 0000000000099060 g 0f SECT 01 0000 [.text] __ZN6BltMgr16CreateAuxSurfMgrEv 000000000009ec92 g 0f SECT 01 0000 [.text] __ZN6BltMgr18DesktopCompositionEP9BltDeviceP27_UBM_DESKTOPCOMPOSITIONINFO 000000000009806a g 0f SECT 01 0000 [.text] __ZN6BltMgr19ExecuteFMaskResolveEP7BltInfo 000000000009d098 g 0f SECT 01 0000 [.text] __ZN6BltMgr19ForcePrePostBltSyncEP7BltInfo 000000000009db14 g 0f SECT 01 0000 [.text] __ZN6BltMgr20EnterCriticalSectionEPv 0000000000098222 g 0f SECT 01 0000 [.text] __ZN6BltMgr20ExecuteHybridResolveEP7BltInfo 000000000009db34 g 0f SECT 01 0000 [.text] __ZN6BltMgr20LeaveCriticalSectionEPv 000000000009a474 g 0f SECT 01 0000 [.text] __ZN6BltMgr20YuvPackedToPackedBltEP7BltInfo 000000000009a634 g 0f SECT 01 0000 [.text] __ZN6BltMgr20YuvPlanarToPackedBltEP7BltInfo13LARGE_INTEGER 000000000009a790 g 0f SECT 01 0000 [.text] __ZN6BltMgr20YuvPlanarToPlanarBltEP7BltInfo13LARGE_INTEGERS2_ 000000000009e29e g 0f SECT 01 0000 [.text] __ZN6BltMgr21AdjustBufferBltFormatEP7BltInfo 0000000000098be6 g 0f SECT 01 0000 [.text] __ZN6BltMgr21InitDefaultSampleLocsEPK15_UBM_CREATEINFO 000000000009fe5a g 0f SECT 01 0000 [.text] __ZN6BltMgr21IsLinearGeneralDstBltEPK7BltInfo 000000000009fe1a g 0f SECT 01 0000 [.text] __ZN6BltMgr21IsLinearGeneralSrcBltEPK7BltInfo 000000000009e520 g 0f SECT 01 0000 [.text] __ZN6BltMgr22OptimizeBufferBltRectsEP7BltInfoj 000000000009a212 g 0f SECT 01 0000 [.text] __ZN6BltMgr22OptimizePrePostBltSyncEP7BltInfojj 0000000000098e9e g 0f SECT 01 0000 [.text] __ZN6BltMgr22SetupInterpolationRectEP17InterpolationDesc 0000000000098e3c g 0f SECT 01 0000 [.text] __ZN6BltMgr23SetupRotMirrorTransformEPj16_UBM_ROTATION_CWjj 000000000009a378 g 0f SECT 01 0000 [.text] __ZN6BltMgr24ComputeNumRectsRemainingEP7BltInfo 000000000009743c g 0f SECT 01 0000 [.text] __ZN6BltMgr24ExecuteEdgeDetectResolveEP7BltInfo 000000000009906c g 0f SECT 01 0000 [.text] __ZN6BltMgr27YuvPackMacroPixelClearColorE11_UBM_FORMATP11_UBM_VECTOR 000000000009c75e g 0f SECT 01 0000 [.text] __ZN6BltMgr29ExecuteCompressedDepthResolveEP7BltInfo 00000000000970da g 0f SECT 01 0000 [.text] __ZN6BltMgr29HwlExecuteEdgeDetectPrePassesEP7BltInfoP13_UBM_SURFINFO 000000000009e900 g 0f SECT 01 0000 [.text] __ZN6BltMgr29SelectAAResolveTentFilterTapsEP7BltInfojfP22AAResolveTapDescriptorj 000000000009ff6c g 0f SECT 01 0000 [.text] __ZN6BltMgr35SetupNonEvenLinearFilterSampleCountEj 0000000000098dd0 g 0f SECT 01 0000 [.text] __ZN6BltMgr36SetDefaultSkipPrePostBltSyncSettingsEP7BltInfo 00000000000988e8 g 0f SECT 01 0000 [.text] __ZN6BltMgr4InitEPK14BltMgrInitInfo 0000000000098fde g 0f SECT 01 0000 [.text] __ZN6BltMgr4TrimEv 0000000000099ac0 g 0f SECT 01 0000 [.text] __ZN6BltMgr5ClearEP9BltDeviceP14_UBM_CLEARINFO 0000000000098878 g 0f SECT 01 0000 [.text] __ZN6BltMgr6CreateEPK15_UBM_CREATEINFO 000000000009d0a2 g 0f SECT 01 0000 [.text] __ZN6BltMgr6ExpandEP9BltDeviceP15_UBM_EXPANDINFO 000000000009ac9e g 0f SECT 01 0000 [.text] __ZN6BltMgr6MemcpyEP9BltDeviceP15_UBM_MEMCPYINFO 000000000009df2c g 0f SECT 01 0000 [.text] __ZN6BltMgr6MemsetEP9BltDeviceP15_UBM_MEMSETINFO 0000000000098b5c g 0f SECT 01 0000 [.text] __ZN6BltMgr7DestroyEv 000000000009b8b2 g 0f SECT 01 0000 [.text] __ZN6BltMgr7GenMipsEP9BltDeviceP16_UBM_GENMIPSINFO 000000000009b050 g 0f SECT 01 0000 [.text] __ZN6BltMgr7StretchEP9BltDeviceP16_UBM_STRETCHINFO 000000000009bfa6 g 0f SECT 01 0000 [.text] __ZN6BltMgr8CompressEP9BltDeviceP17_UBM_COMPRESSINFO 000000000009d46c g 0f SECT 01 0000 [.text] __ZN6BltMgr8GradientEP9BltDeviceP17_UBM_GRADIENTINFO 000000000009c306 g 0f SECT 01 0000 [.text] __ZN6BltMgr9AAResolveEP9BltDeviceP18_UBM_AARESOLVEINFO 000000000009d702 g 0f SECT 01 0000 [.text] __ZN6BltMgr9AATextOutEP9BltDeviceP18_UBM_AATEXTOUTINFO 000000000009dc2e g 0f SECT 01 0000 [.text] __ZN6BltMgr9AddHandleEPvS0_j19_VCOP_RESOURCE_TYPEjj26_UBM_ADDHANDLE_INPUT_FLAGS 0000000000096b08 g 0f SECT 01 0000 [.text] __ZN6BltMgr9GenHisBltEP9BltDevicePK13_UBM_SURFINFO 0000000000098784 g 0f SECT 01 0000 [.text] __ZN6BltMgrC2Ev 0000000000098830 g 0f SECT 01 0000 [.text] __ZN6BltMgrD0Ev 00000000000987fa g 0f SECT 01 0000 [.text] __ZN6BltMgrD1Ev 00000000000987c4 g 0f SECT 01 0000 [.text] __ZN6BltMgrD2Ev 00000000000cdb82 g 0f SECT 01 0000 [.text] __ZN7AddrLib10GetAddrLibEPv 00000000000d040e g 0f SECT 01 0000 [.text] __ZN7AddrLib11Bits2NumberEjz 00000000001a8b10 g 0f SECT 03 0000 [.const] __ZN7AddrLib11m_modeFlagsE 00000000000ce62e g 0f SECT 01 0000 [.text] __ZN7AddrLib12IsMacroTiledE13_AddrTileMode 00000000000d03a8 g 0f SECT 01 0000 [.text] __ZN7AddrLib12IsMicroTiledE13_AddrTileMode 00000000000d03f6 g 0f SECT 01 0000 [.text] __ZN7AddrLib13IsPrtTileModeE13_AddrTileMode 00000000000d038e g 0f SECT 01 0000 [.text] __ZN7AddrLib14IsMacro3dTiledE13_AddrTileMode 00000000000ce648 g 0f SECT 01 0000 [.text] __ZN7AddrLib16ComputeFmaskInfoEPK30_ADDR_COMPUTE_FMASK_INFO_INPUTP31_ADDR_COMPUTE_FMASK_INFO_OUTPUT 00000000000cdb4c g 0f SECT 01 0000 [.text] __ZN7AddrLib17SetAddrChipFamilyEjj 00000000000cdb6e g 0f SECT 01 0000 [.text] __ZN7AddrLib22SetMinPitchAlignPixelsEj 00000000000cdf6a g 0f SECT 01 0000 [.text] __ZN7AddrLib23ComputeSurfaceThicknessE13_AddrTileMode 00000000000d03dc g 0f SECT 01 0000 [.text] __ZN7AddrLib23IsPrtNoRotationTileModeE13_AddrTileMode 00000000000cd8e0 g 0f SECT 01 0000 [.text] __ZN7AddrLib6CreateEPK18_ADDR_CREATE_INPUTP19_ADDR_CREATE_OUTPUT 00000000000d03c2 g 0f SECT 01 0000 [.text] __ZN7AddrLib8IsLinearE13_AddrTileMode 00000000000cd7f0 g 0f SECT 01 0000 [.text] __ZN7AddrLibC2EPK10AddrClient 00000000000cd77c g 0f SECT 01 0000 [.text] __ZN7AddrLibC2Ev 00000000000cd864 g 0f SECT 01 0000 [.text] __ZN7AddrLibD0Ev 00000000000cd880 g 0f SECT 01 0000 [.text] __ZN7AddrLibD1Ev 00000000000cd8b0 g 0f SECT 01 0000 [.text] __ZN7AddrLibD2Ev 00000000000a7b6c g 0f SECT 01 0000 [.text] __ZN7UbmMath10IsInfOrNaNEf 00000000000a7d66 g 0f SECT 01 0000 [.text] __ZN7UbmMath10Log2OfPow2Ej 0000000000146b7c g 0f SECT 03 0000 [.const] __ZN7UbmMath11Float10DescE 0000000000146b44 g 0f SECT 03 0000 [.const] __ZN7UbmMath11Float11DescE 0000000000146b0c g 0f SECT 03 0000 [.const] __ZN7UbmMath11Float16DescE 00000000000a7d88 g 0f SECT 01 0000 [.text] __ZN7UbmMath12ComputeCRC32EPvj 0000000000146b04 g 0f SECT 03 0000 [.const] __ZN7UbmMath13FloatMinusOneE 00000000000a78e2 g 0f SECT 01 0000 [.text] __ZN7UbmMath13FloatToSFixedEfjj16UbmMathRoundMode 00000000000a77dc g 0f SECT 01 0000 [.text] __ZN7UbmMath13FloatToUFixedEfjj16UbmMathRoundMode 00000000000a79f8 g 0f SECT 01 0000 [.text] __ZN7UbmMath13SFixedToFloatEijj 00000000000a7a4e g 0f SECT 01 0000 [.text] __ZN7UbmMath13UFixedToFloatEjjj 00000000000a7ba6 g 0f SECT 01 0000 [.text] __ZN7UbmMath15Float32ToFloatNEfPKNS_13NBitFloatDescE 00000000000a7c8c g 0f SECT 01 0000 [.text] __ZN7UbmMath15FloatNToFloat32EjPKNS_13NBitFloatDescE 00000000000a7ad2 g 0f SECT 01 0000 [.text] __ZN7UbmMath3PowEff 00000000000a7aea g 0f SECT 01 0000 [.text] __ZN7UbmMath3PowEfi 00000000000a7b36 g 0f SECT 01 0000 [.text] __ZN7UbmMath4Pow2Ef 00000000000a7b52 g 0f SECT 01 0000 [.text] __ZN7UbmMath5IsInfEf 00000000000a78b6 g 0f SECT 01 0000 [.text] __ZN7UbmMath5IsNaNEf 00000000000a7aaa g 0f SECT 01 0000 [.text] __ZN7UbmMath7fastExpEf 0000000000146b00 g 0f SECT 03 0000 [.const] __ZN7UbmMath8FloatOneE 0000000000146b08 g 0f SECT 03 0000 [.const] __ZN7UbmMath9FloatZeroE 00000000000a77ca g 0f SECT 01 0000 [.text] __ZN7UbmMathC1Ev 00000000000a77c4 g 0f SECT 01 0000 [.text] __ZN7UbmMathC2Ev 00000000000a77d6 g 0f SECT 01 0000 [.text] __ZN7UbmMathD1Ev 00000000000a77d0 g 0f SECT 01 0000 [.text] __ZN7UbmMathD2Ev 000000000052e0a8 g 0f SECT 0a 0000 [__DATA.__common] __ZN8AMDSIVMM10gMetaClassE 00000000003ab388 g 0f SECT 08 0000 [.const_data] __ZN8AMDSIVMM10superClassE 0000000000066864 g 0f SECT 01 0000 [.text] __ZN8AMDSIVMM12clearWithDMAEyy 000000000006697a g 0f SECT 01 0000 [.text] __ZN8AMDSIVMM17allocateVMContextEv 00000000000667ec g 0f SECT 01 0000 [.text] __ZN8AMDSIVMM25programPageTableRegistersEP19__AMD_VMID_LL_ENTRY 0000000000066762 g 0f SECT 01 0000 [.text] __ZN8AMDSIVMM4initEP30AMDRadeonX4000_IAMDHWInterface 00000000000665d0 g 0f SECT 01 0000 [.text] __ZN8AMDSIVMM9MetaClassC1Ev 0000000000066690 g 0f SECT 01 0000 [.text] __ZN8AMDSIVMM9MetaClassC2Ev 00000000003ab380 g 0f SECT 08 0000 [.const_data] __ZN8AMDSIVMM9metaClassE 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__ZN9BltResFmt17ConvertTo_I8_UINTEPK11_UBM_VECTORjPvj 00000000000a6292 g 0f SECT 01 0000 [.text] __ZN9BltResFmt17ConvertTo_L8_SINTEPK11_UBM_VECTORjPvj 00000000000a6228 g 0f SECT 01 0000 [.text] __ZN9BltResFmt17ConvertTo_L8_UINTEPK11_UBM_VECTORjPvj 00000000000a5368 g 0f SECT 01 0000 [.text] __ZN9BltResFmt17ConvertTo_R8_SINTEPK11_UBM_VECTORjPvj 00000000000a5282 g 0f SECT 01 0000 [.text] __ZN9BltResFmt17ConvertTo_R8_UINTEPK11_UBM_VECTORjPvj 00000000000a6a3c g 0f SECT 01 0000 [.text] __ZN9BltResFmt17YuvMacroPixelSizeE11_UBM_FORMAT 00000000000a5f4a g 0f SECT 01 0000 [.text] __ZN9BltResFmt18ConvertTo_A16_SINTEPK11_UBM_VECTORjPvj 00000000000a5ee0 g 0f SECT 01 0000 [.text] __ZN9BltResFmt18ConvertTo_A16_UINTEPK11_UBM_VECTORjPvj 00000000000a5e7a g 0f SECT 01 0000 [.text] __ZN9BltResFmt18ConvertTo_A32_SINTEPK11_UBM_VECTORjPvj 00000000000a5e14 g 0f SECT 01 0000 [.text] __ZN9BltResFmt18ConvertTo_A32_UINTEPK11_UBM_VECTORjPvj 00000000000a53da g 0f SECT 01 0000 [.text] __ZN9BltResFmt18ConvertTo_A8_UNORMEPK11_UBM_VECTORjPvj 00000000000a6416 g 0f SECT 01 0000 [.text] __ZN9BltResFmt18ConvertTo_I16_SINTEPK11_UBM_VECTORjPvj 00000000000a63b8 g 0f SECT 01 0000 [.text] __ZN9BltResFmt18ConvertTo_I16_UINTEPK11_UBM_VECTORjPvj 00000000000a635a g 0f SECT 01 0000 [.text] __ZN9BltResFmt18ConvertTo_I32_SINTEPK11_UBM_VECTORjPvj 00000000000a62fc g 0f SECT 01 0000 [.text] __ZN9BltResFmt18ConvertTo_I32_UINTEPK11_UBM_VECTORjPvj 00000000000a61be g 0f SECT 01 0000 [.text] __ZN9BltResFmt18ConvertTo_L16_SINTEPK11_UBM_VECTORjPvj 00000000000a6154 g 0f SECT 01 0000 [.text] __ZN9BltResFmt18ConvertTo_L16_UINTEPK11_UBM_VECTORjPvj 00000000000a60ec g 0f SECT 01 0000 [.text] __ZN9BltResFmt18ConvertTo_L32_SINTEPK11_UBM_VECTORjPvj 00000000000a6084 g 0f SECT 01 0000 [.text] __ZN9BltResFmt18ConvertTo_L32_UINTEPK11_UBM_VECTORjPvj 00000000000a519c g 0f SECT 01 0000 [.text] __ZN9BltResFmt18ConvertTo_R16_SINTEPK11_UBM_VECTORjPvj 00000000000a50b4 g 0f SECT 01 0000 [.text] __ZN9BltResFmt18ConvertTo_R16_UINTEPK11_UBM_VECTORjPvj 00000000000a5446 g 0f SECT 01 0000 [.text] __ZN9BltResFmt18ConvertTo_R1_UNORMEPK11_UBM_VECTORjPvj 00000000000a4ab0 g 0f SECT 01 0000 [.text] __ZN9BltResFmt18ConvertTo_R32_SINTEPK11_UBM_VECTORjPvj 00000000000a4a3e g 0f SECT 01 0000 [.text] __ZN9BltResFmt18ConvertTo_R32_UINTEPK11_UBM_VECTORjPvj 00000000000a52f4 g 0f SECT 01 0000 [.text] __ZN9BltResFmt18ConvertTo_R8_SNORMEPK11_UBM_VECTORjPvj 00000000000a520e g 0f SECT 01 0000 [.text] __ZN9BltResFmt18ConvertTo_R8_UNORMEPK11_UBM_VECTORjPvj 00000000000a6046 g 0f SECT 01 0000 [.text] __ZN9BltResFmt19ConvertFrom_A8_SINTEPKvjP11_UBM_VECTOR 00000000000a5fde g 0f SECT 01 0000 [.text] __ZN9BltResFmt19ConvertFrom_A8_UINTEPKvjP11_UBM_VECTOR 00000000000a64fe g 0f SECT 01 0000 [.text] __ZN9BltResFmt19ConvertFrom_I8_SINTEPKvjP11_UBM_VECTOR 00000000000a64a0 g 0f SECT 01 0000 [.text] __ZN9BltResFmt19ConvertFrom_I8_UINTEPKvjP11_UBM_VECTOR 00000000000a62be g 0f SECT 01 0000 [.text] __ZN9BltResFmt19ConvertFrom_L8_SINTEPKvjP11_UBM_VECTOR 00000000000a6254 g 0f SECT 01 0000 [.text] __ZN9BltResFmt19ConvertFrom_L8_UINTEPKvjP11_UBM_VECTOR 00000000000a5392 g 0f SECT 01 0000 [.text] __ZN9BltResFmt19ConvertFrom_R8_SINTEPKvjP11_UBM_VECTOR 00000000000a52ac g 0f SECT 01 0000 [.text] __ZN9BltResFmt19ConvertFrom_R8_UINTEPKvjP11_UBM_VECTOR 00000000000a6846 g 0f SECT 01 0000 [.text] __ZN9BltResFmt19ConvertTo_L8A8_SINTEPK11_UBM_VECTORjPvj 00000000000a67a8 g 0f SECT 01 0000 [.text] __ZN9BltResFmt19ConvertTo_L8A8_UINTEPK11_UBM_VECTORjPvj 00000000000a4fce g 0f SECT 01 0000 [.text] __ZN9BltResFmt19ConvertTo_R16_FLOATEPK11_UBM_VECTORjPvj 00000000000a5126 g 0f SECT 01 0000 [.text] __ZN9BltResFmt19ConvertTo_R16_SNORMEPK11_UBM_VECTORjPvj 00000000000a503e g 0f SECT 01 0000 [.text] __ZN9BltResFmt19ConvertTo_R16_UNORMEPK11_UBM_VECTORjPvj 00000000000a49f6 g 0f SECT 01 0000 [.text] __ZN9BltResFmt19ConvertTo_R32_FLOATEPK11_UBM_VECTORjPvj 00000000000a4f1c g 0f SECT 01 0000 [.text] __ZN9BltResFmt19ConvertTo_R8G8_SINTEPK11_UBM_VECTORjPvj 00000000000a4db2 g 0f SECT 01 0000 [.text] __ZN9BltResFmt19ConvertTo_R8G8_UINTEPK11_UBM_VECTORjPvj 00000000000a5f76 g 0f SECT 01 0000 [.text] __ZN9BltResFmt20ConvertFrom_A16_SINTEPKvjP11_UBM_VECTOR 00000000000a5f0c g 0f SECT 01 0000 [.text] __ZN9BltResFmt20ConvertFrom_A16_UINTEPKvjP11_UBM_VECTOR 00000000000a5ea4 g 0f SECT 01 0000 [.text] __ZN9BltResFmt20ConvertFrom_A32_SINTEPKvjP11_UBM_VECTOR 00000000000a5e3e g 0f SECT 01 0000 [.text] __ZN9BltResFmt20ConvertFrom_A32_UINTEPKvjP11_UBM_VECTOR 00000000000a5408 g 0f SECT 01 0000 [.text] __ZN9BltResFmt20ConvertFrom_A8_UNORMEPKvjP11_UBM_VECTOR 00000000000a6442 g 0f SECT 01 0000 [.text] __ZN9BltResFmt20ConvertFrom_I16_SINTEPKvjP11_UBM_VECTOR 00000000000a63e4 g 0f SECT 01 0000 [.text] __ZN9BltResFmt20ConvertFrom_I16_UINTEPKvjP11_UBM_VECTOR 00000000000a6386 g 0f SECT 01 0000 [.text] __ZN9BltResFmt20ConvertFrom_I32_SINTEPKvjP11_UBM_VECTOR 00000000000a6328 g 0f SECT 01 0000 [.text] __ZN9BltResFmt20ConvertFrom_I32_UINTEPKvjP11_UBM_VECTOR 00000000000a61ea g 0f SECT 01 0000 [.text] __ZN9BltResFmt20ConvertFrom_L16_SINTEPKvjP11_UBM_VECTOR 00000000000a6180 g 0f SECT 01 0000 [.text] __ZN9BltResFmt20ConvertFrom_L16_UINTEPKvjP11_UBM_VECTOR 00000000000a6118 g 0f SECT 01 0000 [.text] __ZN9BltResFmt20ConvertFrom_L32_SINTEPKvjP11_UBM_VECTOR 00000000000a60b0 g 0f SECT 01 0000 [.text] __ZN9BltResFmt20ConvertFrom_L32_UINTEPKvjP11_UBM_VECTOR 00000000000a5db2 g 0f SECT 01 0000 [.text] __ZN9BltResFmt20ConvertFrom_L8_UNORMEPKvjP11_UBM_VECTOR 00000000000a51c6 g 0f SECT 01 0000 [.text] __ZN9BltResFmt20ConvertFrom_R16_SINTEPKvjP11_UBM_VECTOR 00000000000a50de g 0f SECT 01 0000 [.text] __ZN9BltResFmt20ConvertFrom_R16_UINTEPKvjP11_UBM_VECTOR 00000000000a5482 g 0f SECT 01 0000 [.text] __ZN9BltResFmt20ConvertFrom_R1_UNORMEPKvjP11_UBM_VECTOR 00000000000a4ada g 0f SECT 01 0000 [.text] __ZN9BltResFmt20ConvertFrom_R32_SINTEPKvjP11_UBM_VECTOR 00000000000a4a68 g 0f SECT 01 0000 [.text] __ZN9BltResFmt20ConvertFrom_R32_UINTEPKvjP11_UBM_VECTOR 00000000000a5320 g 0f SECT 01 0000 [.text] __ZN9BltResFmt20ConvertFrom_R8_SNORMEPKvjP11_UBM_VECTOR 00000000000a523a g 0f SECT 01 0000 [.text] __ZN9BltResFmt20ConvertFrom_R8_UNORMEPKvjP11_UBM_VECTOR 00000000000a4e64 g 0f SECT 01 0000 [.text] __ZN9BltResFmt20ConvertTo_R8G8_SNORMEPK11_UBM_VECTORjPvj 00000000000a4cfa g 0f SECT 01 0000 [.text] __ZN9BltResFmt20ConvertTo_R8G8_UNORMEPK11_UBM_VECTORjPvj 00000000000a689e g 0f SECT 01 0000 [.text] __ZN9BltResFmt21ConvertFrom_L8A8_SINTEPKvjP11_UBM_VECTOR 00000000000a6800 g 0f SECT 01 0000 [.text] __ZN9BltResFmt21ConvertFrom_L8A8_UINTEPKvjP11_UBM_VECTOR 00000000000a4ff6 g 0f SECT 01 0000 [.text] __ZN9BltResFmt21ConvertFrom_R16_FLOATEPKvjP11_UBM_VECTOR 00000000000a5154 g 0f SECT 01 0000 [.text] __ZN9BltResFmt21ConvertFrom_R16_SNORMEPKvjP11_UBM_VECTOR 00000000000a506c g 0f SECT 01 0000 [.text] __ZN9BltResFmt21ConvertFrom_R16_UNORMEPKvjP11_UBM_VECTOR 00000000000a4a0a g 0f SECT 01 0000 [.text] __ZN9BltResFmt21ConvertFrom_R32_FLOATEPKvjP11_UBM_VECTOR 00000000000a4f72 g 0f SECT 01 0000 [.text] __ZN9BltResFmt21ConvertFrom_R8G8_SINTEPKvjP11_UBM_VECTOR 00000000000a4e08 g 0f SECT 01 0000 [.text] __ZN9BltResFmt21ConvertFrom_R8G8_UINTEPKvjP11_UBM_VECTOR 00000000000a6708 g 0f SECT 01 0000 [.text] __ZN9BltResFmt21ConvertTo_L16A16_SINTEPK11_UBM_VECTORjPvj 00000000000a6668 g 0f SECT 01 0000 [.text] __ZN9BltResFmt21ConvertTo_L16A16_UINTEPK11_UBM_VECTORjPvj 00000000000a65cc g 0f SECT 01 0000 [.text] __ZN9BltResFmt21ConvertTo_L32A32_SINTEPK11_UBM_VECTORjPvj 00000000000a6530 g 0f SECT 01 0000 [.text] __ZN9BltResFmt21ConvertTo_L32A32_UINTEPK11_UBM_VECTORjPvj 00000000000a4942 g 0f SECT 01 0000 [.text] __ZN9BltResFmt21ConvertTo_R16G16_SINTEPK11_UBM_VECTORjPvj 00000000000a47d4 g 0f SECT 01 0000 [.text] __ZN9BltResFmt21ConvertTo_R16G16_UINTEPK11_UBM_VECTORjPvj 00000000000a39ac g 0f SECT 01 0000 [.text] __ZN9BltResFmt21ConvertTo_R32G32_SINTEPK11_UBM_VECTORjPvj 00000000000a38fc g 0f SECT 01 0000 [.text] __ZN9BltResFmt21ConvertTo_R32G32_UINTEPK11_UBM_VECTORjPvj 00000000000a6a16 g 0f SECT 01 0000 [.text] __ZN9BltResFmt21IsYuvMacroPixelFormatE11_UBM_FORMAT 00000000000a4ec0 g 0f SECT 01 0000 [.text] __ZN9BltResFmt22ConvertFrom_R8G8_SNORMEPKvjP11_UBM_VECTOR 00000000000a4d56 g 0f SECT 01 0000 [.text] __ZN9BltResFmt22ConvertFrom_R8G8_UNORMEPKvjP11_UBM_VECTOR 00000000000a5586 g 0f SECT 01 0000 [.text] __ZN9BltResFmt22ConvertTo_B5G6R5_UNORMEPK11_UBM_VECTORjPvj 00000000000a4662 g 0f SECT 01 0000 [.text] __ZN9BltResFmt22ConvertTo_R16G16_FLOATEPK11_UBM_VECTORjPvj 00000000000a4888 g 0f SECT 01 0000 [.text] __ZN9BltResFmt22ConvertTo_R16G16_SNORMEPK11_UBM_VECTORjPvj 00000000000a471a g 0f SECT 01 0000 [.text] __ZN9BltResFmt22ConvertTo_R16G16_UNORMEPK11_UBM_VECTORjPvj 00000000000a38a2 g 0f SECT 01 0000 [.text] __ZN9BltResFmt22ConvertTo_R32G32_FLOATEPK11_UBM_VECTORjPvj 00000000000a6762 g 0f SECT 01 0000 [.text] __ZN9BltResFmt23ConvertFrom_L16A16_SINTEPKvjP11_UBM_VECTOR 00000000000a66c2 g 0f SECT 01 0000 [.text] __ZN9BltResFmt23ConvertFrom_L16A16_UINTEPKvjP11_UBM_VECTOR 00000000000a6624 g 0f SECT 01 0000 [.text] __ZN9BltResFmt23ConvertFrom_L32A32_SINTEPKvjP11_UBM_VECTOR 00000000000a6588 g 0f SECT 01 0000 [.text] __ZN9BltResFmt23ConvertFrom_L32A32_UINTEPKvjP11_UBM_VECTOR 00000000000a499a g 0f SECT 01 0000 [.text] __ZN9BltResFmt23ConvertFrom_R16G16_SINTEPKvjP11_UBM_VECTOR 00000000000a482c g 0f SECT 01 0000 [.text] __ZN9BltResFmt23ConvertFrom_R16G16_UINTEPKvjP11_UBM_VECTOR 00000000000a3a02 g 0f SECT 01 0000 [.text] __ZN9BltResFmt23ConvertFrom_R32G32_SINTEPKvjP11_UBM_VECTOR 00000000000a3952 g 0f SECT 01 0000 [.text] __ZN9BltResFmt23ConvertFrom_R32G32_UINTEPKvjP11_UBM_VECTOR 00000000000a456a g 0f SECT 01 0000 [.text] __ZN9BltResFmt23ConvertTo_R8G8B8A8_SINTEPK11_UBM_VECTORjPvj 00000000000a436e g 0f SECT 01 0000 [.text] __ZN9BltResFmt23ConvertTo_R8G8B8A8_UINTEPK11_UBM_VECTORjPvj 00000000000a5644 g 0f SECT 01 0000 [.text] __ZN9BltResFmt24ConvertFrom_B5G6R5_UNORMEPKvjP11_UBM_VECTOR 00000000000a46b6 g 0f SECT 01 0000 [.text] __ZN9BltResFmt24ConvertFrom_R16G16_FLOATEPKvjP11_UBM_VECTOR 00000000000a48e6 g 0f SECT 01 0000 [.text] __ZN9BltResFmt24ConvertFrom_R16G16_SNORMEPKvjP11_UBM_VECTOR 00000000000a4778 g 0f SECT 01 0000 [.text] __ZN9BltResFmt24ConvertFrom_R16G16_UNORMEPKvjP11_UBM_VECTOR 00000000000a38c4 g 0f SECT 01 0000 [.text] __ZN9BltResFmt24ConvertFrom_R32G32_FLOATEPKvjP11_UBM_VECTOR 00000000000a5ba6 g 0f SECT 01 0000 [.text] __ZN9BltResFmt24ConvertTo_A8B8G8R8_UNORMEPK11_UBM_VECTORjPvj 00000000000a5a30 g 0f SECT 01 0000 [.text] __ZN9BltResFmt24ConvertTo_B4G4R4A4_UNORMEPK11_UBM_VECTORjPvj 00000000000a56bc g 0f SECT 01 0000 [.text] __ZN9BltResFmt24ConvertTo_B5G5R5A1_UNORMEPK11_UBM_VECTORjPvj 00000000000a592c g 0f SECT 01 0000 [.text] __ZN9BltResFmt24ConvertTo_B8G8R8A8_SNORMEPK11_UBM_VECTORjPvj 00000000000a5828 g 0f SECT 01 0000 [.text] __ZN9BltResFmt24ConvertTo_B8G8R8A8_UNORMEPK11_UBM_VECTORjPvj 00000000000a32d4 g 0f SECT 01 0000 [.text] __ZN9BltResFmt24ConvertTo_R32G32B32_SINTEPK11_UBM_VECTORjPvj 00000000000a3202 g 0f SECT 01 0000 [.text] __ZN9BltResFmt24ConvertTo_R32G32B32_UINTEPK11_UBM_VECTORjPvj 00000000000a4466 g 0f SECT 01 0000 [.text] __ZN9BltResFmt24ConvertTo_R8G8B8A8_SNORMEPK11_UBM_VECTORjPvj 00000000000a426a g 0f SECT 01 0000 [.text] __ZN9BltResFmt24ConvertTo_R8G8B8A8_UNORMEPK11_UBM_VECTORjPvj 00000000000a45fa g 0f SECT 01 0000 [.text] __ZN9BltResFmt25ConvertFrom_R8G8B8A8_SINTEPKvjP11_UBM_VECTOR 00000000000a43fe g 0f SECT 01 0000 [.text] __ZN9BltResFmt25ConvertFrom_R8G8B8A8_UINTEPKvjP11_UBM_VECTOR 00000000000a414e g 0f SECT 01 0000 [.text] __ZN9BltResFmt25ConvertTo_R11G11B10_FLOATEPK11_UBM_VECTORjPvj 00000000000a319c g 0f SECT 01 0000 [.text] __ZN9BltResFmt25ConvertTo_R32G32B32_FLOATEPK11_UBM_VECTORjPvj 00000000000a5c42 g 0f SECT 01 0000 [.text] __ZN9BltResFmt26ConvertFrom_A8B8G8R8_UNORMEPKvjP11_UBM_VECTOR 00000000000a5b1e g 0f SECT 01 0000 [.text] __ZN9BltResFmt26ConvertFrom_B4G4R4A4_UNORMEPKvjP11_UBM_VECTOR 00000000000a579c g 0f SECT 01 0000 [.text] __ZN9BltResFmt26ConvertFrom_B5G5R5A1_UNORMEPKvjP11_UBM_VECTOR 00000000000a59c8 g 0f SECT 01 0000 [.text] __ZN9BltResFmt26ConvertFrom_B8G8R8A8_SNORMEPKvjP11_UBM_VECTOR 00000000000a58c4 g 0f SECT 01 0000 [.text] __ZN9BltResFmt26ConvertFrom_B8G8R8A8_UNORMEPKvjP11_UBM_VECTOR 00000000000a3346 g 0f SECT 01 0000 [.text] __ZN9BltResFmt26ConvertFrom_R32G32B32_SINTEPKvjP11_UBM_VECTOR 00000000000a3274 g 0f SECT 01 0000 [.text] __ZN9BltResFmt26ConvertFrom_R32G32B32_UINTEPKvjP11_UBM_VECTOR 00000000000a4502 g 0f SECT 01 0000 [.text] __ZN9BltResFmt26ConvertFrom_R8G8B8A8_SNORMEPKvjP11_UBM_VECTOR 00000000000a4306 g 0f SECT 01 0000 [.text] __ZN9BltResFmt26ConvertFrom_R8G8B8A8_UNORMEPKvjP11_UBM_VECTOR 00000000000a3ca2 g 0f SECT 01 0000 [.text] __ZN9BltResFmt26ConvertTo_R10G10B10A2_UINTEPK11_UBM_VECTORjPvj 00000000000a41f6 g 0f SECT 01 0000 [.text] __ZN9BltResFmt27ConvertFrom_R11G11B10_FLOATEPKvjP11_UBM_VECTOR 00000000000a31ce g 0f SECT 01 0000 [.text] __ZN9BltResFmt27ConvertFrom_R32G32B32_FLOATEPKvjP11_UBM_VECTOR 00000000000a4062 g 0f SECT 01 0000 [.text] __ZN9BltResFmt27ConvertTo_A2B10G10R10_UNORMEPK11_UBM_VECTORjPvj 00000000000a3f76 g 0f SECT 01 0000 [.text] __ZN9BltResFmt27ConvertTo_A2R10G10B10_UNORMEPK11_UBM_VECTORjPvj 00000000000a3dfc g 0f SECT 01 0000 [.text] __ZN9BltResFmt27ConvertTo_B10G10R10A2_UNORMEPK11_UBM_VECTORjPvj 00000000000a4ba6 g 0f SECT 01 0000 [.text] __ZN9BltResFmt27ConvertTo_D24_UNORM_S8_UINTEPK11_UBM_VECTORjPvj 00000000000a3b28 g 0f SECT 01 0000 [.text] __ZN9BltResFmt27ConvertTo_R10G10B10A2_UNORMEPK11_UBM_VECTORjPvj 00000000000a37a6 g 0f SECT 01 0000 [.text] __ZN9BltResFmt27ConvertTo_R16G16B16A16_SINTEPK11_UBM_VECTORjPvj 00000000000a35a2 g 0f SECT 01 0000 [.text] __ZN9BltResFmt27ConvertTo_R16G16B16A16_UINTEPK11_UBM_VECTORjPvj 00000000000a30a8 g 0f SECT 01 0000 [.text] __ZN9BltResFmt27ConvertTo_R32G32B32A32_SINTEPK11_UBM_VECTORjPvj 00000000000a2fb4 g 0f SECT 01 0000 [.text] __ZN9BltResFmt27ConvertTo_R32G32B32A32_UINTEPK11_UBM_VECTORjPvj 00000000000a3d80 g 0f SECT 01 0000 [.text] __ZN9BltResFmt28ConvertFrom_R10G10B10A2_UINTEPKvjP11_UBM_VECTOR 00000000000a5caa g 0f SECT 01 0000 [.text] __ZN9BltResFmt28ConvertTo_B16G16R16A16_SNORMEPK11_UBM_VECTORjPvj 00000000000a33a6 g 0f SECT 01 0000 [.text] __ZN9BltResFmt28ConvertTo_R16G16B16A16_FLOATEPK11_UBM_VECTORjPvj 00000000000a369e g 0f SECT 01 0000 [.text] __ZN9BltResFmt28ConvertTo_R16G16B16A16_SNORMEPK11_UBM_VECTORjPvj 00000000000a349a g 0f SECT 01 0000 [.text] __ZN9BltResFmt28ConvertTo_R16G16B16A16_UNORMEPK11_UBM_VECTORjPvj 00000000000a2f58 g 0f SECT 01 0000 [.text] __ZN9BltResFmt28ConvertTo_R32G32B32A32_FLOATEPK11_UBM_VECTORjPvj 00000000000a3ee6 g 0f SECT 01 0000 [.text] __ZN9BltResFmt29ConvertFrom_B10G10R10A2_UNORMEPKvjP11_UBM_VECTOR 00000000000a4c1e g 0f SECT 01 0000 [.text] __ZN9BltResFmt29ConvertFrom_D24_UNORM_S8_UINTEPKvjP11_UBM_VECTOR 00000000000a3c12 g 0f SECT 01 0000 [.text] __ZN9BltResFmt29ConvertFrom_R10G10B10A2_UNORMEPKvjP11_UBM_VECTOR 00000000000a383a g 0f SECT 01 0000 [.text] __ZN9BltResFmt29ConvertFrom_R16G16B16A16_SINTEPKvjP11_UBM_VECTOR 00000000000a3636 g 0f SECT 01 0000 [.text] __ZN9BltResFmt29ConvertFrom_R16G16B16A16_UINTEPKvjP11_UBM_VECTOR 00000000000a3138 g 0f SECT 01 0000 [.text] __ZN9BltResFmt29ConvertFrom_R32G32B32A32_SINTEPKvjP11_UBM_VECTOR 00000000000a3044 g 0f SECT 01 0000 [.text] __ZN9BltResFmt29ConvertFrom_R32G32B32A32_UINTEPKvjP11_UBM_VECTOR 00000000000a5d4a g 0f SECT 01 0000 [.text] __ZN9BltResFmt30ConvertFrom_B16G16R16A16_SNORMEPKvjP11_UBM_VECTOR 00000000000a3432 g 0f SECT 01 0000 [.text] __ZN9BltResFmt30ConvertFrom_R16G16B16A16_FLOATEPKvjP11_UBM_VECTOR 00000000000a373e g 0f SECT 01 0000 [.text] __ZN9BltResFmt30ConvertFrom_R16G16B16A16_SNORMEPKvjP11_UBM_VECTOR 00000000000a353a g 0f SECT 01 0000 [.text] __ZN9BltResFmt30ConvertFrom_R16G16B16A16_UNORMEPKvjP11_UBM_VECTOR 00000000000a2f98 g 0f SECT 01 0000 [.text] __ZN9BltResFmt30ConvertFrom_R32G32B32A32_FLOATEPKvjP11_UBM_VECTOR 00000000000a54c0 g 0f SECT 01 0000 [.text] __ZN9BltResFmt30ConvertFrom_R9G9B9E5_SHAREDEXPEPKvjP11_UBM_VECTOR 00000000000a3a5c g 0f SECT 01 0000 [.text] __ZN9BltResFmt30ConvertTo_D32_FLOAT_S8X24_UINTEPK11_UBM_VECTORjPvj 00000000000a4b22 g 0f SECT 01 0000 [.text] __ZN9BltResFmt30ConvertTo_X24_TYPELESS_G8_UINTEPK11_UBM_VECTORjPvj 00000000000a4c80 g 0f SECT 01 0000 [.text] __ZN9BltResFmt31ConvertTo_D24_UNORM_X8_TYPELESSEPK11_UBM_VECTORjPvj 00000000000a712c g 0f SECT 01 0000 [.text] __ZN9BltResFmt31ConvertTo_R24_UNORM_X8_TYPELESSEPK11_UBM_VECTORjPvj 00000000000a3aa4 g 0f SECT 01 0000 [.text] __ZN9BltResFmt32ConvertFrom_D32_FLOAT_S8X24_UINTEPKvjP11_UBM_VECTOR 00000000000a4b52 g 0f SECT 01 0000 [.text] __ZN9BltResFmt32ConvertFrom_X24_TYPELESS_G8_UINTEPKvjP11_UBM_VECTOR 00000000000a4cac g 0f SECT 01 0000 [.text] __ZN9BltResFmt33ConvertFrom_D24_UNORM_X8_TYPELESSEPKvjP11_UBM_VECTOR 00000000000a718c g 0f SECT 01 0000 [.text] __ZN9BltResFmt33ConvertFrom_R24_UNORM_X8_TYPELESSEPKvjP11_UBM_VECTOR 00000000000a3af8 g 0f SECT 01 0000 [.text] __ZN9BltResFmt33ConvertTo_X32_TYPELESS_G8X24_UINTEPK11_UBM_VECTORjPvj 00000000000a7158 g 0f SECT 01 0000 [.text] __ZN9BltResFmt36ConvertFrom_R32_FLOAT_X8X24_TYPELESSEPKvjP11_UBM_VECTOR 00000000000a009c g 0f SECT 01 0000 [.text] __ZN9BltResFmt4InitE32UBM_FORMAT_MISSING_COMP_DEFAULTS 00000000000a2f44 g 0f SECT 01 0000 [.text] __ZN9BltResFmt5IsYuvE11_UBM_FORMAT 00000000000a0064 g 0f SECT 01 0000 [.text] __ZN9BltResFmt6CreateEPK15_UBM_CREATEINFO 00000000000a2e40 g 0f SECT 01 0000 [.text] __ZN9BltResFmt7DestroyEv 00000000000a6974 g 0f SECT 01 0000 [.text] __ZN9BltResFmt8HasAlphaE11_UBM_FORMAT 00000000000a6900 g 0f SECT 01 0000 [.text] __ZN9BltResFmt8HasDepthE11_UBM_FORMAT 00000000000a0014 g 0f SECT 01 0000 [.text] __ZN9BltResFmtC1Ev 000000000009fff4 g 0f SECT 01 0000 [.text] __ZN9BltResFmtC2Ev 00000000000a0048 g 0f SECT 01 0000 [.text] __ZN9BltResFmtD0Ev 00000000000a003e g 0f SECT 01 0000 [.text] __ZN9BltResFmtD1Ev 00000000000a0034 g 0f SECT 01 0000 [.text] __ZN9BltResFmtD2Ev 00000000000a7282 g 0f SECT 01 0000 [.text] __ZN9BltShader17SetBltShaderInputEPK14BltShaderInput 00000000000a72b0 g 0f SECT 01 0000 [.text] __ZN9BltShader7CpuLoadEPv13LARGE_INTEGERPh 00000000000a722e g 0f SECT 01 0000 [.text] __ZN9BltShaderC1Ev 00000000000a71da g 0f SECT 01 0000 [.text] __ZN9BltShaderC2Ev 00000000000d644c g 0f SECT 01 0000 [.text] __ZN9CIAddrLib19HwlComputeFmaskInfoEPK30_ADDR_COMPUTE_FMASK_INFO_INPUTP31_ADDR_COMPUTE_FMASK_INFO_OUTPUT 00000000000d6004 g 0f SECT 01 0000 [.text] __ZN9CIAddrLib19HwlInitGlobalParamsEPK18_ADDR_CREATE_INPUT 00000000000d5efe g 0f SECT 01 0000 [.text] __ZN9CIAddrLib20HwlConvertChipFamilyEjj 00000000000d60a2 g 0f SECT 01 0000 [.text] __ZN9CIAddrLib20InitTileSettingTableEPKjj 00000000000d6156 g 0f SECT 01 0000 [.text] __ZN9CIAddrLib21InitMacroTileCfgTableEPKjj 00000000000d5a5e g 0f SECT 01 0000 [.text] __ZN9CIAddrLibC1EPK10AddrClient 00000000000d5aae g 0f SECT 01 0000 [.text] __ZN9CIAddrLibC2EPK10AddrClient 00000000000d5afe g 0f SECT 01 0000 [.text] __ZN9CIAddrLibD0Ev 00000000000d5b1a g 0f SECT 01 0000 [.text] __ZN9CIAddrLibD1Ev 00000000000d5b24 g 0f SECT 01 0000 [.text] __ZN9CIAddrLibD2Ev 00000000000d4e2a g 0f SECT 01 0000 [.text] __ZN9SIAddrLib12DecodeGbRegsEPK20_ADDR_REGISTER_VALUE 00000000000d4eee g 0f SECT 01 0000 [.text] __ZN9SIAddrLib19HwlInitGlobalParamsEPK18_ADDR_CREATE_INPUT 00000000000d4946 g 0f SECT 01 0000 [.text] __ZN9SIAddrLib20HwlConvertChipFamilyEjj 00000000000d4f50 g 0f SECT 01 0000 [.text] __ZN9SIAddrLib20InitTileSettingTableEPKjj 00000000000d34f8 g 0f SECT 01 0000 [.text] __ZN9SIAddrLibC1EPK10AddrClient 00000000000d353e g 0f SECT 01 0000 [.text] __ZN9SIAddrLibC2EPK10AddrClient 00000000000d3584 g 0f SECT 01 0000 [.text] __ZN9SIAddrLibD0Ev 00000000000d35a0 g 0f SECT 01 0000 [.text] __ZN9SIAddrLibD1Ev 00000000000d35aa g 0f SECT 01 0000 [.text] __ZN9SIAddrLibD2Ev 000000000052eca0 g 0f SECT 0a 0000 [__DATA.__common] __ZN9UbmObject12m_freeSysMemE 000000000052ec98 g 0f SECT 0a 0000 [__DATA.__common] __ZN9UbmObject13m_allocSysMemE 00000000000a7e78 g 0f SECT 01 0000 [.text] __ZN9UbmObject16SetupSysMemFuncsEPFPvPK22_UBM_ALLOCSYSMEM_INPUTEPF17_UBM_E_RETURNCODES0_E 00000000000a7dde g 0f SECT 01 0000 [.text] __ZN9UbmObjectC1Ev 00000000000a7dd8 g 0f SECT 01 0000 [.text] __ZN9UbmObjectC2Ev 00000000000a7dea g 0f SECT 01 0000 [.text] __ZN9UbmObjectD1Ev 00000000000a7de4 g 0f SECT 01 0000 [.text] __ZN9UbmObjectD2Ev 00000000000a7e62 g 0f SECT 01 0000 [.text] __ZN9UbmObjectdaEPv 00000000000a7e1e g 0f SECT 01 0000 [.text] __ZN9UbmObjectdlEPv 00000000000a7e34 g 0f SECT 01 0000 [.text] __ZN9UbmObjectnaEm 00000000000a7df0 g 0f SECT 01 0000 [.text] __ZN9UbmObjectnwEm 00000000000cd616 g 0f SECT 01 0000 [.text] __ZNK10AddrObject10AddrMallocEm 00000000000cd75c g 0f SECT 01 0000 [.text] __ZNK10AddrObject10DebugPrintEPKcz 00000000000cd69a g 0f SECT 01 0000 [.text] __ZNK10AddrObject8AddrFreeEPv 00000000000871d2 g 0f SECT 01 0000 [.text] __ZNK11AMDVIHWGart12getMetaClassEv 0000000000087212 g 0f SECT 01 0000 [.text] __ZNK11AMDVIHWGart9MetaClass5allocEv 00000000000d16ca g 0f SECT 01 0000 [.text] __ZNK11AddrElemLib16PixGetExportNormE16_AddrColorFormat18_AddrSurfaceNumber16_AddrSurfaceSwap 00000000000d0e9c g 0f SECT 01 0000 [.text] __ZNK11AddrElemLib17Flt32ToColorPixelE16_AddrColorFormat18_AddrSurfaceNumber16_AddrSurfaceSwapPK11ADDR_FLT_32Pa 00000000000d0c06 g 0f SECT 01 0000 [.text] __ZNK11AddrElemLib17Flt32ToDepthPixelE16_AddrDepthFormatPK11ADDR_FLT_32Pa 00000000000d0fe6 g 0f SECT 01 0000 [.text] __ZNK11AddrElemLib19PixGetColorCompInfoE16_AddrColorFormat18_AddrSurfaceNumber16_AddrSurfaceSwapP21ADDR_PIXEL_FORMATINFO 00000000000d0d00 g 0f SECT 01 0000 [.text] __ZNK11AddrElemLib19PixGetDepthCompInfoE16_AddrDepthFormatP21ADDR_PIXEL_FORMATINFO 00000000000d284a g 0f SECT 01 0000 [.text] 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01 0000 [.text] __ZNK11R800AddrLib24HwlSanityCheckMacroTiledEP14_ADDR_TILEINFO 00000000000d3090 g 0f SECT 01 0000 [.text] __ZNK11R800AddrLib25HwlCheckLastMacroTiledLvlEPK32_ADDR_COMPUTE_SURFACE_INFO_INPUTP33_ADDR_COMPUTE_SURFACE_INFO_OUTPUT 00000000000d3028 g 0f SECT 01 0000 [.text] __ZNK11R800AddrLib26HwlGetPitchAlignmentLinearEj19_ADDR_SURFACE_FLAGS 00000000000d3048 g 0f SECT 01 0000 [.text] __ZNK11R800AddrLib26HwlGetSizeAdjustmentLinearE13_AddrTileModejjjjPjS1_S1_ 00000000000d1c42 g 0f SECT 01 0000 [.text] __ZNK11R800AddrLib27ComputeSurfaceInfoPowerSaveEPK32_ADDR_COMPUTE_SURFACE_INFO_INPUTP33_ADDR_COMPUTE_SURFACE_INFO_OUTPUT 00000000000d1d2a g 0f SECT 01 0000 [.text] __ZNK11R800AddrLib30HwlComputeSurfaceAddrFromCoordEPK41_ADDR_COMPUTE_SURFACE_ADDRFROMCOORD_INPUTP42_ADDR_COMPUTE_SURFACE_ADDRFROMCOORD_OUTPUT 00000000000d1eec g 0f SECT 01 0000 [.text] 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SECT 01 0000 [.text] __ZNK11SiBltResFmt12AlphaIsOnMSBE11_UBM_FORMAT 00000000000bcefa g 0f SECT 01 0000 [.text] __ZNK11SiBltResFmt12GetRoundModeE11_UBM_FORMAT 00000000000bcf36 g 0f SECT 01 0000 [.text] __ZNK11SiBltResFmt12SupportGammaE11_UBM_FORMAT 00000000000bceae g 0f SECT 01 0000 [.text] __ZNK11SiBltResFmt13GetBlendClampE11_UBM_FORMAT 00000000000bc35c g 0f SECT 01 0000 [.text] __ZNK11SiBltResFmt13GetHwColorFmtE11_UBM_FORMATj 00000000000bcc8e g 0f SECT 01 0000 [.text] __ZNK11SiBltResFmt13GetNumberTypeE11_UBM_FORMAT 00000000000bce2a g 0f SECT 01 0000 [.text] __ZNK11SiBltResFmt14GetBlendBypassE11_UBM_FORMAT 00000000000bcfe8 g 0f SECT 01 0000 [.text] __ZNK11SiBltResFmt14GetCompSettingE11ColorFormat11SurfaceSwap 00000000000bcc62 g 0f SECT 01 0000 [.text] __ZNK11SiBltResFmt14GetHwBufNumFmtE11_UBM_FORMAT 00000000000bcc14 g 0f SECT 01 0000 [.text] __ZNK11SiBltResFmt14GetHwImgNumFmtE11_UBM_FORMAT 00000000000bccba g 0f SECT 01 0000 [.text] __ZNK11SiBltResFmt14GetSurfaceSwapE11_UBM_FORMATj 00000000000bd5de g 0f SECT 01 0000 [.text] __ZNK11SiBltResFmt15GetCompBitCountE11_UBM_FORMATjj 00000000000bcc40 g 0f SECT 01 0000 [.text] __ZNK11SiBltResFmt15GetHwBufDataFmtE11_UBM_FORMAT 00000000000bc340 g 0f SECT 01 0000 [.text] __ZNK11SiBltResFmt15GetHwEndianModeE11_UBM_ENDIAN 00000000000bc794 g 0f SECT 01 0000 [.text] __ZNK11SiBltResFmt15GetHwImgDataFmtE11_UBM_FORMATj 00000000000bc772 g 0f SECT 01 0000 [.text] __ZNK11SiBltResFmt15GetHwStencilFmtE11_UBM_FORMAT 00000000000bd590 g 0f SECT 01 0000 [.text] __ZNK11SiBltResFmt18DepthBytesPerPixelE11_UBM_FORMAT 00000000000bd5fa g 0f SECT 01 0000 [.text] __ZNK11SiBltResFmt19GetDccFastClearCodeE11_UBM_FORMATPK12_UBM_VECTORL 00000000000bd036 g 0f SECT 01 0000 [.text] __ZNK11SiBltResFmt19GetShaderExportModeE11_UBM_FORMATjjj 00000000000bcfd8 g 0f SECT 01 0000 [.text] __ZNK11SiBltResFmt19IsTcCompatibleDepthE11_UBM_FORMAT 00000000000bcfc4 g 0f SECT 01 0000 [.text] __ZNK11SiBltResFmt7IsFmaskE11_UBM_FORMAT 00000000000bcf10 g 0f SECT 01 0000 [.text] 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__ZNK12AMDSISPURing9MetaClass5allocEv 000000000002aaa2 g 0f SECT 01 0000 [.text] __ZNK12AMDSISurface12getMetaClassEv 000000000002aae2 g 0f SECT 01 0000 [.text] __ZNK12AMDSISurface9MetaClass5allocEv 0000000000071c42 g 0f SECT 01 0000 [.text] __ZNK12AMDSIUVDRing12getMetaClassEv 0000000000071c82 g 0f SECT 01 0000 [.text] __ZNK12AMDSIUVDRing9MetaClass5allocEv 0000000000070402 g 0f SECT 01 0000 [.text] __ZNK12AMDSIVCERing12getMetaClassEv 0000000000070442 g 0f SECT 01 0000 [.text] __ZNK12AMDSIVCERing9MetaClass5allocEv 00000000000897f2 g 0f SECT 01 0000 [.text] __ZNK12AMDVIDisplay12getMetaClassEv 0000000000089832 g 0f SECT 01 0000 [.text] __ZNK12AMDVIDisplay9MetaClass5allocEv 000000000007c762 g 0f SECT 01 0000 [.text] __ZNK13AMDCIHWMemory12getMetaClassEv 000000000007c7a2 g 0f SECT 01 0000 [.text] __ZNK13AMDCIHWMemory9MetaClass5allocEv 0000000000074842 g 0f SECT 01 0000 [.text] __ZNK13AMDCIHardware12getMetaClassEv 0000000000074882 g 0f SECT 01 0000 [.text] __ZNK13AMDCIHardware9MetaClass5allocEv 000000000003e170 g 0f SECT 01 0000 [.text] __ZNK13AMDCIResource12getFMaskInfoEP30_ADDR_COMPUTE_FMASK_INFO_INPUTP31_ADDR_COMPUTE_FMASK_INFO_OUTPUTP14_ADDR_TILEINFO 000000000003d702 g 0f SECT 01 0000 [.text] __ZNK13AMDCIResource12getMetaClassEv 000000000003d808 g 0f SECT 01 0000 [.text] __ZNK13AMDCIResource15isLinearGeneralEP13_UBM_SURFINFO 000000000003e2ca g 0f SECT 01 0000 [.text] __ZNK13AMDCIResource19stencilBufferOffsetEP16IOAccelMemoryMapjjj 000000000003e1bc g 0f SECT 01 0000 [.text] __ZNK13AMDCIResource22fillTilingInfoForFMaskEP15AMD_TILING_INFOPK14_ADDR_TILEINFO13_AddrTileModei13_AddrTileType 000000000003daaa g 0f SECT 01 0000 [.text] __ZNK13AMDCIResource25fillUBMSurfaceInfoBackingEP13_UBM_SURFINFOP16IOAccelMemoryMapjjjPb 000000000003d7f4 g 0f SECT 01 0000 [.text] __ZNK13AMDCIResource27getArrayMode_linear_alignedEv 000000000003d800 g 0f SECT 01 0000 [.text] __ZNK13AMDCIResource27getArrayMode_linear_generalEv 000000000003d742 g 0f SECT 01 0000 [.text] __ZNK13AMDCIResource9MetaClass5allocEv 000000000007a482 g 0f SECT 01 0000 [.text] __ZNK13AMDCIsDMARing12getMetaClassEv 000000000007a4c2 g 0f SECT 01 0000 [.text] __ZNK13AMDCIsDMARing9MetaClass5allocEv 0000000000062be2 g 0f SECT 01 0000 [.text] __ZNK13AMDSIHWMemory12getMetaClassEv 0000000000062c22 g 0f SECT 01 0000 [.text] __ZNK13AMDSIHWMemory9MetaClass5allocEv 0000000000066ba2 g 0f SECT 01 0000 [.text] __ZNK13AMDSIHardware12getMetaClassEv 0000000000066be2 g 0f SECT 01 0000 [.text] __ZNK13AMDSIHardware9MetaClass5allocEv 000000000002a6e6 g 0f SECT 01 0000 [.text] __ZNK13AMDSIResource12getFMaskInfoEP30_ADDR_COMPUTE_FMASK_INFO_INPUTP31_ADDR_COMPUTE_FMASK_INFO_OUTPUTP14_ADDR_TILEINFO 000000000002a2c2 g 0f SECT 01 0000 [.text] __ZNK13AMDSIResource12getMetaClassEv 000000000002a40c g 0f SECT 01 0000 [.text] __ZNK13AMDSIResource15isLinearGeneralEP13_UBM_SURFINFO 000000000002a7e0 g 0f SECT 01 0000 [.text] __ZNK13AMDSIResource19stencilBufferOffsetEP16IOAccelMemoryMapjjj 000000000002a732 g 0f SECT 01 0000 [.text] __ZNK13AMDSIResource22fillTilingInfoForFMaskEP15AMD_TILING_INFOPK14_ADDR_TILEINFO13_AddrTileModei13_AddrTileType 000000000002a632 g 0f SECT 01 0000 [.text] __ZNK13AMDSIResource25fillUBMSurfaceInfoBackingEP13_UBM_SURFINFOP16IOAccelMemoryMapjjjPb 000000000002a3f8 g 0f SECT 01 0000 [.text] __ZNK13AMDSIResource27getArrayMode_linear_alignedEv 000000000002a404 g 0f SECT 01 0000 [.text] __ZNK13AMDSIResource27getArrayMode_linear_generalEv 000000000002a302 g 0f SECT 01 0000 [.text] __ZNK13AMDSIResource9MetaClass5allocEv 00000000000876e2 g 0f SECT 01 0000 [.text] __ZNK13AMDVIHWMemory12getMetaClassEv 0000000000087722 g 0f SECT 01 0000 [.text] __ZNK13AMDVIHWMemory9MetaClass5allocEv 0000000000083ec2 g 0f SECT 01 0000 [.text] __ZNK13AMDVIHardware12getMetaClassEv 0000000000083f02 g 0f SECT 01 0000 [.text] __ZNK13AMDVIHardware9MetaClass5allocEv 0000000000047a94 g 0f SECT 01 0000 [.text] __ZNK13AMDVIResource12getFMaskInfoEP30_ADDR_COMPUTE_FMASK_INFO_INPUTP31_ADDR_COMPUTE_FMASK_INFO_OUTPUTP14_ADDR_TILEINFO 0000000000047012 g 0f SECT 01 0000 [.text] __ZNK13AMDVIResource12getMetaClassEv 0000000000047118 g 0f SECT 01 0000 [.text] __ZNK13AMDVIResource15isLinearGeneralEP13_UBM_SURFINFO 0000000000047bee g 0f SECT 01 0000 [.text] __ZNK13AMDVIResource19stencilBufferOffsetEP16IOAccelMemoryMapjjj 0000000000047ae0 g 0f SECT 01 0000 [.text] __ZNK13AMDVIResource22fillTilingInfoForFMaskEP15AMD_TILING_INFOPK14_ADDR_TILEINFO13_AddrTileModei13_AddrTileType 00000000000473ce g 0f SECT 01 0000 [.text] __ZNK13AMDVIResource25fillUBMSurfaceInfoBackingEP13_UBM_SURFINFOP16IOAccelMemoryMapjjjPb 0000000000047104 g 0f SECT 01 0000 [.text] __ZNK13AMDVIResource27getArrayMode_linear_alignedEv 0000000000047110 g 0f SECT 01 0000 [.text] __ZNK13AMDVIResource27getArrayMode_linear_generalEv 0000000000047052 g 0f SECT 01 0000 [.text] __ZNK13AMDVIResource9MetaClass5allocEv 000000000008cf32 g 0f SECT 01 0000 [.text] __ZNK13AMDVIsDMARing12getMetaClassEv 000000000008cf72 g 0f SECT 01 0000 [.text] __ZNK13AMDVIsDMARing9MetaClass5allocEv 00000000000b2e32 g 0f SECT 01 0000 [.text] __ZNK13SiBltDrawRegs13GetDccSettingEPK11SiBltDevicePK13_UBM_SURFINFO 00000000000b224c g 0f SECT 01 0000 [.text] __ZNK13SiBltDrawRegs19GetNumEntriesNeededEPK7BltInfo 00000000000b3860 g 0f SECT 01 0000 [.text] __ZNK13SiBltDrawRegs28GetDecompressZPlaneThresholdEPK11SiBltDevicej 00000000000a776a g 0f SECT 01 0000 [.text] __ZNK13SurfAttribute10FreeSysMemEPv 00000000000a7740 g 0f SECT 01 0000 [.text] __ZNK13SurfAttribute11AllocSysMemEj 0000000000043b22 g 0f SECT 01 0000 [.text] __ZNK14AMDCICLContext12getMetaClassEv 0000000000043b62 g 0f SECT 01 0000 [.text] __ZNK14AMDCICLContext9MetaClass5allocEv 0000000000078012 g 0f SECT 01 0000 [.text] __ZNK14AMDCIPM4Engine12getMetaClassEv 0000000000078052 g 0f SECT 01 0000 [.text] __ZNK14AMDCIPM4Engine9MetaClass5allocEv 000000000003a46a g 0f SECT 01 0000 [.text] __ZNK14AMDSICLContext12getMetaClassEv 000000000003a4aa g 0f SECT 01 0000 [.text] __ZNK14AMDSICLContext9MetaClass5allocEv 000000000006d622 g 0f SECT 01 0000 [.text] __ZNK14AMDSIDMAEngine12getMetaClassEv 000000000006d662 g 0f SECT 01 0000 [.text] __ZNK14AMDSIDMAEngine9MetaClass5allocEv 000000000003202c g 0f SECT 01 0000 [.text] __ZNK14AMDSIGLContext12getMetaClassEv 0000000000032b1a g 0f SECT 01 0000 [.text] __ZNK14AMDSIGLContext18get_texture_offsetEP31AMDRadeonX4000_AMDAccelResourcej 00000000000326b6 g 0f SECT 01 0000 [.text] __ZNK14AMDSIGLContext19CmdBufOffsetIsValidERK24IOAccelCommandStreamInfoj 0000000000033bfa g 0f SECT 01 0000 [.text] __ZNK14AMDSIGLContext21get_max_render_slicesEP31AMDRadeonX4000_AMDAccelResource 000000000003206c g 0f SECT 01 0000 [.text] __ZNK14AMDSIGLContext9MetaClass5allocEv 000000000006b182 g 0f SECT 01 0000 [.text] __ZNK14AMDSIPM4Engine12getMetaClassEv 000000000006b1c2 g 0f SECT 01 0000 [.text] __ZNK14AMDSIPM4Engine9MetaClass5allocEv 0000000000072232 g 0f SECT 01 0000 [.text] __ZNK14AMDSISPUEngine12getMetaClassEv 0000000000072272 g 0f SECT 01 0000 [.text] __ZNK14AMDSISPUEngine9MetaClass5allocEv 00000000000651b2 g 0f SECT 01 0000 [.text] __ZNK14AMDSIVMContext12getMetaClassEv 00000000000651f2 g 0f SECT 01 0000 [.text] __ZNK14AMDSIVMContext9MetaClass5allocEv 000000000008f3f2 g 0f SECT 01 0000 [.text] __ZNK14AMDVIPM4Engine12getMetaClassEv 000000000008f432 g 0f SECT 01 0000 [.text] __ZNK14AMDVIPM4Engine9MetaClass5allocEv 0000000000087df2 g 0f SECT 01 0000 [.text] __ZNK14AMDVIVMContext12getMetaClassEv 0000000000087e32 g 0f SECT 01 0000 [.text] __ZNK14AMDVIVMContext9MetaClass5allocEv 00000000000da25c g 0f SECT 01 0000 [.text] __ZNK14EgBasedAddrLib16HwlTileInfoEqualEPK14_ADDR_TILEINFOS2_ 00000000000d9ea4 g 0f SECT 01 0000 [.text] __ZNK14EgBasedAddrLib17ComputeHtileBytesEjjjijPyj 00000000000d9afe g 0f SECT 01 0000 [.text] __ZNK14EgBasedAddrLib18GetBankPipeSwizzleEjjyP14_ADDR_TILEINFO 00000000000da8de g 0f SECT 01 0000 [.text] __ZNK14EgBasedAddrLib18HwlComputeHtileBppEii 00000000000d94bc g 0f SECT 01 0000 [.text] __ZNK14EgBasedAddrLib19ComputeBankFromAddrEyjj 00000000000d9a50 g 0f SECT 01 0000 [.text] __ZNK14EgBasedAddrLib19ComputeBankRotationE13_AddrTileModejj 00000000000d9a8a g 0f SECT 01 0000 [.text] __ZNK14EgBasedAddrLib19ComputePipeRotationE13_AddrTileModej 00000000000d7e4c g 0f SECT 01 0000 [.text] __ZNK14EgBasedAddrLib19HwlDegradeBaseLevelEPK32_ADDR_COMPUTE_SURFACE_INFO_INPUT 00000000000d87c6 g 0f SECT 01 0000 [.text] __ZNK14EgBasedAddrLib20ComputeBankFromCoordEjjj13_AddrTileModejjP14_ADDR_TILEINFO 00000000000d9bae g 0f SECT 01 0000 [.text] __ZNK14EgBasedAddrLib21HwlComputeBaseSwizzleEPK32_ADDR_COMPUTE_BASE_SWIZZLE_INPUTP33_ADDR_COMPUTE_BASE_SWIZZLE_OUTPUT 00000000000da740 g 0f SECT 01 0000 [.text] __ZNK14EgBasedAddrLib21HwlComputeSurfaceInfoEPK32_ADDR_COMPUTE_SURFACE_INFO_INPUTP33_ADDR_COMPUTE_SURFACE_INFO_OUTPUT 00000000000d7dc4 g 0f SECT 01 0000 [.text] __ZNK14EgBasedAddrLib21SanityCheckMacroTiledEP14_ADDR_TILEINFO 00000000000d8372 g 0f SECT 01 0000 [.text] __ZNK14EgBasedAddrLib22ExtractBankPipeSwizzleEjP14_ADDR_TILEINFOPjS2_ 00000000000da290 g 0f SECT 01 0000 [.text] __ZNK14EgBasedAddrLib22HwlConvertTileInfoToHWEPK32_ADDR_CONVERT_TILEINFOTOHW_INPUTP33_ADDR_CONVERT_TILEINFOTOHW_OUTPUT 00000000000d9c8c g 0f SECT 01 0000 [.text] __ZNK14EgBasedAddrLib23ComputeSliceTileSwizzleE13_AddrTileModejjyP14_ADDR_TILEINFO 00000000000d7fd4 g 0f SECT 01 0000 [.text] __ZNK14EgBasedAddrLib23HwlDegradeThickTileModeE13_AddrTileModejPj 00000000000d7280 g 0f SECT 01 0000 [.text] __ZNK14EgBasedAddrLib24ComputeSurfaceInfoLinearEPK32_ADDR_COMPUTE_SURFACE_INFO_INPUTP33_ADDR_COMPUTE_SURFACE_INFO_OUTPUTj 00000000000da8ea g 0f SECT 01 0000 [.text] __ZNK14EgBasedAddrLib24HwlComputeHtileBaseAlignEiiP14_ADDR_TILEINFO 00000000000d7c92 g 0f SECT 01 0000 [.text] __ZNK14EgBasedAddrLib24HwlReduceBankWidthHeightEjj19_ADDR_SURFACE_FLAGSjjjP14_ADDR_TILEINFO 00000000000d9ad2 g 0f SECT 01 0000 [.text] __ZNK14EgBasedAddrLib25HwlCombineBankPipeSwizzleEjjP14_ADDR_TILEINFOyPj 00000000000d9ab2 g 0f SECT 01 0000 [.text] __ZNK14EgBasedAddrLib25HwlExtractBankPipeSwizzleEPK36_ADDR_EXTRACT_BANKPIPE_SWIZZLE_INPUTP37_ADDR_EXTRACT_BANKPIPE_SWIZZLE_OUTPUT 00000000000d70ce g 0f SECT 01 0000 [.text] __ZNK14EgBasedAddrLib26DispatchComputeSurfaceInfoEPK32_ADDR_COMPUTE_SURFACE_INFO_INPUTP33_ADDR_COMPUTE_SURFACE_INFO_OUTPUT 00000000000da8a0 g 0f SECT 01 0000 [.text] __ZNK14EgBasedAddrLib26HwlComputeSliceTileSwizzleEPK32_ADDR_COMPUTE_SLICESWIZZLE_INPUTP33_ADDR_COMPUTE_SLICESWIZZLE_OUTPUT 00000000000d7574 g 0f SECT 01 0000 [.text] __ZNK14EgBasedAddrLib28ComputeSurfaceInfoMacroTiledEPK32_ADDR_COMPUTE_SURFACE_INFO_INPUTP33_ADDR_COMPUTE_SURFACE_INFO_OUTPUTj13_AddrTileMode 00000000000d73d8 g 0f SECT 01 0000 [.text] __ZNK14EgBasedAddrLib28ComputeSurfaceInfoMicroTiledEPK32_ADDR_COMPUTE_SURFACE_INFO_INPUTP33_ADDR_COMPUTE_SURFACE_INFO_OUTPUTj13_AddrTileMode 00000000000da1c8 g 0f SECT 01 0000 [.text] __ZNK14EgBasedAddrLib28HwlComputeFmaskAddrFromCoordEPK39_ADDR_COMPUTE_FMASK_ADDRFROMCOORD_INPUTP40_ADDR_COMPUTE_FMASK_ADDRFROMCOORD_OUTPUT 00000000000da1d0 g 0f SECT 01 0000 [.text] __ZNK14EgBasedAddrLib28HwlComputeFmaskCoordFromAddrEPK39_ADDR_COMPUTE_FMASK_COORDFROMADDR_INPUTP40_ADDR_COMPUTE_FMASK_COORDFROMADDR_OUTPUT 00000000000d7882 g 0f SECT 01 0000 [.text] __ZNK14EgBasedAddrLib30ComputeSurfaceAlignmentsLinearE13_AddrTileModej19_ADDR_SURFACE_FLAGSPjS2_S2_ 00000000000d7b6c g 0f SECT 01 0000 [.text] __ZNK14EgBasedAddrLib30ComputeSurfaceMipLevelTileModeE13_AddrTileModejjjjjjjP14_ADDR_TILEINFO 00000000000d89ce g 0f SECT 01 0000 [.text] __ZNK14EgBasedAddrLib30HwlComputePixelCoordFromOffsetEjjj13_AddrTileModejjPjS1_S1_S1_13_AddrTileTypei 00000000000d9e18 g 0f SECT 01 0000 [.text] __ZNK14EgBasedAddrLib30HwlComputeQbStereoRightSwizzleEP33_ADDR_COMPUTE_SURFACE_INFO_OUTPUT 00000000000da844 g 0f SECT 01 0000 [.text] __ZNK14EgBasedAddrLib30HwlComputeSurfaceAddrFromCoordEPK41_ADDR_COMPUTE_SURFACE_ADDRFROMCOORD_INPUTP42_ADDR_COMPUTE_SURFACE_ADDRFROMCOORD_OUTPUT 00000000000da880 g 0f SECT 01 0000 [.text] __ZNK14EgBasedAddrLib30HwlComputeSurfaceCoordFromAddrEPK41_ADDR_COMPUTE_SURFACE_COORDFROMADDR_INPUTP42_ADDR_COMPUTE_SURFACE_COORDFROMADDR_OUTPUT 00000000000da926 g 0f SECT 01 0000 [.text] __ZNK14EgBasedAddrLib30HwlGetPitchAlignmentMicroTiledE13_AddrTileModej19_ADDR_SURFACE_FLAGSj 00000000000da97c g 0f SECT 01 0000 [.text] __ZNK14EgBasedAddrLib30HwlGetSizeAdjustmentMicroTiledEjj19_ADDR_SURFACE_FLAGSjjjPjS1_ 00000000000d94ec g 0f SECT 01 0000 [.text] __ZNK14EgBasedAddrLib33ComputeSurfaceCoord2DFromBankPipeE13_AddrTileModejjjjjjjjP14_ADDR_TILEINFOP17CoordFromBankPipe 00000000000d7998 g 0f SECT 01 0000 [.text] __ZNK14EgBasedAddrLib34ComputeSurfaceAlignmentsMacroTiledE13_AddrTileModej19_ADDR_SURFACE_FLAGSjjP14_ADDR_TILEINFOPjS4_S4_ 00000000000d7906 g 0f SECT 01 0000 [.text] __ZNK14EgBasedAddrLib34ComputeSurfaceAlignmentsMicroTiledE13_AddrTileModej19_ADDR_SURFACE_FLAGSjPjS2_S2_ 00000000000d805e g 0f SECT 01 0000 [.text] __ZNK14EgBasedAddrLib35DispatchComputeSurfaceAddrFromCoordEPK41_ADDR_COMPUTE_SURFACE_ADDRFROMCOORD_INPUTP42_ADDR_COMPUTE_SURFACE_ADDRFROMCOORD_OUTPUT 00000000000d8f6e g 0f SECT 01 0000 [.text] __ZNK14EgBasedAddrLib35DispatchComputeSurfaceCoordFromAddrEPK41_ADDR_COMPUTE_SURFACE_COORDFROMADDR_INPUTP42_ADDR_COMPUTE_SURFACE_COORDFROMADDR_OUTPUT 00000000000d846a g 0f SECT 01 0000 [.text] __ZNK14EgBasedAddrLib37ComputeSurfaceAddrFromCoordMacroTiledEjjjjjjjj13_AddrTileMode13_AddrTileTypeiijjP14_ADDR_TILEINFOPj 00000000000d826e g 0f SECT 01 0000 [.text] __ZNK14EgBasedAddrLib37ComputeSurfaceAddrFromCoordMicroTiledEjjjjjjjj13_AddrTileMode13_AddrTileTypeiPj 00000000000d91d6 g 0f SECT 01 0000 [.text] __ZNK14EgBasedAddrLib37ComputeSurfaceCoordFromAddrMacroTiledEyjjjjj13_AddrTileModejj13_AddrTileTypeiijjP14_ADDR_TILEINFOPjS4_S4_S4_ 000000000007e2b2 g 0f SECT 01 0000 [.text] __ZNK15AMDCIDMAChannel12getMetaClassEv 000000000007e3fc g 0f SECT 01 0000 [.text] __ZNK15AMDCIDMAChannel21writeSemaphoreCommandEPjyb 000000000007e2f2 g 0f SECT 01 0000 [.text] __ZNK15AMDCIDMAChannel9MetaClass5allocEv 000000000007d282 g 0f SECT 01 0000 [.text] __ZNK15AMDCIPM4Channel12getMetaClassEv 000000000007dcb6 g 0f SECT 01 0000 [.text] __ZNK15AMDCIPM4Channel21writeSemaphoreCommandEPjyb 000000000007d2c2 g 0f SECT 01 0000 [.text] __ZNK15AMDCIPM4Channel9MetaClass5allocEv 000000000007f162 g 0f SECT 01 0000 [.text] __ZNK15AMDCISAMUEngine12getMetaClassEv 000000000007f1a2 g 0f SECT 01 0000 [.text] __ZNK15AMDCISAMUEngine9MetaClass5allocEv 0000000000081c52 g 0f SECT 01 0000 [.text] __ZNK15AMDCIVCEChannel12getMetaClassEv 0000000000081d6c g 0f SECT 01 0000 [.text] __ZNK15AMDCIVCEChannel21writeSemaphoreCommandEPjyb 0000000000081c92 g 0f SECT 01 0000 [.text] __ZNK15AMDCIVCEChannel9MetaClass5allocEv 00000000000829b2 g 0f SECT 01 0000 [.text] __ZNK15AMDCIVCELLQRing12getMetaClassEv 00000000000829f2 g 0f SECT 01 0000 [.text] __ZNK15AMDCIVCELLQRing9MetaClass5allocEv 0000000000079c42 g 0f SECT 01 0000 [.text] __ZNK15AMDCIsDMAEngine12getMetaClassEv 0000000000079c82 g 0f SECT 01 0000 [.text] __ZNK15AMDCIsDMAEngine9MetaClass5allocEv 000000000006db12 g 0f SECT 01 0000 [.text] __ZNK15AMDSIDMAChannel12getMetaClassEv 000000000006dc5c g 0f SECT 01 0000 [.text] __ZNK15AMDSIDMAChannel21writeSemaphoreCommandEPjyb 000000000006db52 g 0f SECT 01 0000 [.text] __ZNK15AMDSIDMAChannel9MetaClass5allocEv 000000000006c5a2 g 0f SECT 01 0000 [.text] __ZNK15AMDSIPM4Channel12getMetaClassEv 000000000006c5e2 g 0f SECT 01 0000 [.text] __ZNK15AMDSIPM4Channel9MetaClass5allocEv 0000000000072f42 g 0f SECT 01 0000 [.text] __ZNK15AMDSISPUChannel12getMetaClassEv 0000000000072f82 g 0f SECT 01 0000 [.text] __ZNK15AMDSISPUChannel9MetaClass5allocEv 0000000000070d82 g 0f SECT 01 0000 [.text] __ZNK15AMDSIUVDChannel12getMetaClassEv 0000000000070ff4 g 0f SECT 01 0000 [.text] __ZNK15AMDSIUVDChannel21writeSemaphoreCommandEPjyb 0000000000070dc2 g 0f SECT 01 0000 [.text] __ZNK15AMDSIUVDChannel9MetaClass5allocEv 000000000006fc32 g 0f SECT 01 0000 [.text] __ZNK15AMDSIVCEChannel12getMetaClassEv 000000000006fd4c g 0f SECT 01 0000 [.text] __ZNK15AMDSIVCEChannel21writeSemaphoreCommandEPjyb 000000000006fc72 g 0f SECT 01 0000 [.text] __ZNK15AMDSIVCEChannel9MetaClass5allocEv 0000000000070992 g 0f SECT 01 0000 [.text] __ZNK15AMDSIVCELLQRing12getMetaClassEv 00000000000709d2 g 0f SECT 01 0000 [.text] __ZNK15AMDSIVCELLQRing9MetaClass5allocEv 000000000008df72 g 0f SECT 01 0000 [.text] __ZNK15AMDVIPM4Channel12getMetaClassEv 000000000008e9a8 g 0f SECT 01 0000 [.text] __ZNK15AMDVIPM4Channel21writeSemaphoreCommandEPjyb 000000000008dfb2 g 0f SECT 01 0000 [.text] __ZNK15AMDVIPM4Channel9MetaClass5allocEv 0000000000092372 g 0f SECT 01 0000 [.text] __ZNK15AMDVISAMUEngine12getMetaClassEv 00000000000923b2 g 0f SECT 01 0000 [.text] __ZNK15AMDVISAMUEngine9MetaClass5allocEv 000000000008c712 g 0f SECT 01 0000 [.text] __ZNK15AMDVIsDMAEngine12getMetaClassEv 000000000008c752 g 0f SECT 01 0000 [.text] __ZNK15AMDVIsDMAEngine9MetaClass5allocEv 00000000000cb5a8 g 0f SECT 01 0000 [.text] __ZNK15SiSurfAttribute11GetTileModeEPK13_UBM_SURFINFO 00000000000cb674 g 0f SECT 01 0000 [.text] __ZNK15SiSurfAttribute11GetTileTypeEPK13_UBM_SURFINFO 00000000000cb6f4 g 0f SECT 01 0000 [.text] __ZNK15SiSurfAttribute12GetArrayModeEi 00000000000cb830 g 0f SECT 01 0000 [.text] __ZNK15SiSurfAttribute13GetTileConfigEi 00000000000cb7ac g 0f SECT 01 0000 [.text] __ZNK15SiSurfAttribute14GetCBTileIndexEiPj 00000000000cb8b0 g 0f SECT 01 0000 [.text] __ZNK15SiSurfAttribute16ComputeTileIndexE14_UBM_TILE_MODE14_UBM_TILE_TYPEj 00000000000cb6be g 0f SECT 01 0000 [.text] __ZNK15SiSurfAttribute16GetMicroTileModeEi 00000000000cb71c g 0f SECT 01 0000 [.text] __ZNK15SiSurfAttribute16IsValidTileIndexEi 00000000000cb7f8 g 0f SECT 01 0000 [.text] __ZNK15SiSurfAttribute21GetDepthTileSplitSizeEi 00000000000cba42 g 0f SECT 01 0000 [.text] __ZNK15SiSurfAttribute21GetMacroTileDimensionEjPjS0_ 00000000000cba14 g 0f SECT 01 0000 [.text] __ZNK15SiSurfAttribute25GetLinearAlignedTileIndexEv 00000000000cb73a g 0f SECT 01 0000 [.text] __ZNK15SiSurfAttribute28GetCICompressZResolveCBIndexEi 00000000000cb572 g 0f SECT 01 0000 [.text] __ZNK15SiSurfAttribute33GetLinearAlignedSurfacePitchAlignEj 00000000000cb58e g 0f SECT 01 0000 [.text] __ZNK15SiSurfAttribute33GetLinearAlignedSurfaceSliceAlignEj 0000000000082da2 g 0f SECT 01 0000 [.text] __ZNK16AMDCIComputeRing12getMetaClassEv 0000000000082de2 g 0f SECT 01 0000 [.text] __ZNK16AMDCIComputeRing9MetaClass5allocEv 000000000007cef2 g 0f SECT 01 0000 [.text] __ZNK16AMDCIHWUtilities12getMetaClassEv 000000000007d052 g 0f SECT 01 0000 [.text] __ZNK16AMDCIHWUtilities14getUbmTileModeEj 000000000007cf32 g 0f SECT 01 0000 [.text] __ZNK16AMDCIHWUtilities9MetaClass5allocEv 000000000007fa32 g 0f SECT 01 0000 [.text] __ZNK16AMDCISAMURBIRing12getMetaClassEv 000000000007fa72 g 0f SECT 01 0000 [.text] __ZNK16AMDCISAMURBIRing9MetaClass5allocEv 0000000000080f22 g 0f SECT 01 0000 [.text] __ZNK16AMDCIUVDHWEngine12getMetaClassEv 0000000000080f62 g 0f SECT 01 0000 [.text] __ZNK16AMDCIUVDHWEngine9MetaClass5allocEv 0000000000081452 g 0f SECT 01 0000 [.text] __ZNK16AMDCIVCEHWEngine12getMetaClassEv 0000000000081492 g 0f SECT 01 0000 [.text] __ZNK16AMDCIVCEHWEngine9MetaClass5allocEv 0000000000073902 g 0f SECT 01 0000 [.text] __ZNK16AMDSIComputeRing12getMetaClassEv 0000000000073942 g 0f SECT 01 0000 [.text] __ZNK16AMDSIComputeRing9MetaClass5allocEv 0000000000064df2 g 0f SECT 01 0000 [.text] __ZNK16AMDSIHWUtilities12getMetaClassEv 000000000006503c g 0f SECT 01 0000 [.text] __ZNK16AMDSIHWUtilities14getUbmTileModeEj 0000000000064e32 g 0f SECT 01 0000 [.text] __ZNK16AMDSIHWUtilities9MetaClass5allocEv 0000000000071432 g 0f SECT 01 0000 [.text] __ZNK16AMDSIUVDHWEngine12getMetaClassEv 0000000000071472 g 0f SECT 01 0000 [.text] __ZNK16AMDSIUVDHWEngine9MetaClass5allocEv 000000000006f432 g 0f SECT 01 0000 [.text] __ZNK16AMDSIVCEHWEngine12getMetaClassEv 000000000006f472 g 0f SECT 01 0000 [.text] __ZNK16AMDSIVCEHWEngine9MetaClass5allocEv 0000000000086c32 g 0f SECT 01 0000 [.text] __ZNK16AMDTongaHardware12getMetaClassEv 0000000000086c72 g 0f SECT 01 0000 [.text] __ZNK16AMDTongaHardware9MetaClass5allocEv 000000000008d9f2 g 0f SECT 01 0000 [.text] __ZNK16AMDVIComputeRing12getMetaClassEv 000000000008da32 g 0f SECT 01 0000 [.text] __ZNK16AMDVIComputeRing9MetaClass5allocEv 000000000008b4e2 g 0f SECT 01 0000 [.text] __ZNK16AMDVIHWUtilities12getMetaClassEv 000000000008b642 g 0f SECT 01 0000 [.text] __ZNK16AMDVIHWUtilities14getUbmTileModeEj 000000000008b522 g 0f SECT 01 0000 [.text] __ZNK16AMDVIHWUtilities9MetaClass5allocEv 0000000000092812 g 0f SECT 01 0000 [.text] __ZNK16AMDVISAMURBIRing12getMetaClassEv 0000000000092852 g 0f SECT 01 0000 [.text] __ZNK16AMDVISAMURBIRing9MetaClass5allocEv 000000000008b862 g 0f SECT 01 0000 [.text] __ZNK16AMDVIsDMAChannel12getMetaClassEv 000000000008b9ac g 0f SECT 01 0000 [.text] __ZNK16AMDVIsDMAChannel21writeSemaphoreCommandEPjyb 000000000008b8a2 g 0f SECT 01 0000 [.text] __ZNK16AMDVIsDMAChannel9MetaClass5allocEv 000000000006a892 g 0f SECT 01 0000 [.text] __ZNK16AMDVerdeHardware12getMetaClassEv 000000000006a8d2 g 0f SECT 01 0000 [.text] __ZNK16AMDVerdeHardware9MetaClass5allocEv 00000000000bb618 g 0f SECT 01 0000 [.text] __ZNK16SiBltPixelShader16GetShaderMemSizeEv 00000000000bbac0 g 0f SECT 01 0000 [.text] __ZNK16SiBltPixelShader17GetPsCbShaderMaskEv 00000000000bb5d4 g 0f SECT 01 0000 [.text] __ZNK16SiBltPixelShader21GetTotalPatchCodeSizeEv 00000000000bb66a g 0f SECT 01 0000 [.text] __ZNK16SiBltPixelShader23GetRoundedShaderMemSizeEv 00000000000bb5ea g 0f SECT 01 0000 [.text] __ZNK16SiBltPixelShader26GetPatchTrackerDwordOffsetEv 00000000000bbaee g 0f SECT 01 0000 [.text] __ZNK16SiBltPixelShader9WriteToHwEP11SiBltDevicePK17SiBltVertexShader 0000000000079772 g 0f SECT 01 0000 [.text] __ZNK17AMDCICommandsRing12getMetaClassEv 00000000000797b2 g 0f SECT 01 0000 [.text] __ZNK17AMDCICommandsRing9MetaClass5allocEv 0000000000077a72 g 0f SECT 01 0000 [.text] __ZNK17AMDHawaiiHardware12getMetaClassEv 0000000000077ab2 g 0f SECT 01 0000 [.text] __ZNK17AMDHawaiiHardware9MetaClass5allocEv 000000000006cfc2 g 0f SECT 01 0000 [.text] __ZNK17AMDSICommandsRing12getMetaClassEv 000000000006d002 g 0f SECT 01 0000 [.text] __ZNK17AMDSICommandsRing9MetaClass5allocEv 000000000002ace2 g 0f SECT 01 0000 [.text] __ZNK17AMDSIVideoContext12getMetaClassEv 000000000002ad22 g 0f SECT 01 0000 [.text] __ZNK17AMDSIVideoContext9MetaClass5allocEv 0000000000069c72 g 0f SECT 01 0000 [.text] __ZNK17AMDTahitiHardware12getMetaClassEv 0000000000069cb2 g 0f SECT 01 0000 [.text] __ZNK17AMDTahitiHardware9MetaClass5allocEv 000000000008d522 g 0f SECT 01 0000 [.text] __ZNK17AMDVICommandsRing12getMetaClassEv 000000000008d562 g 0f SECT 01 0000 [.text] __ZNK17AMDVICommandsRing9MetaClass5allocEv 000000000006c242 g 0f SECT 01 0000 [.text] __ZNK17AMDVerdePM4Engine12getMetaClassEv 000000000006c282 g 0f SECT 01 0000 [.text] __ZNK17AMDVerdePM4Engine9MetaClass5allocEv 00000000000ca358 g 0f SECT 01 0000 [.text] __ZNK17SiBltVertexShader20GetVsSemanticsOffsetEjj 00000000000ca390 g 0f SECT 01 0000 [.text] __ZNK17SiBltVertexShader9WriteToHwEP11SiBltDevice 00000000000cb074 g 0f SECT 01 0000 [.text] __ZNK17SiShaderVidMemMgr18HwlVidMemAllocInfoEP22_UBM_ALLOCVIDMEM_INPUT 00000000000774c2 g 0f SECT 01 0000 [.text] __ZNK18AMDBonaireHardware12getMetaClassEv 0000000000077502 g 0f SECT 01 0000 [.text] __ZNK18AMDBonaireHardware9MetaClass5allocEv 00000000000803b2 g 0f SECT 01 0000 [.text] __ZNK18AMDCISAMUGPCOMRing12getMetaClassEv 00000000000803f2 g 0f SECT 01 0000 [.text] __ZNK18AMDCISAMUGPCOMRing9MetaClass5allocEv 0000000000082102 g 0f SECT 01 0000 [.text] __ZNK18AMDCIVCELLQChannel12getMetaClassEv 0000000000082142 g 0f SECT 01 0000 [.text] __ZNK18AMDCIVCELLQChannel9MetaClass5allocEv 00000000000700e2 g 0f SECT 01 0000 [.text] __ZNK18AMDSIVCELLQChannel12getMetaClassEv 0000000000070122 g 0f SECT 01 0000 [.text] __ZNK18AMDSIVCELLQChannel9MetaClass5allocEv 000000000006bb82 g 0f SECT 01 0000 [.text] __ZNK18AMDTahitiPM4Engine12getMetaClassEv 000000000006bbc2 g 0f SECT 01 0000 [.text] __ZNK18AMDTahitiPM4Engine9MetaClass5allocEv 0000000000092f52 g 0f SECT 01 0000 [.text] __ZNK18AMDVISAMUGPCOMRing12getMetaClassEv 0000000000092f92 g 0f SECT 01 0000 [.text] __ZNK18AMDVISAMUGPCOMRing9MetaClass5allocEv 00000000000aadc2 g 0f SECT 01 0000 [.text] __ZNK18SiBltComputeShader9WriteToHwEP11SiBltDevice 00000000000be5e2 g 0f SECT 01 0000 [.text] __ZNK18SiBltShaderLibrary15SelectExportZPsE11_UBM_FORMATjj 00000000000be3cc g 0f SECT 01 0000 [.text] __ZNK18SiBltShaderLibrary15SelectStretchPsEPK7BltInfo 00000000000be61a g 0f SECT 01 0000 [.text] __ZNK18SiBltShaderLibrary26SelectFMaskShaderResolvePsE31_UBM_MSAA_SHADER_RESOLVE_FILTERjj 00000000000be6a8 g 0f SECT 01 0000 [.text] __ZNK18SiBltShaderLibrary26SelectFastDepthClearShaderEPK7BltInfo 00000000000be5b8 g 0f SECT 01 0000 [.text] __ZNK18SiBltShaderLibrary26SelectShaderColorResolvePsE31_UBM_MSAA_SHADER_RESOLVE_FILTERjj 00000000000be6f2 g 0f SECT 01 0000 [.text] __ZNK18SiBltShaderLibrary9GetCsTypeEPK7BltInfo 00000000000bdf58 g 0f SECT 01 0000 [.text] __ZNK18SiBltShaderLibrary9GetPsTypeEPK7BltInfo 00000000000bde36 g 0f SECT 01 0000 [.text] __ZNK18SiBltShaderLibrary9GetVsTypeEPK7BltInfo 000000000007ffb2 g 0f SECT 01 0000 [.text] __ZNK19AMDCISAMURBIChannel12getMetaClassEv 000000000007fff2 g 0f SECT 01 0000 [.text] __ZNK19AMDCISAMURBIChannel9MetaClass5allocEv 000000000006a282 g 0f SECT 01 0000 [.text] __ZNK19AMDPitcairnHardware12getMetaClassEv 000000000006a2c2 g 0f SECT 01 0000 [.text] __ZNK19AMDPitcairnHardware9MetaClass5allocEv 000000000002a0c2 g 0f SECT 01 0000 [.text] __ZNK19AMDSIDisplayMachine12getMetaClassEv 000000000002a102 g 0f SECT 01 0000 [.text] __ZNK19AMDSIDisplayMachine9MetaClass5allocEv 000000000006aea2 g 0f SECT 01 0000 [.text] __ZNK19AMDSIHWAlignManager12getMetaClassEv 000000000006aee2 g 0f SECT 01 0000 [.text] __ZNK19AMDSIHWAlignManager9MetaClass5allocEv 0000000000046e12 g 0f SECT 01 0000 [.text] __ZNK19AMDVIDisplayMachine12getMetaClassEv 0000000000046e52 g 0f SECT 01 0000 [.text] __ZNK19AMDVIDisplayMachine9MetaClass5allocEv 0000000000092c22 g 0f SECT 01 0000 [.text] __ZNK19AMDVISAMURBIChannel12getMetaClassEv 0000000000092c62 g 0f SECT 01 0000 [.text] __ZNK19AMDVISAMURBIChannel9MetaClass5allocEv 000000000006bee2 g 0f SECT 01 0000 [.text] __ZNK20AMDPitcairnPM4Engine12getMetaClassEv 000000000006bf22 g 0f SECT 01 0000 [.text] __ZNK20AMDPitcairnPM4Engine9MetaClass5allocEv 0000000000080b32 g 0f SECT 01 0000 [.text] __ZNK21AMDCISAMUGPCOMChannel12getMetaClassEv 0000000000080b72 g 0f SECT 01 0000 [.text] __ZNK21AMDCISAMUGPCOMChannel9MetaClass5allocEv 0000000000093442 g 0f SECT 01 0000 [.text] __ZNK21AMDVISAMUGPCOMChannel12getMetaClassEv 0000000000093482 g 0f SECT 01 0000 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__ZNK30AMDRadeonX4000_IAMDHWVMContext9MetaClass5allocEv 000000000000bd50 g 0f SECT 01 0000 [.text] __ZNK31AMDRadeonX4000_AMDAccelResource11getRowBytesEj 000000000000a172 g 0f SECT 01 0000 [.text] __ZNK31AMDRadeonX4000_AMDAccelResource12getMetaClassEv 000000000000c4a4 g 0f SECT 01 0000 [.text] __ZNK31AMDRadeonX4000_AMDAccelResource12getRowPixelsEj 000000000000bdea g 0f SECT 01 0000 [.text] __ZNK31AMDRadeonX4000_AMDAccelResource14getSysRowBytesEj 000000000000bd6a g 0f SECT 01 0000 [.text] __ZNK31AMDRadeonX4000_AMDAccelResource15getBufferOffsetEjjj 000000000000c7a8 g 0f SECT 01 0000 [.text] __ZNK31AMDRadeonX4000_AMDAccelResource15getSysRowPixelsEj 000000000000c4da g 0f SECT 01 0000 [.text] __ZNK31AMDRadeonX4000_AMDAccelResource16getHeightAlignedEj 000000000000c798 g 0f SECT 01 0000 [.text] __ZNK31AMDRadeonX4000_AMDAccelResource17getMaxMipmapLevelEv 000000000000be04 g 0f SECT 01 0000 [.text] __ZNK31AMDRadeonX4000_AMDAccelResource18getSysBufferOffsetEjjj 000000000000c7f0 g 0f SECT 01 0000 [.text] __ZNK31AMDRadeonX4000_AMDAccelResource19getSysHeightAlignedEj 000000000000c52e g 0f SECT 01 0000 [.text] __ZNK31AMDRadeonX4000_AMDAccelResource25fillUBMSurfaceInfoBackingEP13_UBM_SURFINFOP16IOAccelMemoryMapjjjPb 000000000000c458 g 0f SECT 01 0000 [.text] __ZNK31AMDRadeonX4000_AMDAccelResource8getWidthEj 000000000000a1b2 g 0f SECT 01 0000 [.text] __ZNK31AMDRadeonX4000_AMDAccelResource9MetaClass5allocEv 000000000000c47e g 0f SECT 01 0000 [.text] __ZNK31AMDRadeonX4000_AMDAccelResource9getHeightEj 0000000000050372 g 0f SECT 01 0000 [.text] __ZNK31AMDRadeonX4000_AMDNullHWChannel12getMetaClassEv 00000000000503b2 g 0f SECT 01 0000 [.text] __ZNK31AMDRadeonX4000_AMDNullHWChannel9MetaClass5allocEv 000000000001ad02 g 0f SECT 01 0000 [.text] __ZNK31AMDRadeonX4000_AMDSPUAppContext12getMetaClassEv 000000000001ad42 g 0f SECT 01 0000 [.text] __ZNK31AMDRadeonX4000_AMDSPUAppContext9MetaClass5allocEv 000000000012431a g 0f SECT 01 0000 [.text] __ZNK31AMDRadeonX4000_IAMDSMLInterface12getMetaClassEv 000000000012435a g 0f SECT 01 0000 [.text] __ZNK31AMDRadeonX4000_IAMDSMLInterface9MetaClass5allocEv 0000000000015fb2 g 0f SECT 01 0000 [.text] __ZNK32AMDRadeonX4000_AMDAccel2DContext12getMetaClassEv 0000000000015ff2 g 0f SECT 01 0000 [.text] __ZNK32AMDRadeonX4000_AMDAccel2DContext9MetaClass5allocEv 0000000000026602 g 0f SECT 01 0000 [.text] __ZNK32AMDRadeonX4000_AMDAccelCLContext12getMetaClassEv 0000000000026642 g 0f SECT 01 0000 [.text] __ZNK32AMDRadeonX4000_AMDAccelCLContext9MetaClass5allocEv 00000000000285c2 g 0f SECT 01 0000 [.text] __ZNK32AMDRadeonX4000_AMDAccelMemoryMap12getMetaClassEv 0000000000028602 g 0f SECT 01 0000 [.text] __ZNK32AMDRadeonX4000_AMDAccelMemoryMap9MetaClass5allocEv 00000000000289aa g 0f SECT 01 0000 [.text] __ZNK32AMDRadeonX4000_AMDAccelMemoryMap9getLengthEv 0000000000027b82 g 0f SECT 01 0000 [.text] __ZNK32AMDRadeonX4000_AMDAccelSysMemory12getMetaClassEv 0000000000027bc2 g 0f SECT 01 0000 [.text] __ZNK32AMDRadeonX4000_AMDAccelSysMemory9MetaClass5allocEv 0000000000027df2 g 0f SECT 01 0000 [.text] __ZNK32AMDRadeonX4000_AMDAccelVidMemory12getMetaClassEv 0000000000027e32 g 0f SECT 01 0000 [.text] __ZNK32AMDRadeonX4000_AMDAccelVidMemory9MetaClass5allocEv 0000000000126968 g 0f SECT 01 0000 [.text] __ZNK32AMDRadeonX4000_AMDHDCPGetCertMsg12getMetaClassEv 00000000001269a8 g 0f SECT 01 0000 [.text] __ZNK32AMDRadeonX4000_AMDHDCPGetCertMsg9MetaClass5allocEv 000000000004f5c2 g 0f SECT 01 0000 [.text] __ZNK32AMDRadeonX4000_AMDHWAlignManager12getMetaClassEv 000000000004f602 g 0f SECT 01 0000 [.text] __ZNK32AMDRadeonX4000_AMDHWAlignManager9MetaClass5allocEv 0000000000127e02 g 0f SECT 01 0000 [.text] __ZNK32AMDRadeonX4000_AMDSMLSIInterface12getMetaClassEv 0000000000127e42 g 0f SECT 01 0000 [.text] __ZNK32AMDRadeonX4000_AMDSMLSIInterface9MetaClass5allocEv 000000000012b512 g 0f SECT 01 0000 [.text] __ZNK32AMDRadeonX4000_AMDSMLVIInterface12getMetaClassEv 000000000012b552 g 0f SECT 01 0000 [.text] __ZNK32AMDRadeonX4000_AMDSMLVIInterface9MetaClass5allocEv 0000000000012672 g 0f SECT 01 0000 [.text] __ZNK33AMDRadeonX4000_AMDAccelStatistics12getMetaClassEv 00000000000126b2 g 0f SECT 01 0000 [.text] __ZNK33AMDRadeonX4000_AMDAccelStatistics9MetaClass5allocEv 000000000001a7c2 g 0f SECT 01 0000 [.text] __ZNK33AMDRadeonX4000_AMDAccelUVDContext12getMetaClassEv 000000000001a802 g 0f SECT 01 0000 [.text] __ZNK33AMDRadeonX4000_AMDAccelUVDContext9MetaClass5allocEv 000000000001eab2 g 0f SECT 01 0000 [.text] __ZNK33AMDRadeonX4000_AMDAccelVCEContext12getMetaClassEv 000000000001eaf2 g 0f SECT 01 0000 [.text] __ZNK33AMDRadeonX4000_AMDAccelVCEContext9MetaClass5allocEv 00000000000570d2 g 0f SECT 01 0000 [.text] __ZNK33AMDRadeonX4000_AMDHWSemaphorePool12getMetaClassEv 0000000000057112 g 0f SECT 01 0000 [.text] __ZNK33AMDRadeonX4000_AMDHWSemaphorePool9MetaClass5allocEv 0000000000056e42 g 0f SECT 01 0000 [.text] __ZNK33AMDRadeonX4000_AMDNullHWSemaphore12getMetaClassEv 0000000000056e82 g 0f SECT 01 0000 [.text] __ZNK33AMDRadeonX4000_AMDNullHWSemaphore9MetaClass5allocEv 00000000001298b2 g 0f SECT 01 0000 [.text] __ZNK33AMDRadeonX4000_AMDSMLCIKInterface12getMetaClassEv 00000000001298f2 g 0f SECT 01 0000 [.text] __ZNK33AMDRadeonX4000_AMDSMLCIKInterface9MetaClass5allocEv 0000000000052880 g 0f SECT 01 0000 [.text] __ZNK33AMDRadeonX4000_IAMDHWAlignManager12getMetaClassEv 00000000000528c0 g 0f SECT 01 0000 [.text] __ZNK33AMDRadeonX4000_IAMDHWAlignManager9MetaClass5allocEv 000000000012665a g 0f SECT 01 0000 [.text] __ZNK34AMDRadeonX4000_AMDHDCPGetStatusMsg12getMetaClassEv 000000000012669a g 0f SECT 01 0000 [.text] __ZNK34AMDRadeonX4000_AMDHDCPGetStatusMsg9MetaClass5allocEv 0000000000052d9c g 0f SECT 01 0000 [.text] __ZNK34AMDRadeonX4000_IAMDHWSemaphorePool12getMetaClassEv 0000000000052ddc g 0f SECT 01 0000 [.text] __ZNK34AMDRadeonX4000_IAMDHWSemaphorePool9MetaClass5allocEv 0000000000025d82 g 0f SECT 01 0000 [.text] __ZNK34AMDRadeonX4000_IAMDStatisticsGroup12getMetaClassEv 0000000000025dc2 g 0f SECT 01 0000 [.text] __ZNK34AMDRadeonX4000_IAMDStatisticsGroup9MetaClass5allocEv 0000000000009542 g 0f SECT 01 0000 [.text] __ZNK35AMDRadeonX4000_AMDAccelEventMachine12getMetaClassEv 0000000000009582 g 0f SECT 01 0000 [.text] __ZNK35AMDRadeonX4000_AMDAccelEventMachine9MetaClass5allocEv 0000000000017f2e g 0f SECT 01 0000 [.text] __ZNK35AMDRadeonX4000_AMDAccelVideoContext12getMetaClassEv 0000000000017f6e g 0f SECT 01 0000 [.text] __ZNK35AMDRadeonX4000_AMDAccelVideoContext9MetaClass5allocEv 0000000000021afc g 0f SECT 01 0000 [.text] __ZNK35AMDRadeonX4000_AMDAtomicBlitManager12getMetaClassEv 0000000000021b3c g 0f SECT 01 0000 [.text] __ZNK35AMDRadeonX4000_AMDAtomicBlitManager9MetaClass5allocEv 0000000000057882 g 0f SECT 01 0000 [.text] __ZNK35AMDRadeonX4000_AMDHWSemaphoreMemMgr12getMetaClassEv 00000000000578c2 g 0f SECT 01 0000 [.text] __ZNK35AMDRadeonX4000_AMDHWSemaphoreMemMgr9MetaClass5allocEv 0000000000126132 g 0f SECT 01 0000 [.text] __ZNK36AMDRadeonX4000_AMDHDCPOpenSessionMsg12getMetaClassEv 0000000000126172 g 0f SECT 01 0000 [.text] __ZNK36AMDRadeonX4000_AMDHDCPOpenSessionMsg9MetaClass5allocEv 000000000005e062 g 0f SECT 01 0000 [.text] __ZNK36AMDRadeonX4000_AMDPM4CommandsUtility12getMetaClassEv 000000000005e0a2 g 0f SECT 01 0000 [.text] __ZNK36AMDRadeonX4000_AMDPM4CommandsUtility9MetaClass5allocEv 0000000000021a22 g 0f SECT 01 0000 [.text] __ZNK36AMDRadeonX4000_IAMDAtomicBlitManager12getMetaClassEv 0000000000021a62 g 0f SECT 01 0000 [.text] __ZNK36AMDRadeonX4000_IAMDAtomicBlitManager9MetaClass5allocEv 0000000000052e76 g 0f SECT 01 0000 [.text] __ZNK36AMDRadeonX4000_IAMDHWSemaphoreMemMgr12getMetaClassEv 0000000000052eb6 g 0f SECT 01 0000 [.text] __ZNK36AMDRadeonX4000_IAMDHWSemaphoreMemMgr9MetaClass5allocEv 0000000000025652 g 0f SECT 01 0000 [.text] __ZNK36AMDRadeonX4000_IAMDStatisticsManager12getMetaClassEv 0000000000025692 g 0f SECT 01 0000 [.text] __ZNK36AMDRadeonX4000_IAMDStatisticsManager9MetaClass5allocEv 0000000000005982 g 0f SECT 01 0000 [.text] __ZNK37AMDRadeonX4000_AMDAccelDisplayMachine12getMetaClassEv 00000000000059c2 g 0f SECT 01 0000 [.text] __ZNK37AMDRadeonX4000_AMDAccelDisplayMachine9MetaClass5allocEv 000000000012751c g 0f SECT 01 0000 [.text] __ZNK37AMDRadeonX4000_AMDFPReleaseSessionMsg12getMetaClassEv 000000000012755c g 0f SECT 01 0000 [.text] __ZNK37AMDRadeonX4000_AMDFPReleaseSessionMsg9MetaClass5allocEv 0000000000001462 g 0f SECT 01 0000 [.text] __ZNK37AMDRadeonX4000_AMDGraphicsAccelerator12getMetaClassEv 00000000000014a2 g 0f SECT 01 0000 [.text] __ZNK37AMDRadeonX4000_AMDGraphicsAccelerator9MetaClass5allocEv 0000000000126428 g 0f SECT 01 0000 [.text] __ZNK37AMDRadeonX4000_AMDHDCPCloseSessionMsg12getMetaClassEv 0000000000126468 g 0f SECT 01 0000 [.text] __ZNK37AMDRadeonX4000_AMDHDCPCloseSessionMsg9MetaClass5allocEv 00000000000262e2 g 0f SECT 01 0000 [.text] __ZNK37AMDRadeonX4000_AMDHWChannelStatsGroup12getMetaClassEv 0000000000026322 g 0f SECT 01 0000 [.text] __ZNK37AMDRadeonX4000_AMDHWChannelStatsGroup9MetaClass5allocEv 000000000005302a g 0f SECT 01 0000 [.text] __ZNK37AMDRadeonX4000_IAMDPM4CommandsUtility12getMetaClassEv 000000000005306a g 0f SECT 01 0000 [.text] __ZNK37AMDRadeonX4000_IAMDPM4CommandsUtility9MetaClass5allocEv 0000000000025e7c g 0f SECT 01 0000 [.text] __ZNK38AMDRadeonX4000_AMDAccelStatisticsGroup12getMetaClassEv 0000000000025ebc g 0f SECT 01 0000 [.text] __ZNK38AMDRadeonX4000_AMDAccelStatisticsGroup9MetaClass5allocEv 0000000000016e52 g 0f SECT 01 0000 [.text] __ZNK38AMDRadeonX4000_AMDInterruptEventSource12getMetaClassEv 0000000000016e92 g 0f SECT 01 0000 [.text] __ZNK38AMDRadeonX4000_AMDInterruptEventSource9MetaClass5allocEv 000000000001217c g 0f SECT 01 0000 [.text] __ZNK39AMDRadeonX4000_AMDAccelSharedUserClient12getMetaClassEv 00000000000121bc g 0f SECT 01 0000 [.text] __ZNK39AMDRadeonX4000_AMDAccelSharedUserClient9MetaClass5allocEv 0000000000016c32 g 0f SECT 01 0000 [.text] __ZNK40AMDRadeonX4000_AMDAccelCommandBufferPool12getMetaClassEv 0000000000016c72 g 0f SECT 01 0000 [.text] __ZNK40AMDRadeonX4000_AMDAccelCommandBufferPool9MetaClass5allocEv 000000000002574c g 0f SECT 01 0000 [.text] __ZNK40AMDRadeonX4000_AMDAccelStatisticsManager12getMetaClassEv 000000000002578c g 0f SECT 01 0000 [.text] __ZNK40AMDRadeonX4000_AMDAccelStatisticsManager9MetaClass5allocEv 000000000004e392 g 0f SECT 01 0000 [.text] __ZNK41AMDRadeonX4000_AMDUVDInterruptEventSource12getMetaClassEv 000000000004e3d2 g 0f SECT 01 0000 [.text] __ZNK41AMDRadeonX4000_AMDUVDInterruptEventSource9MetaClass5allocEv 000000000009deb2 g 0f SECT 01 0000 [.text] __ZNK6BltMgr10DebugPrintEPcz 000000000009900c g 0f SECT 01 0000 [.text] __ZNK6BltMgr10FreeSysMemEPv 000000000009d9dc g 0f SECT 01 0000 [.text] __ZNK6BltMgr10FreeVidMemEPv 000000000009da06 g 0f SECT 01 0000 [.text] __ZNK6BltMgr10LockVidMemEPv13LARGE_INTEGER 0000000000098f5c g 0f SECT 01 0000 [.text] __ZNK6BltMgr11AllocSysMemEj 000000000009a252 g 0f SECT 01 0000 [.text] __ZNK6BltMgr11IsBufferBltEPK7BltInfo 000000000009ff06 g 0f SECT 01 0000 [.text] __ZNK6BltMgr12IsTileMode1dEPK13_UBM_SURFINFO 000000000009ff24 g 0f SECT 01 0000 [.text] __ZNK6BltMgr12IsTileMode2dEPK13_UBM_SURFINFO 000000000009da42 g 0f SECT 01 0000 [.text] __ZNK6BltMgr12UnlockVidMemEPv 0000000000098f86 g 0f SECT 01 0000 [.text] __ZNK6BltMgr13GetSampleLocsEPK7BltInfojPj 000000000009db54 g 0f SECT 01 0000 [.text] __ZNK6BltMgr14VerifyCmdSpaceEPvjj 000000000009ff42 g 0f SECT 01 0000 [.text] __ZNK6BltMgr15IsTileModeThickEPK13_UBM_SURFINFO 000000000009fee8 g 0f SECT 01 0000 [.text] __ZNK6BltMgr15IsTileModeTiledEPK13_UBM_SURFINFO 000000000009da74 g 0f SECT 01 0000 [.text] __ZNK6BltMgr15ReportDrawCountEPvP7BltInfo 000000000009fece g 0f SECT 01 0000 [.text] __ZNK6BltMgr16IsTileModeLinearEPK13_UBM_SURFINFO 000000000009dbb0 g 0f SECT 01 0000 [.text] __ZNK6BltMgr16VerifyCmdSpaceExEPvjjP17_UBM_CMDBUF_STATE 0000000000098e1c g 0f SECT 01 0000 [.text] __ZNK6BltMgr17NumColorFragmentsEPK13_UBM_SURFINFO 000000000009a2e0 g 0f SECT 01 0000 [.text] __ZNK6BltMgr17OptimizeClipRectsEP7BltInfo 000000000009dab0 g 0f SECT 01 0000 [.text] __ZNK6BltMgr19NotifyPreambleAddedEPv18_UBM_PREAMBLE_TYPE 00000000000970d4 g 0f SECT 01 0000 [.text] __ZNK6BltMgr20FindUnknSampReplFragEP7BltInfojP12_UBM_VECTORL 000000000009de88 g 0f SECT 01 0000 [.text] __ZNK6BltMgr20GetCmdBufFreeEntriesEPv 0000000000096cd2 g 0f SECT 01 0000 [.text] __ZNK6BltMgr21ComputeGridNormConstsEP7BltInfoijjP11_UBM_VECTORS3_S3_ 000000000009b884 g 0f SECT 01 0000 [.text] __ZNK6BltMgr22IsLinearGeneralSurfaceEPK13_UBM_SURFINFO 000000000009dac8 g 0f SECT 01 0000 [.text] __ZNK6BltMgr25CreateCriticalSectionLockEPPv 000000000009bc54 g 0f SECT 01 0000 [.text] __ZNK6BltMgr25IsVerifyCmdSpaceExSupportEv 000000000009daf4 g 0f SECT 01 0000 [.text] __ZNK6BltMgr26DestroyCriticalSectionLockEPv 000000000009dc14 g 0f SECT 01 0000 [.text] __ZNK6BltMgr5FlushEPv 000000000009da58 g 0f SECT 01 0000 [.text] __ZNK6BltMgr7BltSyncEPvPK18_UBM_BLTSYNC_INPUT 000000000009fdb8 g 0f SECT 01 0000 [.text] __ZNK6BltMgr8IsBufferEPK13_UBM_SURFINFO 00000000000d0578 g 0f SECT 01 0000 [.text] __ZNK7AddrLib11HwlGetPipesEPK14_ADDR_TILEINFO 00000000000ce9f2 g 0f SECT 01 0000 [.text] __ZNK7AddrLib12GetTileIndexEPK25_ADDR_GET_TILEINDEX_INPUTP26_ADDR_GET_TILEINDEX_OUTPUT 00000000000d06b2 g 0f SECT 01 0000 [.text] __ZNK7AddrLib13GetExportNormEPK25_ELEM_GETEXPORTNORM_INPUT 00000000000d01be g 0f SECT 01 0000 [.text] __ZNK7AddrLib13PadDimensionsE13_AddrTileModej19_ADDR_SURFACE_FLAGSjP14_ADDR_TILEINFOjjPjjS4_jS4_j 00000000000ceff0 g 0f SECT 01 0000 [.text] __ZNK7AddrLib14ComputeDccInfoEPK27_ADDR_COMPUTE_DCCINFO_INPUTP28_ADDR_COMPUTE_DCCINFO_OUTPUT 00000000000d06da g 0f SECT 01 0000 [.text] __ZNK7AddrLib14ComputePrtInfoEPK20_ADDR_PRT_INFO_INPUTP21_ADDR_PRT_INFO_OUTPUT 00000000000cdf80 g 0f SECT 01 0000 [.text] __ZNK7AddrLib15ComputeMipLevelEP32_ADDR_COMPUTE_SURFACE_INFO_INPUT 00000000000d056c g 0f SECT 01 0000 [.text] __ZNK7AddrLib15HwlSetupTileCfgEiiP14_ADDR_TILEINFOP13_AddrTileModeP13_AddrTileType 00000000000cee14 g 0f SECT 01 0000 [.text] __ZNK7AddrLib16ComputeCmaskInfoE17_ADDR_CMASK_FLAGSjjjiP14_ADDR_TILEINFOPjS3_PyS3_S3_S4_S3_S3_ 00000000000ced00 g 0f SECT 01 0000 [.text] __ZNK7AddrLib16ComputeCmaskInfoEPK29_ADDR_COMPUTE_CMASKINFO_INPUTP31_ADDR_COMPUTE_CMASK_INFO_OUTPUT 00000000000ceb62 g 0f SECT 01 0000 [.text] __ZNK7AddrLib16ComputeHtileInfoE17_ADDR_HTILE_FLAGSjjjiiiP14_ADDR_TILEINFOPjS3_PyS3_S3_S4_S3_ 00000000000cea1a g 0f SECT 01 0000 [.text] __ZNK7AddrLib16ComputeHtileInfoEPK30_ADDR_COMPUTE_HTILE_INFO_INPUTP31_ADDR_COMPUTE_HTILE_INFO_OUTPUT 00000000000ce88a g 0f SECT 01 0000 [.text] __ZNK7AddrLib16ConvertTileIndexEPK29_ADDR_CONVERT_TILEINDEX_INPUTP30_ADDR_CONVERT_TILEINDEX_OUTPUT 00000000000ce098 g 0f SECT 01 0000 [.text] __ZNK7AddrLib16DegradeBaseLevelEPK32_ADDR_COMPUTE_SURFACE_INFO_INPUTP13_AddrTileMode 00000000000cf5ec g 0f SECT 01 0000 [.text] __ZNK7AddrLib17ComputeCmaskBytesEjjj 00000000000ce930 g 0f SECT 01 0000 [.text] __ZNK7AddrLib17ConvertTileIndex1EPK30_ADDR_CONVERT_TILEINDEX1_INPUTP30_ADDR_CONVERT_TILEINDEX_OUTPUT 00000000000d0674 g 0f SECT 01 0000 [.text] __ZNK7AddrLib17Flt32ToColorPixelEPK29_ELEM_FLT32TOCOLORPIXEL_INPUTP30_ELEM_FLT32TOCOLORPIXEL_OUTPUT 00000000000d05ce g 0f SECT 01 0000 [.text] __ZNK7AddrLib17Flt32ToDepthPixelEPK29_ELEM_FLT32TODEPTHPIXEL_INPUTP30_ELEM_FLT32TODEPTHPIXEL_OUTPUT 00000000000ce57e g 0f SECT 01 0000 [.text] __ZNK7AddrLib18ComputeBaseSwizzleEPK32_ADDR_COMPUTE_BASE_SWIZZLE_INPUTP33_ADDR_COMPUTE_BASE_SWIZZLE_OUTPUT 00000000000cdb8c g 0f SECT 01 0000 [.text] __ZNK7AddrLib18ComputeSurfaceInfoEPK32_ADDR_COMPUTE_SURFACE_INFO_INPUTP33_ADDR_COMPUTE_SURFACE_INFO_OUTPUT 00000000000cf8f2 g 0f SECT 01 0000 [.text] __ZNK7AddrLib19ComputePipeFromAddrEyy 00000000000d0582 g 0f SECT 01 0000 [.text] __ZNK7AddrLib19ComputeQbStereoInfoEP33_ADDR_COMPUTE_SURFACE_INFO_OUTPUT 00000000000ce7fc g 0f SECT 01 0000 [.text] __ZNK7AddrLib19ConvertTileInfoToHWEPK32_ADDR_CONVERT_TILEINFOTOHW_INPUTP33_ADDR_CONVERT_TILEINFOTOHW_OUTPUT 00000000000cdfce g 0f SECT 01 0000 [.text] __ZNK7AddrLib19PostComputeMipLevelEP32_ADDR_COMPUTE_SURFACE_INFO_INPUTP33_ADDR_COMPUTE_SURFACE_INFO_OUTPUT 00000000000d0188 g 0f SECT 01 0000 [.text] __ZNK7AddrLib20AdjustPitchAlignmentE19_ADDR_SURFACE_FLAGSPj 00000000000cf5ae g 0f SECT 01 0000 [.text] __ZNK7AddrLib21ComputeCmaskBaseAlignE17_ADDR_CMASK_FLAGSP14_ADDR_TILEINFO 00000000000d04aa g 0f SECT 01 0000 [.text] __ZNK7AddrLib21DegradeLargeThickTileE13_AddrTileModej 00000000000ce4bc g 0f SECT 01 0000 [.text] __ZNK7AddrLib22CombineBankPipeSwizzleEPK36_ADDR_COMBINE_BANKPIPE_SWIZZLE_INPUTP37_ADDR_COMBINE_BANKPIPE_SWIZZLE_OUTPUT 00000000000ce434 g 0f SECT 01 0000 [.text] __ZNK7AddrLib22ExtractBankPipeSwizzleEPK36_ADDR_EXTRACT_BANKPIPE_SWIZZLE_INPUTP37_ADDR_EXTRACT_BANKPIPE_SWIZZLE_OUTPUT 00000000000ce39a g 0f SECT 01 0000 [.text] __ZNK7AddrLib23ComputeSliceTileSwizzleEPK32_ADDR_COMPUTE_SLICESWIZZLE_INPUTP33_ADDR_COMPUTE_SLICESWIZZLE_OUTPUT 00000000000cf316 g 0f SECT 01 0000 [.text] __ZNK7AddrLib25ComputeCmaskAddrFromCoordEPK39_ADDR_COMPUTE_CMASK_ADDRFROMCOORD_INPUTP40_ADDR_COMPUTE_CMASK_ADDRFROMCOORD_OUTPUT 00000000000cf416 g 0f SECT 01 0000 [.text] __ZNK7AddrLib25ComputeCmaskCoordFromAddrEPK39_ADDR_COMPUTE_CMASK_COORDFROMADDR_INPUTP40_ADDR_COMPUTE_CMASK_COORDFROMADDR_OUTPUT 00000000000ce79c g 0f SECT 01 0000 [.text] __ZNK7AddrLib25ComputeFmaskAddrFromCoordEPK39_ADDR_COMPUTE_FMASK_ADDRFROMCOORD_INPUTP40_ADDR_COMPUTE_FMASK_ADDRFROMCOORD_OUTPUT 00000000000ce7cc g 0f SECT 01 0000 [.text] __ZNK7AddrLib25ComputeFmaskCoordFromAddrEPK39_ADDR_COMPUTE_FMASK_COORDFROMADDR_INPUTP40_ADDR_COMPUTE_FMASK_COORDFROMADDR_OUTPUT 00000000000cf0a4 g 0f SECT 01 0000 [.text] __ZNK7AddrLib25ComputeHtileAddrFromCoordEPK39_ADDR_COMPUTE_HTILE_ADDRFROMCOORD_INPUTP40_ADDR_COMPUTE_HTILE_ADDRFROMCOORD_OUTPUT 00000000000cf1d8 g 0f SECT 01 0000 [.text] __ZNK7AddrLib25ComputeHtileCoordFromAddrEPK39_ADDR_COMPUTE_HTILE_COORDFROMADDR_INPUTP40_ADDR_COMPUTE_HTILE_COORDFROMADDR_OUTPUT 00000000000cf60c g 0f SECT 01 0000 [.text] __ZNK7AddrLib26ComputeXmaskCoordYFromPipeEjj 00000000000d0310 g 0f SECT 01 0000 [.text] __ZNK7AddrLib26HwlPreHandleBaseLvl3xPitchEPK32_ADDR_COMPUTE_SURFACE_INFO_INPUTj 00000000000ce18c g 0f SECT 01 0000 [.text] __ZNK7AddrLib27ComputeSurfaceAddrFromCoordEPK41_ADDR_COMPUTE_SURFACE_ADDRFROMCOORD_INPUTP42_ADDR_COMPUTE_SURFACE_ADDRFROMCOORD_OUTPUT 00000000000ce29c g 0f SECT 01 0000 [.text] __ZNK7AddrLib27ComputeSurfaceCoordFromAddrEPK41_ADDR_COMPUTE_SURFACE_COORDFROMADDR_INPUTP42_ADDR_COMPUTE_SURFACE_COORDFROMADDR_OUTPUT 00000000000d035c g 0f SECT 01 0000 [.text] __ZNK7AddrLib27HwlPostHandleBaseLvl3xPitchEPK32_ADDR_COMPUTE_SURFACE_INFO_INPUTj 00000000000cf91a g 0f SECT 01 0000 [.text] __ZNK7AddrLib28HwlComputeXmaskAddrFromCoordEjjjjjjjiiiP14_ADDR_TILEINFOPj 00000000000cf64e g 0f SECT 01 0000 [.text] __ZNK7AddrLib28HwlComputeXmaskCoordFromAddrEyjjjjjiiiP14_ADDR_TILEINFOPjS2_S2_ 00000000000cf530 g 0f SECT 01 0000 [.text] __ZNK7AddrLib29ComputeTileDataWidthAndHeightEjjP14_ADDR_TILEINFOPjS2_ 00000000000cfe10 g 0f SECT 01 0000 [.text] __ZNK7AddrLib32ComputePixelIndexWithinMicroTileEjjjj13_AddrTileMode13_AddrTileType 00000000000cfc28 g 0f SECT 01 0000 [.text] __ZNK7AddrLib33ComputeSurfaceAddrFromCoordLinearEjjjjjjjjPj 00000000000cfc64 g 0f SECT 01 0000 [.text] __ZNK7AddrLib33ComputeSurfaceCoordFromAddrLinearEyjjjjjPjS0_S0_S0_ 00000000000cfcc0 g 0f SECT 01 0000 [.text] __ZNK7AddrLib37ComputeSurfaceCoordFromAddrMicroTiledEyjjjjj13_AddrTileModejjPjS1_S1_S1_13_AddrTileTypei 00000000000cf590 g 0f SECT 01 0000 [.text] __ZNK7AddrLib38HwlComputeTileDataWidthAndHeightLinearEPjS0_jP14_ADDR_TILEINFO 0000000000066682 g 0f SECT 01 0000 [.text] __ZNK8AMDSIVMM12getMetaClassEv 00000000000666c2 g 0f SECT 01 0000 [.text] __ZNK8AMDSIVMM9MetaClass5allocEv 00000000000892b2 g 0f SECT 01 0000 [.text] __ZNK8AMDVIVMM12getMetaClassEv 00000000000892f2 g 0f SECT 01 0000 [.text] __ZNK8AMDVIVMM9MetaClass5allocEv 00000000000baa20 g 0f SECT 01 0000 [.text] __ZNK8SiBltMgr15HwlRenderWithDBEPK13_UBM_SURFINFO 00000000000b5d7a g 0f SECT 01 0000 [.text] __ZNK8SiBltMgr17ShouldEnableGammaEPK7BltInfo 00000000000b76ca g 0f SECT 01 0000 [.text] __ZNK8SiBltMgr17SizeWriteVgtEventEv 00000000000bb454 g 0f SECT 01 0000 [.text] __ZNK8SiBltMgr18ClientSyncCpDmaBltEPK7BltInfo 00000000000ba950 g 0f SECT 01 0000 [.text] __ZNK8SiBltMgr18HwlCanUseCBResolveEPK13_UBM_SURFINFOS2_ 00000000000b5d50 g 0f SECT 01 0000 [.text] __ZNK8SiBltMgr18HwlSetTilingParamsEP13_UBM_SURFINFO14_UBM_TILE_MODE14_UBM_TILE_TYPEj 00000000000b9e8a g 0f SECT 01 0000 [.text] __ZNK8SiBltMgr19ClientSync3dDrawBltEPK7BltInfo 00000000000cbdf0 g 0f SECT 01 0000 [.text] __ZNK8SiBltMgr19ClientSyncDrmDmaBltEPK7BltInfo 00000000000b5af0 g 0f SECT 01 0000 [.text] __ZNK8SiBltMgr20GetFMaskBitsPerIndexEPK13_UBM_SURFINFO 00000000000b6830 g 0f SECT 01 0000 [.text] __ZNK8SiBltMgr23ClientSync3dDispatchBltEPK7BltInfo 00000000000ba8aa g 0f SECT 01 0000 [.text] __ZNK8SiBltMgr25ComputeNumClipRectEntriesEPK7BltInfo 00000000000b76b2 g 0f SECT 01 0000 [.text] __ZNK8SiBltMgr30Compute3dDrawPreBltSyncEntriesEPK7BltInfo 00000000000b76be g 0f SECT 01 0000 [.text] __ZNK8SiBltMgr31Compute3dDrawPostBltSyncEntriesEPK7BltInfo 00000000000a2e52 g 0f SECT 01 0000 [.text] __ZNK9BltResFmt10GetResInfoE11_UBM_FORMATj 00000000000a6f40 g 0f SECT 01 0000 [.text] __ZNK9BltResFmt11ConvertFromE11_UBM_FORMATPKvjP11_UBM_VECTORj 00000000000a68e4 g 0f SECT 01 0000 [.text] __ZNK9BltResFmt13BytesPerPixelE11_UBM_FORMATj 00000000000a6c50 g 0f SECT 01 0000 [.text] __ZNK9BltResFmt15CompBitCountMaxE11_UBM_FORMAT 00000000000a6b20 g 0f SECT 01 0000 [.text] __ZNK9BltResFmt20ConvertFormatForCopyE11_UBM_FORMAT 00000000000a6d30 g 0f SECT 01 0000 [.text] __ZNK9BltResFmt9ConvertToE11_UBM_FORMATPK11_UBM_VECTORjPvjj 00000000000d6abc g 0f SECT 01 0000 [.text] __ZNK9CIAddrLib14ReadGbTileModeEjP15ADDR_TILECONFIG 00000000000d632a g 0f SECT 01 0000 [.text] __ZNK9CIAddrLib15HwlSetupTileCfgEiiP14_ADDR_TILEINFOP13_AddrTileModeP13_AddrTileType 00000000000d6ede g 0f SECT 01 0000 [.text] __ZNK9CIAddrLib16HwlPadDimensionsE13_AddrTileModej19_ADDR_SURFACE_FLAGSjP14_ADDR_TILEINFOjjPjjS4_jS4_j 00000000000d6700 g 0f SECT 01 0000 [.text] __ZNK9CIAddrLib16HwlSetupTileInfoE13_AddrTileMode19_ADDR_SURFACE_FLAGSjjjjP14_ADDR_TILEINFOS3_13_AddrTileTypeP33_ADDR_COMPUTE_SURFACE_INFO_OUTPUT 00000000000d5b2e g 0f SECT 01 0000 [.text] __ZNK9CIAddrLib17HwlComputeDccInfoEPK27_ADDR_COMPUTE_DCCINFO_INPUTP28_ADDR_COMPUTE_DCCINFO_OUTPUT 00000000000d6be8 g 0f SECT 01 0000 [.text] __ZNK9CIAddrLib18ReadGbMacroTileCfgEjP14_ADDR_TILEINFO 00000000000d65f0 g 0f SECT 01 0000 [.text] __ZNK9CIAddrLib19HwlOverrideTileModeEPK32_ADDR_COMPUTE_SURFACE_INFO_INPUTP13_AddrTileModeP13_AddrTileType 00000000000d6414 g 0f SECT 01 0000 [.text] __ZNK9CIAddrLib21HwlComputeSurfaceInfoEPK32_ADDR_COMPUTE_SURFACE_INFO_INPUTP33_ADDR_COMPUTE_SURFACE_INFO_OUTPUT 00000000000d624c g 0f SECT 01 0000 [.text] __ZNK9CIAddrLib21HwlPostCheckTileIndexEPK14_ADDR_TILEINFO13_AddrTileMode13_AddrTileTypei 00000000000d65e8 g 0f SECT 01 0000 [.text] __ZNK9CIAddrLib23HwlDegradeThickTileModeE13_AddrTileModejPj 00000000000d6c3a g 0f SECT 01 0000 [.text] __ZNK9CIAddrLib24HwlComputeMacroModeIndexEi19_ADDR_SURFACE_FLAGSjjP14_ADDR_TILEINFOP13_AddrTileModeP13_AddrTileType 00000000000d65c2 g 0f SECT 01 0000 [.text] __ZNK9CIAddrLib24HwlFmaskPreThunkSurfInfoEPK30_ADDR_COMPUTE_FMASK_INFO_INPUTPK31_ADDR_COMPUTE_FMASK_INFO_OUTPUTP32_ADDR_COMPUTE_SURFACE_INFO_INPUTP33_ADDR_COMPUTE_SURFACE_INFO_OUTPUT 00000000000d65d6 g 0f SECT 01 0000 [.text] __ZNK9CIAddrLib25HwlFmaskPostThunkSurfInfoEPK33_ADDR_COMPUTE_SURFACE_INFO_OUTPUTP31_ADDR_COMPUTE_FMASK_INFO_OUTPUT 00000000000d5c70 g 0f SECT 01 0000 [.text] __ZNK9CIAddrLib28HwlComputeCmaskAddrFromCoordEPK39_ADDR_COMPUTE_CMASK_ADDRFROMCOORD_INPUTP40_ADDR_COMPUTE_CMASK_ADDRFROMCOORD_OUTPUT 00000000000d5d1e g 0f SECT 01 0000 [.text] __ZNK9CIAddrLib31HwlComputeMetadataNibbleAddressEyyyjjjjjjj 00000000000d6e2e g 0f SECT 01 0000 [.text] __ZNK9CIAddrLib32HwlStereoCheckRightOffsetPaddingEv 00000000000d6e06 g 0f SECT 01 0000 [.text] __ZNK9CIAddrLib38HwlComputeTileDataWidthAndHeightLinearEPjS0_jP14_ADDR_TILEINFO 00000000000d35b4 g 0f SECT 01 0000 [.text] __ZNK9SIAddrLib11HwlGetPipesEPK14_ADDR_TILEINFO 00000000000d3640 g 0f SECT 01 0000 [.text] __ZNK9SIAddrLib14GetPipePerSurfE12_AddrPipeCfg 00000000000d559c g 0f SECT 01 0000 [.text] __ZNK9SIAddrLib14GetTileSettingEj 00000000000d57a6 g 0f SECT 01 0000 [.text] __ZNK9SIAddrLib14ReadGbTileModeEjP15ADDR_TILECONFIG 00000000000d5840 g 0f SECT 01 0000 [.text] __ZNK9SIAddrLib15HwlGetTileIndexEPK25_ADDR_GET_TILEINDEX_INPUTP26_ADDR_GET_TILEINDEX_OUTPUT 00000000000d56ac g 0f SECT 01 0000 [.text] __ZNK9SIAddrLib15HwlSetupTileCfgEiiP14_ADDR_TILEINFOP13_AddrTileModeP13_AddrTileType 00000000000d540c g 0f SECT 01 0000 [.text] __ZNK9SIAddrLib16HwlPreAdjustBankEjjP14_ADDR_TILEINFO 00000000000d49a6 g 0f SECT 01 0000 [.text] __ZNK9SIAddrLib16HwlSetupTileInfoE13_AddrTileMode19_ADDR_SURFACE_FLAGSjjjjP14_ADDR_TILEINFOS3_13_AddrTileTypeP33_ADDR_COMPUTE_SURFACE_INFO_OUTPUT 00000000000d557e g 0f SECT 01 0000 [.text] __ZNK9SIAddrLib16HwlTileInfoEqualEPK14_ADDR_TILEINFOS2_ 00000000000d5452 g 0f SECT 01 0000 [.text] __ZNK9SIAddrLib18HwlComputeMipLevelEP32_ADDR_COMPUTE_SURFACE_INFO_INPUT 00000000000d588e g 0f SECT 01 0000 [.text] __ZNK9SIAddrLib19HwlComputeFmaskBitsEPK30_ADDR_COMPUTE_FMASK_INFO_INPUTPj 00000000000d5948 g 0f SECT 01 0000 [.text] __ZNK9SIAddrLib19HwlOverrideTileModeEPK32_ADDR_COMPUTE_SURFACE_INFO_INPUTP13_AddrTileModeP13_AddrTileType 00000000000d36c4 g 0f SECT 01 0000 [.text] __ZNK9SIAddrLib20ComputePipeFromCoordEjjj13_AddrTileModejiP14_ADDR_TILEINFO 00000000000d4138 g 0f SECT 01 0000 [.text] __ZNK9SIAddrLib20HwlComputeHtileBytesEjjjijPyj 00000000000d543c g 0f SECT 01 0000 [.text] __ZNK9SIAddrLib21HwlComputeSurfaceInfoEPK32_ADDR_COMPUTE_SURFACE_INFO_INPUTP33_ADDR_COMPUTE_SURFACE_INFO_OUTPUT 00000000000d55ae g 0f SECT 01 0000 [.text] __ZNK9SIAddrLib21HwlPostCheckTileIndexEPK14_ADDR_TILEINFO13_AddrTileMode13_AddrTileTypei 00000000000d4fc2 g 0f SECT 01 0000 [.text] __ZNK9SIAddrLib22HwlConvertTileInfoToHWEPK32_ADDR_CONVERT_TILEINFOTOHW_INPUTP33_ADDR_CONVERT_TILEINFOTOHW_OUTPUT 00000000000d556c g 0f SECT 01 0000 [.text] __ZNK9SIAddrLib23HwlDegradeThickTileModeE13_AddrTileModejPj 00000000000d586e g 0f SECT 01 0000 [.text] __ZNK9SIAddrLib24HwlFmaskPreThunkSurfInfoEPK30_ADDR_COMPUTE_FMASK_INFO_INPUTPK31_ADDR_COMPUTE_FMASK_INFO_OUTPUTP32_ADDR_COMPUTE_SURFACE_INFO_INPUTP33_ADDR_COMPUTE_SURFACE_INFO_OUTPUT 00000000000d548e g 0f SECT 01 0000 [.text] __ZNK9SIAddrLib25HwlCheckLastMacroTiledLvlEPK32_ADDR_COMPUTE_SURFACE_INFO_INPUTP33_ADDR_COMPUTE_SURFACE_INFO_OUTPUT 00000000000d587a g 0f SECT 01 0000 [.text] __ZNK9SIAddrLib25HwlFmaskPostThunkSurfInfoEPK33_ADDR_COMPUTE_SURFACE_INFO_OUTPUTP31_ADDR_COMPUTE_FMASK_INFO_OUTPUT 00000000000d473e g 0f SECT 01 0000 [.text] __ZNK9SIAddrLib26HwlGetPitchAlignmentLinearEj19_ADDR_SURFACE_FLAGS 00000000000d4782 g 0f SECT 01 0000 [.text] __ZNK9SIAddrLib26HwlGetSizeAdjustmentLinearE13_AddrTileModejjjjPjS1_S1_ 00000000000d4824 g 0f SECT 01 0000 [.text] __ZNK9SIAddrLib26HwlPreHandleBaseLvl3xPitchEPK32_ADDR_COMPUTE_SURFACE_INFO_INPUTj 00000000000d484a g 0f SECT 01 0000 [.text] __ZNK9SIAddrLib27HwlPostHandleBaseLvl3xPitchEPK32_ADDR_COMPUTE_SURFACE_INFO_INPUTj 00000000000d3fb4 g 0f SECT 01 0000 [.text] __ZNK9SIAddrLib27TileCoordToMaskElementIndexEjj12_AddrPipeCfgPjS1_ 00000000000d4142 g 0f SECT 01 0000 [.text] __ZNK9SIAddrLib28HwlComputeXmaskAddrFromCoordEjjjjjjjiiiP14_ADDR_TILEINFOPj 00000000000d4406 g 0f SECT 01 0000 [.text] __ZNK9SIAddrLib28HwlComputeXmaskCoordFromAddrEyjjjjjiiiP14_ADDR_TILEINFOPjS2_S2_ 00000000000d500e g 0f SECT 01 0000 [.text] __ZNK9SIAddrLib30HwlComputeXmaskCoordYFrom8PipeEjj 00000000000d4870 g 0f SECT 01 0000 [.text] __ZNK9SIAddrLib30HwlGetPitchAlignmentMicroTiledE13_AddrTileModej19_ADDR_SURFACE_FLAGSj 00000000000d488e g 0f SECT 01 0000 [.text] __ZNK9SIAddrLib30HwlGetSizeAdjustmentMicroTiledEjj19_ADDR_SURFACE_FLAGSjjjPjS1_ 00000000000d3998 g 0f SECT 01 0000 [.text] __ZNK9SIAddrLib34ComputeTileCoordFromPipeAndElemIdxEjj12_AddrPipeCfgjjjPjS1_ 00000000000d5016 g 0f SECT 01 0000 [.text] __ZNK9SIAddrLib36HwlComputeSurfaceCoord2DFromBankPipeE13_AddrTileModePjS1_jjjjjjiP14_ADDR_TILEINFO 00000000000d4110 g 0f SECT 01 0000 [.text] __ZNK9SIAddrLib38HwlComputeTileDataWidthAndHeightLinearEPjS0_jP14_ADDR_TILEINFO 00000000003be550 g 0f SECT 08 0000 [.const_data] __ZTV10AddrObject 00000000003bdc90 g 0f SECT 08 0000 [.const_data] __ZTV10AuxSurfMgr 00000000003b9910 g 0f SECT 08 0000 [.const_data] __ZTV11AMDVIHWGart 00000000003be6e0 g 0f SECT 08 0000 [.const_data] __ZTV11AddrElemLib 00000000003be710 g 0f SECT 08 0000 [.const_data] __ZTV11R800AddrLib 00000000003be1c0 g 0f SECT 08 0000 [.const_data] __ZTV11SiBltDevice 00000000003be360 g 0f SECT 08 0000 [.const_data] __ZTV11SiBltResFmt 00000000003be390 g 0f SECT 08 0000 [.const_data] __ZTV11SiBltShader 00000000003b4970 g 0f SECT 08 0000 [.const_data] __ZTV12AMDCIDisplay 00000000003b7d60 g 0f SECT 08 0000 [.const_data] __ZTV12AMDCIVCERing 00000000003af220 g 0f SECT 08 0000 [.const_data] __ZTV12AMDSIDMARing 00000000003aaa00 g 0f SECT 08 0000 [.const_data] __ZTV12AMDSIDisplay 00000000003b19e0 g 0f SECT 08 0000 [.const_data] __ZTV12AMDSISPURing 0000000000397700 g 0f SECT 08 0000 [.const_data] __ZTV12AMDSISurface 00000000003b0f40 g 0f SECT 08 0000 [.const_data] __ZTV12AMDSIUVDRing 00000000003b00a0 g 0f SECT 08 0000 [.const_data] __ZTV12AMDSIVCERing 00000000003ba550 g 0f SECT 08 0000 [.const_data] __ZTV12AMDVIDisplay 00000000003b4df0 g 0f SECT 08 0000 [.const_data] __ZTV13AMDCIHWMemory 00000000003b2420 g 0f SECT 08 0000 [.const_data] __ZTV13AMDCIHardware 000000000039d0e0 g 0f SECT 08 0000 [.const_data] __ZTV13AMDCIResource 00000000003b4390 g 0f SECT 08 0000 [.const_data] __ZTV13AMDCIsDMARing 00000000003aa680 g 0f SECT 08 0000 [.const_data] __ZTV13AMDSIHWMemory 00000000003ab6c0 g 0f SECT 08 0000 [.const_data] __ZTV13AMDSIHardware 00000000003972c0 g 0f SECT 08 0000 [.const_data] __ZTV13AMDSIResource 00000000003b9bf0 g 0f SECT 08 0000 [.const_data] __ZTV13AMDVIHWMemory 00000000003b8ab0 g 0f SECT 08 0000 [.const_data] __ZTV13AMDVIHardware 00000000003a0370 g 0f SECT 08 0000 [.const_data] __ZTV13AMDVIResource 00000000003bb370 g 0f SECT 08 0000 [.const_data] __ZTV13AMDVIsDMARing 00000000003be030 g 0f SECT 08 0000 [.const_data] __ZTV13SurfAttribute 000000000039d5b0 g 0f SECT 08 0000 [.const_data] __ZTV14AMDCICLContext 00000000003b39b0 g 0f SECT 08 0000 [.const_data] __ZTV14AMDCIPM4Engine 000000000039a180 g 0f SECT 08 0000 [.const_data] __ZTV14AMDSICLContext 00000000003aeaf0 g 0f SECT 08 0000 [.const_data] __ZTV14AMDSIDMAEngine 0000000000399470 g 0f SECT 08 0000 [.const_data] __ZTV14AMDSIGLContext 00000000003ad660 g 0f SECT 08 0000 [.const_data] __ZTV14AMDSIPM4Engine 00000000003b1260 g 0f SECT 08 0000 [.const_data] __ZTV14AMDSISPUEngine 00000000003ab0e0 g 0f SECT 08 0000 [.const_data] __ZTV14AMDSIVMContext 00000000003bc3a0 g 0f SECT 08 0000 [.const_data] __ZTV14AMDVIPM4Engine 00000000003b9f70 g 0f SECT 08 0000 [.const_data] __ZTV14AMDVIVMContext 00000000003becb0 g 0f SECT 08 0000 [.const_data] __ZTV14EgBasedAddrLib 00000000003b57f0 g 0f SECT 08 0000 [.const_data] __ZTV15AMDCIDMAChannel 00000000003b53e0 g 0f SECT 08 0000 [.const_data] __ZTV15AMDCIPM4Channel 00000000003b5bf0 g 0f SECT 08 0000 [.const_data] __ZTV15AMDCISAMUEngine 00000000003b7600 g 0f SECT 08 0000 [.const_data] __ZTV15AMDCIVCEChannel 00000000003b8080 g 0f SECT 08 0000 [.const_data] __ZTV15AMDCIVCELLQRing 00000000003b4050 g 0f SECT 08 0000 [.const_data] __ZTV15AMDCIsDMAEngine 00000000003aee20 g 0f SECT 08 0000 [.const_data] __ZTV15AMDSIDMAChannel 00000000003ae3e0 g 0f SECT 08 0000 [.const_data] __ZTV15AMDSIPM4Channel 00000000003b1640 g 0f SECT 08 0000 [.const_data] __ZTV15AMDSISPUChannel 00000000003b06e0 g 0f SECT 08 0000 [.const_data] __ZTV15AMDSIUVDChannel 00000000003af940 g 0f SECT 08 0000 [.const_data] __ZTV15AMDSIVCEChannel 00000000003b03c0 g 0f SECT 08 0000 [.const_data] __ZTV15AMDSIVCELLQRing 00000000003bbcd0 g 0f SECT 08 0000 [.const_data] __ZTV15AMDVIPM4Channel 00000000003bcb20 g 0f SECT 08 0000 [.const_data] __ZTV15AMDVISAMUEngine 00000000003bb030 g 0f SECT 08 0000 [.const_data] __ZTV15AMDVIsDMAEngine 00000000003bdfc0 g 0f SECT 08 0000 [.const_data] __ZTV15ShaderVidMemMgr 00000000003be090 g 0f SECT 08 0000 [.const_data] __ZTV15SiBltAuxSurfMgr 00000000003be4f0 g 0f SECT 08 0000 [.const_data] __ZTV15SiSurfAttribute 00000000003b83a0 g 0f SECT 08 0000 [.const_data] __ZTV16AMDCIComputeRing 00000000003b5170 g 0f SECT 08 0000 [.const_data] __ZTV16AMDCIHWUtilities 00000000003b5fc0 g 0f SECT 08 0000 [.const_data] __ZTV16AMDCISAMURBIRing 00000000003b6d70 g 0f SECT 08 0000 [.const_data] __ZTV16AMDCIUVDHWEngine 00000000003b7200 g 0f SECT 08 0000 [.const_data] __ZTV16AMDCIVCEHWEngine 00000000003b1d10 g 0f SECT 08 0000 [.const_data] __ZTV16AMDSIComputeRing 00000000003aae70 g 0f SECT 08 0000 [.const_data] __ZTV16AMDSIHWUtilities 00000000003b0ab0 g 0f SECT 08 0000 [.const_data] __ZTV16AMDSIUVDHWEngine 00000000003af540 g 0f SECT 08 0000 [.const_data] __ZTV16AMDSIVCEHWEngine 00000000003b91e0 g 0f SECT 08 0000 [.const_data] __ZTV16AMDTongaHardware 00000000003bb9b0 g 0f SECT 08 0000 [.const_data] __ZTV16AMDVIComputeRing 00000000003ba9c0 g 0f SECT 08 0000 [.const_data] __ZTV16AMDVIHWUtilities 00000000003bcef0 g 0f SECT 08 0000 [.const_data] __ZTV16AMDVISAMURBIRing 00000000003bac30 g 0f SECT 08 0000 [.const_data] __ZTV16AMDVIsDMAChannel 00000000003acc50 g 0f SECT 08 0000 [.const_data] __ZTV16AMDVerdeHardware 00000000003be310 g 0f SECT 08 0000 [.const_data] __ZTV16SiBltPixelShader 00000000003b3d30 g 0f SECT 08 0000 [.const_data] __ZTV17AMDCICommandsRing 00000000003b3280 g 0f SECT 08 0000 [.const_data] __ZTV17AMDHawaiiHardware 00000000003ae7d0 g 0f SECT 08 0000 [.const_data] __ZTV17AMDSICommandsRing 0000000000398200 g 0f SECT 08 0000 [.const_data] __ZTV17AMDSIVideoContext 00000000003abdf0 g 0f SECT 08 0000 [.const_data] __ZTV17AMDTahitiHardware 00000000003bb690 g 0f SECT 08 0000 [.const_data] __ZTV17AMDVICommandsRing 00000000003ae080 g 0f SECT 08 0000 [.const_data] __ZTV17AMDVerdePM4Engine 00000000003be3e0 g 0f SECT 08 0000 [.const_data] __ZTV17SiShaderVidMemMgr 00000000003b2b50 g 0f SECT 08 0000 [.const_data] __ZTV18AMDBonaireHardware 00000000003b6690 g 0f SECT 08 0000 [.const_data] __ZTV18AMDCISAMUGPCOMRing 00000000003b79b0 g 0f SECT 08 0000 [.const_data] __ZTV18AMDCIVCELLQChannel 00000000003afcf0 g 0f SECT 08 0000 [.const_data] __ZTV18AMDSIVCELLQChannel 00000000003ad9c0 g 0f SECT 08 0000 [.const_data] __ZTV18AMDTahitiPM4Engine 00000000003bd5c0 g 0f SECT 08 0000 [.const_data] __ZTV18AMDVISAMUGPCOMRing 00000000003b62f0 g 0f SECT 08 0000 [.const_data] __ZTV19AMDCISAMURBIChannel 00000000003ac520 g 0f SECT 08 0000 [.const_data] __ZTV19AMDPitcairnHardware 00000000003968a0 g 0f SECT 08 0000 [.const_data] __ZTV19AMDSIDisplayMachine 00000000003ad380 g 0f SECT 08 0000 [.const_data] __ZTV19AMDSIHWAlignManager 000000000039f950 g 0f SECT 08 0000 [.const_data] __ZTV19AMDVIDisplayMachine 00000000003bd220 g 0f SECT 08 0000 [.const_data] __ZTV19AMDVISAMURBIChannel 00000000003add20 g 0f SECT 08 0000 [.const_data] __ZTV20AMDPitcairnPM4Engine 00000000003b69d0 g 0f SECT 08 0000 [.const_data] __ZTV21AMDCISAMUGPCOMChannel 00000000003bd900 g 0f SECT 08 0000 [.const_data] __ZTV21AMDVISAMUGPCOMChannel 00000000003b86c0 g 0f SECT 08 0000 [.const_data] __ZTV22AMDCIPM4ComputeChannel 00000000003965e0 g 0f SECT 08 0000 [.const_data] __ZTV22AMDSIAtomicBlitManager 00000000003b2030 g 0f SECT 08 0000 [.const_data] __ZTV22AMDSIPM4ComputeChannel 00000000003bc730 g 0f SECT 08 0000 [.const_data] __ZTV22AMDVIPM4ComputeChannel 00000000003b46b0 g 0f SECT 08 0000 [.const_data] __ZTV23AMDCIPM4CommandsUtility 00000000003a7c30 g 0f SECT 08 0000 [.const_data] __ZTV23AMDRadeonX4000_AMDHWVMM 00000000003c3a90 g 0f SECT 08 0000 [.const_data] __ZTV23AMDRadeonX4000_AMDSIDRM 00000000003c3cf0 g 0f SECT 08 0000 [.const_data] __ZTV23AMDRadeonX4000_AMDSISPU 00000000003c3f80 g 0f SECT 08 0000 [.const_data] __ZTV23AMDRadeonX4000_AMDSIVCE 00000000003c52b0 g 0f SECT 08 0000 [.const_data] __ZTV23AMDRadeonX4000_AMDUVDVI 00000000003c5530 g 0f SECT 08 0000 [.const_data] __ZTV23AMDRadeonX4000_AMDVIDRM 00000000003c5790 g 0f SECT 08 0000 [.const_data] __ZTV23AMDRadeonX4000_AMDVISPU 00000000003c5a20 g 0f SECT 08 0000 [.const_data] __ZTV23AMDRadeonX4000_AMDVIVCE 00000000003bc0e0 g 0f SECT 08 0000 [.const_data] __ZTV23AMDVIPM4CommandsUtility 000000000039ada0 g 0f SECT 08 0000 [.const_data] __ZTV24AMDCIGraphicsAccelerator 0000000000390b00 g 0f SECT 08 0000 [.const_data] __ZTV24AMDRadeonX4000_AMDBltMgr 00000000003c4800 g 0f SECT 08 0000 [.const_data] __ZTV24AMDRadeonX4000_AMDCIKDRM 00000000003c4a60 g 0f SECT 08 0000 [.const_data] __ZTV24AMDRadeonX4000_AMDCIKSPU 00000000003c4cf0 g 0f SECT 08 0000 [.const_data] __ZTV24AMDRadeonX4000_AMDCIKVCE 00000000003a3070 g 0f SECT 08 0000 [.const_data] __ZTV24AMDRadeonX4000_AMDHWGart 00000000003a6c50 g 0f SECT 08 0000 [.const_data] __ZTV24AMDRadeonX4000_AMDHWRing 00000000003c13e0 g 0f SECT 08 0000 [.const_data] __ZTV24AMDRadeonX4000_AMDSMLDRM 00000000003c1620 g 0f SECT 08 0000 [.const_data] __ZTV24AMDRadeonX4000_AMDSMLSPU 00000000003c1160 g 0f SECT 08 0000 [.const_data] __ZTV24AMDRadeonX4000_AMDSMLUVD 00000000003c1b40 g 0f SECT 08 0000 [.const_data] __ZTV24AMDRadeonX4000_AMDSMLVCE 00000000003c4580 g 0f SECT 08 0000 [.const_data] __ZTV24AMDRadeonX4000_AMDUVDCIK 00000000003a6080 g 0f SECT 08 0000 [.const_data] __ZTV24AMDRadeonX4000_IAMDHWVMM 00000000003936e0 g 0f SECT 08 0000 [.const_data] __ZTV24AMDSIGraphicsAccelerator 000000000039e1d0 g 0f SECT 08 0000 [.const_data] __ZTV24AMDVIGraphicsAccelerator 00000000003a7f60 g 0f SECT 08 0000 [.const_data] __ZTV25AMDRadeonX4000_AMDNULLVMM 00000000003a4880 g 0f SECT 08 0000 [.const_data] __ZTV25AMDRadeonX4000_IAMDHWGart 00000000003a4b30 g 0f SECT 08 0000 [.const_data] __ZTV25AMDRadeonX4000_IAMDHWRing 00000000003c0450 g 0f SECT 08 0000 [.const_data] __ZTV25AMDRadeonX4000_IAMDSMLDRM 00000000003c0680 g 0f SECT 08 0000 [.const_data] __ZTV25AMDRadeonX4000_IAMDSMLSPU 00000000003c0220 g 0f SECT 08 0000 [.const_data] __ZTV25AMDRadeonX4000_IAMDSMLUVD 00000000003c08b0 g 0f SECT 08 0000 [.const_data] __ZTV25AMDRadeonX4000_IAMDSMLVCE 0000000000390d40 g 0f SECT 08 0000 [.const_data] __ZTV25AMDRadeonX4000_VendorGart 00000000003a2a40 g 0f SECT 08 0000 [.const_data] __ZTV26AMDRadeonX4000_AMDHWEngine 00000000003a6650 g 0f SECT 08 0000 [.const_data] __ZTV26AMDRadeonX4000_AMDHWMemory 00000000003a8280 g 0f SECT 08 0000 [.const_data] __ZTV26AMDRadeonX4000_AMDHardware 000000000038fb70 g 0f SECT 08 0000 [.const_data] __ZTV26AMDRadeonX4000_AMDSPUEvent 0000000000392c10 g 0f SECT 08 0000 [.const_data] __ZTV27AMDRadeonX4000_AMDAccelTask 00000000003a0b30 g 0f SECT 08 0000 [.const_data] __ZTV27AMDRadeonX4000_AMDHWChannel 00000000003a0ed0 g 0f SECT 08 0000 [.const_data] __ZTV27AMDRadeonX4000_AMDHWDisplay 00000000003a07b0 g 0f SECT 08 0000 [.const_data] __ZTV27AMDRadeonX4000_AMDHWHandler 0000000000390f70 g 0f SECT 08 0000 [.const_data] __ZTV27AMDRadeonX4000_AMDHashTable 00000000003c18b0 g 0f SECT 08 0000 [.const_data] __ZTV27AMDRadeonX4000_AMDSMLSPUMsg 00000000003a5a30 g 0f SECT 08 0000 [.const_data] __ZTV27AMDRadeonX4000_IAMDHWEngine 00000000003a4540 g 0f SECT 08 0000 [.const_data] __ZTV27AMDRadeonX4000_IAMDHWMemory 000000000039ed90 g 0f SECT 08 0000 [.const_data] __ZTV27AMDTongaGraphicsAccelerator 0000000000395a20 g 0f SECT 08 0000 [.const_data] __ZTV27AMDVerdeGraphicsAccelerator 000000000039c520 g 0f SECT 08 0000 [.const_data] __ZTV28AMDHawaiiGraphicsAccelerator 00000000003911a0 g 0f SECT 08 0000 [.const_data] __ZTV28AMDRadeonX4000_AMDLinkedList 000000000038fdb0 g 0f SECT 08 0000 [.const_data] __ZTV28AMDRadeonX4000_AMDSPUContext 0000000000390380 g 0f SECT 08 0000 [.const_data] __ZTV28AMDRadeonX4000_AMDTPTManager 00000000003c3810 g 0f SECT 08 0000 [.const_data] __ZTV28AMDRadeonX4000_AMDUVDTrinity 00000000003a5d20 g 0f SECT 08 0000 [.const_data] __ZTV28AMDRadeonX4000_IAMDHWChannel 00000000003a3870 g 0f SECT 08 0000 [.const_data] __ZTV28AMDRadeonX4000_IAMDHWDisplay 00000000003a3c80 g 0f SECT 08 0000 [.const_data] __ZTV28AMDRadeonX4000_IAMDHWHandler 0000000000394e60 g 0f SECT 08 0000 [.const_data] __ZTV28AMDTahitiGraphicsAccelerator 000000000039b960 g 0f SECT 08 0000 [.const_data] __ZTV29AMDBonaireGraphicsAccelerator 0000000000389d30 g 0f SECT 08 0000 [.const_data] __ZTV29AMDRadeonX4000_AMDAccelDevice 000000000038ba40 g 0f SECT 08 0000 [.const_data] __ZTV29AMDRadeonX4000_AMDAccelShared 00000000003a20d0 g 0f SECT 08 0000 [.const_data] __ZTV29AMDRadeonX4000_AMDDMAHWEngine 00000000003c2a80 g 0f SECT 08 0000 [.const_data] __ZTV29AMDRadeonX4000_AMDFPGenKeyMsg 00000000003a69d0 g 0f SECT 08 0000 [.const_data] __ZTV29AMDRadeonX4000_AMDHWRegisters 00000000003a6f70 g 0f SECT 08 0000 [.const_data] __ZTV29AMDRadeonX4000_AMDHWSemaphore 00000000003a1340 g 0f SECT 08 0000 [.const_data] __ZTV29AMDRadeonX4000_AMDHWUtilities 00000000003a7980 g 0f SECT 08 0000 [.const_data] __ZTV29AMDRadeonX4000_AMDHWVMContext 00000000003a8ba0 g 0f SECT 08 0000 [.const_data] __ZTV29AMDRadeonX4000_AMDPM4HWEngine 00000000003a92e0 g 0f SECT 08 0000 [.const_data] __ZTV29AMDRadeonX4000_AMDSPUHWEngine 00000000003aa1f0 g 0f SECT 08 0000 [.const_data] __ZTV29AMDRadeonX4000_AMDUVDHWEngine 00000000003a9a40 g 0f SECT 08 0000 [.const_data] __ZTV29AMDRadeonX4000_AMDVCEHWEngine 00000000003942a0 g 0f SECT 08 0000 [.const_data] __ZTV30AMDPitcairnGraphicsAccelerator 0000000000389a00 g 0f SECT 08 0000 [.const_data] __ZTV30AMDRadeonX4000_AMDAccelChannel 000000000038c9c0 g 0f SECT 08 0000 [.const_data] __ZTV30AMDRadeonX4000_AMDAccelSurface 00000000003a1cd0 g 0f SECT 08 0000 [.const_data] __ZTV30AMDRadeonX4000_AMDDMAHWChannel 00000000003c3230 g 0f SECT 08 0000 [.const_data] __ZTV30AMDRadeonX4000_AMDFPEncryptMsg 00000000003c27f0 g 0f SECT 08 0000 [.const_data] __ZTV30AMDRadeonX4000_AMDFPGetCertMsg 00000000003c2d10 g 0f SECT 08 0000 [.const_data] __ZTV30AMDRadeonX4000_AMDFPTestKeyMsg 00000000003a2d70 g 0f SECT 08 0000 [.const_data] __ZTV30AMDRadeonX4000_AMDNullHWEngine 00000000003a8f00 g 0f SECT 08 0000 [.const_data] __ZTV30AMDRadeonX4000_AMDPM4HWChannel 00000000003c0e10 g 0f SECT 08 0000 [.const_data] __ZTV30AMDRadeonX4000_AMDSMLInterface 00000000003a96a0 g 0f SECT 08 0000 [.const_data] __ZTV30AMDRadeonX4000_AMDSPUHWChannel 00000000003a1900 g 0f SECT 08 0000 [.const_data] __ZTV30AMDRadeonX4000_AMDUVDHWChannel 00000000003a9e40 g 0f SECT 08 0000 [.const_data] __ZTV30AMDRadeonX4000_AMDVCEHWChannel 00000000003a3350 g 0f SECT 08 0000 [.const_data] __ZTV30AMDRadeonX4000_IAMDHWInterface 00000000003a42c0 g 0f SECT 08 0000 [.const_data] __ZTV30AMDRadeonX4000_IAMDHWRegisters 00000000003a4e00 g 0f SECT 08 0000 [.const_data] __ZTV30AMDRadeonX4000_IAMDHWSemaphore 00000000003a5530 g 0f SECT 08 0000 [.const_data] __ZTV30AMDRadeonX4000_IAMDHWUtilities 00000000003a63a0 g 0f SECT 08 0000 [.const_data] __ZTV30AMDRadeonX4000_IAMDHWVMContext 000000000038b600 g 0f SECT 08 0000 [.const_data] __ZTV31AMDRadeonX4000_AMDAccelResource 00000000003a26e0 g 0f SECT 08 0000 [.const_data] __ZTV31AMDRadeonX4000_AMDNullHWChannel 000000000038f8f0 g 0f SECT 08 0000 [.const_data] __ZTV31AMDRadeonX4000_AMDSPUAppContext 00000000003c0ae0 g 0f SECT 08 0000 [.const_data] __ZTV31AMDRadeonX4000_IAMDSMLInterface 000000000038d4c0 g 0f SECT 08 0000 [.const_data] __ZTV32AMDRadeonX4000_AMDAccel2DContext 0000000000392020 g 0f SECT 08 0000 [.const_data] __ZTV32AMDRadeonX4000_AMDAccelCLContext 0000000000393440 g 0f SECT 08 0000 [.const_data] __ZTV32AMDRadeonX4000_AMDAccelMemoryMap 0000000000392ea0 g 0f SECT 08 0000 [.const_data] __ZTV32AMDRadeonX4000_AMDAccelSysMemory 0000000000393160 g 0f SECT 08 0000 [.const_data] __ZTV32AMDRadeonX4000_AMDAccelVidMemory 00000000003c2560 g 0f SECT 08 0000 [.const_data] __ZTV32AMDRadeonX4000_AMDHDCPGetCertMsg 00000000003a2400 g 0f SECT 08 0000 [.const_data] __ZTV32AMDRadeonX4000_AMDHWAlignManager 00000000003c34c0 g 0f SECT 08 0000 [.const_data] __ZTV32AMDRadeonX4000_AMDSMLSIInterface 00000000003c4f60 g 0f SECT 08 0000 [.const_data] __ZTV32AMDRadeonX4000_AMDSMLVIInterface 000000000038c770 g 0f SECT 08 0000 [.const_data] __ZTV33AMDRadeonX4000_AMDAccelStatistics 000000000038f6b0 g 0f SECT 08 0000 [.const_data] __ZTV33AMDRadeonX4000_AMDAccelUVDContext 0000000000390140 g 0f SECT 08 0000 [.const_data] __ZTV33AMDRadeonX4000_AMDAccelVCEContext 00000000003a74c0 g 0f SECT 08 0000 [.const_data] __ZTV33AMDRadeonX4000_AMDHWSemaphorePool 00000000003a7210 g 0f SECT 08 0000 [.const_data] __ZTV33AMDRadeonX4000_AMDNullHWSemaphore 00000000003c4230 g 0f SECT 08 0000 [.const_data] __ZTV33AMDRadeonX4000_AMDSMLCIKInterface 00000000003a3ff0 g 0f SECT 08 0000 [.const_data] __ZTV33AMDRadeonX4000_IAMDHWAlignManager 00000000003c22d0 g 0f SECT 08 0000 [.const_data] __ZTV34AMDRadeonX4000_AMDHDCPGetStatusMsg 00000000003a5090 g 0f SECT 08 0000 [.const_data] __ZTV34AMDRadeonX4000_IAMDHWSemaphorePool 00000000003918d0 g 0f SECT 08 0000 [.const_data] __ZTV34AMDRadeonX4000_IAMDStatisticsGroup 000000000038b230 g 0f SECT 08 0000 [.const_data] __ZTV35AMDRadeonX4000_AMDAccelEventMachine 000000000038e660 g 0f SECT 08 0000 [.const_data] __ZTV35AMDRadeonX4000_AMDAccelVideoContext 0000000000390840 g 0f SECT 08 0000 [.const_data] __ZTV35AMDRadeonX4000_AMDAtomicBlitManager 00000000003a7730 g 0f SECT 08 0000 [.const_data] __ZTV35AMDRadeonX4000_AMDHWSemaphoreMemMgr 00000000003c1db0 g 0f SECT 08 0000 [.const_data] __ZTV36AMDRadeonX4000_AMDHDCPOpenSessionMsg 00000000003a8900 g 0f SECT 08 0000 [.const_data] __ZTV36AMDRadeonX4000_AMDPM4CommandsUtility 00000000003905b0 g 0f SECT 08 0000 [.const_data] __ZTV36AMDRadeonX4000_IAMDAtomicBlitManager 00000000003a52e0 g 0f SECT 08 0000 [.const_data] __ZTV36AMDRadeonX4000_IAMDHWSemaphoreMemMgr 00000000003913d0 g 0f SECT 08 0000 [.const_data] __ZTV36AMDRadeonX4000_IAMDStatisticsManager 000000000038a7f0 g 0f SECT 08 0000 [.const_data] __ZTV37AMDRadeonX4000_AMDAccelDisplayMachine 00000000003c2fa0 g 0f SECT 08 0000 [.const_data] __ZTV37AMDRadeonX4000_AMDFPReleaseSessionMsg 0000000000388dd0 g 0f SECT 08 0000 [.const_data] __ZTV37AMDRadeonX4000_AMDGraphicsAccelerator 00000000003c2040 g 0f SECT 08 0000 [.const_data] __ZTV37AMDRadeonX4000_AMDHDCPCloseSessionMsg 0000000000391db0 g 0f SECT 08 0000 [.const_data] __ZTV37AMDRadeonX4000_AMDHWChannelStatsGroup 00000000003a5790 g 0f SECT 08 0000 [.const_data] __ZTV37AMDRadeonX4000_IAMDPM4CommandsUtility 0000000000391b40 g 0f SECT 08 0000 [.const_data] __ZTV38AMDRadeonX4000_AMDAccelStatisticsGroup 000000000038e2d0 g 0f SECT 08 0000 [.const_data] __ZTV38AMDRadeonX4000_AMDInterruptEventSource 000000000038bc80 g 0f SECT 08 0000 [.const_data] __ZTV39AMDRadeonX4000_AMDAccelSharedUserClient 000000000038e090 g 0f SECT 08 0000 [.const_data] __ZTV40AMDRadeonX4000_AMDAccelCommandBufferPool 0000000000391650 g 0f SECT 08 0000 [.const_data] __ZTV40AMDRadeonX4000_AMDAccelStatisticsManager 00000000003a15b0 g 0f SECT 08 0000 [.const_data] __ZTV41AMDRadeonX4000_AMDUVDInterruptEventSource 00000000003bde20 g 0f SECT 08 0000 [.const_data] __ZTV6BltMgr 00000000003be580 g 0f SECT 08 0000 [.const_data] __ZTV7AddrLib 00000000003ab390 g 0f SECT 08 0000 [.const_data] __ZTV8AMDSIVMM 00000000003ba220 g 0f SECT 08 0000 [.const_data] __ZTV8AMDVIVMM 00000000003be220 g 0f SECT 08 0000 [.const_data] __ZTV8SiBltMgr 00000000003bdf40 g 0f SECT 08 0000 [.const_data] __ZTV9BltResFmt 00000000003bdf70 g 0f SECT 08 0000 [.const_data] __ZTV9BltShader 00000000003bead0 g 0f SECT 08 0000 [.const_data] __ZTV9CIAddrLib 00000000003be8f0 g 0f SECT 08 0000 [.const_data] __ZTV9SIAddrLib 00000000003b9af0 g 0f SECT 08 0000 [.const_data] __ZTVN11AMDVIHWGart9MetaClassE 00000000003b4cf0 g 0f SECT 08 0000 [.const_data] __ZTVN12AMDCIDisplay9MetaClassE 00000000003b7f80 g 0f SECT 08 0000 [.const_data] __ZTVN12AMDCIVCERing9MetaClassE 00000000003af440 g 0f SECT 08 0000 [.const_data] __ZTVN12AMDSIDMARing9MetaClassE 00000000003aad70 g 0f SECT 08 0000 [.const_data] __ZTVN12AMDSIDisplay9MetaClassE 00000000003b1c10 g 0f SECT 08 0000 [.const_data] __ZTVN12AMDSISPURing9MetaClassE 0000000000398100 g 0f SECT 08 0000 [.const_data] __ZTVN12AMDSISurface9MetaClassE 00000000003b1160 g 0f SECT 08 0000 [.const_data] __ZTVN12AMDSIUVDRing9MetaClassE 00000000003b02c0 g 0f SECT 08 0000 [.const_data] __ZTVN12AMDSIVCERing9MetaClassE 00000000003ba8c0 g 0f SECT 08 0000 [.const_data] __ZTVN12AMDVIDisplay9MetaClassE 00000000003b5070 g 0f SECT 08 0000 [.const_data] __ZTVN13AMDCIHWMemory9MetaClassE 00000000003b2a50 g 0f SECT 08 0000 [.const_data] __ZTVN13AMDCIHardware9MetaClassE 000000000039d420 g 0f SECT 08 0000 [.const_data] __ZTVN13AMDCIResource9MetaClassE 00000000003b45b0 g 0f SECT 08 0000 [.const_data] __ZTVN13AMDCIsDMARing9MetaClassE 00000000003aa900 g 0f SECT 08 0000 [.const_data] __ZTVN13AMDSIHWMemory9MetaClassE 00000000003abcf0 g 0f SECT 08 0000 [.const_data] __ZTVN13AMDSIHardware9MetaClassE 0000000000397600 g 0f SECT 08 0000 [.const_data] __ZTVN13AMDSIResource9MetaClassE 00000000003b9e70 g 0f SECT 08 0000 [.const_data] __ZTVN13AMDVIHWMemory9MetaClassE 00000000003b90e0 g 0f SECT 08 0000 [.const_data] __ZTVN13AMDVIHardware9MetaClassE 00000000003a06b0 g 0f SECT 08 0000 [.const_data] __ZTVN13AMDVIResource9MetaClassE 00000000003bb590 g 0f SECT 08 0000 [.const_data] __ZTVN13AMDVIsDMARing9MetaClassE 000000000039e0a0 g 0f SECT 08 0000 [.const_data] __ZTVN14AMDCICLContext9MetaClassE 00000000003b3c30 g 0f SECT 08 0000 [.const_data] __ZTVN14AMDCIPM4Engine9MetaClassE 000000000039ac70 g 0f SECT 08 0000 [.const_data] __ZTVN14AMDSICLContext9MetaClassE 00000000003aed20 g 0f SECT 08 0000 [.const_data] __ZTVN14AMDSIDMAEngine9MetaClassE 0000000000399f70 g 0f SECT 08 0000 [.const_data] __ZTVN14AMDSIGLContext9MetaClassE 00000000003ad8c0 g 0f SECT 08 0000 [.const_data] __ZTVN14AMDSIPM4Engine9MetaClassE 00000000003b1540 g 0f SECT 08 0000 [.const_data] __ZTVN14AMDSISPUEngine9MetaClassE 00000000003ab290 g 0f SECT 08 0000 [.const_data] __ZTVN14AMDSIVMContext9MetaClassE 00000000003bc630 g 0f SECT 08 0000 [.const_data] __ZTVN14AMDVIPM4Engine9MetaClassE 00000000003ba120 g 0f SECT 08 0000 [.const_data] __ZTVN14AMDVIVMContext9MetaClassE 00000000003b5af0 g 0f SECT 08 0000 [.const_data] __ZTVN15AMDCIDMAChannel9MetaClassE 00000000003b56f0 g 0f SECT 08 0000 [.const_data] __ZTVN15AMDCIPM4Channel9MetaClassE 00000000003b5ec0 g 0f SECT 08 0000 [.const_data] __ZTVN15AMDCISAMUEngine9MetaClassE 00000000003b78b0 g 0f SECT 08 0000 [.const_data] __ZTVN15AMDCIVCEChannel9MetaClassE 00000000003b82a0 g 0f SECT 08 0000 [.const_data] __ZTVN15AMDCIVCELLQRing9MetaClassE 00000000003b4290 g 0f SECT 08 0000 [.const_data] __ZTVN15AMDCIsDMAEngine9MetaClassE 00000000003af120 g 0f SECT 08 0000 [.const_data] __ZTVN15AMDSIDMAChannel9MetaClassE 00000000003ae6d0 g 0f SECT 08 0000 [.const_data] __ZTVN15AMDSIPM4Channel9MetaClassE 00000000003b18e0 g 0f SECT 08 0000 [.const_data] __ZTVN15AMDSISPUChannel9MetaClassE 00000000003b09b0 g 0f SECT 08 0000 [.const_data] __ZTVN15AMDSIUVDChannel9MetaClassE 00000000003afbf0 g 0f SECT 08 0000 [.const_data] __ZTVN15AMDSIVCEChannel9MetaClassE 00000000003b05e0 g 0f SECT 08 0000 [.const_data] __ZTVN15AMDSIVCELLQRing9MetaClassE 00000000003bbfe0 g 0f SECT 08 0000 [.const_data] __ZTVN15AMDVIPM4Channel9MetaClassE 00000000003bcdf0 g 0f SECT 08 0000 [.const_data] __ZTVN15AMDVISAMUEngine9MetaClassE 00000000003bb270 g 0f SECT 08 0000 [.const_data] __ZTVN15AMDVIsDMAEngine9MetaClassE 00000000003b85c0 g 0f SECT 08 0000 [.const_data] __ZTVN16AMDCIComputeRing9MetaClassE 00000000003b52e0 g 0f SECT 08 0000 [.const_data] __ZTVN16AMDCIHWUtilities9MetaClassE 00000000003b61f0 g 0f SECT 08 0000 [.const_data] __ZTVN16AMDCISAMURBIRing9MetaClassE 00000000003b7100 g 0f SECT 08 0000 [.const_data] __ZTVN16AMDCIUVDHWEngine9MetaClassE 00000000003b7500 g 0f SECT 08 0000 [.const_data] __ZTVN16AMDCIVCEHWEngine9MetaClassE 00000000003b1f30 g 0f SECT 08 0000 [.const_data] __ZTVN16AMDSIComputeRing9MetaClassE 00000000003aafe0 g 0f SECT 08 0000 [.const_data] __ZTVN16AMDSIHWUtilities9MetaClassE 00000000003b0e40 g 0f SECT 08 0000 [.const_data] __ZTVN16AMDSIUVDHWEngine9MetaClassE 00000000003af840 g 0f SECT 08 0000 [.const_data] __ZTVN16AMDSIVCEHWEngine9MetaClassE 00000000003b9810 g 0f SECT 08 0000 [.const_data] __ZTVN16AMDTongaHardware9MetaClassE 00000000003bbbd0 g 0f SECT 08 0000 [.const_data] __ZTVN16AMDVIComputeRing9MetaClassE 00000000003bab30 g 0f SECT 08 0000 [.const_data] __ZTVN16AMDVIHWUtilities9MetaClassE 00000000003bd120 g 0f SECT 08 0000 [.const_data] __ZTVN16AMDVISAMURBIRing9MetaClassE 00000000003baf30 g 0f SECT 08 0000 [.const_data] __ZTVN16AMDVIsDMAChannel9MetaClassE 00000000003ad280 g 0f SECT 08 0000 [.const_data] __ZTVN16AMDVerdeHardware9MetaClassE 00000000003b3f50 g 0f SECT 08 0000 [.const_data] __ZTVN17AMDCICommandsRing9MetaClassE 00000000003b38b0 g 0f SECT 08 0000 [.const_data] __ZTVN17AMDHawaiiHardware9MetaClassE 00000000003ae9f0 g 0f SECT 08 0000 [.const_data] __ZTVN17AMDSICommandsRing9MetaClassE 0000000000398d00 g 0f SECT 08 0000 [.const_data] __ZTVN17AMDSIVideoContext9MetaClassE 00000000003ac420 g 0f SECT 08 0000 [.const_data] __ZTVN17AMDTahitiHardware9MetaClassE 00000000003bb8b0 g 0f SECT 08 0000 [.const_data] __ZTVN17AMDVICommandsRing9MetaClassE 00000000003ae2e0 g 0f SECT 08 0000 [.const_data] __ZTVN17AMDVerdePM4Engine9MetaClassE 00000000003b3180 g 0f SECT 08 0000 [.const_data] __ZTVN18AMDBonaireHardware9MetaClassE 00000000003b68d0 g 0f SECT 08 0000 [.const_data] __ZTVN18AMDCISAMUGPCOMRing9MetaClassE 00000000003b7c60 g 0f SECT 08 0000 [.const_data] __ZTVN18AMDCIVCELLQChannel9MetaClassE 00000000003affa0 g 0f SECT 08 0000 [.const_data] __ZTVN18AMDSIVCELLQChannel9MetaClassE 00000000003adc20 g 0f SECT 08 0000 [.const_data] __ZTVN18AMDTahitiPM4Engine9MetaClassE 00000000003bd800 g 0f SECT 08 0000 [.const_data] __ZTVN18AMDVISAMUGPCOMRing9MetaClassE 00000000003b6590 g 0f SECT 08 0000 [.const_data] __ZTVN19AMDCISAMURBIChannel9MetaClassE 00000000003acb50 g 0f SECT 08 0000 [.const_data] __ZTVN19AMDPitcairnHardware9MetaClassE 00000000003971c0 g 0f SECT 08 0000 [.const_data] __ZTVN19AMDSIDisplayMachine9MetaClassE 00000000003ad560 g 0f SECT 08 0000 [.const_data] __ZTVN19AMDSIHWAlignManager9MetaClassE 00000000003a0270 g 0f SECT 08 0000 [.const_data] __ZTVN19AMDVIDisplayMachine9MetaClassE 00000000003bd4c0 g 0f SECT 08 0000 [.const_data] __ZTVN19AMDVISAMURBIChannel9MetaClassE 00000000003adf80 g 0f SECT 08 0000 [.const_data] __ZTVN20AMDPitcairnPM4Engine9MetaClassE 00000000003b6c70 g 0f SECT 08 0000 [.const_data] __ZTVN21AMDCISAMUGPCOMChannel9MetaClassE 00000000003bdba0 g 0f SECT 08 0000 [.const_data] __ZTVN21AMDVISAMUGPCOMChannel9MetaClassE 00000000003b89b0 g 0f SECT 08 0000 [.const_data] __ZTVN22AMDCIPM4ComputeChannel9MetaClassE 00000000003967a0 g 0f SECT 08 0000 [.const_data] __ZTVN22AMDSIAtomicBlitManager9MetaClassE 00000000003b2320 g 0f SECT 08 0000 [.const_data] __ZTVN22AMDSIPM4ComputeChannel9MetaClassE 00000000003bca20 g 0f SECT 08 0000 [.const_data] __ZTVN22AMDVIPM4ComputeChannel9MetaClassE 00000000003b4870 g 0f SECT 08 0000 [.const_data] __ZTVN23AMDCIPM4CommandsUtility9MetaClassE 00000000003a7e60 g 0f SECT 08 0000 [.const_data] __ZTVN23AMDRadeonX4000_AMDHWVMM9MetaClassE 00000000003c3bf0 g 0f SECT 08 0000 [.const_data] __ZTVN23AMDRadeonX4000_AMDSIDRM9MetaClassE 00000000003c3e80 g 0f SECT 08 0000 [.const_data] __ZTVN23AMDRadeonX4000_AMDSISPU9MetaClassE 00000000003c40f0 g 0f SECT 08 0000 [.const_data] __ZTVN23AMDRadeonX4000_AMDSIVCE9MetaClassE 00000000003c5430 g 0f SECT 08 0000 [.const_data] __ZTVN23AMDRadeonX4000_AMDUVDVI9MetaClassE 00000000003c5690 g 0f SECT 08 0000 [.const_data] __ZTVN23AMDRadeonX4000_AMDVIDRM9MetaClassE 00000000003c5920 g 0f SECT 08 0000 [.const_data] __ZTVN23AMDRadeonX4000_AMDVISPU9MetaClassE 00000000003c5b90 g 0f SECT 08 0000 [.const_data] __ZTVN23AMDRadeonX4000_AMDVIVCE9MetaClassE 00000000003bc2a0 g 0f SECT 08 0000 [.const_data] __ZTVN23AMDVIPM4CommandsUtility9MetaClassE 000000000039b860 g 0f SECT 08 0000 [.const_data] __ZTVN24AMDCIGraphicsAccelerator9MetaClassE 0000000000390c40 g 0f SECT 08 0000 [.const_data] __ZTVN24AMDRadeonX4000_AMDBltMgr9MetaClassE 00000000003c4960 g 0f SECT 08 0000 [.const_data] __ZTVN24AMDRadeonX4000_AMDCIKDRM9MetaClassE 00000000003c4bf0 g 0f SECT 08 0000 [.const_data] __ZTVN24AMDRadeonX4000_AMDCIKSPU9MetaClassE 00000000003c4e60 g 0f SECT 08 0000 [.const_data] __ZTVN24AMDRadeonX4000_AMDCIKVCE9MetaClassE 00000000003a3250 g 0f SECT 08 0000 [.const_data] __ZTVN24AMDRadeonX4000_AMDHWGart9MetaClassE 00000000003a6e70 g 0f SECT 08 0000 [.const_data] __ZTVN24AMDRadeonX4000_AMDHWRing9MetaClassE 00000000003c1520 g 0f SECT 08 0000 [.const_data] __ZTVN24AMDRadeonX4000_AMDSMLDRM9MetaClassE 00000000003c17b0 g 0f SECT 08 0000 [.const_data] __ZTVN24AMDRadeonX4000_AMDSMLSPU9MetaClassE 00000000003c12e0 g 0f SECT 08 0000 [.const_data] __ZTVN24AMDRadeonX4000_AMDSMLUVD9MetaClassE 00000000003c1cb0 g 0f SECT 08 0000 [.const_data] __ZTVN24AMDRadeonX4000_AMDSMLVCE9MetaClassE 00000000003c4700 g 0f SECT 08 0000 [.const_data] __ZTVN24AMDRadeonX4000_AMDUVDCIK9MetaClassE 00000000003a62a0 g 0f SECT 08 0000 [.const_data] __ZTVN24AMDRadeonX4000_IAMDHWVMM9MetaClassE 00000000003941a0 g 0f SECT 08 0000 [.const_data] __ZTVN24AMDSIGraphicsAccelerator9MetaClassE 000000000039ec90 g 0f SECT 08 0000 [.const_data] __ZTVN24AMDVIGraphicsAccelerator9MetaClassE 00000000003a8180 g 0f SECT 08 0000 [.const_data] __ZTVN25AMDRadeonX4000_AMDNULLVMM9MetaClassE 00000000003a4a30 g 0f SECT 08 0000 [.const_data] __ZTVN25AMDRadeonX4000_IAMDHWGart9MetaClassE 00000000003a4d00 g 0f SECT 08 0000 [.const_data] __ZTVN25AMDRadeonX4000_IAMDHWRing9MetaClassE 00000000003c0580 g 0f SECT 08 0000 [.const_data] __ZTVN25AMDRadeonX4000_IAMDSMLDRM9MetaClassE 00000000003c07b0 g 0f SECT 08 0000 [.const_data] __ZTVN25AMDRadeonX4000_IAMDSMLSPU9MetaClassE 00000000003c0350 g 0f SECT 08 0000 [.const_data] __ZTVN25AMDRadeonX4000_IAMDSMLUVD9MetaClassE 00000000003c09e0 g 0f SECT 08 0000 [.const_data] __ZTVN25AMDRadeonX4000_IAMDSMLVCE9MetaClassE 0000000000390e70 g 0f SECT 08 0000 [.const_data] __ZTVN25AMDRadeonX4000_VendorGart9MetaClassE 00000000003a2c70 g 0f SECT 08 0000 [.const_data] __ZTVN26AMDRadeonX4000_AMDHWEngine9MetaClassE 00000000003a68d0 g 0f SECT 08 0000 [.const_data] __ZTVN26AMDRadeonX4000_AMDHWMemory9MetaClassE 00000000003a8800 g 0f SECT 08 0000 [.const_data] __ZTVN26AMDRadeonX4000_AMDHardware9MetaClassE 000000000038fcb0 g 0f SECT 08 0000 [.const_data] __ZTVN26AMDRadeonX4000_AMDSPUEvent9MetaClassE 0000000000392da0 g 0f SECT 08 0000 [.const_data] __ZTVN27AMDRadeonX4000_AMDAccelTask9MetaClassE 00000000003a0dd0 g 0f SECT 08 0000 [.const_data] __ZTVN27AMDRadeonX4000_AMDHWChannel9MetaClassE 00000000003a1240 g 0f SECT 08 0000 [.const_data] __ZTVN27AMDRadeonX4000_AMDHWDisplay9MetaClassE 00000000003a0a30 g 0f SECT 08 0000 [.const_data] __ZTVN27AMDRadeonX4000_AMDHWHandler9MetaClassE 00000000003910a0 g 0f SECT 08 0000 [.const_data] __ZTVN27AMDRadeonX4000_AMDHashTable9MetaClassE 00000000003c1a40 g 0f SECT 08 0000 [.const_data] __ZTVN27AMDRadeonX4000_AMDSMLSPUMsg9MetaClassE 00000000003a5c20 g 0f SECT 08 0000 [.const_data] __ZTVN27AMDRadeonX4000_IAMDHWEngine9MetaClassE 00000000003a4780 g 0f SECT 08 0000 [.const_data] __ZTVN27AMDRadeonX4000_IAMDHWMemory9MetaClassE 000000000039f850 g 0f SECT 08 0000 [.const_data] __ZTVN27AMDTongaGraphicsAccelerator9MetaClassE 00000000003964e0 g 0f SECT 08 0000 [.const_data] __ZTVN27AMDVerdeGraphicsAccelerator9MetaClassE 000000000039cfe0 g 0f SECT 08 0000 [.const_data] __ZTVN28AMDHawaiiGraphicsAccelerator9MetaClassE 00000000003912d0 g 0f SECT 08 0000 [.const_data] __ZTVN28AMDRadeonX4000_AMDLinkedList9MetaClassE 0000000000390040 g 0f SECT 08 0000 [.const_data] __ZTVN28AMDRadeonX4000_AMDSPUContext9MetaClassE 00000000003904b0 g 0f SECT 08 0000 [.const_data] __ZTVN28AMDRadeonX4000_AMDTPTManager9MetaClassE 00000000003c3990 g 0f SECT 08 0000 [.const_data] __ZTVN28AMDRadeonX4000_AMDUVDTrinity9MetaClassE 00000000003a5f80 g 0f SECT 08 0000 [.const_data] __ZTVN28AMDRadeonX4000_IAMDHWChannel9MetaClassE 00000000003a3b80 g 0f SECT 08 0000 [.const_data] __ZTVN28AMDRadeonX4000_IAMDHWDisplay9MetaClassE 00000000003a3ef0 g 0f SECT 08 0000 [.const_data] __ZTVN28AMDRadeonX4000_IAMDHWHandler9MetaClassE 0000000000395920 g 0f SECT 08 0000 [.const_data] __ZTVN28AMDTahitiGraphicsAccelerator9MetaClassE 000000000039c420 g 0f SECT 08 0000 [.const_data] __ZTVN29AMDBonaireGraphicsAccelerator9MetaClassE 000000000038a6c0 g 0f SECT 08 0000 [.const_data] __ZTVN29AMDRadeonX4000_AMDAccelDevice9MetaClassE 000000000038bb80 g 0f SECT 08 0000 [.const_data] __ZTVN29AMDRadeonX4000_AMDAccelShared9MetaClassE 00000000003a2300 g 0f SECT 08 0000 [.const_data] __ZTVN29AMDRadeonX4000_AMDDMAHWEngine9MetaClassE 00000000003c2c10 g 0f SECT 08 0000 [.const_data] __ZTVN29AMDRadeonX4000_AMDFPGenKeyMsg9MetaClassE 00000000003a6b50 g 0f SECT 08 0000 [.const_data] __ZTVN29AMDRadeonX4000_AMDHWRegisters9MetaClassE 00000000003a7110 g 0f SECT 08 0000 [.const_data] __ZTVN29AMDRadeonX4000_AMDHWSemaphore9MetaClassE 00000000003a14b0 g 0f SECT 08 0000 [.const_data] __ZTVN29AMDRadeonX4000_AMDHWUtilities9MetaClassE 00000000003a7b30 g 0f SECT 08 0000 [.const_data] __ZTVN29AMDRadeonX4000_AMDHWVMContext9MetaClassE 00000000003a8e00 g 0f SECT 08 0000 [.const_data] __ZTVN29AMDRadeonX4000_AMDPM4HWEngine9MetaClassE 00000000003a95a0 g 0f SECT 08 0000 [.const_data] __ZTVN29AMDRadeonX4000_AMDSPUHWEngine9MetaClassE 00000000003aa580 g 0f SECT 08 0000 [.const_data] __ZTVN29AMDRadeonX4000_AMDUVDHWEngine9MetaClassE 00000000003a9d40 g 0f SECT 08 0000 [.const_data] __ZTVN29AMDRadeonX4000_AMDVCEHWEngine9MetaClassE 0000000000394d60 g 0f SECT 08 0000 [.const_data] __ZTVN30AMDPitcairnGraphicsAccelerator9MetaClassE 0000000000389c10 g 0f SECT 08 0000 [.const_data] __ZTVN30AMDRadeonX4000_AMDAccelChannel9MetaClassE 000000000038d3c0 g 0f SECT 08 0000 [.const_data] __ZTVN30AMDRadeonX4000_AMDAccelSurface9MetaClassE 00000000003a1fd0 g 0f SECT 08 0000 [.const_data] __ZTVN30AMDRadeonX4000_AMDDMAHWChannel9MetaClassE 00000000003c33c0 g 0f SECT 08 0000 [.const_data] __ZTVN30AMDRadeonX4000_AMDFPEncryptMsg9MetaClassE 00000000003c2980 g 0f SECT 08 0000 [.const_data] __ZTVN30AMDRadeonX4000_AMDFPGetCertMsg9MetaClassE 00000000003c2ea0 g 0f SECT 08 0000 [.const_data] __ZTVN30AMDRadeonX4000_AMDFPTestKeyMsg9MetaClassE 00000000003a2f70 g 0f SECT 08 0000 [.const_data] __ZTVN30AMDRadeonX4000_AMDNullHWEngine9MetaClassE 00000000003a91e0 g 0f SECT 08 0000 [.const_data] __ZTVN30AMDRadeonX4000_AMDPM4HWChannel9MetaClassE 00000000003c1060 g 0f SECT 08 0000 [.const_data] __ZTVN30AMDRadeonX4000_AMDSMLInterface9MetaClassE 00000000003a9940 g 0f SECT 08 0000 [.const_data] __ZTVN30AMDRadeonX4000_AMDSPUHWChannel9MetaClassE 00000000003a1bd0 g 0f SECT 08 0000 [.const_data] __ZTVN30AMDRadeonX4000_AMDUVDHWChannel9MetaClassE 00000000003aa0f0 g 0f SECT 08 0000 [.const_data] __ZTVN30AMDRadeonX4000_AMDVCEHWChannel9MetaClassE 00000000003a3770 g 0f SECT 08 0000 [.const_data] __ZTVN30AMDRadeonX4000_IAMDHWInterface9MetaClassE 00000000003a4440 g 0f SECT 08 0000 [.const_data] __ZTVN30AMDRadeonX4000_IAMDHWRegisters9MetaClassE 00000000003a4f90 g 0f SECT 08 0000 [.const_data] __ZTVN30AMDRadeonX4000_IAMDHWSemaphore9MetaClassE 00000000003a5690 g 0f SECT 08 0000 [.const_data] __ZTVN30AMDRadeonX4000_IAMDHWUtilities9MetaClassE 00000000003a6550 g 0f SECT 08 0000 [.const_data] __ZTVN30AMDRadeonX4000_IAMDHWVMContext9MetaClassE 000000000038b940 g 0f SECT 08 0000 [.const_data] __ZTVN31AMDRadeonX4000_AMDAccelResource9MetaClassE 00000000003a2940 g 0f SECT 08 0000 [.const_data] __ZTVN31AMDRadeonX4000_AMDNullHWChannel9MetaClassE 000000000038fa70 g 0f SECT 08 0000 [.const_data] __ZTVN31AMDRadeonX4000_AMDSPUAppContext9MetaClassE 00000000003c0d10 g 0f SECT 08 0000 [.const_data] __ZTVN31AMDRadeonX4000_IAMDSMLInterface9MetaClassE 000000000038df90 g 0f SECT 08 0000 [.const_data] __ZTVN32AMDRadeonX4000_AMDAccel2DContext9MetaClassE 0000000000392b10 g 0f SECT 08 0000 [.const_data] __ZTVN32AMDRadeonX4000_AMDAccelCLContext9MetaClassE 00000000003935e0 g 0f SECT 08 0000 [.const_data] __ZTVN32AMDRadeonX4000_AMDAccelMemoryMap9MetaClassE 0000000000393060 g 0f SECT 08 0000 [.const_data] __ZTVN32AMDRadeonX4000_AMDAccelSysMemory9MetaClassE 0000000000393340 g 0f SECT 08 0000 [.const_data] __ZTVN32AMDRadeonX4000_AMDAccelVidMemory9MetaClassE 00000000003c26f0 g 0f SECT 08 0000 [.const_data] __ZTVN32AMDRadeonX4000_AMDHDCPGetCertMsg9MetaClassE 00000000003a25e0 g 0f SECT 08 0000 [.const_data] __ZTVN32AMDRadeonX4000_AMDHWAlignManager9MetaClassE 00000000003c3710 g 0f SECT 08 0000 [.const_data] __ZTVN32AMDRadeonX4000_AMDSMLSIInterface9MetaClassE 00000000003c51b0 g 0f SECT 08 0000 [.const_data] __ZTVN32AMDRadeonX4000_AMDSMLVIInterface9MetaClassE 000000000038c8c0 g 0f SECT 08 0000 [.const_data] __ZTVN33AMDRadeonX4000_AMDAccelStatistics9MetaClassE 000000000038f7f0 g 0f SECT 08 0000 [.const_data] __ZTVN33AMDRadeonX4000_AMDAccelUVDContext9MetaClassE 0000000000390280 g 0f SECT 08 0000 [.const_data] __ZTVN33AMDRadeonX4000_AMDAccelVCEContext9MetaClassE 00000000003a7630 g 0f SECT 08 0000 [.const_data] __ZTVN33AMDRadeonX4000_AMDHWSemaphorePool9MetaClassE 00000000003a73c0 g 0f SECT 08 0000 [.const_data] __ZTVN33AMDRadeonX4000_AMDNullHWSemaphore9MetaClassE 00000000003c4480 g 0f SECT 08 0000 [.const_data] __ZTVN33AMDRadeonX4000_AMDSMLCIKInterface9MetaClassE 00000000003a41c0 g 0f SECT 08 0000 [.const_data] __ZTVN33AMDRadeonX4000_IAMDHWAlignManager9MetaClassE 00000000003c2460 g 0f SECT 08 0000 [.const_data] __ZTVN34AMDRadeonX4000_AMDHDCPGetStatusMsg9MetaClassE 00000000003a51e0 g 0f SECT 08 0000 [.const_data] __ZTVN34AMDRadeonX4000_IAMDHWSemaphorePool9MetaClassE 0000000000391a40 g 0f SECT 08 0000 [.const_data] __ZTVN34AMDRadeonX4000_IAMDStatisticsGroup9MetaClassE 000000000038b500 g 0f SECT 08 0000 [.const_data] __ZTVN35AMDRadeonX4000_AMDAccelEventMachine9MetaClassE 000000000038f160 g 0f SECT 08 0000 [.const_data] __ZTVN35AMDRadeonX4000_AMDAccelVideoContext9MetaClassE 0000000000390a00 g 0f SECT 08 0000 [.const_data] __ZTVN35AMDRadeonX4000_AMDAtomicBlitManager9MetaClassE 00000000003a7880 g 0f SECT 08 0000 [.const_data] __ZTVN35AMDRadeonX4000_AMDHWSemaphoreMemMgr9MetaClassE 00000000003c1f40 g 0f SECT 08 0000 [.const_data] __ZTVN36AMDRadeonX4000_AMDHDCPOpenSessionMsg9MetaClassE 00000000003a8aa0 g 0f SECT 08 0000 [.const_data] __ZTVN36AMDRadeonX4000_AMDPM4CommandsUtility9MetaClassE 0000000000390740 g 0f SECT 08 0000 [.const_data] __ZTVN36AMDRadeonX4000_IAMDAtomicBlitManager9MetaClassE 00000000003a5430 g 0f SECT 08 0000 [.const_data] __ZTVN36AMDRadeonX4000_IAMDHWSemaphoreMemMgr9MetaClassE 0000000000391550 g 0f SECT 08 0000 [.const_data] __ZTVN36AMDRadeonX4000_IAMDStatisticsManager9MetaClassE 000000000038b110 g 0f SECT 08 0000 [.const_data] __ZTVN37AMDRadeonX4000_AMDAccelDisplayMachine9MetaClassE 00000000003c3130 g 0f SECT 08 0000 [.const_data] __ZTVN37AMDRadeonX4000_AMDFPReleaseSessionMsg9MetaClassE 0000000000389890 g 0f SECT 08 0000 [.const_data] __ZTVN37AMDRadeonX4000_AMDGraphicsAccelerator9MetaClassE 00000000003c21d0 g 0f SECT 08 0000 [.const_data] __ZTVN37AMDRadeonX4000_AMDHDCPCloseSessionMsg9MetaClassE 0000000000391f20 g 0f SECT 08 0000 [.const_data] __ZTVN37AMDRadeonX4000_AMDHWChannelStatsGroup9MetaClassE 00000000003a5930 g 0f SECT 08 0000 [.const_data] __ZTVN37AMDRadeonX4000_IAMDPM4CommandsUtility9MetaClassE 0000000000391cb0 g 0f SECT 08 0000 [.const_data] __ZTVN38AMDRadeonX4000_AMDAccelStatisticsGroup9MetaClassE 000000000038e520 g 0f SECT 08 0000 [.const_data] __ZTVN38AMDRadeonX4000_AMDInterruptEventSource9MetaClassE 000000000038c610 g 0f SECT 08 0000 [.const_data] __ZTVN39AMDRadeonX4000_AMDAccelSharedUserClient9MetaClassE 000000000038e1d0 g 0f SECT 08 0000 [.const_data] __ZTVN40AMDRadeonX4000_AMDAccelCommandBufferPool9MetaClassE 00000000003917d0 g 0f SECT 08 0000 [.const_data] __ZTVN40AMDRadeonX4000_AMDAccelStatisticsManager9MetaClassE 00000000003a1800 g 0f SECT 08 0000 [.const_data] __ZTVN41AMDRadeonX4000_AMDUVDInterruptEventSource9MetaClassE 00000000003ab5c0 g 0f SECT 08 0000 [.const_data] __ZTVN8AMDSIVMM9MetaClassE 00000000003ba450 g 0f SECT 08 0000 [.const_data] __ZTVN8AMDVIVMM9MetaClassE 00000000000949bf g 0f SECT 01 0000 [.text] ___divdi3 000000000009383c g 0f SECT 01 0000 [.text] ___isfinited 0000000000093822 g 0f SECT 01 0000 [.text] ___isfinitef 00000000000937ee g 0f SECT 01 0000 [.text] ___isnand 00000000000937c5 g 0f SECT 01 0000 [.text] ___isnanf 00000000000949fb g 0f SECT 01 0000 [.text] ___moddi3 0000000000094439 g 0f SECT 01 0000 [.text] ___qdivrem 00000000004d25e0 g 0f SECT 09 0000 [.data] _aDowngradeSuperSUMO_GoldenRegisterSettings 0000000000122e89 g 0f SECT 01 0000 [.text] _aes_byte_sub 000000000012375f g 0f SECT 01 0000 [.text] _aes_cbc_decrypt 0000000000123691 g 0f SECT 01 0000 [.text] _aes_cbc_encrypt 000000000012382e g 0f SECT 01 0000 [.text] _aes_cntr_encrypt 00000000001234e4 g 0f SECT 01 0000 [.text] _aes_dec 0000000000123995 g 0f SECT 01 0000 [.text] _aes_dm_hash 000000000012362d g 0f SECT 01 0000 [.text] _aes_ecb_decrypt 00000000001235c9 g 0f SECT 01 0000 [.text] _aes_ecb_encrypt 0000000000122f95 g 0f SECT 01 0000 [.text] _aes_enc 00000000001232a3 g 0f SECT 01 0000 [.text] _aes_invbyte_sub 000000000012323f g 0f SECT 01 0000 [.text] _aes_invshift_row 0000000000122f0f g 0f SECT 01 0000 [.text] _aes_mix_column 000000000052cd60 g 0f SECT 09 0000 [.data] _aes_rsbox 000000000052cc60 g 0f SECT 09 0000 [.data] _aes_sbox 0000000000122eab g 0f SECT 01 0000 [.text] _aes_shift_row 00000000003c60a0 g 0f SECT 09 0000 [.data] _ati_format_info_table 00000000003c69b0 g 0f SECT 09 0000 [.data] _ati_si_format_info_table 00000000003c5f80 g 0f SECT 09 0000 [.data] _cailEngines 00000000000f375c g 0f SECT 01 0000 [.text] _cailReadRomImage 000000000009385d g 0f SECT 01 0000 [.text] _ceil 00000000004d3430 g 0f SECT 09 0000 [.data] _checkFireGLValues 0000000000120f85 g 0f SECT 01 0000 [.text] _cmdCall_Table 0000000000120ee3 g 0f SECT 01 0000 [.text] _cmdDelay_Microsec 0000000000120eb6 g 0f SECT 01 0000 [.text] _cmdDelay_Millisec 0000000000121001 g 0f SECT 01 0000 [.text] _cmdNOP_ 0000000000120df3 g 0f SECT 01 0000 [.text] _cmdSetDataBlock 0000000000120e54 g 0f SECT 01 0000 [.text] _cmdSet_ATI_Port 0000000000120e71 g 0f SECT 01 0000 [.text] _cmdSet_Reg_Block 0000000000120e8f g 0f SECT 01 0000 [.text] _cmdSet_X_Port 0000000000123e4e g 0f SECT 01 0000 [.text] _copy128 0000000000093905 g 0f SECT 01 0000 [.text] _copysign 000000000012159c g 0f SECT 01 0000 [.text] _driveClock 000000000012166b g 0f SECT 01 0000 [.text] _driveData 0000000000121a36 g 0f SECT 01 0000 [.text] _enableClock 0000000000121add g 0f SECT 01 0000 [.text] _enableData 00000000004d1830 g 0f SECT 09 0000 [.data] _evergreen_cs_data 00000000000f098c g 0f SECT 01 0000 [.text] _execute_easf_bios_function 00000000000938e8 g 0f SECT 01 0000 [.text] _fabs 00000000000936b1 g 0f SECT 01 0000 [.text] _floor 0000000000093a65 g 0f SECT 01 0000 [.text] _frexp 00000000003c5f70 g 0f SECT 09 0000 [.data] _gAMDHWMemoryAllocationTypeNames 00000000003c5f30 g 0f SECT 09 0000 [.data] _gAMDHwEngineTypeNames 00000000003c5c80 g 0f SECT 09 0000 [.data] _gLogLevelModuleNames 00000000003c5e10 g 0f SECT 09 0000 [.data] _gLogLevelNames 000000000052ce60 g 0f SECT 0a 0000 [__DATA.__common] _g_acceleratorCount 000000000052d384 g 0f SECT 0a 0000 [__DATA.__common] _g_klogRefCount 000000000052d250 g 0f SECT 0a 0000 [__DATA.__common] _g_lvntProcNameBuff 000000000052d2c0 g 0f SECT 0a 0000 [__DATA.__common] _g_pLogLevelMasks 0000000000123129 g 0f SECT 01 0000 [.text] _generate_aes_round_keys 0000000000121376 g 0f SECT 01 0000 [.text] _getClock 0000000000121489 g 0f SECT 01 0000 [.text] _getData 0000000000122d7a g 0f SECT 01 0000 [.text] _inc_cntr 00000000000f1c9e g 0f SECT 01 0000 [.text] _init_rlc_clear_state_buffer_for_llano_trinity 000000000012232c g 0f SECT 01 0000 [.text] _isLineUp 00000000003c5fd0 g 0f SECT 09 0000 [.data] _kmod_info 0000000000093a40 g 0f SECT 01 0000 [.text] _ldexp 0000000000122def g 0f SECT 01 0000 [.text] _next_aes_enc_key 00000000004413a0 g 0f SECT 09 0000 [.data] _ni_cs_data 0000000000093bcc g 0f SECT 01 0000 [.text] _pow 0000000000093bb5 g 0f SECT 01 0000 [.text] _powf 0000000000122351 g 0f SECT 01 0000 [.text] _processI2CDebugRequest 000000000012196e g 0f SECT 01 0000 [.text] _readBit 0000000000121d02 g 0f SECT 01 0000 [.text] _readBuffer 0000000000121be8 g 0f SECT 01 0000 [.text] _readByte 00000000003d7058 g 0f SECT 09 0000 [.data] _sBonaireGbMacroTileModeTbl 00000000003d7048 g 0f SECT 09 0000 [.data] _sBonaireGbTileModeTbl 00000000003e3240 g 0f SECT 09 0000 [.data] _sCapeVerdeGbTileModeTbl 00000000003e6f88 g 0f SECT 09 0000 [.data] _sCarrizoGbMacroTileModeTbl 00000000003e6f78 g 0f SECT 09 0000 [.data] _sCarrizoGbTileModeTbl 00000000004438e0 g 0f SECT 09 0000 [.data] _sGodavariCsRegWrite 0000000000443c70 g 0f SECT 09 0000 [.data] _sGodavariCsRegWriteList 0000000000443f50 g 0f SECT 09 0000 [.data] _sGodavariMetaDataList 00000000004499a0 g 0f SECT 09 0000 [.data] _sHawaiiGbMacroTileModeTbl 0000000000449990 g 0f SECT 09 0000 [.data] _sHawaiiGbTileModeTbl 0000000000459ad8 g 0f SECT 09 0000 [.data] _sIcelandGbMacroTileModeTbl 0000000000459ac8 g 0f SECT 09 0000 [.data] _sIcelandGbTileModeTbl 00000000004b7230 g 0f SECT 09 0000 [.data] _sKalindiCsRegWrite 00000000004b75c0 g 0f SECT 09 0000 [.data] _sKalindiCsRegWriteList 00000000004b78a0 g 0f SECT 09 0000 [.data] _sKalindiMetaDataList 00000000004bad40 g 0f SECT 09 0000 [.data] _sOlandGbTileModeTbl 00000000004c1610 g 0f SECT 09 0000 [.data] _sSpectreGbMacroTileModeTbl 00000000004c1600 g 0f SECT 09 0000 [.data] _sSpectreGbTileModeTbl 00000000004d3d40 g 0f SECT 09 0000 [.data] _sTahitiGbTileModeTbl 00000000004d7848 g 0f SECT 09 0000 [.data] _sTongaGbMacroTileModeTbl 00000000004d7838 g 0f SECT 09 0000 [.data] _sTongaGbTileModeTbl 0000000000093931 g 0f SECT 01 0000 [.text] _scalbn 00000000001088e8 g 0f SECT 01 0000 [.text] _setup_vce_clock_gating_mode 0000000000094a5c g 0f SECT 01 0000 [.text] _si_window_mode_to_ati_format 0000000000123d49 g 0f SECT 01 0000 [.text] _simple_dm_hash 0000000000093af1 g 0f SECT 01 0000 [.text] _sqrt 00000000001a91d0 g 0f SECT 03 0000 [.const] _ulBIOSScratchRegistersPreserveMaskAtom 0000000000459a70 g 0f SECT 09 0000 [.data] _ulIcelandUcodeLoadOrderTbl 00000000000f35ae g 0f SECT 01 0000 [.text] _ulReadMmRegisterUlong 00000000000f3703 g 0f SECT 01 0000 [.text] _ulReadMmRegisterUlongDirectIO 00000000000f3653 g 0f SECT 01 0000 [.text] _ulReadMmRegisterUlongViaAddr 00000000000daa12 g 0f SECT 01 0000 [.text] _ulRead_RialtoMmReg 00000000000daad8 g 0f SECT 01 0000 [.text] _ulRead_RialtoPCIEEndPointCFGReg 00000000000daa71 g 0f SECT 01 0000 [.text] _ulRead_RialtoPCIERootComplexCFGReg 00000000004b7200 g 0f SECT 09 0000 [.data] _ulUcodeLoadOrderTbl 0000000000121370 g 0f SECT 01 0000 [.text] _usleep 00000000000e7a97 g 0f SECT 01 0000 [.text] _vGetRegulation 00000000000f3677 g 0f SECT 01 0000 [.text] _vWriteMmRegisterUlong 00000000000f371e g 0f SECT 01 0000 [.text] _vWriteMmRegisterUlongDirectIO 00000000000f3667 g 0f SECT 01 0000 [.text] _vWriteMmRegisterUlongViaAddr 00000000000daa3f g 0f SECT 01 0000 [.text] _vWrite_RialtoMmReg 00000000000dab09 g 0f SECT 01 0000 [.text] _vWrite_RialtoPCIEEndPointCFGReg 00000000000daaa2 g 0f SECT 01 0000 [.text] _vWrite_RialtoPCIERootComplexCFGReg 0000000000108794 g 0f SECT 01 0000 [.text] _validate_vce_firmware 000000000012173a g 0f SECT 01 0000 [.text] _waitClock 0000000000121784 g 0f SECT 01 0000 [.text] _waitData 0000000000094a39 g 0f SECT 01 0000 [.text] _window_mode_to_ati_format 0000000000121866 g 0f SECT 01 0000 [.text] _writeBit 0000000000121c62 g 0f SECT 01 0000 [.text] _writeBuffer 0000000000121b85 g 0f SECT 01 0000 [.text] _writeByte 0000000000123e65 g 0f SECT 01 0000 [.text] _xor128 0000000000123e7f g 0f SECT 01 0000 [.text] _xor32 0000000000123e39 g 0f SECT 01 0000 [.text] _zero128 0000000000000000 g 01 UND 00 fe00 _IODelay 0000000000000000 g 01 UND 00 fe00 _IOFlushProcessorCache 0000000000000000 g 01 UND 00 fe00 _IOFree 0000000000000000 g 01 UND 00 fe00 _IOFreeAligned 0000000000000000 g 01 UND 00 fe00 _IOFreePageable 0000000000000000 g 01 UND 00 fe00 _IOLockAlloc 0000000000000000 g 01 UND 00 fe00 _IOLockFree 0000000000000000 g 01 UND 00 fe00 _IOLockLock 0000000000000000 g 01 UND 00 fe00 _IOLockUnlock 0000000000000000 g 01 UND 00 fe00 _IOLog 0000000000000000 g 01 UND 00 fe00 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__ZN9IOService19_RESERVEDIOService8Ev 0000000000000000 g 01 UND 00 fe00 __ZN9IOService19_RESERVEDIOService9Ev 0000000000000000 g 01 UND 00 fe00 __ZN9IOService19registerPowerDriverEPS_P14IOPMPowerStatem 0000000000000000 g 01 UND 00 fe00 __ZN9IOService19unregisterInterruptEi 0000000000000000 g 01 UND 00 fe00 __ZN9IOService20_RESERVEDIOService10Ev 0000000000000000 g 01 UND 00 fe00 __ZN9IOService20_RESERVEDIOService11Ev 0000000000000000 g 01 UND 00 fe00 __ZN9IOService20_RESERVEDIOService12Ev 0000000000000000 g 01 UND 00 fe00 __ZN9IOService20_RESERVEDIOService13Ev 0000000000000000 g 01 UND 00 fe00 __ZN9IOService20_RESERVEDIOService14Ev 0000000000000000 g 01 UND 00 fe00 __ZN9IOService20_RESERVEDIOService15Ev 0000000000000000 g 01 UND 00 fe00 __ZN9IOService20_RESERVEDIOService16Ev 0000000000000000 g 01 UND 00 fe00 __ZN9IOService20_RESERVEDIOService17Ev 0000000000000000 g 01 UND 00 fe00 __ZN9IOService20_RESERVEDIOService18Ev 0000000000000000 g 01 UND 00 fe00 __ZN9IOService20_RESERVEDIOService19Ev 0000000000000000 g 01 UND 00 fe00 __ZN9IOService20_RESERVEDIOService20Ev 0000000000000000 g 01 UND 00 fe00 __ZN9IOService20_RESERVEDIOService21Ev 0000000000000000 g 01 UND 00 fe00 __ZN9IOService20_RESERVEDIOService22Ev 0000000000000000 g 01 UND 00 fe00 __ZN9IOService20_RESERVEDIOService23Ev 0000000000000000 g 01 UND 00 fe00 __ZN9IOService20_RESERVEDIOService24Ev 0000000000000000 g 01 UND 00 fe00 __ZN9IOService20_RESERVEDIOService25Ev 0000000000000000 g 01 UND 00 fe00 __ZN9IOService20_RESERVEDIOService26Ev 0000000000000000 g 01 UND 00 fe00 __ZN9IOService20_RESERVEDIOService27Ev 0000000000000000 g 01 UND 00 fe00 __ZN9IOService20_RESERVEDIOService28Ev 0000000000000000 g 01 UND 00 fe00 __ZN9IOService20_RESERVEDIOService29Ev 0000000000000000 g 01 UND 00 fe00 __ZN9IOService20_RESERVEDIOService30Ev 0000000000000000 g 01 UND 00 fe00 __ZN9IOService20_RESERVEDIOService31Ev 0000000000000000 g 01 UND 00 fe00 __ZN9IOService20_RESERVEDIOService32Ev 0000000000000000 g 01 UND 00 fe00 __ZN9IOService20_RESERVEDIOService33Ev 0000000000000000 g 01 UND 00 fe00 __ZN9IOService20_RESERVEDIOService34Ev 0000000000000000 g 01 UND 00 fe00 __ZN9IOService20_RESERVEDIOService35Ev 0000000000000000 g 01 UND 00 fe00 __ZN9IOService20_RESERVEDIOService36Ev 0000000000000000 g 01 UND 00 fe00 __ZN9IOService20_RESERVEDIOService37Ev 0000000000000000 g 01 UND 00 fe00 __ZN9IOService20_RESERVEDIOService38Ev 0000000000000000 g 01 UND 00 fe00 __ZN9IOService20_RESERVEDIOService39Ev 0000000000000000 g 01 UND 00 fe00 __ZN9IOService20_RESERVEDIOService40Ev 0000000000000000 g 01 UND 00 fe00 __ZN9IOService20_RESERVEDIOService41Ev 0000000000000000 g 01 UND 00 fe00 __ZN9IOService20_RESERVEDIOService42Ev 0000000000000000 g 01 UND 00 fe00 __ZN9IOService20_RESERVEDIOService43Ev 0000000000000000 g 01 UND 00 fe00 __ZN9IOService20_RESERVEDIOService44Ev 0000000000000000 g 01 UND 00 fe00 __ZN9IOService20_RESERVEDIOService45Ev 0000000000000000 g 01 UND 00 fe00 __ZN9IOService20_RESERVEDIOService46Ev 0000000000000000 g 01 UND 00 fe00 __ZN9IOService20_RESERVEDIOService47Ev 0000000000000000 g 01 UND 00 fe00 __ZN9IOService20callPlatformFunctionEPK8OSSymbolbPvS3_S3_S3_ 0000000000000000 g 01 UND 00 fe00 __ZN9IOService20callPlatformFunctionEPKcbPvS2_S2_S2_ 0000000000000000 g 01 UND 00 fe00 __ZN9IOService20getDeviceMemoryCountEv 0000000000000000 g 01 UND 00 fe00 __ZN9IOService20unlockForArbitrationEv 0000000000000000 g 01 UND 00 fe00 __ZN9IOService21powerStateDidChangeToEmmPS_ 0000000000000000 g 01 UND 00 fe00 __ZN9IOService22copyClientWithCategoryEPK8OSSymbol 0000000000000000 g 01 UND 00 fe00 __ZN9IOService22powerStateWillChangeToEmmPS_ 0000000000000000 g 01 UND 00 fe00 __ZN9IOService23acknowledgeNotificationEPvj 0000000000000000 g 01 UND 00 fe00 __ZN9IOService23requestPowerDomainStateEmP17IOPowerConnectionm 0000000000000000 g 01 UND 00 fe00 __ZN9IOService24getDeviceMemoryWithIndexEj 0000000000000000 g 01 UND 00 fe00 __ZN9IOService24mapDeviceMemoryWithIndexEjj 0000000000000000 g 01 UND 00 fe00 __ZN9IOService24powerStateForDomainStateEm 0000000000000000 g 01 UND 00 fe00 __ZN9IOService27maxCapabilityForDomainStateEm 0000000000000000 g 01 UND 00 fe00 __ZN9IOService31initialPowerStateForDomainStateEm 0000000000000000 g 01 UND 00 fe00 __ZN9IOService4freeEv 0000000000000000 g 01 UND 00 fe00 __ZN9IOService4initEP12OSDictionary 0000000000000000 g 01 UND 00 fe00 __ZN9IOService4initEP15IORegistryEntryPK15IORegistryPlane 0000000000000000 g 01 UND 00 fe00 __ZN9IOService4openEPS_jPv 0000000000000000 g 01 UND 00 fe00 __ZN9IOService4stopEPS_ 0000000000000000 g 01 UND 00 fe00 __ZN9IOService5closeEPS_j 0000000000000000 g 01 UND 00 fe00 __ZN9IOService5probeEPS_Pi 0000000000000000 g 01 UND 00 fe00 __ZN9IOService5startEPS_ 0000000000000000 g 01 UND 00 fe00 __ZN9IOService6PMinitEv 0000000000000000 g 01 UND 00 fe00 __ZN9IOService6PMstopEv 0000000000000000 g 01 UND 00 fe00 __ZN9IOService6attachEPS_ 0000000000000000 g 01 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fe00 __ZNK11OSMetaClass7releaseEi 0000000000000000 g 01 UND 00 fe00 __ZNK11OSMetaClass7releaseEv 0000000000000000 g 01 UND 00 fe00 __ZNK11OSMetaClass9serializeEP11OSSerialize 0000000000000000 g 01 UND 00 fe00 __ZNK13IOAccelMemory15getPrepareCountEv 0000000000000000 g 01 UND 00 fe00 __ZNK13IOAccelMemory7releaseEv 0000000000000000 g 01 UND 00 fe00 __ZNK13IOEventSource11getWorkLoopEv 0000000000000000 g 01 UND 00 fe00 __ZNK13IOEventSource7getNextEv 0000000000000000 g 01 UND 00 fe00 __ZNK13IOEventSource8onThreadEv 0000000000000000 g 01 UND 00 fe00 __ZNK13IOEventSource9getActionEv 0000000000000000 g 01 UND 00 fe00 __ZNK13IOEventSource9isEnabledEv 0000000000000000 g 01 UND 00 fe00 __ZNK15IORegistryEntry11compareNameEP8OSStringPS1_ 0000000000000000 g 01 UND 00 fe00 __ZNK15IORegistryEntry11getLocationEPK15IORegistryPlane 0000000000000000 g 01 UND 00 fe00 __ZNK15IORegistryEntry11getPropertyEPK8OSString 0000000000000000 g 01 UND 00 fe00 __ZNK15IORegistryEntry11getPropertyEPK8OSStringPK15IORegistryPlanej 0000000000000000 g 01 UND 00 fe00 __ZNK15IORegistryEntry11getPropertyEPK8OSSymbol 0000000000000000 g 01 UND 00 fe00 __ZNK15IORegistryEntry11getPropertyEPK8OSSymbolPK15IORegistryPlanej 0000000000000000 g 01 UND 00 fe00 __ZNK15IORegistryEntry11getPropertyEPKc 0000000000000000 g 01 UND 00 fe00 __ZNK15IORegistryEntry11getPropertyEPKcPK15IORegistryPlanej 0000000000000000 g 01 UND 00 fe00 __ZNK15IORegistryEntry12compareNamesEP8OSObjectPP8OSString 0000000000000000 g 01 UND 00 fe00 __ZNK15IORegistryEntry12copyLocationEPK15IORegistryPlane 0000000000000000 g 01 UND 00 fe00 __ZNK15IORegistryEntry12copyPropertyEPK8OSString 0000000000000000 g 01 UND 00 fe00 __ZNK15IORegistryEntry12copyPropertyEPK8OSStringPK15IORegistryPlanej 0000000000000000 g 01 UND 00 fe00 __ZNK15IORegistryEntry12copyPropertyEPK8OSSymbol 0000000000000000 g 01 UND 00 fe00 __ZNK15IORegistryEntry12copyPropertyEPK8OSSymbolPK15IORegistryPlanej 0000000000000000 g 01 UND 00 fe00 __ZNK15IORegistryEntry12copyPropertyEPKc 0000000000000000 g 01 UND 00 fe00 __ZNK15IORegistryEntry12copyPropertyEPKcPK15IORegistryPlanej 0000000000000000 g 01 UND 00 fe00 __ZNK15IORegistryEntry13getChildEntryEPK15IORegistryPlane 0000000000000000 g 01 UND 00 fe00 __ZNK15IORegistryEntry14applyToParentsEPFvPS_PvES1_PK15IORegistryPlane 0000000000000000 g 01 UND 00 fe00 __ZNK15IORegistryEntry14copyChildEntryEPK15IORegistryPlane 0000000000000000 g 01 UND 00 fe00 __ZNK15IORegistryEntry14getParentEntryEPK15IORegistryPlane 0000000000000000 g 01 UND 00 fe00 __ZNK15IORegistryEntry15applyToChildrenEPFvPS_PvES1_PK15IORegistryPlane 0000000000000000 g 01 UND 00 fe00 __ZNK15IORegistryEntry15copyParentEntryEPK15IORegistryPlane 0000000000000000 g 01 UND 00 fe00 __ZNK15IORegistryEntry16getChildIteratorEPK15IORegistryPlane 0000000000000000 g 01 UND 00 fe00 __ZNK15IORegistryEntry16getPathComponentEPcPiPK15IORegistryPlane 0000000000000000 g 01 UND 00 fe00 __ZNK15IORegistryEntry17getParentIteratorEPK15IORegistryPlane 0000000000000000 g 01 UND 00 fe00 __ZNK15IORegistryEntry24dictionaryWithPropertiesEv 0000000000000000 g 01 UND 00 fe00 __ZNK15IORegistryEntry7getNameEPK15IORegistryPlane 0000000000000000 g 01 UND 00 fe00 __ZNK15IORegistryEntry7getPathEPcPiPK15IORegistryPlane 0000000000000000 g 01 UND 00 fe00 __ZNK15IORegistryEntry7inPlaneEPK15IORegistryPlane 0000000000000000 g 01 UND 00 fe00 __ZNK15IORegistryEntry7isChildEPS_PK15IORegistryPlaneb 0000000000000000 g 01 UND 00 fe00 __ZNK15IORegistryEntry8copyNameEPK15IORegistryPlane 0000000000000000 g 01 UND 00 fe00 __ZNK15IORegistryEntry8getDepthEPK15IORegistryPlane 0000000000000000 g 01 UND 00 fe00 __ZNK15IORegistryEntry8isParentEPS_PK15IORegistryPlaneb 0000000000000000 g 01 UND 00 fe00 __ZNK15OSMetaClassBase9isEqualToEPKS_ 0000000000000000 g 01 UND 00 fe00 __ZNK16IOAccelMemoryMap15getPrepareCountEv 0000000000000000 g 01 UND 00 fe00 __ZNK16IOAccelMemoryMap7releaseEv 0000000000000000 g 01 UND 00 fe00 __ZNK16IOAccelResource26retainEv 0000000000000000 g 01 UND 00 fe00 __ZNK16IOAccelResource27releaseEv 0000000000000000 g 01 UND 00 fe00 __ZNK22IOInterruptEventSource11getIntIndexEv 0000000000000000 g 01 UND 00 fe00 __ZNK22IOInterruptEventSource11getProviderEv 0000000000000000 g 01 UND 00 fe00 __ZNK22IOInterruptEventSource14getAutoDisableEv 0000000000000000 g 01 UND 00 fe00 __ZNK8OSObject12taggedRetainEPKv 0000000000000000 g 01 UND 00 fe00 __ZNK8OSObject13taggedReleaseEPKv 0000000000000000 g 01 UND 00 fe00 __ZNK8OSObject13taggedReleaseEPKvi 0000000000000000 g 01 UND 00 fe00 __ZNK8OSObject14getRetainCountEv 0000000000000000 g 01 UND 00 fe00 __ZNK8OSObject6retainEv 0000000000000000 g 01 UND 00 fe00 __ZNK8OSObject7releaseEi 0000000000000000 g 01 UND 00 fe00 __ZNK8OSObject7releaseEv 0000000000000000 g 01 UND 00 fe00 __ZNK8OSObject9serializeEP11OSSerialize 0000000000000000 g 01 UND 00 fe00 __ZNK9IOService11getProviderEv 0000000000000000 g 01 UND 00 fe00 __ZNK9IOService11getWorkLoopEv 0000000000000000 g 01 UND 00 fe00 __ZNK9IOService12handleIsOpenEPKS_ 0000000000000000 g 01 UND 00 fe00 __ZNK9IOService17getClientIteratorEv 0000000000000000 g 01 UND 00 fe00 __ZNK9IOService19getProviderIteratorEv 0000000000000000 g 01 UND 00 fe00 __ZNK9IOService19serializePropertiesEP11OSSerialize 0000000000000000 g 01 UND 00 fe00 __ZNK9IOService21getOpenClientIteratorEv 0000000000000000 g 01 UND 00 fe00 __ZNK9IOService23getOpenProviderIteratorEv 0000000000000000 g 01 UND 00 fe00 __ZNK9IOService6isOpenEPKS_ 0000000000000000 g 01 UND 00 fe00 __ZNK9IOService8getStateEv 0000000000000000 g 01 UND 00 fe00 __ZNK9IOService9getClientEv 0000000000000000 g 01 UND 00 fe00 __ZTV11IOAccelTask 0000000000000000 g 01 UND 00 fe00 __ZTV14IOAccelDevice2 0000000000000000 g 01 UND 00 fe00 __ZTV14IOAccelShared2 0000000000000000 g 01 UND 00 fe00 __ZTV15IOAccelSurface2 0000000000000000 g 01 UND 00 fe00 __ZTV16IOAccelMemoryMap 0000000000000000 g 01 UND 00 fe00 __ZTV16IOAccelResource2 0000000000000000 g 01 UND 00 fe00 __ZTV16IOAccelSysMemory 0000000000000000 g 01 UND 00 fe00 __ZTV16IOAccelVidMemory 0000000000000000 g 01 UND 00 fe00 __ZTV17IOAccel2DContext2 0000000000000000 g 01 UND 00 fe00 __ZTV17IOAccelCLContext2 0000000000000000 g 01 UND 00 fe00 __ZTV17IOAccelGLContext2 0000000000000000 g 01 UND 00 fe00 __ZTV18IOAccelStatistics2 0000000000000000 g 01 UND 00 fe00 __ZTV19IOAccelFIFOChannel2 0000000000000000 g 01 UND 00 fe00 __ZTV20IOAccelVideoContext2 0000000000000000 g 01 UND 00 fe00 __ZTV22IOAccelDisplayMachine2 0000000000000000 g 01 UND 00 fe00 __ZTV22IOGraphicsAccelerator2 0000000000000000 g 01 UND 00 fe00 __ZTV22IOInterruptEventSource 0000000000000000 g 01 UND 00 fe00 __ZTV23IOAccelMemoryAllocator2 0000000000000000 g 01 UND 00 fe00 __ZTV24IOAccelEventMachineList2 0000000000000000 g 01 UND 00 fe00 __ZTV24IOAccelSharedUserClient2 0000000000000000 g 01 UND 00 fe00 __ZTV25IOAccelCommandBufferPool2 0000000000000000 g 01 UND 00 fe00 __ZTV8OSObject 0000000000000000 g 01 UND 00 fe00 __ZTV9IOService 0000000000000000 g 01 UND 00 fe00 __ZdlPv 0000000000000000 g 01 UND 00 fe00 __Znwm 0000000000000000 g 01 UND 00 fe00 ___bzero 0000000000000000 g 01 UND 00 fe00 ___cxa_pure_virtual 0000000000000000 g 01 UND 00 fe00 ___stack_chk_fail 0000000000000000 g 01 UND 00 fe00 ___stack_chk_guard 0000000000000000 g 01 UND 00 fe00 _absolutetime_to_nanoseconds 0000000000000000 g 01 UND 00 fe00 _assert_wait_timeout 0000000000000000 g 01 UND 00 fe00 _bcopy 0000000000000000 g 01 UND 00 fe00 _bzero 0000000000000000 g 01 UND 00 fe00 _clock_get_uptime 0000000000000000 g 01 UND 00 fe00 _gIODTPlane 0000000000000000 g 01 UND 00 fe00 _kdebug_enable 0000000000000000 g 01 UND 00 fe00 _kernel_debug 0000000000000000 g 01 UND 00 fe00 _kernel_task 0000000000000000 g 01 UND 00 fe00 _kprintf 0000000000000000 g 01 UND 00 fe00 _memcpy 0000000000000000 g 01 UND 00 fe00 _memmove 0000000000000000 g 01 UND 00 fe00 _memset 0000000000000000 g 01 UND 00 fe00 _page_shift 0000000000000000 g 01 UND 00 fe00 _page_size 0000000000000000 g 01 UND 00 fe00 _panic 0000000000000000 g 01 UND 00 fe00 _proc_selfname 0000000000000000 g 01 UND 00 fe00 _snprintf 0000000000000000 g 01 UND 00 fe00 _sscanf 0000000000000000 g 01 UND 00 fe00 _strcmp 0000000000000000 g 01 UND 00 fe00 _strlen 0000000000000000 g 01 UND 00 fe00 _strncpy 0000000000000000 g 01 UND 00 fe00 _sysctlbyname 0000000000000000 g 01 UND 00 fe00 _thread_blockThese symbols decoded (demangled) are:/System/Library/Extensions/AMDRadeonX4000.kext/Contents/MacOS/AMDRadeonX4000: file format mach-unsigned __int128-x86-64 SYMBOL TABLE: 0000000000001402 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDGraphicsAccelerator::MetaClass::~MetaClass() 0000000000001d74 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDGraphicsAccelerator::getAccelChannel(_eAMD_HW_ENGINE_TYPE, _eAMD_HW_RING_TYPE) 0000000000004528 long 0e SECT 01 0000 [.text] IOGraphicsAccelerator2::getWorkLoop() const 0000000000004536 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDGraphicsAccelerator::MetaClass::~MetaClass() 0000000000004540 long 0e SECT 01 0000 [.text] __GLOBAL__I_a 0000000000004580 long 0e SECT 01 0000 [.text] __GLOBAL__D_a 00000000000045d2 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelChannel::MetaClass::~MetaClass() 0000000000005458 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelChannel::MetaClass::~MetaClass() 0000000000005462 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelChannel::getHWChannel() 000000000000546c long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelChannel::getName() 000000000000547a long 0e SECT 01 0000 [.text] IOAccelCommandDescriptor::init(IOGraphicsAccelerator2*) 00000000000054c0 long 0e SECT 01 0000 [.text] __GLOBAL__I_a 0000000000005500 long 0e SECT 01 0000 [.text] __GLOBAL__D_a 0000000000005552 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelDevice::MetaClass::~MetaClass() 0000000000005864 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelDevice::MetaClass::~MetaClass() 0000000000005870 long 0e SECT 01 0000 [.text] __GLOBAL__I_a 00000000000058b0 long 0e SECT 01 0000 [.text] __GLOBAL__D_a 0000000000005902 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelDisplayMachine::MetaClass::~MetaClass() 0000000000007012 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDGraphicsAccelerator::getAccelChannel(_eAMD_HW_ENGINE_TYPE, _eAMD_HW_RING_TYPE) 00000000000093da long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelDisplayMachine::MetaClass::~MetaClass() 00000000000093e4 long 0e SECT 01 0000 [.text] IOAccelCommandDescriptor::init(IOGraphicsAccelerator2*) 0000000000009430 long 0e SECT 01 0000 [.text] __GLOBAL__I_a 0000000000009470 long 0e SECT 01 0000 [.text] __GLOBAL__D_a 00000000000094c2 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelEventMachine::MetaClass::~MetaClass() 000000000000a054 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelEventMachine::MetaClass::~MetaClass() 000000000000a05e long 0e SECT 01 0000 [.text] IOAccelEventMachine2::createEventQueue() 000000000000a066 long 0e SECT 01 0000 [.text] IOAccelEventMachine2::destroyEventQueue(IOAccelEventQueue*) 000000000000a06c long 0e SECT 01 0000 [.text] IOAccelEventMachine2::cleanEventQueue(IOAccelEventQueue*) 000000000000a072 long 0e SECT 01 0000 [.text] IOAccelEventMachineList2::enableEventCollection() 000000000000a080 long 0e SECT 01 0000 [.text] __GLOBAL__I_a 000000000000a0c0 long 0e SECT 01 0000 [.text] __GLOBAL__D_a 000000000000a112 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelResource::MetaClass::~MetaClass() 000000000001189e long 0e SECT 01 0000 [.text] IOAccelResource2::getRetainCount() const 00000000000118a8 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelResource::getAlignedLength() 00000000000118e0 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelResource::alignSurfaceToHTile(unsigned int*, unsigned int*) 00000000000118e6 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelResource::MetaClass::~MetaClass() 00000000000118f0 long 0e SECT 01 0000 [.text] __GLOBAL__I_a 0000000000011930 long 0e SECT 01 0000 [.text] __GLOBAL__D_a 0000000000011982 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelShared::MetaClass::~MetaClass() 00000000000120fc long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelSharedUserClient::MetaClass::~MetaClass() 0000000000012526 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelShared::MetaClass::~MetaClass() 0000000000012530 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelSharedUserClient::MetaClass::~MetaClass() 0000000000012540 long 0e SECT 01 0000 [.text] __GLOBAL__I_a 00000000000125a0 long 0e SECT 01 0000 [.text] __GLOBAL__D_a 00000000000125f2 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelStatistics::MetaClass::~MetaClass() 0000000000012894 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelStatistics::MetaClass::~MetaClass() 00000000000128a0 long 0e SECT 01 0000 [.text] __GLOBAL__I_a 00000000000128e0 long 0e SECT 01 0000 [.text] __GLOBAL__D_a 0000000000012932 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelSurface::MetaClass::~MetaClass() 0000000000015e92 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelSurface::MetaClass::~MetaClass() 0000000000015ea0 long 0e SECT 01 0000 [.text] __GLOBAL__I_a 0000000000015ee0 long 0e SECT 01 0000 [.text] __GLOBAL__D_a 0000000000015f32 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDAccel2DContext::MetaClass::~MetaClass() 0000000000016ac4 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDAccel2DContext::MetaClass::~MetaClass() 0000000000016ace long 0e SECT 01 0000 [.text] IOAccelContext2::getOwningTask() 0000000000016adc long 0e SECT 01 0000 [.text] IOAccelContext2::getGPUTask() 0000000000016aea long 0e SECT 01 0000 [.text] IOAccelContext2::getOwningTaskPid() 0000000000016af6 long 0e SECT 01 0000 [.text] IOAccelSubmitter2::retireCommandBuffer(IOAccelBlockFence*) 0000000000016afc long 0e SECT 01 0000 [.text] IOAccelContext2::postTokenSanityCheck(IOAccelCommandStreamInfo&) 0000000000016b02 long 0e SECT 01 0000 [.text] IOAccelContext2::getDataBufferPrivate(IOAccelResource2*, IOAccelResourcePrivate*, unsigned long long) 0000000000016b08 long 0e SECT 01 0000 [.text] IOAccelContext2::validateDataBuffer(unsigned long long, IOBufferMemoryDescriptor*, IOAccelResource2*) 0000000000016b10 long 0e SECT 01 0000 [.text] IOAccelContext2::invalidate() 0000000000016b16 long 0e SECT 01 0000 [.text] IOAccelContext2::getFrameDelimiter() 0000000000016b20 long 0e SECT 01 0000 [.text] __GLOBAL__I_a 0000000000016b60 long 0e SECT 01 0000 [.text] __GLOBAL__D_a 0000000000016bb2 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelCommandBufferPool::MetaClass::~MetaClass() 0000000000016d36 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelCommandBufferPool::MetaClass::~MetaClass() 0000000000016d40 long 0e SECT 01 0000 [.text] __GLOBAL__I_a 0000000000016d80 long 0e SECT 01 0000 [.text] __GLOBAL__D_a 0000000000016dd2 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDInterruptEventSource::MetaClass::~MetaClass() 0000000000016f64 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDInterruptEventSource::MetaClass::~MetaClass() 0000000000016f70 long 0e SECT 01 0000 [.text] __GLOBAL__I_a 0000000000016fb0 long 0e SECT 01 0000 [.text] __GLOBAL__D_a 0000000000017eae long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelVideoContext::MetaClass::~MetaClass() 00000000000192fc long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDGraphicsAccelerator::getAccelChannel(_eAMD_HW_ENGINE_TYPE, _eAMD_HW_RING_TYPE) 000000000001a656 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelVideoContext::MetaClass::~MetaClass() 000000000001a660 long 0e SECT 01 0000 [.text] IOAccelContext2::getOwningTask() 000000000001a66e long 0e SECT 01 0000 [.text] IOAccelContext2::getGPUTask() 000000000001a67c long 0e SECT 01 0000 [.text] IOAccelContext2::getOwningTaskPid() 000000000001a688 long 0e SECT 01 0000 [.text] IOAccelSubmitter2::retireCommandBuffer(IOAccelBlockFence*) 000000000001a68e long 0e SECT 01 0000 [.text] IOAccelContext2::postTokenSanityCheck(IOAccelCommandStreamInfo&) 000000000001a694 long 0e SECT 01 0000 [.text] IOAccelContext2::getDataBufferPrivate(IOAccelResource2*, IOAccelResourcePrivate*, unsigned long long) 000000000001a69a long 0e SECT 01 0000 [.text] IOAccelContext2::validateDataBuffer(unsigned long long, IOBufferMemoryDescriptor*, IOAccelResource2*) 000000000001a6a2 long 0e SECT 01 0000 [.text] IOAccelContext2::invalidate() 000000000001a6a8 long 0e SECT 01 0000 [.text] IOAccelContext2::getFrameDelimiter() 000000000001a6b0 long 0e SECT 01 0000 [.text] __GLOBAL__I_a 000000000001a6f0 long 0e SECT 01 0000 [.text] __GLOBAL__D_a 000000000001a742 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelUVDContext::MetaClass::~MetaClass() 000000000001abde long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelUVDContext::MetaClass::~MetaClass() 000000000001abf0 long 0e SECT 01 0000 [.text] __GLOBAL__I_a 000000000001ac30 long 0e SECT 01 0000 [.text] __GLOBAL__D_a 000000000001ac82 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDSPUAppContext::MetaClass::~MetaClass() 000000000001b80c long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDSPUEvent::MetaClass::~MetaClass() 000000000001bac8 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDSPUContext::MetaClass::~MetaClass() 000000000001e916 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDSPUAppContext::MetaClass::~MetaClass() 000000000001e920 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDSPUEvent::MetaClass::~MetaClass() 000000000001e92a long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDSPUContext::MetaClass::~MetaClass() 000000000001e940 long 0e SECT 01 0000 [.text] __GLOBAL__I_a 000000000001e9d0 long 0e SECT 01 0000 [.text] __GLOBAL__D_a 000000000001ea32 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelVCEContext::MetaClass::~MetaClass() 000000000001ecce long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDGraphicsAccelerator::getAccelChannel(_eAMD_HW_ENGINE_TYPE, _eAMD_HW_RING_TYPE) 000000000001f0ae long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelVCEContext::MetaClass::~MetaClass() 000000000001f0c0 long 0e SECT 01 0000 [.text] __GLOBAL__I_a 000000000001f100 long 0e SECT 01 0000 [.text] __GLOBAL__D_a 000000000001f152 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDTPTManager::MetaClass::~MetaClass() 0000000000021924 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDTPTManager::MetaClass::~MetaClass() 0000000000021930 long 0e SECT 01 0000 [.text] __GLOBAL__I_a 0000000000021970 long 0e SECT 01 0000 [.text] __GLOBAL__D_a 00000000000219c2 long 0e SECT 01 0000 [.text] AMDRadeonX4000_IAMDAtomicBlitManager::MetaClass::~MetaClass() 0000000000021a9c long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDAtomicBlitManager::MetaClass::~MetaClass() 0000000000021bd6 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDGraphicsAccelerator::getAccelChannel(_eAMD_HW_ENGINE_TYPE, _eAMD_HW_RING_TYPE) 0000000000022fb6 long 0e SECT 01 0000 [.text] AMDRadeonX4000_IAMDAtomicBlitManager::init() 0000000000022fc8 long 0e SECT 01 0000 [.text] AMDRadeonX4000_IAMDAtomicBlitManager::free() 0000000000022fda long 0e SECT 01 0000 [.text] AMDRadeonX4000_IAMDAtomicBlitManager::MetaClass::~MetaClass() 0000000000022fe4 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDAtomicBlitManager::MetaClass::~MetaClass() 0000000000022fee long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDAtomicBlitManager::GetError() const 0000000000023000 long 0e SECT 01 0000 [.text] __GLOBAL__I_a 0000000000023070 long 0e SECT 01 0000 [.text] __GLOBAL__D_a 00000000000230c2 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDBltMgr::MetaClass::~MetaClass() 0000000000024474 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDBltMgr::MetaClass::~MetaClass() 0000000000024480 long 0e SECT 01 0000 [.text] __GLOBAL__I_a 00000000000244c0 long 0e SECT 01 0000 [.text] __GLOBAL__D_a 0000000000024512 long 0e SECT 01 0000 [.text] AMDRadeonX4000_VendorGart::MetaClass::~MetaClass() 000000000002498c long 0e SECT 01 0000 [.text] AMDRadeonX4000_VendorGart::MetaClass::~MetaClass() 00000000000249a0 long 0e SECT 01 0000 [.text] __GLOBAL__I_a 00000000000249e0 long 0e SECT 01 0000 [.text] __GLOBAL__D_a 0000000000024a32 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHashTable::MetaClass::~MetaClass() 0000000000024efc long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHashTable::MetaClass::~MetaClass() 0000000000024f10 long 0e SECT 01 0000 [.text] __GLOBAL__I_a 0000000000024f50 long 0e SECT 01 0000 [.text] __GLOBAL__D_a 00000000000250d2 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDLinkedList::MetaClass::~MetaClass() 000000000002554a long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDLinkedList::MetaClass::~MetaClass() 0000000000025560 long 0e SECT 01 0000 [.text] __GLOBAL__I_a 00000000000255a0 long 0e SECT 01 0000 [.text] __GLOBAL__D_a 00000000000255f2 long 0e SECT 01 0000 [.text] AMDRadeonX4000_IAMDStatisticsManager::MetaClass::~MetaClass() 00000000000256cc long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelStatisticsManager::MetaClass::~MetaClass() 0000000000025c20 long 0e SECT 01 0000 [.text] AMDRadeonX4000_IAMDStatisticsManager::init() 0000000000025c32 long 0e SECT 01 0000 [.text] AMDRadeonX4000_IAMDStatisticsManager::free() 0000000000025c44 long 0e SECT 01 0000 [.text] AMDRadeonX4000_IAMDStatisticsManager::MetaClass::~MetaClass() 0000000000025c4e long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelStatisticsManager::MetaClass::~MetaClass() 0000000000025c60 long 0e SECT 01 0000 [.text] __GLOBAL__I_a 0000000000025cd0 long 0e SECT 01 0000 [.text] __GLOBAL__D_a 0000000000025d22 long 0e SECT 01 0000 [.text] AMDRadeonX4000_IAMDStatisticsGroup::MetaClass::~MetaClass() 0000000000025dfc long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelStatisticsGroup::MetaClass::~MetaClass() 000000000002613a long 0e SECT 01 0000 [.text] AMDRadeonX4000_IAMDStatisticsGroup::init() 000000000002614c long 0e SECT 01 0000 [.text] AMDRadeonX4000_IAMDStatisticsGroup::free() 000000000002615e long 0e SECT 01 0000 [.text] AMDRadeonX4000_IAMDStatisticsGroup::MetaClass::~MetaClass() 0000000000026168 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelStatisticsGroup::MetaClass::~MetaClass() 0000000000026172 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelStatisticsGroup::getTotalStats() 000000000002617c long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelStatisticsGroup::getGroupId() 0000000000026186 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelStatisticsGroup::getGroupName() 0000000000026190 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelStatisticsGroup::getGroupInfo() 00000000000261a0 long 0e SECT 01 0000 [.text] __GLOBAL__I_a 0000000000026210 long 0e SECT 01 0000 [.text] __GLOBAL__D_a 0000000000026262 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWChannelStatsGroup::MetaClass::~MetaClass() 00000000000264cc long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWChannelStatsGroup::MetaClass::~MetaClass() 00000000000264d6 long 0e SECT 01 0000 [.text] AMDRadeonX4000_IAMDStatisticsGroup::init() 00000000000264e8 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelStatisticsGroup::getTotalStats() 00000000000264f2 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelStatisticsGroup::getGroupId() 00000000000264fc long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelStatisticsGroup::getGroupName() 0000000000026506 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelStatisticsGroup::getGroupInfo() 0000000000026510 long 0e SECT 01 0000 [.text] __GLOBAL__I_a 0000000000026550 long 0e SECT 01 0000 [.text] __GLOBAL__D_a 00000000000265a2 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelCLContext::MetaClass::~MetaClass() 00000000000267d0 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDGraphicsAccelerator::getAccelChannel(_eAMD_HW_ENGINE_TYPE, _eAMD_HW_RING_TYPE) 00000000000271e0 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelCLContext::MetaClass::~MetaClass() 00000000000271ea long 0e SECT 01 0000 [.text] IOAccelContext2::getOwningTask() 00000000000271f8 long 0e SECT 01 0000 [.text] IOAccelContext2::getGPUTask() 0000000000027206 long 0e SECT 01 0000 [.text] IOAccelContext2::getOwningTaskPid() 0000000000027212 long 0e SECT 01 0000 [.text] IOAccelSubmitter2::retireCommandBuffer(IOAccelBlockFence*) 0000000000027218 long 0e SECT 01 0000 [.text] IOAccelContext2::postTokenSanityCheck(IOAccelCommandStreamInfo&) 000000000002721e long 0e SECT 01 0000 [.text] IOAccelContext2::getDataBufferPrivate(IOAccelResource2*, IOAccelResourcePrivate*, unsigned long long) 0000000000027224 long 0e SECT 01 0000 [.text] IOAccelContext2::validateDataBuffer(unsigned long long, IOBufferMemoryDescriptor*, IOAccelResource2*) 000000000002722c long 0e SECT 01 0000 [.text] IOAccelContext2::invalidate() 0000000000027232 long 0e SECT 01 0000 [.text] IOAccelContext2::getFrameDelimiter() 0000000000027240 long 0e SECT 01 0000 [.text] __GLOBAL__I_a 0000000000027280 long 0e SECT 01 0000 [.text] __GLOBAL__D_a 00000000000272d2 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelTask::MetaClass::~MetaClass() 0000000000027a60 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelTask::MetaClass::~MetaClass() 0000000000027a70 long 0e SECT 01 0000 [.text] __GLOBAL__I_a 0000000000027ab0 long 0e SECT 01 0000 [.text] __GLOBAL__D_a 0000000000027b02 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelSysMemory::MetaClass::~MetaClass() 0000000000027c9a long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelSysMemory::MetaClass::~MetaClass() 0000000000027ca4 long 0e SECT 01 0000 [.text] IOAccelMemory::getLength() 0000000000027cae long 0e SECT 01 0000 [.text] IOAccelSysMemory::setTag(unsigned int) 0000000000027cc6 long 0e SECT 01 0000 [.text] IOAccelSysMemory::getTag() 0000000000027ce0 long 0e SECT 01 0000 [.text] __GLOBAL__I_a 0000000000027d20 long 0e SECT 01 0000 [.text] __GLOBAL__D_a 0000000000027d72 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelVidMemory::MetaClass::~MetaClass() 000000000002847c long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelVidMemory::MetaClass::~MetaClass() 0000000000028486 long 0e SECT 01 0000 [.text] IOAccelMemory::getLength() 0000000000028490 long 0e SECT 01 0000 [.text] IOAccelVidMemory::setTag(unsigned int) 000000000002849a long 0e SECT 01 0000 [.text] IOAccelVidMemory::getTag() 00000000000284b0 long 0e SECT 01 0000 [.text] __GLOBAL__I_a 00000000000284f0 long 0e SECT 01 0000 [.text] __GLOBAL__D_a 0000000000028542 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelMemoryMap::MetaClass::~MetaClass() 0000000000028e2c long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelMemoryMap::MetaClass::~MetaClass() 0000000000028e36 long 0e SECT 01 0000 [.text] IOAccelMemoryMap::matchOptionBits(unsigned int) 0000000000028e40 long 0e SECT 01 0000 [.text] __GLOBAL__I_a 0000000000028e80 long 0e SECT 01 0000 [.text] __GLOBAL__D_a 0000000000028ed2 long 0e SECT 01 0000 [.text] AMDSIGraphicsAccelerator::MetaClass::~MetaClass() 00000000000291b6 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDGraphicsAccelerator::getAccelChannel(_eAMD_HW_ENGINE_TYPE, _eAMD_HW_RING_TYPE) 000000000002921e long 0e SECT 01 0000 [.text] AMDSIGraphicsAccelerator::MetaClass::~MetaClass() 0000000000029228 long 0e SECT 01 0000 [.text] IOGraphicsAccelerator2::getWorkLoop() const 0000000000029240 long 0e SECT 01 0000 [.text] __GLOBAL__I_a 0000000000029280 long 0e SECT 01 0000 [.text] __GLOBAL__D_a 00000000000292d2 long 0e SECT 01 0000 [.text] AMDPitcairnGraphicsAccelerator::MetaClass::~MetaClass() 000000000002952a long 0e SECT 01 0000 [.text] AMDPitcairnGraphicsAccelerator::MetaClass::~MetaClass() 0000000000029534 long 0e SECT 01 0000 [.text] IOGraphicsAccelerator2::getWorkLoop() const 0000000000029550 long 0e SECT 01 0000 [.text] __GLOBAL__I_a 0000000000029590 long 0e SECT 01 0000 [.text] __GLOBAL__D_a 00000000000295e2 long 0e SECT 01 0000 [.text] AMDTahitiGraphicsAccelerator::MetaClass::~MetaClass() 000000000002983a long 0e SECT 01 0000 [.text] AMDTahitiGraphicsAccelerator::MetaClass::~MetaClass() 0000000000029844 long 0e SECT 01 0000 [.text] IOGraphicsAccelerator2::getWorkLoop() const 0000000000029860 long 0e SECT 01 0000 [.text] __GLOBAL__I_a 00000000000298a0 long 0e SECT 01 0000 [.text] __GLOBAL__D_a 00000000000298f2 long 0e SECT 01 0000 [.text] AMDVerdeGraphicsAccelerator::MetaClass::~MetaClass() 0000000000029a78 long 0e SECT 01 0000 [.text] AMDVerdeGraphicsAccelerator::MetaClass::~MetaClass() 0000000000029a82 long 0e SECT 01 0000 [.text] IOGraphicsAccelerator2::getWorkLoop() const 0000000000029a90 long 0e SECT 01 0000 [.text] __GLOBAL__I_a 0000000000029ad0 long 0e SECT 01 0000 [.text] __GLOBAL__D_a 0000000000029b22 long 0e SECT 01 0000 [.text] AMDSIAtomicBlitManager::MetaClass::~MetaClass() 0000000000029f84 long 0e SECT 01 0000 [.text] AMDSIAtomicBlitManager::MetaClass::~MetaClass() 0000000000029f8e long 0e SECT 01 0000 [.text] AMDRadeonX4000_IAMDAtomicBlitManager::init() 0000000000029fa0 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDAtomicBlitManager::GetError() const 0000000000029fb0 long 0e SECT 01 0000 [.text] __GLOBAL__I_a 0000000000029ff0 long 0e SECT 01 0000 [.text] __GLOBAL__D_a 000000000002a042 long 0e SECT 01 0000 [.text] AMDSIDisplayMachine::MetaClass::~MetaClass() 000000000002a1a2 long 0e SECT 01 0000 [.text] AMDSIDisplayMachine::MetaClass::~MetaClass() 000000000002a1b0 long 0e SECT 01 0000 [.text] __GLOBAL__I_a 000000000002a1f0 long 0e SECT 01 0000 [.text] __GLOBAL__D_a 000000000002a242 long 0e SECT 01 0000 [.text] AMDSIResource::MetaClass::~MetaClass() 000000000002a8ba long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDGraphicsAccelerator::getAccelChannel(_eAMD_HW_ENGINE_TYPE, _eAMD_HW_RING_TYPE) 000000000002a930 long 0e SECT 01 0000 [.text] AMDSIResource::MetaClass::~MetaClass() 000000000002a93a long 0e SECT 01 0000 [.text] IOAccelResource2::getRetainCount() const 000000000002a944 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelResource::getAlignedLength() 000000000002a97c long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelResource::alignSurfaceToHTile(unsigned int*, unsigned int*) 000000000002a990 long 0e SECT 01 0000 [.text] __GLOBAL__I_a 000000000002a9d0 long 0e SECT 01 0000 [.text] __GLOBAL__D_a 000000000002aa22 long 0e SECT 01 0000 [.text] AMDSISurface::MetaClass::~MetaClass() 000000000002abc0 long 0e SECT 01 0000 [.text] AMDSISurface::MetaClass::~MetaClass() 000000000002abd0 long 0e SECT 01 0000 [.text] __GLOBAL__I_a 000000000002ac10 long 0e SECT 01 0000 [.text] __GLOBAL__D_a 000000000002ac62 long 0e SECT 01 0000 [.text] AMDSIVideoContext::MetaClass::~MetaClass() 000000000002adc2 long 0e SECT 01 0000 [.text] AMDSIVideoContext::MetaClass::~MetaClass() 000000000002adcc long 0e SECT 01 0000 [.text] IOAccelContext2::getOwningTask() 000000000002adda long 0e SECT 01 0000 [.text] IOAccelContext2::getGPUTask() 000000000002ade8 long 0e SECT 01 0000 [.text] IOAccelContext2::getOwningTaskPid() 000000000002adf4 long 0e SECT 01 0000 [.text] IOAccelSubmitter2::retireCommandBuffer(IOAccelBlockFence*) 000000000002adfa long 0e SECT 01 0000 [.text] IOAccelContext2::postTokenSanityCheck(IOAccelCommandStreamInfo&) 000000000002ae00 long 0e SECT 01 0000 [.text] IOAccelContext2::getDataBufferPrivate(IOAccelResource2*, IOAccelResourcePrivate*, unsigned long long) 000000000002ae06 long 0e SECT 01 0000 [.text] IOAccelContext2::validateDataBuffer(unsigned long long, IOBufferMemoryDescriptor*, IOAccelResource2*) 000000000002ae0e long 0e SECT 01 0000 [.text] IOAccelContext2::invalidate() 000000000002ae14 long 0e SECT 01 0000 [.text] IOAccelContext2::getFrameDelimiter() 000000000002ae20 long 0e SECT 01 0000 [.text] __GLOBAL__I_a 000000000002ae60 long 0e SECT 01 0000 [.text] __GLOBAL__D_a 0000000000031fac long 0e SECT 01 0000 [.text] AMDSIGLContext::MetaClass::~MetaClass() 0000000000034d5a long 0e SECT 01 0000 [.text] GetSurfaceBuffer(IOAccelSurface2*, IOAccelShared2*, eIOAccelGLBufferType) 0000000000034d8e long 0e SECT 01 0000 [.text] AMDSIGLContext::MetaClass::~MetaClass() 0000000000034d98 long 0e SECT 01 0000 [.text] IOAccelContext2::getOwningTask() 0000000000034da6 long 0e SECT 01 0000 [.text] IOAccelContext2::getGPUTask() 0000000000034db4 long 0e SECT 01 0000 [.text] IOAccelContext2::getOwningTaskPid() 0000000000034dc0 long 0e SECT 01 0000 [.text] IOAccelSubmitter2::retireCommandBuffer(IOAccelBlockFence*) 0000000000034dc6 long 0e SECT 01 0000 [.text] IOAccelContext2::postTokenSanityCheck(IOAccelCommandStreamInfo&) 0000000000034dcc long 0e SECT 01 0000 [.text] IOAccelContext2::getDataBufferPrivate(IOAccelResource2*, IOAccelResourcePrivate*, unsigned long long) 0000000000034dd2 long 0e SECT 01 0000 [.text] IOAccelContext2::validateDataBuffer(unsigned long long, IOBufferMemoryDescriptor*, IOAccelResource2*) 0000000000034dda long 0e SECT 01 0000 [.text] IOAccelContext2::getFrameDelimiter() 0000000000034de2 long 0e SECT 01 0000 [.text] IOAccelCommandDescriptor::init(IOGraphicsAccelerator2*) 0000000000034e20 long 0e SECT 01 0000 [.text] __GLOBAL__I_a 0000000000034e60 long 0e SECT 01 0000 [.text] __GLOBAL__D_a 000000000003a3ea long 0e SECT 01 0000 [.text] AMDSICLContext::MetaClass::~MetaClass() 000000000003a6fe long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDGraphicsAccelerator::getAccelChannel(_eAMD_HW_ENGINE_TYPE, _eAMD_HW_RING_TYPE) 000000000003cd54 long 0e SECT 01 0000 [.text] AMDSICLContext::MetaClass::~MetaClass() 000000000003cd5e long 0e SECT 01 0000 [.text] IOAccelContext2::getOwningTask() 000000000003cd6c long 0e SECT 01 0000 [.text] IOAccelContext2::getGPUTask() 000000000003cd7a long 0e SECT 01 0000 [.text] IOAccelContext2::getOwningTaskPid() 000000000003cd86 long 0e SECT 01 0000 [.text] IOAccelSubmitter2::retireCommandBuffer(IOAccelBlockFence*) 000000000003cd8c long 0e SECT 01 0000 [.text] IOAccelContext2::postTokenSanityCheck(IOAccelCommandStreamInfo&) 000000000003cd92 long 0e SECT 01 0000 [.text] IOAccelContext2::getDataBufferPrivate(IOAccelResource2*, IOAccelResourcePrivate*, unsigned long long) 000000000003cd98 long 0e SECT 01 0000 [.text] IOAccelContext2::validateDataBuffer(unsigned long long, IOBufferMemoryDescriptor*, IOAccelResource2*) 000000000003cda0 long 0e SECT 01 0000 [.text] IOAccelContext2::invalidate() 000000000003cda6 long 0e SECT 01 0000 [.text] IOAccelContext2::getFrameDelimiter() 000000000003cdae long 0e SECT 01 0000 [.text] AMDSICLContext::getSubmitRingBufferSize() 000000000003cdc0 long 0e SECT 01 0000 [.text] __GLOBAL__I_a 000000000003ce00 long 0e SECT 01 0000 [.text] __GLOBAL__D_a 000000000003ce52 long 0e SECT 01 0000 [.text] AMDCIGraphicsAccelerator::MetaClass::~MetaClass() 000000000003d10e long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDGraphicsAccelerator::getAccelChannel(_eAMD_HW_ENGINE_TYPE, _eAMD_HW_RING_TYPE) 000000000003d176 long 0e SECT 01 0000 [.text] AMDCIGraphicsAccelerator::MetaClass::~MetaClass() 000000000003d180 long 0e SECT 01 0000 [.text] IOGraphicsAccelerator2::getWorkLoop() const 000000000003d190 long 0e SECT 01 0000 [.text] __GLOBAL__I_a 000000000003d1d0 long 0e SECT 01 0000 [.text] __GLOBAL__D_a 000000000003d222 long 0e SECT 01 0000 [.text] AMDBonaireGraphicsAccelerator::MetaClass::~MetaClass() 000000000003d3a8 long 0e SECT 01 0000 [.text] AMDBonaireGraphicsAccelerator::MetaClass::~MetaClass() 000000000003d3b2 long 0e SECT 01 0000 [.text] IOGraphicsAccelerator2::getWorkLoop() const 000000000003d3c0 long 0e SECT 01 0000 [.text] __GLOBAL__I_a 000000000003d400 long 0e SECT 01 0000 [.text] __GLOBAL__D_a 000000000003d452 long 0e SECT 01 0000 [.text] AMDHawaiiGraphicsAccelerator::MetaClass::~MetaClass() 000000000003d5d8 long 0e SECT 01 0000 [.text] AMDHawaiiGraphicsAccelerator::MetaClass::~MetaClass() 000000000003d5e2 long 0e SECT 01 0000 [.text] IOGraphicsAccelerator2::getWorkLoop() const 000000000003d5f0 long 0e SECT 01 0000 [.text] __GLOBAL__I_a 000000000003d630 long 0e SECT 01 0000 [.text] __GLOBAL__D_a 000000000003d682 long 0e SECT 01 0000 [.text] AMDCIResource::MetaClass::~MetaClass() 000000000003e254 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDGraphicsAccelerator::getAccelChannel(_eAMD_HW_ENGINE_TYPE, _eAMD_HW_RING_TYPE) 000000000003e34e long 0e SECT 01 0000 [.text] AMDCIResource::MetaClass::~MetaClass() 000000000003e358 long 0e SECT 01 0000 [.text] IOAccelResource2::getRetainCount() const 000000000003e362 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelResource::getAlignedLength() 000000000003e39a long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelResource::alignSurfaceToHTile(unsigned int*, unsigned int*) 000000000003e3a0 long 0e SECT 01 0000 [.text] __GLOBAL__I_a 000000000003e3e0 long 0e SECT 01 0000 [.text] __GLOBAL__D_a 0000000000043aa2 long 0e SECT 01 0000 [.text] AMDCICLContext::MetaClass::~MetaClass() 0000000000043e10 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDGraphicsAccelerator::getAccelChannel(_eAMD_HW_ENGINE_TYPE, _eAMD_HW_RING_TYPE) 00000000000465ae long 0e SECT 01 0000 [.text] AMDCICLContext::MetaClass::~MetaClass() 00000000000465b8 long 0e SECT 01 0000 [.text] IOAccelContext2::getOwningTask() 00000000000465c6 long 0e SECT 01 0000 [.text] IOAccelContext2::getGPUTask() 00000000000465d4 long 0e SECT 01 0000 [.text] IOAccelContext2::getOwningTaskPid() 00000000000465e0 long 0e SECT 01 0000 [.text] IOAccelSubmitter2::retireCommandBuffer(IOAccelBlockFence*) 00000000000465e6 long 0e SECT 01 0000 [.text] IOAccelContext2::postTokenSanityCheck(IOAccelCommandStreamInfo&) 00000000000465ec long 0e SECT 01 0000 [.text] IOAccelContext2::getDataBufferPrivate(IOAccelResource2*, IOAccelResourcePrivate*, unsigned long long) 00000000000465f2 long 0e SECT 01 0000 [.text] IOAccelContext2::validateDataBuffer(unsigned long long, IOBufferMemoryDescriptor*, IOAccelResource2*) 00000000000465fa long 0e SECT 01 0000 [.text] IOAccelContext2::invalidate() 0000000000046600 long 0e SECT 01 0000 [.text] IOAccelContext2::getFrameDelimiter() 0000000000046608 long 0e SECT 01 0000 [.text] AMDCICLContext::getSubmitRingBufferSize() 0000000000046620 long 0e SECT 01 0000 [.text] __GLOBAL__I_a 0000000000046660 long 0e SECT 01 0000 [.text] __GLOBAL__D_a 00000000000466b2 long 0e SECT 01 0000 [.text] AMDVIGraphicsAccelerator::MetaClass::~MetaClass() 000000000004696e long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDGraphicsAccelerator::getAccelChannel(_eAMD_HW_ENGINE_TYPE, _eAMD_HW_RING_TYPE) 00000000000469d6 long 0e SECT 01 0000 [.text] AMDVIGraphicsAccelerator::MetaClass::~MetaClass() 00000000000469e0 long 0e SECT 01 0000 [.text] IOGraphicsAccelerator2::getWorkLoop() const 00000000000469f0 long 0e SECT 01 0000 [.text] __GLOBAL__I_a 0000000000046a30 long 0e SECT 01 0000 [.text] __GLOBAL__D_a 0000000000046a82 long 0e SECT 01 0000 [.text] AMDTongaGraphicsAccelerator::MetaClass::~MetaClass() 0000000000046cda long 0e SECT 01 0000 [.text] AMDTongaGraphicsAccelerator::MetaClass::~MetaClass() 0000000000046ce4 long 0e SECT 01 0000 [.text] IOGraphicsAccelerator2::getWorkLoop() const 0000000000046d00 long 0e SECT 01 0000 [.text] __GLOBAL__I_a 0000000000046d40 long 0e SECT 01 0000 [.text] __GLOBAL__D_a 0000000000046d92 long 0e SECT 01 0000 [.text] AMDVIDisplayMachine::MetaClass::~MetaClass() 0000000000046ef2 long 0e SECT 01 0000 [.text] AMDVIDisplayMachine::MetaClass::~MetaClass() 0000000000046f00 long 0e SECT 01 0000 [.text] __GLOBAL__I_a 0000000000046f40 long 0e SECT 01 0000 [.text] __GLOBAL__D_a 0000000000046f92 long 0e SECT 01 0000 [.text] AMDVIResource::MetaClass::~MetaClass() 0000000000047b78 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDGraphicsAccelerator::getAccelChannel(_eAMD_HW_ENGINE_TYPE, _eAMD_HW_RING_TYPE) 0000000000047c72 long 0e SECT 01 0000 [.text] AMDVIResource::MetaClass::~MetaClass() 0000000000047c7c long 0e SECT 01 0000 [.text] IOAccelResource2::getRetainCount() const 0000000000047c86 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelResource::getAlignedLength() 0000000000047cbe long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelResource::alignSurfaceToHTile(unsigned int*, unsigned int*) 0000000000047cd0 long 0e SECT 01 0000 [.text] __GLOBAL__I_a 0000000000047d10 long 0e SECT 01 0000 [.text] __GLOBAL__D_a 0000000000047d62 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWHandler::MetaClass::~MetaClass() 000000000004857e long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWHandler::MetaClass::~MetaClass() 0000000000048588 long 0e SECT 01 0000 [.text] AMDRadeonX4000_IAMDHWHandler::init() 000000000004859a long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWHandler::gpuStateChangedEvent(bool) 00000000000485b4 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWHandler::isAccelEnabled() 00000000000485c8 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWHandler::getDiagnosticMode() 00000000000485d8 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWHandler::gartUsedSpaceInBytesChangedEvent(unsigned int) 00000000000485de long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWHandler::getNumericProperty(char const*) 00000000000485ec long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWHandler::getNumericProperty(char const*, unsigned int*) 00000000000485fa long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWHandler::printSlotNumber() 0000000000048608 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWHandler::getSlotNumber() 0000000000048618 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWHandler::getAccelBlitStructsStretch() 0000000000048628 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWHandler::getAccelBlitStructsMemcpy() 0000000000048638 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWHandler::getAccelID() 0000000000048648 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWHandler::getAccelIDStr() 0000000000048658 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWHandler::getAccelChannel(int) 0000000000048674 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWHandler::getGlobalCommandBufferPool(IOAccelChannel2*) 000000000004868a long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWHandler::getGlobalCommandBufferPool(_eAMD_HW_ENGINE_TYPE, _eAMD_HW_RING_TYPE) 000000000004870a long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWHandler::freeAllGPUMappings() 000000000004871c long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWHandler::getEventMachine() 000000000004872e long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWHandler::createSurfaceBuffer() 000000000004874a long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWHandler::createResource() 0000000000048758 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWHandler::signalVBL() 0000000000048766 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWHandler::getAccelConfigBits() 0000000000048776 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWHandler::writeAccleratorDiagnosisReport(char*&, unsigned int&) 000000000004878c long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWHandler::enableHWMemoryCleanupThread(unsigned int) 000000000004879a long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWHandler::disableHWMemoryCleanupThread() 00000000000487a8 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWHandler::getVCxtPMLock() 00000000000487c0 long 0e SECT 01 0000 [.text] __GLOBAL__I_a 0000000000048800 long 0e SECT 01 0000 [.text] __GLOBAL__D_a 0000000000048852 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWChannel::MetaClass::~MetaClass() 000000000004a87a long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWChannel::MetaClass::~MetaClass() 000000000004a884 long 0e SECT 01 0000 [.text] AMDRadeonX4000_IAMDHWChannel::init() 000000000004a896 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWChannel::getChannelIndex() 000000000004a8a0 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWChannel::getChannelRingType() 000000000004a8bc long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWChannel::initializeSubmitCommandBufferInfo(AMD_SUBMIT_COMMAND_BUFFER_INFO*) 000000000004a8d2 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWChannel::alignCommandBufferAddress(unsigned int) 000000000004a8e8 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWChannel::writeSemaphoreCommand(unsigned int*, unsigned long long, bool) const 000000000004a8f0 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWChannel::getName() 000000000004a8fa long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWChannel::dumpEngineHangState(bool) 000000000004a914 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWChannel::writeProfilingCommand(unsigned int*, unsigned long long, unsigned int, bool) 000000000004a91c long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWChannel::engineType() 000000000004a92e long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWChannel::isDebugFlagEnabled(unsigned int) 000000000004a942 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWChannel::getTimestampInterruptRef() 000000000004a94c long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWChannel::getHWStatisticsGroupTable() 000000000004a95a long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWChannel::clearInterrupEnableFlag() 000000000004a964 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWChannel::getIndirectCommandSize() 000000000004a970 long 0e SECT 01 0000 [.text] __GLOBAL__I_a 000000000004a9b0 long 0e SECT 01 0000 [.text] __GLOBAL__D_a 000000000004aa02 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWDisplay::MetaClass::~MetaClass() 000000000004dd40 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWDisplay::getBuiltIn(unsigned int) 000000000004dd5c long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWDisplay::getBuiltInExists() 000000000004dd6a long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWDisplay::getInterlaced(unsigned int) 000000000004dd84 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWDisplay::setFullScreenEnabled(unsigned int, bool) 000000000004dda8 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWDisplay::getFullScreenEnabled(unsigned int) 000000000004ddc4 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWDisplay::isFEDSEnabled() 000000000004ddd2 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWDisplay::isFEDSEnabled(unsigned int) 000000000004ddee long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWDisplay::FEDSIsColorBuffer(unsigned int) 000000000004de06 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWDisplay::FEDSSetIsColorBuffer(unsigned int, unsigned int) 000000000004de1e long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWDisplay::isAnyDisplayModeAccelBacked() 000000000004de2a long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWDisplay::isDisplayModeAccelBacked(unsigned int) 000000000004de44 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWDisplay::getScalerFlags(unsigned int) 000000000004de66 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWDisplay::isScaledNeeded() 000000000004deae long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWDisplay::isScaledNeeded(unsigned int) 000000000004dece long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWDisplay::isFedsRequired() 000000000004df16 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWDisplay::isFedsRequired(unsigned int) 000000000004df4c long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWDisplay::getFedsParamInfo() const 000000000004df56 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWDisplay::isFEDSBufferDirty(unsigned int) 000000000004df70 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWDisplay::MetaClass::~MetaClass() 000000000004df80 long 0e SECT 01 0000 [.text] __GLOBAL__I_a 000000000004dfc0 long 0e SECT 01 0000 [.text] __GLOBAL__D_a 000000000004e012 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWUtilities::MetaClass::~MetaClass() 000000000004e264 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWUtilities::MetaClass::~MetaClass() 000000000004e26e long 0e SECT 01 0000 [.text] AMDRadeonX4000_IAMDHWUtilities::init() 000000000004e280 long 0e SECT 01 0000 [.text] __GLOBAL__I_a 000000000004e2c0 long 0e SECT 01 0000 [.text] __GLOBAL__D_a 000000000004e312 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDUVDInterruptEventSource::MetaClass::~MetaClass() 000000000004e4b6 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDUVDHWChannel::MetaClass::~MetaClass() 000000000004ec54 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDUVDInterruptEventSource::MetaClass::~MetaClass() 000000000004ec5e long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDUVDHWChannel::MetaClass::~MetaClass() 000000000004ec68 long 0e SECT 01 0000 [.text] AMDRadeonX4000_IAMDHWChannel::init() 000000000004ec7a long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWChannel::getChannelIndex() 000000000004ec84 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWChannel::getChannelRingType() 000000000004eca0 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWChannel::initializeSubmitCommandBufferInfo(AMD_SUBMIT_COMMAND_BUFFER_INFO*) 000000000004ecb6 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWChannel::alignCommandBufferAddress(unsigned int) 000000000004eccc long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWChannel::writeSemaphoreCommand(unsigned int*, unsigned long long, bool) const 000000000004ecd4 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWChannel::getName() 000000000004ecde long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWChannel::dumpEngineHangState(bool) 000000000004ecf8 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWChannel::writeProfilingCommand(unsigned int*, unsigned long long, unsigned int, bool) 000000000004ed00 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWChannel::engineType() 000000000004ed12 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWChannel::isDebugFlagEnabled(unsigned int) 000000000004ed26 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWChannel::getTimestampInterruptRef() 000000000004ed30 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWChannel::getHWStatisticsGroupTable() 000000000004ed3e long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWChannel::clearInterrupEnableFlag() 000000000004ed48 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWChannel::getIndirectCommandSize() 000000000004ed54 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDUVDHWChannel::capPerfTableStatesForUVD(bool) 000000000004ed60 long 0e SECT 01 0000 [.text] __GLOBAL__I_a 000000000004edc0 long 0e SECT 01 0000 [.text] __GLOBAL__D_a 000000000004ee12 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDDMAHWChannel::MetaClass::~MetaClass() 000000000004ef34 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDDMAHWChannel::MetaClass::~MetaClass() 000000000004ef3e long 0e SECT 01 0000 [.text] AMDRadeonX4000_IAMDHWChannel::init() 000000000004ef50 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWChannel::getChannelIndex() 000000000004ef5a long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWChannel::getChannelRingType() 000000000004ef76 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWChannel::initializeSubmitCommandBufferInfo(AMD_SUBMIT_COMMAND_BUFFER_INFO*) 000000000004ef8c long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWChannel::alignCommandBufferAddress(unsigned int) 000000000004efa2 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWChannel::writeSemaphoreCommand(unsigned int*, unsigned long long, bool) const 000000000004efaa long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWChannel::getName() 000000000004efb4 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWChannel::dumpEngineHangState(bool) 000000000004efce long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWChannel::writeProfilingCommand(unsigned int*, unsigned long long, unsigned int, bool) 000000000004efd6 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWChannel::engineType() 000000000004efe8 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWChannel::isDebugFlagEnabled(unsigned int) 000000000004effc long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWChannel::getTimestampInterruptRef() 000000000004f006 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWChannel::getHWStatisticsGroupTable() 000000000004f014 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWChannel::clearInterrupEnableFlag() 000000000004f01e long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWChannel::getIndirectCommandSize() 000000000004f02a long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDDMAHWChannel::getDmaPktInfo(AMD_DMA_COMMAND_TYPE) const 000000000004f040 long 0e SECT 01 0000 [.text] __GLOBAL__I_a 000000000004f080 long 0e SECT 01 0000 [.text] __GLOBAL__D_a 000000000004f0d2 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDDMAHWEngine::MetaClass::~MetaClass() 000000000004f436 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDDMAHWEngine::MetaClass::~MetaClass() 000000000004f440 long 0e SECT 01 0000 [.text] AMDRadeonX4000_IAMDHWEngine::init() 000000000004f452 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWEngine::type() 000000000004f45c long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWEngine::isEnabled() 000000000004f466 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWEngine::setVirtualSpaceReady(bool) 000000000004f46c long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDDMAHWEngine::setMemoryAllocationsEnabled(bool) 000000000004f472 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDDMAHWEngine::initializeRegisters() 000000000004f478 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDDMAHWEngine::systemWillChangeSpeedEvent() 000000000004f47e long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDDMAHWEngine::systemDidChangeSpeedEvent() 000000000004f484 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWEngine::getVersion(unsigned int) 000000000004f494 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWEngine::getChannelCount() 000000000004f49e long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWEngine::getTimestampIRQSourcex(_eAMD_HW_RING_TYPE) 000000000004f4a6 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWEngine::getFwvFunction() 000000000004f4b0 long 0e SECT 01 0000 [.text] __GLOBAL__I_a 000000000004f4f0 long 0e SECT 01 0000 [.text] __GLOBAL__D_a 000000000004f542 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWAlignManager::MetaClass::~MetaClass() 00000000000501fa long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWAlignManager::MetaClass::~MetaClass() 0000000000050204 long 0e SECT 01 0000 [.text] AMDRadeonX4000_IAMDHWAlignManager::init() 0000000000050216 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWAlignManager::getHandle() 0000000000050220 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWAlignManager::getAddrTileMode(unsigned int) 0000000000050228 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWAlignManager::getArrayMode(_AddrTileMode) 0000000000050230 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWAlignManager::getTileType(unsigned int) 0000000000050238 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWAlignManager::getMicroTileMode(_AddrTileType) 0000000000050240 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWAlignManager::getLinearAlignedTileIndex() 000000000005024a long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWAlignManager::getLinearGeneralTileIndex() 0000000000050260 long 0e SECT 01 0000 [.text] __GLOBAL__I_a 00000000000502a0 long 0e SECT 01 0000 [.text] __GLOBAL__D_a 00000000000502f2 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDNullHWChannel::MetaClass::~MetaClass() 0000000000050452 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDNullHWChannel::init() 0000000000050464 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDNullHWChannel::free() 0000000000050476 long 0e SECT 01 0000 [.text] AMDRadeonX4000_IAMDHWChannel::init(int, AMDRadeonX4000_IAMDHWInterface*, AMDRadeonX4000_IAMDHWEngine*, AMDRadeonX4000_IAMDHWRing*, char const*) 0000000000050488 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDNullHWChannel::getChannelIndex() 0000000000050494 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDNullHWChannel::getChannelRingType() 000000000005049c long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDNullHWChannel::isEnabled() 00000000000504a4 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDNullHWChannel::isEmpty() 00000000000504ac long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDNullHWChannel::isIdle() 00000000000504b4 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDNullHWChannel::limitedWaitForIdle(unsigned int, unsigned int) 00000000000504bc long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDNullHWChannel::waitForIdle() 00000000000504c2 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDNullHWChannel::initializeSubmitCommandBufferInfo(AMD_SUBMIT_COMMAND_BUFFER_INFO*) 00000000000504c8 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDNullHWChannel::submitCommandBuffer(AMD_SUBMIT_COMMAND_BUFFER_INFO*, unsigned int*) 00000000000504d0 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDNullHWChannel::waitForTimestamp(unsigned int, unsigned long long*, bool) 00000000000504d8 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDNullHWChannel::checkForTimestamp(unsigned int) 00000000000504e0 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDNullHWChannel::waitForLastSubmittedTimestamp() 00000000000504e8 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDNullHWChannel::getCommandSubmitTimestamp() 00000000000504f4 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDNullHWChannel::getCommandLastReadTimestamp() 00000000000504fc long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDNullHWChannel::setCommandTimestampPairs(unsigned int*, unsigned int*) 0000000000050502 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDNullHWChannel::alignIBCommandBuffer(unsigned int*, unsigned int) 000000000005050a long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDNullHWChannel::alignCommandBufferAddress(unsigned int) 0000000000050512 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDNullHWChannel::getIBAlignmentFactor() 000000000005051a long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDNullHWChannel::getOneDwordNOPCommand() 0000000000050522 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDNullHWChannel::writeSurfaceSyncCommand(unsigned int*, unsigned int, unsigned long long, unsigned long long, unsigned int) 000000000005052c long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDNullHWChannel::writeEventWriteCommand(unsigned int*, unsigned int, unsigned int) 0000000000050536 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDNullHWChannel::writeEventWriteEOPCommand(unsigned int*, unsigned int, unsigned int, unsigned long long, unsigned int, unsigned int, unsigned long long) 0000000000050540 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDNullHWChannel::writeSemaphoreCommand(unsigned int*, unsigned long long, bool) const 0000000000050548 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDNullHWChannel::getName() 0000000000050556 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDNullHWChannel::setDebugFlags(unsigned int) 000000000005055c long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDNullHWChannel::clearDebugFlags(unsigned int) 0000000000050562 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDNullHWChannel::timeStampEnableInterruptAndSleep(unsigned int) 000000000005056a long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDNullHWChannel::timeStampDisableInterrupt() 0000000000050570 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDNullHWChannel::isTimeStampExpired(unsigned int) 0000000000050578 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDNullHWChannel::vblEnableInterrupt() 000000000005057e long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDNullHWChannel::vblDisableInterrupt() 0000000000050584 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDNullHWChannel::dumpEngineHangState(bool) 000000000005058a long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDNullHWChannel::hasPendingWaitCommands(unsigned int) 0000000000050592 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDNullHWChannel::writeProfilingCommand(unsigned int*, unsigned long long, unsigned int, bool) 000000000005059a long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDNullHWChannel::engineType() 00000000000505a6 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDNullHWChannel::writeDiagnosisReport(char*&, unsigned int&) 00000000000505ac long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDNullHWChannel::isDebugFlagEnabled(unsigned int) 00000000000505b4 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDNullHWChannel::MetaClass::~MetaClass() 00000000000505c0 long 0e SECT 01 0000 [.text] __GLOBAL__I_a 0000000000050600 long 0e SECT 01 0000 [.text] __GLOBAL__D_a 0000000000050652 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWEngine::MetaClass::~MetaClass() 0000000000050efa long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWEngine::MetaClass::~MetaClass() 0000000000050f04 long 0e SECT 01 0000 [.text] AMDRadeonX4000_IAMDHWEngine::init() 0000000000050f16 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWEngine::type() 0000000000050f20 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWEngine::isEnabled() 0000000000050f2a long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWEngine::setVirtualSpaceReady(bool) 0000000000050f30 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWEngine::getVersion(unsigned int) 0000000000050f40 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWEngine::getChannelCount() 0000000000050f4a long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWEngine::getTimestampIRQSourcex(_eAMD_HW_RING_TYPE) 0000000000050f52 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWEngine::getFwvFunction() 0000000000050f60 long 0e SECT 01 0000 [.text] __GLOBAL__I_a 0000000000050fa0 long 0e SECT 01 0000 [.text] __GLOBAL__D_a 0000000000050ff2 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDNullHWEngine::MetaClass::~MetaClass() 0000000000051152 long 0e SECT 01 0000 [.text] AMDRadeonX4000_IAMDHWEngine::init() 0000000000051164 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDNullHWEngine::free() 0000000000051176 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDNullHWEngine::type() 0000000000051182 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDNullHWEngine::powerUp() 000000000005118a long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDNullHWEngine::powerOff() 0000000000051192 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDNullHWEngine::start() 000000000005119a long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDNullHWEngine::stop() 00000000000511a2 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDNullHWEngine::isEnabled() 00000000000511aa long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDNullHWEngine::setVirtualSpaceReady(bool) 00000000000511b0 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDNullHWEngine::setMemoryAllocationsEnabled(bool) 00000000000511b6 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDNullHWEngine::initializeRegisters() 00000000000511bc long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDNullHWEngine::systemWillChangeSpeedEvent() 00000000000511c2 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDNullHWEngine::systemDidChangeSpeedEvent() 00000000000511c8 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDNullHWEngine::initializeSubmitCommandBufferInfo(AMD_SUBMIT_COMMAND_BUFFER_INFO*) 00000000000511ce long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDNullHWEngine::isIdle() 00000000000511d6 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDNullHWEngine::limitedWaitForIdle(unsigned int, unsigned int) 00000000000511de long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDNullHWEngine::waitForIdle() 00000000000511e4 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDNullHWEngine::alignCommandBufferAddress(unsigned int) 00000000000511ec long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDNullHWEngine::getVersion(unsigned int) 00000000000511f4 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDNullHWEngine::getChannelCount() 00000000000511fc long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDNullHWEngine::getHWChannel(_eAMD_HW_RING_TYPE) 0000000000051204 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDNullHWEngine::getTimestampIRQSourcex(_eAMD_HW_RING_TYPE) 000000000005120c long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDNullHWEngine::getFwvFunction() 0000000000051214 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDNullHWEngine::dumpEngineHangState(bool) 000000000005121a long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDNullHWEngine::writeDiagnosisReport(char*&, unsigned int&) 0000000000051220 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDNullHWEngine::reset(_eAMD_HW_RING_TYPE) 0000000000051228 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDNullHWEngine::init(AMDRadeonX4000_IAMDHWInterface*, _eAMD_HW_ENGINE_TYPE) 000000000005123a long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDNullHWEngine::MetaClass::~MetaClass() 0000000000051250 long 0e SECT 01 0000 [.text] __GLOBAL__I_a 0000000000051290 long 0e SECT 01 0000 [.text] __GLOBAL__D_a 00000000000512e2 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWGart::MetaClass::~MetaClass() 000000000005248c long 0e SECT 01 0000 [.text] AMDRadeonX4000_IAMDHWGart::init() 000000000005249e long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWGart::getVirtualSpaceRemappingBaseAddress() 00000000000524a8 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWGart::getSize() 00000000000524b2 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWGart::getBaseTableAddress() 00000000000524c0 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWGart::getBaseTablePadSize() 00000000000524cc long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWGart::getTotalAllocationSize() 00000000000524f2 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWGart::MetaClass::~MetaClass() 0000000000052500 long 0e SECT 01 0000 [.text] __GLOBAL__I_a 0000000000052540 long 0e SECT 01 0000 [.text] __GLOBAL__D_a 0000000000052592 long 0e SECT 01 0000 [.text] AMDRadeonX4000_IAMDHWInterface::MetaClass::~MetaClass() 000000000005266c long 0e SECT 01 0000 [.text] AMDRadeonX4000_IAMDHWDisplay::MetaClass::~MetaClass() 0000000000052746 long 0e SECT 01 0000 [.text] AMDRadeonX4000_IAMDHWHandler::MetaClass::~MetaClass() 0000000000052820 long 0e SECT 01 0000 [.text] AMDRadeonX4000_IAMDHWAlignManager::MetaClass::~MetaClass() 00000000000528fa long 0e SECT 01 0000 [.text] AMDRadeonX4000_IAMDHWRegisters::MetaClass::~MetaClass() 00000000000529d4 long 0e SECT 01 0000 [.text] AMDRadeonX4000_IAMDHWMemory::MetaClass::~MetaClass() 0000000000052aae long 0e SECT 01 0000 [.text] AMDRadeonX4000_IAMDHWGart::MetaClass::~MetaClass() 0000000000052b88 long 0e SECT 01 0000 [.text] AMDRadeonX4000_IAMDHWRing::MetaClass::~MetaClass() 0000000000052c62 long 0e SECT 01 0000 [.text] AMDRadeonX4000_IAMDHWSemaphore::MetaClass::~MetaClass() 0000000000052d3c long 0e SECT 01 0000 [.text] AMDRadeonX4000_IAMDHWSemaphorePool::MetaClass::~MetaClass() 0000000000052e16 long 0e SECT 01 0000 [.text] AMDRadeonX4000_IAMDHWSemaphoreMemMgr::MetaClass::~MetaClass() 0000000000052ef0 long 0e SECT 01 0000 [.text] AMDRadeonX4000_IAMDHWUtilities::MetaClass::~MetaClass() 0000000000052fca long 0e SECT 01 0000 [.text] AMDRadeonX4000_IAMDPM4CommandsUtility::MetaClass::~MetaClass() 00000000000530a4 long 0e SECT 01 0000 [.text] AMDRadeonX4000_IAMDHWEngine::MetaClass::~MetaClass() 000000000005317e long 0e SECT 01 0000 [.text] AMDRadeonX4000_IAMDHWChannel::MetaClass::~MetaClass() 0000000000053258 long 0e SECT 01 0000 [.text] AMDRadeonX4000_IAMDHWVMM::MetaClass::~MetaClass() 0000000000053332 long 0e SECT 01 0000 [.text] AMDRadeonX4000_IAMDHWVMContext::MetaClass::~MetaClass() 00000000000533da long 0e SECT 01 0000 [.text] AMDRadeonX4000_IAMDHWMemory::init() 00000000000533ec long 0e SECT 01 0000 [.text] AMDRadeonX4000_IAMDHWMemory::free() 00000000000533fe long 0e SECT 01 0000 [.text] AMDRadeonX4000_IAMDHWInterface::init() 0000000000053410 long 0e SECT 01 0000 [.text] AMDRadeonX4000_IAMDHWInterface::free() 0000000000053422 long 0e SECT 01 0000 [.text] AMDRadeonX4000_IAMDHWInterface::MetaClass::~MetaClass() 000000000005342c long 0e SECT 01 0000 [.text] AMDRadeonX4000_IAMDHWDisplay::MetaClass::~MetaClass() 0000000000053436 long 0e SECT 01 0000 [.text] AMDRadeonX4000_IAMDHWHandler::init() 0000000000053448 long 0e SECT 01 0000 [.text] AMDRadeonX4000_IAMDHWHandler::free() 000000000005345a long 0e SECT 01 0000 [.text] AMDRadeonX4000_IAMDHWHandler::MetaClass::~MetaClass() 0000000000053464 long 0e SECT 01 0000 [.text] AMDRadeonX4000_IAMDHWAlignManager::init() 0000000000053476 long 0e SECT 01 0000 [.text] AMDRadeonX4000_IAMDHWAlignManager::free() 0000000000053488 long 0e SECT 01 0000 [.text] AMDRadeonX4000_IAMDHWAlignManager::MetaClass::~MetaClass() 0000000000053492 long 0e SECT 01 0000 [.text] AMDRadeonX4000_IAMDHWRegisters::init() 00000000000534a4 long 0e SECT 01 0000 [.text] AMDRadeonX4000_IAMDHWRegisters::free() 00000000000534b6 long 0e SECT 01 0000 [.text] AMDRadeonX4000_IAMDHWRegisters::MetaClass::~MetaClass() 00000000000534c0 long 0e SECT 01 0000 [.text] AMDRadeonX4000_IAMDHWMemory::MetaClass::~MetaClass() 00000000000534ca long 0e SECT 01 0000 [.text] AMDRadeonX4000_IAMDHWGart::init() 00000000000534dc long 0e SECT 01 0000 [.text] AMDRadeonX4000_IAMDHWGart::free() 00000000000534ee long 0e SECT 01 0000 [.text] AMDRadeonX4000_IAMDHWGart::MetaClass::~MetaClass() 00000000000534f8 long 0e SECT 01 0000 [.text] AMDRadeonX4000_IAMDHWRing::init() 000000000005350a long 0e SECT 01 0000 [.text] AMDRadeonX4000_IAMDHWRing::free() 000000000005351c long 0e SECT 01 0000 [.text] AMDRadeonX4000_IAMDHWRing::MetaClass::~MetaClass() 0000000000053526 long 0e SECT 01 0000 [.text] AMDRadeonX4000_IAMDHWSemaphore::init() 0000000000053538 long 0e SECT 01 0000 [.text] AMDRadeonX4000_IAMDHWSemaphore::free() 000000000005354a long 0e SECT 01 0000 [.text] AMDRadeonX4000_IAMDHWSemaphore::MetaClass::~MetaClass() 0000000000053554 long 0e SECT 01 0000 [.text] AMDRadeonX4000_IAMDHWSemaphorePool::init() 0000000000053566 long 0e SECT 01 0000 [.text] AMDRadeonX4000_IAMDHWSemaphorePool::free() 0000000000053578 long 0e SECT 01 0000 [.text] AMDRadeonX4000_IAMDHWSemaphorePool::MetaClass::~MetaClass() 0000000000053582 long 0e SECT 01 0000 [.text] AMDRadeonX4000_IAMDHWSemaphoreMemMgr::init() 0000000000053594 long 0e SECT 01 0000 [.text] AMDRadeonX4000_IAMDHWSemaphoreMemMgr::free() 00000000000535a6 long 0e SECT 01 0000 [.text] AMDRadeonX4000_IAMDHWSemaphoreMemMgr::MetaClass::~MetaClass() 00000000000535b0 long 0e SECT 01 0000 [.text] AMDRadeonX4000_IAMDHWUtilities::init() 00000000000535c2 long 0e SECT 01 0000 [.text] AMDRadeonX4000_IAMDHWUtilities::free() 00000000000535d4 long 0e SECT 01 0000 [.text] AMDRadeonX4000_IAMDHWUtilities::MetaClass::~MetaClass() 00000000000535de long 0e SECT 01 0000 [.text] AMDRadeonX4000_IAMDPM4CommandsUtility::init() 00000000000535f0 long 0e SECT 01 0000 [.text] AMDRadeonX4000_IAMDPM4CommandsUtility::free() 0000000000053602 long 0e SECT 01 0000 [.text] AMDRadeonX4000_IAMDPM4CommandsUtility::MetaClass::~MetaClass() 000000000005360c long 0e SECT 01 0000 [.text] AMDRadeonX4000_IAMDHWEngine::init() 000000000005361e long 0e SECT 01 0000 [.text] AMDRadeonX4000_IAMDHWEngine::free() 0000000000053630 long 0e SECT 01 0000 [.text] AMDRadeonX4000_IAMDHWEngine::MetaClass::~MetaClass() 000000000005363a long 0e SECT 01 0000 [.text] AMDRadeonX4000_IAMDHWChannel::init() 000000000005364c long 0e SECT 01 0000 [.text] AMDRadeonX4000_IAMDHWChannel::free() 000000000005365e long 0e SECT 01 0000 [.text] AMDRadeonX4000_IAMDHWChannel::init(int, AMDRadeonX4000_IAMDHWInterface*, AMDRadeonX4000_IAMDHWEngine*, AMDRadeonX4000_IAMDHWRing*, char const*) 0000000000053670 long 0e SECT 01 0000 [.text] AMDRadeonX4000_IAMDHWChannel::MetaClass::~MetaClass() 000000000005367a long 0e SECT 01 0000 [.text] AMDRadeonX4000_IAMDHWVMM::init() 000000000005368c long 0e SECT 01 0000 [.text] AMDRadeonX4000_IAMDHWVMM::free() 000000000005369e long 0e SECT 01 0000 [.text] AMDRadeonX4000_IAMDHWVMM::MetaClass::~MetaClass() 00000000000536a8 long 0e SECT 01 0000 [.text] AMDRadeonX4000_IAMDHWVMContext::init() 00000000000536ba long 0e SECT 01 0000 [.text] AMDRadeonX4000_IAMDHWVMContext::free() 00000000000536cc long 0e SECT 01 0000 [.text] AMDRadeonX4000_IAMDHWVMContext::MetaClass::~MetaClass() 00000000000536e0 long 0e SECT 01 0000 [.text] __GLOBAL__I_a 00000000000539b0 long 0e SECT 01 0000 [.text] __GLOBAL__D_a 0000000000053ac2 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWMemory::MetaClass::~MetaClass() 000000000005553a long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWMemory::MetaClass::~MetaClass() 0000000000055544 long 0e SECT 01 0000 [.text] AMDRadeonX4000_IAMDHWMemory::init() 0000000000055556 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWMemory::getMemoryDescriptor() 0000000000055564 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWMemory::isMapped() 0000000000055570 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWMemory::setReservedNdrvSpace(unsigned long long) 000000000005557a long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWMemory::getTotalSize() 0000000000055584 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWMemory::getVisibleSize() 000000000005558e long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWMemory::getInvisibleSize() 000000000005559c long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWMemory::isNonVisibleMemoryExists() 00000000000555b0 long 0e SECT 01 0000 [.text] __GLOBAL__I_a 00000000000555f0 long 0e SECT 01 0000 [.text] __GLOBAL__D_a 0000000000055642 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWRegisters::MetaClass::~MetaClass() 0000000000055b4c long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWRegisters::MetaClass::~MetaClass() 0000000000055b56 long 0e SECT 01 0000 [.text] AMDRadeonX4000_IAMDHWRegisters::init() 0000000000055b68 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWRegisters::isEnabled() 0000000000055b80 long 0e SECT 01 0000 [.text] __GLOBAL__I_a 0000000000055bc0 long 0e SECT 01 0000 [.text] __GLOBAL__D_a 0000000000055c12 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWRing::MetaClass::~MetaClass() 000000000005661c long 0e SECT 01 0000 [.text] AMDRadeonX4000_IAMDHWRing::init() 000000000005662e long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWRing::isEnabled() 0000000000056638 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWRing::getHead() 0000000000056648 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWRing::getTail() 0000000000056654 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWRing::getFreeSpace() 0000000000056684 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWRing::isEmpty() 00000000000566b2 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWRing::getRingGartAddr() 00000000000566bc long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWRing::getSize() 00000000000566c6 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWRing::getRingBlock(unsigned int) 00000000000566d8 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWRing::commitBlock(unsigned int) 00000000000566e8 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWRing::getRingId() 00000000000566f4 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWRing::MetaClass::~MetaClass() 0000000000056700 long 0e SECT 01 0000 [.text] __GLOBAL__I_a 0000000000056740 long 0e SECT 01 0000 [.text] __GLOBAL__D_a 0000000000056792 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWSemaphore::MetaClass::~MetaClass() 0000000000056ca6 long 0e SECT 01 0000 [.text] AMDRadeonX4000_IAMDHWSemaphore::init() 0000000000056cb8 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWSemaphore::setTag(unsigned int) 0000000000056cc4 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWSemaphore::getTag() 0000000000056cd0 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWSemaphore::waitForDone() 0000000000056cfc long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWSemaphore::registerEventListener(AMDRadeonX4000_IAMDHWInterface*, _eAMD_HW_EVENT_TYPE) 0000000000056d04 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWSemaphore::unregisterEventListener(AMDRadeonX4000_IAMDHWInterface*, _eAMD_HW_EVENT_TYPE) 0000000000056d0c long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWSemaphore::getSignalEvent() 0000000000056d16 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWSemaphore::getWaitEvent() 0000000000056d20 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWSemaphore::MetaClass::~MetaClass() 0000000000056d30 long 0e SECT 01 0000 [.text] __GLOBAL__I_a 0000000000056d70 long 0e SECT 01 0000 [.text] __GLOBAL__D_a 0000000000056dc2 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDNullHWSemaphore::MetaClass::~MetaClass() 0000000000056f22 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDNullHWSemaphore::MetaClass::~MetaClass() 0000000000056f2c long 0e SECT 01 0000 [.text] AMDRadeonX4000_IAMDHWSemaphore::init() 0000000000056f3e long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDNullHWSemaphore::free() 0000000000056f44 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDNullHWSemaphore::wait(IOAccelEvent*, int, unsigned int*, unsigned int&) 0000000000056f4c long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDNullHWSemaphore::signal(IOAccelEvent*, int, unsigned int*, unsigned int&) 0000000000056f54 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDNullHWSemaphore::done() 0000000000056f5c long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDNullHWSemaphore::reset() 0000000000056f62 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDNullHWSemaphore::setState(bool) 0000000000056f68 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDNullHWSemaphore::setTag(unsigned int) 0000000000056f72 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDNullHWSemaphore::getTag() 0000000000056f7c long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDNullHWSemaphore::waitForDone() 0000000000056f82 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDNullHWSemaphore::registerEventListener(AMDRadeonX4000_IAMDHWInterface*, _eAMD_HW_EVENT_TYPE) 0000000000056f8a long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDNullHWSemaphore::unregisterEventListener(AMDRadeonX4000_IAMDHWInterface*, _eAMD_HW_EVENT_TYPE) 0000000000056f92 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDNullHWSemaphore::getSignalEvent() 0000000000056f9a long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDNullHWSemaphore::getWaitEvent() 0000000000056fa2 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDNullHWSemaphore::init(AMDRadeonX4000_IAMDHWInterface*, bool) 0000000000056faa long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDNullHWSemaphore::getEngine() const 0000000000056fb6 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDNullHWSemaphore::getStamp() const 0000000000056fc0 long 0e SECT 01 0000 [.text] __GLOBAL__I_a 0000000000057000 long 0e SECT 01 0000 [.text] __GLOBAL__D_a 0000000000057052 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWSemaphorePool::MetaClass::~MetaClass() 000000000005773c long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWSemaphorePool::MetaClass::~MetaClass() 0000000000057746 long 0e SECT 01 0000 [.text] AMDRadeonX4000_IAMDHWSemaphorePool::init() 0000000000057758 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWSemaphorePool::releaseSemaphoreData(unsigned long long) 0000000000057770 long 0e SECT 01 0000 [.text] __GLOBAL__I_a 00000000000577b0 long 0e SECT 01 0000 [.text] __GLOBAL__D_a 0000000000057802 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWSemaphoreMemMgr::MetaClass::~MetaClass() 0000000000057c70 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWSemaphoreMemMgr::MetaClass::~MetaClass() 0000000000057c7a long 0e SECT 01 0000 [.text] AMDRadeonX4000_IAMDHWSemaphoreMemMgr::init() 0000000000057c90 long 0e SECT 01 0000 [.text] __GLOBAL__I_a 0000000000057cd0 long 0e SECT 01 0000 [.text] __GLOBAL__D_a 0000000000057d22 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWVMContext::MetaClass::~MetaClass() 0000000000058b24 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWVMContext::MetaClass::~MetaClass() 0000000000058b2e long 0e SECT 01 0000 [.text] AMDRadeonX4000_IAMDHWVMContext::init() 0000000000058b40 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWVMContext::mapLocalVA(unsigned long long, unsigned long long, unsigned long long) 0000000000058b66 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWVMContext::mapSystemVA(unsigned long long, IOMemoryDescriptor*) 0000000000058b90 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWVMContext::mapSystemVA(unsigned long long, unsigned long long, unsigned long long) 0000000000058bb8 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWVMContext::getCurrentVMID() 0000000000058bd4 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWVMContext::getPDBaseAddress() 0000000000058be2 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWVMContext::isPageTableUpdated() 0000000000058bee long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWVMContext::clearPageTableUpdated() 0000000000058c00 long 0e SECT 01 0000 [.text] __GLOBAL__I_a 0000000000058c40 long 0e SECT 01 0000 [.text] __GLOBAL__D_a 0000000000058c92 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWVMM::MetaClass::~MetaClass() 00000000000598a4 long 0e SECT 01 0000 [.text] AMDRadeonX4000_IAMDHWVMM::init() 00000000000598b6 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWVMM::getBaseAddress() 00000000000598c0 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWVMM::getVMPTVirtualAddress() 00000000000598ca long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWVMM::getVMPTVirtualAddress(unsigned long long) 0000000000059902 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWVMM::getVMRangeStart() 000000000005990c long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWVMM::getVMRangeEnd() 000000000005991a long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWVMM::getVMPTBCoverage() 0000000000059928 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWVMM::getVMPTBVRAMSize() 0000000000059936 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWVMM::getVMPTDVRAMSize() 0000000000059944 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWVMM::getVMPTBTotal() 0000000000059952 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWVMM::getVMPTBPerPTB() 0000000000059960 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWVMM::getFragmentStrategy() 000000000005996c long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWVMM::getBIGKValue() 0000000000059978 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWVMM::getBIGKInBytes() 0000000000059984 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWVMM::getFragmentAlignment() 0000000000059990 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWVMM::MetaClass::~MetaClass() 00000000000599a0 long 0e SECT 01 0000 [.text] __GLOBAL__I_a 00000000000599e0 long 0e SECT 01 0000 [.text] __GLOBAL__D_a 0000000000059a32 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDNULLVMM::MetaClass::~MetaClass() 0000000000059b92 long 0e SECT 01 0000 [.text] AMDRadeonX4000_IAMDHWVMM::init() 0000000000059ba4 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDNULLVMM::free() 0000000000059bb6 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDNULLVMM::init(AMDRadeonX4000_IAMDHWInterface*) 0000000000059bc8 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDNULLVMM::setVirtualSpaceReady(bool) 0000000000059bce long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDNULLVMM::setMemoryAllocationsEnabled(bool) 0000000000059bd4 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDNULLVMM::createVMContext() 0000000000059bdc long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDNULLVMM::releaseVMContext(AMDRadeonX4000_IAMDHWVMContext*) 0000000000059be2 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDNULLVMM::removeFromVMIDList(AMDRadeonX4000_IAMDHWVMContext*) 0000000000059be8 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDNULLVMM::allocVMPD(GLKMemoryElement*) 0000000000059bee long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDNULLVMM::freeVMPD(GLKMemoryElement*) 0000000000059bf4 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDNULLVMM::allocVMPTB(GLKMemoryElement*) 0000000000059bfa long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDNULLVMM::freeVMPTB(GLKMemoryElement*) 0000000000059c00 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDNULLVMM::assignVMID(AMDRadeonX4000_IAMDHWVMContext*, unsigned int&, AMDRadeonX4000_IAMDHWChannel*, IOAccelEvent**, bool*) 0000000000059c08 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDNULLVMM::getCurrentVMID(AMDRadeonX4000_IAMDHWVMContext*) 0000000000059c10 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDNULLVMM::getBaseAddress() 0000000000059c18 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDNULLVMM::getVMPTVirtualAddress() 0000000000059c20 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDNULLVMM::getVMPTVirtualAddress(unsigned long long) 0000000000059c28 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDNULLVMM::getVMRangeStart() 0000000000059c30 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDNULLVMM::getVMRangeEnd() 0000000000059c38 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDNULLVMM::getVMPTBCoverage() 0000000000059c40 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDNULLVMM::getVMPTBVRAMSize() 0000000000059c48 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDNULLVMM::getVMPTDVRAMSize() 0000000000059c50 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDNULLVMM::getVMPTBTotal() 0000000000059c58 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDNULLVMM::getVMPTBPerPTB() 0000000000059c60 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDNULLVMM::getMinVMID() 0000000000059c68 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDNULLVMM::getMaxVMID() 0000000000059c70 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDNULLVMM::isInVMReservedPool(unsigned long long) 0000000000059c78 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDNULLVMM::getFragmentStrategy() 0000000000059c80 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDNULLVMM::getBIGKValue() 0000000000059c88 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDNULLVMM::getBIGKInBytes() 0000000000059c90 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDNULLVMM::getFragmentAlignment() 0000000000059c98 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDNULLVMM::MetaClass::~MetaClass() 0000000000059cb0 long 0e SECT 01 0000 [.text] __GLOBAL__I_a 0000000000059cf0 long 0e SECT 01 0000 [.text] __GLOBAL__D_a 0000000000059d42 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHardware::MetaClass::~MetaClass() 000000000005dce2 long 0e SECT 01 0000 [.text] AMDRadeonX4000_IAMDHWInterface::init() 000000000005dcf4 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHardware::getHWMemoryDescriptor() 000000000005dd02 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHardware::getChipEngine() 000000000005dd0e long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHardware::getConfigBits() 000000000005dd1a long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHardware::getHWCapabilities() 000000000005dd24 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHardware::getAMDHwCailAdapterInfo() 000000000005dd32 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHardware::getMaskSettings() 000000000005dd40 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHardware::getChipID() 000000000005dd4c long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHardware::getChipRev() 000000000005dd58 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHardware::getSubSystemID() 000000000005dd64 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHardware::getFamily() 000000000005dd70 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHardware::getPreDefinedNdrvVramReservedSpace() 000000000005dd7c long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHardware::setTLBInvalidateNeeded(unsigned int) 000000000005dd92 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHardware::getDiagReportBuffer() 000000000005ddae long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHardware::getDiagReportBufferSize() 000000000005ddba long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHardware::verifyThreadsActive() 000000000005ddc2 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHardware::isEnabled() 000000000005ddce long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHardware::isMultiEngineSyncEnabled() 000000000005ddda long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHardware::getCailHandle() 000000000005dde8 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHardware::getAMDHWHandler() 000000000005ddf2 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHardware::getHWRegisters() 000000000005de00 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHardware::getHWMemory() 000000000005de0e long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHardware::getHWGart() 000000000005de1c long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHardware::getHWVMM() 000000000005de2a long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHardware::getHWDisplay() 000000000005de38 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHardware::getHWAlignManager() 000000000005de46 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHardware::getAMDHWUtilities() 000000000005de54 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHardware::getHWEngine(_eAMD_HW_ENGINE_TYPE) 000000000005de64 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHardware::getChannelCount() 000000000005de70 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHardware::getChannelWriteBackDescriptor() 000000000005de7e long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHardware::getChannelWriteBackFrameSize() 000000000005de8a long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHardware::getChannelWritePointerPollOffset(int) 000000000005de92 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHardware::getChannelWritePointerPollAddr(int) 000000000005de9a long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHardware::getHWSemaphorePool() 000000000005dea8 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHardware::getIOPCIDevice() 000000000005deb2 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHardware::getSML() 000000000005dec0 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHardware::getPM4CommandsUtility() 000000000005dece long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHardware::getGpuDebugPolicy() 000000000005deda long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHardware::getCailIri() const 000000000005dee8 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHardware::setPPLibIri(CAIL_IRI_REGISTRY_STRUCT*) 000000000005df30 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHardware::getGPUVMDefaultSettings() 000000000005df38 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHardware::MetaClass::~MetaClass() 000000000005df50 long 0e SECT 01 0000 [.text] __GLOBAL__I_a 000000000005df90 long 0e SECT 01 0000 [.text] __GLOBAL__D_a 000000000005dfe2 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDPM4CommandsUtility::MetaClass::~MetaClass() 000000000005e794 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDPM4CommandsUtility::MetaClass::~MetaClass() 000000000005e7a0 long 0e SECT 01 0000 [.text] __GLOBAL__I_a 000000000005e7e0 long 0e SECT 01 0000 [.text] __GLOBAL__D_a 000000000005e832 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDPM4HWEngine::MetaClass::~MetaClass() 000000000005eb3c long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDPM4HWEngine::MetaClass::~MetaClass() 000000000005eb46 long 0e SECT 01 0000 [.text] AMDRadeonX4000_IAMDHWEngine::init() 000000000005eb58 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWEngine::type() 000000000005eb62 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWEngine::isEnabled() 000000000005eb6c long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWEngine::setVirtualSpaceReady(bool) 000000000005eb72 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDPM4HWEngine::setMemoryAllocationsEnabled(bool) 000000000005eb78 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDPM4HWEngine::initializeRegisters() 000000000005eba8 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDPM4HWEngine::systemDidChangeSpeedEvent() 000000000005ebae long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWEngine::getVersion(unsigned int) 000000000005ebbe long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWEngine::getChannelCount() 000000000005ebc8 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWEngine::getTimestampIRQSourcex(_eAMD_HW_RING_TYPE) 000000000005ebd0 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWEngine::getFwvFunction() 000000000005ebe0 long 0e SECT 01 0000 [.text] __GLOBAL__I_a 000000000005ec20 long 0e SECT 01 0000 [.text] __GLOBAL__D_a 000000000005ec72 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDPM4HWChannel::MetaClass::~MetaClass() 000000000005eef6 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDPM4HWChannel::MetaClass::~MetaClass() 000000000005ef00 long 0e SECT 01 0000 [.text] AMDRadeonX4000_IAMDHWChannel::init() 000000000005ef12 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWChannel::getChannelIndex() 000000000005ef1c long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWChannel::getChannelRingType() 000000000005ef38 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWChannel::initializeSubmitCommandBufferInfo(AMD_SUBMIT_COMMAND_BUFFER_INFO*) 000000000005ef4e long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWChannel::alignCommandBufferAddress(unsigned int) 000000000005ef64 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWChannel::getName() 000000000005ef6e long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWChannel::dumpEngineHangState(bool) 000000000005ef88 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWChannel::writeProfilingCommand(unsigned int*, unsigned long long, unsigned int, bool) 000000000005ef90 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWChannel::engineType() 000000000005efa2 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWChannel::isDebugFlagEnabled(unsigned int) 000000000005efb6 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWChannel::getTimestampInterruptRef() 000000000005efc0 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWChannel::getHWStatisticsGroupTable() 000000000005efce long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWChannel::clearInterrupEnableFlag() 000000000005efd8 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWChannel::getIndirectCommandSize() 000000000005efe4 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDPM4HWChannel::enableScratchRegisterWriteback() 000000000005efea long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDPM4HWChannel::disableScratchRegisterWriteback() 000000000005eff0 long 0e SECT 01 0000 [.text] __GLOBAL__I_a 000000000005f030 long 0e SECT 01 0000 [.text] __GLOBAL__D_a 000000000005f082 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDSPUHWEngine::MetaClass::~MetaClass() 000000000005fa7c long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDSPUHWEngine::MetaClass::~MetaClass() 000000000005fa86 long 0e SECT 01 0000 [.text] AMDRadeonX4000_IAMDHWEngine::init() 000000000005fa98 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWEngine::type() 000000000005faa2 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWEngine::isEnabled() 000000000005faac long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWEngine::setVirtualSpaceReady(bool) 000000000005fab2 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDSPUHWEngine::initializeRegisters() 000000000005fab8 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDSPUHWEngine::systemWillChangeSpeedEvent() 000000000005fabe long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDSPUHWEngine::systemDidChangeSpeedEvent() 000000000005fac4 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDSPUHWEngine::alignCommandBufferAddress(unsigned int) 000000000005fad6 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWEngine::getVersion(unsigned int) 000000000005fae6 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWEngine::getChannelCount() 000000000005faf0 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWEngine::getTimestampIRQSourcex(_eAMD_HW_RING_TYPE) 000000000005faf8 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWEngine::getFwvFunction() 000000000005fb00 long 0e SECT 01 0000 [.text] __GLOBAL__I_a 000000000005fb40 long 0e SECT 01 0000 [.text] __GLOBAL__D_a 000000000005fb92 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDSPUHWChannel::MetaClass::~MetaClass() 000000000005fc9c long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDSPUHWChannel::MetaClass::~MetaClass() 000000000005fca6 long 0e SECT 01 0000 [.text] AMDRadeonX4000_IAMDHWChannel::init() 000000000005fcb8 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWChannel::getChannelIndex() 000000000005fcc2 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWChannel::getChannelRingType() 000000000005fcde long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWChannel::initializeSubmitCommandBufferInfo(AMD_SUBMIT_COMMAND_BUFFER_INFO*) 000000000005fcf4 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWChannel::alignCommandBufferAddress(unsigned int) 000000000005fd0a long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDSPUHWChannel::getIBAlignmentFactor() 000000000005fd16 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDSPUHWChannel::getOneDwordNOPCommand() 000000000005fd22 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWChannel::writeSemaphoreCommand(unsigned int*, unsigned long long, bool) const 000000000005fd2a long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWChannel::getName() 000000000005fd34 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWChannel::dumpEngineHangState(bool) 000000000005fd4e long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWChannel::writeProfilingCommand(unsigned int*, unsigned long long, unsigned int, bool) 000000000005fd56 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWChannel::engineType() 000000000005fd68 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWChannel::isDebugFlagEnabled(unsigned int) 000000000005fd7c long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWChannel::getTimestampInterruptRef() 000000000005fd86 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWChannel::getHWStatisticsGroupTable() 000000000005fd94 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWChannel::clearInterrupEnableFlag() 000000000005fd9e long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDSPUHWChannel::getIndirectCommandSize() 000000000005fdb0 long 0e SECT 01 0000 [.text] __GLOBAL__I_a 000000000005fdf0 long 0e SECT 01 0000 [.text] __GLOBAL__D_a 000000000005fe42 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDVCEHWEngine::MetaClass::~MetaClass() 0000000000060c32 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDVCEHWEngine::MetaClass::~MetaClass() 0000000000060c3c long 0e SECT 01 0000 [.text] AMDRadeonX4000_IAMDHWEngine::init() 0000000000060c4e long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWEngine::type() 0000000000060c58 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWEngine::isEnabled() 0000000000060c62 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWEngine::setVirtualSpaceReady(bool) 0000000000060c68 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDVCEHWEngine::initializeRegisters() 0000000000060c6e long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDVCEHWEngine::systemWillChangeSpeedEvent() 0000000000060c74 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDVCEHWEngine::systemDidChangeSpeedEvent() 0000000000060c7a long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDVCEHWEngine::alignCommandBufferAddress(unsigned int) 0000000000060c86 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWEngine::getVersion(unsigned int) 0000000000060c96 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWEngine::getChannelCount() 0000000000060ca0 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWEngine::getTimestampIRQSourcex(_eAMD_HW_RING_TYPE) 0000000000060ca8 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWEngine::getFwvFunction() 0000000000060cb0 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDVCEHWEngine::dumpEngineHangState(bool) 0000000000060cb6 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDVCEHWEngine::getTotalCapability() 0000000000060cca long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDVCEHWEngine::getCurrentCapability() 0000000000060cde long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDVCEHWEngine::getVCEVClk() 0000000000060cea long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDVCEHWEngine::getVCECClk() 0000000000060d00 long 0e SECT 01 0000 [.text] __GLOBAL__I_a 0000000000060d40 long 0e SECT 01 0000 [.text] __GLOBAL__D_a 0000000000060d92 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDVCEHWChannel::MetaClass::~MetaClass() 0000000000060efe long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDVCEHWChannel::MetaClass::~MetaClass() 0000000000060f08 long 0e SECT 01 0000 [.text] AMDRadeonX4000_IAMDHWChannel::init() 0000000000060f1a long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWChannel::getChannelIndex() 0000000000060f24 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWChannel::getChannelRingType() 0000000000060f40 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWChannel::initializeSubmitCommandBufferInfo(AMD_SUBMIT_COMMAND_BUFFER_INFO*) 0000000000060f56 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWChannel::alignCommandBufferAddress(unsigned int) 0000000000060f6c long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDVCEHWChannel::getIBAlignmentFactor() 0000000000060f78 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDVCEHWChannel::getOneDwordNOPCommand() 0000000000060f80 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWChannel::writeSemaphoreCommand(unsigned int*, unsigned long long, bool) const 0000000000060f88 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWChannel::getName() 0000000000060f92 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWChannel::dumpEngineHangState(bool) 0000000000060fac long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWChannel::writeProfilingCommand(unsigned int*, unsigned long long, unsigned int, bool) 0000000000060fb4 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWChannel::engineType() 0000000000060fc6 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWChannel::isDebugFlagEnabled(unsigned int) 0000000000060fda long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWChannel::getTimestampInterruptRef() 0000000000060fe4 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWChannel::getHWStatisticsGroupTable() 0000000000060ff2 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWChannel::clearInterrupEnableFlag() 0000000000060ffc long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWChannel::getIndirectCommandSize() 0000000000061010 long 0e SECT 01 0000 [.text] __GLOBAL__I_a 0000000000061050 long 0e SECT 01 0000 [.text] __GLOBAL__D_a 00000000000610a2 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDUVDHWEngine::MetaClass::~MetaClass() 00000000000629f0 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDUVDHWEngine::MetaClass::~MetaClass() 00000000000629fa long 0e SECT 01 0000 [.text] AMDRadeonX4000_IAMDHWEngine::init() 0000000000062a0c long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWEngine::type() 0000000000062a16 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDUVDHWEngine::initializeRegisters() 0000000000062a1c long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDUVDHWEngine::systemWillChangeSpeedEvent() 0000000000062a22 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDUVDHWEngine::systemDidChangeSpeedEvent() 0000000000062a28 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWEngine::getVersion(unsigned int) 0000000000062a38 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWEngine::getChannelCount() 0000000000062a42 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWEngine::getTimestampIRQSourcex(_eAMD_HW_RING_TYPE) 0000000000062a4a long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWEngine::getFwvFunction() 0000000000062a52 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDUVDHWEngine::getFirmwareAddress() 0000000000062a60 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDUVDHWEngine::getTotalCapability() 0000000000062a74 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDUVDHWEngine::getCurrentCapability() 0000000000062a88 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDUVDHWEngine::getUVDVclk() 0000000000062a94 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDUVDHWEngine::getUVDDclk() 0000000000062aa0 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDUVDHWEngine::getHWRegisters() 0000000000062aaa long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDUVDHWEngine::getKeySelect() 0000000000062ab6 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDUVDHWEngine::setDpmSupported(bool) 0000000000062ac4 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDUVDHWEngine::commitUVDFWMsg(_SML_UVD_MSG*, unsigned long long, unsigned long long) 0000000000062ad0 long 0e SECT 01 0000 [.text] __GLOBAL__I_a 0000000000062b10 long 0e SECT 01 0000 [.text] __GLOBAL__D_a 0000000000062b62 long 0e SECT 01 0000 [.text] AMDSIHWMemory::MetaClass::~MetaClass() 00000000000631de long 0e SECT 01 0000 [.text] AMDSIHWMemory::MetaClass::~MetaClass() 00000000000631e8 long 0e SECT 01 0000 [.text] AMDRadeonX4000_IAMDHWMemory::init() 00000000000631fa long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWMemory::getMemoryDescriptor() 0000000000063208 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWMemory::isMapped() 0000000000063214 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWMemory::setReservedNdrvSpace(unsigned long long) 000000000006321e long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWMemory::getTotalSize() 0000000000063228 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWMemory::getVisibleSize() 0000000000063232 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWMemory::getInvisibleSize() 0000000000063240 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWMemory::isNonVisibleMemoryExists() 0000000000063260 long 0e SECT 01 0000 [.text] __GLOBAL__I_a 00000000000632a0 long 0e SECT 01 0000 [.text] __GLOBAL__D_a 00000000000632f2 long 0e SECT 01 0000 [.text] AMDSIDisplay::MetaClass::~MetaClass() 0000000000064a8e long 0e SECT 01 0000 [.text] AMDSIDisplay::MetaClass::~MetaClass() 0000000000064a98 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWDisplay::getBuiltIn(unsigned int) 0000000000064ab4 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWDisplay::getBuiltInExists() 0000000000064ac2 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWDisplay::getInterlaced(unsigned int) 0000000000064adc long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWDisplay::setFullScreenEnabled(unsigned int, bool) 0000000000064b00 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWDisplay::getFullScreenEnabled(unsigned int) 0000000000064b1c long 0e SECT 01 0000 [.text] AMDSIDisplay::getNumberOfSupportedDisplays() 0000000000064b28 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWDisplay::isFEDSEnabled() 0000000000064b36 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWDisplay::isFEDSEnabled(unsigned int) 0000000000064b52 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWDisplay::FEDSIsColorBuffer(unsigned int) 0000000000064b6a long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWDisplay::FEDSSetIsColorBuffer(unsigned int, unsigned int) 0000000000064b82 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWDisplay::isAnyDisplayModeAccelBacked() 0000000000064b8e long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWDisplay::isDisplayModeAccelBacked(unsigned int) 0000000000064ba8 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWDisplay::getScalerFlags(unsigned int) 0000000000064bca long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWDisplay::isScaledNeeded() 0000000000064c12 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWDisplay::isScaledNeeded(unsigned int) 0000000000064c32 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWDisplay::isFedsRequired() 0000000000064c7a long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWDisplay::isFedsRequired(unsigned int) 0000000000064cb0 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWDisplay::getFedsParamInfo() const 0000000000064cba long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWDisplay::isFEDSBufferDirty(unsigned int) 0000000000064cd4 long 0e SECT 01 0000 [.text] AMDSIDisplay::writeTilingControlRegisters(unsigned int, unsigned int*, unsigned int) 0000000000064ce0 long 0e SECT 01 0000 [.text] __GLOBAL__I_a 0000000000064d20 long 0e SECT 01 0000 [.text] __GLOBAL__D_a 0000000000064d72 long 0e SECT 01 0000 [.text] AMDSIHWUtilities::MetaClass::~MetaClass() 0000000000065076 long 0e SECT 01 0000 [.text] AMDSIHWUtilities::MetaClass::~MetaClass() 0000000000065080 long 0e SECT 01 0000 [.text] AMDRadeonX4000_IAMDHWUtilities::init() 00000000000650a0 long 0e SECT 01 0000 [.text] __GLOBAL__I_a 00000000000650e0 long 0e SECT 01 0000 [.text] __GLOBAL__D_a 0000000000065132 long 0e SECT 01 0000 [.text] AMDSIVMContext::MetaClass::~MetaClass() 000000000006648e long 0e SECT 01 0000 [.text] AMDSIVMContext::MetaClass::~MetaClass() 0000000000066498 long 0e SECT 01 0000 [.text] AMDRadeonX4000_IAMDHWVMContext::init() 00000000000664aa long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWVMContext::mapLocalVA(unsigned long long, unsigned long long, unsigned long long) 00000000000664d0 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWVMContext::mapSystemVA(unsigned long long, IOMemoryDescriptor*) 00000000000664fa long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWVMContext::mapSystemVA(unsigned long long, unsigned long long, unsigned long long) 0000000000066522 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWVMContext::getCurrentVMID() 000000000006653e long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWVMContext::getPDBaseAddress() 000000000006654c long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWVMContext::isPageTableUpdated() 0000000000066558 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWVMContext::clearPageTableUpdated() 0000000000066570 long 0e SECT 01 0000 [.text] __GLOBAL__I_a 00000000000665b0 long 0e SECT 01 0000 [.text] __GLOBAL__D_a 0000000000066602 long 0e SECT 01 0000 [.text] AMDSIVMM::MetaClass::~MetaClass() 00000000000669a0 long 0e SECT 01 0000 [.text] AMDSIVMM::MetaClass::~MetaClass() 00000000000669aa long 0e SECT 01 0000 [.text] AMDRadeonX4000_IAMDHWVMM::init() 00000000000669bc long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWVMM::getBaseAddress() 00000000000669c6 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWVMM::getVMPTVirtualAddress() 00000000000669d0 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWVMM::getVMPTVirtualAddress(unsigned long long) 0000000000066a08 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWVMM::getVMRangeStart() 0000000000066a12 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWVMM::getVMRangeEnd() 0000000000066a20 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWVMM::getVMPTBCoverage() 0000000000066a2e long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWVMM::getVMPTBVRAMSize() 0000000000066a3c long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWVMM::getVMPTDVRAMSize() 0000000000066a4a long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWVMM::getVMPTBTotal() 0000000000066a58 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWVMM::getVMPTBPerPTB() 0000000000066a66 long 0e SECT 01 0000 [.text] AMDSIVMM::getMinVMID() 0000000000066a72 long 0e SECT 01 0000 [.text] AMDSIVMM::getMaxVMID() 0000000000066a7e long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWVMM::getFragmentStrategy() 0000000000066a8a long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWVMM::getBIGKValue() 0000000000066a96 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWVMM::getBIGKInBytes() 0000000000066aa2 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWVMM::getFragmentAlignment() 0000000000066ab0 long 0e SECT 01 0000 [.text] __GLOBAL__I_a 0000000000066af0 long 0e SECT 01 0000 [.text] __GLOBAL__D_a 0000000000066b42 long 0e SECT 01 0000 [.text] AMDSIHardware::MetaClass::~MetaClass() 00000000000698d8 long 0e SECT 01 0000 [.text] AMDSIHardware::MetaClass::~MetaClass() 00000000000698e2 long 0e SECT 01 0000 [.text] AMDRadeonX4000_IAMDHWInterface::init() 00000000000698f4 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHardware::getHWMemoryDescriptor() 0000000000069902 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHardware::getChipEngine() 000000000006990e long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHardware::getConfigBits() 000000000006991a long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHardware::getHWCapabilities() 0000000000069924 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHardware::getAMDHwCailAdapterInfo() 0000000000069932 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHardware::getMaskSettings() 0000000000069940 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHardware::getChipID() 000000000006994c long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHardware::getChipRev() 0000000000069958 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHardware::getSubSystemID() 0000000000069964 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHardware::getFamily() 0000000000069970 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHardware::getPreDefinedNdrvVramReservedSpace() 000000000006997c long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHardware::setTLBInvalidateNeeded(unsigned int) 0000000000069992 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHardware::getDiagReportBuffer() 00000000000699ae long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHardware::getDiagReportBufferSize() 00000000000699ba long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHardware::isEnabled() 00000000000699c6 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHardware::isMultiEngineSyncEnabled() 00000000000699d2 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHardware::getCailHandle() 00000000000699e0 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHardware::getAMDHWHandler() 00000000000699ea long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHardware::getHWRegisters() 00000000000699f8 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHardware::getHWMemory() 0000000000069a06 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHardware::getHWGart() 0000000000069a14 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHardware::getHWVMM() 0000000000069a22 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHardware::getHWDisplay() 0000000000069a30 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHardware::getHWAlignManager() 0000000000069a3e long 0e SECT 01 0000 [.text] AMDSIHardware::getHWWorkarounds() 0000000000069a4c long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHardware::getAMDHWUtilities() 0000000000069a5a long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHardware::getHWEngine(_eAMD_HW_ENGINE_TYPE) 0000000000069a6a long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHardware::getChannelCount() 0000000000069a76 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHardware::getChannelWriteBackDescriptor() 0000000000069a84 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHardware::getChannelWriteBackFrameSize() 0000000000069a90 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHardware::getChannelWritePointerPollOffset(int) 0000000000069a98 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHardware::getChannelWritePointerPollAddr(int) 0000000000069aa0 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHardware::getHWSemaphorePool() 0000000000069aae long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHardware::getIOPCIDevice() 0000000000069ab8 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHardware::getSML() 0000000000069ac6 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHardware::getPM4CommandsUtility() 0000000000069ad4 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHardware::getGpuDebugPolicy() 0000000000069ae0 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHardware::getCailIri() const 0000000000069aee long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHardware::setPPLibIri(CAIL_IRI_REGISTRY_STRUCT*) 0000000000069b36 long 0e SECT 01 0000 [.text] AMDSIHardware::getGPUVMDefaultSettings() 0000000000069b42 long 0e SECT 01 0000 [.text] AMDSIHardware::getMEQCmdQueueSelIndex() 0000000000069b4e long 0e SECT 01 0000 [.text] AMDSIHardware::shallInitializeMC_VM_MD_L1_TLB3_CNTL() 0000000000069b56 long 0e SECT 01 0000 [.text] AMDSIHardware::allocatePM4Engine() 0000000000069b60 long 0e SECT 01 0000 [.text] __GLOBAL__I_a 0000000000069ba0 long 0e SECT 01 0000 [.text] __GLOBAL__D_a 0000000000069bf2 long 0e SECT 01 0000 [.text] AMDTahitiHardware::MetaClass::~MetaClass() 0000000000069ed2 long 0e SECT 01 0000 [.text] AMDRadeonX4000_IAMDHWInterface::init() 0000000000069ee4 long 0e SECT 01 0000 [.text] AMDTahitiHardware::free() 0000000000069ef6 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHardware::getHWMemoryDescriptor() 0000000000069f04 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHardware::getChipEngine() 0000000000069f10 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHardware::getConfigBits() 0000000000069f1c long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHardware::getHWCapabilities() 0000000000069f26 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHardware::getAMDHwCailAdapterInfo() 0000000000069f34 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHardware::getMaskSettings() 0000000000069f42 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHardware::getChipID() 0000000000069f4e long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHardware::getChipRev() 0000000000069f5a long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHardware::getSubSystemID() 0000000000069f66 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHardware::getFamily() 0000000000069f72 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHardware::getPreDefinedNdrvVramReservedSpace() 0000000000069f7e long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHardware::setTLBInvalidateNeeded(unsigned int) 0000000000069f94 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHardware::getDiagReportBuffer() 0000000000069fb0 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHardware::getDiagReportBufferSize() 0000000000069fbc long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHardware::isEnabled() 0000000000069fc8 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHardware::isMultiEngineSyncEnabled() 0000000000069fd4 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHardware::getCailHandle() 0000000000069fe2 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHardware::getAMDHWHandler() 0000000000069fec long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHardware::getHWRegisters() 0000000000069ffa long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHardware::getHWMemory() 000000000006a008 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHardware::getHWGart() 000000000006a016 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHardware::getHWVMM() 000000000006a024 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHardware::getHWDisplay() 000000000006a032 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHardware::getHWAlignManager() 000000000006a040 long 0e SECT 01 0000 [.text] AMDSIHardware::getHWWorkarounds() 000000000006a04e long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHardware::getAMDHWUtilities() 000000000006a05c long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHardware::getHWEngine(_eAMD_HW_ENGINE_TYPE) 000000000006a06c long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHardware::getChannelCount() 000000000006a078 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHardware::getChannelWriteBackDescriptor() 000000000006a086 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHardware::getChannelWriteBackFrameSize() 000000000006a092 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHardware::getChannelWritePointerPollOffset(int) 000000000006a09a long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHardware::getChannelWritePointerPollAddr(int) 000000000006a0a2 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHardware::getHWSemaphorePool() 000000000006a0b0 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHardware::getIOPCIDevice() 000000000006a0ba long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHardware::getSML() 000000000006a0c8 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHardware::getPM4CommandsUtility() 000000000006a0d6 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHardware::getGpuDebugPolicy() 000000000006a0e2 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHardware::getCailIri() const 000000000006a0f0 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHardware::setPPLibIri(CAIL_IRI_REGISTRY_STRUCT*) 000000000006a138 long 0e SECT 01 0000 [.text] AMDSIHardware::getGPUVMDefaultSettings() 000000000006a144 long 0e SECT 01 0000 [.text] AMDSIHardware::getMEQCmdQueueSelIndex() 000000000006a150 long 0e SECT 01 0000 [.text] AMDSIHardware::shallInitializeMC_VM_MD_L1_TLB3_CNTL() 000000000006a158 long 0e SECT 01 0000 [.text] AMDTahitiHardware::MetaClass::~MetaClass() 000000000006a170 long 0e SECT 01 0000 [.text] __GLOBAL__I_a 000000000006a1b0 long 0e SECT 01 0000 [.text] __GLOBAL__D_a 000000000006a202 long 0e SECT 01 0000 [.text] AMDPitcairnHardware::MetaClass::~MetaClass() 000000000006a4e6 long 0e SECT 01 0000 [.text] AMDRadeonX4000_IAMDHWInterface::init() 000000000006a4f8 long 0e SECT 01 0000 [.text] AMDPitcairnHardware::free() 000000000006a50a long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHardware::getHWMemoryDescriptor() 000000000006a518 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHardware::getChipEngine() 000000000006a524 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHardware::getConfigBits() 000000000006a530 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHardware::getHWCapabilities() 000000000006a53a long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHardware::getAMDHwCailAdapterInfo() 000000000006a548 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHardware::getMaskSettings() 000000000006a556 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHardware::getChipID() 000000000006a562 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHardware::getChipRev() 000000000006a56e long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHardware::getSubSystemID() 000000000006a57a long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHardware::getFamily() 000000000006a586 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHardware::getPreDefinedNdrvVramReservedSpace() 000000000006a592 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHardware::setTLBInvalidateNeeded(unsigned int) 000000000006a5a8 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHardware::getDiagReportBuffer() 000000000006a5c4 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHardware::getDiagReportBufferSize() 000000000006a5d0 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHardware::isEnabled() 000000000006a5dc long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHardware::isMultiEngineSyncEnabled() 000000000006a5e8 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHardware::getCailHandle() 000000000006a5f6 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHardware::getAMDHWHandler() 000000000006a600 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHardware::getHWRegisters() 000000000006a60e long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHardware::getHWMemory() 000000000006a61c long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHardware::getHWGart() 000000000006a62a long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHardware::getHWVMM() 000000000006a638 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHardware::getHWDisplay() 000000000006a646 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHardware::getHWAlignManager() 000000000006a654 long 0e SECT 01 0000 [.text] AMDSIHardware::getHWWorkarounds() 000000000006a662 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHardware::getAMDHWUtilities() 000000000006a670 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHardware::getHWEngine(_eAMD_HW_ENGINE_TYPE) 000000000006a680 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHardware::getChannelCount() 000000000006a68c long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHardware::getChannelWriteBackDescriptor() 000000000006a69a long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHardware::getChannelWriteBackFrameSize() 000000000006a6a6 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHardware::getChannelWritePointerPollOffset(int) 000000000006a6ae long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHardware::getChannelWritePointerPollAddr(int) 000000000006a6b6 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHardware::getHWSemaphorePool() 000000000006a6c4 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHardware::getIOPCIDevice() 000000000006a6ce long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHardware::getSML() 000000000006a6dc long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHardware::getPM4CommandsUtility() 000000000006a6ea long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHardware::getGpuDebugPolicy() 000000000006a6f6 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHardware::getCailIri() const 000000000006a704 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHardware::setPPLibIri(CAIL_IRI_REGISTRY_STRUCT*) 000000000006a74c long 0e SECT 01 0000 [.text] AMDSIHardware::getGPUVMDefaultSettings() 000000000006a758 long 0e SECT 01 0000 [.text] AMDSIHardware::getMEQCmdQueueSelIndex() 000000000006a764 long 0e SECT 01 0000 [.text] AMDSIHardware::shallInitializeMC_VM_MD_L1_TLB3_CNTL() 000000000006a76c long 0e SECT 01 0000 [.text] AMDPitcairnHardware::MetaClass::~MetaClass() 000000000006a780 long 0e SECT 01 0000 [.text] __GLOBAL__I_a 000000000006a7c0 long 0e SECT 01 0000 [.text] __GLOBAL__D_a 000000000006a812 long 0e SECT 01 0000 [.text] AMDVerdeHardware::MetaClass::~MetaClass() 000000000006aaf6 long 0e SECT 01 0000 [.text] AMDRadeonX4000_IAMDHWInterface::init() 000000000006ab08 long 0e SECT 01 0000 [.text] AMDVerdeHardware::free() 000000000006ab1a long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHardware::getHWMemoryDescriptor() 000000000006ab28 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHardware::getChipEngine() 000000000006ab34 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHardware::getConfigBits() 000000000006ab40 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHardware::getHWCapabilities() 000000000006ab4a long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHardware::getAMDHwCailAdapterInfo() 000000000006ab58 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHardware::getMaskSettings() 000000000006ab66 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHardware::getChipID() 000000000006ab72 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHardware::getChipRev() 000000000006ab7e long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHardware::getSubSystemID() 000000000006ab8a long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHardware::getFamily() 000000000006ab96 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHardware::getPreDefinedNdrvVramReservedSpace() 000000000006aba2 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHardware::setTLBInvalidateNeeded(unsigned int) 000000000006abb8 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHardware::getDiagReportBuffer() 000000000006abd4 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHardware::getDiagReportBufferSize() 000000000006abe0 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHardware::isEnabled() 000000000006abec long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHardware::isMultiEngineSyncEnabled() 000000000006abf8 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHardware::getCailHandle() 000000000006ac06 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHardware::getAMDHWHandler() 000000000006ac10 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHardware::getHWRegisters() 000000000006ac1e long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHardware::getHWMemory() 000000000006ac2c long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHardware::getHWGart() 000000000006ac3a long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHardware::getHWVMM() 000000000006ac48 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHardware::getHWDisplay() 000000000006ac56 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHardware::getHWAlignManager() 000000000006ac64 long 0e SECT 01 0000 [.text] AMDSIHardware::getHWWorkarounds() 000000000006ac72 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHardware::getAMDHWUtilities() 000000000006ac80 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHardware::getHWEngine(_eAMD_HW_ENGINE_TYPE) 000000000006ac90 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHardware::getChannelCount() 000000000006ac9c long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHardware::getChannelWriteBackDescriptor() 000000000006acaa long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHardware::getChannelWriteBackFrameSize() 000000000006acb6 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHardware::getChannelWritePointerPollOffset(int) 000000000006acbe long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHardware::getChannelWritePointerPollAddr(int) 000000000006acc6 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHardware::getHWSemaphorePool() 000000000006acd4 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHardware::getIOPCIDevice() 000000000006acde long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHardware::getSML() 000000000006acec long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHardware::getPM4CommandsUtility() 000000000006acfa long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHardware::getGpuDebugPolicy() 000000000006ad06 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHardware::getCailIri() const 000000000006ad14 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHardware::setPPLibIri(CAIL_IRI_REGISTRY_STRUCT*) 000000000006ad5c long 0e SECT 01 0000 [.text] AMDSIHardware::getGPUVMDefaultSettings() 000000000006ad68 long 0e SECT 01 0000 [.text] AMDSIHardware::getMEQCmdQueueSelIndex() 000000000006ad74 long 0e SECT 01 0000 [.text] AMDSIHardware::shallInitializeMC_VM_MD_L1_TLB3_CNTL() 000000000006ad7c long 0e SECT 01 0000 [.text] AMDVerdeHardware::MetaClass::~MetaClass() 000000000006ad90 long 0e SECT 01 0000 [.text] __GLOBAL__I_a 000000000006add0 long 0e SECT 01 0000 [.text] __GLOBAL__D_a 000000000006ae22 long 0e SECT 01 0000 [.text] AMDSIHWAlignManager::MetaClass::~MetaClass() 000000000006b00c long 0e SECT 01 0000 [.text] AMDSIHWAlignManager::MetaClass::~MetaClass() 000000000006b016 long 0e SECT 01 0000 [.text] AMDRadeonX4000_IAMDHWAlignManager::init() 000000000006b028 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWAlignManager::getHandle() 000000000006b032 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWAlignManager::getAddrTileMode(unsigned int) 000000000006b03a long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWAlignManager::getArrayMode(_AddrTileMode) 000000000006b042 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWAlignManager::getTileType(unsigned int) 000000000006b04a long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWAlignManager::getMicroTileMode(_AddrTileType) 000000000006b052 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWAlignManager::getLinearAlignedTileIndex() 000000000006b05c long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWAlignManager::getLinearGeneralTileIndex() 000000000006b070 long 0e SECT 01 0000 [.text] __GLOBAL__I_a 000000000006b0b0 long 0e SECT 01 0000 [.text] __GLOBAL__D_a 000000000006b102 long 0e SECT 01 0000 [.text] AMDSIPM4Engine::MetaClass::~MetaClass() 000000000006b9a8 long 0e SECT 01 0000 [.text] AMDSIPM4Engine::MetaClass::~MetaClass() 000000000006b9b2 long 0e SECT 01 0000 [.text] AMDRadeonX4000_IAMDHWEngine::init() 000000000006b9c4 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWEngine::type() 000000000006b9ce long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWEngine::isEnabled() 000000000006b9d8 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWEngine::setVirtualSpaceReady(bool) 000000000006b9de long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDPM4HWEngine::setMemoryAllocationsEnabled(bool) 000000000006b9e4 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDPM4HWEngine::initializeRegisters() 000000000006ba14 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDPM4HWEngine::systemDidChangeSpeedEvent() 000000000006ba1a long 0e SECT 01 0000 [.text] AMDSIPM4Engine::alignCommandBufferAddress(unsigned int) 000000000006ba22 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWEngine::getVersion(unsigned int) 000000000006ba32 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWEngine::getChannelCount() 000000000006ba3c long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWEngine::getTimestampIRQSourcex(_eAMD_HW_RING_TYPE) 000000000006ba44 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWEngine::getFwvFunction() 000000000006ba4c long 0e SECT 01 0000 [.text] AMDSIPM4Engine::dumpEngineHangState(bool) 000000000006ba70 long 0e SECT 01 0000 [.text] __GLOBAL__I_a 000000000006bab0 long 0e SECT 01 0000 [.text] __GLOBAL__D_a 000000000006bb02 long 0e SECT 01 0000 [.text] AMDTahitiPM4Engine::MetaClass::~MetaClass() 000000000006bd0c long 0e SECT 01 0000 [.text] AMDTahitiPM4Engine::MetaClass::~MetaClass() 000000000006bd16 long 0e SECT 01 0000 [.text] AMDRadeonX4000_IAMDHWEngine::init() 000000000006bd28 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWEngine::type() 000000000006bd32 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWEngine::isEnabled() 000000000006bd3c long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWEngine::setVirtualSpaceReady(bool) 000000000006bd42 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDPM4HWEngine::setMemoryAllocationsEnabled(bool) 000000000006bd48 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDPM4HWEngine::initializeRegisters() 000000000006bd78 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDPM4HWEngine::systemDidChangeSpeedEvent() 000000000006bd7e long 0e SECT 01 0000 [.text] AMDSIPM4Engine::alignCommandBufferAddress(unsigned int) 000000000006bd86 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWEngine::getVersion(unsigned int) 000000000006bd96 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWEngine::getChannelCount() 000000000006bda0 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWEngine::getTimestampIRQSourcex(_eAMD_HW_RING_TYPE) 000000000006bda8 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWEngine::getFwvFunction() 000000000006bdb0 long 0e SECT 01 0000 [.text] AMDSIPM4Engine::dumpEngineHangState(bool) 000000000006bdd0 long 0e SECT 01 0000 [.text] __GLOBAL__I_a 000000000006be10 long 0e SECT 01 0000 [.text] __GLOBAL__D_a 000000000006be62 long 0e SECT 01 0000 [.text] AMDPitcairnPM4Engine::MetaClass::~MetaClass() 000000000006c06c long 0e SECT 01 0000 [.text] AMDPitcairnPM4Engine::MetaClass::~MetaClass() 000000000006c076 long 0e SECT 01 0000 [.text] AMDRadeonX4000_IAMDHWEngine::init() 000000000006c088 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWEngine::type() 000000000006c092 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWEngine::isEnabled() 000000000006c09c long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWEngine::setVirtualSpaceReady(bool) 000000000006c0a2 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDPM4HWEngine::setMemoryAllocationsEnabled(bool) 000000000006c0a8 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDPM4HWEngine::initializeRegisters() 000000000006c0d8 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDPM4HWEngine::systemDidChangeSpeedEvent() 000000000006c0de long 0e SECT 01 0000 [.text] AMDSIPM4Engine::alignCommandBufferAddress(unsigned int) 000000000006c0e6 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWEngine::getVersion(unsigned int) 000000000006c0f6 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWEngine::getChannelCount() 000000000006c100 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWEngine::getTimestampIRQSourcex(_eAMD_HW_RING_TYPE) 000000000006c108 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWEngine::getFwvFunction() 000000000006c110 long 0e SECT 01 0000 [.text] AMDSIPM4Engine::dumpEngineHangState(bool) 000000000006c130 long 0e SECT 01 0000 [.text] __GLOBAL__I_a 000000000006c170 long 0e SECT 01 0000 [.text] __GLOBAL__D_a 000000000006c1c2 long 0e SECT 01 0000 [.text] AMDVerdePM4Engine::MetaClass::~MetaClass() 000000000006c3cc long 0e SECT 01 0000 [.text] AMDVerdePM4Engine::MetaClass::~MetaClass() 000000000006c3d6 long 0e SECT 01 0000 [.text] AMDRadeonX4000_IAMDHWEngine::init() 000000000006c3e8 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWEngine::type() 000000000006c3f2 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWEngine::isEnabled() 000000000006c3fc long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWEngine::setVirtualSpaceReady(bool) 000000000006c402 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDPM4HWEngine::setMemoryAllocationsEnabled(bool) 000000000006c408 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDPM4HWEngine::initializeRegisters() 000000000006c438 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDPM4HWEngine::systemDidChangeSpeedEvent() 000000000006c43e long 0e SECT 01 0000 [.text] AMDSIPM4Engine::alignCommandBufferAddress(unsigned int) 000000000006c446 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWEngine::getVersion(unsigned int) 000000000006c456 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWEngine::getChannelCount() 000000000006c460 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWEngine::getTimestampIRQSourcex(_eAMD_HW_RING_TYPE) 000000000006c468 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWEngine::getFwvFunction() 000000000006c470 long 0e SECT 01 0000 [.text] AMDSIPM4Engine::dumpEngineHangState(bool) 000000000006c490 long 0e SECT 01 0000 [.text] __GLOBAL__I_a 000000000006c4d0 long 0e SECT 01 0000 [.text] __GLOBAL__D_a 000000000006c522 long 0e SECT 01 0000 [.text] AMDSIPM4Channel::MetaClass::~MetaClass() 000000000006cdbe long 0e SECT 01 0000 [.text] AMDSIPM4Channel::MetaClass::~MetaClass() 000000000006cdc8 long 0e SECT 01 0000 [.text] AMDRadeonX4000_IAMDHWChannel::init() 000000000006cdda long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWChannel::getChannelIndex() 000000000006cde4 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWChannel::getChannelRingType() 000000000006ce00 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWChannel::initializeSubmitCommandBufferInfo(AMD_SUBMIT_COMMAND_BUFFER_INFO*) 000000000006ce16 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWChannel::alignCommandBufferAddress(unsigned int) 000000000006ce2c long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWChannel::getName() 000000000006ce36 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWChannel::dumpEngineHangState(bool) 000000000006ce50 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWChannel::engineType() 000000000006ce62 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWChannel::isDebugFlagEnabled(unsigned int) 000000000006ce76 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWChannel::getTimestampInterruptRef() 000000000006ce80 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWChannel::getHWStatisticsGroupTable() 000000000006ce8e long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWChannel::clearInterrupEnableFlag() 000000000006ce98 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWChannel::getIndirectCommandSize() 000000000006ceb0 long 0e SECT 01 0000 [.text] __GLOBAL__I_a 000000000006cef0 long 0e SECT 01 0000 [.text] __GLOBAL__D_a 000000000006cf42 long 0e SECT 01 0000 [.text] AMDSICommandsRing::MetaClass::~MetaClass() 000000000006d420 long 0e SECT 01 0000 [.text] AMDSICommandsRing::MetaClass::~MetaClass() 000000000006d42a long 0e SECT 01 0000 [.text] AMDRadeonX4000_IAMDHWRing::init() 000000000006d43c long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWRing::isEnabled() 000000000006d446 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWRing::getHead() 000000000006d456 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWRing::getTail() 000000000006d462 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWRing::getFreeSpace() 000000000006d492 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWRing::isEmpty() 000000000006d4c0 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWRing::getRingGartAddr() 000000000006d4ca long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWRing::getSize() 000000000006d4d4 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWRing::getRingBlock(unsigned int) 000000000006d4e6 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWRing::commitBlock(unsigned int) 000000000006d4f6 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWRing::getRingId() 000000000006d510 long 0e SECT 01 0000 [.text] __GLOBAL__I_a 000000000006d550 long 0e SECT 01 0000 [.text] __GLOBAL__D_a 000000000006d5a2 long 0e SECT 01 0000 [.text] AMDSIDMAEngine::MetaClass::~MetaClass() 000000000006d96a long 0e SECT 01 0000 [.text] AMDSIDMAEngine::MetaClass::~MetaClass() 000000000006d974 long 0e SECT 01 0000 [.text] AMDRadeonX4000_IAMDHWEngine::init() 000000000006d986 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWEngine::type() 000000000006d990 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWEngine::isEnabled() 000000000006d99a long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWEngine::setVirtualSpaceReady(bool) 000000000006d9a0 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDDMAHWEngine::setMemoryAllocationsEnabled(bool) 000000000006d9a6 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDDMAHWEngine::initializeRegisters() 000000000006d9ac long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDDMAHWEngine::systemWillChangeSpeedEvent() 000000000006d9b2 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDDMAHWEngine::systemDidChangeSpeedEvent() 000000000006d9b8 long 0e SECT 01 0000 [.text] AMDSIDMAEngine::alignCommandBufferAddress(unsigned int) 000000000006d9ca long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWEngine::getVersion(unsigned int) 000000000006d9da long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWEngine::getChannelCount() 000000000006d9e4 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWEngine::getTimestampIRQSourcex(_eAMD_HW_RING_TYPE) 000000000006d9ec long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWEngine::getFwvFunction() 000000000006da00 long 0e SECT 01 0000 [.text] __GLOBAL__I_a 000000000006da40 long 0e SECT 01 0000 [.text] __GLOBAL__D_a 000000000006da92 long 0e SECT 01 0000 [.text] AMDSIDMAChannel::MetaClass::~MetaClass() 000000000006e98a long 0e SECT 01 0000 [.text] AMDSIDMAChannel::MetaClass::~MetaClass() 000000000006e994 long 0e SECT 01 0000 [.text] AMDRadeonX4000_IAMDHWChannel::init() 000000000006e9a6 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWChannel::getChannelIndex() 000000000006e9b0 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWChannel::getChannelRingType() 000000000006e9cc long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWChannel::initializeSubmitCommandBufferInfo(AMD_SUBMIT_COMMAND_BUFFER_INFO*) 000000000006e9e2 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWChannel::alignCommandBufferAddress(unsigned int) 000000000006e9f8 long 0e SECT 01 0000 [.text] AMDSIDMAChannel::getIBAlignmentFactor() 000000000006ea04 long 0e SECT 01 0000 [.text] AMDSIDMAChannel::getOneDwordNOPCommand() 000000000006ea10 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWChannel::getName() 000000000006ea1a long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWChannel::dumpEngineHangState(bool) 000000000006ea34 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWChannel::engineType() 000000000006ea46 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWChannel::isDebugFlagEnabled(unsigned int) 000000000006ea5a long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWChannel::getTimestampInterruptRef() 000000000006ea64 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWChannel::getHWStatisticsGroupTable() 000000000006ea72 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWChannel::clearInterrupEnableFlag() 000000000006ea7c long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWChannel::getIndirectCommandSize() 000000000006ea88 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDDMAHWChannel::getDmaPktInfo(AMD_DMA_COMMAND_TYPE) const 000000000006eaa0 long 0e SECT 01 0000 [.text] __GLOBAL__I_a 000000000006eae0 long 0e SECT 01 0000 [.text] __GLOBAL__D_a 000000000006eb32 long 0e SECT 01 0000 [.text] AMDSIDMARing::MetaClass::~MetaClass() 000000000006f23c long 0e SECT 01 0000 [.text] AMDSIDMARing::MetaClass::~MetaClass() 000000000006f246 long 0e SECT 01 0000 [.text] AMDRadeonX4000_IAMDHWRing::init() 000000000006f258 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWRing::isEnabled() 000000000006f262 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWRing::getTail() 000000000006f26e long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWRing::getFreeSpace() 000000000006f29e long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWRing::isEmpty() 000000000006f2cc long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWRing::getRingGartAddr() 000000000006f2d6 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWRing::getSize() 000000000006f2e0 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWRing::getRingBlock(unsigned int) 000000000006f2f2 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWRing::commitBlock(unsigned int) 000000000006f302 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWRing::getRingId() 000000000006f30e long 0e SECT 01 0000 [.text] AMDSIDMARing::enableReadPointerWriteBack() 000000000006f314 long 0e SECT 01 0000 [.text] AMDSIDMARing::disableReadPointerWriteBack() 000000000006f320 long 0e SECT 01 0000 [.text] __GLOBAL__I_a 000000000006f360 long 0e SECT 01 0000 [.text] __GLOBAL__D_a 000000000006f3b2 long 0e SECT 01 0000 [.text] AMDSIVCEHWEngine::MetaClass::~MetaClass() 000000000006fa5a long 0e SECT 01 0000 [.text] AMDSIVCEHWEngine::MetaClass::~MetaClass() 000000000006fa64 long 0e SECT 01 0000 [.text] AMDRadeonX4000_IAMDHWEngine::init() 000000000006fa76 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWEngine::type() 000000000006fa80 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWEngine::isEnabled() 000000000006fa8a long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWEngine::setVirtualSpaceReady(bool) 000000000006fa90 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDVCEHWEngine::initializeRegisters() 000000000006fa96 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDVCEHWEngine::systemWillChangeSpeedEvent() 000000000006fa9c long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDVCEHWEngine::systemDidChangeSpeedEvent() 000000000006faa2 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDVCEHWEngine::alignCommandBufferAddress(unsigned int) 000000000006faae long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWEngine::getVersion(unsigned int) 000000000006fabe long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWEngine::getChannelCount() 000000000006fac8 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWEngine::getTimestampIRQSourcex(_eAMD_HW_RING_TYPE) 000000000006fad0 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWEngine::getFwvFunction() 000000000006fad8 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDVCEHWEngine::getTotalCapability() 000000000006faec long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDVCEHWEngine::getCurrentCapability() 000000000006fb00 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDVCEHWEngine::getVCEVClk() 000000000006fb0c long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDVCEHWEngine::getVCECClk() 000000000006fb20 long 0e SECT 01 0000 [.text] __GLOBAL__I_a 000000000006fb60 long 0e SECT 01 0000 [.text] __GLOBAL__D_a 000000000006fbb2 long 0e SECT 01 0000 [.text] AMDSIVCEChannel::MetaClass::~MetaClass() 000000000006fed8 long 0e SECT 01 0000 [.text] AMDSIVCEChannel::MetaClass::~MetaClass() 000000000006fee2 long 0e SECT 01 0000 [.text] AMDRadeonX4000_IAMDHWChannel::init() 000000000006fef4 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWChannel::getChannelIndex() 000000000006fefe long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWChannel::getChannelRingType() 000000000006ff1a long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWChannel::initializeSubmitCommandBufferInfo(AMD_SUBMIT_COMMAND_BUFFER_INFO*) 000000000006ff30 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWChannel::alignCommandBufferAddress(unsigned int) 000000000006ff46 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDVCEHWChannel::getIBAlignmentFactor() 000000000006ff52 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDVCEHWChannel::getOneDwordNOPCommand() 000000000006ff5a long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWChannel::getName() 000000000006ff64 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWChannel::dumpEngineHangState(bool) 000000000006ff7e long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWChannel::writeProfilingCommand(unsigned int*, unsigned long long, unsigned int, bool) 000000000006ff86 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWChannel::engineType() 000000000006ff98 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWChannel::isDebugFlagEnabled(unsigned int) 000000000006ffac long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWChannel::getTimestampInterruptRef() 000000000006ffb6 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWChannel::getHWStatisticsGroupTable() 000000000006ffc4 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWChannel::clearInterrupEnableFlag() 000000000006ffd0 long 0e SECT 01 0000 [.text] __GLOBAL__I_a 0000000000070010 long 0e SECT 01 0000 [.text] __GLOBAL__D_a 0000000000070062 long 0e SECT 01 0000 [.text] AMDSIVCELLQChannel::MetaClass::~MetaClass() 00000000000701f2 long 0e SECT 01 0000 [.text] AMDSIVCELLQChannel::MetaClass::~MetaClass() 00000000000701fc long 0e SECT 01 0000 [.text] AMDRadeonX4000_IAMDHWChannel::init() 000000000007020e long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWChannel::getChannelIndex() 0000000000070218 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWChannel::getChannelRingType() 0000000000070234 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWChannel::initializeSubmitCommandBufferInfo(AMD_SUBMIT_COMMAND_BUFFER_INFO*) 000000000007024a long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWChannel::alignCommandBufferAddress(unsigned int) 0000000000070260 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDVCEHWChannel::getIBAlignmentFactor() 000000000007026c long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDVCEHWChannel::getOneDwordNOPCommand() 0000000000070274 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWChannel::getName() 000000000007027e long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWChannel::dumpEngineHangState(bool) 0000000000070298 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWChannel::writeProfilingCommand(unsigned int*, unsigned long long, unsigned int, bool) 00000000000702a0 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWChannel::engineType() 00000000000702b2 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWChannel::isDebugFlagEnabled(unsigned int) 00000000000702c6 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWChannel::getTimestampInterruptRef() 00000000000702d0 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWChannel::getHWStatisticsGroupTable() 00000000000702de long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWChannel::clearInterrupEnableFlag() 00000000000702f0 long 0e SECT 01 0000 [.text] __GLOBAL__I_a 0000000000070330 long 0e SECT 01 0000 [.text] __GLOBAL__D_a 0000000000070382 long 0e SECT 01 0000 [.text] AMDSIVCERing::MetaClass::~MetaClass() 00000000000707ac long 0e SECT 01 0000 [.text] AMDSIVCERing::MetaClass::~MetaClass() 00000000000707b6 long 0e SECT 01 0000 [.text] AMDRadeonX4000_IAMDHWRing::init() 00000000000707c8 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWRing::isEnabled() 00000000000707d2 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWRing::getTail() 00000000000707de long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWRing::getFreeSpace() 000000000007080e long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWRing::isEmpty() 000000000007083c long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWRing::getRingGartAddr() 0000000000070846 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWRing::getSize() 0000000000070850 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWRing::getRingBlock(unsigned int) 0000000000070862 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWRing::commitBlock(unsigned int) 0000000000070872 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWRing::getRingId() 0000000000070880 long 0e SECT 01 0000 [.text] __GLOBAL__I_a 00000000000708c0 long 0e SECT 01 0000 [.text] __GLOBAL__D_a 0000000000070912 long 0e SECT 01 0000 [.text] AMDSIVCELLQRing::MetaClass::~MetaClass() 0000000000070b9a long 0e SECT 01 0000 [.text] AMDSIVCELLQRing::MetaClass::~MetaClass() 0000000000070ba4 long 0e SECT 01 0000 [.text] AMDRadeonX4000_IAMDHWRing::init() 0000000000070bb6 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWRing::isEnabled() 0000000000070bc0 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWRing::getTail() 0000000000070bcc long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWRing::getFreeSpace() 0000000000070bfc long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWRing::isEmpty() 0000000000070c2a long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWRing::getRingGartAddr() 0000000000070c34 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWRing::getSize() 0000000000070c3e long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWRing::getRingBlock(unsigned int) 0000000000070c50 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWRing::commitBlock(unsigned int) 0000000000070c60 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWRing::getRingId() 0000000000070c70 long 0e SECT 01 0000 [.text] __GLOBAL__I_a 0000000000070cb0 long 0e SECT 01 0000 [.text] __GLOBAL__D_a 0000000000070d02 long 0e SECT 01 0000 [.text] AMDSIUVDChannel::MetaClass::~MetaClass() 0000000000071222 long 0e SECT 01 0000 [.text] AMDSIUVDChannel::MetaClass::~MetaClass() 000000000007122c long 0e SECT 01 0000 [.text] AMDRadeonX4000_IAMDHWChannel::init() 000000000007123e long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWChannel::getChannelIndex() 0000000000071248 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWChannel::getChannelRingType() 0000000000071264 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWChannel::initializeSubmitCommandBufferInfo(AMD_SUBMIT_COMMAND_BUFFER_INFO*) 000000000007127a long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWChannel::alignCommandBufferAddress(unsigned int) 0000000000071290 long 0e SECT 01 0000 [.text] AMDSIUVDChannel::getIBAlignmentFactor() 000000000007129c long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWChannel::getName() 00000000000712a6 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWChannel::dumpEngineHangState(bool) 00000000000712c0 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWChannel::writeProfilingCommand(unsigned int*, unsigned long long, unsigned int, bool) 00000000000712c8 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWChannel::engineType() 00000000000712da long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWChannel::isDebugFlagEnabled(unsigned int) 00000000000712ee long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWChannel::getTimestampInterruptRef() 00000000000712f8 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWChannel::getHWStatisticsGroupTable() 0000000000071306 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWChannel::clearInterrupEnableFlag() 0000000000071310 long 0e SECT 01 0000 [.text] AMDSIUVDChannel::getIndirectCommandSize() 0000000000071320 long 0e SECT 01 0000 [.text] __GLOBAL__I_a 0000000000071360 long 0e SECT 01 0000 [.text] __GLOBAL__D_a 00000000000713b2 long 0e SECT 01 0000 [.text] AMDSIUVDHWEngine::MetaClass::~MetaClass() 0000000000071a3c long 0e SECT 01 0000 [.text] AMDRadeonX4000_IAMDHWEngine::init() 0000000000071a4e long 0e SECT 01 0000 [.text] AMDSIUVDHWEngine::free() 0000000000071a60 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWEngine::type() 0000000000071a6a long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDUVDHWEngine::initializeRegisters() 0000000000071a70 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDUVDHWEngine::systemWillChangeSpeedEvent() 0000000000071a76 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDUVDHWEngine::systemDidChangeSpeedEvent() 0000000000071a7c long 0e SECT 01 0000 [.text] AMDSIUVDHWEngine::alignCommandBufferAddress(unsigned int) 0000000000071a88 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWEngine::getVersion(unsigned int) 0000000000071a98 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWEngine::getChannelCount() 0000000000071aa2 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWEngine::getTimestampIRQSourcex(_eAMD_HW_RING_TYPE) 0000000000071aaa long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDUVDHWEngine::getFirmwareAddress() 0000000000071ab8 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDUVDHWEngine::getTotalCapability() 0000000000071acc long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDUVDHWEngine::getCurrentCapability() 0000000000071ae0 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDUVDHWEngine::getUVDVclk() 0000000000071aec long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDUVDHWEngine::getUVDDclk() 0000000000071af8 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDUVDHWEngine::getHWRegisters() 0000000000071b02 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDUVDHWEngine::getKeySelect() 0000000000071b0e long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDUVDHWEngine::setDpmSupported(bool) 0000000000071b1c long 0e SECT 01 0000 [.text] AMDSIUVDHWEngine::MetaClass::~MetaClass() 0000000000071b30 long 0e SECT 01 0000 [.text] __GLOBAL__I_a 0000000000071b70 long 0e SECT 01 0000 [.text] __GLOBAL__D_a 0000000000071bc2 long 0e SECT 01 0000 [.text] AMDSIUVDRing::MetaClass::~MetaClass() 0000000000072046 long 0e SECT 01 0000 [.text] AMDSIUVDRing::MetaClass::~MetaClass() 0000000000072050 long 0e SECT 01 0000 [.text] AMDRadeonX4000_IAMDHWRing::init() 0000000000072062 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWRing::isEnabled() 000000000007206c long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWRing::getTail() 0000000000072078 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWRing::getFreeSpace() 00000000000720a8 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWRing::isEmpty() 00000000000720d6 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWRing::getRingGartAddr() 00000000000720e0 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWRing::getSize() 00000000000720ea long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWRing::getRingBlock(unsigned int) 00000000000720fc long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWRing::commitBlock(unsigned int) 000000000007210c long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWRing::getRingId() 0000000000072120 long 0e SECT 01 0000 [.text] __GLOBAL__I_a 0000000000072160 long 0e SECT 01 0000 [.text] __GLOBAL__D_a 00000000000721b2 long 0e SECT 01 0000 [.text] AMDSISPUEngine::MetaClass::~MetaClass() 0000000000072da4 long 0e SECT 01 0000 [.text] AMDSISPUEngine::MetaClass::~MetaClass() 0000000000072dae long 0e SECT 01 0000 [.text] AMDRadeonX4000_IAMDHWEngine::init() 0000000000072dc0 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWEngine::type() 0000000000072dca long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWEngine::isEnabled() 0000000000072dd4 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWEngine::setVirtualSpaceReady(bool) 0000000000072dda long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDSPUHWEngine::initializeRegisters() 0000000000072de0 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDSPUHWEngine::systemWillChangeSpeedEvent() 0000000000072de6 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDSPUHWEngine::systemDidChangeSpeedEvent() 0000000000072dec long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDSPUHWEngine::alignCommandBufferAddress(unsigned int) 0000000000072dfe long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWEngine::getVersion(unsigned int) 0000000000072e0e long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWEngine::getChannelCount() 0000000000072e18 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWEngine::getTimestampIRQSourcex(_eAMD_HW_RING_TYPE) 0000000000072e20 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWEngine::getFwvFunction() 0000000000072e30 long 0e SECT 01 0000 [.text] __GLOBAL__I_a 0000000000072e70 long 0e SECT 01 0000 [.text] __GLOBAL__D_a 0000000000072ec2 long 0e SECT 01 0000 [.text] AMDSISPUChannel::MetaClass::~MetaClass() 000000000007311a long 0e SECT 01 0000 [.text] AMDSISPUChannel::MetaClass::~MetaClass() 0000000000073124 long 0e SECT 01 0000 [.text] AMDRadeonX4000_IAMDHWChannel::init() 0000000000073136 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWChannel::getChannelIndex() 0000000000073140 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWChannel::getChannelRingType() 000000000007315c long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWChannel::initializeSubmitCommandBufferInfo(AMD_SUBMIT_COMMAND_BUFFER_INFO*) 0000000000073172 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWChannel::alignCommandBufferAddress(unsigned int) 0000000000073188 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDSPUHWChannel::getIBAlignmentFactor() 0000000000073194 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDSPUHWChannel::getOneDwordNOPCommand() 00000000000731a0 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWChannel::writeSemaphoreCommand(unsigned int*, unsigned long long, bool) const 00000000000731a8 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWChannel::getName() 00000000000731b2 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWChannel::dumpEngineHangState(bool) 00000000000731cc long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWChannel::writeProfilingCommand(unsigned int*, unsigned long long, unsigned int, bool) 00000000000731d4 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWChannel::engineType() 00000000000731e6 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWChannel::isDebugFlagEnabled(unsigned int) 00000000000731fa long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWChannel::getTimestampInterruptRef() 0000000000073204 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWChannel::getHWStatisticsGroupTable() 0000000000073212 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWChannel::clearInterrupEnableFlag() 000000000007321c long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDSPUHWChannel::getIndirectCommandSize() 0000000000073230 long 0e SECT 01 0000 [.text] __GLOBAL__I_a 0000000000073270 long 0e SECT 01 0000 [.text] __GLOBAL__D_a 00000000000732c2 long 0e SECT 01 0000 [.text] AMDSISPURing::MetaClass::~MetaClass() 0000000000073722 long 0e SECT 01 0000 [.text] AMDSISPURing::MetaClass::~MetaClass() 000000000007372c long 0e SECT 01 0000 [.text] AMDRadeonX4000_IAMDHWRing::init() 000000000007373e long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWRing::isEnabled() 0000000000073748 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWRing::getTail() 0000000000073754 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWRing::getFreeSpace() 0000000000073784 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWRing::isEmpty() 00000000000737b2 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWRing::getRingGartAddr() 00000000000737bc long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWRing::getSize() 00000000000737c6 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWRing::getRingBlock(unsigned int) 00000000000737d8 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWRing::getRingId() 00000000000737f0 long 0e SECT 01 0000 [.text] __GLOBAL__I_a 0000000000073830 long 0e SECT 01 0000 [.text] __GLOBAL__D_a 0000000000073882 long 0e SECT 01 0000 [.text] AMDSIComputeRing::MetaClass::~MetaClass() 0000000000073e0e long 0e SECT 01 0000 [.text] AMDSIComputeRing::MetaClass::~MetaClass() 0000000000073e18 long 0e SECT 01 0000 [.text] AMDRadeonX4000_IAMDHWRing::init() 0000000000073e2a long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWRing::isEnabled() 0000000000073e34 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWRing::getHead() 0000000000073e44 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWRing::getTail() 0000000000073e50 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWRing::getFreeSpace() 0000000000073e80 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWRing::isEmpty() 0000000000073eae long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWRing::getRingGartAddr() 0000000000073eb8 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWRing::getSize() 0000000000073ec2 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWRing::getRingBlock(unsigned int) 0000000000073ed4 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWRing::commitBlock(unsigned int) 0000000000073ee4 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWRing::getRingId() 0000000000073ef0 long 0e SECT 01 0000 [.text] __GLOBAL__I_a 0000000000073f30 long 0e SECT 01 0000 [.text] __GLOBAL__D_a 0000000000073f82 long 0e SECT 01 0000 [.text] AMDSIPM4ComputeChannel::MetaClass::~MetaClass() 0000000000074664 long 0e SECT 01 0000 [.text] AMDSIPM4ComputeChannel::MetaClass::~MetaClass() 000000000007466e long 0e SECT 01 0000 [.text] AMDRadeonX4000_IAMDHWChannel::init() 0000000000074680 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWChannel::getChannelIndex() 000000000007468a long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWChannel::getChannelRingType() 00000000000746a6 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWChannel::initializeSubmitCommandBufferInfo(AMD_SUBMIT_COMMAND_BUFFER_INFO*) 00000000000746bc long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWChannel::alignCommandBufferAddress(unsigned int) 00000000000746d2 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWChannel::getName() 00000000000746dc long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWChannel::dumpEngineHangState(bool) 00000000000746f6 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWChannel::engineType() 0000000000074708 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWChannel::isDebugFlagEnabled(unsigned int) 000000000007471c long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWChannel::getTimestampInterruptRef() 0000000000074726 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWChannel::getHWStatisticsGroupTable() 0000000000074734 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWChannel::clearInterrupEnableFlag() 000000000007473e long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWChannel::getIndirectCommandSize() 0000000000074750 long 0e SECT 01 0000 [.text] __GLOBAL__I_a 0000000000074790 long 0e SECT 01 0000 [.text] __GLOBAL__D_a 00000000000747e2 long 0e SECT 01 0000 [.text] AMDCIHardware::MetaClass::~MetaClass() 0000000000077132 long 0e SECT 01 0000 [.text] AMDCIHardware::MetaClass::~MetaClass() 000000000007713c long 0e SECT 01 0000 [.text] AMDRadeonX4000_IAMDHWInterface::init() 000000000007714e long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHardware::getHWMemoryDescriptor() 000000000007715c long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHardware::getChipEngine() 0000000000077168 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHardware::getConfigBits() 0000000000077174 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHardware::getHWCapabilities() 000000000007717e long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHardware::getAMDHwCailAdapterInfo() 000000000007718c long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHardware::getMaskSettings() 000000000007719a long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHardware::getChipID() 00000000000771a6 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHardware::getChipRev() 00000000000771b2 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHardware::getSubSystemID() 00000000000771be long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHardware::getFamily() 00000000000771ca long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHardware::getPreDefinedNdrvVramReservedSpace() 00000000000771d6 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHardware::setTLBInvalidateNeeded(unsigned int) 00000000000771ec long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHardware::getDiagReportBuffer() 0000000000077208 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHardware::getDiagReportBufferSize() 0000000000077214 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHardware::isEnabled() 0000000000077220 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHardware::isMultiEngineSyncEnabled() 000000000007722c long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHardware::getCailHandle() 000000000007723a long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHardware::getAMDHWHandler() 0000000000077244 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHardware::getHWRegisters() 0000000000077252 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHardware::getHWMemory() 0000000000077260 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHardware::getHWGart() 000000000007726e long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHardware::getHWVMM() 000000000007727c long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHardware::getHWDisplay() 000000000007728a long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHardware::getHWAlignManager() 0000000000077298 long 0e SECT 01 0000 [.text] AMDCIHardware::getHWWorkarounds() 00000000000772a6 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHardware::getAMDHWUtilities() 00000000000772b4 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHardware::getHWEngine(_eAMD_HW_ENGINE_TYPE) 00000000000772c4 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHardware::getChannelCount() 00000000000772d0 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHardware::getChannelWriteBackDescriptor() 00000000000772de long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHardware::getChannelWriteBackFrameSize() 00000000000772ea long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHardware::getHWSemaphorePool() 00000000000772f8 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHardware::getIOPCIDevice() 0000000000077302 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHardware::getSML() 0000000000077310 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHardware::getPM4CommandsUtility() 000000000007731e long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHardware::getGpuDebugPolicy() 000000000007732a long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHardware::getCailIri() const 0000000000077338 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHardware::setPPLibIri(CAIL_IRI_REGISTRY_STRUCT*) 0000000000077380 long 0e SECT 01 0000 [.text] AMDCIHardware::getGPUVMDefaultSettings() 000000000007738c long 0e SECT 01 0000 [.text] AMDCIHardware::getMEQCmdQueueSelIndex() 0000000000077398 long 0e SECT 01 0000 [.text] AMDCIHardware::shallInitializeMC_VM_MD_L1_TLB3_CNTL() 00000000000773a0 long 0e SECT 01 0000 [.text] AMDCIHardware::allocatePM4Engine() 00000000000773b0 long 0e SECT 01 0000 [.text] __GLOBAL__I_a 00000000000773f0 long 0e SECT 01 0000 [.text] __GLOBAL__D_a 0000000000077442 long 0e SECT 01 0000 [.text] AMDBonaireHardware::MetaClass::~MetaClass() 00000000000776ce long 0e SECT 01 0000 [.text] AMDRadeonX4000_IAMDHWInterface::init() 00000000000776e0 long 0e SECT 01 0000 [.text] AMDBonaireHardware::free() 00000000000776f2 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHardware::getHWMemoryDescriptor() 0000000000077700 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHardware::getChipEngine() 000000000007770c long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHardware::getConfigBits() 0000000000077718 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHardware::getHWCapabilities() 0000000000077722 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHardware::getAMDHwCailAdapterInfo() 0000000000077730 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHardware::getMaskSettings() 000000000007773e long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHardware::getChipID() 000000000007774a long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHardware::getChipRev() 0000000000077756 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHardware::getSubSystemID() 0000000000077762 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHardware::getFamily() 000000000007776e long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHardware::getPreDefinedNdrvVramReservedSpace() 000000000007777a long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHardware::setTLBInvalidateNeeded(unsigned int) 0000000000077790 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHardware::getDiagReportBuffer() 00000000000777ac long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHardware::getDiagReportBufferSize() 00000000000777b8 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHardware::isEnabled() 00000000000777c4 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHardware::isMultiEngineSyncEnabled() 00000000000777d0 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHardware::getCailHandle() 00000000000777de long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHardware::getAMDHWHandler() 00000000000777e8 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHardware::getHWRegisters() 00000000000777f6 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHardware::getHWMemory() 0000000000077804 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHardware::getHWGart() 0000000000077812 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHardware::getHWVMM() 0000000000077820 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHardware::getHWDisplay() 000000000007782e long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHardware::getHWAlignManager() 000000000007783c long 0e SECT 01 0000 [.text] AMDCIHardware::getHWWorkarounds() 000000000007784a long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHardware::getAMDHWUtilities() 0000000000077858 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHardware::getHWEngine(_eAMD_HW_ENGINE_TYPE) 0000000000077868 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHardware::getChannelCount() 0000000000077874 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHardware::getChannelWriteBackDescriptor() 0000000000077882 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHardware::getChannelWriteBackFrameSize() 000000000007788e long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHardware::getHWSemaphorePool() 000000000007789c long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHardware::getIOPCIDevice() 00000000000778a6 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHardware::getSML() 00000000000778b4 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHardware::getPM4CommandsUtility() 00000000000778c2 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHardware::getGpuDebugPolicy() 00000000000778ce long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHardware::getCailIri() const 00000000000778dc long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHardware::setPPLibIri(CAIL_IRI_REGISTRY_STRUCT*) 0000000000077924 long 0e SECT 01 0000 [.text] AMDCIHardware::getGPUVMDefaultSettings() 0000000000077930 long 0e SECT 01 0000 [.text] AMDCIHardware::getMEQCmdQueueSelIndex() 000000000007793c long 0e SECT 01 0000 [.text] AMDCIHardware::shallInitializeMC_VM_MD_L1_TLB3_CNTL() 0000000000077944 long 0e SECT 01 0000 [.text] AMDCIHardware::allocatePM4Engine() 000000000007794c long 0e SECT 01 0000 [.text] AMDBonaireHardware::MetaClass::~MetaClass() 0000000000077960 long 0e SECT 01 0000 [.text] __GLOBAL__I_a 00000000000779a0 long 0e SECT 01 0000 [.text] __GLOBAL__D_a 00000000000779f2 long 0e SECT 01 0000 [.text] AMDHawaiiHardware::MetaClass::~MetaClass() 0000000000077c76 long 0e SECT 01 0000 [.text] AMDRadeonX4000_IAMDHWInterface::init() 0000000000077c88 long 0e SECT 01 0000 [.text] AMDHawaiiHardware::free() 0000000000077c9a long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHardware::getHWMemoryDescriptor() 0000000000077ca8 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHardware::getChipEngine() 0000000000077cb4 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHardware::getConfigBits() 0000000000077cc0 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHardware::getHWCapabilities() 0000000000077cca long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHardware::getAMDHwCailAdapterInfo() 0000000000077cd8 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHardware::getMaskSettings() 0000000000077ce6 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHardware::getChipID() 0000000000077cf2 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHardware::getChipRev() 0000000000077cfe long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHardware::getSubSystemID() 0000000000077d0a long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHardware::getFamily() 0000000000077d16 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHardware::getPreDefinedNdrvVramReservedSpace() 0000000000077d22 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHardware::setTLBInvalidateNeeded(unsigned int) 0000000000077d38 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHardware::getDiagReportBuffer() 0000000000077d54 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHardware::getDiagReportBufferSize() 0000000000077d60 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHardware::isEnabled() 0000000000077d6c long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHardware::isMultiEngineSyncEnabled() 0000000000077d78 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHardware::getCailHandle() 0000000000077d86 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHardware::getAMDHWHandler() 0000000000077d90 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHardware::getHWRegisters() 0000000000077d9e long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHardware::getHWMemory() 0000000000077dac long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHardware::getHWGart() 0000000000077dba long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHardware::getHWVMM() 0000000000077dc8 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHardware::getHWDisplay() 0000000000077dd6 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHardware::getHWAlignManager() 0000000000077de4 long 0e SECT 01 0000 [.text] AMDCIHardware::getHWWorkarounds() 0000000000077df2 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHardware::getAMDHWUtilities() 0000000000077e00 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHardware::getHWEngine(_eAMD_HW_ENGINE_TYPE) 0000000000077e10 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHardware::getChannelCount() 0000000000077e1c long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHardware::getChannelWriteBackDescriptor() 0000000000077e2a long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHardware::getChannelWriteBackFrameSize() 0000000000077e36 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHardware::getHWSemaphorePool() 0000000000077e44 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHardware::getIOPCIDevice() 0000000000077e4e long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHardware::getSML() 0000000000077e5c long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHardware::getPM4CommandsUtility() 0000000000077e6a long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHardware::getGpuDebugPolicy() 0000000000077e76 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHardware::getCailIri() const 0000000000077e84 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHardware::setPPLibIri(CAIL_IRI_REGISTRY_STRUCT*) 0000000000077ecc long 0e SECT 01 0000 [.text] AMDCIHardware::getGPUVMDefaultSettings() 0000000000077ed8 long 0e SECT 01 0000 [.text] AMDCIHardware::getMEQCmdQueueSelIndex() 0000000000077ee4 long 0e SECT 01 0000 [.text] AMDCIHardware::shallInitializeMC_VM_MD_L1_TLB3_CNTL() 0000000000077eec long 0e SECT 01 0000 [.text] AMDCIHardware::allocatePM4Engine() 0000000000077ef4 long 0e SECT 01 0000 [.text] AMDHawaiiHardware::MetaClass::~MetaClass() 0000000000077f00 long 0e SECT 01 0000 [.text] __GLOBAL__I_a 0000000000077f40 long 0e SECT 01 0000 [.text] __GLOBAL__D_a 0000000000077f92 long 0e SECT 01 0000 [.text] AMDCIPM4Engine::MetaClass::~MetaClass() 00000000000795ae long 0e SECT 01 0000 [.text] AMDCIPM4Engine::MetaClass::~MetaClass() 00000000000795b8 long 0e SECT 01 0000 [.text] AMDRadeonX4000_IAMDHWEngine::init() 00000000000795ca long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWEngine::type() 00000000000795d4 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWEngine::isEnabled() 00000000000795de long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDPM4HWEngine::initializeRegisters() 000000000007960e long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDPM4HWEngine::systemDidChangeSpeedEvent() 0000000000079614 long 0e SECT 01 0000 [.text] AMDCIPM4Engine::alignCommandBufferAddress(unsigned int) 000000000007961c long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWEngine::getVersion(unsigned int) 000000000007962c long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWEngine::getChannelCount() 0000000000079636 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWEngine::getFwvFunction() 000000000007963e long 0e SECT 01 0000 [.text] AMDCIPM4Engine::dumpEngineHangState(bool) 0000000000079658 long 0e SECT 01 0000 [.text] AMDCIPM4Engine::loadPM4Microcode() 0000000000079660 long 0e SECT 01 0000 [.text] __GLOBAL__I_a 00000000000796a0 long 0e SECT 01 0000 [.text] __GLOBAL__D_a 00000000000796f2 long 0e SECT 01 0000 [.text] AMDCICommandsRing::MetaClass::~MetaClass() 0000000000079a4e long 0e SECT 01 0000 [.text] AMDCICommandsRing::MetaClass::~MetaClass() 0000000000079a58 long 0e SECT 01 0000 [.text] AMDRadeonX4000_IAMDHWRing::init() 0000000000079a6a long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWRing::isEnabled() 0000000000079a74 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWRing::getHead() 0000000000079a84 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWRing::getTail() 0000000000079a90 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWRing::getFreeSpace() 0000000000079ac0 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWRing::isEmpty() 0000000000079aee long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWRing::getRingGartAddr() 0000000000079af8 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWRing::getSize() 0000000000079b02 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWRing::getRingBlock(unsigned int) 0000000000079b14 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWRing::commitBlock(unsigned int) 0000000000079b24 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWRing::getRingId() 0000000000079b30 long 0e SECT 01 0000 [.text] __GLOBAL__I_a 0000000000079b70 long 0e SECT 01 0000 [.text] __GLOBAL__D_a 0000000000079bc2 long 0e SECT 01 0000 [.text] AMDCIsDMAEngine::MetaClass::~MetaClass() 000000000007a2d4 long 0e SECT 01 0000 [.text] AMDCIsDMAEngine::MetaClass::~MetaClass() 000000000007a2de long 0e SECT 01 0000 [.text] AMDRadeonX4000_IAMDHWEngine::init() 000000000007a2f0 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWEngine::type() 000000000007a2fa long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWEngine::isEnabled() 000000000007a304 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWEngine::setVirtualSpaceReady(bool) 000000000007a30a long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDDMAHWEngine::setMemoryAllocationsEnabled(bool) 000000000007a310 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDDMAHWEngine::initializeRegisters() 000000000007a316 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDDMAHWEngine::systemWillChangeSpeedEvent() 000000000007a31c long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDDMAHWEngine::systemDidChangeSpeedEvent() 000000000007a322 long 0e SECT 01 0000 [.text] AMDCIsDMAEngine::alignCommandBufferAddress(unsigned int) 000000000007a334 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWEngine::getVersion(unsigned int) 000000000007a344 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWEngine::getChannelCount() 000000000007a34e long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWEngine::getTimestampIRQSourcex(_eAMD_HW_RING_TYPE) 000000000007a356 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWEngine::getFwvFunction() 000000000007a35e long 0e SECT 01 0000 [.text] AMDCIsDMAEngine::getVersion() 000000000007a370 long 0e SECT 01 0000 [.text] __GLOBAL__I_a 000000000007a3b0 long 0e SECT 01 0000 [.text] __GLOBAL__D_a 000000000007a402 long 0e SECT 01 0000 [.text] AMDCIsDMARing::MetaClass::~MetaClass() 000000000007a8fc long 0e SECT 01 0000 [.text] AMDCIsDMARing::MetaClass::~MetaClass() 000000000007a906 long 0e SECT 01 0000 [.text] AMDRadeonX4000_IAMDHWRing::init() 000000000007a918 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWRing::isEnabled() 000000000007a922 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWRing::getTail() 000000000007a92e long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWRing::getFreeSpace() 000000000007a95e long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWRing::isEmpty() 000000000007a98c long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWRing::getRingGartAddr() 000000000007a996 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWRing::getSize() 000000000007a9a0 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWRing::getRingBlock(unsigned int) 000000000007a9b2 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWRing::commitBlock(unsigned int) 000000000007a9c2 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWRing::getRingId() 000000000007a9d0 long 0e SECT 01 0000 [.text] __GLOBAL__I_a 000000000007aa10 long 0e SECT 01 0000 [.text] __GLOBAL__D_a 000000000007aa62 long 0e SECT 01 0000 [.text] AMDCIPM4CommandsUtility::MetaClass::~MetaClass() 000000000007aeae long 0e SECT 01 0000 [.text] AMDCIPM4CommandsUtility::init() 000000000007aec0 long 0e SECT 01 0000 [.text] AMDCIPM4CommandsUtility::free() 000000000007aed2 long 0e SECT 01 0000 [.text] AMDCIPM4CommandsUtility::MetaClass::~MetaClass() 000000000007aee0 long 0e SECT 01 0000 [.text] __GLOBAL__I_a 000000000007af20 long 0e SECT 01 0000 [.text] __GLOBAL__D_a 000000000007af72 long 0e SECT 01 0000 [.text] AMDCIDisplay::MetaClass::~MetaClass() 000000000007c402 long 0e SECT 01 0000 [.text] AMDCIDisplay::MetaClass::~MetaClass() 000000000007c40c long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWDisplay::getBuiltIn(unsigned int) 000000000007c428 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWDisplay::getBuiltInExists() 000000000007c436 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWDisplay::getInterlaced(unsigned int) 000000000007c450 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWDisplay::setFullScreenEnabled(unsigned int, bool) 000000000007c474 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWDisplay::getFullScreenEnabled(unsigned int) 000000000007c490 long 0e SECT 01 0000 [.text] AMDCIDisplay::getNumberOfSupportedDisplays() 000000000007c49c long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWDisplay::isFEDSEnabled() 000000000007c4aa long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWDisplay::isFEDSEnabled(unsigned int) 000000000007c4c6 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWDisplay::FEDSIsColorBuffer(unsigned int) 000000000007c4de long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWDisplay::FEDSSetIsColorBuffer(unsigned int, unsigned int) 000000000007c4f6 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWDisplay::isAnyDisplayModeAccelBacked() 000000000007c502 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWDisplay::isDisplayModeAccelBacked(unsigned int) 000000000007c51c long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWDisplay::getScalerFlags(unsigned int) 000000000007c53e long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWDisplay::isScaledNeeded() 000000000007c586 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWDisplay::isScaledNeeded(unsigned int) 000000000007c5a6 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWDisplay::isFedsRequired() 000000000007c5ee long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWDisplay::isFedsRequired(unsigned int) 000000000007c624 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWDisplay::getFedsParamInfo() const 000000000007c62e long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWDisplay::isFEDSBufferDirty(unsigned int) 000000000007c648 long 0e SECT 01 0000 [.text] AMDCIDisplay::writeTilingControlRegisters(unsigned int, unsigned int*, unsigned int) 000000000007c650 long 0e SECT 01 0000 [.text] __GLOBAL__I_a 000000000007c690 long 0e SECT 01 0000 [.text] __GLOBAL__D_a 000000000007c6e2 long 0e SECT 01 0000 [.text] AMDCIHWMemory::MetaClass::~MetaClass() 000000000007cd5e long 0e SECT 01 0000 [.text] AMDCIHWMemory::MetaClass::~MetaClass() 000000000007cd68 long 0e SECT 01 0000 [.text] AMDRadeonX4000_IAMDHWMemory::init() 000000000007cd7a long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWMemory::getMemoryDescriptor() 000000000007cd88 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWMemory::isMapped() 000000000007cd94 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWMemory::setReservedNdrvSpace(unsigned long long) 000000000007cd9e long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWMemory::getTotalSize() 000000000007cda8 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWMemory::getVisibleSize() 000000000007cdb2 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWMemory::getInvisibleSize() 000000000007cdc0 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWMemory::isNonVisibleMemoryExists() 000000000007cde0 long 0e SECT 01 0000 [.text] __GLOBAL__I_a 000000000007ce20 long 0e SECT 01 0000 [.text] __GLOBAL__D_a 000000000007ce72 long 0e SECT 01 0000 [.text] AMDCIHWUtilities::MetaClass::~MetaClass() 000000000007d126 long 0e SECT 01 0000 [.text] AMDRadeonX4000_IAMDHWUtilities::init() 000000000007d138 long 0e SECT 01 0000 [.text] AMDCIHWUtilities::free() 000000000007d14a long 0e SECT 01 0000 [.text] AMDCIHWUtilities::init(AMDRadeonX4000_IAMDHWInterface*) 000000000007d15c long 0e SECT 01 0000 [.text] AMDCIHWUtilities::MetaClass::~MetaClass() 000000000007d170 long 0e SECT 01 0000 [.text] __GLOBAL__I_a 000000000007d1b0 long 0e SECT 01 0000 [.text] __GLOBAL__D_a 000000000007d202 long 0e SECT 01 0000 [.text] AMDCIPM4Channel::MetaClass::~MetaClass() 000000000007e09c long 0e SECT 01 0000 [.text] AMDCIPM4Channel::MetaClass::~MetaClass() 000000000007e0a6 long 0e SECT 01 0000 [.text] AMDRadeonX4000_IAMDHWChannel::init() 000000000007e0b8 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWChannel::getChannelIndex() 000000000007e0c2 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWChannel::getChannelRingType() 000000000007e0de long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWChannel::initializeSubmitCommandBufferInfo(AMD_SUBMIT_COMMAND_BUFFER_INFO*) 000000000007e0f4 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWChannel::alignCommandBufferAddress(unsigned int) 000000000007e10a long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWChannel::getName() 000000000007e114 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWChannel::dumpEngineHangState(bool) 000000000007e12e long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWChannel::engineType() 000000000007e140 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWChannel::isDebugFlagEnabled(unsigned int) 000000000007e154 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWChannel::getTimestampInterruptRef() 000000000007e15e long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWChannel::getHWStatisticsGroupTable() 000000000007e16c long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWChannel::clearInterrupEnableFlag() 000000000007e176 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWChannel::getIndirectCommandSize() 000000000007e182 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDPM4HWChannel::enableScratchRegisterWriteback() 000000000007e188 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDPM4HWChannel::disableScratchRegisterWriteback() 000000000007e18e long 0e SECT 01 0000 [.text] AMDCIPM4Channel::setupPerFramePacket(unsigned int, unsigned int, unsigned int, unsigned int) 000000000007e194 long 0e SECT 01 0000 [.text] AMDCIPM4Channel::resetPerFramePacket() 000000000007e1a0 long 0e SECT 01 0000 [.text] __GLOBAL__I_a 000000000007e1e0 long 0e SECT 01 0000 [.text] __GLOBAL__D_a 000000000007e232 long 0e SECT 01 0000 [.text] AMDCIDMAChannel::MetaClass::~MetaClass() 000000000007ef3a long 0e SECT 01 0000 [.text] AMDCIDMAChannel::MetaClass::~MetaClass() 000000000007ef44 long 0e SECT 01 0000 [.text] AMDRadeonX4000_IAMDHWChannel::init() 000000000007ef56 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWChannel::getChannelIndex() 000000000007ef60 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWChannel::getChannelRingType() 000000000007ef7c long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWChannel::initializeSubmitCommandBufferInfo(AMD_SUBMIT_COMMAND_BUFFER_INFO*) 000000000007ef92 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWChannel::alignCommandBufferAddress(unsigned int) 000000000007efa8 long 0e SECT 01 0000 [.text] AMDCIDMAChannel::getIBAlignmentFactor() 000000000007efb4 long 0e SECT 01 0000 [.text] AMDCIDMAChannel::getOneDwordNOPCommand() 000000000007efbc long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWChannel::getName() 000000000007efc6 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWChannel::dumpEngineHangState(bool) 000000000007efe0 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWChannel::engineType() 000000000007eff2 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWChannel::isDebugFlagEnabled(unsigned int) 000000000007f006 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWChannel::getTimestampInterruptRef() 000000000007f010 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWChannel::getHWStatisticsGroupTable() 000000000007f01e long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWChannel::clearInterrupEnableFlag() 000000000007f028 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWChannel::getIndirectCommandSize() 000000000007f034 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDDMAHWChannel::getDmaPktInfo(AMD_DMA_COMMAND_TYPE) const 000000000007f050 long 0e SECT 01 0000 [.text] __GLOBAL__I_a 000000000007f090 long 0e SECT 01 0000 [.text] __GLOBAL__D_a 000000000007f0e2 long 0e SECT 01 0000 [.text] AMDCISAMUEngine::MetaClass::~MetaClass() 000000000007f892 long 0e SECT 01 0000 [.text] AMDCISAMUEngine::MetaClass::~MetaClass() 000000000007f89c long 0e SECT 01 0000 [.text] AMDRadeonX4000_IAMDHWEngine::init() 000000000007f8ae long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWEngine::type() 000000000007f8b8 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWEngine::isEnabled() 000000000007f8c2 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWEngine::setVirtualSpaceReady(bool) 000000000007f8c8 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDSPUHWEngine::initializeRegisters() 000000000007f8ce long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDSPUHWEngine::systemWillChangeSpeedEvent() 000000000007f8d4 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDSPUHWEngine::systemDidChangeSpeedEvent() 000000000007f8da long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDSPUHWEngine::alignCommandBufferAddress(unsigned int) 000000000007f8ec long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWEngine::getVersion(unsigned int) 000000000007f8fc long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWEngine::getChannelCount() 000000000007f906 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWEngine::getTimestampIRQSourcex(_eAMD_HW_RING_TYPE) 000000000007f90e long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWEngine::getFwvFunction() 000000000007f920 long 0e SECT 01 0000 [.text] __GLOBAL__I_a 000000000007f960 long 0e SECT 01 0000 [.text] __GLOBAL__D_a 000000000007f9b2 long 0e SECT 01 0000 [.text] AMDCISAMURBIRing::MetaClass::~MetaClass() 000000000007fe14 long 0e SECT 01 0000 [.text] AMDCISAMURBIRing::MetaClass::~MetaClass() 000000000007fe1e long 0e SECT 01 0000 [.text] AMDRadeonX4000_IAMDHWRing::init() 000000000007fe30 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWRing::isEnabled() 000000000007fe3a long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWRing::isEmpty() 000000000007fe68 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWRing::getRingGartAddr() 000000000007fe72 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWRing::getSize() 000000000007fe7c long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWRing::getRingBlock(unsigned int) 000000000007fe8e long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWRing::getRingId() 000000000007fea0 long 0e SECT 01 0000 [.text] __GLOBAL__I_a 000000000007fee0 long 0e SECT 01 0000 [.text] __GLOBAL__D_a 000000000007ff32 long 0e SECT 01 0000 [.text] AMDCISAMURBIChannel::MetaClass::~MetaClass() 000000000008018a long 0e SECT 01 0000 [.text] AMDCISAMURBIChannel::MetaClass::~MetaClass() 0000000000080194 long 0e SECT 01 0000 [.text] AMDRadeonX4000_IAMDHWChannel::init() 00000000000801a6 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWChannel::getChannelIndex() 00000000000801b0 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWChannel::getChannelRingType() 00000000000801cc long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWChannel::initializeSubmitCommandBufferInfo(AMD_SUBMIT_COMMAND_BUFFER_INFO*) 00000000000801e2 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWChannel::alignCommandBufferAddress(unsigned int) 00000000000801f8 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDSPUHWChannel::getIBAlignmentFactor() 0000000000080204 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDSPUHWChannel::getOneDwordNOPCommand() 0000000000080210 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWChannel::writeSemaphoreCommand(unsigned int*, unsigned long long, bool) const 0000000000080218 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWChannel::getName() 0000000000080222 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWChannel::dumpEngineHangState(bool) 000000000008023c long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWChannel::writeProfilingCommand(unsigned int*, unsigned long long, unsigned int, bool) 0000000000080244 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWChannel::engineType() 0000000000080256 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWChannel::isDebugFlagEnabled(unsigned int) 000000000008026a long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWChannel::getTimestampInterruptRef() 0000000000080274 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWChannel::getHWStatisticsGroupTable() 0000000000080282 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWChannel::clearInterrupEnableFlag() 000000000008028c long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDSPUHWChannel::getIndirectCommandSize() 00000000000802a0 long 0e SECT 01 0000 [.text] __GLOBAL__I_a 00000000000802e0 long 0e SECT 01 0000 [.text] __GLOBAL__D_a 0000000000080332 long 0e SECT 01 0000 [.text] AMDCISAMUGPCOMRing::MetaClass::~MetaClass() 0000000000080936 long 0e SECT 01 0000 [.text] AMDCISAMUGPCOMRing::MetaClass::~MetaClass() 0000000000080940 long 0e SECT 01 0000 [.text] AMDRadeonX4000_IAMDHWRing::init() 0000000000080952 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWRing::isEnabled() 000000000008095c long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWRing::getTail() 0000000000080968 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWRing::getFreeSpace() 0000000000080998 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWRing::isEmpty() 00000000000809c6 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWRing::getRingGartAddr() 00000000000809d0 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWRing::getSize() 00000000000809da long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWRing::getRingBlock(unsigned int) 00000000000809ec long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWRing::getRingId() 00000000000809f8 long 0e SECT 01 0000 [.text] AMDCISAMUGPCOMRing::getFeedbackAddr() 0000000000080a06 long 0e SECT 01 0000 [.text] AMDCISAMUGPCOMRing::getFeedbackBufSize() 0000000000080a20 long 0e SECT 01 0000 [.text] __GLOBAL__I_a 0000000000080a60 long 0e SECT 01 0000 [.text] __GLOBAL__D_a 0000000000080ab2 long 0e SECT 01 0000 [.text] AMDCISAMUGPCOMChannel::MetaClass::~MetaClass() 0000000000080cf6 long 0e SECT 01 0000 [.text] AMDCISAMUGPCOMChannel::MetaClass::~MetaClass() 0000000000080d00 long 0e SECT 01 0000 [.text] AMDRadeonX4000_IAMDHWChannel::init() 0000000000080d12 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWChannel::getChannelIndex() 0000000000080d1c long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWChannel::getChannelRingType() 0000000000080d38 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWChannel::initializeSubmitCommandBufferInfo(AMD_SUBMIT_COMMAND_BUFFER_INFO*) 0000000000080d4e long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWChannel::alignCommandBufferAddress(unsigned int) 0000000000080d64 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDSPUHWChannel::getIBAlignmentFactor() 0000000000080d70 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDSPUHWChannel::getOneDwordNOPCommand() 0000000000080d7c long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWChannel::writeSemaphoreCommand(unsigned int*, unsigned long long, bool) const 0000000000080d84 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWChannel::getName() 0000000000080d8e long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWChannel::dumpEngineHangState(bool) 0000000000080da8 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWChannel::writeProfilingCommand(unsigned int*, unsigned long long, unsigned int, bool) 0000000000080db0 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWChannel::engineType() 0000000000080dc2 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWChannel::isDebugFlagEnabled(unsigned int) 0000000000080dd6 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWChannel::getTimestampInterruptRef() 0000000000080de0 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWChannel::getHWStatisticsGroupTable() 0000000000080dee long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWChannel::clearInterrupEnableFlag() 0000000000080df8 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDSPUHWChannel::getIndirectCommandSize() 0000000000080e10 long 0e SECT 01 0000 [.text] __GLOBAL__I_a 0000000000080e50 long 0e SECT 01 0000 [.text] __GLOBAL__D_a 0000000000080ea2 long 0e SECT 01 0000 [.text] AMDCIUVDHWEngine::MetaClass::~MetaClass() 000000000008126e long 0e SECT 01 0000 [.text] AMDRadeonX4000_IAMDHWEngine::init() 0000000000081280 long 0e SECT 01 0000 [.text] AMDCIUVDHWEngine::free() 0000000000081292 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWEngine::type() 000000000008129c long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDUVDHWEngine::initializeRegisters() 00000000000812a2 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDUVDHWEngine::systemWillChangeSpeedEvent() 00000000000812a8 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDUVDHWEngine::systemDidChangeSpeedEvent() 00000000000812ae long 0e SECT 01 0000 [.text] AMDSIUVDHWEngine::alignCommandBufferAddress(unsigned int) 00000000000812ba long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWEngine::getVersion(unsigned int) 00000000000812ca long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWEngine::getChannelCount() 00000000000812d4 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWEngine::getTimestampIRQSourcex(_eAMD_HW_RING_TYPE) 00000000000812dc long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDUVDHWEngine::getFirmwareAddress() 00000000000812ea long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDUVDHWEngine::getTotalCapability() 00000000000812fe long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDUVDHWEngine::getCurrentCapability() 0000000000081312 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDUVDHWEngine::getHWRegisters() 000000000008131c long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDUVDHWEngine::getKeySelect() 0000000000081328 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDUVDHWEngine::setDpmSupported(bool) 0000000000081336 long 0e SECT 01 0000 [.text] AMDCIUVDHWEngine::MetaClass::~MetaClass() 0000000000081340 long 0e SECT 01 0000 [.text] __GLOBAL__I_a 0000000000081380 long 0e SECT 01 0000 [.text] __GLOBAL__D_a 00000000000813d2 long 0e SECT 01 0000 [.text] AMDCIVCEHWEngine::MetaClass::~MetaClass() 0000000000081a8c long 0e SECT 01 0000 [.text] AMDCIVCEHWEngine::MetaClass::~MetaClass() 0000000000081a96 long 0e SECT 01 0000 [.text] AMDRadeonX4000_IAMDHWEngine::init() 0000000000081aa8 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWEngine::type() 0000000000081ab2 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWEngine::isEnabled() 0000000000081abc long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWEngine::setVirtualSpaceReady(bool) 0000000000081ac2 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDVCEHWEngine::initializeRegisters() 0000000000081ac8 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDVCEHWEngine::systemWillChangeSpeedEvent() 0000000000081ace long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDVCEHWEngine::systemDidChangeSpeedEvent() 0000000000081ad4 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDVCEHWEngine::alignCommandBufferAddress(unsigned int) 0000000000081ae0 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWEngine::getVersion(unsigned int) 0000000000081af0 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWEngine::getChannelCount() 0000000000081afa long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWEngine::getTimestampIRQSourcex(_eAMD_HW_RING_TYPE) 0000000000081b02 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWEngine::getFwvFunction() 0000000000081b0a long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDVCEHWEngine::getTotalCapability() 0000000000081b1e long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDVCEHWEngine::getCurrentCapability() 0000000000081b32 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDVCEHWEngine::getVCEVClk() 0000000000081b40 long 0e SECT 01 0000 [.text] __GLOBAL__I_a 0000000000081b80 long 0e SECT 01 0000 [.text] __GLOBAL__D_a 0000000000081bd2 long 0e SECT 01 0000 [.text] AMDCIVCEChannel::MetaClass::~MetaClass() 0000000000081ef8 long 0e SECT 01 0000 [.text] AMDCIVCEChannel::MetaClass::~MetaClass() 0000000000081f02 long 0e SECT 01 0000 [.text] AMDRadeonX4000_IAMDHWChannel::init() 0000000000081f14 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWChannel::getChannelIndex() 0000000000081f1e long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWChannel::getChannelRingType() 0000000000081f3a long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWChannel::initializeSubmitCommandBufferInfo(AMD_SUBMIT_COMMAND_BUFFER_INFO*) 0000000000081f50 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWChannel::alignCommandBufferAddress(unsigned int) 0000000000081f66 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDVCEHWChannel::getIBAlignmentFactor() 0000000000081f72 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDVCEHWChannel::getOneDwordNOPCommand() 0000000000081f7a long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWChannel::getName() 0000000000081f84 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWChannel::dumpEngineHangState(bool) 0000000000081f9e long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWChannel::writeProfilingCommand(unsigned int*, unsigned long long, unsigned int, bool) 0000000000081fa6 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWChannel::engineType() 0000000000081fb8 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWChannel::isDebugFlagEnabled(unsigned int) 0000000000081fcc long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWChannel::getTimestampInterruptRef() 0000000000081fd6 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWChannel::getHWStatisticsGroupTable() 0000000000081fe4 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWChannel::clearInterrupEnableFlag() 0000000000081ff0 long 0e SECT 01 0000 [.text] __GLOBAL__I_a 0000000000082030 long 0e SECT 01 0000 [.text] __GLOBAL__D_a 0000000000082082 long 0e SECT 01 0000 [.text] AMDCIVCELLQChannel::MetaClass::~MetaClass() 0000000000082212 long 0e SECT 01 0000 [.text] AMDCIVCELLQChannel::MetaClass::~MetaClass() 000000000008221c long 0e SECT 01 0000 [.text] AMDRadeonX4000_IAMDHWChannel::init() 000000000008222e long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWChannel::getChannelIndex() 0000000000082238 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWChannel::getChannelRingType() 0000000000082254 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWChannel::initializeSubmitCommandBufferInfo(AMD_SUBMIT_COMMAND_BUFFER_INFO*) 000000000008226a long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWChannel::alignCommandBufferAddress(unsigned int) 0000000000082280 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDVCEHWChannel::getIBAlignmentFactor() 000000000008228c long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDVCEHWChannel::getOneDwordNOPCommand() 0000000000082294 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWChannel::getName() 000000000008229e long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWChannel::dumpEngineHangState(bool) 00000000000822b8 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWChannel::writeProfilingCommand(unsigned int*, unsigned long long, unsigned int, bool) 00000000000822c0 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWChannel::engineType() 00000000000822d2 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWChannel::isDebugFlagEnabled(unsigned int) 00000000000822e6 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWChannel::getTimestampInterruptRef() 00000000000822f0 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWChannel::getHWStatisticsGroupTable() 00000000000822fe long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWChannel::clearInterrupEnableFlag() 0000000000082310 long 0e SECT 01 0000 [.text] __GLOBAL__I_a 0000000000082350 long 0e SECT 01 0000 [.text] __GLOBAL__D_a 00000000000823a2 long 0e SECT 01 0000 [.text] AMDCIVCERing::MetaClass::~MetaClass() 00000000000827cc long 0e SECT 01 0000 [.text] AMDCIVCERing::MetaClass::~MetaClass() 00000000000827d6 long 0e SECT 01 0000 [.text] AMDRadeonX4000_IAMDHWRing::init() 00000000000827e8 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWRing::isEnabled() 00000000000827f2 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWRing::getTail() 00000000000827fe long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWRing::getFreeSpace() 000000000008282e long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWRing::isEmpty() 000000000008285c long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWRing::getRingGartAddr() 0000000000082866 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWRing::getSize() 0000000000082870 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWRing::getRingBlock(unsigned int) 0000000000082882 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWRing::commitBlock(unsigned int) 0000000000082892 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWRing::getRingId() 00000000000828a0 long 0e SECT 01 0000 [.text] __GLOBAL__I_a 00000000000828e0 long 0e SECT 01 0000 [.text] __GLOBAL__D_a 0000000000082932 long 0e SECT 01 0000 [.text] AMDCIVCELLQRing::MetaClass::~MetaClass() 0000000000082bba long 0e SECT 01 0000 [.text] AMDCIVCELLQRing::MetaClass::~MetaClass() 0000000000082bc4 long 0e SECT 01 0000 [.text] AMDRadeonX4000_IAMDHWRing::init() 0000000000082bd6 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWRing::isEnabled() 0000000000082be0 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWRing::getTail() 0000000000082bec long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWRing::getFreeSpace() 0000000000082c1c long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWRing::isEmpty() 0000000000082c4a long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWRing::getRingGartAddr() 0000000000082c54 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWRing::getSize() 0000000000082c5e long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWRing::getRingBlock(unsigned int) 0000000000082c70 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWRing::commitBlock(unsigned int) 0000000000082c80 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWRing::getRingId() 0000000000082c90 long 0e SECT 01 0000 [.text] __GLOBAL__I_a 0000000000082cd0 long 0e SECT 01 0000 [.text] __GLOBAL__D_a 0000000000082d22 long 0e SECT 01 0000 [.text] AMDCIComputeRing::MetaClass::~MetaClass() 0000000000083106 long 0e SECT 01 0000 [.text] AMDCIComputeRing::MetaClass::~MetaClass() 0000000000083110 long 0e SECT 01 0000 [.text] AMDRadeonX4000_IAMDHWRing::init() 0000000000083122 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWRing::isEnabled() 000000000008312c long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWRing::getHead() 000000000008313c long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWRing::getTail() 0000000000083148 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWRing::getFreeSpace() 0000000000083178 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWRing::isEmpty() 00000000000831a6 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWRing::getRingGartAddr() 00000000000831b0 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWRing::getSize() 00000000000831ba long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWRing::getRingBlock(unsigned int) 00000000000831cc long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWRing::commitBlock(unsigned int) 00000000000831dc long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWRing::getRingId() 00000000000831f0 long 0e SECT 01 0000 [.text] __GLOBAL__I_a 0000000000083230 long 0e SECT 01 0000 [.text] __GLOBAL__D_a 0000000000083282 long 0e SECT 01 0000 [.text] AMDCIPM4ComputeChannel::MetaClass::~MetaClass() 0000000000083cac long 0e SECT 01 0000 [.text] AMDCIPM4ComputeChannel::MetaClass::~MetaClass() 0000000000083cb6 long 0e SECT 01 0000 [.text] AMDRadeonX4000_IAMDHWChannel::init() 0000000000083cc8 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWChannel::getChannelIndex() 0000000000083cd2 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWChannel::getChannelRingType() 0000000000083cee long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWChannel::initializeSubmitCommandBufferInfo(AMD_SUBMIT_COMMAND_BUFFER_INFO*) 0000000000083d04 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWChannel::alignCommandBufferAddress(unsigned int) 0000000000083d1a long 0e SECT 01 0000 [.text] AMDCIPM4ComputeChannel::getIBAlignmentFactor() 0000000000083d26 long 0e SECT 01 0000 [.text] AMDCIPM4ComputeChannel::getOneDwordNOPCommand() 0000000000083d32 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWChannel::getName() 0000000000083d3c long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWChannel::dumpEngineHangState(bool) 0000000000083d56 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWChannel::writeProfilingCommand(unsigned int*, unsigned long long, unsigned int, bool) 0000000000083d5e long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWChannel::engineType() 0000000000083d70 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWChannel::isDebugFlagEnabled(unsigned int) 0000000000083d84 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWChannel::getTimestampInterruptRef() 0000000000083d8e long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWChannel::getHWStatisticsGroupTable() 0000000000083d9c long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWChannel::clearInterrupEnableFlag() 0000000000083da6 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWChannel::getIndirectCommandSize() 0000000000083db2 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDPM4HWChannel::enableScratchRegisterWriteback() 0000000000083db8 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDPM4HWChannel::disableScratchRegisterWriteback() 0000000000083dbe long 0e SECT 01 0000 [.text] AMDCIPM4ComputeChannel::setupPerFramePacket(unsigned int, unsigned int, unsigned int, unsigned int) 0000000000083dc4 long 0e SECT 01 0000 [.text] AMDCIPM4ComputeChannel::resetPerFramePacket() 0000000000083dd0 long 0e SECT 01 0000 [.text] __GLOBAL__I_a 0000000000083e10 long 0e SECT 01 0000 [.text] __GLOBAL__D_a 0000000000083e62 long 0e SECT 01 0000 [.text] AMDVIHardware::MetaClass::~MetaClass() 00000000000868a4 long 0e SECT 01 0000 [.text] AMDVIHardware::MetaClass::~MetaClass() 00000000000868ae long 0e SECT 01 0000 [.text] AMDRadeonX4000_IAMDHWInterface::init() 00000000000868c0 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHardware::getHWMemoryDescriptor() 00000000000868ce long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHardware::getChipEngine() 00000000000868da long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHardware::getConfigBits() 00000000000868e6 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHardware::getHWCapabilities() 00000000000868f0 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHardware::getAMDHwCailAdapterInfo() 00000000000868fe long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHardware::getMaskSettings() 000000000008690c long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHardware::getChipID() 0000000000086918 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHardware::getChipRev() 0000000000086924 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHardware::getSubSystemID() 0000000000086930 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHardware::getFamily() 000000000008693c long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHardware::getPreDefinedNdrvVramReservedSpace() 0000000000086948 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHardware::setTLBInvalidateNeeded(unsigned int) 000000000008695e long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHardware::getDiagReportBuffer() 000000000008697a long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHardware::getDiagReportBufferSize() 0000000000086986 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHardware::isEnabled() 0000000000086992 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHardware::isMultiEngineSyncEnabled() 000000000008699e long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHardware::getCailHandle() 00000000000869ac long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHardware::getAMDHWHandler() 00000000000869b6 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHardware::getHWRegisters() 00000000000869c4 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHardware::getHWMemory() 00000000000869d2 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHardware::getHWGart() 00000000000869e0 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHardware::getHWVMM() 00000000000869ee long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHardware::getHWDisplay() 00000000000869fc long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHardware::getHWAlignManager() 0000000000086a0a long 0e SECT 01 0000 [.text] AMDVIHardware::getHWWorkarounds() 0000000000086a18 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHardware::getAMDHWUtilities() 0000000000086a26 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHardware::getHWEngine(_eAMD_HW_ENGINE_TYPE) 0000000000086a36 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHardware::getChannelCount() 0000000000086a42 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHardware::getChannelWriteBackDescriptor() 0000000000086a50 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHardware::getChannelWriteBackFrameSize() 0000000000086a5c long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHardware::getHWSemaphorePool() 0000000000086a6a long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHardware::getIOPCIDevice() 0000000000086a74 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHardware::getSML() 0000000000086a82 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHardware::getPM4CommandsUtility() 0000000000086a90 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHardware::getGpuDebugPolicy() 0000000000086a9c long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHardware::getCailIri() const 0000000000086aaa long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHardware::setPPLibIri(CAIL_IRI_REGISTRY_STRUCT*) 0000000000086af2 long 0e SECT 01 0000 [.text] AMDVIHardware::getGPUVMDefaultSettings() 0000000000086afe long 0e SECT 01 0000 [.text] AMDVIHardware::getMEQCmdQueueSelIndex() 0000000000086b0a long 0e SECT 01 0000 [.text] AMDVIHardware::shallInitializeMC_VM_MD_L1_TLB3_CNTL() 0000000000086b20 long 0e SECT 01 0000 [.text] __GLOBAL__I_a 0000000000086b60 long 0e SECT 01 0000 [.text] __GLOBAL__D_a 0000000000086bb2 long 0e SECT 01 0000 [.text] AMDTongaHardware::MetaClass::~MetaClass() 0000000000086e3e long 0e SECT 01 0000 [.text] AMDRadeonX4000_IAMDHWInterface::init() 0000000000086e50 long 0e SECT 01 0000 [.text] AMDTongaHardware::free() 0000000000086e62 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHardware::getHWMemoryDescriptor() 0000000000086e70 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHardware::getChipEngine() 0000000000086e7c long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHardware::getConfigBits() 0000000000086e88 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHardware::getHWCapabilities() 0000000000086e92 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHardware::getAMDHwCailAdapterInfo() 0000000000086ea0 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHardware::getMaskSettings() 0000000000086eae long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHardware::getChipID() 0000000000086eba long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHardware::getChipRev() 0000000000086ec6 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHardware::getSubSystemID() 0000000000086ed2 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHardware::getFamily() 0000000000086ede long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHardware::getPreDefinedNdrvVramReservedSpace() 0000000000086eea long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHardware::setTLBInvalidateNeeded(unsigned int) 0000000000086f00 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHardware::getDiagReportBuffer() 0000000000086f1c long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHardware::getDiagReportBufferSize() 0000000000086f28 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHardware::isEnabled() 0000000000086f34 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHardware::isMultiEngineSyncEnabled() 0000000000086f40 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHardware::getCailHandle() 0000000000086f4e long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHardware::getAMDHWHandler() 0000000000086f58 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHardware::getHWRegisters() 0000000000086f66 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHardware::getHWMemory() 0000000000086f74 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHardware::getHWGart() 0000000000086f82 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHardware::getHWVMM() 0000000000086f90 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHardware::getHWDisplay() 0000000000086f9e long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHardware::getHWAlignManager() 0000000000086fac long 0e SECT 01 0000 [.text] AMDVIHardware::getHWWorkarounds() 0000000000086fba long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHardware::getAMDHWUtilities() 0000000000086fc8 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHardware::getHWEngine(_eAMD_HW_ENGINE_TYPE) 0000000000086fd8 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHardware::getChannelCount() 0000000000086fe4 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHardware::getChannelWriteBackDescriptor() 0000000000086ff2 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHardware::getChannelWriteBackFrameSize() 0000000000086ffe long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHardware::getHWSemaphorePool() 000000000008700c long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHardware::getIOPCIDevice() 0000000000087016 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHardware::getSML() 0000000000087024 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHardware::getPM4CommandsUtility() 0000000000087032 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHardware::getGpuDebugPolicy() 000000000008703e long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHardware::getCailIri() const 000000000008704c long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHardware::setPPLibIri(CAIL_IRI_REGISTRY_STRUCT*) 0000000000087094 long 0e SECT 01 0000 [.text] AMDVIHardware::getGPUVMDefaultSettings() 00000000000870a0 long 0e SECT 01 0000 [.text] AMDVIHardware::getMEQCmdQueueSelIndex() 00000000000870ac long 0e SECT 01 0000 [.text] AMDVIHardware::shallInitializeMC_VM_MD_L1_TLB3_CNTL() 00000000000870b4 long 0e SECT 01 0000 [.text] AMDTongaHardware::MetaClass::~MetaClass() 00000000000870c0 long 0e SECT 01 0000 [.text] __GLOBAL__I_a 0000000000087100 long 0e SECT 01 0000 [.text] __GLOBAL__D_a 0000000000087152 long 0e SECT 01 0000 [.text] AMDVIHWGart::MetaClass::~MetaClass() 0000000000087552 long 0e SECT 01 0000 [.text] AMDVIHWGart::MetaClass::~MetaClass() 000000000008755c long 0e SECT 01 0000 [.text] AMDRadeonX4000_IAMDHWGart::init() 000000000008756e long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWGart::getVirtualSpaceRemappingBaseAddress() 0000000000087578 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWGart::getSize() 0000000000087582 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWGart::getBaseTableAddress() 0000000000087590 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWGart::getBaseTablePadSize() 000000000008759c long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWGart::getTotalAllocationSize() 00000000000875d0 long 0e SECT 01 0000 [.text] __GLOBAL__I_a 0000000000087610 long 0e SECT 01 0000 [.text] __GLOBAL__D_a 0000000000087662 long 0e SECT 01 0000 [.text] AMDVIHWMemory::MetaClass::~MetaClass() 0000000000087c64 long 0e SECT 01 0000 [.text] AMDVIHWMemory::MetaClass::~MetaClass() 0000000000087c6e long 0e SECT 01 0000 [.text] AMDRadeonX4000_IAMDHWMemory::init() 0000000000087c80 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWMemory::getMemoryDescriptor() 0000000000087c8e long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWMemory::isMapped() 0000000000087c9a long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWMemory::setReservedNdrvSpace(unsigned long long) 0000000000087ca4 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWMemory::getTotalSize() 0000000000087cae long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWMemory::getVisibleSize() 0000000000087cb8 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWMemory::getInvisibleSize() 0000000000087cc6 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWMemory::isNonVisibleMemoryExists() 0000000000087ce0 long 0e SECT 01 0000 [.text] __GLOBAL__I_a 0000000000087d20 long 0e SECT 01 0000 [.text] __GLOBAL__D_a 0000000000087d72 long 0e SECT 01 0000 [.text] AMDVIVMContext::MetaClass::~MetaClass() 00000000000890c8 long 0e SECT 01 0000 [.text] AMDVIVMContext::MetaClass::~MetaClass() 00000000000890d2 long 0e SECT 01 0000 [.text] AMDRadeonX4000_IAMDHWVMContext::init() 00000000000890e4 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWVMContext::mapLocalVA(unsigned long long, unsigned long long, unsigned long long) 000000000008910a long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWVMContext::mapSystemVA(unsigned long long, IOMemoryDescriptor*) 0000000000089134 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWVMContext::mapSystemVA(unsigned long long, unsigned long long, unsigned long long) 000000000008915c long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWVMContext::getCurrentVMID() 0000000000089178 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWVMContext::getPDBaseAddress() 0000000000089186 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWVMContext::isPageTableUpdated() 0000000000089192 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWVMContext::clearPageTableUpdated() 00000000000891a0 long 0e SECT 01 0000 [.text] __GLOBAL__I_a 00000000000891e0 long 0e SECT 01 0000 [.text] __GLOBAL__D_a 0000000000089232 long 0e SECT 01 0000 [.text] AMDVIVMM::MetaClass::~MetaClass() 00000000000895d0 long 0e SECT 01 0000 [.text] AMDVIVMM::MetaClass::~MetaClass() 00000000000895da long 0e SECT 01 0000 [.text] AMDRadeonX4000_IAMDHWVMM::init() 00000000000895ec long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWVMM::getBaseAddress() 00000000000895f6 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWVMM::getVMPTVirtualAddress() 0000000000089600 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWVMM::getVMPTVirtualAddress(unsigned long long) 0000000000089638 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWVMM::getVMRangeStart() 0000000000089642 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWVMM::getVMRangeEnd() 0000000000089650 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWVMM::getVMPTBCoverage() 000000000008965e long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWVMM::getVMPTBVRAMSize() 000000000008966c long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWVMM::getVMPTDVRAMSize() 000000000008967a long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWVMM::getVMPTBTotal() 0000000000089688 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWVMM::getVMPTBPerPTB() 0000000000089696 long 0e SECT 01 0000 [.text] AMDVIVMM::getMinVMID() 00000000000896a2 long 0e SECT 01 0000 [.text] AMDVIVMM::getMaxVMID() 00000000000896ae long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWVMM::getFragmentStrategy() 00000000000896ba long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWVMM::getBIGKValue() 00000000000896c6 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWVMM::getBIGKInBytes() 00000000000896d2 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWVMM::getFragmentAlignment() 00000000000896e0 long 0e SECT 01 0000 [.text] __GLOBAL__I_a 0000000000089720 long 0e SECT 01 0000 [.text] __GLOBAL__D_a 0000000000089772 long 0e SECT 01 0000 [.text] AMDVIDisplay::MetaClass::~MetaClass() 000000000008b184 long 0e SECT 01 0000 [.text] AMDVIDisplay::MetaClass::~MetaClass() 000000000008b18e long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWDisplay::getBuiltIn(unsigned int) 000000000008b1aa long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWDisplay::getBuiltInExists() 000000000008b1b8 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWDisplay::getInterlaced(unsigned int) 000000000008b1d2 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWDisplay::setFullScreenEnabled(unsigned int, bool) 000000000008b1f6 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWDisplay::getFullScreenEnabled(unsigned int) 000000000008b212 long 0e SECT 01 0000 [.text] AMDVIDisplay::getNumberOfSupportedDisplays() 000000000008b21e long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWDisplay::isFEDSEnabled() 000000000008b22c long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWDisplay::isFEDSEnabled(unsigned int) 000000000008b248 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWDisplay::FEDSIsColorBuffer(unsigned int) 000000000008b260 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWDisplay::FEDSSetIsColorBuffer(unsigned int, unsigned int) 000000000008b278 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWDisplay::isAnyDisplayModeAccelBacked() 000000000008b284 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWDisplay::isDisplayModeAccelBacked(unsigned int) 000000000008b29e long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWDisplay::getScalerFlags(unsigned int) 000000000008b2c0 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWDisplay::isScaledNeeded() 000000000008b308 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWDisplay::isScaledNeeded(unsigned int) 000000000008b328 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWDisplay::isFedsRequired() 000000000008b370 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWDisplay::isFedsRequired(unsigned int) 000000000008b3a6 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWDisplay::getFedsParamInfo() const 000000000008b3b0 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWDisplay::isFEDSBufferDirty(unsigned int) 000000000008b3d0 long 0e SECT 01 0000 [.text] __GLOBAL__I_a 000000000008b410 long 0e SECT 01 0000 [.text] __GLOBAL__D_a 000000000008b462 long 0e SECT 01 0000 [.text] AMDVIHWUtilities::MetaClass::~MetaClass() 000000000008b734 long 0e SECT 01 0000 [.text] AMDVIHWUtilities::MetaClass::~MetaClass() 000000000008b73e long 0e SECT 01 0000 [.text] AMDRadeonX4000_IAMDHWUtilities::init() 000000000008b750 long 0e SECT 01 0000 [.text] __GLOBAL__I_a 000000000008b790 long 0e SECT 01 0000 [.text] __GLOBAL__D_a 000000000008b7e2 long 0e SECT 01 0000 [.text] AMDVIsDMAChannel::MetaClass::~MetaClass() 000000000008c4ea long 0e SECT 01 0000 [.text] AMDVIsDMAChannel::MetaClass::~MetaClass() 000000000008c4f4 long 0e SECT 01 0000 [.text] AMDRadeonX4000_IAMDHWChannel::init() 000000000008c506 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWChannel::getChannelIndex() 000000000008c510 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWChannel::getChannelRingType() 000000000008c52c long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWChannel::initializeSubmitCommandBufferInfo(AMD_SUBMIT_COMMAND_BUFFER_INFO*) 000000000008c542 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWChannel::alignCommandBufferAddress(unsigned int) 000000000008c558 long 0e SECT 01 0000 [.text] AMDVIsDMAChannel::getIBAlignmentFactor() 000000000008c564 long 0e SECT 01 0000 [.text] AMDVIsDMAChannel::getOneDwordNOPCommand() 000000000008c570 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWChannel::getName() 000000000008c57a long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWChannel::dumpEngineHangState(bool) 000000000008c594 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWChannel::engineType() 000000000008c5a6 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWChannel::isDebugFlagEnabled(unsigned int) 000000000008c5ba long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWChannel::getTimestampInterruptRef() 000000000008c5c4 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWChannel::getHWStatisticsGroupTable() 000000000008c5d2 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWChannel::clearInterrupEnableFlag() 000000000008c5dc long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWChannel::getIndirectCommandSize() 000000000008c5e8 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDDMAHWChannel::getDmaPktInfo(AMD_DMA_COMMAND_TYPE) const 000000000008c600 long 0e SECT 01 0000 [.text] __GLOBAL__I_a 000000000008c640 long 0e SECT 01 0000 [.text] __GLOBAL__D_a 000000000008c692 long 0e SECT 01 0000 [.text] AMDVIsDMAEngine::MetaClass::~MetaClass() 000000000008cd80 long 0e SECT 01 0000 [.text] AMDVIsDMAEngine::MetaClass::~MetaClass() 000000000008cd8a long 0e SECT 01 0000 [.text] AMDRadeonX4000_IAMDHWEngine::init() 000000000008cd9c long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWEngine::type() 000000000008cda6 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWEngine::isEnabled() 000000000008cdb0 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWEngine::setVirtualSpaceReady(bool) 000000000008cdb6 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDDMAHWEngine::setMemoryAllocationsEnabled(bool) 000000000008cdbc long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDDMAHWEngine::initializeRegisters() 000000000008cdc2 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDDMAHWEngine::systemWillChangeSpeedEvent() 000000000008cdc8 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDDMAHWEngine::systemDidChangeSpeedEvent() 000000000008cdce long 0e SECT 01 0000 [.text] AMDVIsDMAEngine::alignCommandBufferAddress(unsigned int) 000000000008cde0 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWEngine::getVersion(unsigned int) 000000000008cdf0 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWEngine::getChannelCount() 000000000008cdfa long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWEngine::getTimestampIRQSourcex(_eAMD_HW_RING_TYPE) 000000000008ce02 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWEngine::getFwvFunction() 000000000008ce0a long 0e SECT 01 0000 [.text] AMDVIsDMAEngine::getVersion() 000000000008ce20 long 0e SECT 01 0000 [.text] __GLOBAL__I_a 000000000008ce60 long 0e SECT 01 0000 [.text] __GLOBAL__D_a 000000000008ceb2 long 0e SECT 01 0000 [.text] AMDVIsDMARing::MetaClass::~MetaClass() 000000000008d334 long 0e SECT 01 0000 [.text] AMDVIsDMARing::MetaClass::~MetaClass() 000000000008d33e long 0e SECT 01 0000 [.text] AMDRadeonX4000_IAMDHWRing::init() 000000000008d350 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWRing::isEnabled() 000000000008d35a long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWRing::getTail() 000000000008d366 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWRing::getFreeSpace() 000000000008d396 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWRing::isEmpty() 000000000008d3c4 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWRing::getRingGartAddr() 000000000008d3ce long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWRing::getSize() 000000000008d3d8 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWRing::getRingBlock(unsigned int) 000000000008d3ea long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWRing::commitBlock(unsigned int) 000000000008d3fa long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWRing::getRingId() 000000000008d410 long 0e SECT 01 0000 [.text] __GLOBAL__I_a 000000000008d450 long 0e SECT 01 0000 [.text] __GLOBAL__D_a 000000000008d4a2 long 0e SECT 01 0000 [.text] AMDVICommandsRing::MetaClass::~MetaClass() 000000000008d7fe long 0e SECT 01 0000 [.text] AMDVICommandsRing::MetaClass::~MetaClass() 000000000008d808 long 0e SECT 01 0000 [.text] AMDRadeonX4000_IAMDHWRing::init() 000000000008d81a long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWRing::isEnabled() 000000000008d824 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWRing::getHead() 000000000008d834 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWRing::getTail() 000000000008d840 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWRing::getFreeSpace() 000000000008d870 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWRing::isEmpty() 000000000008d89e long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWRing::getRingGartAddr() 000000000008d8a8 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWRing::getSize() 000000000008d8b2 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWRing::getRingBlock(unsigned int) 000000000008d8c4 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWRing::commitBlock(unsigned int) 000000000008d8d4 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWRing::getRingId() 000000000008d8e0 long 0e SECT 01 0000 [.text] __GLOBAL__I_a 000000000008d920 long 0e SECT 01 0000 [.text] __GLOBAL__D_a 000000000008d972 long 0e SECT 01 0000 [.text] AMDVIComputeRing::MetaClass::~MetaClass() 000000000008dd74 long 0e SECT 01 0000 [.text] AMDVIComputeRing::MetaClass::~MetaClass() 000000000008dd7e long 0e SECT 01 0000 [.text] AMDRadeonX4000_IAMDHWRing::init() 000000000008dd90 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWRing::isEnabled() 000000000008dd9a long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWRing::getHead() 000000000008ddaa long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWRing::getTail() 000000000008ddb6 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWRing::getFreeSpace() 000000000008dde6 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWRing::isEmpty() 000000000008de14 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWRing::getRingGartAddr() 000000000008de1e long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWRing::getSize() 000000000008de28 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWRing::getRingBlock(unsigned int) 000000000008de3a long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWRing::commitBlock(unsigned int) 000000000008de4a long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWRing::getRingId() 000000000008de60 long 0e SECT 01 0000 [.text] __GLOBAL__I_a 000000000008dea0 long 0e SECT 01 0000 [.text] __GLOBAL__D_a 000000000008def2 long 0e SECT 01 0000 [.text] AMDVIPM4Channel::MetaClass::~MetaClass() 000000000008ed8e long 0e SECT 01 0000 [.text] AMDVIPM4Channel::MetaClass::~MetaClass() 000000000008ed98 long 0e SECT 01 0000 [.text] AMDRadeonX4000_IAMDHWChannel::init() 000000000008edaa long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWChannel::getChannelIndex() 000000000008edb4 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWChannel::getChannelRingType() 000000000008edd0 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWChannel::initializeSubmitCommandBufferInfo(AMD_SUBMIT_COMMAND_BUFFER_INFO*) 000000000008ede6 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWChannel::alignCommandBufferAddress(unsigned int) 000000000008edfc long 0e SECT 01 0000 [.text] AMDVIPM4Channel::getOneDwordNOPCommand() 000000000008ee08 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWChannel::getName() 000000000008ee12 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWChannel::dumpEngineHangState(bool) 000000000008ee2c long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWChannel::engineType() 000000000008ee3e long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWChannel::isDebugFlagEnabled(unsigned int) 000000000008ee52 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWChannel::getTimestampInterruptRef() 000000000008ee5c long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWChannel::getHWStatisticsGroupTable() 000000000008ee6a long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWChannel::clearInterrupEnableFlag() 000000000008ee74 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWChannel::getIndirectCommandSize() 000000000008ee80 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDPM4HWChannel::enableScratchRegisterWriteback() 000000000008ee86 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDPM4HWChannel::disableScratchRegisterWriteback() 000000000008ee8c long 0e SECT 01 0000 [.text] AMDVIPM4Channel::setupPerFramePacket(unsigned int, unsigned int, unsigned int, unsigned int) 000000000008ee92 long 0e SECT 01 0000 [.text] AMDVIPM4Channel::resetPerFramePacket() 000000000008eea0 long 0e SECT 01 0000 [.text] __GLOBAL__I_a 000000000008eee0 long 0e SECT 01 0000 [.text] __GLOBAL__D_a 000000000008ef32 long 0e SECT 01 0000 [.text] AMDVIPM4CommandsUtility::MetaClass::~MetaClass() 000000000008f2be long 0e SECT 01 0000 [.text] AMDVIPM4CommandsUtility::free() 000000000008f2d0 long 0e SECT 01 0000 [.text] AMDVIPM4CommandsUtility::MetaClass::~MetaClass() 000000000008f2e0 long 0e SECT 01 0000 [.text] __GLOBAL__I_a 000000000008f320 long 0e SECT 01 0000 [.text] __GLOBAL__D_a 000000000008f372 long 0e SECT 01 0000 [.text] AMDVIPM4Engine::MetaClass::~MetaClass() 00000000000914f2 long 0e SECT 01 0000 [.text] AMDVIPM4Engine::MetaClass::~MetaClass() 00000000000914fc long 0e SECT 01 0000 [.text] AMDRadeonX4000_IAMDHWEngine::init() 000000000009150e long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWEngine::type() 0000000000091518 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWEngine::isEnabled() 0000000000091522 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDPM4HWEngine::initializeRegisters() 0000000000091552 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDPM4HWEngine::systemDidChangeSpeedEvent() 0000000000091558 long 0e SECT 01 0000 [.text] AMDVIPM4Engine::alignCommandBufferAddress(unsigned int) 0000000000091560 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWEngine::getVersion(unsigned int) 0000000000091570 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWEngine::getChannelCount() 000000000009157a long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWEngine::getFwvFunction() 0000000000091582 long 0e SECT 01 0000 [.text] AMDVIPM4Engine::dumpEngineHangState(bool) 000000000009159c long 0e SECT 01 0000 [.text] AMDVIPM4Engine::loadPM4Microcode() 00000000000915b0 long 0e SECT 01 0000 [.text] __GLOBAL__I_a 00000000000915f0 long 0e SECT 01 0000 [.text] __GLOBAL__D_a 0000000000091642 long 0e SECT 01 0000 [.text] AMDVIPM4ComputeChannel::MetaClass::~MetaClass() 0000000000092134 long 0e SECT 01 0000 [.text] AMDVIPM4ComputeChannel::MetaClass::~MetaClass() 000000000009213e long 0e SECT 01 0000 [.text] AMDRadeonX4000_IAMDHWChannel::init() 0000000000092150 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWChannel::getChannelIndex() 000000000009215a long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWChannel::getChannelRingType() 0000000000092176 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWChannel::initializeSubmitCommandBufferInfo(AMD_SUBMIT_COMMAND_BUFFER_INFO*) 000000000009218c long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWChannel::alignCommandBufferAddress(unsigned int) 00000000000921a2 long 0e SECT 01 0000 [.text] AMDVIPM4ComputeChannel::getIBAlignmentFactor() 00000000000921ae long 0e SECT 01 0000 [.text] AMDVIPM4ComputeChannel::getOneDwordNOPCommand() 00000000000921ba long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWChannel::getName() 00000000000921c4 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWChannel::dumpEngineHangState(bool) 00000000000921de long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWChannel::writeProfilingCommand(unsigned int*, unsigned long long, unsigned int, bool) 00000000000921e6 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWChannel::engineType() 00000000000921f8 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWChannel::isDebugFlagEnabled(unsigned int) 000000000009220c long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWChannel::getTimestampInterruptRef() 0000000000092216 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWChannel::getHWStatisticsGroupTable() 0000000000092224 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWChannel::clearInterrupEnableFlag() 000000000009222e long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWChannel::getIndirectCommandSize() 000000000009223a long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDPM4HWChannel::enableScratchRegisterWriteback() 0000000000092240 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDPM4HWChannel::disableScratchRegisterWriteback() 0000000000092246 long 0e SECT 01 0000 [.text] AMDVIPM4ComputeChannel::setupPerFramePacket(unsigned int, unsigned int, unsigned int, unsigned int) 000000000009224c long 0e SECT 01 0000 [.text] AMDVIPM4ComputeChannel::resetPerFramePacket() 0000000000092260 long 0e SECT 01 0000 [.text] __GLOBAL__I_a 00000000000922a0 long 0e SECT 01 0000 [.text] __GLOBAL__D_a 00000000000922f2 long 0e SECT 01 0000 [.text] AMDVISAMUEngine::MetaClass::~MetaClass() 000000000009266e long 0e SECT 01 0000 [.text] AMDVISAMUEngine::MetaClass::~MetaClass() 0000000000092678 long 0e SECT 01 0000 [.text] AMDRadeonX4000_IAMDHWEngine::init() 000000000009268a long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWEngine::type() 0000000000092694 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWEngine::isEnabled() 000000000009269e long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWEngine::setVirtualSpaceReady(bool) 00000000000926a4 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDSPUHWEngine::initializeRegisters() 00000000000926aa long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDSPUHWEngine::systemWillChangeSpeedEvent() 00000000000926b0 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDSPUHWEngine::systemDidChangeSpeedEvent() 00000000000926b6 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDSPUHWEngine::alignCommandBufferAddress(unsigned int) 00000000000926c8 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWEngine::getVersion(unsigned int) 00000000000926d8 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWEngine::getChannelCount() 00000000000926e2 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWEngine::getTimestampIRQSourcex(_eAMD_HW_RING_TYPE) 00000000000926ea long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWEngine::getFwvFunction() 0000000000092700 long 0e SECT 01 0000 [.text] __GLOBAL__I_a 0000000000092740 long 0e SECT 01 0000 [.text] __GLOBAL__D_a 0000000000092792 long 0e SECT 01 0000 [.text] AMDVISAMURBIRing::MetaClass::~MetaClass() 0000000000092a7c long 0e SECT 01 0000 [.text] AMDVISAMURBIRing::MetaClass::~MetaClass() 0000000000092a86 long 0e SECT 01 0000 [.text] AMDRadeonX4000_IAMDHWRing::init() 0000000000092a98 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWRing::isEnabled() 0000000000092aa2 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWRing::isEmpty() 0000000000092ad0 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWRing::getRingGartAddr() 0000000000092ada long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWRing::getSize() 0000000000092ae4 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWRing::getRingBlock(unsigned int) 0000000000092af6 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWRing::getRingId() 0000000000092b10 long 0e SECT 01 0000 [.text] __GLOBAL__I_a 0000000000092b50 long 0e SECT 01 0000 [.text] __GLOBAL__D_a 0000000000092ba2 long 0e SECT 01 0000 [.text] AMDVISAMURBIChannel::MetaClass::~MetaClass() 0000000000092d26 long 0e SECT 01 0000 [.text] AMDVISAMURBIChannel::MetaClass::~MetaClass() 0000000000092d30 long 0e SECT 01 0000 [.text] AMDRadeonX4000_IAMDHWChannel::init() 0000000000092d42 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWChannel::getChannelIndex() 0000000000092d4c long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWChannel::getChannelRingType() 0000000000092d68 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWChannel::initializeSubmitCommandBufferInfo(AMD_SUBMIT_COMMAND_BUFFER_INFO*) 0000000000092d7e long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWChannel::alignCommandBufferAddress(unsigned int) 0000000000092d94 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDSPUHWChannel::getIBAlignmentFactor() 0000000000092da0 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDSPUHWChannel::getOneDwordNOPCommand() 0000000000092dac long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWChannel::writeSemaphoreCommand(unsigned int*, unsigned long long, bool) const 0000000000092db4 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWChannel::getName() 0000000000092dbe long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWChannel::dumpEngineHangState(bool) 0000000000092dd8 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWChannel::writeProfilingCommand(unsigned int*, unsigned long long, unsigned int, bool) 0000000000092de0 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWChannel::engineType() 0000000000092df2 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWChannel::isDebugFlagEnabled(unsigned int) 0000000000092e06 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWChannel::getTimestampInterruptRef() 0000000000092e10 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWChannel::getHWStatisticsGroupTable() 0000000000092e1e long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWChannel::clearInterrupEnableFlag() 0000000000092e28 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDSPUHWChannel::getIndirectCommandSize() 0000000000092e40 long 0e SECT 01 0000 [.text] __GLOBAL__I_a 0000000000092e80 long 0e SECT 01 0000 [.text] __GLOBAL__D_a 0000000000092ed2 long 0e SECT 01 0000 [.text] AMDVISAMUGPCOMRing::MetaClass::~MetaClass() 0000000000093248 long 0e SECT 01 0000 [.text] AMDVISAMUGPCOMRing::MetaClass::~MetaClass() 0000000000093252 long 0e SECT 01 0000 [.text] AMDRadeonX4000_IAMDHWRing::init() 0000000000093264 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWRing::isEnabled() 000000000009326e long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWRing::getTail() 000000000009327a long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWRing::getFreeSpace() 00000000000932aa long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWRing::isEmpty() 00000000000932d8 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWRing::getRingGartAddr() 00000000000932e2 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWRing::getSize() 00000000000932ec long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWRing::getRingBlock(unsigned int) 00000000000932fe long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWRing::getRingId() 000000000009330a long 0e SECT 01 0000 [.text] AMDCISAMUGPCOMRing::getFeedbackAddr() 0000000000093318 long 0e SECT 01 0000 [.text] AMDCISAMUGPCOMRing::getFeedbackBufSize() 0000000000093330 long 0e SECT 01 0000 [.text] __GLOBAL__I_a 0000000000093370 long 0e SECT 01 0000 [.text] __GLOBAL__D_a 00000000000933c2 long 0e SECT 01 0000 [.text] AMDVISAMUGPCOMChannel::MetaClass::~MetaClass() 0000000000093546 long 0e SECT 01 0000 [.text] AMDVISAMUGPCOMChannel::MetaClass::~MetaClass() 0000000000093550 long 0e SECT 01 0000 [.text] AMDRadeonX4000_IAMDHWChannel::init() 0000000000093562 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWChannel::getChannelIndex() 000000000009356c long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWChannel::getChannelRingType() 0000000000093588 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWChannel::initializeSubmitCommandBufferInfo(AMD_SUBMIT_COMMAND_BUFFER_INFO*) 000000000009359e long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWChannel::alignCommandBufferAddress(unsigned int) 00000000000935b4 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDSPUHWChannel::getIBAlignmentFactor() 00000000000935c0 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDSPUHWChannel::getOneDwordNOPCommand() 00000000000935cc long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWChannel::writeSemaphoreCommand(unsigned int*, unsigned long long, bool) const 00000000000935d4 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWChannel::getName() 00000000000935de long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWChannel::dumpEngineHangState(bool) 00000000000935f8 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWChannel::writeProfilingCommand(unsigned int*, unsigned long long, unsigned int, bool) 0000000000093600 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWChannel::engineType() 0000000000093612 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWChannel::isDebugFlagEnabled(unsigned int) 0000000000093626 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWChannel::getTimestampInterruptRef() 0000000000093630 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWChannel::getHWStatisticsGroupTable() 000000000009363e long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHWChannel::clearInterrupEnableFlag() 0000000000093648 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDSPUHWChannel::getIndirectCommandSize() 0000000000093660 long 0e SECT 01 0000 [.text] __GLOBAL__I_a 00000000000936a0 long 0e SECT 01 0000 [.text] __GLOBAL__D_a 000000000009496c long 0e SECT 01 0000 [.text] _shl 0000000000094b78 __float128 e SECT 01 0000 [.text] __start 0000000000094b92 __float128 e SECT 01 0000 [.text] _OSKextGetCurrentIdentifier 0000000000094ba3 __float128 e SECT 01 0000 [.text] _OSKextGetCurrentVersionString 0000000000094bb4 __float128 e SECT 01 0000 [.text] _OSKextGetCurrentLoadTag 0000000000094bc4 __float128 e SECT 01 0000 [.text] __stop 000000000009844c long 0e SECT 01 0000 [.text] AuxSurfMgr::~AuxSurfMgr() 0000000000098456 long 0e SECT 01 0000 [.text] AuxSurfMgr::~AuxSurfMgr() 0000000000098472 long 0e SECT 01 0000 [.text] AuxSurfMgr::HwlRequiresHTileMappingSurf() 000000000009847a long 0e SECT 01 0000 [.text] AuxSurfMgr::HwlInitCmaskAsTexSurf(_UBM_SURFINFO const*, CachedAuxSurf*) 0000000000098486 long 0e SECT 01 0000 [.text] AuxSurfMgr::HwlDestroyCmaskAsTexSurf(CachedAuxSurf*) 000000000009848c long 0e SECT 01 0000 [.text] AuxSurfMgr::HwlInitFmaskAsTexSurf(_UBM_SURFINFO const*, CachedAuxSurf*) 0000000000098498 long 0e SECT 01 0000 [.text] AuxSurfMgr::HwlDestroyFmaskAsTexSurf(CachedAuxSurf*) 000000000009849e long 0e SECT 01 0000 [.text] AuxSurfMgr::HwlInitOffsetTexSurf(_UBM_SURFINFO const*, CachedAuxSurf*) 00000000000984aa long 0e SECT 01 0000 [.text] AuxSurfMgr::HwlDestroyOffsetTexSurf(CachedAuxSurf*) 00000000000984b0 long 0e SECT 01 0000 [.text] AuxSurfMgr::HwlInitHtileAsColorSurf(_UBM_SURFINFO const*, CachedAuxSurf*) 00000000000984bc long 0e SECT 01 0000 [.text] AuxSurfMgr::HwlDestroyHtileAsColorSurf(CachedAuxSurf*) 00000000000984c2 long 0e SECT 01 0000 [.text] AuxSurfMgr::HwlInitHiSSurf(_UBM_SURFINFO const*, CachedAuxSurf*) 00000000000984ce long 0e SECT 01 0000 [.text] AuxSurfMgr::HwlDestroyHiSSurf(CachedAuxSurf*) 00000000000984d4 long 0e SECT 01 0000 [.text] AuxSurfMgr::HwlInitNeighborMaskSurf(_UBM_SURFINFO const*, CachedAuxSurf*) 00000000000984e0 long 0e SECT 01 0000 [.text] AuxSurfMgr::HwlDestroyNeighborMaskSurf(CachedAuxSurf*) 00000000000984e6 long 0e SECT 01 0000 [.text] AuxSurfMgr::HwlInitEdgeMaskSurf(_UBM_SURFINFO const*, CachedAuxSurf*) 00000000000984f2 long 0e SECT 01 0000 [.text] AuxSurfMgr::HwlDestroyEdgeMaskSurf(CachedAuxSurf*) 00000000000984f8 long 0e SECT 01 0000 [.text] AuxSurfMgr::HwlInitPixPreSurf(_UBM_SURFINFO const*, CachedAuxSurf*) 0000000000098504 long 0e SECT 01 0000 [.text] AuxSurfMgr::HwlDestroyPixPreSurf(CachedAuxSurf*) 000000000009850a long 0e SECT 01 0000 [.text] AuxSurfMgr::HwlInitGradSurf(_UBM_SURFINFO const*, CachedAuxSurf*) 0000000000098516 long 0e SECT 01 0000 [.text] AuxSurfMgr::HwlDestroyGradSurf(CachedAuxSurf*) 000000000009851c long 0e SECT 01 0000 [.text] AuxSurfMgr::HwlInitAdvAaDepthSurf(_UBM_SURFINFO const*, CachedAuxSurf*) 0000000000098528 long 0e SECT 01 0000 [.text] AuxSurfMgr::HwlDestroyAdvAaDepthSurf(CachedAuxSurf*) 000000000009852e long 0e SECT 01 0000 [.text] AuxSurfMgr::HwlInitMlaaSepEdgeSurf(_UBM_SURFINFO const*, CachedAuxSurf*) 000000000009853a long 0e SECT 01 0000 [.text] AuxSurfMgr::HwlDestroyMlaaSepEdgeSurf(CachedAuxSurf*) 0000000000098540 long 0e SECT 01 0000 [.text] AuxSurfMgr::HwlInitMlaaEdgeCountSurf(_UBM_SURFINFO const*, CachedAuxSurf*, MlaaEdgeCountSurfDesc) 000000000009854c long 0e SECT 01 0000 [.text] AuxSurfMgr::HwlDestroyMlaaEdgeCountSurf(CachedAuxSurf*) 0000000000098552 long 0e SECT 01 0000 [.text] AuxSurfMgr::HwlInitHTileOffsetSurf(_UBM_SURFINFO const*, _UBM_SURFINFO const*, CachedAuxSurf*) 000000000009855e long 0e SECT 01 0000 [.text] AuxSurfMgr::HwlDestroyHTileOffsetSurf(CachedAuxSurf*) 0000000000098564 long 0e SECT 01 0000 [.text] AuxSurfMgr::HwlInitHTileMappingSurf(_UBM_SURFINFO const*, _UBM_SURFINFO const*, CachedAuxSurf*) 0000000000098570 long 0e SECT 01 0000 [.text] AuxSurfMgr::HwlDestroyHTileMappingSurf(CachedAuxSurf*) 0000000000098722 long 0e SECT 01 0000 [.text] BltDevice::~BltDevice() 000000000009872c long 0e SECT 01 0000 [.text] BltDevice::~BltDevice() 0000000000098748 long 0e SECT 01 0000 [.text] BltDevice::HwlInit(_UBM_DEVICEINFO const*) 0000000000098750 long 0e SECT 01 0000 [.text] BltDevice::HwlTrim() 0000000000098758 long 0e SECT 01 0000 [.text] BltDevice::HwlDestroy() 0000000000098760 long 0e SECT 01 0000 [.text] BltDevice::HwlNotifyShadowMemoryInfo(_UBM_STATESHADOWMEMORYINFO*) 000000000009876c long 0e SECT 01 0000 [.text] BltDevice::HwlClearStateInit() 0000000000098778 long 0e SECT 01 0000 [.text] BltDevice::HwlComputeStateInit() 000000000009ff84 long 0e SECT 01 0000 [.text] BltMgr::HwlGetShadowMemorySize() 000000000009ff8c long 0e SECT 01 0000 [.text] BltMgr::HwlInit() 000000000009ff94 long 0e SECT 01 0000 [.text] BltMgr::HwlTrim() 000000000009ff9c long 0e SECT 01 0000 [.text] BltMgr::HwlDestroy() 000000000009ffa4 long 0e SECT 01 0000 [.text] BltMgr::HwlInitBltInfo(BltInfo*) 000000000009ffaa long 0e SECT 01 0000 [.text] BltMgr::HwlGpuLoadShaders(BltDevice*) 000000000009ffb6 long 0e SECT 01 0000 [.text] BltMgr::HwlCreateHtileSurfInfo(_UBM_SURFINFO*, _UBM_SURFINFO*) 000000000009ffbc long 0e SECT 01 0000 [.text] BltMgr::HwlIsCompressedDepthResolveSupported(BltInfo*) 000000000009ffc4 long 0e SECT 01 0000 [.text] BltMgr::HwlIsOptimizedYuvBltSupported(_UBM_SURFINFO const*, unsigned int) 000000000009ffcc long 0e SECT 01 0000 [.text] BltMgr::HwlGetHtileCopyBltEngine() 00000000000a72e4 long 0e SECT 01 0000 [.text] BltShader::~BltShader() 00000000000a72ee long 0e SECT 01 0000 [.text] BltShader::~BltShader() 00000000000a730a long 0e SECT 01 0000 [.text] BltShader::GpuLoad(BltDevice*, void*, LARGE_INTEGER) 00000000000a7310 long 0e SECT 01 0000 [.text] BltShader::GetShaderMemSize() const 00000000000a731a long 0e SECT 01 0000 [.text] BltShader::GetRoundedShaderMemSize() const 00000000000a7586 long 0e SECT 01 0000 [.text] ShaderVidMemMgr::GpuLoadInitialShaders(BltDevice*) 00000000000a7592 long 0e SECT 01 0000 [.text] ShaderVidMemMgr::GetComputeShader(unsigned int) 00000000000a759a long 0e SECT 01 0000 [.text] ShaderVidMemMgr::GpuLoadAllShaders(BltDevice*) 00000000000a75a6 long 0e SECT 01 0000 [.text] ShaderVidMemMgr::HwlVidMemAllocInfo(_UBM_ALLOCVIDMEM_INPUT*) const 00000000000a7784 long 0e SECT 01 0000 [.text] SurfAttribute::GetTileMode(_UBM_SURFINFO const*) const 00000000000a7790 long 0e SECT 01 0000 [.text] SurfAttribute::GetTileType(_UBM_SURFINFO const*) const 00000000000a779c long 0e SECT 01 0000 [.text] SurfAttribute::GetLinearAlignedTileIndex() const 00000000000a77a8 long 0e SECT 01 0000 [.text] SurfAttribute::GetLinearAlignedSurfacePitchAlign(unsigned int) const 00000000000a77b0 long 0e SECT 01 0000 [.text] SurfAttribute::GetLinearAlignedSurfaceSliceAlign(unsigned int) const 00000000000a77b8 long 0e SECT 01 0000 [.text] SurfAttribute::GetMacroTileDimension(unsigned int, unsigned int*, unsigned int*) const 00000000000aacb4 long 0e SECT 01 0000 [.text] SiBltAuxSurfMgr::~SiBltAuxSurfMgr() 00000000000aacbe long 0e SECT 01 0000 [.text] SiBltAuxSurfMgr::~SiBltAuxSurfMgr() 00000000000aacda long 0e SECT 01 0000 [.text] AuxSurfMgr::HwlRequiresHTileMappingSurf() 00000000000aace2 long 0e SECT 01 0000 [.text] SiBltAuxSurfMgr::HwlDestroyCmaskAsTexSurf(CachedAuxSurf*) 00000000000aace8 long 0e SECT 01 0000 [.text] SiBltAuxSurfMgr::HwlDestroyFmaskAsTexSurf(CachedAuxSurf*) 00000000000aacee long 0e SECT 01 0000 [.text] SiBltAuxSurfMgr::HwlDestroyHtileAsColorSurf(CachedAuxSurf*) 00000000000aacf4 long 0e SECT 01 0000 [.text] SiBltAuxSurfMgr::HwlDestroyHiSSurf(CachedAuxSurf*) 00000000000aacfa long 0e SECT 01 0000 [.text] SiBltAuxSurfMgr::HwlDestroyNeighborMaskSurf(CachedAuxSurf*) 00000000000aad00 long 0e SECT 01 0000 [.text] SiBltAuxSurfMgr::HwlDestroyEdgeMaskSurf(CachedAuxSurf*) 00000000000aad06 long 0e SECT 01 0000 [.text] SiBltAuxSurfMgr::HwlDestroyPixPreSurf(CachedAuxSurf*) 00000000000aad0c long 0e SECT 01 0000 [.text] SiBltAuxSurfMgr::HwlDestroyGradSurf(CachedAuxSurf*) 00000000000aad12 long 0e SECT 01 0000 [.text] SiBltAuxSurfMgr::HwlDestroyAdvAaDepthSurf(CachedAuxSurf*) 00000000000aad18 long 0e SECT 01 0000 [.text] SiBltAuxSurfMgr::HwlDestroyMlaaSepEdgeSurf(CachedAuxSurf*) 00000000000aad1e long 0e SECT 01 0000 [.text] SiBltAuxSurfMgr::HwlDestroyMlaaEdgeCountSurf(CachedAuxSurf*) 00000000000aad24 long 0e SECT 01 0000 [.text] AuxSurfMgr::HwlInitHTileMappingSurf(_UBM_SURFINFO const*, _UBM_SURFINFO const*, CachedAuxSurf*) 00000000000aad30 long 0e SECT 01 0000 [.text] AuxSurfMgr::HwlDestroyHTileMappingSurf(CachedAuxSurf*) 00000000000b21aa long 0e SECT 01 0000 [.text] SiBltDevice::HwlClearStateInit() 00000000000b21b6 long 0e SECT 01 0000 [.text] BltDevice::HwlComputeStateInit() 00000000000b6552 long 0e SECT 01 0000 [.text] BltMgr::HwlTrim() 00000000000b655a long 0e SECT 01 0000 [.text] SiBltMgr::HwlGetMaxWidthHeight() const 00000000000b6566 long 0e SECT 01 0000 [.text] SiBltMgr::HwlGetHtileCopyBltEngine() 00000000000bc20c long 0e SECT 01 0000 [.text] SiBltPixelShader::~SiBltPixelShader() 00000000000bc216 long 0e SECT 01 0000 [.text] SiBltPixelShader::~SiBltPixelShader() 00000000000bdd24 long 0e SECT 01 0000 [.text] SiBltShader::~SiBltShader() 00000000000bdd2e long 0e SECT 01 0000 [.text] SiBltShader::~SiBltShader() 00000000000bdd4a long 0e SECT 01 0000 [.text] BltShader::GetShaderMemSize() const 00000000000bdd54 long 0e SECT 01 0000 [.text] BltShader::GetRoundedShaderMemSize() const 00000000000cb12a long 0e SECT 01 0000 [.text] SiBltComputeShader::~SiBltComputeShader() 00000000000cb134 long 0e SECT 01 0000 [.text] SiBltComputeShader::~SiBltComputeShader() 00000000000cb150 long 0e SECT 01 0000 [.text] BltShader::GetShaderMemSize() const 00000000000cb15a long 0e SECT 01 0000 [.text] BltShader::GetRoundedShaderMemSize() const 00000000000cb164 long 0e SECT 01 0000 [.text] SiBltVertexShader::~SiBltVertexShader() 00000000000cb16e long 0e SECT 01 0000 [.text] SiBltVertexShader::~SiBltVertexShader() 00000000000d086c long 0e SECT 01 0000 [.text] AddrLib::HwlGetTileIndex(_ADDR_GET_TILEINDEX_INPUT const*, _ADDR_GET_TILEINDEX_OUTPUT*) const 00000000000d0878 long 0e SECT 01 0000 [.text] AddrLib::HwlComputeDccInfo(_ADDR_COMPUTE_DCCINFO_INPUT const*, _ADDR_COMPUTE_DCCINFO_OUTPUT*) const 00000000000d0884 long 0e SECT 01 0000 [.text] AddrLib::HwlComputeCmaskAddrFromCoord(_ADDR_COMPUTE_CMASK_ADDRFROMCOORD_INPUT const*, _ADDR_COMPUTE_CMASK_ADDRFROMCOORD_OUTPUT*) const 00000000000d0890 long 0e SECT 01 0000 [.text] AddrLib::HwlOverrideTileMode(_ADDR_COMPUTE_SURFACE_INFO_INPUT const*, _AddrTileMode*, _AddrTileType*) const 00000000000d0898 long 0e SECT 01 0000 [.text] AddrLib::HwlPadDimensions(_AddrTileMode, unsigned int, _ADDR_SURFACE_FLAGS, unsigned int, _ADDR_TILEINFO*, unsigned int, unsigned int, unsigned int*, unsigned int, unsigned int*, unsigned int, unsigned int*, unsigned int) const 00000000000d089e long 0e SECT 01 0000 [.text] AddrLib::HwlComputeMacroModeIndex(int, _ADDR_SURFACE_FLAGS, unsigned int, unsigned int, _ADDR_TILEINFO*, _AddrTileMode*, _AddrTileType*) const 00000000000d3428 long 0e SECT 01 0000 [.text] EgBasedAddrLib::HwlGetMaxCmaskBlockMax() const 00000000000d3434 long 0e SECT 01 0000 [.text] AddrLib::HwlGetTileIndex(_ADDR_GET_TILEINDEX_INPUT const*, _ADDR_GET_TILEINDEX_OUTPUT*) const 00000000000d3440 long 0e SECT 01 0000 [.text] AddrLib::HwlComputeDccInfo(_ADDR_COMPUTE_DCCINFO_INPUT const*, _ADDR_COMPUTE_DCCINFO_OUTPUT*) const 00000000000d344c long 0e SECT 01 0000 [.text] AddrLib::HwlComputeCmaskAddrFromCoord(_ADDR_COMPUTE_CMASK_ADDRFROMCOORD_INPUT const*, _ADDR_COMPUTE_CMASK_ADDRFROMCOORD_OUTPUT*) const 00000000000d3458 long 0e SECT 01 0000 [.text] AddrLib::HwlOverrideTileMode(_ADDR_COMPUTE_SURFACE_INFO_INPUT const*, _AddrTileMode*, _AddrTileType*) const 00000000000d3460 long 0e SECT 01 0000 [.text] AddrLib::HwlPadDimensions(_AddrTileMode, unsigned int, _ADDR_SURFACE_FLAGS, unsigned int, _ADDR_TILEINFO*, unsigned int, unsigned int, unsigned int*, unsigned int, unsigned int*, unsigned int, unsigned int*, unsigned int) const 00000000000d3466 long 0e SECT 01 0000 [.text] AddrLib::HwlComputeMacroModeIndex(int, _ADDR_SURFACE_FLAGS, unsigned int, unsigned int, _ADDR_TILEINFO*, _AddrTileMode*, _AddrTileType*) const 00000000000d3472 long 0e SECT 01 0000 [.text] R800AddrLib::HwlPreAdjustBank(unsigned int, unsigned int, _ADDR_TILEINFO*) const 00000000000d347a long 0e SECT 01 0000 [.text] EgBasedAddrLib::HwlPostCheckTileIndex(_ADDR_TILEINFO const*, _AddrTileMode, _AddrTileType, int) const 00000000000d3486 long 0e SECT 01 0000 [.text] EgBasedAddrLib::HwlFmaskPreThunkSurfInfo(_ADDR_COMPUTE_FMASK_INFO_INPUT const*, _ADDR_COMPUTE_FMASK_INFO_OUTPUT const*, _ADDR_COMPUTE_SURFACE_INFO_INPUT*, _ADDR_COMPUTE_SURFACE_INFO_OUTPUT*) const 00000000000d348c long 0e SECT 01 0000 [.text] EgBasedAddrLib::HwlFmaskPostThunkSurfInfo(_ADDR_COMPUTE_SURFACE_INFO_OUTPUT const*, _ADDR_COMPUTE_FMASK_INFO_OUTPUT*) const 00000000000d3492 long 0e SECT 01 0000 [.text] EgBasedAddrLib::HwlStereoCheckRightOffsetPadding() const 00000000000d59a0 long 0e SECT 01 0000 [.text] EgBasedAddrLib::HwlGetMaxCmaskBlockMax() const 00000000000d59ac long 0e SECT 01 0000 [.text] AddrLib::HwlComputeDccInfo(_ADDR_COMPUTE_DCCINFO_INPUT const*, _ADDR_COMPUTE_DCCINFO_OUTPUT*) const 00000000000d59b8 long 0e SECT 01 0000 [.text] AddrLib::HwlComputeCmaskAddrFromCoord(_ADDR_COMPUTE_CMASK_ADDRFROMCOORD_INPUT const*, _ADDR_COMPUTE_CMASK_ADDRFROMCOORD_OUTPUT*) const 00000000000d59c4 long 0e SECT 01 0000 [.text] AddrLib::HwlPadDimensions(_AddrTileMode, unsigned int, _ADDR_SURFACE_FLAGS, unsigned int, _ADDR_TILEINFO*, unsigned int, unsigned int, unsigned int*, unsigned int, unsigned int*, unsigned int, unsigned int*, unsigned int) const 00000000000d59ca long 0e SECT 01 0000 [.text] AddrLib::HwlComputeMacroModeIndex(int, _ADDR_SURFACE_FLAGS, unsigned int, unsigned int, _ADDR_TILEINFO*, _AddrTileMode*, _AddrTileType*) const 00000000000d59d6 long 0e SECT 01 0000 [.text] SIAddrLib::HwlSanityCheckMacroTiled(_ADDR_TILEINFO*) const 00000000000d59e2 long 0e SECT 01 0000 [.text] EgBasedAddrLib::HwlStereoCheckRightOffsetPadding() const 00000000000d59ea long 0e SECT 01 0000 [.text] SIAddrLib::HwlReduceBankWidthHeight(unsigned int, unsigned int, _ADDR_SURFACE_FLAGS, unsigned int, unsigned int, unsigned int, _ADDR_TILEINFO*) const 00000000000d6e41 long 0e SECT 01 0000 [.text] AddrInsertBits(unsigned long long, unsigned long long, unsigned int, unsigned int) 00000000000d704a long 0e SECT 01 0000 [.text] EgBasedAddrLib::HwlGetMaxCmaskBlockMax() const 00000000000d7056 long 0e SECT 01 0000 [.text] SIAddrLib::HwlSanityCheckMacroTiled(_ADDR_TILEINFO*) const 00000000000d7062 long 0e SECT 01 0000 [.text] SIAddrLib::HwlReduceBankWidthHeight(unsigned int, unsigned int, _ADDR_SURFACE_FLAGS, unsigned int, unsigned int, unsigned int, _ADDR_TILEINFO*) const 00000000000da9a8 long 0e SECT 01 0000 [.text] EgBasedAddrLib::HwlGetMaxCmaskBlockMax() const 00000000000da9b4 long 0e SECT 01 0000 [.text] AddrLib::HwlGetTileIndex(_ADDR_GET_TILEINDEX_INPUT const*, _ADDR_GET_TILEINDEX_OUTPUT*) const 00000000000da9c0 long 0e SECT 01 0000 [.text] AddrLib::HwlComputeDccInfo(_ADDR_COMPUTE_DCCINFO_INPUT const*, _ADDR_COMPUTE_DCCINFO_OUTPUT*) const 00000000000da9cc long 0e SECT 01 0000 [.text] AddrLib::HwlComputeCmaskAddrFromCoord(_ADDR_COMPUTE_CMASK_ADDRFROMCOORD_INPUT const*, _ADDR_COMPUTE_CMASK_ADDRFROMCOORD_OUTPUT*) const 00000000000da9d8 long 0e SECT 01 0000 [.text] AddrLib::HwlOverrideTileMode(_ADDR_COMPUTE_SURFACE_INFO_INPUT const*, _AddrTileMode*, _AddrTileType*) const 00000000000da9e0 long 0e SECT 01 0000 [.text] AddrLib::HwlPadDimensions(_AddrTileMode, unsigned int, _ADDR_SURFACE_FLAGS, unsigned int, _ADDR_TILEINFO*, unsigned int, unsigned int, unsigned int*, unsigned int, unsigned int*, unsigned int, unsigned int*, unsigned int) const 00000000000da9e6 long 0e SECT 01 0000 [.text] AddrLib::HwlComputeMacroModeIndex(int, _ADDR_SURFACE_FLAGS, unsigned int, unsigned int, _ADDR_TILEINFO*, _AddrTileMode*, _AddrTileType*) const 00000000000da9f2 long 0e SECT 01 0000 [.text] EgBasedAddrLib::HwlPostCheckTileIndex(_ADDR_TILEINFO const*, _AddrTileMode, _AddrTileType, int) const 00000000000da9fe long 0e SECT 01 0000 [.text] EgBasedAddrLib::HwlFmaskPreThunkSurfInfo(_ADDR_COMPUTE_FMASK_INFO_INPUT const*, _ADDR_COMPUTE_FMASK_INFO_OUTPUT const*, _ADDR_COMPUTE_SURFACE_INFO_INPUT*, _ADDR_COMPUTE_SURFACE_INFO_OUTPUT*) const 00000000000daa04 long 0e SECT 01 0000 [.text] EgBasedAddrLib::HwlFmaskPostThunkSurfInfo(_ADDR_COMPUTE_SURFACE_INFO_OUTPUT const*, _ADDR_COMPUTE_FMASK_INFO_OUTPUT*) const 00000000000daa0a long 0e SECT 01 0000 [.text] EgBasedAddrLib::HwlStereoCheckRightOffsetPadding() const 00000000000db3bb long 0e SECT 01 0000 [.text] _should_vbios_post 00000000000db405 long 0e SECT 01 0000 [.text] _post_vbios 00000000000dbe24 long 0e SECT 01 0000 [.text] _get_atom_bios_string 00000000000dca1f long 0e SECT 01 0000 [.text] _Bonaire_RestoreAdapterCfgRegisters 00000000000dca9b long 0e SECT 01 0000 [.text] _Bonaire_GetPcieLinkSpeedSupport 00000000000dcc33 long 0e SECT 01 0000 [.text] _Bonair_CheckPcieLinkUpconfigSupport 00000000000dccf1 long 0e SECT 01 0000 [.text] _Bonaire_PCIELane_Switch 00000000000dcda0 long 0e SECT 01 0000 [.text] _Bonaire_UpdateSwConstantForHwConfig 00000000000dce34 long 0e SECT 01 0000 [.text] _Bonaire_CheckMemoryConfiguration 00000000000dce99 long 0e SECT 01 0000 [.text] _Bonaire_SetupCgReferenceClock 00000000000dcec1 long 0e SECT 01 0000 [.text] _Bonaire_GetGbTileMode 00000000000dcef4 long 0e SECT 01 0000 [.text] _Bonaire_GetGbMacroTileMode 00000000000dcf11 long 0e SECT 01 0000 [.text] _Bonaire_EnableCpInterrupt 00000000000dcf4a long 0e SECT 01 0000 [.text] _Bonaire_DisableCpInterrupt 00000000000dcf83 long 0e SECT 01 0000 [.text] _Bonaire_DisableCpIdleInterrupt 00000000000dcfbc long 0e SECT 01 0000 [.text] _Bonaire_ResetRlc 00000000000dd017 long 0e SECT 01 0000 [.text] _Bonaire_UpdateGfxClockGating 00000000000dd0ed long 0e SECT 01 0000 [.text] _Bonaire_UpdateSystemClockGating 00000000000dd98a long 0e SECT 01 0000 [.text] _Bonaire_UpdateMultimediaClockGating 00000000000ddab8 long 0e SECT 01 0000 [.text] _Bonaire_UpdateVceClockGating 00000000000ddb53 long 0e SECT 01 0000 [.text] _Bonaire_UpdateCoarseGrainClockGating 00000000000ddcd2 long 0e SECT 01 0000 [.text] _Bonaire_UpdateMediumGrainClockGating 00000000000ddf60 long 0e SECT 01 0000 [.text] _Bonaire_DisableUvdMediumGrainClockGating 00000000000ddfaa long 0e SECT 01 0000 [.text] _Bonaire_EnableUvdMediumGrainClockGating 00000000000ddff7 long 0e SECT 01 0000 [.text] _Bonaire_UpdateXdmaSclkGating 00000000000de071 long 0e SECT 01 0000 [.text] _Bonaire_InitNonsurfAperture 00000000000de0a4 long 0e SECT 01 0000 [.text] _Bonaire_ProgramPcieGen3 00000000000de454 long 0e SECT 01 0000 [.text] _Bonaire_InitUvdClocks 00000000000de57e long 0e SECT 01 0000 [.text] _Bonaire_InitVceClocks 00000000000de732 long 0e SECT 01 0000 [.text] _Bonaire_InitAcpClocks 00000000000de7ef long 0e SECT 01 0000 [.text] _Bonaire_InitSamuClocks 00000000000de8bb long 0e SECT 01 0000 [.text] _Bonaire_CheckAcpHarvested 00000000000de922 long 0e SECT 01 0000 [.text] _Bonaire_LoadUcode 00000000000dea05 long 0e SECT 01 0000 [.text] _Bonaire_InitCSBHeader 00000000000dea64 long 0e SECT 01 0000 [.text] _Bonaire_InitMasterPacketHeader 00000000000deac3 long 0e SECT 01 0000 [.text] _Bonaire_MicroEngineControlCp 00000000000dee3c long 0e SECT 01 0000 [.text] _Bonaire_MicroEngineControlMec 00000000000df394 long 0e SECT 01 0000 [.text] _Bonaire_MicroEngineControlSdma 00000000000df95c long 0e SECT 01 0000 [.text] _Bonaire_QueryCuReservationRegisterInfo 00000000000df978 long 0e SECT 01 0000 [.text] _Bonaire_UpdateAsicConfigRegisters 00000000000dfe9c long 0e SECT 01 0000 [.text] _Bonaire_CsQueryRegWriteList 00000000000dfeae long 0e SECT 01 0000 [.text] _Bonaire_CsQueryMetaDataRegList 00000000000dfec0 long 0e SECT 01 0000 [.text] _Bonaire_AsicState 00000000000dff40 long 0e SECT 01 0000 [.text] _Bonaire_WaitForIdle 00000000000dffa0 long 0e SECT 01 0000 [.text] _Bonaire_WaitForIdleGui 00000000000e000d long 0e SECT 01 0000 [.text] _Bonaire_IsDisplayBlockHang 00000000000e0182 long 0e SECT 01 0000 [.text] _Bonaire_IsGuiIdle 00000000000e01e1 long 0e SECT 01 0000 [.text] _Bonaire_WaitForIdleSdma 00000000000e0276 long 0e SECT 01 0000 [.text] _Bonaire_WaitForIdleCp 00000000000e02e3 long 0e SECT 01 0000 [.text] _Bonaire_WaitForIdleVce 00000000000e0358 long 0e SECT 01 0000 [.text] _Bonaire_WaitForIdleUvd 00000000000e03cd long 0e SECT 01 0000 [.text] _Bonaire_SelectSeSh 00000000000e041b long 0e SECT 01 0000 [.text] _Bonaire_CheckAsicBlockState 00000000000e053f long 0e SECT 01 0000 [.text] _Bonaire_TdrBegin 00000000000e0832 long 0e SECT 01 0000 [.text] _Bonaire_MonitorEngineInternalState 00000000000e097e long 0e SECT 01 0000 [.text] _Bonaire_MonitorPerformanceCounter 00000000000e0ab1 long 0e SECT 01 0000 [.text] _Bonaire_LiteResetEngine 00000000000e0c40 long 0e SECT 01 0000 [.text] _Bonaire_IsNonEngineChipHung 00000000000e0c7b long 0e SECT 01 0000 [.text] _Bonaire_EncodeBlocksForReset 00000000000e0d04 long 0e SECT 01 0000 [.text] _Bonaire_SoftResetMethod 00000000000e0e95 long 0e SECT 01 0000 [.text] _Bonaire_DisableFbMemAccess 00000000000e10e2 long 0e SECT 01 0000 [.text] _Bonaire_EnableFbMemAccess 00000000000e12a9 long 0e SECT 01 0000 [.text] _Bonaire_PostLiteReset 00000000000e1383 long 0e SECT 01 0000 [.text] _Bonaire_PreLiteReset 00000000000e1389 long 0e SECT 01 0000 [.text] _Bonaire_UvdInit 00000000000e1897 long 0e SECT 01 0000 [.text] _Bonaire_UvdSuspend 00000000000e1ae0 long 0e SECT 01 0000 [.text] _Bonaire_SetupUvdCacheWindows 00000000000e1b8f long 0e SECT 01 0000 [.text] _Bonaire_VceInit 00000000000e1ef8 long 0e SECT 01 0000 [.text] _Bonaire_VceSuspend 00000000000e20c0 long 0e SECT 01 0000 [.text] _Bonaire_SamuInit 00000000000e258e long 0e SECT 01 0000 [.text] _Bonaire_SamuSuspend 00000000000e25e0 long 0e SECT 01 0000 [.text] _Bonaire_SamuSetClk 00000000000e270a long 0e SECT 01 0000 [.text] _Bonaire_SamuCheckDebugBoard 00000000000e273a long 0e SECT 01 0000 [.text] _Bonaire_SamuSrbmSoftReset 00000000000e2749 long 0e SECT 01 0000 [.text] _Bonaire_RaiseSamuResetInterrupt 00000000000e27e7 long 0e SECT 01 0000 [.text] _Bonaire_UpdateSamuSwClockGating 00000000000e2844 long 0e SECT 01 0000 [.text] _Bonaire_HdpHideReservedBlock 00000000000e28cc long 0e SECT 01 0000 [.text] _Bonaire_HdpUnhideReservedBlock 00000000000e29f5 long 0e SECT 01 0000 [.text] _Bonaire_ExecuteDmaCopy 00000000000e2abb long 0e SECT 01 0000 [.text] _Bonaire_ClearFbMemory 00000000000e2bf2 long 0e SECT 01 0000 [.text] _Bonaire_CfSetPeerApertureDefault 00000000000e2d3a long 0e SECT 01 0000 [.text] _Bonaire_CfEnableMailbox 00000000000e2db8 long 0e SECT 01 0000 [.text] _Bonaire_LocalHaltRlc 00000000000e2f35 long 0e SECT 01 0000 [.text] _Bonaire_ClockGatingControl 00000000000e2fa6 long 0e SECT 01 0000 [.text] _Bonaire_EnableLBPW 00000000000e2fe1 long 0e SECT 01 0000 [.text] _Bonaire_micro_engine_control 00000000000e303a long 0e SECT 01 0000 [.text] _Bonaire_get_indirect_register_smc 00000000000e3052 long 0e SECT 01 0000 [.text] _Bonaire_set_indirect_register_smc 00000000000e306d long 0e SECT 01 0000 [.text] _Bonaire_get_indirect_register_pcie 00000000000e3085 long 0e SECT 01 0000 [.text] _Bonaire_set_indirect_register_pcie 00000000000e30a0 long 0e SECT 01 0000 [.text] _bonaire_get_indirect_register_sam_sab 00000000000e30b8 long 0e SECT 01 0000 [.text] _bonaire_set_indirect_register_sam_sab 00000000000e30d3 long 0e SECT 01 0000 [.text] _bonaire_get_indirect_register_sam 00000000000e30eb long 0e SECT 01 0000 [.text] _bonaire_set_indirect_register_sam 00000000000e3106 long 0e SECT 01 0000 [.text] _Bonaire_ReadMmPciConfigRegister 00000000000e315d long 0e SECT 01 0000 [.text] _Bonaire_WriteMmPciConfigRegister 00000000000e31b8 long 0e SECT 01 0000 [.text] _Bonaire_GpioReadPin 00000000000e3250 long 0e SECT 01 0000 [.text] _Bonaire_GetPaScRasterConfig 00000000000e32a3 long 0e SECT 01 0000 [.text] _Bonaire_SwitchMcConfigContext 00000000000e3375 long 0e SECT 01 0000 [.text] _bonaire_perform_grbm_soft_reset 00000000000e33e7 long 0e SECT 01 0000 [.text] _bonaire_perform_srbm_soft_reset 00000000000e3632 long 0e SECT 01 0000 [.text] _bonaire_halt_rlc 00000000000e376c long 0e SECT 01 0000 [.text] _bonaire_access_doorbell_aperture 00000000000e3822 long 0e SECT 01 0000 [.text] _bonaire_set_uvd_dynamic_clock_mode 00000000000e38a9 long 0e SECT 01 0000 [.text] _bonaire_set_vce_sw_clock_gating 00000000000e3999 long 0e SECT 01 0000 [.text] _bonaire_set_vce_dyn_clock_gating 00000000000e3a53 long 0e SECT 01 0000 [.text] _bonaire_init_vce_clock_gating 00000000000e3ae7 long 0e SECT 01 0000 [.text] _bonaire_program_samu_sw_clock_gating 00000000000e3b6b long 0e SECT 01 0000 [.text] _bonaire_local_update_rlc 00000000000e3ba0 long 0e SECT 01 0000 [.text] _Bonaire_IsSAMUHung 00000000000e3bd1 long 0e SECT 01 0000 [.text] _bonaire_load_ucode_via_port_register 00000000000e3c49 long 0e SECT 01 0000 [.text] _bonaire_set_uvd_clock 00000000000e3d50 long 0e SECT 01 0000 [.text] _bonaire_link_equalization_callback 00000000000e4014 long 0e SECT 01 0000 [.text] _bonaire_update_register_golden_settings 00000000000e42df long 0e SECT 01 0000 [.text] _bonaire_init_ucode_buffer 00000000000e4324 long 0e SECT 01 0000 [.text] _bonaire_init_ECC 00000000000e4595 long 0e SECT 01 0000 [.text] _bonaire_init_power_gating 00000000000e45e1 long 0e SECT 01 0000 [.text] _bonaire_init_LBPW 00000000000e46a9 long 0e SECT 01 0000 [.text] _bonaire_init_clock_gating 00000000000e4771 long 0e SECT 01 0000 [.text] _bonaire_init_rlc 00000000000e4864 long 0e SECT 01 0000 [.text] _bonaire_unhalt_rlc 00000000000e48ab long 0e SECT 01 0000 [.text] _bonaire_program_pcie_link_width 00000000000e48b6 long 0e SECT 01 0000 [.text] _bonaire_program_aspm 00000000000ea4cf long 0e SECT 01 0000 [.text] _get_master_offset_to_caps 00000000000ea60a long 0e SECT 01 0000 [.text] _check_pcie_cap 00000000000eba0f long 0e SECT 01 0000 [.text] _check_register_state_in_group 00000000000eceb2 long 0e SECT 01 0000 [.text] _CopyMcToMcViaCpDma 00000000000ed541 long 0e SECT 01 0000 [.text] _check_next_p2p 00000000000ed6cf long 0e SECT 01 0000 [.text] _check_mvpu_switch_port_info 00000000000ed83b long 0e SECT 01 0000 [.text] _set_PCI_to_PCI_bridge_info 00000000000ed8a2 long 0e SECT 01 0000 [.text] _get_asic_caps_set_from_table 00000000000eefe0 long 0e SECT 01 0000 [.text] _check_CF_ID_info 00000000000ef2fd long 0e SECT 01 0000 [.text] _collect_crossfire_info 00000000000f125c long 0e SECT 01 0000 [.text] _reserve_fb_for_rlc 00000000000f1605 long 0e SECT 01 0000 [.text] _check_and_reserve_fb_for_samu 00000000000f169a long 0e SECT 01 0000 [.text] _reserve_fb_for_micro_engine 00000000000f1710 long 0e SECT 01 0000 [.text] _add_block_from_fb_high 00000000000f1b36 long 0e SECT 01 0000 [.text] _get_rlc_buffer_info 00000000000f1ead long 0e SECT 01 0000 [.text] _get_clear_state_buffer_size_for_llano_trinity 00000000000f24eb long 0e SECT 01 0000 [.text] _get_next_border 00000000000f2536 long 0e SECT 01 0000 [.text] _add_new_block 00000000000f268a long 0e SECT 01 0000 [.text] _overlap_new_block 00000000000f46b5 long 0e SECT 01 0000 [.text] _iri_release 00000000000f46dd long 0e SECT 01 0000 [.text] _iri_call 00000000000f4ad9 long 0e SECT 01 0000 [.text] _get_p2p_flush_command 00000000000f4b14 long 0e SECT 01 0000 [.text] _setup_uvd_clock 00000000000f4b4a long 0e SECT 01 0000 [.text] _switch_pcie_lane 00000000000f4b85 long 0e SECT 01 0000 [.text] _query_aspm_inactivity_cap 00000000000f4bbb long 0e SECT 01 0000 [.text] _switch_ultra_low_power_state 00000000000f4cb7 long 0e SECT 01 0000 [.text] _query_adapter_info 00000000000f4d13 long 0e SECT 01 0000 [.text] _query_cf_memory_client_group 00000000000f4d42 long 0e SECT 01 0000 [.text] _get_cf_p2p_flush_command_ex 00000000000f4d7d long 0e SECT 01 0000 [.text] _query_system_info 00000000000f4dd6 long 0e SECT 01 0000 [.text] _power_control 00000000000f4e21 long 0e SECT 01 0000 [.text] _setup_vce_clock 00000000000f4e57 long 0e SECT 01 0000 [.text] _query_mc_address_range 00000000000f4e88 long 0e SECT 01 0000 [.text] _micro_engine_control 00000000000f4eab long 0e SECT 01 0000 [.text] _setup_samu_clock 00000000000f4ed8 long 0e SECT 01 0000 [.text] _setup_acp_clock 00000000000f4f12 long 0e SECT 01 0000 [.text] _event_notification 00000000000f4f34 long 0e SECT 01 0000 [.text] _query_micro_code_info 00000000000f4f67 long 0e SECT 01 0000 [.text] _get_firmware_image 00000000000f5120 long 0e SECT 01 0000 [.text] _cs_init_meta_data_list_reg_value 00000000000f51a2 long 0e SECT 01 0000 [.text] _cs_init_meta_data_list_reg_number 00000000000f5224 long 0e SECT 01 0000 [.text] _set_gen2_tls 00000000000f5270 long 0e SECT 01 0000 [.text] _fill_meta_data 00000000000f5678 long 0e SECT 01 0000 [.text] _get_powerplay_IRI 00000000000f5d2f long 0e SECT 01 0000 [.text] _write_pci_cfg_registers 00000000000f6bbd long 0e SECT 01 0000 [.text] _wait_for_multiobj_condition 00000000000f748b long 0e SECT 01 0000 [.text] _acpi_control_method_function_ext 00000000000f7f77 long 0e SECT 01 0000 [.text] _get_max_MC_address_space 00000000000f8932 long 0e SECT 01 0000 [.text] _adjust_fb_size 00000000000f89a1 long 0e SECT 01 0000 [.text] _get_available_range_from_top 00000000000f89ff long 0e SECT 01 0000 [.text] _get_available_range_from_base 00000000000f9268 long 0e SECT 01 0000 [.text] _perform_power_control 00000000000f9a44 long 0e SECT 01 0000 [.text] _perform_enable_LBPW 00000000000fa301 long 0e SECT 01 0000 [.text] _update_gfx_medium_grain_power_gating 00000000000fa5d8 long 0e SECT 01 0000 [.text] _update_gfx_coarse_grain_power_gating 00000000000fa68c long 0e SECT 01 0000 [.text] _update_gmc_power_gating_mode 00000000000fa7f4 long 0e SECT 01 0000 [.text] _update_drmdma_power_gating_mode 00000000000fa87d long 0e SECT 01 0000 [.text] _update_gfx_clock_gating 00000000000faa47 long 0e SECT 01 0000 [.text] _update_mc_light_sleep_mode 00000000000facff long 0e SECT 01 0000 [.text] _update_mc_medium_grain_clock_gating_mode 00000000000fafb7 long 0e SECT 01 0000 [.text] _update_drmdma_medium_grain_clock_gating_mode 00000000000fb150 long 0e SECT 01 0000 [.text] _update_bif_medium_grain_light_sleep_mode 00000000000fb1c1 long 0e SECT 01 0000 [.text] _update_uvd_medium_grain_clock_gating_mode 00000000000fb2a6 long 0e SECT 01 0000 [.text] _update_spu_medium_grain_clock_gating_mode 00000000000fb32f long 0e SECT 01 0000 [.text] _update_xdma_sclk_gating_mode 00000000000fb3a7 long 0e SECT 01 0000 [.text] _update_xdma_light_sleep_mode 00000000000fb41f long 0e SECT 01 0000 [.text] _update_hdp_medium_grain_clock_gating_mode 00000000000fb497 long 0e SECT 01 0000 [.text] _update_hdp_light_sleep_mode 00000000000fb506 long 0e SECT 01 0000 [.text] _update_drm_light_sleep_mode 00000000000fb575 long 0e SECT 01 0000 [.text] _disable_uvd_power_gating 00000000000fb6b3 long 0e SECT 01 0000 [.text] _enable_uvd_power_gating 00000000000fb8fd long 0e SECT 01 0000 [.text] _disable_vce_power_gating 00000000000fba34 long 0e SECT 01 0000 [.text] _enable_vce_power_gating 00000000000fbca4 long 0e SECT 01 0000 [.text] _update_coarse_grain_clock_gating 00000000000fbf04 long 0e SECT 01 0000 [.text] _update_medium_grain_clock_gating 00000000000fc0a4 long 0e SECT 01 0000 [.text] _local_halt_rlc 00000000000fc17b long 0e SECT 01 0000 [.text] _local_update_rlc 00000000000fc1b0 long 0e SECT 01 0000 [.text] _disable_gfx_static_medium_grain_power_gating 00000000000fc1e6 long 0e SECT 01 0000 [.text] _disable_gfx_dyn_medium_grain_power_gating 00000000000fc46a long 0e SECT 01 0000 [.text] _Carrizo_EnableSckSlowDownOnPowerUp 00000000000fc4b0 long 0e SECT 01 0000 [.text] _Carrizo_EnableSckSlowDownOnPowerDown 00000000000fc4f6 long 0e SECT 01 0000 [.text] _Carrizo_EnableCpPowerGating 00000000000fc53c long 0e SECT 01 0000 [.text] _Carrizo_UpdateGfxPowerGating 00000000000fc8c5 long 0e SECT 01 0000 [.text] _Carrizo_SetupASIC 00000000000fc8db long 0e SECT 01 0000 [.text] _Carrizo_SetupCgReferenceClock 00000000000fc8fd long 0e SECT 01 0000 [.text] _Carrizo_CheckDsmuSupport 00000000000fc903 long 0e SECT 01 0000 [.text] _Carrizo_UpdateSwConstantForHwConfig 00000000000fc9fd long 0e SECT 01 0000 [.text] _Carrizo_ZeroFbConfigAndSize 00000000000fca8e long 0e SECT 01 0000 [.text] _Carrizo_FillMetaData 00000000000fcaea long 0e SECT 01 0000 [.text] _Carrizo_UpdateCoarseGrainClockGating 00000000000fcc3c long 0e SECT 01 0000 [.text] _Carrizo_UpdateMediumGrainClockGating 00000000000fce8a long 0e SECT 01 0000 [.text] _Carrizo_PowerGatingControl 00000000000fcea7 long 0e SECT 01 0000 [.text] _Carrizo_CheckAcpHarvested 00000000000fcf0e long 0e SECT 01 0000 [.text] _Carrizo_FormatSmuDramDataBuffer 00000000000fd00f long 0e SECT 01 0000 [.text] _carrizo_wait_rlc_serdes_master_idle 00000000000fd11d long 0e SECT 01 0000 [.text] _carrizo_send_serdes_cmd 00000000000fd1a1 long 0e SECT 01 0000 [.text] _carrizo_register_update_for_asic_sku 00000000000fd660 long 0e SECT 01 0000 [.text] _carrizo_init_ucode_buffer 00000000000fd6b0 long 0e SECT 01 0000 [.text] _carrizo_halt_rlc 00000000000fd6ed long 0e SECT 01 0000 [.text] _carrizo_reset_rlc 00000000000fd6ff long 0e SECT 01 0000 [.text] _carrizo_init_power_gating 00000000000fd77f long 0e SECT 01 0000 [.text] _carrizo_init_LBPW 00000000000fd833 long 0e SECT 01 0000 [.text] _carrizo_init_clock_gating 00000000000fd886 long 0e SECT 01 0000 [.text] _carrizo_init_nonsurf_aperture 00000000000fd891 long 0e SECT 01 0000 [.text] _carrizo_init_uvd_clocks 00000000000fd89c long 0e SECT 01 0000 [.text] _carrizo_init_vce_clocks 00000000000fd8a7 long 0e SECT 01 0000 [.text] _carrizo_init_acp_clocks 00000000000fd8b2 long 0e SECT 01 0000 [.text] _Carrizo_DisableGfxDynamicMGPowerGating 00000000000fd9ec long 0e SECT 01 0000 [.text] _select_se 00000000000fe453 long 0e SECT 01 0000 [.text] _set_gb_addr_config_registers 00000000000fe4fe long 0e SECT 01 0000 [.text] _Cayman_halt_micro_engine 00000000000fe9f7 long 0e SECT 01 0000 [.text] _Cayman_set_clk_bypass_mode 00000000000feab9 long 0e SECT 01 0000 [.text] _Cayman_disable_FB_mem_access 00000000000fed6a long 0e SECT 01 0000 [.text] _Cayman_soft_reset_method 00000000000ff1b2 long 0e SECT 01 0000 [.text] _Cayman_encode_blocks_for_reset 00000000000ff34b long 0e SECT 01 0000 [.text] _Cayman_check_asic_block_state 00000000000ff660 long 0e SECT 01 0000 [.text] _enable_electrical_idle_detectors 00000000000ffd1e long 0e SECT 01 0000 [.text] _program_upll 00000000000fff3f long 0e SECT 01 0000 [.text] _select_upll_vclk_dclk 0000000000100033 long 0e SECT 01 0000 [.text] _set_uvd_dynamic_clock_mode 000000000010009b long 0e SECT 01 0000 [.text] _program_spread_spectrum 000000000010052d long 0e SECT 01 0000 [.text] _select_upll_bypass 0000000000100ce1 long 0e SECT 01 0000 [.text] _get_gb_addr_config_setting 0000000000100dfc long 0e SECT 01 0000 [.text] _setup_peer_aperture_mc_addr 0000000000100f75 long 0e SECT 01 0000 [.text] _setup_peer_system_bar 0000000000101953 long 0e SECT 01 0000 [.text] _reset_grbm_srbm 0000000000101a3a long 0e SECT 01 0000 [.text] _Cayman_WaitForVBlank 0000000000101ae9 long 0e SECT 01 0000 [.text] _Cayman_IsCounterMoving 0000000000101b3c long 0e SECT 01 0000 [.text] _Cayman_init_additional_registers 0000000000101b98 long 0e SECT 01 0000 [.text] _Cayman_init_shader_pipe_registers 0000000000101e11 long 0e SECT 01 0000 [.text] _Cayman_init_nonsurf_aperture 0000000000101e44 long 0e SECT 01 0000 [.text] _Cayman_init_LBPW 0000000000101e8a long 0e SECT 01 0000 [.text] _Cayman_init_RLC_legacy_mode 000000000010202d long 0e SECT 01 0000 [.text] _Cayman_program_PCIE_Gen2 000000000010230a long 0e SECT 01 0000 [.text] _Cayman_program_aspm 0000000000102603 long 0e SECT 01 0000 [.text] _init_uvd_clocks 000000000010278a long 0e SECT 01 0000 [.text] _init_uvd_internal_clock_gating 000000000010281c long 0e SECT 01 0000 [.text] _Cayman_enable_FB_mem_access 0000000000102c02 long 0e SECT 01 0000 [.text] _select_se 0000000000103c35 long 0e SECT 01 0000 [.text] _set_gb_addr_config_registers 0000000000103c8b long 0e SECT 01 0000 [.text] _Cypress_halt_micro_engine 0000000000103daf long 0e SECT 01 0000 [.text] _bif_soft_reset 000000000010407a long 0e SECT 01 0000 [.text] _asic_hot_reset 000000000010414b long 0e SECT 01 0000 [.text] _Cypress_set_clk_bypass_mode 000000000010420d long 0e SECT 01 0000 [.text] _Cypress_soft_reset_method 0000000000104738 long 0e SECT 01 0000 [.text] _Cypress_check_asic_block_state 00000000001049b5 long 0e SECT 01 0000 [.text] _enable_electrical_idle_detectors 000000000010511a long 0e SECT 01 0000 [.text] _program_upll 0000000000105350 long 0e SECT 01 0000 [.text] _select_upll_vclk_dclk 0000000000105444 long 0e SECT 01 0000 [.text] _set_uvd_clk_gating_branches 00000000001054ae long 0e SECT 01 0000 [.text] _set_uvd_dynamic_clock_mode 0000000000105521 long 0e SECT 01 0000 [.text] _program_spread_spectrum 00000000001059e6 long 0e SECT 01 0000 [.text] _select_upll_bypass 0000000000106131 long 0e SECT 01 0000 [.text] _get_gb_addr_config_setting 000000000010624c long 0e SECT 01 0000 [.text] _setup_peer_aperture_mc_addr 00000000001063c5 long 0e SECT 01 0000 [.text] _setup_peer_system_bar 0000000000106e23 long 0e SECT 01 0000 [.text] _Cypress_init_additional_registers 0000000000106ed6 long 0e SECT 01 0000 [.text] _Cypress_init_shader_pipe_registers 000000000010713d long 0e SECT 01 0000 [.text] _Cypress_init_nonsurf_aperture 0000000000107170 long 0e SECT 01 0000 [.text] _Cypress_init_RLC_legacy_mode 0000000000107288 long 0e SECT 01 0000 [.text] _Cypress_program_PCIE_Gen2 0000000000107634 long 0e SECT 01 0000 [.text] _Cypress_program_aspm 00000000001079c5 long 0e SECT 01 0000 [.text] _init_uvd_clocks 0000000000107b4c long 0e SECT 01 0000 [.text] _init_uvd_internal_clock_gating 0000000000107f6f long 0e SECT 01 0000 [.text] _set_uvd_clock 00000000001086cd long 0e SECT 01 0000 [.text] _force_vce_clock_on 0000000000108ed1 long 0e SECT 01 0000 [.text] _Godavari_FormatSmuDramDataBuffer 0000000000109587 long 0e SECT 01 0000 [.text] _find_smu_entry 0000000000109f2c long 0e SECT 01 0000 [.text] _Iceland_SetupASIC 0000000000109f42 long 0e SECT 01 0000 [.text] _Iceland_RestoreAdapterCfgRegisters 0000000000109fa8 long 0e SECT 01 0000 [.text] _Iceland_FindAsicRevID 0000000000109fca long 0e SECT 01 0000 [.text] _Iceland_UpdateSwConstantForHwConfig 000000000010a05e long 0e SECT 01 0000 [.text] _Iceland_CheckMemoryConfiguration 000000000010a0c3 long 0e SECT 01 0000 [.text] _Iceland_IsFlrSupported 000000000010a0fa long 0e SECT 01 0000 [.text] _Iceland_GetGbTileMode 000000000010a12d long 0e SECT 01 0000 [.text] _Iceland_GetGbMacroTileMode 000000000010a14b long 0e SECT 01 0000 [.text] _Iceland_EnableCpInterrupt 000000000010a184 long 0e SECT 01 0000 [.text] _Iceland_DisableCpInterrupt 000000000010a1bd long 0e SECT 01 0000 [.text] _Iceland_DisableCpIdleInterrupt 000000000010a1f6 long 0e SECT 01 0000 [.text] _Iceland_UpdateCoarseGrainClockGating 000000000010a44b long 0e SECT 01 0000 [.text] _Iceland_UpdateMediumGrainClockGating 000000000010a6c9 long 0e SECT 01 0000 [.text] _Iceland_UpdateXdmaSclkGating 000000000010a6cf long 0e SECT 01 0000 [.text] _Iceland_ZeroFbConfigAndSize 000000000010a704 long 0e SECT 01 0000 [.text] _Iceland_FormatSmuDramDataBuffer 000000000010a865 long 0e SECT 01 0000 [.text] _Iceland_InitCSBHeader 000000000010a8c4 long 0e SECT 01 0000 [.text] _Iceland_MicroEngineControlCp 000000000010ac38 long 0e SECT 01 0000 [.text] _Iceland_MicroEngineControlMec 000000000010b2f8 long 0e SECT 01 0000 [.text] _Iceland_MicroEngineControlSdma 000000000010b92c long 0e SECT 01 0000 [.text] _Iceland_LoadRlcUcode 000000000010ba20 long 0e SECT 01 0000 [.text] _Iceland_GetRlcSaveRestoreRegisterListInfo 000000000010ba6e long 0e SECT 01 0000 [.text] _Iceland_QueryCuReservationRegisterInfo 000000000010ba8a long 0e SECT 01 0000 [.text] _Iceland_AsicState 000000000010baee long 0e SECT 01 0000 [.text] _Iceland_GetHungBlocks 000000000010bde8 long 0e SECT 01 0000 [.text] _Iceland_TdrBegin 000000000010c0f2 long 0e SECT 01 0000 [.text] _Iceland_MonitorEngineInternalState 000000000010c1f3 long 0e SECT 01 0000 [.text] _Iceland_CheckAsicBlockState 000000000010c2ed long 0e SECT 01 0000 [.text] _Iceland_SoftResetMethod 000000000010c46d long 0e SECT 01 0000 [.text] _Iceland_FunctionLevelReset 000000000010c612 long 0e SECT 01 0000 [.text] _Iceland_PostLiteReset 000000000010c798 long 0e SECT 01 0000 [.text] _Iceland_PreLiteReset 000000000010caa0 long 0e SECT 01 0000 [.text] _Iceland_CfInitPeerAperture 000000000010cc32 long 0e SECT 01 0000 [.text] _Iceland_CfSetPeerApertureDefault 000000000010cd7a long 0e SECT 01 0000 [.text] _Iceland_CfCloseTemporaryMailBox 000000000010ce0c long 0e SECT 01 0000 [.text] _Iceland_CfEnableMailbox 000000000010ce8a long 0e SECT 01 0000 [.text] _Iceland_LocalHaltRlc 000000000010cf15 long 0e SECT 01 0000 [.text] _Iceland_PowerGatingControl 000000000010cf2b long 0e SECT 01 0000 [.text] _Iceland_EnableLBPW 000000000010cf66 long 0e SECT 01 0000 [.text] _Iceland_EnterRlcSafeMode 000000000010d05a long 0e SECT 01 0000 [.text] _Iceland_ExitRlcSafeMode 000000000010d107 long 0e SECT 01 0000 [.text] _Iceland_WaitForDmaEngineIdle 000000000010d190 long 0e SECT 01 0000 [.text] _Iceland_WaitForIdleGui 000000000010d2c0 long 0e SECT 01 0000 [.text] _iceland_perform_grbm_soft_reset 000000000010d332 long 0e SECT 01 0000 [.text] _iceland_perform_srbm_soft_reset 000000000010d3a4 long 0e SECT 01 0000 [.text] _iceland_halt_rlc 000000000010d3e1 long 0e SECT 01 0000 [.text] _iceland_wait_rlc_serdes_master_idle 000000000010d4ef long 0e SECT 01 0000 [.text] _Iceland_IsVCEHung 000000000010d55e long 0e SECT 01 0000 [.text] _iceland_send_serdes_cmd 000000000010d5e2 long 0e SECT 01 0000 [.text] _iceland_register_update_for_asic_sku 000000000010d6dc long 0e SECT 01 0000 [.text] _iceland_init_ucode_buffer 000000000010d72c long 0e SECT 01 0000 [.text] _iceland_init_ECC 000000000010d94c long 0e SECT 01 0000 [.text] _iceland_reset_rlc 000000000010d95e long 0e SECT 01 0000 [.text] _iceland_init_power_gating 000000000010d99f long 0e SECT 01 0000 [.text] _iceland_init_LBPW 000000000010da53 long 0e SECT 01 0000 [.text] _iceland_init_clock_gating 000000000010da96 long 0e SECT 01 0000 [.text] _iceland_init_nonsurf_aperture 000000000010daa1 long 0e SECT 01 0000 [.text] _iceland_program_PCIE_Gen3 000000000010daac long 0e SECT 01 0000 [.text] _iceland_program_pcie_link_width 000000000010dab7 long 0e SECT 01 0000 [.text] _iceland_program_aspm 000000000010dac2 long 0e SECT 01 0000 [.text] _iceland_restore_audio_enablement 000000000010fb0e long 0e SECT 01 0000 [.text] _CailCompareEngineReadWritePointers 0000000000110740 long 0e SECT 01 0000 [.text] _Spectre_EnableRlcChubHandshaking 0000000000110786 long 0e SECT 01 0000 [.text] _Spectre_EnableSckSlowDownOnPowerUp 00000000001107cc long 0e SECT 01 0000 [.text] _Spectre_EnableSckSlowDownOnPowerDown 0000000000110812 long 0e SECT 01 0000 [.text] _Spectre_EnableCpPowerGating 0000000000110858 long 0e SECT 01 0000 [.text] _Spectre_EnableGDSPowerGating 000000000011089e long 0e SECT 01 0000 [.text] _Spectre_UpdateGfxPowerGating 0000000000110b8a long 0e SECT 01 0000 [.text] _Spectre_EnterRlcSafeMode 0000000000110c73 long 0e SECT 01 0000 [.text] _Spectre_ExitRlcSafeMode 0000000000110e0a long 0e SECT 01 0000 [.text] _Spectre_SetupCgReferenceClock 0000000000110e2c long 0e SECT 01 0000 [.text] _Spectre_MemoryConfigAndSize 0000000000110e86 long 0e SECT 01 0000 [.text] _Spectre_GetIntegrateAsicFbMcBaseAddr 0000000000110ea0 long 0e SECT 01 0000 [.text] _Spectre_ReserveFbMcRange 0000000000110f3b long 0e SECT 01 0000 [.text] _Spectre_UpdateSwConstantForHwConfig 0000000000111035 long 0e SECT 01 0000 [.text] _Spectre_CheckDsmuSupport 0000000000111071 long 0e SECT 01 0000 [.text] _Spectre_GetRlcSaveRestoreRegisterListInfo 00000000001110bf long 0e SECT 01 0000 [.text] _Spectre_PowerGatingControl 00000000001110dc long 0e SECT 01 0000 [.text] _Spectre_CheckAcpHarvested 0000000000111143 long 0e SECT 01 0000 [.text] _Spectre_EventNotification 000000000011141c long 0e SECT 01 0000 [.text] _Spectre_DisableGfxStaticMGPowerGating 0000000000111452 long 0e SECT 01 0000 [.text] _Spectre_DisableGfxDynamicMGPowerGating 0000000000111802 long 0e SECT 01 0000 [.text] _set_uvd_clock 0000000000112597 long 0e SECT 01 0000 [.text] _disable_cp_interrupt 0000000000112615 long 0e SECT 01 0000 [.text] _enable_cp_interrupt 0000000000112956 long 0e SECT 01 0000 [.text] _wait_for_vce_idle 0000000000112afe long 0e SECT 01 0000 [.text] _select_se_sh 00000000001131d2 long 0e SECT 01 0000 [.text] _disable_FB_mem_access 0000000000113410 long 0e SECT 01 0000 [.text] _set_clk_bypass_mode 00000000001134f7 long 0e SECT 01 0000 [.text] _powerdown_spll 000000000011357f long 0e SECT 01 0000 [.text] _soft_reset_method 0000000000113fd4 long 0e SECT 01 0000 [.text] _check_asic_block_state 00000000001146a5 long 0e SECT 01 0000 [.text] _program_upll 00000000001148c6 long 0e SECT 01 0000 [.text] _select_upll_vclk_dclk 00000000001149f1 long 0e SECT 01 0000 [.text] _set_uvd_dynamic_clock_mode 0000000000114a59 long 0e SECT 01 0000 [.text] _program_spread_spectrum 0000000000114eb5 long 0e SECT 01 0000 [.text] _select_upll_bypass 0000000000115780 long 0e SECT 01 0000 [.text] _program_vcepll 00000000001159a1 long 0e SECT 01 0000 [.text] _select_vcepll_evclk_ecclk 0000000000115aa7 long 0e SECT 01 0000 [.text] _program_vcepll_spread_spectrum 0000000000115e01 long 0e SECT 01 0000 [.text] _select_vcepll_bypass 0000000000116378 long 0e SECT 01 0000 [.text] _Tahiti_SetupPeerDataAperture 0000000000116409 long 0e SECT 01 0000 [.text] _Tahiti_SetupPeerApertureMcAddr 000000000011659b long 0e SECT 01 0000 [.text] _Tahiti_SetupPeerSystemBar 0000000000116683 long 0e SECT 01 0000 [.text] _Tahiti_SetupP2pBarCfg 000000000011673d long 0e SECT 01 0000 [.text] _Tahiti_SetupMemoryClientGroup 0000000000117a4b long 0e SECT 01 0000 [.text] _Tahiti_CheckPcieLinkUpconfigSupport 0000000000117b09 long 0e SECT 01 0000 [.text] _Tahiti_CheckPcieAspmSupport 0000000000117b6f long 0e SECT 01 0000 [.text] _Tahiti_ProgramPcieLinkWidth 0000000000117bdf long 0e SECT 01 0000 [.text] _Tahiti_ZeroFbConfigAndSize 0000000000117c70 long 0e SECT 01 0000 [.text] _resync_peer_aperture_internal_state 0000000000117cc7 long 0e SECT 01 0000 [.text] _Tahiti_CfEnableMailbox 0000000000117fa0 long 0e SECT 01 0000 [.text] _Tahiti_GetPaScRasterConfig 000000000011801c long 0e SECT 01 0000 [.text] _init_additional_registers 000000000011807b long 0e SECT 01 0000 [.text] _update_register_golden_settings 00000000001185e3 long 0e SECT 01 0000 [.text] _init_ECC 0000000000118973 long 0e SECT 01 0000 [.text] _reset_rlc 00000000001189de long 0e SECT 01 0000 [.text] _init_power_gating 0000000000118a3d long 0e SECT 01 0000 [.text] _init_LBPW 0000000000118ac4 long 0e SECT 01 0000 [.text] _init_clock_gating 0000000000118b75 long 0e SECT 01 0000 [.text] _init_rlc 0000000000118bfb long 0e SECT 01 0000 [.text] _init_nonsurf_aperture 0000000000118c2e long 0e SECT 01 0000 [.text] _program_PCIE_Gen3 0000000000118e47 long 0e SECT 01 0000 [.text] _program_aspm 0000000000119491 long 0e SECT 01 0000 [.text] _init_uvd_clocks 0000000000119613 long 0e SECT 01 0000 [.text] _init_vce_clocks 0000000000119795 long 0e SECT 01 0000 [.text] _link_equalization_callback 0000000000119cc5 long 0e SECT 01 0000 [.text] _Tonga_SetupASIC 0000000000119cdb long 0e SECT 01 0000 [.text] _Tonga_IsDisplayBlockHang 0000000000119e87 long 0e SECT 01 0000 [.text] _Tonga_CheckAsicBlockState 0000000000119fed long 0e SECT 01 0000 [.text] _Tonga_DisableFbMemAccess 000000000011a22d long 0e SECT 01 0000 [.text] _Tonga_EnableFbMemAccess 000000000011a3f4 long 0e SECT 01 0000 [.text] _Tonga_ProgramAspm 000000000011a775 long 0e SECT 01 0000 [.text] _Tonga_MonitorEngineInternalState 000000000011a8ec long 0e SECT 01 0000 [.text] _Tonga_SoftResetMethod 000000000011aac9 long 0e SECT 01 0000 [.text] _Tonga_CheckAcpHarvested 000000000011ab41 long 0e SECT 01 0000 [.text] _Tonga_ZeroFbConfigAndSize 000000000011abd2 long 0e SECT 01 0000 [.text] _Tonga_GetFbMemorySize 000000000011ac30 long 0e SECT 01 0000 [.text] _Tonga_InitCSBHeader 000000000011ac70 long 0e SECT 01 0000 [.text] _Tonga_MicroEngineControlCp 000000000011b158 long 0e SECT 01 0000 [.text] _Tonga_MicroEngineControlMec 000000000011b858 long 0e SECT 01 0000 [.text] _Tonga_MicroEngineControlSdma 000000000011be88 long 0e SECT 01 0000 [.text] _Tonga_GetFbMcBaseAddress 000000000011bea2 long 0e SECT 01 0000 [.text] _Tonga_DoorbellApertureControl 000000000011bedf long 0e SECT 01 0000 [.text] _Tonga_UpdateGfxClockGating 000000000011c027 long 0e SECT 01 0000 [.text] _Tonga_UpdateSystemClockGating 000000000011c2e3 long 0e SECT 01 0000 [.text] _Tonga_UvdInit 000000000011cbb4 long 0e SECT 01 0000 [.text] _Tonga_UvdSuspend 000000000011ce41 long 0e SECT 01 0000 [.text] _Tonga_IsUVDIdle 000000000011ce6a long 0e SECT 01 0000 [.text] _Tonga_SetupUvdCacheWindows 000000000011ceff long 0e SECT 01 0000 [.text] _Tonga_VceInit 000000000011d394 long 0e SECT 01 0000 [.text] _Tonga_VceSuspend 000000000011d60a long 0e SECT 01 0000 [.text] _Tonga_SamuInit 000000000011db71 long 0e SECT 01 0000 [.text] _Tonga_SamuSuspend 000000000011dc99 long 0e SECT 01 0000 [.text] _Tonga_SamuSetClk 000000000011ddc3 long 0e SECT 01 0000 [.text] _Tonga_SamuCheckDebugBoard 000000000011ddd3 long 0e SECT 01 0000 [.text] _Tonga_SamuSrbmSoftReset 000000000011de0b long 0e SECT 01 0000 [.text] _Tonga_RaiseSamuResetInterrupt 000000000011dea9 long 0e SECT 01 0000 [.text] _tonga_get_indirect_register_sam 000000000011dec1 long 0e SECT 01 0000 [.text] _tonga_set_indirect_register_sam 000000000011dedc long 0e SECT 01 0000 [.text] _Tonga_UpdateVceClockGating 000000000011dfe9 long 0e SECT 01 0000 [.text] _Tonga_UpdateVceLightSleep 000000000011e0bf long 0e SECT 01 0000 [.text] _Tonga_UpdateSamuLightSleep 000000000011e165 long 0e SECT 01 0000 [.text] _Tonga_GetDoutScratch3 000000000011e19f long 0e SECT 01 0000 [.text] _Tonga_DetectHwVirtualization 000000000011e294 long 0e SECT 01 0000 [.text] _Tonga_CalculateVirtualizationReservedOffset 000000000011e36c long 0e SECT 01 0000 [.text] _tonga_set_uvd_clk_gating_branches 000000000011e3db long 0e SECT 01 0000 [.text] _tonga_set_uvd_dynamic_clock_mode 000000000011eab8 long 0e SECT 01 0000 [.text] _tonga_process_ind_reg_list 000000000011eb72 long 0e SECT 01 0000 [.text] _tonga_set_sdma_door_bell_and_id 000000000011ec1b long 0e SECT 01 0000 [.text] _Tonga_RestoreAdapterCfgRegisters 000000000011ec66 long 0e SECT 01 0000 [.text] _tonga_set_reg_in_uvd_dpg_mode 000000000011eca5 long 0e SECT 01 0000 [.text] _tonga_set_uvd_dynamic_clock_mode_in_dpg_mode 000000000011ed05 long 0e SECT 01 0000 [.text] _tonga_set_vce_light_sleep 000000000011ed4c long 0e SECT 01 0000 [.text] _tonga_set_vce_sw_clock_gating 000000000011eeea long 0e SECT 01 0000 [.text] _tonga_set_vce_dyn_clock_gating 000000000011efff long 0e SECT 01 0000 [.text] _tonga_override_vce_clock_gating 000000000011f046 long 0e SECT 01 0000 [.text] _tonga_perform_srbm_soft_reset 000000000011f0b8 long 0e SECT 01 0000 [.text] _tonga_register_update_for_asic_sku 000000000011f48b long 0e SECT 01 0000 [.text] _tonga_init_ECC 000000000011f4e8 long 0e SECT 01 0000 [.text] _tonga_init_ucode_buffer 000000000011f525 long 0e SECT 01 0000 [.text] _tonga_halt_rlc 000000000011f52d long 0e SECT 01 0000 [.text] _tonga_reset_rlc 000000000011f54c long 0e SECT 01 0000 [.text] _tonga_init_power_gating 000000000011f5c4 long 0e SECT 01 0000 [.text] _tonga_init_LBPW 000000000011f678 long 0e SECT 01 0000 [.text] _tonga_init_nonsurf_aperture 000000000011f683 long 0e SECT 01 0000 [.text] _tonga_program_PCIE_Gen3 000000000011f68e long 0e SECT 01 0000 [.text] _tonga_program_pcie_link_width 000000000011f699 long 0e SECT 01 0000 [.text] _tonga_init_uvd_clocks 000000000011f6a4 long 0e SECT 01 0000 [.text] _tonga_init_vce_clocks 000000000011f6af long 0e SECT 01 0000 [.text] _tonga_init_acp_clocks 000000000011f6ba long 0e SECT 01 0000 [.text] _tonga_init_samu_clocks 000000000011f6c5 long 0e SECT 01 0000 [.text] _tonga_restore_audio_enablement 000000000011f719 long 0e SECT 01 0000 [.text] _cail_tonga_force_ECCV2 000000000011f8fb long 0e SECT 01 0000 [.text] _tonga_program_samu_sw_clock_gating 000000000012108c long 0e SECT 01 0000 [.text] _NotImplemented 0000000000123ed2 long 0e SECT 01 0000 [.text] AMDRadeonX4000_IAMDSMLUVD::MetaClass::~MetaClass() 0000000000123fcc long 0e SECT 01 0000 [.text] AMDRadeonX4000_IAMDSMLDRM::MetaClass::~MetaClass() 00000000001240c6 long 0e SECT 01 0000 [.text] AMDRadeonX4000_IAMDSMLSPU::MetaClass::~MetaClass() 00000000001241c0 long 0e SECT 01 0000 [.text] AMDRadeonX4000_IAMDSMLVCE::MetaClass::~MetaClass() 00000000001242ba long 0e SECT 01 0000 [.text] AMDRadeonX4000_IAMDSMLInterface::MetaClass::~MetaClass() 0000000000124362 long 0e SECT 01 0000 [.text] AMDRadeonX4000_IAMDSMLUVD::init() 0000000000124374 long 0e SECT 01 0000 [.text] AMDRadeonX4000_IAMDSMLUVD::free() 0000000000124386 long 0e SECT 01 0000 [.text] AMDRadeonX4000_IAMDSMLDRM::init() 0000000000124398 long 0e SECT 01 0000 [.text] AMDRadeonX4000_IAMDSMLDRM::free() 00000000001243aa long 0e SECT 01 0000 [.text] AMDRadeonX4000_IAMDSMLSPU::init() 00000000001243bc long 0e SECT 01 0000 [.text] AMDRadeonX4000_IAMDSMLSPU::free() 00000000001243ce long 0e SECT 01 0000 [.text] AMDRadeonX4000_IAMDSMLVCE::init() 00000000001243e0 long 0e SECT 01 0000 [.text] AMDRadeonX4000_IAMDSMLVCE::free() 00000000001243f2 long 0e SECT 01 0000 [.text] AMDRadeonX4000_IAMDSMLInterface::init() 0000000000124404 long 0e SECT 01 0000 [.text] AMDRadeonX4000_IAMDSMLInterface::free() 0000000000124416 long 0e SECT 01 0000 [.text] AMDRadeonX4000_IAMDSMLUVD::MetaClass::~MetaClass() 0000000000124420 long 0e SECT 01 0000 [.text] AMDRadeonX4000_IAMDSMLDRM::MetaClass::~MetaClass() 000000000012442a long 0e SECT 01 0000 [.text] AMDRadeonX4000_IAMDSMLSPU::MetaClass::~MetaClass() 0000000000124434 long 0e SECT 01 0000 [.text] AMDRadeonX4000_IAMDSMLVCE::MetaClass::~MetaClass() 000000000012443e long 0e SECT 01 0000 [.text] AMDRadeonX4000_IAMDSMLInterface::MetaClass::~MetaClass() 0000000000124450 long 0e SECT 01 0000 [.text] __GLOBAL__I_a 0000000000124540 long 0e SECT 01 0000 [.text] __GLOBAL__D_a 00000000001245c2 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDSMLInterface::MetaClass::~MetaClass() 0000000000124c20 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDSMLInterface::MetaClass::~MetaClass() 0000000000124c2a long 0e SECT 01 0000 [.text] AMDRadeonX4000_IAMDSMLInterface::init() 0000000000124c3c long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDSMLInterface::createUVD() 0000000000124c42 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDSMLInterface::createDRM() 0000000000124c48 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDSMLInterface::createSPU() 0000000000124c4e long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDSMLInterface::createVCE() 0000000000124c60 long 0e SECT 01 0000 [.text] __GLOBAL__I_a 0000000000124ca0 long 0e SECT 01 0000 [.text] __GLOBAL__D_a 0000000000124cf2 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDSMLUVD::MetaClass::~MetaClass() 0000000000125472 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDSMLUVD::MetaClass::~MetaClass() 000000000012547c long 0e SECT 01 0000 [.text] AMDRadeonX4000_IAMDSMLUVD::init() 0000000000125490 long 0e SECT 01 0000 [.text] __GLOBAL__I_a 00000000001254d0 long 0e SECT 01 0000 [.text] __GLOBAL__D_a 0000000000125522 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDSMLDRM::MetaClass::~MetaClass() 00000000001256da long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDSMLDRM::MetaClass::~MetaClass() 00000000001256f0 long 0e SECT 01 0000 [.text] __GLOBAL__I_a 0000000000125730 long 0e SECT 01 0000 [.text] __GLOBAL__D_a 0000000000125782 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDSMLSPU::MetaClass::~MetaClass() 00000000001258c6 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDSMLSPU::MetaClass::~MetaClass() 00000000001258d0 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDSMLSPU::writeSetPremContentCmd(_SAMU_GPCOM_CMD*) 00000000001258e0 long 0e SECT 01 0000 [.text] __GLOBAL__I_a 0000000000125920 long 0e SECT 01 0000 [.text] __GLOBAL__D_a 0000000000125972 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDSMLSPUMsg::MetaClass::~MetaClass() 0000000000125b72 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDSMLSPUMsg::MetaClass::~MetaClass() 0000000000125b7c long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDSMLSPUMsg::getMsg() 0000000000125b84 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDSMLSPUMsg::getMsgSize() 0000000000125b8e long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDSMLSPUMsg::getMsgMemSize() 0000000000125b98 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDSMLSPUMsg::getMsgOffset() 0000000000125ba2 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDSMLSPUMsg::getBuffers() 0000000000125bac long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDSMLSPUMsg::setMsgBuffer(unsigned long long) 0000000000125bb6 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDSMLSPUMsg::setOutBuffer(int, unsigned long long, unsigned char*) 0000000000125bbc long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDSMLSPUMsg::getOutput() 0000000000125bc2 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDSMLSPUMsg::getOutputMemSize(int) 0000000000125bd4 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDSMLSPUMsg::getOutputDataSize(int) 0000000000125be6 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDSMLSPUMsg::getNumOutBuffers() 0000000000125bf0 long 0e SECT 01 0000 [.text] __GLOBAL__I_a 0000000000125c30 long 0e SECT 01 0000 [.text] __GLOBAL__D_a 0000000000125c92 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDSMLVCE::MetaClass::~MetaClass() 0000000000125ffc long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDSMLVCE::MetaClass::~MetaClass() 0000000000126006 long 0e SECT 01 0000 [.text] AMDRadeonX4000_IAMDSMLVCE::init() 0000000000126020 long 0e SECT 01 0000 [.text] __GLOBAL__I_a 0000000000126060 long 0e SECT 01 0000 [.text] __GLOBAL__D_a 00000000001260b2 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHDCPOpenSessionMsg::MetaClass::~MetaClass() 00000000001263a8 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHDCPCloseSessionMsg::MetaClass::~MetaClass() 00000000001265da long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHDCPGetStatusMsg::MetaClass::~MetaClass() 00000000001268e8 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHDCPGetCertMsg::MetaClass::~MetaClass() 0000000000126b88 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDFPGetCertMsg::MetaClass::~MetaClass() 0000000000126e6a long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDFPGenKeyMsg::MetaClass::~MetaClass() 00000000001271b0 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDFPTestKeyMsg::MetaClass::~MetaClass() 000000000012749c long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDFPReleaseSessionMsg::MetaClass::~MetaClass() 00000000001276ce long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDFPEncryptMsg::MetaClass::~MetaClass() 00000000001279f2 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHDCPOpenSessionMsg::MetaClass::~MetaClass() 00000000001279fc long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHDCPOpenSessionMsg::getMsg() 0000000000127a0a long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDSMLSPUMsg::getMsgSize() 0000000000127a14 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDSMLSPUMsg::getMsgMemSize() 0000000000127a1e long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDSMLSPUMsg::getMsgOffset() 0000000000127a28 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDSMLSPUMsg::getBuffers() 0000000000127a32 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDSMLSPUMsg::setMsgBuffer(unsigned long long) 0000000000127a3c long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDSMLSPUMsg::getOutputMemSize(int) 0000000000127a4e long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDSMLSPUMsg::getOutputDataSize(int) 0000000000127a60 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDSMLSPUMsg::getNumOutBuffers() 0000000000127a6a long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHDCPCloseSessionMsg::MetaClass::~MetaClass() 0000000000127a74 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHDCPCloseSessionMsg::getMsg() 0000000000127a82 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDSMLSPUMsg::setOutBuffer(int, unsigned long long, unsigned char*) 0000000000127a88 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDSMLSPUMsg::getOutput() 0000000000127a8e long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHDCPGetStatusMsg::MetaClass::~MetaClass() 0000000000127a98 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHDCPGetStatusMsg::getMsg() 0000000000127aa6 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHDCPGetCertMsg::MetaClass::~MetaClass() 0000000000127ab0 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDHDCPGetCertMsg::getMsg() 0000000000127abe long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDFPGetCertMsg::MetaClass::~MetaClass() 0000000000127ac8 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDFPGetCertMsg::getMsg() 0000000000127ad6 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDFPGenKeyMsg::MetaClass::~MetaClass() 0000000000127ae0 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDFPGenKeyMsg::getMsg() 0000000000127aee long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDFPTestKeyMsg::MetaClass::~MetaClass() 0000000000127af8 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDFPTestKeyMsg::getMsg() 0000000000127b06 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDFPReleaseSessionMsg::MetaClass::~MetaClass() 0000000000127b10 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDFPReleaseSessionMsg::getMsg() 0000000000127b1e long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDFPEncryptMsg::MetaClass::~MetaClass() 0000000000127b28 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDFPEncryptMsg::getMsg() 0000000000127b40 long 0e SECT 01 0000 [.text] __GLOBAL__I_a 0000000000127cd0 long 0e SECT 01 0000 [.text] __GLOBAL__D_a 0000000000127d82 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDSMLSIInterface::MetaClass::~MetaClass() 0000000000127fa6 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDSMLSIInterface::MetaClass::~MetaClass() 0000000000127fb0 long 0e SECT 01 0000 [.text] AMDRadeonX4000_IAMDSMLInterface::init() 0000000000127fd0 long 0e SECT 01 0000 [.text] __GLOBAL__I_a 0000000000128010 long 0e SECT 01 0000 [.text] __GLOBAL__D_a 0000000000128062 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDUVDTrinity::MetaClass::~MetaClass() 0000000000128248 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDUVDTrinity::MetaClass::~MetaClass() 0000000000128252 long 0e SECT 01 0000 [.text] AMDRadeonX4000_IAMDSMLUVD::init() 0000000000128270 long 0e SECT 01 0000 [.text] __GLOBAL__I_a 00000000001282b0 long 0e SECT 01 0000 [.text] __GLOBAL__D_a 0000000000128302 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDSIDRM::MetaClass::~MetaClass() 0000000000128c38 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDSIDRM::MetaClass::~MetaClass() 0000000000128c50 long 0e SECT 01 0000 [.text] __GLOBAL__I_a 0000000000128c90 long 0e SECT 01 0000 [.text] __GLOBAL__D_a 0000000000128ce2 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDSISPU::MetaClass::~MetaClass() 000000000012937e long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDSISPU::MetaClass::~MetaClass() 0000000000129388 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDSMLSPU::writeSetPremContentCmd(_SAMU_GPCOM_CMD*) 0000000000129390 long 0e SECT 01 0000 [.text] __GLOBAL__I_a 00000000001293d0 long 0e SECT 01 0000 [.text] __GLOBAL__D_a 0000000000129422 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDSIVCE::MetaClass::~MetaClass() 000000000012977a long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDSIVCE::MetaClass::~MetaClass() 0000000000129784 long 0e SECT 01 0000 [.text] AMDRadeonX4000_IAMDSMLVCE::init() 00000000001297a0 long 0e SECT 01 0000 [.text] __GLOBAL__I_a 00000000001297e0 long 0e SECT 01 0000 [.text] __GLOBAL__D_a 0000000000129832 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDSMLCIKInterface::MetaClass::~MetaClass() 0000000000129a56 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDSMLCIKInterface::MetaClass::~MetaClass() 0000000000129a60 long 0e SECT 01 0000 [.text] AMDRadeonX4000_IAMDSMLInterface::init() 0000000000129a80 long 0e SECT 01 0000 [.text] __GLOBAL__I_a 0000000000129ac0 long 0e SECT 01 0000 [.text] __GLOBAL__D_a 0000000000129b12 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDUVDCIK::MetaClass::~MetaClass() 0000000000129eaa long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDUVDCIK::MetaClass::~MetaClass() 0000000000129eb4 long 0e SECT 01 0000 [.text] AMDRadeonX4000_IAMDSMLUVD::init() 0000000000129ed0 long 0e SECT 01 0000 [.text] __GLOBAL__I_a 0000000000129f10 long 0e SECT 01 0000 [.text] __GLOBAL__D_a 0000000000129f62 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDCIKDRM::MetaClass::~MetaClass() 000000000012a934 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDCIKDRM::MetaClass::~MetaClass() 000000000012a940 long 0e SECT 01 0000 [.text] __GLOBAL__I_a 000000000012a980 long 0e SECT 01 0000 [.text] __GLOBAL__D_a 000000000012a9d2 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDCIKSPU::MetaClass::~MetaClass() 000000000012b100 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDCIKSPU::MetaClass::~MetaClass() 000000000012b110 long 0e SECT 01 0000 [.text] __GLOBAL__I_a 000000000012b150 long 0e SECT 01 0000 [.text] __GLOBAL__D_a 000000000012b1a2 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDCIKVCE::MetaClass::~MetaClass() 000000000012b3d6 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDCIKVCE::MetaClass::~MetaClass() 000000000012b3e0 long 0e SECT 01 0000 [.text] AMDRadeonX4000_IAMDSMLVCE::init() 000000000012b400 long 0e SECT 01 0000 [.text] __GLOBAL__I_a 000000000012b440 long 0e SECT 01 0000 [.text] __GLOBAL__D_a 000000000012b492 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDSMLVIInterface::MetaClass::~MetaClass() 000000000012b6b6 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDSMLVIInterface::MetaClass::~MetaClass() 000000000012b6c0 long 0e SECT 01 0000 [.text] AMDRadeonX4000_IAMDSMLInterface::init() 000000000012b6e0 long 0e SECT 01 0000 [.text] __GLOBAL__I_a 000000000012b720 long 0e SECT 01 0000 [.text] __GLOBAL__D_a 000000000012b772 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDUVDVI::MetaClass::~MetaClass() 000000000012b910 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDUVDVI::MetaClass::~MetaClass() 000000000012b91a long 0e SECT 01 0000 [.text] AMDRadeonX4000_IAMDSMLUVD::init() 000000000012b930 long 0e SECT 01 0000 [.text] __GLOBAL__I_a 000000000012b970 long 0e SECT 01 0000 [.text] __GLOBAL__D_a 000000000012b9c2 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDVIDRM::MetaClass::~MetaClass() 000000000012c394 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDVIDRM::MetaClass::~MetaClass() 000000000012c3a0 long 0e SECT 01 0000 [.text] __GLOBAL__I_a 000000000012c3e0 long 0e SECT 01 0000 [.text] __GLOBAL__D_a 000000000012c432 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDVISPU::MetaClass::~MetaClass() 000000000012c61c long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDVISPU::MetaClass::~MetaClass() 000000000012c630 long 0e SECT 01 0000 [.text] __GLOBAL__I_a 000000000012c670 long 0e SECT 01 0000 [.text] __GLOBAL__D_a 000000000012c6c2 long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDVIVCE::MetaClass::~MetaClass() 000000000012c92e long 0e SECT 01 0000 [.text] AMDRadeonX4000_AMDVIVCE::MetaClass::~MetaClass() 000000000012c938 long 0e SECT 01 0000 [.text] AMDRadeonX4000_IAMDSMLVCE::init() 000000000012c950 long 0e SECT 01 0000 [.text] __GLOBAL__I_a 000000000012c990 long 0e SECT 01 0000 [.text] __GLOBAL__D_a 000000000012f630 long 0e SECT 03 0000 [.const] g_AMDGraphicsAcceleratorName 000000000012f66c long 0e SECT 03 0000 [.const] tokenArgSizes 000000000012f6a0 long 0e SECT 03 0000 [.const] deviceTypeTable 000000000012f6d0 long 0e SECT 03 0000 [.const] deviceTypeTable 000000000012f700 long 0e SECT 03 0000 [.const] tokenArgSizeVaries 000000000012f710 long 0e SECT 03 0000 [.const] tokenArgSizes 000000000012f740 long 0e SECT 03 0000 [.const] AMDSIGLContext::write_kernel_render_target_regs(unsigned int*)::hwLog2NumSamples 000000000012f790 long 0e SECT 03 0000 [.const] getDbZInfo(AMDRadeonX4000_AMDAccelResource const*, unsigned int, bool, bool, SI_HwWorkAroundsRec*)::hwLog2NumSamples 000000000012f7e0 long 0e SECT 03 0000 [.const] tokenArgSizes 000000000012f800 long 0e SECT 03 0000 [.const] AMDSICLContext::getPixelBytes(unsigned int, unsigned int)::pixelBytes 000000000012fee0 long 0e SECT 03 0000 [.const] tokenArgSizes 000000000012fef0 long 0e SECT 03 0000 [.const] AMDCICLContext::getPixelBytes(unsigned int, unsigned int)::pixelBytes 00000000001305d0 long 0e SECT 03 0000 [.const] deviceTypeTable 00000000001305e8 long 0e SECT 03 0000 [.const] AMDRadeonX4000_AMDHWChannel::initStatisticsGroups()::channelName 0000000000130a40 long 0e SECT 03 0000 [.const] AMDSIDisplay::getPixelMode(unsigned int, unsigned int)::pixelModeTable 0000000000130b30 long 0e SECT 03 0000 [.const] AMDSIHardware::programPageTableRegisters(AMD_VM_PAGE_TABLE_INFO*, unsigned int)::VM_CONTEXT_BASE_ADDRESSES 0000000000130b70 long 0e SECT 03 0000 [.const] AMD_SI_ASIC_HANG_LOG_DUMP_REGISTERS::asicHangLogDumpRegisters 0000000000131400 long 0e SECT 03 0000 [.const] AMD_SI_ASIC_HANG_LOG_DUMP_REGISTERS::asicHangLogDumpReorderQueueRegisters 0000000000131470 long 0e SECT 03 0000 [.const] AMD_SI_ASIC_HANG_LOG_DUMP_REGISTERS::asicHangLogDumpMeStateQueueRegisters 00000000001314e0 long 0e SECT 03 0000 [.const] TAHITI_UCODE::aF32_PFP_Ucode 0000000000133660 long 0e SECT 03 0000 [.const] TAHITI_UCODE::aF32_ME_Ucode 00000000001357e0 long 0e SECT 03 0000 [.const] TAHITI_UCODE::aF32_CE_Ucode 0000000000137960 long 0e SECT 03 0000 [.const] PITCAIRN_UCODE::aF32_PFP_Ucode 0000000000139ae0 long 0e SECT 03 0000 [.const] PITCAIRN_UCODE::aF32_ME_Ucode 000000000013bc60 long 0e SECT 03 0000 [.const] PITCAIRN_UCODE::aF32_CE_Ucode 000000000013dde0 long 0e SECT 03 0000 [.const] VERDE_UCODE::aF32_PFP_Ucode 000000000013ff60 long 0e SECT 03 0000 [.const] VERDE_UCODE::aF32_ME_Ucode 00000000001420e0 long 0e SECT 03 0000 [.const] VERDE_UCODE::aF32_CE_Ucode 0000000000144260 long 0e SECT 03 0000 [.const] AMDSIDMAChannel::submitVMInvalidate(unsigned int, unsigned long long, unsigned int)::VM_CONTEXT_BASE_ADDRESSES 00000000001442c0 long 0e SECT 03 0000 [.const] AMDCIHardware::programPageTableRegisters(AMD_VM_PAGE_TABLE_INFO*, unsigned int)::VM_CONTEXT_BASE_ADDRESSES 0000000000144300 long 0e SECT 03 0000 [.const] AMD_CI_ASIC_HANG_LOG_DUMP_REGISTERS::asicHangLogDumpRegisters 0000000000144ba0 long 0e SECT 03 0000 [.const] AMD_CI_ASIC_HANG_LOG_DUMP_REGISTERS::asicHangLogDumpReorderQueueRegisters 0000000000144bd0 long 0e SECT 03 0000 [.const] AMD_CI_ASIC_HANG_LOG_DUMP_REGISTERS::asicHangLogDumpMeStateQueueRegisters 0000000000144c30 long 0e SECT 03 0000 [.const] engineRingTable 00000000001450a0 long 0e SECT 03 0000 [.const] AMDCIDisplay::getPixelMode(unsigned int, unsigned int)::pixelModeTable 0000000000145160 long 0e SECT 03 0000 [.const] AMDCIDMAChannel::submitVMInvalidate(unsigned int, unsigned long long, unsigned int)::VM_CONTEXT_BASE_ADDRESSES 0000000000145260 long 0e SECT 03 0000 [.const] AMDVIHardware::programPageTableRegisters(AMD_VM_PAGE_TABLE_INFO*, unsigned int)::VM_CONTEXT_BASE_ADDRESSES 00000000001452a0 long 0e SECT 03 0000 [.const] AMD_VI_ASIC_HANG_LOG_DUMP_REGISTERS::asicHangLogDumpRegisters 0000000000145b40 long 0e SECT 03 0000 [.const] AMD_VI_ASIC_HANG_LOG_DUMP_REGISTERS::asicHangLogDumpReorderQueueRegisters 0000000000145b70 long 0e SECT 03 0000 [.const] AMD_VI_ASIC_HANG_LOG_DUMP_REGISTERS::asicHangLogDumpMeStateQueueRegisters 0000000000145fe0 long 0e SECT 03 0000 [.const] AMDVIDisplay::getPixelMode(unsigned int, unsigned int)::pixelModeTable 00000000001460b0 long 0e SECT 03 0000 [.const] AMDVIsDMAChannel::submitVMInvalidate(unsigned int, unsigned long long, unsigned int)::VM_CONTEXT_BASE_ADDRESSES 00000000001460f0 long 0e SECT 03 0000 [.const] engineRingTable 00000000001463f0 long 0e SECT 03 0000 [.const] _bp 0000000000146400 long 0e SECT 03 0000 [.const] _dp_l 0000000000146410 long 0e SECT 03 0000 [.const] _dp_h 0000000000146420 long 0e SECT 03 0000 [.const] ___qdivrem.zero 00000000001464a0 long 0e SECT 03 0000 [.const] BltMgr::SelectAAResolveTentFilterTaps(BltInfo*, unsigned int, float, AAResolveTapDescriptor*, unsigned int)::pixOffsets 00000000001464c8 long 0e SECT 03 0000 [.const] BltMgr::DesktopComposition(BltDevice*, _UBM_DESKTOPCOMPOSITIONINFO*)::StdGrayWeights 000000000014658c long 0e SECT 03 0000 [.const] Desc_NOT_PACKED 0000000000146608 long 0e SECT 03 0000 [.const] Desc_SPLIT_G70_B54__R70_B10 0000000000146684 long 0e SECT 03 0000 [.const] Desc_SPLIT_B70_G10__R70_G76 0000000000146700 long 0e SECT 03 0000 [.const] Desc_G70_B54__R70_B10 000000000014677c long 0e SECT 03 0000 [.const] Desc_B70_R32__G70_R76 00000000001467f8 long 0e SECT 03 0000 [.const] Desc_B70_R30__G70_R74 0000000000146874 long 0e SECT 03 0000 [.const] Desc_B70__G70__R70 00000000001468f0 long 0e SECT 03 0000 [.const] Desc_R70_G76 000000000014696c long 0e SECT 03 0000 [.const] Desc_G70_B54 00000000001469e8 long 0e SECT 03 0000 [.const] Desc_NATIVE 0000000000146bc0 long 0e SECT 03 0000 [.const] CRC32Table 0000000000146fe0 long 0e SECT 03 0000 [.const] SiBltDevice::WaitOnFlushAndInvTimestamp()::ClearedTimestamp 0000000000146fe4 long 0e SECT 03 0000 [.const] SiBltDevice::WaitOnCsDone()::ClearedTimestamp 0000000000146ff0 long 0e SECT 03 0000 [.const] ViContextRegDefs 0000000000147050 long 0e SECT 03 0000 [.const] CiContextRegDefs 00000000001470b0 long 0e SECT 03 0000 [.const] SiContextRegDefs 0000000000147110 long 0e SECT 03 0000 [.const] siGfxShaderRegDefs 0000000000147130 long 0e SECT 03 0000 [.const] SiComputeShaderRegDefs 00000000001471d4 long 0e SECT 03 0000 [.const] UbmDefaultPatchHandle 00000000001471e0 long 0e SECT 03 0000 [.const] SiBltDrawRegs::SetupAndWriteClipRects(BltInfo const*, _UBM_RECTL const*, unsigned int)::ClipRule 0000000000147200 long 0e SECT 03 0000 [.const] SiBltDrawRegs::SetupAndWriteCentroidPriorities(BltInfo const*)::pDefaultCentroidPriorities 0000000000147240 long 0e SECT 03 0000 [.const] SiBltDrawRegs::SetupAlphaBlend(BltInfo const*)::SiUbmBlendModeToHwTable 0000000000147330 long 0e SECT 03 0000 [.const] RectToVertTransform 0000000000147360 long 0e SECT 03 0000 [.const] TransposeRect0 00000000001473b0 long 0e SECT 03 0000 [.const] TransposeRect90 0000000000147400 long 0e SECT 03 0000 [.const] TransposeRect180 0000000000147450 long 0e SECT 03 0000 [.const] TransposeRect270 00000000001474a0 long 0e SECT 03 0000 [.const] SiBltMgr::SetupRectPosTexTexConstants(BltInfo const*)::MirrorTransformDefault 00000000001474b0 long 0e SECT 03 0000 [.const] VertRotation90 00000000001474c0 long 0e SECT 03 0000 [.const] VertRotation180 00000000001474d0 long 0e SECT 03 0000 [.const] VertRotation270 00000000001474e0 long 0e SECT 03 0000 [.const] SiBltMgr::HwlGetDefaultSampleLocs(unsigned int)::SiSampleLocs2 00000000001474f0 long 0e SECT 03 0000 [.const] SiBltMgr::HwlGetDefaultSampleLocs(unsigned int)::SiSampleLocs4 0000000000147510 long 0e SECT 03 0000 [.const] SiBltMgr::HwlGetDefaultSampleLocs(unsigned int)::SiSampleLocs8 0000000000147550 long 0e SECT 03 0000 [.const] SiBltMgr::HwlGetDefaultSampleLocs(unsigned int)::SiSampleLocs16 00000000001475d0 long 0e SECT 03 0000 [.const] SiBltMgr::HwlGetDefaultSampleLocs(unsigned int)::SiQuadSampleLocs2 0000000000147610 long 0e SECT 03 0000 [.const] SiBltMgr::HwlGetDefaultSampleLocs(unsigned int)::SiQuadSampleLocs4 0000000000147690 long 0e SECT 03 0000 [.const] SiBltMgr::HwlGetDefaultSampleLocs(unsigned int)::SiQuadSampleLocs8 0000000000147790 long 0e SECT 03 0000 [.const] SiBltMgr::HwlGetDefaultSampleLocs(unsigned int)::SiQuadSampleLocs16 0000000000147990 long 0e SECT 03 0000 [.const] SiBltMgr::SetupDitherTextureData(_UBM_SURFINFO const*)::DitherTex 0000000000147d90 long 0e SECT 03 0000 [.const] SiBltResFmt::GetDstSel(_UBM_FORMAT, unsigned int, unsigned int) const::CompSwizToDstSel 00000000001482e0 long 0e SECT 03 0000 [.const] gShaderCode_si_RectPos_VS 00000000001483e0 long 0e SECT 03 0000 [.const] gShRegisters_si_RectPos_VS 00000000001483f0 long 0e SECT 03 0000 [.const] gContextRegisters_si_RectPos_VS 0000000000148400 long 0e SECT 03 0000 [.const] gUserElementTable_si_RectPos_VS 0000000000148430 long 0e SECT 03 0000 [.const] gOutSemantics_si_RectPos_VS 0000000000148440 long 0e SECT 03 0000 [.const] gShaderCode_si_RectPosTexTex_VS 0000000000148780 long 0e SECT 03 0000 [.const] gShRegisters_si_RectPosTexTex_VS 0000000000148790 long 0e SECT 03 0000 [.const] gContextRegisters_si_RectPosTexTex_VS 00000000001487a0 long 0e SECT 03 0000 [.const] gUserElementTable_si_RectPosTexTex_VS 00000000001487d0 long 0e SECT 03 0000 [.const] gOutSemantics_si_RectPosTexTex_VS 00000000001487f0 long 0e SECT 03 0000 [.const] gShaderCode_si_RectPosTexFast_VS 0000000000148880 long 0e SECT 03 0000 [.const] gShRegisters_si_RectPosTexFast_VS 0000000000148890 long 0e SECT 03 0000 [.const] gContextRegisters_si_RectPosTexFast_VS 00000000001488a0 long 0e SECT 03 0000 [.const] gUserElementTable_si_RectPosTexFast_VS 0000000000148900 long 0e SECT 03 0000 [.const] gOutSemantics_si_RectPosTexFast_VS 0000000000148910 long 0e SECT 03 0000 [.const] gShaderCode_si_VertPosColor_VS 0000000000148960 long 0e SECT 03 0000 [.const] gShRegisters_si_VertPosColor_VS 0000000000148970 long 0e SECT 03 0000 [.const] gContextRegisters_si_VertPosColor_VS 0000000000148980 long 0e SECT 03 0000 [.const] gUserElementTable_si_VertPosColor_VS 00000000001489b0 long 0e SECT 03 0000 [.const] gOutSemantics_si_VertPosColor_VS 00000000001489c0 long 0e SECT 03 0000 [.const] gShaderCode_si_RectPosTexTexComposite_VS 0000000000148b40 long 0e SECT 03 0000 [.const] gShRegisters_si_RectPosTexTexComposite_VS 0000000000148b50 long 0e SECT 03 0000 [.const] gContextRegisters_si_RectPosTexTexComposite_VS 0000000000148b60 long 0e SECT 03 0000 [.const] gUserElementTable_si_RectPosTexTexComposite_VS 0000000000148b90 long 0e SECT 03 0000 [.const] gOutSemantics_si_RectPosTexTexComposite_VS 0000000000148bb0 long 0e SECT 03 0000 [.const] gShaderCode_si_Zero_PS 0000000000148bd0 long 0e SECT 03 0000 [.const] gShRegisters_si_Zero_PS 0000000000148be0 long 0e SECT 03 0000 [.const] gContextRegisters_si_Zero_PS 0000000000148c20 long 0e SECT 03 0000 [.const] gUserElementTable_si_Zero_PS 0000000000148c40 long 0e SECT 03 0000 [.const] gInSemantics_si_Zero_PS 0000000000148c54 long 0e SECT 03 0000 [.const] gPatchInfoOffset_si_Zero_PS 0000000000148c60 long 0e SECT 03 0000 [.const] gPatchInfoCode_si_Zero_PS 0000000000148d00 long 0e SECT 03 0000 [.const] gShaderCode_si_Const_PS 0000000000148d30 long 0e SECT 03 0000 [.const] gShRegisters_si_Const_PS 0000000000148d40 long 0e SECT 03 0000 [.const] gContextRegisters_si_Const_PS 0000000000148d80 long 0e SECT 03 0000 [.const] gUserElementTable_si_Const_PS 0000000000148da0 long 0e SECT 03 0000 [.const] gInSemantics_si_Const_PS 0000000000148db4 long 0e SECT 03 0000 [.const] gPatchInfoOffset_si_Const_PS 0000000000148dc0 long 0e SECT 03 0000 [.const] gPatchInfoCode_si_Const_PS 0000000000148e60 long 0e SECT 03 0000 [.const] gShaderCode_si_Tex_PS 0000000000148ea0 long 0e SECT 03 0000 [.const] gShRegisters_si_Tex_PS 0000000000148eb0 long 0e SECT 03 0000 [.const] gContextRegisters_si_Tex_PS 0000000000148ef0 long 0e SECT 03 0000 [.const] gUserElementTable_si_Tex_PS 0000000000148f20 long 0e SECT 03 0000 [.const] gInSemantics_si_Tex_PS 0000000000148f34 long 0e SECT 03 0000 [.const] gPatchInfoOffset_si_Tex_PS 0000000000148f40 long 0e SECT 03 0000 [.const] gPatchInfoCode_si_Tex_PS 0000000000148fe0 long 0e SECT 03 0000 [.const] gShaderCode_si_TexCoord_PS 0000000000149020 long 0e SECT 03 0000 [.const] gShRegisters_si_TexCoord_PS 0000000000149030 long 0e SECT 03 0000 [.const] gContextRegisters_si_TexCoord_PS 0000000000149070 long 0e SECT 03 0000 [.const] gUserElementTable_si_TexCoord_PS 0000000000149090 long 0e SECT 03 0000 [.const] gInSemantics_si_TexCoord_PS 00000000001490a4 long 0e SECT 03 0000 [.const] gPatchInfoOffset_si_TexCoord_PS 00000000001490b0 long 0e SECT 03 0000 [.const] gPatchInfoCode_si_TexCoord_PS 0000000000149150 long 0e SECT 03 0000 [.const] gShaderCode_si_TexGammaDst_PS 0000000000149250 long 0e SECT 03 0000 [.const] gShRegisters_si_TexGammaDst_PS 0000000000149260 long 0e SECT 03 0000 [.const] gContextRegisters_si_TexGammaDst_PS 00000000001492a0 long 0e SECT 03 0000 [.const] gUserElementTable_si_TexGammaDst_PS 00000000001492d0 long 0e SECT 03 0000 [.const] gInSemantics_si_TexGammaDst_PS 00000000001492e4 long 0e SECT 03 0000 [.const] gPatchInfoOffset_si_TexGammaDst_PS 00000000001492f0 long 0e SECT 03 0000 [.const] gPatchInfoCode_si_TexGammaDst_PS 0000000000149390 long 0e SECT 03 0000 [.const] gShaderCode_si_MsaaResolve1_PS 00000000001493d0 long 0e SECT 03 0000 [.const] gShRegisters_si_MsaaResolve1_PS 00000000001493e0 long 0e SECT 03 0000 [.const] gContextRegisters_si_MsaaResolve1_PS 0000000000149420 long 0e SECT 03 0000 [.const] gUserElementTable_si_MsaaResolve1_PS 0000000000149450 long 0e SECT 03 0000 [.const] gInSemantics_si_MsaaResolve1_PS 0000000000149464 long 0e SECT 03 0000 [.const] gPatchInfoOffset_si_MsaaResolve1_PS 0000000000149470 long 0e SECT 03 0000 [.const] gPatchInfoCode_si_MsaaResolve1_PS 0000000000149510 long 0e SECT 03 0000 [.const] gShaderCode_si_MsaaResolve2_PS 0000000000149580 long 0e SECT 03 0000 [.const] gShRegisters_si_MsaaResolve2_PS 0000000000149590 long 0e SECT 03 0000 [.const] gContextRegisters_si_MsaaResolve2_PS 00000000001495d0 long 0e SECT 03 0000 [.const] gUserElementTable_si_MsaaResolve2_PS 0000000000149600 long 0e SECT 03 0000 [.const] gInSemantics_si_MsaaResolve2_PS 0000000000149614 long 0e SECT 03 0000 [.const] gPatchInfoOffset_si_MsaaResolve2_PS 0000000000149620 long 0e SECT 03 0000 [.const] gPatchInfoCode_si_MsaaResolve2_PS 00000000001496c0 long 0e SECT 03 0000 [.const] gShaderCode_si_MsaaResolve4_PS 0000000000149770 long 0e SECT 03 0000 [.const] gShRegisters_si_MsaaResolve4_PS 0000000000149780 long 0e SECT 03 0000 [.const] gContextRegisters_si_MsaaResolve4_PS 00000000001497c0 long 0e SECT 03 0000 [.const] gUserElementTable_si_MsaaResolve4_PS 00000000001497f0 long 0e SECT 03 0000 [.const] gInSemantics_si_MsaaResolve4_PS 0000000000149804 long 0e SECT 03 0000 [.const] gPatchInfoOffset_si_MsaaResolve4_PS 0000000000149810 long 0e SECT 03 0000 [.const] gPatchInfoCode_si_MsaaResolve4_PS 00000000001498b0 long 0e SECT 03 0000 [.const] gShaderCode_si_MsaaResolve8_PS 00000000001499e0 long 0e SECT 03 0000 [.const] gShRegisters_si_MsaaResolve8_PS 00000000001499f0 long 0e SECT 03 0000 [.const] gContextRegisters_si_MsaaResolve8_PS 0000000000149a30 long 0e SECT 03 0000 [.const] gUserElementTable_si_MsaaResolve8_PS 0000000000149a60 long 0e SECT 03 0000 [.const] gInSemantics_si_MsaaResolve8_PS 0000000000149a74 long 0e SECT 03 0000 [.const] gPatchInfoOffset_si_MsaaResolve8_PS 0000000000149a80 long 0e SECT 03 0000 [.const] gPatchInfoCode_si_MsaaResolve8_PS 0000000000149b20 long 0e SECT 03 0000 [.const] gShaderCode_si_MsaaFMaskExpand_PS 0000000000149ba0 long 0e SECT 03 0000 [.const] gShRegisters_si_MsaaFMaskExpand_PS 0000000000149bb0 long 0e SECT 03 0000 [.const] gContextRegisters_si_MsaaFMaskExpand_PS 0000000000149bf0 long 0e SECT 03 0000 [.const] gUserElementTable_si_MsaaFMaskExpand_PS 0000000000149c20 long 0e SECT 03 0000 [.const] gInSemantics_si_MsaaFMaskExpand_PS 0000000000149c34 long 0e SECT 03 0000 [.const] gPatchInfoOffset_si_MsaaFMaskExpand_PS 0000000000149c40 long 0e SECT 03 0000 [.const] gPatchInfoCode_si_MsaaFMaskExpand_PS 0000000000149ce0 long 0e SECT 03 0000 [.const] gShaderCode_si_MsaaDepthResolve_PS 0000000000149d20 long 0e SECT 03 0000 [.const] gShRegisters_si_MsaaDepthResolve_PS 0000000000149d30 long 0e SECT 03 0000 [.const] gContextRegisters_si_MsaaDepthResolve_PS 0000000000149d70 long 0e SECT 03 0000 [.const] gUserElementTable_si_MsaaDepthResolve_PS 0000000000149da0 long 0e SECT 03 0000 [.const] gInSemantics_si_MsaaDepthResolve_PS 0000000000149db4 long 0e SECT 03 0000 [.const] gPatchInfoOffset_si_MsaaDepthResolve_PS 0000000000149dc0 long 0e SECT 03 0000 [.const] gPatchInfoCode_si_MsaaDepthResolve_PS 0000000000149e60 long 0e SECT 03 0000 [.const] gShaderCode_si_MsaaDepthStencilResolve_PS 0000000000149ec0 long 0e SECT 03 0000 [.const] gShRegisters_si_MsaaDepthStencilResolve_PS 0000000000149ed0 long 0e SECT 03 0000 [.const] gContextRegisters_si_MsaaDepthStencilResolve_PS 0000000000149f10 long 0e SECT 03 0000 [.const] gUserElementTable_si_MsaaDepthStencilResolve_PS 0000000000149f60 long 0e SECT 03 0000 [.const] gInSemantics_si_MsaaDepthStencilResolve_PS 0000000000149f74 long 0e SECT 03 0000 [.const] gPatchInfoOffset_si_MsaaDepthStencilResolve_PS 0000000000149f80 long 0e SECT 03 0000 [.const] gPatchInfoCode_si_MsaaDepthStencilResolve_PS 000000000014a020 long 0e SECT 03 0000 [.const] gShaderCode_si_TexZStencilAsColor_PS 000000000014a080 long 0e SECT 03 0000 [.const] gShRegisters_si_TexZStencilAsColor_PS 000000000014a090 long 0e SECT 03 0000 [.const] gContextRegisters_si_TexZStencilAsColor_PS 000000000014a0d0 long 0e SECT 03 0000 [.const] gUserElementTable_si_TexZStencilAsColor_PS 000000000014a120 long 0e SECT 03 0000 [.const] gInSemantics_si_TexZStencilAsColor_PS 000000000014a134 long 0e SECT 03 0000 [.const] gPatchInfoOffset_si_TexZStencilAsColor_PS 000000000014a140 long 0e SECT 03 0000 [.const] gPatchInfoCode_si_TexZStencilAsColor_PS 000000000014a1e0 long 0e SECT 03 0000 [.const] gShaderCode_si_MsaaTexZStencilAsColor_PS 000000000014a240 long 0e SECT 03 0000 [.const] gShRegisters_si_MsaaTexZStencilAsColor_PS 000000000014a250 long 0e SECT 03 0000 [.const] gContextRegisters_si_MsaaTexZStencilAsColor_PS 000000000014a290 long 0e SECT 03 0000 [.const] gUserElementTable_si_MsaaTexZStencilAsColor_PS 000000000014a2b0 long 0e SECT 03 0000 [.const] gInSemantics_si_MsaaTexZStencilAsColor_PS 000000000014a2c4 long 0e SECT 03 0000 [.const] gPatchInfoOffset_si_MsaaTexZStencilAsColor_PS 000000000014a2d0 long 0e SECT 03 0000 [.const] gPatchInfoCode_si_MsaaTexZStencilAsColor_PS 000000000014a370 long 0e SECT 03 0000 [.const] gShaderCode_si_TexAsZ_PS 000000000014a3b0 long 0e SECT 03 0000 [.const] gShRegisters_si_TexAsZ_PS 000000000014a3c0 long 0e SECT 03 0000 [.const] gContextRegisters_si_TexAsZ_PS 000000000014a400 long 0e SECT 03 0000 [.const] gUserElementTable_si_TexAsZ_PS 000000000014a430 long 0e SECT 03 0000 [.const] gInSemantics_si_TexAsZ_PS 000000000014a444 long 0e SECT 03 0000 [.const] gPatchInfoOffset_si_TexAsZ_PS 000000000014a450 long 0e SECT 03 0000 [.const] gPatchInfoCode_si_TexAsZ_PS 000000000014a4f0 long 0e SECT 03 0000 [.const] gShaderCode_si_TexAsZStencil_PS 000000000014a550 long 0e SECT 03 0000 [.const] gShRegisters_si_TexAsZStencil_PS 000000000014a560 long 0e SECT 03 0000 [.const] gContextRegisters_si_TexAsZStencil_PS 000000000014a5a0 long 0e SECT 03 0000 [.const] gUserElementTable_si_TexAsZStencil_PS 000000000014a5f0 long 0e SECT 03 0000 [.const] gInSemantics_si_TexAsZStencil_PS 000000000014a604 long 0e SECT 03 0000 [.const] gPatchInfoOffset_si_TexAsZStencil_PS 000000000014a610 long 0e SECT 03 0000 [.const] gPatchInfoCode_si_TexAsZStencil_PS 000000000014a6b0 long 0e SECT 03 0000 [.const] gShaderCode_si_MsaaTexAsZ_PS 000000000014a700 long 0e SECT 03 0000 [.const] gShRegisters_si_MsaaTexAsZ_PS 000000000014a710 long 0e SECT 03 0000 [.const] gContextRegisters_si_MsaaTexAsZ_PS 000000000014a750 long 0e SECT 03 0000 [.const] gUserElementTable_si_MsaaTexAsZ_PS 000000000014a780 long 0e SECT 03 0000 [.const] gInSemantics_si_MsaaTexAsZ_PS 000000000014a794 long 0e SECT 03 0000 [.const] gPatchInfoOffset_si_MsaaTexAsZ_PS 000000000014a7a0 long 0e SECT 03 0000 [.const] gPatchInfoCode_si_MsaaTexAsZ_PS 000000000014a840 long 0e SECT 03 0000 [.const] gShaderCode_si_MsaaTexAsZStencil_PS 000000000014a8a0 long 0e SECT 03 0000 [.const] gShRegisters_si_MsaaTexAsZStencil_PS 000000000014a8b0 long 0e SECT 03 0000 [.const] gContextRegisters_si_MsaaTexAsZStencil_PS 000000000014a8f0 long 0e SECT 03 0000 [.const] gUserElementTable_si_MsaaTexAsZStencil_PS 000000000014a940 long 0e SECT 03 0000 [.const] gInSemantics_si_MsaaTexAsZStencil_PS 000000000014a954 long 0e SECT 03 0000 [.const] gPatchInfoOffset_si_MsaaTexAsZStencil_PS 000000000014a960 long 0e SECT 03 0000 [.const] gPatchInfoCode_si_MsaaTexAsZStencil_PS 000000000014aa00 long 0e SECT 03 0000 [.const] gShaderCode_si_VolTex_PS 000000000014aa50 long 0e SECT 03 0000 [.const] gShRegisters_si_VolTex_PS 000000000014aa60 long 0e SECT 03 0000 [.const] gContextRegisters_si_VolTex_PS 000000000014aaa0 long 0e SECT 03 0000 [.const] gUserElementTable_si_VolTex_PS 000000000014aad0 long 0e SECT 03 0000 [.const] gInSemantics_si_VolTex_PS 000000000014aae4 long 0e SECT 03 0000 [.const] gPatchInfoOffset_si_VolTex_PS 000000000014aaf0 long 0e SECT 03 0000 [.const] gPatchInfoCode_si_VolTex_PS 000000000014ab90 long 0e SECT 03 0000 [.const] gShaderCode_si_AAText_PS 000000000014ac60 long 0e SECT 03 0000 [.const] gShRegisters_si_AAText_PS 000000000014ac70 long 0e SECT 03 0000 [.const] gContextRegisters_si_AAText_PS 000000000014acb0 long 0e SECT 03 0000 [.const] gUserElementTable_si_AAText_PS 000000000014ad00 long 0e SECT 03 0000 [.const] gInSemantics_si_AAText_PS 000000000014ad14 long 0e SECT 03 0000 [.const] gPatchInfoOffset_si_AAText_PS 000000000014ad20 long 0e SECT 03 0000 [.const] gPatchInfoCode_si_AAText_PS 000000000014adc0 long 0e SECT 03 0000 [.const] gShaderCode_si_SlowAAText_PS 000000000014ae80 long 0e SECT 03 0000 [.const] gShRegisters_si_SlowAAText_PS 000000000014ae90 long 0e SECT 03 0000 [.const] gContextRegisters_si_SlowAAText_PS 000000000014aed0 long 0e SECT 03 0000 [.const] gUserElementTable_si_SlowAAText_PS 000000000014af30 long 0e SECT 03 0000 [.const] gInSemantics_si_SlowAAText_PS 000000000014af58 long 0e SECT 03 0000 [.const] gPatchInfoOffset_si_SlowAAText_PS 000000000014af60 long 0e SECT 03 0000 [.const] gPatchInfoCode_si_SlowAAText_PS 000000000014b000 long 0e SECT 03 0000 [.const] gShaderCode_si_ClearTypeGamma_PS 000000000014b180 long 0e SECT 03 0000 [.const] gShRegisters_si_ClearTypeGamma_PS 000000000014b190 long 0e SECT 03 0000 [.const] gContextRegisters_si_ClearTypeGamma_PS 000000000014b1d0 long 0e SECT 03 0000 [.const] gUserElementTable_si_ClearTypeGamma_PS 000000000014b220 long 0e SECT 03 0000 [.const] gInSemantics_si_ClearTypeGamma_PS 000000000014b248 long 0e SECT 03 0000 [.const] gPatchInfoOffset_si_ClearTypeGamma_PS 000000000014b250 long 0e SECT 03 0000 [.const] gPatchInfoCode_si_ClearTypeGamma_PS 000000000014b2f0 long 0e SECT 03 0000 [.const] gShaderCode_si_TexColorKey_PS 000000000014b430 long 0e SECT 03 0000 [.const] gShRegisters_si_TexColorKey_PS 000000000014b440 long 0e SECT 03 0000 [.const] gContextRegisters_si_TexColorKey_PS 000000000014b480 long 0e SECT 03 0000 [.const] gUserElementTable_si_TexColorKey_PS 000000000014b4e0 long 0e SECT 03 0000 [.const] gInSemantics_si_TexColorKey_PS 000000000014b508 long 0e SECT 03 0000 [.const] gPatchInfoOffset_si_TexColorKey_PS 000000000014b510 long 0e SECT 03 0000 [.const] gPatchInfoCode_si_TexColorKey_PS 000000000014b5b0 long 0e SECT 03 0000 [.const] gShaderCode_si_TexSrcColorKey_PS 000000000014b670 long 0e SECT 03 0000 [.const] gShRegisters_si_TexSrcColorKey_PS 000000000014b680 long 0e SECT 03 0000 [.const] gContextRegisters_si_TexSrcColorKey_PS 000000000014b6c0 long 0e SECT 03 0000 [.const] gUserElementTable_si_TexSrcColorKey_PS 000000000014b710 long 0e SECT 03 0000 [.const] gInSemantics_si_TexSrcColorKey_PS 000000000014b724 long 0e SECT 03 0000 [.const] gPatchInfoOffset_si_TexSrcColorKey_PS 000000000014b730 long 0e SECT 03 0000 [.const] gPatchInfoCode_si_TexSrcColorKey_PS 000000000014b7d0 long 0e SECT 03 0000 [.const] gShaderCode_si_TexMulConst_PS 000000000014b830 long 0e SECT 03 0000 [.const] gShRegisters_si_TexMulConst_PS 000000000014b840 long 0e SECT 03 0000 [.const] gContextRegisters_si_TexMulConst_PS 000000000014b880 long 0e SECT 03 0000 [.const] gUserElementTable_si_TexMulConst_PS 000000000014b8d0 long 0e SECT 03 0000 [.const] gInSemantics_si_TexMulConst_PS 000000000014b8e4 long 0e SECT 03 0000 [.const] gPatchInfoOffset_si_TexMulConst_PS 000000000014b8f0 long 0e SECT 03 0000 [.const] gPatchInfoCode_si_TexMulConst_PS 000000000014b990 long 0e SECT 03 0000 [.const] gShaderCode_si_TexDither_PS 000000000014ba00 long 0e SECT 03 0000 [.const] gShRegisters_si_TexDither_PS 000000000014ba10 long 0e SECT 03 0000 [.const] gContextRegisters_si_TexDither_PS 000000000014ba50 long 0e SECT 03 0000 [.const] gUserElementTable_si_TexDither_PS 000000000014bab0 long 0e SECT 03 0000 [.const] gInSemantics_si_TexDither_PS 000000000014bac4 long 0e SECT 03 0000 [.const] gPatchInfoOffset_si_TexDither_PS 000000000014bad0 long 0e SECT 03 0000 [.const] gPatchInfoCode_si_TexDither_PS 000000000014bb70 long 0e SECT 03 0000 [.const] gShaderCode_si_YuvToRgb_PS 000000000014bc40 long 0e SECT 03 0000 [.const] gShRegisters_si_YuvToRgb_PS 000000000014bc50 long 0e SECT 03 0000 [.const] gContextRegisters_si_YuvToRgb_PS 000000000014bc90 long 0e SECT 03 0000 [.const] gUserElementTable_si_YuvToRgb_PS 000000000014bce0 long 0e SECT 03 0000 [.const] gInSemantics_si_YuvToRgb_PS 000000000014bcf4 long 0e SECT 03 0000 [.const] gPatchInfoOffset_si_YuvToRgb_PS 000000000014bd00 long 0e SECT 03 0000 [.const] gPatchInfoCode_si_YuvToRgb_PS 000000000014bda0 long 0e SECT 03 0000 [.const] gShaderCode_si_YuvIntUvToRgb_PS 000000000014be50 long 0e SECT 03 0000 [.const] gShRegisters_si_YuvIntUvToRgb_PS 000000000014be60 long 0e SECT 03 0000 [.const] gContextRegisters_si_YuvIntUvToRgb_PS 000000000014bea0 long 0e SECT 03 0000 [.const] gUserElementTable_si_YuvIntUvToRgb_PS 000000000014bf00 long 0e SECT 03 0000 [.const] gInSemantics_si_YuvIntUvToRgb_PS 000000000014bf14 long 0e SECT 03 0000 [.const] gPatchInfoOffset_si_YuvIntUvToRgb_PS 000000000014bf20 long 0e SECT 03 0000 [.const] gPatchInfoCode_si_YuvIntUvToRgb_PS 000000000014bfc0 long 0e SECT 03 0000 [.const] gShaderCode_si_YuvIntUvToYuy2_PS 000000000014c060 long 0e SECT 03 0000 [.const] gShRegisters_si_YuvIntUvToYuy2_PS 000000000014c070 long 0e SECT 03 0000 [.const] gContextRegisters_si_YuvIntUvToYuy2_PS 000000000014c0b0 long 0e SECT 03 0000 [.const] gUserElementTable_si_YuvIntUvToYuy2_PS 000000000014c110 long 0e SECT 03 0000 [.const] gInSemantics_si_YuvIntUvToYuy2_PS 000000000014c124 long 0e SECT 03 0000 [.const] gPatchInfoOffset_si_YuvIntUvToYuy2_PS 000000000014c130 long 0e SECT 03 0000 [.const] gPatchInfoCode_si_YuvIntUvToYuy2_PS 000000000014c1d0 long 0e SECT 03 0000 [.const] gShaderCode_si_YuvToYuy2_PS 000000000014c280 long 0e SECT 03 0000 [.const] gShRegisters_si_YuvToYuy2_PS 000000000014c290 long 0e SECT 03 0000 [.const] gContextRegisters_si_YuvToYuy2_PS 000000000014c2d0 long 0e SECT 03 0000 [.const] gUserElementTable_si_YuvToYuy2_PS 000000000014c320 long 0e SECT 03 0000 [.const] gInSemantics_si_YuvToYuy2_PS 000000000014c334 long 0e SECT 03 0000 [.const] gPatchInfoOffset_si_YuvToYuy2_PS 000000000014c340 long 0e SECT 03 0000 [.const] gPatchInfoCode_si_YuvToYuy2_PS 000000000014c3e0 long 0e SECT 03 0000 [.const] gShaderCode_si_MsaaFMaskResolve2_PS 000000000014c480 long 0e SECT 03 0000 [.const] gShRegisters_si_MsaaFMaskResolve2_PS 000000000014c490 long 0e SECT 03 0000 [.const] gContextRegisters_si_MsaaFMaskResolve2_PS 000000000014c4d0 long 0e SECT 03 0000 [.const] gUserElementTable_si_MsaaFMaskResolve2_PS 000000000014c500 long 0e SECT 03 0000 [.const] gInSemantics_si_MsaaFMaskResolve2_PS 000000000014c514 long 0e SECT 03 0000 [.const] gPatchInfoOffset_si_MsaaFMaskResolve2_PS 000000000014c520 long 0e SECT 03 0000 [.const] gPatchInfoCode_si_MsaaFMaskResolve2_PS 000000000014c5c0 long 0e SECT 03 0000 [.const] gShaderCode_si_MsaaFMaskResolve4_PS 000000000014c6f0 long 0e SECT 03 0000 [.const] gShRegisters_si_MsaaFMaskResolve4_PS 000000000014c700 long 0e SECT 03 0000 [.const] gContextRegisters_si_MsaaFMaskResolve4_PS 000000000014c740 long 0e SECT 03 0000 [.const] gUserElementTable_si_MsaaFMaskResolve4_PS 000000000014c770 long 0e SECT 03 0000 [.const] gInSemantics_si_MsaaFMaskResolve4_PS 000000000014c784 long 0e SECT 03 0000 [.const] gPatchInfoOffset_si_MsaaFMaskResolve4_PS 000000000014c790 long 0e SECT 03 0000 [.const] gPatchInfoCode_si_MsaaFMaskResolve4_PS 000000000014c830 long 0e SECT 03 0000 [.const] gShaderCode_si_MsaaFMaskResolve8_PS 000000000014ca00 long 0e SECT 03 0000 [.const] gShRegisters_si_MsaaFMaskResolve8_PS 000000000014ca10 long 0e SECT 03 0000 [.const] gContextRegisters_si_MsaaFMaskResolve8_PS 000000000014ca50 long 0e SECT 03 0000 [.const] gUserElementTable_si_MsaaFMaskResolve8_PS 000000000014ca80 long 0e SECT 03 0000 [.const] gInSemantics_si_MsaaFMaskResolve8_PS 000000000014ca94 long 0e SECT 03 0000 [.const] gPatchInfoOffset_si_MsaaFMaskResolve8_PS 000000000014caa0 long 0e SECT 03 0000 [.const] gPatchInfoCode_si_MsaaFMaskResolve8_PS 000000000014cb40 long 0e SECT 03 0000 [.const] gShaderCode_si_MsaaFMaskResolve2Frag4Samp_PS 000000000014cce0 long 0e SECT 03 0000 [.const] gShRegisters_si_MsaaFMaskResolve2Frag4Samp_PS 000000000014ccf0 long 0e SECT 03 0000 [.const] gContextRegisters_si_MsaaFMaskResolve2Frag4Samp_PS 000000000014cd30 long 0e SECT 03 0000 [.const] gUserElementTable_si_MsaaFMaskResolve2Frag4Samp_PS 000000000014cd60 long 0e SECT 03 0000 [.const] gInSemantics_si_MsaaFMaskResolve2Frag4Samp_PS 000000000014cd74 long 0e SECT 03 0000 [.const] gPatchInfoOffset_si_MsaaFMaskResolve2Frag4Samp_PS 000000000014cd80 long 0e SECT 03 0000 [.const] gPatchInfoCode_si_MsaaFMaskResolve2Frag4Samp_PS 000000000014ce20 long 0e SECT 03 0000 [.const] gShaderCode_si_MsaaFMaskResolve2Frag8Samp_PS 000000000014d160 long 0e SECT 03 0000 [.const] gShRegisters_si_MsaaFMaskResolve2Frag8Samp_PS 000000000014d170 long 0e SECT 03 0000 [.const] gContextRegisters_si_MsaaFMaskResolve2Frag8Samp_PS 000000000014d1b0 long 0e SECT 03 0000 [.const] gUserElementTable_si_MsaaFMaskResolve2Frag8Samp_PS 000000000014d1e0 long 0e SECT 03 0000 [.const] gInSemantics_si_MsaaFMaskResolve2Frag8Samp_PS 000000000014d1f4 long 0e SECT 03 0000 [.const] gPatchInfoOffset_si_MsaaFMaskResolve2Frag8Samp_PS 000000000014d200 long 0e SECT 03 0000 [.const] gPatchInfoCode_si_MsaaFMaskResolve2Frag8Samp_PS 000000000014d2a0 long 0e SECT 03 0000 [.const] gShaderCode_si_MsaaFMaskResolve2Frag16Samp_PS 000000000014d930 long 0e SECT 03 0000 [.const] gShRegisters_si_MsaaFMaskResolve2Frag16Samp_PS 000000000014d940 long 0e SECT 03 0000 [.const] gContextRegisters_si_MsaaFMaskResolve2Frag16Samp_PS 000000000014d980 long 0e SECT 03 0000 [.const] gUserElementTable_si_MsaaFMaskResolve2Frag16Samp_PS 000000000014d9b0 long 0e SECT 03 0000 [.const] gInSemantics_si_MsaaFMaskResolve2Frag16Samp_PS 000000000014d9c4 long 0e SECT 03 0000 [.const] gPatchInfoOffset_si_MsaaFMaskResolve2Frag16Samp_PS 000000000014d9d0 long 0e SECT 03 0000 [.const] gPatchInfoCode_si_MsaaFMaskResolve2Frag16Samp_PS 000000000014da70 long 0e SECT 03 0000 [.const] gShaderCode_si_MsaaFMaskResolve4Frag8Samp_PS 000000000014dd30 long 0e SECT 03 0000 [.const] gShRegisters_si_MsaaFMaskResolve4Frag8Samp_PS 000000000014dd40 long 0e SECT 03 0000 [.const] gContextRegisters_si_MsaaFMaskResolve4Frag8Samp_PS 000000000014dd80 long 0e SECT 03 0000 [.const] gUserElementTable_si_MsaaFMaskResolve4Frag8Samp_PS 000000000014ddb0 long 0e SECT 03 0000 [.const] gInSemantics_si_MsaaFMaskResolve4Frag8Samp_PS 000000000014ddc4 long 0e SECT 03 0000 [.const] gPatchInfoOffset_si_MsaaFMaskResolve4Frag8Samp_PS 000000000014ddd0 long 0e SECT 03 0000 [.const] gPatchInfoCode_si_MsaaFMaskResolve4Frag8Samp_PS 000000000014de70 long 0e SECT 03 0000 [.const] gShaderCode_si_MsaaFMaskResolve4Frag16Samp_PS 000000000014e480 long 0e SECT 03 0000 [.const] gShRegisters_si_MsaaFMaskResolve4Frag16Samp_PS 000000000014e490 long 0e SECT 03 0000 [.const] gContextRegisters_si_MsaaFMaskResolve4Frag16Samp_PS 000000000014e4d0 long 0e SECT 03 0000 [.const] gUserElementTable_si_MsaaFMaskResolve4Frag16Samp_PS 000000000014e500 long 0e SECT 03 0000 [.const] gInSemantics_si_MsaaFMaskResolve4Frag16Samp_PS 000000000014e514 long 0e SECT 03 0000 [.const] gPatchInfoOffset_si_MsaaFMaskResolve4Frag16Samp_PS 000000000014e520 long 0e SECT 03 0000 [.const] gPatchInfoCode_si_MsaaFMaskResolve4Frag16Samp_PS 000000000014e5c0 long 0e SECT 03 0000 [.const] gShaderCode_si_MsaaFMaskResolve8Frag16Samp_PS 000000000014eb10 long 0e SECT 03 0000 [.const] gShRegisters_si_MsaaFMaskResolve8Frag16Samp_PS 000000000014eb20 long 0e SECT 03 0000 [.const] gContextRegisters_si_MsaaFMaskResolve8Frag16Samp_PS 000000000014eb60 long 0e SECT 03 0000 [.const] gUserElementTable_si_MsaaFMaskResolve8Frag16Samp_PS 000000000014eb90 long 0e SECT 03 0000 [.const] gInSemantics_si_MsaaFMaskResolve8Frag16Samp_PS 000000000014eba4 long 0e SECT 03 0000 [.const] gPatchInfoOffset_si_MsaaFMaskResolve8Frag16Samp_PS 000000000014ebb0 long 0e SECT 03 0000 [.const] gPatchInfoCode_si_MsaaFMaskResolve8Frag16Samp_PS 000000000014ec50 long 0e SECT 03 0000 [.const] gShaderCode_si_ColorTransform_PS 000000000014eea0 long 0e SECT 03 0000 [.const] gShRegisters_si_ColorTransform_PS 000000000014eeb0 long 0e SECT 03 0000 [.const] gContextRegisters_si_ColorTransform_PS 000000000014eef0 long 0e SECT 03 0000 [.const] gUserElementTable_si_ColorTransform_PS 000000000014ef40 long 0e SECT 03 0000 [.const] gInSemantics_si_ColorTransform_PS 000000000014ef54 long 0e SECT 03 0000 [.const] gPatchInfoOffset_si_ColorTransform_PS 000000000014ef60 long 0e SECT 03 0000 [.const] gPatchInfoCode_si_ColorTransform_PS 000000000014f000 long 0e SECT 03 0000 [.const] gShaderCode_si_NonEvenLinearFilter1D_PS 000000000014f130 long 0e SECT 03 0000 [.const] gShRegisters_si_NonEvenLinearFilter1D_PS 000000000014f140 long 0e SECT 03 0000 [.const] gContextRegisters_si_NonEvenLinearFilter1D_PS 000000000014f180 long 0e SECT 03 0000 [.const] gUserElementTable_si_NonEvenLinearFilter1D_PS 000000000014f1d0 long 0e SECT 03 0000 [.const] gInSemantics_si_NonEvenLinearFilter1D_PS 000000000014f1e4 long 0e SECT 03 0000 [.const] gPatchInfoOffset_si_NonEvenLinearFilter1D_PS 000000000014f1f0 long 0e SECT 03 0000 [.const] gPatchInfoCode_si_NonEvenLinearFilter1D_PS 000000000014f290 long 0e SECT 03 0000 [.const] gShaderCode_si_NonEvenLinearFilter2D_PS 000000000014f4c0 long 0e SECT 03 0000 [.const] gShRegisters_si_NonEvenLinearFilter2D_PS 000000000014f4d0 long 0e SECT 03 0000 [.const] gContextRegisters_si_NonEvenLinearFilter2D_PS 000000000014f510 long 0e SECT 03 0000 [.const] gUserElementTable_si_NonEvenLinearFilter2D_PS 000000000014f560 long 0e SECT 03 0000 [.const] gInSemantics_si_NonEvenLinearFilter2D_PS 000000000014f574 long 0e SECT 03 0000 [.const] gPatchInfoOffset_si_NonEvenLinearFilter2D_PS 000000000014f580 long 0e SECT 03 0000 [.const] gPatchInfoCode_si_NonEvenLinearFilter2D_PS 000000000014f620 long 0e SECT 03 0000 [.const] gShaderCode_si_NonEvenLinearFilter3D_PS 000000000014f930 long 0e SECT 03 0000 [.const] gShRegisters_si_NonEvenLinearFilter3D_PS 000000000014f940 long 0e SECT 03 0000 [.const] gContextRegisters_si_NonEvenLinearFilter3D_PS 000000000014f980 long 0e SECT 03 0000 [.const] gUserElementTable_si_NonEvenLinearFilter3D_PS 000000000014f9d0 long 0e SECT 03 0000 [.const] gInSemantics_si_NonEvenLinearFilter3D_PS 000000000014f9e4 long 0e SECT 03 0000 [.const] gPatchInfoOffset_si_NonEvenLinearFilter3D_PS 000000000014f9f0 long 0e SECT 03 0000 [.const] gPatchInfoCode_si_NonEvenLinearFilter3D_PS 000000000014fa90 long 0e SECT 03 0000 [.const] gShaderCode_si_MLAACalcSepEdgeLength_PS 000000000014fea0 long 0e SECT 03 0000 [.const] gShRegisters_si_MLAACalcSepEdgeLength_PS 000000000014feb0 long 0e SECT 03 0000 [.const] gContextRegisters_si_MLAACalcSepEdgeLength_PS 000000000014fef0 long 0e SECT 03 0000 [.const] gUserElementTable_si_MLAACalcSepEdgeLength_PS 000000000014ff20 long 0e SECT 03 0000 [.const] gInSemantics_si_MLAACalcSepEdgeLength_PS 000000000014ff34 long 0e SECT 03 0000 [.const] gPatchInfoOffset_si_MLAACalcSepEdgeLength_PS 000000000014ff40 long 0e SECT 03 0000 [.const] gPatchInfoCode_si_MLAACalcSepEdgeLength_PS 0000000000150080 long 0e SECT 03 0000 [.const] gShaderCode_si_MLAACalcSepEdgeLengthFast_PS 00000000001506f0 long 0e SECT 03 0000 [.const] gShRegisters_si_MLAACalcSepEdgeLengthFast_PS 0000000000150700 long 0e SECT 03 0000 [.const] gContextRegisters_si_MLAACalcSepEdgeLengthFast_PS 0000000000150740 long 0e SECT 03 0000 [.const] gUserElementTable_si_MLAACalcSepEdgeLengthFast_PS 0000000000150770 long 0e SECT 03 0000 [.const] gInSemantics_si_MLAACalcSepEdgeLengthFast_PS 0000000000150784 long 0e SECT 03 0000 [.const] gPatchInfoOffset_si_MLAACalcSepEdgeLengthFast_PS 0000000000150790 long 0e SECT 03 0000 [.const] gPatchInfoCode_si_MLAACalcSepEdgeLengthFast_PS 0000000000150830 long 0e SECT 03 0000 [.const] gShaderCode_si_MLAACalcSepEdgeLengthInitial_PS 0000000000150a30 long 0e SECT 03 0000 [.const] gShRegisters_si_MLAACalcSepEdgeLengthInitial_PS 0000000000150a40 long 0e SECT 03 0000 [.const] gContextRegisters_si_MLAACalcSepEdgeLengthInitial_PS 0000000000150a80 long 0e SECT 03 0000 [.const] gUserElementTable_si_MLAACalcSepEdgeLengthInitial_PS 0000000000150ab0 long 0e SECT 03 0000 [.const] gInSemantics_si_MLAACalcSepEdgeLengthInitial_PS 0000000000150ac4 long 0e SECT 03 0000 [.const] gPatchInfoOffset_si_MLAACalcSepEdgeLengthInitial_PS 0000000000150ad0 long 0e SECT 03 0000 [.const] gPatchInfoCode_si_MLAACalcSepEdgeLengthInitial_PS 0000000000150c10 long 0e SECT 03 0000 [.const] gShaderCode_si_MLAAFinalBlend_PS 0000000000151530 long 0e SECT 03 0000 [.const] gShRegisters_si_MLAAFinalBlend_PS 0000000000151540 long 0e SECT 03 0000 [.const] gContextRegisters_si_MLAAFinalBlend_PS 0000000000151580 long 0e SECT 03 0000 [.const] gUserElementTable_si_MLAAFinalBlend_PS 00000000001515a0 long 0e SECT 03 0000 [.const] gInSemantics_si_MLAAFinalBlend_PS 00000000001515b4 long 0e SECT 03 0000 [.const] gPatchInfoOffset_si_MLAAFinalBlend_PS 00000000001515c0 long 0e SECT 03 0000 [.const] gPatchInfoCode_si_MLAAFinalBlend_PS 0000000000151660 long 0e SECT 03 0000 [.const] gShaderCode_si_MLAAFinalBlendFast_PS 0000000000152010 long 0e SECT 03 0000 [.const] gShRegisters_si_MLAAFinalBlendFast_PS 0000000000152020 long 0e SECT 03 0000 [.const] gContextRegisters_si_MLAAFinalBlendFast_PS 0000000000152060 long 0e SECT 03 0000 [.const] gUserElementTable_si_MLAAFinalBlendFast_PS 0000000000152090 long 0e SECT 03 0000 [.const] gInSemantics_si_MLAAFinalBlendFast_PS 00000000001520a4 long 0e SECT 03 0000 [.const] gPatchInfoOffset_si_MLAAFinalBlendFast_PS 00000000001520b0 long 0e SECT 03 0000 [.const] gPatchInfoCode_si_MLAAFinalBlendFast_PS 0000000000152150 long 0e SECT 03 0000 [.const] gShaderCode_si_MLAAFindSepEdge_PS 0000000000152250 long 0e SECT 03 0000 [.const] gShRegisters_si_MLAAFindSepEdge_PS 0000000000152260 long 0e SECT 03 0000 [.const] gContextRegisters_si_MLAAFindSepEdge_PS 00000000001522a0 long 0e SECT 03 0000 [.const] gUserElementTable_si_MLAAFindSepEdge_PS 00000000001522d0 long 0e SECT 03 0000 [.const] gInSemantics_si_MLAAFindSepEdge_PS 00000000001522e4 long 0e SECT 03 0000 [.const] gPatchInfoOffset_si_MLAAFindSepEdge_PS 00000000001522f0 long 0e SECT 03 0000 [.const] gPatchInfoCode_si_MLAAFindSepEdge_PS 0000000000152390 long 0e SECT 03 0000 [.const] gShaderCode_si_GenZRangeTex_PS 00000000001526f0 long 0e SECT 03 0000 [.const] gShRegisters_si_GenZRangeTex_PS 0000000000152700 long 0e SECT 03 0000 [.const] gContextRegisters_si_GenZRangeTex_PS 0000000000152740 long 0e SECT 03 0000 [.const] gUserElementTable_si_GenZRangeTex_PS 0000000000152790 long 0e SECT 03 0000 [.const] gInSemantics_si_GenZRangeTex_PS 00000000001527a4 long 0e SECT 03 0000 [.const] gPatchInfoOffset_si_GenZRangeTex_PS 00000000001527b0 long 0e SECT 03 0000 [.const] gPatchInfoCode_si_GenZRangeTex_PS 0000000000152850 long 0e SECT 03 0000 [.const] gShaderCode_si_GenZRangeMip_PS 00000000001528f0 long 0e SECT 03 0000 [.const] gShRegisters_si_GenZRangeMip_PS 0000000000152900 long 0e SECT 03 0000 [.const] gContextRegisters_si_GenZRangeMip_PS 0000000000152940 long 0e SECT 03 0000 [.const] gUserElementTable_si_GenZRangeMip_PS 0000000000152990 long 0e SECT 03 0000 [.const] gInSemantics_si_GenZRangeMip_PS 00000000001529a4 long 0e SECT 03 0000 [.const] gPatchInfoOffset_si_GenZRangeMip_PS 00000000001529b0 long 0e SECT 03 0000 [.const] gPatchInfoCode_si_GenZRangeMip_PS 0000000000152a50 long 0e SECT 03 0000 [.const] gShaderCode_si_GenZRangeMipOdd_PS 0000000000152c50 long 0e SECT 03 0000 [.const] gShRegisters_si_GenZRangeMipOdd_PS 0000000000152c60 long 0e SECT 03 0000 [.const] gContextRegisters_si_GenZRangeMipOdd_PS 0000000000152ca0 long 0e SECT 03 0000 [.const] gUserElementTable_si_GenZRangeMipOdd_PS 0000000000152cd0 long 0e SECT 03 0000 [.const] gInSemantics_si_GenZRangeMipOdd_PS 0000000000152ce4 long 0e SECT 03 0000 [.const] gPatchInfoOffset_si_GenZRangeMipOdd_PS 0000000000152cf0 long 0e SECT 03 0000 [.const] gPatchInfoCode_si_GenZRangeMipOdd_PS 0000000000152d90 long 0e SECT 03 0000 [.const] gShaderCode_si_Composite_PS 0000000000153490 long 0e SECT 03 0000 [.const] gShRegisters_si_Composite_PS 00000000001534a0 long 0e SECT 03 0000 [.const] gContextRegisters_si_Composite_PS 00000000001534e0 long 0e SECT 03 0000 [.const] gUserElementTable_si_Composite_PS 0000000000153530 long 0e SECT 03 0000 [.const] gInSemantics_si_Composite_PS 0000000000153558 long 0e SECT 03 0000 [.const] gPatchInfoOffset_si_Composite_PS 0000000000153560 long 0e SECT 03 0000 [.const] gPatchInfoCode_si_Composite_PS 0000000000153600 long 0e SECT 03 0000 [.const] gShaderCode_si_BufferClear_CS 0000000000153630 long 0e SECT 03 0000 [.const] gShRegisters_si_BufferClear_CS 0000000000153658 long 0e SECT 03 0000 [.const] gContextRegisters_si_BufferClear_CS 0000000000153660 long 0e SECT 03 0000 [.const] gUserElementTable_si_BufferClear_CS 0000000000153690 long 0e SECT 03 0000 [.const] gShaderCode_si_BufferCopy_CS 00000000001536b0 long 0e SECT 03 0000 [.const] gShRegisters_si_BufferCopy_CS 00000000001536d8 long 0e SECT 03 0000 [.const] gContextRegisters_si_BufferCopy_CS 00000000001536e0 long 0e SECT 03 0000 [.const] gUserElementTable_si_BufferCopy_CS 0000000000153710 long 0e SECT 03 0000 [.const] gShaderCode_si_SurfaceClear_CS 0000000000153770 long 0e SECT 03 0000 [.const] gShRegisters_si_SurfaceClear_CS 0000000000153798 long 0e SECT 03 0000 [.const] gContextRegisters_si_SurfaceClear_CS 00000000001537a0 long 0e SECT 03 0000 [.const] gUserElementTable_si_SurfaceClear_CS 00000000001537d0 long 0e SECT 03 0000 [.const] gShaderCode_si_LinGenDstCopy_CS 0000000000153850 long 0e SECT 03 0000 [.const] gShRegisters_si_LinGenDstCopy_CS 0000000000153878 long 0e SECT 03 0000 [.const] gContextRegisters_si_LinGenDstCopy_CS 0000000000153880 long 0e SECT 03 0000 [.const] gUserElementTable_si_LinGenDstCopy_CS 00000000001538d0 long 0e SECT 03 0000 [.const] gShaderCode_si_LinGenSrcCopy_CS 0000000000153940 long 0e SECT 03 0000 [.const] gShRegisters_si_LinGenSrcCopy_CS 0000000000153968 long 0e SECT 03 0000 [.const] gContextRegisters_si_LinGenSrcCopy_CS 0000000000153970 long 0e SECT 03 0000 [.const] gUserElementTable_si_LinGenSrcCopy_CS 00000000001539c0 long 0e SECT 03 0000 [.const] gShaderCode_si_LinGenSrcDstCopy_CS 0000000000153a40 long 0e SECT 03 0000 [.const] gShRegisters_si_LinGenSrcDstCopy_CS 0000000000153a68 long 0e SECT 03 0000 [.const] gContextRegisters_si_LinGenSrcDstCopy_CS 0000000000153a70 long 0e SECT 03 0000 [.const] gUserElementTable_si_LinGenSrcDstCopy_CS 0000000000153ac0 long 0e SECT 03 0000 [.const] gShaderCode_si_HtileCopy_CS 0000000000153af0 long 0e SECT 03 0000 [.const] gShRegisters_si_HtileCopy_CS 0000000000153b18 long 0e SECT 03 0000 [.const] gContextRegisters_si_HtileCopy_CS 0000000000153b20 long 0e SECT 03 0000 [.const] gUserElementTable_si_HtileCopy_CS 0000000000153b50 long 0e SECT 03 0000 [.const] gShaderCode_si_MsaaFMaskExpand2Samp_CS 0000000000153bf0 long 0e SECT 03 0000 [.const] gShRegisters_si_MsaaFMaskExpand2Samp_CS 0000000000153c18 long 0e SECT 03 0000 [.const] gContextRegisters_si_MsaaFMaskExpand2Samp_CS 0000000000153c20 long 0e SECT 03 0000 [.const] gUserElementTable_si_MsaaFMaskExpand2Samp_CS 0000000000153c40 long 0e SECT 03 0000 [.const] gShaderCode_si_MsaaFMaskExpand4Samp_CS 0000000000153d50 long 0e SECT 03 0000 [.const] gShRegisters_si_MsaaFMaskExpand4Samp_CS 0000000000153d78 long 0e SECT 03 0000 [.const] gContextRegisters_si_MsaaFMaskExpand4Samp_CS 0000000000153d80 long 0e SECT 03 0000 [.const] gUserElementTable_si_MsaaFMaskExpand4Samp_CS 0000000000153da0 long 0e SECT 03 0000 [.const] gShaderCode_si_MsaaFMaskExpand8Samp_CS 0000000000153f70 long 0e SECT 03 0000 [.const] gShRegisters_si_MsaaFMaskExpand8Samp_CS 0000000000153f98 long 0e SECT 03 0000 [.const] gContextRegisters_si_MsaaFMaskExpand8Samp_CS 0000000000153fa0 long 0e SECT 03 0000 [.const] gUserElementTable_si_MsaaFMaskExpand8Samp_CS 0000000000153fc0 long 0e SECT 03 0000 [.const] gShaderCode_si_FastDepthClear_CS 0000000000154020 long 0e SECT 03 0000 [.const] gShRegisters_si_FastDepthClear_CS 0000000000154048 long 0e SECT 03 0000 [.const] gContextRegisters_si_FastDepthClear_CS 0000000000154050 long 0e SECT 03 0000 [.const] gUserElementTable_si_FastDepthClear_CS 0000000000154080 long 0e SECT 03 0000 [.const] gShaderCode_si_FastDepthExpClear_CS 0000000000154110 long 0e SECT 03 0000 [.const] gShRegisters_si_FastDepthExpClear_CS 0000000000154138 long 0e SECT 03 0000 [.const] gContextRegisters_si_FastDepthExpClear_CS 0000000000154140 long 0e SECT 03 0000 [.const] gUserElementTable_si_FastDepthExpClear_CS 0000000000154170 long 0e SECT 03 0000 [.const] gShaderCode_si_LinGenDstRepackCopy_CS 0000000000154250 long 0e SECT 03 0000 [.const] gShRegisters_si_LinGenDstRepackCopy_CS 0000000000154278 long 0e SECT 03 0000 [.const] gContextRegisters_si_LinGenDstRepackCopy_CS 0000000000154280 long 0e SECT 03 0000 [.const] gUserElementTable_si_LinGenDstRepackCopy_CS 00000000001542d0 long 0e SECT 03 0000 [.const] gShaderCode_si_VolumeTexCopy_CS 0000000000154360 long 0e SECT 03 0000 [.const] gShRegisters_si_VolumeTexCopy_CS 0000000000154388 long 0e SECT 03 0000 [.const] gContextRegisters_si_VolumeTexCopy_CS 0000000000154390 long 0e SECT 03 0000 [.const] gUserElementTable_si_VolumeTexCopy_CS 00000000001543e0 long 0e SECT 03 0000 [.const] gShaderCode_si_GenerateHiS_PS 0000000000154480 long 0e SECT 03 0000 [.const] gShRegisters_si_GenerateHiS_PS 0000000000154490 long 0e SECT 03 0000 [.const] gContextRegisters_si_GenerateHiS_PS 00000000001544d0 long 0e SECT 03 0000 [.const] gUserElementTable_si_GenerateHiS_PS 0000000000154520 long 0e SECT 03 0000 [.const] gInSemantics_si_GenerateHiS_PS 0000000000154534 long 0e SECT 03 0000 [.const] gPatchInfoOffset_si_GenerateHiS_PS 0000000000154540 long 0e SECT 03 0000 [.const] gPatchInfoCode_si_GenerateHiS_PS 00000000001545e0 long 0e SECT 03 0000 [.const] gShaderCode_si_AdvAARes1_PS 0000000000154640 long 0e SECT 03 0000 [.const] gShRegisters_si_AdvAARes1_PS 0000000000154650 long 0e SECT 03 0000 [.const] gContextRegisters_si_AdvAARes1_PS 0000000000154690 long 0e SECT 03 0000 [.const] gUserElementTable_si_AdvAARes1_PS 00000000001546c0 long 0e SECT 03 0000 [.const] gInSemantics_si_AdvAARes1_PS 00000000001546d4 long 0e SECT 03 0000 [.const] gPatchInfoOffset_si_AdvAARes1_PS 00000000001546e0 long 0e SECT 03 0000 [.const] gPatchInfoCode_si_AdvAARes1_PS 0000000000154820 long 0e SECT 03 0000 [.const] gShaderCode_si_AdvAAEdgeMask4Samp_PS 0000000000154a00 long 0e SECT 03 0000 [.const] gShRegisters_si_AdvAAEdgeMask4Samp_PS 0000000000154a10 long 0e SECT 03 0000 [.const] gContextRegisters_si_AdvAAEdgeMask4Samp_PS 0000000000154a50 long 0e SECT 03 0000 [.const] gUserElementTable_si_AdvAAEdgeMask4Samp_PS 0000000000154a80 long 0e SECT 03 0000 [.const] gInSemantics_si_AdvAAEdgeMask4Samp_PS 0000000000154a94 long 0e SECT 03 0000 [.const] gPatchInfoOffset_si_AdvAAEdgeMask4Samp_PS 0000000000154aa0 long 0e SECT 03 0000 [.const] gPatchInfoCode_si_AdvAAEdgeMask4Samp_PS 0000000000154c80 long 0e SECT 03 0000 [.const] gShaderCode_si_AdvAAEdgeMask8Samp_PS 0000000000154fa0 long 0e SECT 03 0000 [.const] gShRegisters_si_AdvAAEdgeMask8Samp_PS 0000000000154fb0 long 0e SECT 03 0000 [.const] gContextRegisters_si_AdvAAEdgeMask8Samp_PS 0000000000154ff0 long 0e SECT 03 0000 [.const] gUserElementTable_si_AdvAAEdgeMask8Samp_PS 0000000000155020 long 0e SECT 03 0000 [.const] gInSemantics_si_AdvAAEdgeMask8Samp_PS 0000000000155034 long 0e SECT 03 0000 [.const] gPatchInfoOffset_si_AdvAAEdgeMask8Samp_PS 0000000000155040 long 0e SECT 03 0000 [.const] gPatchInfoCode_si_AdvAAEdgeMask8Samp_PS 0000000000155220 long 0e SECT 03 0000 [.const] gShaderCode_si_AdvAAFilterMaskFast_PS 0000000000155460 long 0e SECT 03 0000 [.const] gShRegisters_si_AdvAAFilterMaskFast_PS 0000000000155470 long 0e SECT 03 0000 [.const] gContextRegisters_si_AdvAAFilterMaskFast_PS 00000000001554b0 long 0e SECT 03 0000 [.const] gUserElementTable_si_AdvAAFilterMaskFast_PS 00000000001554d0 long 0e SECT 03 0000 [.const] gInSemantics_si_AdvAAFilterMaskFast_PS 00000000001554e4 long 0e SECT 03 0000 [.const] gPatchInfoOffset_si_AdvAAFilterMaskFast_PS 00000000001554f0 long 0e SECT 03 0000 [.const] gPatchInfoCode_si_AdvAAFilterMaskFast_PS 0000000000155590 long 0e SECT 03 0000 [.const] gShaderCode_si_AdvAAGrad4SampNoReZ_PS 0000000000156e90 long 0e SECT 03 0000 [.const] gShRegisters_si_AdvAAGrad4SampNoReZ_PS 0000000000156ea0 long 0e SECT 03 0000 [.const] gContextRegisters_si_AdvAAGrad4SampNoReZ_PS 0000000000156ee0 long 0e SECT 03 0000 [.const] gUserElementTable_si_AdvAAGrad4SampNoReZ_PS 0000000000156f10 long 0e SECT 03 0000 [.const] gInSemantics_si_AdvAAGrad4SampNoReZ_PS 0000000000156f24 long 0e SECT 03 0000 [.const] gPatchInfoOffset_si_AdvAAGrad4SampNoReZ_PS 0000000000156f30 long 0e SECT 03 0000 [.const] gPatchInfoCode_si_AdvAAGrad4SampNoReZ_PS 0000000000156fd0 long 0e SECT 03 0000 [.const] gShaderCode_si_AdvAAGrad8SampNoReZ_PS 0000000000159c30 long 0e SECT 03 0000 [.const] gShRegisters_si_AdvAAGrad8SampNoReZ_PS 0000000000159c40 long 0e SECT 03 0000 [.const] gContextRegisters_si_AdvAAGrad8SampNoReZ_PS 0000000000159c80 long 0e SECT 03 0000 [.const] gUserElementTable_si_AdvAAGrad8SampNoReZ_PS 0000000000159cb0 long 0e SECT 03 0000 [.const] gInSemantics_si_AdvAAGrad8SampNoReZ_PS 0000000000159cc4 long 0e SECT 03 0000 [.const] gPatchInfoOffset_si_AdvAAGrad8SampNoReZ_PS 0000000000159cd0 long 0e SECT 03 0000 [.const] gPatchInfoCode_si_AdvAAGrad8SampNoReZ_PS 0000000000159d70 long 0e SECT 03 0000 [.const] gShaderCode_si_AdvAAEdG4SampNoReZ_PS 000000000015bf60 long 0e SECT 03 0000 [.const] gShRegisters_si_AdvAAEdG4SampNoReZ_PS 000000000015bf70 long 0e SECT 03 0000 [.const] gContextRegisters_si_AdvAAEdG4SampNoReZ_PS 000000000015bfb0 long 0e SECT 03 0000 [.const] gUserElementTable_si_AdvAAEdG4SampNoReZ_PS 000000000015bfe0 long 0e SECT 03 0000 [.const] gInSemantics_si_AdvAAEdG4SampNoReZ_PS 000000000015bff4 long 0e SECT 03 0000 [.const] gPatchInfoOffset_si_AdvAAEdG4SampNoReZ_PS 000000000015c000 long 0e SECT 03 0000 [.const] gPatchInfoCode_si_AdvAAEdG4SampNoReZ_PS 000000000015c0a0 long 0e SECT 03 0000 [.const] gShaderCode_si_AdvAAEdG8SampNoReZ_PS 0000000000160310 long 0e SECT 03 0000 [.const] gShRegisters_si_AdvAAEdG8SampNoReZ_PS 0000000000160320 long 0e SECT 03 0000 [.const] gContextRegisters_si_AdvAAEdG8SampNoReZ_PS 0000000000160360 long 0e SECT 03 0000 [.const] gUserElementTable_si_AdvAAEdG8SampNoReZ_PS 0000000000160390 long 0e SECT 03 0000 [.const] gInSemantics_si_AdvAAEdG8SampNoReZ_PS 00000000001603a4 long 0e SECT 03 0000 [.const] gPatchInfoOffset_si_AdvAAEdG8SampNoReZ_PS 00000000001603b0 long 0e SECT 03 0000 [.const] gPatchInfoCode_si_AdvAAEdG8SampNoReZ_PS 0000000000160450 long 0e SECT 03 0000 [.const] gShaderCode_si_AdvAAFMaskEdgeMask4Samp_PS 00000000001606c0 long 0e SECT 03 0000 [.const] gShRegisters_si_AdvAAFMaskEdgeMask4Samp_PS 00000000001606d0 long 0e SECT 03 0000 [.const] gContextRegisters_si_AdvAAFMaskEdgeMask4Samp_PS 0000000000160710 long 0e SECT 03 0000 [.const] gUserElementTable_si_AdvAAFMaskEdgeMask4Samp_PS 0000000000160740 long 0e SECT 03 0000 [.const] gInSemantics_si_AdvAAFMaskEdgeMask4Samp_PS 0000000000160754 long 0e SECT 03 0000 [.const] gPatchInfoOffset_si_AdvAAFMaskEdgeMask4Samp_PS 0000000000160760 long 0e SECT 03 0000 [.const] gPatchInfoCode_si_AdvAAFMaskEdgeMask4Samp_PS 0000000000160940 long 0e SECT 03 0000 [.const] gShaderCode_si_AdvAAFMaskEdgeMask8Samp_PS 0000000000160dc0 long 0e SECT 03 0000 [.const] gShRegisters_si_AdvAAFMaskEdgeMask8Samp_PS 0000000000160dd0 long 0e SECT 03 0000 [.const] gContextRegisters_si_AdvAAFMaskEdgeMask8Samp_PS 0000000000160e10 long 0e SECT 03 0000 [.const] gUserElementTable_si_AdvAAFMaskEdgeMask8Samp_PS 0000000000160e40 long 0e SECT 03 0000 [.const] gInSemantics_si_AdvAAFMaskEdgeMask8Samp_PS 0000000000160e54 long 0e SECT 03 0000 [.const] gPatchInfoOffset_si_AdvAAFMaskEdgeMask8Samp_PS 0000000000160e60 long 0e SECT 03 0000 [.const] gPatchInfoCode_si_AdvAAFMaskEdgeMask8Samp_PS 0000000000161040 long 0e SECT 03 0000 [.const] gShaderCode_si_AdvAAFMaskEdG4SampNoReZ_PS 00000000001633e0 long 0e SECT 03 0000 [.const] gShRegisters_si_AdvAAFMaskEdG4SampNoReZ_PS 00000000001633f0 long 0e SECT 03 0000 [.const] gContextRegisters_si_AdvAAFMaskEdG4SampNoReZ_PS 0000000000163430 long 0e SECT 03 0000 [.const] gUserElementTable_si_AdvAAFMaskEdG4SampNoReZ_PS 0000000000163460 long 0e SECT 03 0000 [.const] gInSemantics_si_AdvAAFMaskEdG4SampNoReZ_PS 0000000000163474 long 0e SECT 03 0000 [.const] gPatchInfoOffset_si_AdvAAFMaskEdG4SampNoReZ_PS 0000000000163480 long 0e SECT 03 0000 [.const] gPatchInfoCode_si_AdvAAFMaskEdG4SampNoReZ_PS 0000000000163520 long 0e SECT 03 0000 [.const] gShaderCode_si_AdvAAFMaskEdG8SampNoReZ_PS 0000000000167ab0 long 0e SECT 03 0000 [.const] gShRegisters_si_AdvAAFMaskEdG8SampNoReZ_PS 0000000000167ac0 long 0e SECT 03 0000 [.const] gContextRegisters_si_AdvAAFMaskEdG8SampNoReZ_PS 0000000000167b00 long 0e SECT 03 0000 [.const] gUserElementTable_si_AdvAAFMaskEdG8SampNoReZ_PS 0000000000167b30 long 0e SECT 03 0000 [.const] gInSemantics_si_AdvAAFMaskEdG8SampNoReZ_PS 0000000000167b44 long 0e SECT 03 0000 [.const] gPatchInfoOffset_si_AdvAAFMaskEdG8SampNoReZ_PS 0000000000167b50 long 0e SECT 03 0000 [.const] gPatchInfoCode_si_AdvAAFMaskEdG8SampNoReZ_PS 0000000000167bf0 long 0e SECT 03 0000 [.const] gShaderCode_ci_RectPos_VS 0000000000167ce0 long 0e SECT 03 0000 [.const] gShRegisters_ci_RectPos_VS 0000000000167cf0 long 0e SECT 03 0000 [.const] gContextRegisters_ci_RectPos_VS 0000000000167d00 long 0e SECT 03 0000 [.const] gUserElementTable_ci_RectPos_VS 0000000000167d30 long 0e SECT 03 0000 [.const] gOutSemantics_ci_RectPos_VS 0000000000167d40 long 0e SECT 03 0000 [.const] gShaderCode_ci_RectPosTexTex_VS 00000000001680c0 long 0e SECT 03 0000 [.const] gShRegisters_ci_RectPosTexTex_VS 00000000001680d0 long 0e SECT 03 0000 [.const] gContextRegisters_ci_RectPosTexTex_VS 00000000001680e0 long 0e SECT 03 0000 [.const] gUserElementTable_ci_RectPosTexTex_VS 0000000000168110 long 0e SECT 03 0000 [.const] gOutSemantics_ci_RectPosTexTex_VS 0000000000168130 long 0e SECT 03 0000 [.const] gShaderCode_ci_RectPosTexFast_VS 00000000001681c0 long 0e SECT 03 0000 [.const] gShRegisters_ci_RectPosTexFast_VS 00000000001681d0 long 0e SECT 03 0000 [.const] gContextRegisters_ci_RectPosTexFast_VS 00000000001681e0 long 0e SECT 03 0000 [.const] gUserElementTable_ci_RectPosTexFast_VS 0000000000168240 long 0e SECT 03 0000 [.const] gOutSemantics_ci_RectPosTexFast_VS 0000000000168250 long 0e SECT 03 0000 [.const] gShaderCode_ci_VertPosColor_VS 00000000001682a0 long 0e SECT 03 0000 [.const] gShRegisters_ci_VertPosColor_VS 00000000001682b0 long 0e SECT 03 0000 [.const] gContextRegisters_ci_VertPosColor_VS 00000000001682c0 long 0e SECT 03 0000 [.const] gUserElementTable_ci_VertPosColor_VS 00000000001682f0 long 0e SECT 03 0000 [.const] gOutSemantics_ci_VertPosColor_VS 0000000000168300 long 0e SECT 03 0000 [.const] gShaderCode_ci_RectPosTexTexComposite_VS 00000000001684a0 long 0e SECT 03 0000 [.const] gShRegisters_ci_RectPosTexTexComposite_VS 00000000001684b0 long 0e SECT 03 0000 [.const] gContextRegisters_ci_RectPosTexTexComposite_VS 00000000001684c0 long 0e SECT 03 0000 [.const] gUserElementTable_ci_RectPosTexTexComposite_VS 00000000001684f0 long 0e SECT 03 0000 [.const] gOutSemantics_ci_RectPosTexTexComposite_VS 0000000000168510 long 0e SECT 03 0000 [.const] gShaderCode_ci_Zero_PS 0000000000168530 long 0e SECT 03 0000 [.const] gShRegisters_ci_Zero_PS 0000000000168540 long 0e SECT 03 0000 [.const] gContextRegisters_ci_Zero_PS 0000000000168580 long 0e SECT 03 0000 [.const] gUserElementTable_ci_Zero_PS 00000000001685a0 long 0e SECT 03 0000 [.const] gInSemantics_ci_Zero_PS 00000000001685b4 long 0e SECT 03 0000 [.const] gPatchInfoOffset_ci_Zero_PS 00000000001685c0 long 0e SECT 03 0000 [.const] gPatchInfoCode_ci_Zero_PS 0000000000168660 long 0e SECT 03 0000 [.const] gShaderCode_ci_Const_PS 0000000000168690 long 0e SECT 03 0000 [.const] gShRegisters_ci_Const_PS 00000000001686a0 long 0e SECT 03 0000 [.const] gContextRegisters_ci_Const_PS 00000000001686e0 long 0e SECT 03 0000 [.const] gUserElementTable_ci_Const_PS 0000000000168700 long 0e SECT 03 0000 [.const] gInSemantics_ci_Const_PS 0000000000168714 long 0e SECT 03 0000 [.const] gPatchInfoOffset_ci_Const_PS 0000000000168720 long 0e SECT 03 0000 [.const] gPatchInfoCode_ci_Const_PS 00000000001687c0 long 0e SECT 03 0000 [.const] gShaderCode_ci_Tex_PS 0000000000168800 long 0e SECT 03 0000 [.const] gShRegisters_ci_Tex_PS 0000000000168810 long 0e SECT 03 0000 [.const] gContextRegisters_ci_Tex_PS 0000000000168850 long 0e SECT 03 0000 [.const] gUserElementTable_ci_Tex_PS 0000000000168880 long 0e SECT 03 0000 [.const] gInSemantics_ci_Tex_PS 0000000000168894 long 0e SECT 03 0000 [.const] gPatchInfoOffset_ci_Tex_PS 00000000001688a0 long 0e SECT 03 0000 [.const] gPatchInfoCode_ci_Tex_PS 0000000000168940 long 0e SECT 03 0000 [.const] gShaderCode_ci_TexCoord_PS 0000000000168980 long 0e SECT 03 0000 [.const] gShRegisters_ci_TexCoord_PS 0000000000168990 long 0e SECT 03 0000 [.const] gContextRegisters_ci_TexCoord_PS 00000000001689d0 long 0e SECT 03 0000 [.const] gUserElementTable_ci_TexCoord_PS 00000000001689f0 long 0e SECT 03 0000 [.const] gInSemantics_ci_TexCoord_PS 0000000000168a04 long 0e SECT 03 0000 [.const] gPatchInfoOffset_ci_TexCoord_PS 0000000000168a10 long 0e SECT 03 0000 [.const] gPatchInfoCode_ci_TexCoord_PS 0000000000168ab0 long 0e SECT 03 0000 [.const] gShaderCode_ci_TexGammaDst_PS 0000000000168ba0 long 0e SECT 03 0000 [.const] gShRegisters_ci_TexGammaDst_PS 0000000000168bb0 long 0e SECT 03 0000 [.const] gContextRegisters_ci_TexGammaDst_PS 0000000000168bf0 long 0e SECT 03 0000 [.const] gUserElementTable_ci_TexGammaDst_PS 0000000000168c20 long 0e SECT 03 0000 [.const] gInSemantics_ci_TexGammaDst_PS 0000000000168c34 long 0e SECT 03 0000 [.const] gPatchInfoOffset_ci_TexGammaDst_PS 0000000000168c40 long 0e SECT 03 0000 [.const] gPatchInfoCode_ci_TexGammaDst_PS 0000000000168ce0 long 0e SECT 03 0000 [.const] gShaderCode_ci_MsaaResolve1_PS 0000000000168d20 long 0e SECT 03 0000 [.const] gShRegisters_ci_MsaaResolve1_PS 0000000000168d30 long 0e SECT 03 0000 [.const] gContextRegisters_ci_MsaaResolve1_PS 0000000000168d70 long 0e SECT 03 0000 [.const] gUserElementTable_ci_MsaaResolve1_PS 0000000000168da0 long 0e SECT 03 0000 [.const] gInSemantics_ci_MsaaResolve1_PS 0000000000168db4 long 0e SECT 03 0000 [.const] gPatchInfoOffset_ci_MsaaResolve1_PS 0000000000168dc0 long 0e SECT 03 0000 [.const] gPatchInfoCode_ci_MsaaResolve1_PS 0000000000168e60 long 0e SECT 03 0000 [.const] gShaderCode_ci_MsaaResolve2_PS 0000000000168ed0 long 0e SECT 03 0000 [.const] gShRegisters_ci_MsaaResolve2_PS 0000000000168ee0 long 0e SECT 03 0000 [.const] gContextRegisters_ci_MsaaResolve2_PS 0000000000168f20 long 0e SECT 03 0000 [.const] gUserElementTable_ci_MsaaResolve2_PS 0000000000168f50 long 0e SECT 03 0000 [.const] gInSemantics_ci_MsaaResolve2_PS 0000000000168f64 long 0e SECT 03 0000 [.const] gPatchInfoOffset_ci_MsaaResolve2_PS 0000000000168f70 long 0e SECT 03 0000 [.const] gPatchInfoCode_ci_MsaaResolve2_PS 0000000000169010 long 0e SECT 03 0000 [.const] gShaderCode_ci_MsaaResolve4_PS 00000000001690c0 long 0e SECT 03 0000 [.const] gShRegisters_ci_MsaaResolve4_PS 00000000001690d0 long 0e SECT 03 0000 [.const] gContextRegisters_ci_MsaaResolve4_PS 0000000000169110 long 0e SECT 03 0000 [.const] gUserElementTable_ci_MsaaResolve4_PS 0000000000169140 long 0e SECT 03 0000 [.const] gInSemantics_ci_MsaaResolve4_PS 0000000000169154 long 0e SECT 03 0000 [.const] gPatchInfoOffset_ci_MsaaResolve4_PS 0000000000169160 long 0e SECT 03 0000 [.const] gPatchInfoCode_ci_MsaaResolve4_PS 0000000000169200 long 0e SECT 03 0000 [.const] gShaderCode_ci_MsaaResolve8_PS 0000000000169330 long 0e SECT 03 0000 [.const] gShRegisters_ci_MsaaResolve8_PS 0000000000169340 long 0e SECT 03 0000 [.const] gContextRegisters_ci_MsaaResolve8_PS 0000000000169380 long 0e SECT 03 0000 [.const] gUserElementTable_ci_MsaaResolve8_PS 00000000001693b0 long 0e SECT 03 0000 [.const] gInSemantics_ci_MsaaResolve8_PS 00000000001693c4 long 0e SECT 03 0000 [.const] gPatchInfoOffset_ci_MsaaResolve8_PS 00000000001693d0 long 0e SECT 03 0000 [.const] gPatchInfoCode_ci_MsaaResolve8_PS 0000000000169470 long 0e SECT 03 0000 [.const] gShaderCode_ci_MsaaFMaskExpand_PS 0000000000169510 long 0e SECT 03 0000 [.const] gShRegisters_ci_MsaaFMaskExpand_PS 0000000000169520 long 0e SECT 03 0000 [.const] gContextRegisters_ci_MsaaFMaskExpand_PS 0000000000169560 long 0e SECT 03 0000 [.const] gUserElementTable_ci_MsaaFMaskExpand_PS 0000000000169590 long 0e SECT 03 0000 [.const] gInSemantics_ci_MsaaFMaskExpand_PS 00000000001695a4 long 0e SECT 03 0000 [.const] gPatchInfoOffset_ci_MsaaFMaskExpand_PS 00000000001695b0 long 0e SECT 03 0000 [.const] gPatchInfoCode_ci_MsaaFMaskExpand_PS 0000000000169650 long 0e SECT 03 0000 [.const] gShaderCode_ci_MsaaDepthResolve_PS 0000000000169690 long 0e SECT 03 0000 [.const] gShRegisters_ci_MsaaDepthResolve_PS 00000000001696a0 long 0e SECT 03 0000 [.const] gContextRegisters_ci_MsaaDepthResolve_PS 00000000001696e0 long 0e SECT 03 0000 [.const] gUserElementTable_ci_MsaaDepthResolve_PS 0000000000169710 long 0e SECT 03 0000 [.const] gInSemantics_ci_MsaaDepthResolve_PS 0000000000169724 long 0e SECT 03 0000 [.const] gPatchInfoOffset_ci_MsaaDepthResolve_PS 0000000000169730 long 0e SECT 03 0000 [.const] gPatchInfoCode_ci_MsaaDepthResolve_PS 00000000001697d0 long 0e SECT 03 0000 [.const] gShaderCode_ci_MsaaDepthStencilResolve_PS 0000000000169830 long 0e SECT 03 0000 [.const] gShRegisters_ci_MsaaDepthStencilResolve_PS 0000000000169840 long 0e SECT 03 0000 [.const] gContextRegisters_ci_MsaaDepthStencilResolve_PS 0000000000169880 long 0e SECT 03 0000 [.const] gUserElementTable_ci_MsaaDepthStencilResolve_PS 00000000001698d0 long 0e SECT 03 0000 [.const] gInSemantics_ci_MsaaDepthStencilResolve_PS 00000000001698e4 long 0e SECT 03 0000 [.const] gPatchInfoOffset_ci_MsaaDepthStencilResolve_PS 00000000001698f0 long 0e SECT 03 0000 [.const] gPatchInfoCode_ci_MsaaDepthStencilResolve_PS 0000000000169990 long 0e SECT 03 0000 [.const] gShaderCode_ci_TexZStencilAsColor_PS 00000000001699f0 long 0e SECT 03 0000 [.const] gShRegisters_ci_TexZStencilAsColor_PS 0000000000169a00 long 0e SECT 03 0000 [.const] gContextRegisters_ci_TexZStencilAsColor_PS 0000000000169a40 long 0e SECT 03 0000 [.const] gUserElementTable_ci_TexZStencilAsColor_PS 0000000000169a90 long 0e SECT 03 0000 [.const] gInSemantics_ci_TexZStencilAsColor_PS 0000000000169aa4 long 0e SECT 03 0000 [.const] gPatchInfoOffset_ci_TexZStencilAsColor_PS 0000000000169ab0 long 0e SECT 03 0000 [.const] gPatchInfoCode_ci_TexZStencilAsColor_PS 0000000000169b50 long 0e SECT 03 0000 [.const] gShaderCode_ci_TexAlphaOne_PS 0000000000169ba0 long 0e SECT 03 0000 [.const] gShRegisters_ci_TexAlphaOne_PS 0000000000169bb0 long 0e SECT 03 0000 [.const] gContextRegisters_ci_TexAlphaOne_PS 0000000000169bf0 long 0e SECT 03 0000 [.const] gUserElementTable_ci_TexAlphaOne_PS 0000000000169c20 long 0e SECT 03 0000 [.const] gInSemantics_ci_TexAlphaOne_PS 0000000000169c34 long 0e SECT 03 0000 [.const] gPatchInfoOffset_ci_TexAlphaOne_PS 0000000000169c40 long 0e SECT 03 0000 [.const] gPatchInfoCode_ci_TexAlphaOne_PS 0000000000169ce0 long 0e SECT 03 0000 [.const] gShaderCode_ci_TexAlphaOneInt_PS 0000000000169d30 long 0e SECT 03 0000 [.const] gShRegisters_ci_TexAlphaOneInt_PS 0000000000169d40 long 0e SECT 03 0000 [.const] gContextRegisters_ci_TexAlphaOneInt_PS 0000000000169d80 long 0e SECT 03 0000 [.const] gUserElementTable_ci_TexAlphaOneInt_PS 0000000000169db0 long 0e SECT 03 0000 [.const] gInSemantics_ci_TexAlphaOneInt_PS 0000000000169dc4 long 0e SECT 03 0000 [.const] gPatchInfoOffset_ci_TexAlphaOneInt_PS 0000000000169dd0 long 0e SECT 03 0000 [.const] gPatchInfoCode_ci_TexAlphaOneInt_PS 0000000000169e70 long 0e SECT 03 0000 [.const] gShaderCode_ci_MsaaTexZStencilAsColor_PS 0000000000169ed0 long 0e SECT 03 0000 [.const] gShRegisters_ci_MsaaTexZStencilAsColor_PS 0000000000169ee0 long 0e SECT 03 0000 [.const] gContextRegisters_ci_MsaaTexZStencilAsColor_PS 0000000000169f20 long 0e SECT 03 0000 [.const] gUserElementTable_ci_MsaaTexZStencilAsColor_PS 0000000000169f40 long 0e SECT 03 0000 [.const] gInSemantics_ci_MsaaTexZStencilAsColor_PS 0000000000169f54 long 0e SECT 03 0000 [.const] gPatchInfoOffset_ci_MsaaTexZStencilAsColor_PS 0000000000169f60 long 0e SECT 03 0000 [.const] gPatchInfoCode_ci_MsaaTexZStencilAsColor_PS 000000000016a000 long 0e SECT 03 0000 [.const] gShaderCode_ci_TexAsZ_PS 000000000016a040 long 0e SECT 03 0000 [.const] gShRegisters_ci_TexAsZ_PS 000000000016a050 long 0e SECT 03 0000 [.const] gContextRegisters_ci_TexAsZ_PS 000000000016a090 long 0e SECT 03 0000 [.const] gUserElementTable_ci_TexAsZ_PS 000000000016a0c0 long 0e SECT 03 0000 [.const] gInSemantics_ci_TexAsZ_PS 000000000016a0d4 long 0e SECT 03 0000 [.const] gPatchInfoOffset_ci_TexAsZ_PS 000000000016a0e0 long 0e SECT 03 0000 [.const] gPatchInfoCode_ci_TexAsZ_PS 000000000016a180 long 0e SECT 03 0000 [.const] gShaderCode_ci_TexAsZStencil_PS 000000000016a1e0 long 0e SECT 03 0000 [.const] gShRegisters_ci_TexAsZStencil_PS 000000000016a1f0 long 0e SECT 03 0000 [.const] gContextRegisters_ci_TexAsZStencil_PS 000000000016a230 long 0e SECT 03 0000 [.const] gUserElementTable_ci_TexAsZStencil_PS 000000000016a280 long 0e SECT 03 0000 [.const] gInSemantics_ci_TexAsZStencil_PS 000000000016a294 long 0e SECT 03 0000 [.const] gPatchInfoOffset_ci_TexAsZStencil_PS 000000000016a2a0 long 0e SECT 03 0000 [.const] gPatchInfoCode_ci_TexAsZStencil_PS 000000000016a340 long 0e SECT 03 0000 [.const] gShaderCode_ci_MsaaTexAsZ_PS 000000000016a390 long 0e SECT 03 0000 [.const] gShRegisters_ci_MsaaTexAsZ_PS 000000000016a3a0 long 0e SECT 03 0000 [.const] gContextRegisters_ci_MsaaTexAsZ_PS 000000000016a3e0 long 0e SECT 03 0000 [.const] gUserElementTable_ci_MsaaTexAsZ_PS 000000000016a410 long 0e SECT 03 0000 [.const] gInSemantics_ci_MsaaTexAsZ_PS 000000000016a424 long 0e SECT 03 0000 [.const] gPatchInfoOffset_ci_MsaaTexAsZ_PS 000000000016a430 long 0e SECT 03 0000 [.const] gPatchInfoCode_ci_MsaaTexAsZ_PS 000000000016a4d0 long 0e SECT 03 0000 [.const] gShaderCode_ci_MsaaTexAsZStencil_PS 000000000016a530 long 0e SECT 03 0000 [.const] gShRegisters_ci_MsaaTexAsZStencil_PS 000000000016a540 long 0e SECT 03 0000 [.const] gContextRegisters_ci_MsaaTexAsZStencil_PS 000000000016a580 long 0e SECT 03 0000 [.const] gUserElementTable_ci_MsaaTexAsZStencil_PS 000000000016a5d0 long 0e SECT 03 0000 [.const] gInSemantics_ci_MsaaTexAsZStencil_PS 000000000016a5e4 long 0e SECT 03 0000 [.const] gPatchInfoOffset_ci_MsaaTexAsZStencil_PS 000000000016a5f0 long 0e SECT 03 0000 [.const] gPatchInfoCode_ci_MsaaTexAsZStencil_PS 000000000016a690 long 0e SECT 03 0000 [.const] gShaderCode_ci_VolTex_PS 000000000016a6e0 long 0e SECT 03 0000 [.const] gShRegisters_ci_VolTex_PS 000000000016a6f0 long 0e SECT 03 0000 [.const] gContextRegisters_ci_VolTex_PS 000000000016a730 long 0e SECT 03 0000 [.const] gUserElementTable_ci_VolTex_PS 000000000016a760 long 0e SECT 03 0000 [.const] gInSemantics_ci_VolTex_PS 000000000016a774 long 0e SECT 03 0000 [.const] gPatchInfoOffset_ci_VolTex_PS 000000000016a780 long 0e SECT 03 0000 [.const] gPatchInfoCode_ci_VolTex_PS 000000000016a820 long 0e SECT 03 0000 [.const] gShaderCode_ci_AAText_PS 000000000016a8f0 long 0e SECT 03 0000 [.const] gShRegisters_ci_AAText_PS 000000000016a900 long 0e SECT 03 0000 [.const] gContextRegisters_ci_AAText_PS 000000000016a940 long 0e SECT 03 0000 [.const] gUserElementTable_ci_AAText_PS 000000000016a990 long 0e SECT 03 0000 [.const] gInSemantics_ci_AAText_PS 000000000016a9a4 long 0e SECT 03 0000 [.const] gPatchInfoOffset_ci_AAText_PS 000000000016a9b0 long 0e SECT 03 0000 [.const] gPatchInfoCode_ci_AAText_PS 000000000016aa50 long 0e SECT 03 0000 [.const] gShaderCode_ci_SlowAAText_PS 000000000016ab10 long 0e SECT 03 0000 [.const] gShRegisters_ci_SlowAAText_PS 000000000016ab20 long 0e SECT 03 0000 [.const] gContextRegisters_ci_SlowAAText_PS 000000000016ab60 long 0e SECT 03 0000 [.const] gUserElementTable_ci_SlowAAText_PS 000000000016abc0 long 0e SECT 03 0000 [.const] gInSemantics_ci_SlowAAText_PS 000000000016abe8 long 0e SECT 03 0000 [.const] gPatchInfoOffset_ci_SlowAAText_PS 000000000016abf0 long 0e SECT 03 0000 [.const] gPatchInfoCode_ci_SlowAAText_PS 000000000016ac90 long 0e SECT 03 0000 [.const] gShaderCode_ci_ClearTypeGamma_PS 000000000016ae10 long 0e SECT 03 0000 [.const] gShRegisters_ci_ClearTypeGamma_PS 000000000016ae20 long 0e SECT 03 0000 [.const] gContextRegisters_ci_ClearTypeGamma_PS 000000000016ae60 long 0e SECT 03 0000 [.const] gUserElementTable_ci_ClearTypeGamma_PS 000000000016aeb0 long 0e SECT 03 0000 [.const] gInSemantics_ci_ClearTypeGamma_PS 000000000016aed8 long 0e SECT 03 0000 [.const] gPatchInfoOffset_ci_ClearTypeGamma_PS 000000000016aee0 long 0e SECT 03 0000 [.const] gPatchInfoCode_ci_ClearTypeGamma_PS 000000000016af80 long 0e SECT 03 0000 [.const] gShaderCode_ci_TexColorKey_PS 000000000016b0d0 long 0e SECT 03 0000 [.const] gShRegisters_ci_TexColorKey_PS 000000000016b0e0 long 0e SECT 03 0000 [.const] gContextRegisters_ci_TexColorKey_PS 000000000016b120 long 0e SECT 03 0000 [.const] gUserElementTable_ci_TexColorKey_PS 000000000016b180 long 0e SECT 03 0000 [.const] gInSemantics_ci_TexColorKey_PS 000000000016b1a8 long 0e SECT 03 0000 [.const] gPatchInfoOffset_ci_TexColorKey_PS 000000000016b1b0 long 0e SECT 03 0000 [.const] gPatchInfoCode_ci_TexColorKey_PS 000000000016b250 long 0e SECT 03 0000 [.const] gShaderCode_ci_TexSrcColorKey_PS 000000000016b310 long 0e SECT 03 0000 [.const] gShRegisters_ci_TexSrcColorKey_PS 000000000016b320 long 0e SECT 03 0000 [.const] gContextRegisters_ci_TexSrcColorKey_PS 000000000016b360 long 0e SECT 03 0000 [.const] gUserElementTable_ci_TexSrcColorKey_PS 000000000016b3b0 long 0e SECT 03 0000 [.const] gInSemantics_ci_TexSrcColorKey_PS 000000000016b3c4 long 0e SECT 03 0000 [.const] gPatchInfoOffset_ci_TexSrcColorKey_PS 000000000016b3d0 long 0e SECT 03 0000 [.const] gPatchInfoCode_ci_TexSrcColorKey_PS 000000000016b470 long 0e SECT 03 0000 [.const] gShaderCode_ci_TexMulConst_PS 000000000016b4d0 long 0e SECT 03 0000 [.const] gShRegisters_ci_TexMulConst_PS 000000000016b4e0 long 0e SECT 03 0000 [.const] gContextRegisters_ci_TexMulConst_PS 000000000016b520 long 0e SECT 03 0000 [.const] gUserElementTable_ci_TexMulConst_PS 000000000016b570 long 0e SECT 03 0000 [.const] gInSemantics_ci_TexMulConst_PS 000000000016b584 long 0e SECT 03 0000 [.const] gPatchInfoOffset_ci_TexMulConst_PS 000000000016b590 long 0e SECT 03 0000 [.const] gPatchInfoCode_ci_TexMulConst_PS 000000000016b630 long 0e SECT 03 0000 [.const] gShaderCode_ci_TexDither_PS 000000000016b6a0 long 0e SECT 03 0000 [.const] gShRegisters_ci_TexDither_PS 000000000016b6b0 long 0e SECT 03 0000 [.const] gContextRegisters_ci_TexDither_PS 000000000016b6f0 long 0e SECT 03 0000 [.const] gUserElementTable_ci_TexDither_PS 000000000016b750 long 0e SECT 03 0000 [.const] gInSemantics_ci_TexDither_PS 000000000016b764 long 0e SECT 03 0000 [.const] gPatchInfoOffset_ci_TexDither_PS 000000000016b770 long 0e SECT 03 0000 [.const] gPatchInfoCode_ci_TexDither_PS 000000000016b810 long 0e SECT 03 0000 [.const] gShaderCode_ci_YuvToRgb_PS 000000000016b8e0 long 0e SECT 03 0000 [.const] gShRegisters_ci_YuvToRgb_PS 000000000016b8f0 long 0e SECT 03 0000 [.const] gContextRegisters_ci_YuvToRgb_PS 000000000016b930 long 0e SECT 03 0000 [.const] gUserElementTable_ci_YuvToRgb_PS 000000000016b980 long 0e SECT 03 0000 [.const] gInSemantics_ci_YuvToRgb_PS 000000000016b994 long 0e SECT 03 0000 [.const] gPatchInfoOffset_ci_YuvToRgb_PS 000000000016b9a0 long 0e SECT 03 0000 [.const] gPatchInfoCode_ci_YuvToRgb_PS 000000000016ba40 long 0e SECT 03 0000 [.const] gShaderCode_ci_YuvIntUvToRgb_PS 000000000016baf0 long 0e SECT 03 0000 [.const] gShRegisters_ci_YuvIntUvToRgb_PS 000000000016bb00 long 0e SECT 03 0000 [.const] gContextRegisters_ci_YuvIntUvToRgb_PS 000000000016bb40 long 0e SECT 03 0000 [.const] gUserElementTable_ci_YuvIntUvToRgb_PS 000000000016bba0 long 0e SECT 03 0000 [.const] gInSemantics_ci_YuvIntUvToRgb_PS 000000000016bbb4 long 0e SECT 03 0000 [.const] gPatchInfoOffset_ci_YuvIntUvToRgb_PS 000000000016bbc0 long 0e SECT 03 0000 [.const] gPatchInfoCode_ci_YuvIntUvToRgb_PS 000000000016bc60 long 0e SECT 03 0000 [.const] gShaderCode_ci_YuvIntUvToYuy2_PS 000000000016bd00 long 0e SECT 03 0000 [.const] gShRegisters_ci_YuvIntUvToYuy2_PS 000000000016bd10 long 0e SECT 03 0000 [.const] gContextRegisters_ci_YuvIntUvToYuy2_PS 000000000016bd50 long 0e SECT 03 0000 [.const] gUserElementTable_ci_YuvIntUvToYuy2_PS 000000000016bdb0 long 0e SECT 03 0000 [.const] gInSemantics_ci_YuvIntUvToYuy2_PS 000000000016bdc4 long 0e SECT 03 0000 [.const] gPatchInfoOffset_ci_YuvIntUvToYuy2_PS 000000000016bdd0 long 0e SECT 03 0000 [.const] gPatchInfoCode_ci_YuvIntUvToYuy2_PS 000000000016be70 long 0e SECT 03 0000 [.const] gShaderCode_ci_YuvToYuy2_PS 000000000016bf20 long 0e SECT 03 0000 [.const] gShRegisters_ci_YuvToYuy2_PS 000000000016bf30 long 0e SECT 03 0000 [.const] gContextRegisters_ci_YuvToYuy2_PS 000000000016bf70 long 0e SECT 03 0000 [.const] gUserElementTable_ci_YuvToYuy2_PS 000000000016bfc0 long 0e SECT 03 0000 [.const] gInSemantics_ci_YuvToYuy2_PS 000000000016bfd4 long 0e SECT 03 0000 [.const] gPatchInfoOffset_ci_YuvToYuy2_PS 000000000016bfe0 long 0e SECT 03 0000 [.const] gPatchInfoCode_ci_YuvToYuy2_PS 000000000016c080 long 0e SECT 03 0000 [.const] gShaderCode_ci_MsaaFMaskResolve2_PS 000000000016c140 long 0e SECT 03 0000 [.const] gShRegisters_ci_MsaaFMaskResolve2_PS 000000000016c150 long 0e SECT 03 0000 [.const] gContextRegisters_ci_MsaaFMaskResolve2_PS 000000000016c190 long 0e SECT 03 0000 [.const] gUserElementTable_ci_MsaaFMaskResolve2_PS 000000000016c1c0 long 0e SECT 03 0000 [.const] gInSemantics_ci_MsaaFMaskResolve2_PS 000000000016c1d4 long 0e SECT 03 0000 [.const] gPatchInfoOffset_ci_MsaaFMaskResolve2_PS 000000000016c1e0 long 0e SECT 03 0000 [.const] gPatchInfoCode_ci_MsaaFMaskResolve2_PS 000000000016c280 long 0e SECT 03 0000 [.const] gShaderCode_ci_MsaaFMaskResolve4_PS 000000000016c3c0 long 0e SECT 03 0000 [.const] gShRegisters_ci_MsaaFMaskResolve4_PS 000000000016c3d0 long 0e SECT 03 0000 [.const] gContextRegisters_ci_MsaaFMaskResolve4_PS 000000000016c410 long 0e SECT 03 0000 [.const] gUserElementTable_ci_MsaaFMaskResolve4_PS 000000000016c440 long 0e SECT 03 0000 [.const] gInSemantics_ci_MsaaFMaskResolve4_PS 000000000016c454 long 0e SECT 03 0000 [.const] gPatchInfoOffset_ci_MsaaFMaskResolve4_PS 000000000016c460 long 0e SECT 03 0000 [.const] gPatchInfoCode_ci_MsaaFMaskResolve4_PS 000000000016c500 long 0e SECT 03 0000 [.const] gShaderCode_ci_MsaaFMaskResolve8_PS 000000000016c6e0 long 0e SECT 03 0000 [.const] gShRegisters_ci_MsaaFMaskResolve8_PS 000000000016c6f0 long 0e SECT 03 0000 [.const] gContextRegisters_ci_MsaaFMaskResolve8_PS 000000000016c730 long 0e SECT 03 0000 [.const] gUserElementTable_ci_MsaaFMaskResolve8_PS 000000000016c760 long 0e SECT 03 0000 [.const] gInSemantics_ci_MsaaFMaskResolve8_PS 000000000016c774 long 0e SECT 03 0000 [.const] gPatchInfoOffset_ci_MsaaFMaskResolve8_PS 000000000016c780 long 0e SECT 03 0000 [.const] gPatchInfoCode_ci_MsaaFMaskResolve8_PS 000000000016c820 long 0e SECT 03 0000 [.const] gShaderCode_ci_MsaaFMaskResolve2Frag4Samp_PS 000000000016c9d0 long 0e SECT 03 0000 [.const] gShRegisters_ci_MsaaFMaskResolve2Frag4Samp_PS 000000000016c9e0 long 0e SECT 03 0000 [.const] gContextRegisters_ci_MsaaFMaskResolve2Frag4Samp_PS 000000000016ca20 long 0e SECT 03 0000 [.const] gUserElementTable_ci_MsaaFMaskResolve2Frag4Samp_PS 000000000016ca50 long 0e SECT 03 0000 [.const] gInSemantics_ci_MsaaFMaskResolve2Frag4Samp_PS 000000000016ca64 long 0e SECT 03 0000 [.const] gPatchInfoOffset_ci_MsaaFMaskResolve2Frag4Samp_PS 000000000016ca70 long 0e SECT 03 0000 [.const] gPatchInfoCode_ci_MsaaFMaskResolve2Frag4Samp_PS 000000000016cb10 long 0e SECT 03 0000 [.const] gShaderCode_ci_MsaaFMaskResolve2Frag8Samp_PS 000000000016ce00 long 0e SECT 03 0000 [.const] gShRegisters_ci_MsaaFMaskResolve2Frag8Samp_PS 000000000016ce10 long 0e SECT 03 0000 [.const] gContextRegisters_ci_MsaaFMaskResolve2Frag8Samp_PS 000000000016ce50 long 0e SECT 03 0000 [.const] gUserElementTable_ci_MsaaFMaskResolve2Frag8Samp_PS 000000000016ce80 long 0e SECT 03 0000 [.const] gInSemantics_ci_MsaaFMaskResolve2Frag8Samp_PS 000000000016ce94 long 0e SECT 03 0000 [.const] gPatchInfoOffset_ci_MsaaFMaskResolve2Frag8Samp_PS 000000000016cea0 long 0e SECT 03 0000 [.const] gPatchInfoCode_ci_MsaaFMaskResolve2Frag8Samp_PS 000000000016cf40 long 0e SECT 03 0000 [.const] gShaderCode_ci_MsaaFMaskResolve2Frag16Samp_PS 000000000016d4a0 long 0e SECT 03 0000 [.const] gShRegisters_ci_MsaaFMaskResolve2Frag16Samp_PS 000000000016d4b0 long 0e SECT 03 0000 [.const] gContextRegisters_ci_MsaaFMaskResolve2Frag16Samp_PS 000000000016d4f0 long 0e SECT 03 0000 [.const] gUserElementTable_ci_MsaaFMaskResolve2Frag16Samp_PS 000000000016d520 long 0e SECT 03 0000 [.const] gInSemantics_ci_MsaaFMaskResolve2Frag16Samp_PS 000000000016d534 long 0e SECT 03 0000 [.const] gPatchInfoOffset_ci_MsaaFMaskResolve2Frag16Samp_PS 000000000016d540 long 0e SECT 03 0000 [.const] gPatchInfoCode_ci_MsaaFMaskResolve2Frag16Samp_PS 000000000016d5e0 long 0e SECT 03 0000 [.const] gShaderCode_ci_MsaaFMaskResolve4Frag8Samp_PS 000000000016d880 long 0e SECT 03 0000 [.const] gShRegisters_ci_MsaaFMaskResolve4Frag8Samp_PS 000000000016d890 long 0e SECT 03 0000 [.const] gContextRegisters_ci_MsaaFMaskResolve4Frag8Samp_PS 000000000016d8d0 long 0e SECT 03 0000 [.const] gUserElementTable_ci_MsaaFMaskResolve4Frag8Samp_PS 000000000016d900 long 0e SECT 03 0000 [.const] gInSemantics_ci_MsaaFMaskResolve4Frag8Samp_PS 000000000016d914 long 0e SECT 03 0000 [.const] gPatchInfoOffset_ci_MsaaFMaskResolve4Frag8Samp_PS 000000000016d920 long 0e SECT 03 0000 [.const] gPatchInfoCode_ci_MsaaFMaskResolve4Frag8Samp_PS 000000000016d9c0 long 0e SECT 03 0000 [.const] gShaderCode_ci_MsaaFMaskResolve4Frag16Samp_PS 000000000016def0 long 0e SECT 03 0000 [.const] gShRegisters_ci_MsaaFMaskResolve4Frag16Samp_PS 000000000016df00 long 0e SECT 03 0000 [.const] gContextRegisters_ci_MsaaFMaskResolve4Frag16Samp_PS 000000000016df40 long 0e SECT 03 0000 [.const] gUserElementTable_ci_MsaaFMaskResolve4Frag16Samp_PS 000000000016df70 long 0e SECT 03 0000 [.const] gInSemantics_ci_MsaaFMaskResolve4Frag16Samp_PS 000000000016df84 long 0e SECT 03 0000 [.const] gPatchInfoOffset_ci_MsaaFMaskResolve4Frag16Samp_PS 000000000016df90 long 0e SECT 03 0000 [.const] gPatchInfoCode_ci_MsaaFMaskResolve4Frag16Samp_PS 000000000016e030 long 0e SECT 03 0000 [.const] gShaderCode_ci_MsaaFMaskResolve8Frag16Samp_PS 000000000016e500 long 0e SECT 03 0000 [.const] gShRegisters_ci_MsaaFMaskResolve8Frag16Samp_PS 000000000016e510 long 0e SECT 03 0000 [.const] gContextRegisters_ci_MsaaFMaskResolve8Frag16Samp_PS 000000000016e550 long 0e SECT 03 0000 [.const] gUserElementTable_ci_MsaaFMaskResolve8Frag16Samp_PS 000000000016e580 long 0e SECT 03 0000 [.const] gInSemantics_ci_MsaaFMaskResolve8Frag16Samp_PS 000000000016e594 long 0e SECT 03 0000 [.const] gPatchInfoOffset_ci_MsaaFMaskResolve8Frag16Samp_PS 000000000016e5a0 long 0e SECT 03 0000 [.const] gPatchInfoCode_ci_MsaaFMaskResolve8Frag16Samp_PS 000000000016e640 long 0e SECT 03 0000 [.const] gShaderCode_ci_ColorTransform_PS 000000000016e880 long 0e SECT 03 0000 [.const] gShRegisters_ci_ColorTransform_PS 000000000016e890 long 0e SECT 03 0000 [.const] gContextRegisters_ci_ColorTransform_PS 000000000016e8d0 long 0e SECT 03 0000 [.const] gUserElementTable_ci_ColorTransform_PS 000000000016e920 long 0e SECT 03 0000 [.const] gInSemantics_ci_ColorTransform_PS 000000000016e934 long 0e SECT 03 0000 [.const] gPatchInfoOffset_ci_ColorTransform_PS 000000000016e940 long 0e SECT 03 0000 [.const] gPatchInfoCode_ci_ColorTransform_PS 000000000016e9e0 long 0e SECT 03 0000 [.const] gShaderCode_ci_NonEvenLinearFilter1D_PS 000000000016eb00 long 0e SECT 03 0000 [.const] gShRegisters_ci_NonEvenLinearFilter1D_PS 000000000016eb10 long 0e SECT 03 0000 [.const] gContextRegisters_ci_NonEvenLinearFilter1D_PS 000000000016eb50 long 0e SECT 03 0000 [.const] gUserElementTable_ci_NonEvenLinearFilter1D_PS 000000000016eba0 long 0e SECT 03 0000 [.const] gInSemantics_ci_NonEvenLinearFilter1D_PS 000000000016ebb4 long 0e SECT 03 0000 [.const] gPatchInfoOffset_ci_NonEvenLinearFilter1D_PS 000000000016ebc0 long 0e SECT 03 0000 [.const] gPatchInfoCode_ci_NonEvenLinearFilter1D_PS 000000000016ec60 long 0e SECT 03 0000 [.const] gShaderCode_ci_NonEvenLinearFilter2D_PS 000000000016ee40 long 0e SECT 03 0000 [.const] gShRegisters_ci_NonEvenLinearFilter2D_PS 000000000016ee50 long 0e SECT 03 0000 [.const] gContextRegisters_ci_NonEvenLinearFilter2D_PS 000000000016ee90 long 0e SECT 03 0000 [.const] gUserElementTable_ci_NonEvenLinearFilter2D_PS 000000000016eee0 long 0e SECT 03 0000 [.const] gInSemantics_ci_NonEvenLinearFilter2D_PS 000000000016eef4 long 0e SECT 03 0000 [.const] gPatchInfoOffset_ci_NonEvenLinearFilter2D_PS 000000000016ef00 long 0e SECT 03 0000 [.const] gPatchInfoCode_ci_NonEvenLinearFilter2D_PS 000000000016efa0 long 0e SECT 03 0000 [.const] gShaderCode_ci_NonEvenLinearFilter3D_PS 000000000016f250 long 0e SECT 03 0000 [.const] gShRegisters_ci_NonEvenLinearFilter3D_PS 000000000016f260 long 0e SECT 03 0000 [.const] gContextRegisters_ci_NonEvenLinearFilter3D_PS 000000000016f2a0 long 0e SECT 03 0000 [.const] gUserElementTable_ci_NonEvenLinearFilter3D_PS 000000000016f2f0 long 0e SECT 03 0000 [.const] gInSemantics_ci_NonEvenLinearFilter3D_PS 000000000016f304 long 0e SECT 03 0000 [.const] gPatchInfoOffset_ci_NonEvenLinearFilter3D_PS 000000000016f310 long 0e SECT 03 0000 [.const] gPatchInfoCode_ci_NonEvenLinearFilter3D_PS 000000000016f3b0 long 0e SECT 03 0000 [.const] gShaderCode_ci_MLAACalcSepEdgeLength_PS 000000000016f7c0 long 0e SECT 03 0000 [.const] gShRegisters_ci_MLAACalcSepEdgeLength_PS 000000000016f7d0 long 0e SECT 03 0000 [.const] gContextRegisters_ci_MLAACalcSepEdgeLength_PS 000000000016f810 long 0e SECT 03 0000 [.const] gUserElementTable_ci_MLAACalcSepEdgeLength_PS 000000000016f840 long 0e SECT 03 0000 [.const] gInSemantics_ci_MLAACalcSepEdgeLength_PS 000000000016f854 long 0e SECT 03 0000 [.const] gPatchInfoOffset_ci_MLAACalcSepEdgeLength_PS 000000000016f860 long 0e SECT 03 0000 [.const] gPatchInfoCode_ci_MLAACalcSepEdgeLength_PS 000000000016f9a0 long 0e SECT 03 0000 [.const] gShaderCode_ci_MLAACalcSepEdgeLengthFast_PS 000000000016ffe0 long 0e SECT 03 0000 [.const] gShRegisters_ci_MLAACalcSepEdgeLengthFast_PS 000000000016fff0 long 0e SECT 03 0000 [.const] gContextRegisters_ci_MLAACalcSepEdgeLengthFast_PS 0000000000170030 long 0e SECT 03 0000 [.const] gUserElementTable_ci_MLAACalcSepEdgeLengthFast_PS 0000000000170060 long 0e SECT 03 0000 [.const] gInSemantics_ci_MLAACalcSepEdgeLengthFast_PS 0000000000170074 long 0e SECT 03 0000 [.const] gPatchInfoOffset_ci_MLAACalcSepEdgeLengthFast_PS 0000000000170080 long 0e SECT 03 0000 [.const] gPatchInfoCode_ci_MLAACalcSepEdgeLengthFast_PS 0000000000170120 long 0e SECT 03 0000 [.const] gShaderCode_ci_MLAACalcSepEdgeLengthInitial_PS 0000000000170320 long 0e SECT 03 0000 [.const] gShRegisters_ci_MLAACalcSepEdgeLengthInitial_PS 0000000000170330 long 0e SECT 03 0000 [.const] gContextRegisters_ci_MLAACalcSepEdgeLengthInitial_PS 0000000000170370 long 0e SECT 03 0000 [.const] gUserElementTable_ci_MLAACalcSepEdgeLengthInitial_PS 00000000001703a0 long 0e SECT 03 0000 [.const] gInSemantics_ci_MLAACalcSepEdgeLengthInitial_PS 00000000001703b4 long 0e SECT 03 0000 [.const] gPatchInfoOffset_ci_MLAACalcSepEdgeLengthInitial_PS 00000000001703c0 long 0e SECT 03 0000 [.const] gPatchInfoCode_ci_MLAACalcSepEdgeLengthInitial_PS 0000000000170500 long 0e SECT 03 0000 [.const] gShaderCode_ci_MLAAFinalBlend_PS 0000000000170d70 long 0e SECT 03 0000 [.const] gShRegisters_ci_MLAAFinalBlend_PS 0000000000170d80 long 0e SECT 03 0000 [.const] gContextRegisters_ci_MLAAFinalBlend_PS 0000000000170dc0 long 0e SECT 03 0000 [.const] gUserElementTable_ci_MLAAFinalBlend_PS 0000000000170de0 long 0e SECT 03 0000 [.const] gInSemantics_ci_MLAAFinalBlend_PS 0000000000170df4 long 0e SECT 03 0000 [.const] gPatchInfoOffset_ci_MLAAFinalBlend_PS 0000000000170e00 long 0e SECT 03 0000 [.const] gPatchInfoCode_ci_MLAAFinalBlend_PS 0000000000170ea0 long 0e SECT 03 0000 [.const] gShaderCode_ci_MLAAFinalBlendFast_PS 00000000001717a0 long 0e SECT 03 0000 [.const] gShRegisters_ci_MLAAFinalBlendFast_PS 00000000001717b0 long 0e SECT 03 0000 [.const] gContextRegisters_ci_MLAAFinalBlendFast_PS 00000000001717f0 long 0e SECT 03 0000 [.const] gUserElementTable_ci_MLAAFinalBlendFast_PS 0000000000171820 long 0e SECT 03 0000 [.const] gInSemantics_ci_MLAAFinalBlendFast_PS 0000000000171834 long 0e SECT 03 0000 [.const] gPatchInfoOffset_ci_MLAAFinalBlendFast_PS 0000000000171840 long 0e SECT 03 0000 [.const] gPatchInfoCode_ci_MLAAFinalBlendFast_PS 00000000001718e0 long 0e SECT 03 0000 [.const] gShaderCode_ci_MLAAFindSepEdge_PS 00000000001719e0 long 0e SECT 03 0000 [.const] gShRegisters_ci_MLAAFindSepEdge_PS 00000000001719f0 long 0e SECT 03 0000 [.const] gContextRegisters_ci_MLAAFindSepEdge_PS 0000000000171a30 long 0e SECT 03 0000 [.const] gUserElementTable_ci_MLAAFindSepEdge_PS 0000000000171a60 long 0e SECT 03 0000 [.const] gInSemantics_ci_MLAAFindSepEdge_PS 0000000000171a74 long 0e SECT 03 0000 [.const] gPatchInfoOffset_ci_MLAAFindSepEdge_PS 0000000000171a80 long 0e SECT 03 0000 [.const] gPatchInfoCode_ci_MLAAFindSepEdge_PS 0000000000171b20 long 0e SECT 03 0000 [.const] gShaderCode_ci_GenZRangeTex_PS 0000000000171e60 long 0e SECT 03 0000 [.const] gShRegisters_ci_GenZRangeTex_PS 0000000000171e70 long 0e SECT 03 0000 [.const] gContextRegisters_ci_GenZRangeTex_PS 0000000000171eb0 long 0e SECT 03 0000 [.const] gUserElementTable_ci_GenZRangeTex_PS 0000000000171f00 long 0e SECT 03 0000 [.const] gInSemantics_ci_GenZRangeTex_PS 0000000000171f14 long 0e SECT 03 0000 [.const] gPatchInfoOffset_ci_GenZRangeTex_PS 0000000000171f20 long 0e SECT 03 0000 [.const] gPatchInfoCode_ci_GenZRangeTex_PS 0000000000171fc0 long 0e SECT 03 0000 [.const] gShaderCode_ci_GenZRangeMip_PS 0000000000172060 long 0e SECT 03 0000 [.const] gShRegisters_ci_GenZRangeMip_PS 0000000000172070 long 0e SECT 03 0000 [.const] gContextRegisters_ci_GenZRangeMip_PS 00000000001720b0 long 0e SECT 03 0000 [.const] gUserElementTable_ci_GenZRangeMip_PS 0000000000172100 long 0e SECT 03 0000 [.const] gInSemantics_ci_GenZRangeMip_PS 0000000000172114 long 0e SECT 03 0000 [.const] gPatchInfoOffset_ci_GenZRangeMip_PS 0000000000172120 long 0e SECT 03 0000 [.const] gPatchInfoCode_ci_GenZRangeMip_PS 00000000001721c0 long 0e SECT 03 0000 [.const] gShaderCode_ci_GenZRangeMipOdd_PS 00000000001723c0 long 0e SECT 03 0000 [.const] gShRegisters_ci_GenZRangeMipOdd_PS 00000000001723d0 long 0e SECT 03 0000 [.const] gContextRegisters_ci_GenZRangeMipOdd_PS 0000000000172410 long 0e SECT 03 0000 [.const] gUserElementTable_ci_GenZRangeMipOdd_PS 0000000000172440 long 0e SECT 03 0000 [.const] gInSemantics_ci_GenZRangeMipOdd_PS 0000000000172454 long 0e SECT 03 0000 [.const] gPatchInfoOffset_ci_GenZRangeMipOdd_PS 0000000000172460 long 0e SECT 03 0000 [.const] gPatchInfoCode_ci_GenZRangeMipOdd_PS 0000000000172500 long 0e SECT 03 0000 [.const] gShaderCode_ci_Composite_PS 0000000000172bb0 long 0e SECT 03 0000 [.const] gShRegisters_ci_Composite_PS 0000000000172bc0 long 0e SECT 03 0000 [.const] gContextRegisters_ci_Composite_PS 0000000000172c00 long 0e SECT 03 0000 [.const] gUserElementTable_ci_Composite_PS 0000000000172c50 long 0e SECT 03 0000 [.const] gInSemantics_ci_Composite_PS 0000000000172c78 long 0e SECT 03 0000 [.const] gPatchInfoOffset_ci_Composite_PS 0000000000172c80 long 0e SECT 03 0000 [.const] gPatchInfoCode_ci_Composite_PS 0000000000172d20 long 0e SECT 03 0000 [.const] gShaderCode_ci_BufferClear_CS 0000000000172d50 long 0e SECT 03 0000 [.const] gShRegisters_ci_BufferClear_CS 0000000000172d78 long 0e SECT 03 0000 [.const] gContextRegisters_ci_BufferClear_CS 0000000000172d80 long 0e SECT 03 0000 [.const] gUserElementTable_ci_BufferClear_CS 0000000000172db0 long 0e SECT 03 0000 [.const] gShaderCode_ci_BufferCopy_CS 0000000000172dd0 long 0e SECT 03 0000 [.const] gShRegisters_ci_BufferCopy_CS 0000000000172df8 long 0e SECT 03 0000 [.const] gContextRegisters_ci_BufferCopy_CS 0000000000172e00 long 0e SECT 03 0000 [.const] gUserElementTable_ci_BufferCopy_CS 0000000000172e30 long 0e SECT 03 0000 [.const] gShaderCode_ci_SurfaceClear_CS 0000000000172e90 long 0e SECT 03 0000 [.const] gShRegisters_ci_SurfaceClear_CS 0000000000172eb8 long 0e SECT 03 0000 [.const] gContextRegisters_ci_SurfaceClear_CS 0000000000172ec0 long 0e SECT 03 0000 [.const] gUserElementTable_ci_SurfaceClear_CS 0000000000172ef0 long 0e SECT 03 0000 [.const] gShaderCode_ci_LinGenDstCopy_CS 0000000000172f70 long 0e SECT 03 0000 [.const] gShRegisters_ci_LinGenDstCopy_CS 0000000000172f98 long 0e SECT 03 0000 [.const] gContextRegisters_ci_LinGenDstCopy_CS 0000000000172fa0 long 0e SECT 03 0000 [.const] gUserElementTable_ci_LinGenDstCopy_CS 0000000000172ff0 long 0e SECT 03 0000 [.const] gShaderCode_ci_LinGenSrcCopy_CS 0000000000173060 long 0e SECT 03 0000 [.const] gShRegisters_ci_LinGenSrcCopy_CS 0000000000173088 long 0e SECT 03 0000 [.const] gContextRegisters_ci_LinGenSrcCopy_CS 0000000000173090 long 0e SECT 03 0000 [.const] gUserElementTable_ci_LinGenSrcCopy_CS 00000000001730e0 long 0e SECT 03 0000 [.const] gShaderCode_ci_LinGenSrcDstCopy_CS 0000000000173160 long 0e SECT 03 0000 [.const] gShRegisters_ci_LinGenSrcDstCopy_CS 0000000000173188 long 0e SECT 03 0000 [.const] gContextRegisters_ci_LinGenSrcDstCopy_CS 0000000000173190 long 0e SECT 03 0000 [.const] gUserElementTable_ci_LinGenSrcDstCopy_CS 00000000001731e0 long 0e SECT 03 0000 [.const] gShaderCode_ci_HtileCopy_CS 0000000000173210 long 0e SECT 03 0000 [.const] gShRegisters_ci_HtileCopy_CS 0000000000173238 long 0e SECT 03 0000 [.const] gContextRegisters_ci_HtileCopy_CS 0000000000173240 long 0e SECT 03 0000 [.const] gUserElementTable_ci_HtileCopy_CS 0000000000173270 long 0e SECT 03 0000 [.const] gShaderCode_ci_MsaaFMaskExpand2Samp_CS 0000000000173310 long 0e SECT 03 0000 [.const] gShRegisters_ci_MsaaFMaskExpand2Samp_CS 0000000000173338 long 0e SECT 03 0000 [.const] gContextRegisters_ci_MsaaFMaskExpand2Samp_CS 0000000000173340 long 0e SECT 03 0000 [.const] gUserElementTable_ci_MsaaFMaskExpand2Samp_CS 0000000000173360 long 0e SECT 03 0000 [.const] gShaderCode_ci_MsaaFMaskExpand4Samp_CS 0000000000173460 long 0e SECT 03 0000 [.const] gShRegisters_ci_MsaaFMaskExpand4Samp_CS 0000000000173488 long 0e SECT 03 0000 [.const] gContextRegisters_ci_MsaaFMaskExpand4Samp_CS 0000000000173490 long 0e SECT 03 0000 [.const] gUserElementTable_ci_MsaaFMaskExpand4Samp_CS 00000000001734b0 long 0e SECT 03 0000 [.const] gShaderCode_ci_MsaaFMaskExpand8Samp_CS 0000000000173670 long 0e SECT 03 0000 [.const] gShRegisters_ci_MsaaFMaskExpand8Samp_CS 0000000000173698 long 0e SECT 03 0000 [.const] gContextRegisters_ci_MsaaFMaskExpand8Samp_CS 00000000001736a0 long 0e SECT 03 0000 [.const] gUserElementTable_ci_MsaaFMaskExpand8Samp_CS 00000000001736c0 long 0e SECT 03 0000 [.const] gShaderCode_ci_FastDepthClear_CS 0000000000173720 long 0e SECT 03 0000 [.const] gShRegisters_ci_FastDepthClear_CS 0000000000173748 long 0e SECT 03 0000 [.const] gContextRegisters_ci_FastDepthClear_CS 0000000000173750 long 0e SECT 03 0000 [.const] gUserElementTable_ci_FastDepthClear_CS 0000000000173780 long 0e SECT 03 0000 [.const] gShaderCode_ci_FastDepthExpClear_CS 0000000000173810 long 0e SECT 03 0000 [.const] gShRegisters_ci_FastDepthExpClear_CS 0000000000173838 long 0e SECT 03 0000 [.const] gContextRegisters_ci_FastDepthExpClear_CS 0000000000173840 long 0e SECT 03 0000 [.const] gUserElementTable_ci_FastDepthExpClear_CS 0000000000173870 long 0e SECT 03 0000 [.const] gShaderCode_ci_LinGenDstRepackCopy_CS 0000000000173950 long 0e SECT 03 0000 [.const] gShRegisters_ci_LinGenDstRepackCopy_CS 0000000000173978 long 0e SECT 03 0000 [.const] gContextRegisters_ci_LinGenDstRepackCopy_CS 0000000000173980 long 0e SECT 03 0000 [.const] gUserElementTable_ci_LinGenDstRepackCopy_CS 00000000001739d0 long 0e SECT 03 0000 [.const] gShaderCode_ci_VolumeTexCopy_CS 0000000000173a60 long 0e SECT 03 0000 [.const] gShRegisters_ci_VolumeTexCopy_CS 0000000000173a88 long 0e SECT 03 0000 [.const] gContextRegisters_ci_VolumeTexCopy_CS 0000000000173a90 long 0e SECT 03 0000 [.const] gUserElementTable_ci_VolumeTexCopy_CS 0000000000173ae0 long 0e SECT 03 0000 [.const] gShaderCode_ci_GenerateHiS_PS 0000000000173b80 long 0e SECT 03 0000 [.const] gShRegisters_ci_GenerateHiS_PS 0000000000173b90 long 0e SECT 03 0000 [.const] gContextRegisters_ci_GenerateHiS_PS 0000000000173bd0 long 0e SECT 03 0000 [.const] gUserElementTable_ci_GenerateHiS_PS 0000000000173c20 long 0e SECT 03 0000 [.const] gInSemantics_ci_GenerateHiS_PS 0000000000173c34 long 0e SECT 03 0000 [.const] gPatchInfoOffset_ci_GenerateHiS_PS 0000000000173c40 long 0e SECT 03 0000 [.const] gPatchInfoCode_ci_GenerateHiS_PS 0000000000173ce0 long 0e SECT 03 0000 [.const] gShaderCode_ci_AdvAARes1_PS 0000000000173d40 long 0e SECT 03 0000 [.const] gShRegisters_ci_AdvAARes1_PS 0000000000173d50 long 0e SECT 03 0000 [.const] gContextRegisters_ci_AdvAARes1_PS 0000000000173d90 long 0e SECT 03 0000 [.const] gUserElementTable_ci_AdvAARes1_PS 0000000000173dc0 long 0e SECT 03 0000 [.const] gInSemantics_ci_AdvAARes1_PS 0000000000173dd4 long 0e SECT 03 0000 [.const] gPatchInfoOffset_ci_AdvAARes1_PS 0000000000173de0 long 0e SECT 03 0000 [.const] gPatchInfoCode_ci_AdvAARes1_PS 0000000000173f20 long 0e SECT 03 0000 [.const] gShaderCode_ci_AdvAAEdgeMask4Samp_PS 00000000001740f0 long 0e SECT 03 0000 [.const] gShRegisters_ci_AdvAAEdgeMask4Samp_PS 0000000000174100 long 0e SECT 03 0000 [.const] gContextRegisters_ci_AdvAAEdgeMask4Samp_PS 0000000000174140 long 0e SECT 03 0000 [.const] gUserElementTable_ci_AdvAAEdgeMask4Samp_PS 0000000000174170 long 0e SECT 03 0000 [.const] gInSemantics_ci_AdvAAEdgeMask4Samp_PS 0000000000174184 long 0e SECT 03 0000 [.const] gPatchInfoOffset_ci_AdvAAEdgeMask4Samp_PS 0000000000174190 long 0e SECT 03 0000 [.const] gPatchInfoCode_ci_AdvAAEdgeMask4Samp_PS 0000000000174370 long 0e SECT 03 0000 [.const] gShaderCode_ci_AdvAAEdgeMask8Samp_PS 0000000000174660 long 0e SECT 03 0000 [.const] gShRegisters_ci_AdvAAEdgeMask8Samp_PS 0000000000174670 long 0e SECT 03 0000 [.const] gContextRegisters_ci_AdvAAEdgeMask8Samp_PS 00000000001746b0 long 0e SECT 03 0000 [.const] gUserElementTable_ci_AdvAAEdgeMask8Samp_PS 00000000001746e0 long 0e SECT 03 0000 [.const] gInSemantics_ci_AdvAAEdgeMask8Samp_PS 00000000001746f4 long 0e SECT 03 0000 [.const] gPatchInfoOffset_ci_AdvAAEdgeMask8Samp_PS 0000000000174700 long 0e SECT 03 0000 [.const] gPatchInfoCode_ci_AdvAAEdgeMask8Samp_PS 00000000001748e0 long 0e SECT 03 0000 [.const] gShaderCode_ci_AdvAAFilterMaskFast_PS 0000000000174b20 long 0e SECT 03 0000 [.const] gShRegisters_ci_AdvAAFilterMaskFast_PS 0000000000174b30 long 0e SECT 03 0000 [.const] gContextRegisters_ci_AdvAAFilterMaskFast_PS 0000000000174b70 long 0e SECT 03 0000 [.const] gUserElementTable_ci_AdvAAFilterMaskFast_PS 0000000000174b90 long 0e SECT 03 0000 [.const] gInSemantics_ci_AdvAAFilterMaskFast_PS 0000000000174ba4 long 0e SECT 03 0000 [.const] gPatchInfoOffset_ci_AdvAAFilterMaskFast_PS 0000000000174bb0 long 0e SECT 03 0000 [.const] gPatchInfoCode_ci_AdvAAFilterMaskFast_PS 0000000000174c50 long 0e SECT 03 0000 [.const] gShaderCode_ci_AdvAAGrad4SampNoReZ_PS 0000000000176530 long 0e SECT 03 0000 [.const] gShRegisters_ci_AdvAAGrad4SampNoReZ_PS 0000000000176540 long 0e SECT 03 0000 [.const] gContextRegisters_ci_AdvAAGrad4SampNoReZ_PS 0000000000176580 long 0e SECT 03 0000 [.const] gUserElementTable_ci_AdvAAGrad4SampNoReZ_PS 00000000001765b0 long 0e SECT 03 0000 [.const] gInSemantics_ci_AdvAAGrad4SampNoReZ_PS 00000000001765c4 long 0e SECT 03 0000 [.const] gPatchInfoOffset_ci_AdvAAGrad4SampNoReZ_PS 00000000001765d0 long 0e SECT 03 0000 [.const] gPatchInfoCode_ci_AdvAAGrad4SampNoReZ_PS 0000000000176670 long 0e SECT 03 0000 [.const] gShaderCode_ci_AdvAAGrad8SampNoReZ_PS 00000000001797b0 long 0e SECT 03 0000 [.const] gShRegisters_ci_AdvAAGrad8SampNoReZ_PS 00000000001797c0 long 0e SECT 03 0000 [.const] gContextRegisters_ci_AdvAAGrad8SampNoReZ_PS 0000000000179800 long 0e SECT 03 0000 [.const] gUserElementTable_ci_AdvAAGrad8SampNoReZ_PS 0000000000179830 long 0e SECT 03 0000 [.const] gInSemantics_ci_AdvAAGrad8SampNoReZ_PS 0000000000179844 long 0e SECT 03 0000 [.const] gPatchInfoOffset_ci_AdvAAGrad8SampNoReZ_PS 0000000000179850 long 0e SECT 03 0000 [.const] gPatchInfoCode_ci_AdvAAGrad8SampNoReZ_PS 00000000001798f0 long 0e SECT 03 0000 [.const] gShaderCode_ci_AdvAAEdG4SampNoReZ_PS 000000000017b960 long 0e SECT 03 0000 [.const] gShRegisters_ci_AdvAAEdG4SampNoReZ_PS 000000000017b970 long 0e SECT 03 0000 [.const] gContextRegisters_ci_AdvAAEdG4SampNoReZ_PS 000000000017b9b0 long 0e SECT 03 0000 [.const] gUserElementTable_ci_AdvAAEdG4SampNoReZ_PS 000000000017b9e0 long 0e SECT 03 0000 [.const] gInSemantics_ci_AdvAAEdG4SampNoReZ_PS 000000000017b9f4 long 0e SECT 03 0000 [.const] gPatchInfoOffset_ci_AdvAAEdG4SampNoReZ_PS 000000000017ba00 long 0e SECT 03 0000 [.const] gPatchInfoCode_ci_AdvAAEdG4SampNoReZ_PS 000000000017baa0 long 0e SECT 03 0000 [.const] gShaderCode_ci_AdvAAEdG8SampNoReZ_PS 000000000017fa70 long 0e SECT 03 0000 [.const] gShRegisters_ci_AdvAAEdG8SampNoReZ_PS 000000000017fa80 long 0e SECT 03 0000 [.const] gContextRegisters_ci_AdvAAEdG8SampNoReZ_PS 000000000017fac0 long 0e SECT 03 0000 [.const] gUserElementTable_ci_AdvAAEdG8SampNoReZ_PS 000000000017faf0 long 0e SECT 03 0000 [.const] gInSemantics_ci_AdvAAEdG8SampNoReZ_PS 000000000017fb04 long 0e SECT 03 0000 [.const] gPatchInfoOffset_ci_AdvAAEdG8SampNoReZ_PS 000000000017fb10 long 0e SECT 03 0000 [.const] gPatchInfoCode_ci_AdvAAEdG8SampNoReZ_PS 000000000017fbb0 long 0e SECT 03 0000 [.const] gShaderCode_ci_AdvAAFMaskEdgeMask4Samp_PS 000000000017fe20 long 0e SECT 03 0000 [.const] gShRegisters_ci_AdvAAFMaskEdgeMask4Samp_PS 000000000017fe30 long 0e SECT 03 0000 [.const] gContextRegisters_ci_AdvAAFMaskEdgeMask4Samp_PS 000000000017fe70 long 0e SECT 03 0000 [.const] gUserElementTable_ci_AdvAAFMaskEdgeMask4Samp_PS 000000000017fea0 long 0e SECT 03 0000 [.const] gInSemantics_ci_AdvAAFMaskEdgeMask4Samp_PS 000000000017feb4 long 0e SECT 03 0000 [.const] gPatchInfoOffset_ci_AdvAAFMaskEdgeMask4Samp_PS 000000000017fec0 long 0e SECT 03 0000 [.const] gPatchInfoCode_ci_AdvAAFMaskEdgeMask4Samp_PS 00000000001800a0 long 0e SECT 03 0000 [.const] gShaderCode_ci_AdvAAFMaskEdgeMask8Samp_PS 0000000000180520 long 0e SECT 03 0000 [.const] gShRegisters_ci_AdvAAFMaskEdgeMask8Samp_PS 0000000000180530 long 0e SECT 03 0000 [.const] gContextRegisters_ci_AdvAAFMaskEdgeMask8Samp_PS 0000000000180570 long 0e SECT 03 0000 [.const] gUserElementTable_ci_AdvAAFMaskEdgeMask8Samp_PS 00000000001805a0 long 0e SECT 03 0000 [.const] gInSemantics_ci_AdvAAFMaskEdgeMask8Samp_PS 00000000001805b4 long 0e SECT 03 0000 [.const] gPatchInfoOffset_ci_AdvAAFMaskEdgeMask8Samp_PS 00000000001805c0 long 0e SECT 03 0000 [.const] gPatchInfoCode_ci_AdvAAFMaskEdgeMask8Samp_PS 00000000001807a0 long 0e SECT 03 0000 [.const] gShaderCode_ci_AdvAAFMaskEdG4SampNoReZ_PS 00000000001829b0 long 0e SECT 03 0000 [.const] gShRegisters_ci_AdvAAFMaskEdG4SampNoReZ_PS 00000000001829c0 long 0e SECT 03 0000 [.const] gContextRegisters_ci_AdvAAFMaskEdG4SampNoReZ_PS 0000000000182a00 long 0e SECT 03 0000 [.const] gUserElementTable_ci_AdvAAFMaskEdG4SampNoReZ_PS 0000000000182a30 long 0e SECT 03 0000 [.const] gInSemantics_ci_AdvAAFMaskEdG4SampNoReZ_PS 0000000000182a44 long 0e SECT 03 0000 [.const] gPatchInfoOffset_ci_AdvAAFMaskEdG4SampNoReZ_PS 0000000000182a50 long 0e SECT 03 0000 [.const] gPatchInfoCode_ci_AdvAAFMaskEdG4SampNoReZ_PS 0000000000182af0 long 0e SECT 03 0000 [.const] gShaderCode_ci_AdvAAFMaskEdG8SampNoReZ_PS 0000000000186d30 long 0e SECT 03 0000 [.const] gShRegisters_ci_AdvAAFMaskEdG8SampNoReZ_PS 0000000000186d40 long 0e SECT 03 0000 [.const] gContextRegisters_ci_AdvAAFMaskEdG8SampNoReZ_PS 0000000000186d80 long 0e SECT 03 0000 [.const] gUserElementTable_ci_AdvAAFMaskEdG8SampNoReZ_PS 0000000000186db0 long 0e SECT 03 0000 [.const] gInSemantics_ci_AdvAAFMaskEdG8SampNoReZ_PS 0000000000186dc4 long 0e SECT 03 0000 [.const] gPatchInfoOffset_ci_AdvAAFMaskEdG8SampNoReZ_PS 0000000000186dd0 long 0e SECT 03 0000 [.const] gPatchInfoCode_ci_AdvAAFMaskEdG8SampNoReZ_PS 0000000000186e70 long 0e SECT 03 0000 [.const] gShaderCode_vi_RectPos_VS 0000000000186fc0 long 0e SECT 03 0000 [.const] gShRegisters_vi_RectPos_VS 0000000000186fd0 long 0e SECT 03 0000 [.const] gContextRegisters_vi_RectPos_VS 0000000000186fe0 long 0e SECT 03 0000 [.const] gUserElementTable_vi_RectPos_VS 0000000000187010 long 0e SECT 03 0000 [.const] gOutSemantics_vi_RectPos_VS 0000000000187020 long 0e SECT 03 0000 [.const] gShaderCode_vi_RectPosTexTex_VS 00000000001874b0 long 0e SECT 03 0000 [.const] gShRegisters_vi_RectPosTexTex_VS 00000000001874c0 long 0e SECT 03 0000 [.const] gContextRegisters_vi_RectPosTexTex_VS 00000000001874d0 long 0e SECT 03 0000 [.const] gUserElementTable_vi_RectPosTexTex_VS 0000000000187500 long 0e SECT 03 0000 [.const] gOutSemantics_vi_RectPosTexTex_VS 0000000000187520 long 0e SECT 03 0000 [.const] gShaderCode_vi_RectPosTexFast_VS 00000000001875b0 long 0e SECT 03 0000 [.const] gShRegisters_vi_RectPosTexFast_VS 00000000001875c0 long 0e SECT 03 0000 [.const] gContextRegisters_vi_RectPosTexFast_VS 00000000001875d0 long 0e SECT 03 0000 [.const] gUserElementTable_vi_RectPosTexFast_VS 0000000000187630 long 0e SECT 03 0000 [.const] gOutSemantics_vi_RectPosTexFast_VS 0000000000187640 long 0e SECT 03 0000 [.const] gShaderCode_vi_VertPosColor_VS 0000000000187690 long 0e SECT 03 0000 [.const] gShRegisters_vi_VertPosColor_VS 00000000001876a0 long 0e SECT 03 0000 [.const] gContextRegisters_vi_VertPosColor_VS 00000000001876b0 long 0e SECT 03 0000 [.const] gUserElementTable_vi_VertPosColor_VS 00000000001876e0 long 0e SECT 03 0000 [.const] gOutSemantics_vi_VertPosColor_VS 00000000001876f0 long 0e SECT 03 0000 [.const] gShaderCode_vi_RectPosTexTexComposite_VS 00000000001878c0 long 0e SECT 03 0000 [.const] gShRegisters_vi_RectPosTexTexComposite_VS 00000000001878d0 long 0e SECT 03 0000 [.const] gContextRegisters_vi_RectPosTexTexComposite_VS 00000000001878e0 long 0e SECT 03 0000 [.const] gUserElementTable_vi_RectPosTexTexComposite_VS 0000000000187910 long 0e SECT 03 0000 [.const] gOutSemantics_vi_RectPosTexTexComposite_VS 0000000000187930 long 0e SECT 03 0000 [.const] gShaderCode_vi_Zero_PS 0000000000187950 long 0e SECT 03 0000 [.const] gShRegisters_vi_Zero_PS 0000000000187960 long 0e SECT 03 0000 [.const] gContextRegisters_vi_Zero_PS 00000000001879a0 long 0e SECT 03 0000 [.const] gUserElementTable_vi_Zero_PS 00000000001879c0 long 0e SECT 03 0000 [.const] gInSemantics_vi_Zero_PS 00000000001879d4 long 0e SECT 03 0000 [.const] gPatchInfoOffset_vi_Zero_PS 00000000001879e0 long 0e SECT 03 0000 [.const] gPatchInfoCode_vi_Zero_PS 0000000000187ad0 long 0e SECT 03 0000 [.const] gShaderCode_vi_Const_PS 0000000000187b00 long 0e SECT 03 0000 [.const] gShRegisters_vi_Const_PS 0000000000187b10 long 0e SECT 03 0000 [.const] gContextRegisters_vi_Const_PS 0000000000187b50 long 0e SECT 03 0000 [.const] gUserElementTable_vi_Const_PS 0000000000187b70 long 0e SECT 03 0000 [.const] gInSemantics_vi_Const_PS 0000000000187b84 long 0e SECT 03 0000 [.const] gPatchInfoOffset_vi_Const_PS 0000000000187b90 long 0e SECT 03 0000 [.const] gPatchInfoCode_vi_Const_PS 0000000000187c80 long 0e SECT 03 0000 [.const] gShaderCode_vi_Tex_PS 0000000000187cd0 long 0e SECT 03 0000 [.const] gShRegisters_vi_Tex_PS 0000000000187ce0 long 0e SECT 03 0000 [.const] gContextRegisters_vi_Tex_PS 0000000000187d20 long 0e SECT 03 0000 [.const] gUserElementTable_vi_Tex_PS 0000000000187d50 long 0e SECT 03 0000 [.const] gInSemantics_vi_Tex_PS 0000000000187d64 long 0e SECT 03 0000 [.const] gPatchInfoOffset_vi_Tex_PS 0000000000187d70 long 0e SECT 03 0000 [.const] gPatchInfoCode_vi_Tex_PS 0000000000187e60 long 0e SECT 03 0000 [.const] gShaderCode_vi_TexCoord_PS 0000000000187ea0 long 0e SECT 03 0000 [.const] gShRegisters_vi_TexCoord_PS 0000000000187eb0 long 0e SECT 03 0000 [.const] gContextRegisters_vi_TexCoord_PS 0000000000187ef0 long 0e SECT 03 0000 [.const] gUserElementTable_vi_TexCoord_PS 0000000000187f10 long 0e SECT 03 0000 [.const] gInSemantics_vi_TexCoord_PS 0000000000187f24 long 0e SECT 03 0000 [.const] gPatchInfoOffset_vi_TexCoord_PS 0000000000187f30 long 0e SECT 03 0000 [.const] gPatchInfoCode_vi_TexCoord_PS 0000000000188020 long 0e SECT 03 0000 [.const] gShaderCode_vi_TexGammaDst_PS 0000000000188120 long 0e SECT 03 0000 [.const] gShRegisters_vi_TexGammaDst_PS 0000000000188130 long 0e SECT 03 0000 [.const] gContextRegisters_vi_TexGammaDst_PS 0000000000188170 long 0e SECT 03 0000 [.const] gUserElementTable_vi_TexGammaDst_PS 00000000001881a0 long 0e SECT 03 0000 [.const] gInSemantics_vi_TexGammaDst_PS 00000000001881b4 long 0e SECT 03 0000 [.const] gPatchInfoOffset_vi_TexGammaDst_PS 00000000001881c0 long 0e SECT 03 0000 [.const] gPatchInfoCode_vi_TexGammaDst_PS 00000000001882b0 long 0e SECT 03 0000 [.const] gShaderCode_vi_MsaaResolve1_PS 0000000000188300 long 0e SECT 03 0000 [.const] gShRegisters_vi_MsaaResolve1_PS 0000000000188310 long 0e SECT 03 0000 [.const] gContextRegisters_vi_MsaaResolve1_PS 0000000000188350 long 0e SECT 03 0000 [.const] gUserElementTable_vi_MsaaResolve1_PS 0000000000188380 long 0e SECT 03 0000 [.const] gInSemantics_vi_MsaaResolve1_PS 0000000000188394 long 0e SECT 03 0000 [.const] gPatchInfoOffset_vi_MsaaResolve1_PS 00000000001883a0 long 0e SECT 03 0000 [.const] gPatchInfoCode_vi_MsaaResolve1_PS 0000000000188490 long 0e SECT 03 0000 [.const] gShaderCode_vi_MsaaResolve2_PS 0000000000188510 long 0e SECT 03 0000 [.const] gShRegisters_vi_MsaaResolve2_PS 0000000000188520 long 0e SECT 03 0000 [.const] gContextRegisters_vi_MsaaResolve2_PS 0000000000188560 long 0e SECT 03 0000 [.const] gUserElementTable_vi_MsaaResolve2_PS 0000000000188590 long 0e SECT 03 0000 [.const] gInSemantics_vi_MsaaResolve2_PS 00000000001885a4 long 0e SECT 03 0000 [.const] gPatchInfoOffset_vi_MsaaResolve2_PS 00000000001885b0 long 0e SECT 03 0000 [.const] gPatchInfoCode_vi_MsaaResolve2_PS 00000000001886a0 long 0e SECT 03 0000 [.const] gShaderCode_vi_MsaaResolve4_PS 0000000000188760 long 0e SECT 03 0000 [.const] gShRegisters_vi_MsaaResolve4_PS 0000000000188770 long 0e SECT 03 0000 [.const] gContextRegisters_vi_MsaaResolve4_PS 00000000001887b0 long 0e SECT 03 0000 [.const] gUserElementTable_vi_MsaaResolve4_PS 00000000001887e0 long 0e SECT 03 0000 [.const] gInSemantics_vi_MsaaResolve4_PS 00000000001887f4 long 0e SECT 03 0000 [.const] gPatchInfoOffset_vi_MsaaResolve4_PS 0000000000188800 long 0e SECT 03 0000 [.const] gPatchInfoCode_vi_MsaaResolve4_PS 00000000001888f0 long 0e SECT 03 0000 [.const] gShaderCode_vi_MsaaResolve8_PS 0000000000188a20 long 0e SECT 03 0000 [.const] gShRegisters_vi_MsaaResolve8_PS 0000000000188a30 long 0e SECT 03 0000 [.const] gContextRegisters_vi_MsaaResolve8_PS 0000000000188a70 long 0e SECT 03 0000 [.const] gUserElementTable_vi_MsaaResolve8_PS 0000000000188aa0 long 0e SECT 03 0000 [.const] gInSemantics_vi_MsaaResolve8_PS 0000000000188ab4 long 0e SECT 03 0000 [.const] gPatchInfoOffset_vi_MsaaResolve8_PS 0000000000188ac0 long 0e SECT 03 0000 [.const] gPatchInfoCode_vi_MsaaResolve8_PS 0000000000188bb0 long 0e SECT 03 0000 [.const] gShaderCode_vi_MsaaFMaskExpand_PS 0000000000188c60 long 0e SECT 03 0000 [.const] gShRegisters_vi_MsaaFMaskExpand_PS 0000000000188c70 long 0e SECT 03 0000 [.const] gContextRegisters_vi_MsaaFMaskExpand_PS 0000000000188cb0 long 0e SECT 03 0000 [.const] gUserElementTable_vi_MsaaFMaskExpand_PS 0000000000188ce0 long 0e SECT 03 0000 [.const] gInSemantics_vi_MsaaFMaskExpand_PS 0000000000188cf4 long 0e SECT 03 0000 [.const] gPatchInfoOffset_vi_MsaaFMaskExpand_PS 0000000000188d00 long 0e SECT 03 0000 [.const] gPatchInfoCode_vi_MsaaFMaskExpand_PS 0000000000188df0 long 0e SECT 03 0000 [.const] gShaderCode_vi_MsaaDepthResolve_PS 0000000000188e40 long 0e SECT 03 0000 [.const] gShRegisters_vi_MsaaDepthResolve_PS 0000000000188e50 long 0e SECT 03 0000 [.const] gContextRegisters_vi_MsaaDepthResolve_PS 0000000000188e90 long 0e SECT 03 0000 [.const] gUserElementTable_vi_MsaaDepthResolve_PS 0000000000188ec0 long 0e SECT 03 0000 [.const] gInSemantics_vi_MsaaDepthResolve_PS 0000000000188ed4 long 0e SECT 03 0000 [.const] gPatchInfoOffset_vi_MsaaDepthResolve_PS 0000000000188ee0 long 0e SECT 03 0000 [.const] gPatchInfoCode_vi_MsaaDepthResolve_PS 0000000000188fd0 long 0e SECT 03 0000 [.const] gShaderCode_vi_MsaaDepthStencilResolve_PS 0000000000189040 long 0e SECT 03 0000 [.const] gShRegisters_vi_MsaaDepthStencilResolve_PS 0000000000189050 long 0e SECT 03 0000 [.const] gContextRegisters_vi_MsaaDepthStencilResolve_PS 0000000000189090 long 0e SECT 03 0000 [.const] gUserElementTable_vi_MsaaDepthStencilResolve_PS 00000000001890e0 long 0e SECT 03 0000 [.const] gInSemantics_vi_MsaaDepthStencilResolve_PS 00000000001890f4 long 0e SECT 03 0000 [.const] gPatchInfoOffset_vi_MsaaDepthStencilResolve_PS 0000000000189100 long 0e SECT 03 0000 [.const] gPatchInfoCode_vi_MsaaDepthStencilResolve_PS 00000000001891f0 long 0e SECT 03 0000 [.const] gShaderCode_vi_TexZStencilAsColor_PS 0000000000189260 long 0e SECT 03 0000 [.const] gShRegisters_vi_TexZStencilAsColor_PS 0000000000189270 long 0e SECT 03 0000 [.const] gContextRegisters_vi_TexZStencilAsColor_PS 00000000001892b0 long 0e SECT 03 0000 [.const] gUserElementTable_vi_TexZStencilAsColor_PS 0000000000189300 long 0e SECT 03 0000 [.const] gInSemantics_vi_TexZStencilAsColor_PS 0000000000189314 long 0e SECT 03 0000 [.const] gPatchInfoOffset_vi_TexZStencilAsColor_PS 0000000000189320 long 0e SECT 03 0000 [.const] gPatchInfoCode_vi_TexZStencilAsColor_PS 0000000000189410 long 0e SECT 03 0000 [.const] gShRegisters_vi_TexAlphaOne_PS 0000000000189420 long 0e SECT 03 0000 [.const] gContextRegisters_vi_TexAlphaOne_PS 0000000000189460 long 0e SECT 03 0000 [.const] gUserElementTable_vi_TexAlphaOne_PS 0000000000189490 long 0e SECT 03 0000 [.const] gInSemantics_vi_TexAlphaOne_PS 00000000001894a4 long 0e SECT 03 0000 [.const] gPatchInfoOffset_vi_TexAlphaOne_PS 00000000001894b0 long 0e SECT 03 0000 [.const] gPatchInfoCode_vi_TexAlphaOne_PS 00000000001895a0 long 0e SECT 03 0000 [.const] gShaderCode_vi_TexAlphaOneInt_PS 00000000001895f0 long 0e SECT 03 0000 [.const] gShRegisters_vi_TexAlphaOneInt_PS 0000000000189600 long 0e SECT 03 0000 [.const] gContextRegisters_vi_TexAlphaOneInt_PS 0000000000189640 long 0e SECT 03 0000 [.const] gUserElementTable_vi_TexAlphaOneInt_PS 0000000000189670 long 0e SECT 03 0000 [.const] gInSemantics_vi_TexAlphaOneInt_PS 0000000000189684 long 0e SECT 03 0000 [.const] gPatchInfoOffset_vi_TexAlphaOneInt_PS 0000000000189690 long 0e SECT 03 0000 [.const] gPatchInfoCode_vi_TexAlphaOneInt_PS 0000000000189780 long 0e SECT 03 0000 [.const] gShaderCode_vi_MsaaTexZStencilAsColor_PS 00000000001897f0 long 0e SECT 03 0000 [.const] gShRegisters_vi_MsaaTexZStencilAsColor_PS 0000000000189800 long 0e SECT 03 0000 [.const] gContextRegisters_vi_MsaaTexZStencilAsColor_PS 0000000000189840 long 0e SECT 03 0000 [.const] gUserElementTable_vi_MsaaTexZStencilAsColor_PS 0000000000189860 long 0e SECT 03 0000 [.const] gInSemantics_vi_MsaaTexZStencilAsColor_PS 0000000000189874 long 0e SECT 03 0000 [.const] gPatchInfoOffset_vi_MsaaTexZStencilAsColor_PS 0000000000189880 long 0e SECT 03 0000 [.const] gPatchInfoCode_vi_MsaaTexZStencilAsColor_PS 0000000000189970 long 0e SECT 03 0000 [.const] gShaderCode_vi_TexAsZ_PS 00000000001899c0 long 0e SECT 03 0000 [.const] gShRegisters_vi_TexAsZ_PS 00000000001899d0 long 0e SECT 03 0000 [.const] gContextRegisters_vi_TexAsZ_PS 0000000000189a10 long 0e SECT 03 0000 [.const] gUserElementTable_vi_TexAsZ_PS 0000000000189a40 long 0e SECT 03 0000 [.const] gInSemantics_vi_TexAsZ_PS 0000000000189a54 long 0e SECT 03 0000 [.const] gPatchInfoOffset_vi_TexAsZ_PS 0000000000189a60 long 0e SECT 03 0000 [.const] gPatchInfoCode_vi_TexAsZ_PS 0000000000189b50 long 0e SECT 03 0000 [.const] gShaderCode_vi_TexAsZStencil_PS 0000000000189bc0 long 0e SECT 03 0000 [.const] gShRegisters_vi_TexAsZStencil_PS 0000000000189bd0 long 0e SECT 03 0000 [.const] gContextRegisters_vi_TexAsZStencil_PS 0000000000189c10 long 0e SECT 03 0000 [.const] gUserElementTable_vi_TexAsZStencil_PS 0000000000189c60 long 0e SECT 03 0000 [.const] gInSemantics_vi_TexAsZStencil_PS 0000000000189c74 long 0e SECT 03 0000 [.const] gPatchInfoOffset_vi_TexAsZStencil_PS 0000000000189c80 long 0e SECT 03 0000 [.const] gPatchInfoCode_vi_TexAsZStencil_PS 0000000000189d70 long 0e SECT 03 0000 [.const] gShaderCode_vi_MsaaTexAsZ_PS 0000000000189dc0 long 0e SECT 03 0000 [.const] gShRegisters_vi_MsaaTexAsZ_PS 0000000000189dd0 long 0e SECT 03 0000 [.const] gContextRegisters_vi_MsaaTexAsZ_PS 0000000000189e10 long 0e SECT 03 0000 [.const] gUserElementTable_vi_MsaaTexAsZ_PS 0000000000189e40 long 0e SECT 03 0000 [.const] gInSemantics_vi_MsaaTexAsZ_PS 0000000000189e54 long 0e SECT 03 0000 [.const] gPatchInfoOffset_vi_MsaaTexAsZ_PS 0000000000189e60 long 0e SECT 03 0000 [.const] gPatchInfoCode_vi_MsaaTexAsZ_PS 0000000000189f50 long 0e SECT 03 0000 [.const] gShaderCode_vi_MsaaTexAsZStencil_PS 0000000000189fc0 long 0e SECT 03 0000 [.const] gShRegisters_vi_MsaaTexAsZStencil_PS 0000000000189fd0 long 0e SECT 03 0000 [.const] gContextRegisters_vi_MsaaTexAsZStencil_PS 000000000018a010 long 0e SECT 03 0000 [.const] gUserElementTable_vi_MsaaTexAsZStencil_PS 000000000018a060 long 0e SECT 03 0000 [.const] gInSemantics_vi_MsaaTexAsZStencil_PS 000000000018a074 long 0e SECT 03 0000 [.const] gPatchInfoOffset_vi_MsaaTexAsZStencil_PS 000000000018a080 long 0e SECT 03 0000 [.const] gPatchInfoCode_vi_MsaaTexAsZStencil_PS 000000000018a170 long 0e SECT 03 0000 [.const] gShaderCode_vi_VolTex_PS 000000000018a1c0 long 0e SECT 03 0000 [.const] gShRegisters_vi_VolTex_PS 000000000018a1d0 long 0e SECT 03 0000 [.const] gContextRegisters_vi_VolTex_PS 000000000018a210 long 0e SECT 03 0000 [.const] gUserElementTable_vi_VolTex_PS 000000000018a240 long 0e SECT 03 0000 [.const] gInSemantics_vi_VolTex_PS 000000000018a254 long 0e SECT 03 0000 [.const] gPatchInfoOffset_vi_VolTex_PS 000000000018a260 long 0e SECT 03 0000 [.const] gPatchInfoCode_vi_VolTex_PS 000000000018a350 long 0e SECT 03 0000 [.const] gShaderCode_vi_AAText_PS 000000000018a430 long 0e SECT 03 0000 [.const] gShRegisters_vi_AAText_PS 000000000018a440 long 0e SECT 03 0000 [.const] gContextRegisters_vi_AAText_PS 000000000018a480 long 0e SECT 03 0000 [.const] gUserElementTable_vi_AAText_PS 000000000018a4d0 long 0e SECT 03 0000 [.const] gInSemantics_vi_AAText_PS 000000000018a4e4 long 0e SECT 03 0000 [.const] gPatchInfoOffset_vi_AAText_PS 000000000018a4f0 long 0e SECT 03 0000 [.const] gPatchInfoCode_vi_AAText_PS 000000000018a5e0 long 0e SECT 03 0000 [.const] gShaderCode_vi_SlowAAText_PS 000000000018a6c0 long 0e SECT 03 0000 [.const] gShRegisters_vi_SlowAAText_PS 000000000018a6d0 long 0e SECT 03 0000 [.const] gContextRegisters_vi_SlowAAText_PS 000000000018a710 long 0e SECT 03 0000 [.const] gUserElementTable_vi_SlowAAText_PS 000000000018a770 long 0e SECT 03 0000 [.const] gInSemantics_vi_SlowAAText_PS 000000000018a798 long 0e SECT 03 0000 [.const] gPatchInfoOffset_vi_SlowAAText_PS 000000000018a7a0 long 0e SECT 03 0000 [.const] gPatchInfoCode_vi_SlowAAText_PS 000000000018a890 long 0e SECT 03 0000 [.const] gShaderCode_vi_ClearTypeGamma_PS 000000000018aa40 long 0e SECT 03 0000 [.const] gShRegisters_vi_ClearTypeGamma_PS 000000000018aa50 long 0e SECT 03 0000 [.const] gContextRegisters_vi_ClearTypeGamma_PS 000000000018aa90 long 0e SECT 03 0000 [.const] gUserElementTable_vi_ClearTypeGamma_PS 000000000018aae0 long 0e SECT 03 0000 [.const] gInSemantics_vi_ClearTypeGamma_PS 000000000018ab08 long 0e SECT 03 0000 [.const] gPatchInfoOffset_vi_ClearTypeGamma_PS 000000000018ab10 long 0e SECT 03 0000 [.const] gPatchInfoCode_vi_ClearTypeGamma_PS 000000000018ac00 long 0e SECT 03 0000 [.const] gShaderCode_vi_TexColorKey_PS 000000000018ada0 long 0e SECT 03 0000 [.const] gShRegisters_vi_TexColorKey_PS 000000000018adb0 long 0e SECT 03 0000 [.const] gContextRegisters_vi_TexColorKey_PS 000000000018adf0 long 0e SECT 03 0000 [.const] gUserElementTable_vi_TexColorKey_PS 000000000018ae50 long 0e SECT 03 0000 [.const] gInSemantics_vi_TexColorKey_PS 000000000018ae78 long 0e SECT 03 0000 [.const] gPatchInfoOffset_vi_TexColorKey_PS 000000000018ae80 long 0e SECT 03 0000 [.const] gPatchInfoCode_vi_TexColorKey_PS 000000000018af70 long 0e SECT 03 0000 [.const] gShaderCode_vi_TexSrcColorKey_PS 000000000018b060 long 0e SECT 03 0000 [.const] gShRegisters_vi_TexSrcColorKey_PS 000000000018b070 long 0e SECT 03 0000 [.const] gContextRegisters_vi_TexSrcColorKey_PS 000000000018b0b0 long 0e SECT 03 0000 [.const] gUserElementTable_vi_TexSrcColorKey_PS 000000000018b100 long 0e SECT 03 0000 [.const] gInSemantics_vi_TexSrcColorKey_PS 000000000018b114 long 0e SECT 03 0000 [.const] gPatchInfoOffset_vi_TexSrcColorKey_PS 000000000018b120 long 0e SECT 03 0000 [.const] gPatchInfoCode_vi_TexSrcColorKey_PS 000000000018b210 long 0e SECT 03 0000 [.const] gShaderCode_vi_TexMulConst_PS 000000000018b280 long 0e SECT 03 0000 [.const] gShRegisters_vi_TexMulConst_PS 000000000018b290 long 0e SECT 03 0000 [.const] gContextRegisters_vi_TexMulConst_PS 000000000018b2d0 long 0e SECT 03 0000 [.const] gUserElementTable_vi_TexMulConst_PS 000000000018b320 long 0e SECT 03 0000 [.const] gInSemantics_vi_TexMulConst_PS 000000000018b334 long 0e SECT 03 0000 [.const] gPatchInfoOffset_vi_TexMulConst_PS 000000000018b340 long 0e SECT 03 0000 [.const] gPatchInfoCode_vi_TexMulConst_PS 000000000018b430 long 0e SECT 03 0000 [.const] gShaderCode_vi_TexDither_PS 000000000018b4b0 long 0e SECT 03 0000 [.const] gShRegisters_vi_TexDither_PS 000000000018b4c0 long 0e SECT 03 0000 [.const] gContextRegisters_vi_TexDither_PS 000000000018b500 long 0e SECT 03 0000 [.const] gUserElementTable_vi_TexDither_PS 000000000018b560 long 0e SECT 03 0000 [.const] gInSemantics_vi_TexDither_PS 000000000018b574 long 0e SECT 03 0000 [.const] gPatchInfoOffset_vi_TexDither_PS 000000000018b580 long 0e SECT 03 0000 [.const] gPatchInfoCode_vi_TexDither_PS 000000000018b670 long 0e SECT 03 0000 [.const] gShaderCode_vi_YuvToRgb_PS 000000000018b790 long 0e SECT 03 0000 [.const] gShRegisters_vi_YuvToRgb_PS 000000000018b7a0 long 0e SECT 03 0000 [.const] gContextRegisters_vi_YuvToRgb_PS 000000000018b7e0 long 0e SECT 03 0000 [.const] gUserElementTable_vi_YuvToRgb_PS 000000000018b830 long 0e SECT 03 0000 [.const] gInSemantics_vi_YuvToRgb_PS 000000000018b844 long 0e SECT 03 0000 [.const] gPatchInfoOffset_vi_YuvToRgb_PS 000000000018b850 long 0e SECT 03 0000 [.const] gPatchInfoCode_vi_YuvToRgb_PS 000000000018b940 long 0e SECT 03 0000 [.const] gShaderCode_vi_YuvIntUvToRgb_PS 000000000018ba30 long 0e SECT 03 0000 [.const] gShRegisters_vi_YuvIntUvToRgb_PS 000000000018ba40 long 0e SECT 03 0000 [.const] gContextRegisters_vi_YuvIntUvToRgb_PS 000000000018ba80 long 0e SECT 03 0000 [.const] gUserElementTable_vi_YuvIntUvToRgb_PS 000000000018bae0 long 0e SECT 03 0000 [.const] gInSemantics_vi_YuvIntUvToRgb_PS 000000000018baf4 long 0e SECT 03 0000 [.const] gPatchInfoOffset_vi_YuvIntUvToRgb_PS 000000000018bb00 long 0e SECT 03 0000 [.const] gPatchInfoCode_vi_YuvIntUvToRgb_PS 000000000018bbf0 long 0e SECT 03 0000 [.const] gShaderCode_vi_YuvIntUvToYuy2_PS 000000000018bcb0 long 0e SECT 03 0000 [.const] gShRegisters_vi_YuvIntUvToYuy2_PS 000000000018bcc0 long 0e SECT 03 0000 [.const] gContextRegisters_vi_YuvIntUvToYuy2_PS 000000000018bd00 long 0e SECT 03 0000 [.const] gUserElementTable_vi_YuvIntUvToYuy2_PS 000000000018bd60 long 0e SECT 03 0000 [.const] gInSemantics_vi_YuvIntUvToYuy2_PS 000000000018bd74 long 0e SECT 03 0000 [.const] gPatchInfoOffset_vi_YuvIntUvToYuy2_PS 000000000018bd80 long 0e SECT 03 0000 [.const] gPatchInfoCode_vi_YuvIntUvToYuy2_PS 000000000018be70 long 0e SECT 03 0000 [.const] gShaderCode_vi_YuvToYuy2_PS 000000000018bf50 long 0e SECT 03 0000 [.const] gShRegisters_vi_YuvToYuy2_PS 000000000018bf60 long 0e SECT 03 0000 [.const] gContextRegisters_vi_YuvToYuy2_PS 000000000018bfa0 long 0e SECT 03 0000 [.const] gUserElementTable_vi_YuvToYuy2_PS 000000000018bff0 long 0e SECT 03 0000 [.const] gInSemantics_vi_YuvToYuy2_PS 000000000018c004 long 0e SECT 03 0000 [.const] gPatchInfoOffset_vi_YuvToYuy2_PS 000000000018c010 long 0e SECT 03 0000 [.const] gPatchInfoCode_vi_YuvToYuy2_PS 000000000018c100 long 0e SECT 03 0000 [.const] gShaderCode_vi_MsaaFMaskResolve2_PS 000000000018c1d0 long 0e SECT 03 0000 [.const] gShRegisters_vi_MsaaFMaskResolve2_PS 000000000018c1e0 long 0e SECT 03 0000 [.const] gContextRegisters_vi_MsaaFMaskResolve2_PS 000000000018c220 long 0e SECT 03 0000 [.const] gUserElementTable_vi_MsaaFMaskResolve2_PS 000000000018c250 long 0e SECT 03 0000 [.const] gInSemantics_vi_MsaaFMaskResolve2_PS 000000000018c264 long 0e SECT 03 0000 [.const] gPatchInfoOffset_vi_MsaaFMaskResolve2_PS 000000000018c270 long 0e SECT 03 0000 [.const] gPatchInfoCode_vi_MsaaFMaskResolve2_PS 000000000018c360 long 0e SECT 03 0000 [.const] gShaderCode_vi_MsaaFMaskResolve4_PS 000000000018c4b0 long 0e SECT 03 0000 [.const] gShRegisters_vi_MsaaFMaskResolve4_PS 000000000018c4c0 long 0e SECT 03 0000 [.const] gContextRegisters_vi_MsaaFMaskResolve4_PS 000000000018c500 long 0e SECT 03 0000 [.const] gUserElementTable_vi_MsaaFMaskResolve4_PS 000000000018c530 long 0e SECT 03 0000 [.const] gInSemantics_vi_MsaaFMaskResolve4_PS 000000000018c544 long 0e SECT 03 0000 [.const] gPatchInfoOffset_vi_MsaaFMaskResolve4_PS 000000000018c550 long 0e SECT 03 0000 [.const] gPatchInfoCode_vi_MsaaFMaskResolve4_PS 000000000018c640 long 0e SECT 03 0000 [.const] gShaderCode_vi_MsaaFMaskResolve8_PS 000000000018c830 long 0e SECT 03 0000 [.const] gShRegisters_vi_MsaaFMaskResolve8_PS 000000000018c840 long 0e SECT 03 0000 [.const] gContextRegisters_vi_MsaaFMaskResolve8_PS 000000000018c880 long 0e SECT 03 0000 [.const] gUserElementTable_vi_MsaaFMaskResolve8_PS 000000000018c8b0 long 0e SECT 03 0000 [.const] gInSemantics_vi_MsaaFMaskResolve8_PS 000000000018c8c4 long 0e SECT 03 0000 [.const] gPatchInfoOffset_vi_MsaaFMaskResolve8_PS 000000000018c8d0 long 0e SECT 03 0000 [.const] gPatchInfoCode_vi_MsaaFMaskResolve8_PS 000000000018c9c0 long 0e SECT 03 0000 [.const] gShaderCode_vi_MsaaFMaskResolve2Frag4Samp_PS 000000000018cb80 long 0e SECT 03 0000 [.const] gShRegisters_vi_MsaaFMaskResolve2Frag4Samp_PS 000000000018cb90 long 0e SECT 03 0000 [.const] gContextRegisters_vi_MsaaFMaskResolve2Frag4Samp_PS 000000000018cbd0 long 0e SECT 03 0000 [.const] gUserElementTable_vi_MsaaFMaskResolve2Frag4Samp_PS 000000000018cc00 long 0e SECT 03 0000 [.const] gInSemantics_vi_MsaaFMaskResolve2Frag4Samp_PS 000000000018cc14 long 0e SECT 03 0000 [.const] gPatchInfoOffset_vi_MsaaFMaskResolve2Frag4Samp_PS 000000000018cc20 long 0e SECT 03 0000 [.const] gPatchInfoCode_vi_MsaaFMaskResolve2Frag4Samp_PS 000000000018cd10 long 0e SECT 03 0000 [.const] gShaderCode_vi_MsaaFMaskResolve2Frag8Samp_PS 000000000018d010 long 0e SECT 03 0000 [.const] gShRegisters_vi_MsaaFMaskResolve2Frag8Samp_PS 000000000018d020 long 0e SECT 03 0000 [.const] gContextRegisters_vi_MsaaFMaskResolve2Frag8Samp_PS 000000000018d060 long 0e SECT 03 0000 [.const] gUserElementTable_vi_MsaaFMaskResolve2Frag8Samp_PS 000000000018d090 long 0e SECT 03 0000 [.const] gInSemantics_vi_MsaaFMaskResolve2Frag8Samp_PS 000000000018d0a4 long 0e SECT 03 0000 [.const] gPatchInfoOffset_vi_MsaaFMaskResolve2Frag8Samp_PS 000000000018d0b0 long 0e SECT 03 0000 [.const] gPatchInfoCode_vi_MsaaFMaskResolve2Frag8Samp_PS 000000000018d1a0 long 0e SECT 03 0000 [.const] gShaderCode_vi_MsaaFMaskResolve2Frag16Samp_PS 000000000018d7d0 long 0e SECT 03 0000 [.const] gShRegisters_vi_MsaaFMaskResolve2Frag16Samp_PS 000000000018d7e0 long 0e SECT 03 0000 [.const] gContextRegisters_vi_MsaaFMaskResolve2Frag16Samp_PS 000000000018d820 long 0e SECT 03 0000 [.const] gUserElementTable_vi_MsaaFMaskResolve2Frag16Samp_PS 000000000018d850 long 0e SECT 03 0000 [.const] gInSemantics_vi_MsaaFMaskResolve2Frag16Samp_PS 000000000018d864 long 0e SECT 03 0000 [.const] gPatchInfoOffset_vi_MsaaFMaskResolve2Frag16Samp_PS 000000000018d870 long 0e SECT 03 0000 [.const] gPatchInfoCode_vi_MsaaFMaskResolve2Frag16Samp_PS 000000000018d960 long 0e SECT 03 0000 [.const] gShaderCode_vi_MsaaFMaskResolve4Frag8Samp_PS 000000000018dc10 long 0e SECT 03 0000 [.const] gShRegisters_vi_MsaaFMaskResolve4Frag8Samp_PS 000000000018dc20 long 0e SECT 03 0000 [.const] gContextRegisters_vi_MsaaFMaskResolve4Frag8Samp_PS 000000000018dc60 long 0e SECT 03 0000 [.const] gUserElementTable_vi_MsaaFMaskResolve4Frag8Samp_PS 000000000018dc90 long 0e SECT 03 0000 [.const] gInSemantics_vi_MsaaFMaskResolve4Frag8Samp_PS 000000000018dca4 long 0e SECT 03 0000 [.const] gPatchInfoOffset_vi_MsaaFMaskResolve4Frag8Samp_PS 000000000018dcb0 long 0e SECT 03 0000 [.const] gPatchInfoCode_vi_MsaaFMaskResolve4Frag8Samp_PS 000000000018dda0 long 0e SECT 03 0000 [.const] gShaderCode_vi_MsaaFMaskResolve4Frag16Samp_PS 000000000018e340 long 0e SECT 03 0000 [.const] gShRegisters_vi_MsaaFMaskResolve4Frag16Samp_PS 000000000018e350 long 0e SECT 03 0000 [.const] gContextRegisters_vi_MsaaFMaskResolve4Frag16Samp_PS 000000000018e390 long 0e SECT 03 0000 [.const] gUserElementTable_vi_MsaaFMaskResolve4Frag16Samp_PS 000000000018e3c0 long 0e SECT 03 0000 [.const] gInSemantics_vi_MsaaFMaskResolve4Frag16Samp_PS 000000000018e3d4 long 0e SECT 03 0000 [.const] gPatchInfoOffset_vi_MsaaFMaskResolve4Frag16Samp_PS 000000000018e3e0 long 0e SECT 03 0000 [.const] gPatchInfoCode_vi_MsaaFMaskResolve4Frag16Samp_PS 000000000018e4d0 long 0e SECT 03 0000 [.const] gShaderCode_vi_MsaaFMaskResolve8Frag16Samp_PS 000000000018e9a0 long 0e SECT 03 0000 [.const] gShRegisters_vi_MsaaFMaskResolve8Frag16Samp_PS 000000000018e9b0 long 0e SECT 03 0000 [.const] gContextRegisters_vi_MsaaFMaskResolve8Frag16Samp_PS 000000000018e9f0 long 0e SECT 03 0000 [.const] gUserElementTable_vi_MsaaFMaskResolve8Frag16Samp_PS 000000000018ea20 long 0e SECT 03 0000 [.const] gInSemantics_vi_MsaaFMaskResolve8Frag16Samp_PS 000000000018ea34 long 0e SECT 03 0000 [.const] gPatchInfoOffset_vi_MsaaFMaskResolve8Frag16Samp_PS 000000000018ea40 long 0e SECT 03 0000 [.const] gPatchInfoCode_vi_MsaaFMaskResolve8Frag16Samp_PS 000000000018eb30 long 0e SECT 03 0000 [.const] gShaderCode_vi_ColorTransform_PS 000000000018edc0 long 0e SECT 03 0000 [.const] gShRegisters_vi_ColorTransform_PS 000000000018edd0 long 0e SECT 03 0000 [.const] gContextRegisters_vi_ColorTransform_PS 000000000018ee10 long 0e SECT 03 0000 [.const] gUserElementTable_vi_ColorTransform_PS 000000000018ee60 long 0e SECT 03 0000 [.const] gInSemantics_vi_ColorTransform_PS 000000000018ee74 long 0e SECT 03 0000 [.const] gPatchInfoOffset_vi_ColorTransform_PS 000000000018ee80 long 0e SECT 03 0000 [.const] gPatchInfoCode_vi_ColorTransform_PS 000000000018ef70 long 0e SECT 03 0000 [.const] gShaderCode_vi_NonEvenLinearFilter1D_PS 000000000018f0c0 long 0e SECT 03 0000 [.const] gShRegisters_vi_NonEvenLinearFilter1D_PS 000000000018f0d0 long 0e SECT 03 0000 [.const] gContextRegisters_vi_NonEvenLinearFilter1D_PS 000000000018f110 long 0e SECT 03 0000 [.const] gUserElementTable_vi_NonEvenLinearFilter1D_PS 000000000018f160 long 0e SECT 03 0000 [.const] gInSemantics_vi_NonEvenLinearFilter1D_PS 000000000018f174 long 0e SECT 03 0000 [.const] gPatchInfoOffset_vi_NonEvenLinearFilter1D_PS 000000000018f180 long 0e SECT 03 0000 [.const] gPatchInfoCode_vi_NonEvenLinearFilter1D_PS 000000000018f270 long 0e SECT 03 0000 [.const] gShaderCode_vi_NonEvenLinearFilter2D_PS 000000000018f4a0 long 0e SECT 03 0000 [.const] gShRegisters_vi_NonEvenLinearFilter2D_PS 000000000018f4b0 long 0e SECT 03 0000 [.const] gContextRegisters_vi_NonEvenLinearFilter2D_PS 000000000018f4f0 long 0e SECT 03 0000 [.const] gUserElementTable_vi_NonEvenLinearFilter2D_PS 000000000018f540 long 0e SECT 03 0000 [.const] gInSemantics_vi_NonEvenLinearFilter2D_PS 000000000018f554 long 0e SECT 03 0000 [.const] gPatchInfoOffset_vi_NonEvenLinearFilter2D_PS 000000000018f560 long 0e SECT 03 0000 [.const] gPatchInfoCode_vi_NonEvenLinearFilter2D_PS 000000000018f650 long 0e SECT 03 0000 [.const] gShaderCode_vi_NonEvenLinearFilter3D_PS 000000000018f960 long 0e SECT 03 0000 [.const] gShRegisters_vi_NonEvenLinearFilter3D_PS 000000000018f970 long 0e SECT 03 0000 [.const] gContextRegisters_vi_NonEvenLinearFilter3D_PS 000000000018f9b0 long 0e SECT 03 0000 [.const] gUserElementTable_vi_NonEvenLinearFilter3D_PS 000000000018fa00 long 0e SECT 03 0000 [.const] gInSemantics_vi_NonEvenLinearFilter3D_PS 000000000018fa14 long 0e SECT 03 0000 [.const] gPatchInfoOffset_vi_NonEvenLinearFilter3D_PS 000000000018fa20 long 0e SECT 03 0000 [.const] gPatchInfoCode_vi_NonEvenLinearFilter3D_PS 000000000018fb10 long 0e SECT 03 0000 [.const] gShaderCode_vi_MLAACalcSepEdgeLength_PS 000000000018ff40 long 0e SECT 03 0000 [.const] gShRegisters_vi_MLAACalcSepEdgeLength_PS 000000000018ff50 long 0e SECT 03 0000 [.const] gContextRegisters_vi_MLAACalcSepEdgeLength_PS 000000000018ff90 long 0e SECT 03 0000 [.const] gUserElementTable_vi_MLAACalcSepEdgeLength_PS 000000000018ffc0 long 0e SECT 03 0000 [.const] gInSemantics_vi_MLAACalcSepEdgeLength_PS 000000000018ffd4 long 0e SECT 03 0000 [.const] gPatchInfoOffset_vi_MLAACalcSepEdgeLength_PS 000000000018ffe0 long 0e SECT 03 0000 [.const] gPatchInfoCode_vi_MLAACalcSepEdgeLength_PS 00000000001901c0 long 0e SECT 03 0000 [.const] gShaderCode_vi_MLAACalcSepEdgeLengthFast_PS 0000000000190810 long 0e SECT 03 0000 [.const] gShRegisters_vi_MLAACalcSepEdgeLengthFast_PS 0000000000190820 long 0e SECT 03 0000 [.const] gContextRegisters_vi_MLAACalcSepEdgeLengthFast_PS 0000000000190860 long 0e SECT 03 0000 [.const] gUserElementTable_vi_MLAACalcSepEdgeLengthFast_PS 0000000000190890 long 0e SECT 03 0000 [.const] gInSemantics_vi_MLAACalcSepEdgeLengthFast_PS 00000000001908a4 long 0e SECT 03 0000 [.const] gPatchInfoOffset_vi_MLAACalcSepEdgeLengthFast_PS 00000000001908b0 long 0e SECT 03 0000 [.const] gPatchInfoCode_vi_MLAACalcSepEdgeLengthFast_PS 00000000001909a0 long 0e SECT 03 0000 [.const] gShaderCode_vi_MLAACalcSepEdgeLengthInitial_PS 0000000000190bb0 long 0e SECT 03 0000 [.const] gShRegisters_vi_MLAACalcSepEdgeLengthInitial_PS 0000000000190bc0 long 0e SECT 03 0000 [.const] gContextRegisters_vi_MLAACalcSepEdgeLengthInitial_PS 0000000000190c00 long 0e SECT 03 0000 [.const] gUserElementTable_vi_MLAACalcSepEdgeLengthInitial_PS 0000000000190c30 long 0e SECT 03 0000 [.const] gInSemantics_vi_MLAACalcSepEdgeLengthInitial_PS 0000000000190c44 long 0e SECT 03 0000 [.const] gPatchInfoOffset_vi_MLAACalcSepEdgeLengthInitial_PS 0000000000190c50 long 0e SECT 03 0000 [.const] gPatchInfoCode_vi_MLAACalcSepEdgeLengthInitial_PS 0000000000190e30 long 0e SECT 03 0000 [.const] gShaderCode_vi_MLAAFinalBlend_PS 00000000001916b0 long 0e SECT 03 0000 [.const] gShRegisters_vi_MLAAFinalBlend_PS 00000000001916c0 long 0e SECT 03 0000 [.const] gContextRegisters_vi_MLAAFinalBlend_PS 0000000000191700 long 0e SECT 03 0000 [.const] gUserElementTable_vi_MLAAFinalBlend_PS 0000000000191720 long 0e SECT 03 0000 [.const] gInSemantics_vi_MLAAFinalBlend_PS 0000000000191734 long 0e SECT 03 0000 [.const] gPatchInfoOffset_vi_MLAAFinalBlend_PS 0000000000191740 long 0e SECT 03 0000 [.const] gPatchInfoCode_vi_MLAAFinalBlend_PS 0000000000191830 long 0e SECT 03 0000 [.const] gShaderCode_vi_MLAAFinalBlendFast_PS 0000000000192140 long 0e SECT 03 0000 [.const] gShRegisters_vi_MLAAFinalBlendFast_PS 0000000000192150 long 0e SECT 03 0000 [.const] gContextRegisters_vi_MLAAFinalBlendFast_PS 0000000000192190 long 0e SECT 03 0000 [.const] gUserElementTable_vi_MLAAFinalBlendFast_PS 00000000001921c0 long 0e SECT 03 0000 [.const] gInSemantics_vi_MLAAFinalBlendFast_PS 00000000001921d4 long 0e SECT 03 0000 [.const] gPatchInfoOffset_vi_MLAAFinalBlendFast_PS 00000000001921e0 long 0e SECT 03 0000 [.const] gPatchInfoCode_vi_MLAAFinalBlendFast_PS 00000000001922d0 long 0e SECT 03 0000 [.const] gShaderCode_vi_MLAAFindSepEdge_PS 00000000001923e0 long 0e SECT 03 0000 [.const] gShRegisters_vi_MLAAFindSepEdge_PS 00000000001923f0 long 0e SECT 03 0000 [.const] gContextRegisters_vi_MLAAFindSepEdge_PS 0000000000192430 long 0e SECT 03 0000 [.const] gUserElementTable_vi_MLAAFindSepEdge_PS 0000000000192460 long 0e SECT 03 0000 [.const] gInSemantics_vi_MLAAFindSepEdge_PS 0000000000192474 long 0e SECT 03 0000 [.const] gPatchInfoOffset_vi_MLAAFindSepEdge_PS 0000000000192480 long 0e SECT 03 0000 [.const] gPatchInfoCode_vi_MLAAFindSepEdge_PS 0000000000192570 long 0e SECT 03 0000 [.const] gShaderCode_vi_GenZRangeTex_PS 00000000001928e0 long 0e SECT 03 0000 [.const] gShRegisters_vi_GenZRangeTex_PS 00000000001928f0 long 0e SECT 03 0000 [.const] gContextRegisters_vi_GenZRangeTex_PS 0000000000192930 long 0e SECT 03 0000 [.const] gUserElementTable_vi_GenZRangeTex_PS 0000000000192980 long 0e SECT 03 0000 [.const] gInSemantics_vi_GenZRangeTex_PS 0000000000192994 long 0e SECT 03 0000 [.const] gPatchInfoOffset_vi_GenZRangeTex_PS 00000000001929a0 long 0e SECT 03 0000 [.const] gPatchInfoCode_vi_GenZRangeTex_PS 0000000000192a90 long 0e SECT 03 0000 [.const] gShaderCode_vi_GenZRangeMip_PS 0000000000192b40 long 0e SECT 03 0000 [.const] gShRegisters_vi_GenZRangeMip_PS 0000000000192b50 long 0e SECT 03 0000 [.const] gContextRegisters_vi_GenZRangeMip_PS 0000000000192b90 long 0e SECT 03 0000 [.const] gUserElementTable_vi_GenZRangeMip_PS 0000000000192be0 long 0e SECT 03 0000 [.const] gInSemantics_vi_GenZRangeMip_PS 0000000000192bf4 long 0e SECT 03 0000 [.const] gPatchInfoOffset_vi_GenZRangeMip_PS 0000000000192c00 long 0e SECT 03 0000 [.const] gPatchInfoCode_vi_GenZRangeMip_PS 0000000000192cf0 long 0e SECT 03 0000 [.const] gShaderCode_vi_GenZRangeMipOdd_PS 0000000000192f00 long 0e SECT 03 0000 [.const] gShRegisters_vi_GenZRangeMipOdd_PS 0000000000192f10 long 0e SECT 03 0000 [.const] gContextRegisters_vi_GenZRangeMipOdd_PS 0000000000192f50 long 0e SECT 03 0000 [.const] gUserElementTable_vi_GenZRangeMipOdd_PS 0000000000192f80 long 0e SECT 03 0000 [.const] gInSemantics_vi_GenZRangeMipOdd_PS 0000000000192f94 long 0e SECT 03 0000 [.const] gPatchInfoOffset_vi_GenZRangeMipOdd_PS 0000000000192fa0 long 0e SECT 03 0000 [.const] gPatchInfoCode_vi_GenZRangeMipOdd_PS 0000000000193090 long 0e SECT 03 0000 [.const] gShaderCode_vi_Composite_PS 0000000000193890 long 0e SECT 03 0000 [.const] gShRegisters_vi_Composite_PS 00000000001938a0 long 0e SECT 03 0000 [.const] gContextRegisters_vi_Composite_PS 00000000001938e0 long 0e SECT 03 0000 [.const] gUserElementTable_vi_Composite_PS 0000000000193930 long 0e SECT 03 0000 [.const] gInSemantics_vi_Composite_PS 0000000000193958 long 0e SECT 03 0000 [.const] gPatchInfoOffset_vi_Composite_PS 0000000000193960 long 0e SECT 03 0000 [.const] gPatchInfoCode_vi_Composite_PS 0000000000193a50 long 0e SECT 03 0000 [.const] gShaderCode_vi_BufferClear_CS 0000000000193a80 long 0e SECT 03 0000 [.const] gShRegisters_vi_BufferClear_CS 0000000000193aa8 long 0e SECT 03 0000 [.const] gContextRegisters_vi_BufferClear_CS 0000000000193ab0 long 0e SECT 03 0000 [.const] gUserElementTable_vi_BufferClear_CS 0000000000193ae0 long 0e SECT 03 0000 [.const] gShaderCode_vi_BufferCopy_CS 0000000000193b00 long 0e SECT 03 0000 [.const] gShRegisters_vi_BufferCopy_CS 0000000000193b28 long 0e SECT 03 0000 [.const] gContextRegisters_vi_BufferCopy_CS 0000000000193b30 long 0e SECT 03 0000 [.const] gUserElementTable_vi_BufferCopy_CS 0000000000193b60 long 0e SECT 03 0000 [.const] gShaderCode_vi_SurfaceClear_CS 0000000000193bc0 long 0e SECT 03 0000 [.const] gShRegisters_vi_SurfaceClear_CS 0000000000193be8 long 0e SECT 03 0000 [.const] gContextRegisters_vi_SurfaceClear_CS 0000000000193bf0 long 0e SECT 03 0000 [.const] gUserElementTable_vi_SurfaceClear_CS 0000000000193c20 long 0e SECT 03 0000 [.const] gShaderCode_vi_LinGenDstCopy_CS 0000000000193cb0 long 0e SECT 03 0000 [.const] gShRegisters_vi_LinGenDstCopy_CS 0000000000193cd8 long 0e SECT 03 0000 [.const] gContextRegisters_vi_LinGenDstCopy_CS 0000000000193ce0 long 0e SECT 03 0000 [.const] gUserElementTable_vi_LinGenDstCopy_CS 0000000000193d30 long 0e SECT 03 0000 [.const] gShaderCode_vi_LinGenSrcCopy_CS 0000000000193db0 long 0e SECT 03 0000 [.const] gShRegisters_vi_LinGenSrcCopy_CS 0000000000193dd8 long 0e SECT 03 0000 [.const] gContextRegisters_vi_LinGenSrcCopy_CS 0000000000193de0 long 0e SECT 03 0000 [.const] gUserElementTable_vi_LinGenSrcCopy_CS 0000000000193e30 long 0e SECT 03 0000 [.const] gShaderCode_vi_LinGenSrcDstCopy_CS 0000000000193eb0 long 0e SECT 03 0000 [.const] gShRegisters_vi_LinGenSrcDstCopy_CS 0000000000193ed8 long 0e SECT 03 0000 [.const] gContextRegisters_vi_LinGenSrcDstCopy_CS 0000000000193ee0 long 0e SECT 03 0000 [.const] gUserElementTable_vi_LinGenSrcDstCopy_CS 0000000000193f30 long 0e SECT 03 0000 [.const] gShaderCode_vi_HtileCopy_CS 0000000000193f60 long 0e SECT 03 0000 [.const] gShRegisters_vi_HtileCopy_CS 0000000000193f88 long 0e SECT 03 0000 [.const] gContextRegisters_vi_HtileCopy_CS 0000000000193f90 long 0e SECT 03 0000 [.const] gUserElementTable_vi_HtileCopy_CS 0000000000193fc0 long 0e SECT 03 0000 [.const] gShaderCode_vi_MsaaFMaskExpand2Samp_CS 0000000000194060 long 0e SECT 03 0000 [.const] gShRegisters_vi_MsaaFMaskExpand2Samp_CS 0000000000194088 long 0e SECT 03 0000 [.const] gContextRegisters_vi_MsaaFMaskExpand2Samp_CS 0000000000194090 long 0e SECT 03 0000 [.const] gUserElementTable_vi_MsaaFMaskExpand2Samp_CS 00000000001940b0 long 0e SECT 03 0000 [.const] gShaderCode_vi_MsaaFMaskExpand4Samp_CS 00000000001941c0 long 0e SECT 03 0000 [.const] gShRegisters_vi_MsaaFMaskExpand4Samp_CS 00000000001941e8 long 0e SECT 03 0000 [.const] gContextRegisters_vi_MsaaFMaskExpand4Samp_CS 00000000001941f0 long 0e SECT 03 0000 [.const] gUserElementTable_vi_MsaaFMaskExpand4Samp_CS 0000000000194210 long 0e SECT 03 0000 [.const] gShaderCode_vi_MsaaFMaskExpand8Samp_CS 00000000001943e0 long 0e SECT 03 0000 [.const] gShRegisters_vi_MsaaFMaskExpand8Samp_CS 0000000000194408 long 0e SECT 03 0000 [.const] gContextRegisters_vi_MsaaFMaskExpand8Samp_CS 0000000000194410 long 0e SECT 03 0000 [.const] gUserElementTable_vi_MsaaFMaskExpand8Samp_CS 0000000000194430 long 0e SECT 03 0000 [.const] gShaderCode_vi_FastDepthClear_CS 0000000000194490 long 0e SECT 03 0000 [.const] gShRegisters_vi_FastDepthClear_CS 00000000001944b8 long 0e SECT 03 0000 [.const] gContextRegisters_vi_FastDepthClear_CS 00000000001944c0 long 0e SECT 03 0000 [.const] gUserElementTable_vi_FastDepthClear_CS 00000000001944f0 long 0e SECT 03 0000 [.const] gShaderCode_vi_FastDepthExpClear_CS 0000000000194580 long 0e SECT 03 0000 [.const] gShRegisters_vi_FastDepthExpClear_CS 00000000001945a8 long 0e SECT 03 0000 [.const] gContextRegisters_vi_FastDepthExpClear_CS 00000000001945b0 long 0e SECT 03 0000 [.const] gUserElementTable_vi_FastDepthExpClear_CS 00000000001945e0 long 0e SECT 03 0000 [.const] gShaderCode_vi_LinGenDstRepackCopy_CS 00000000001946e0 long 0e SECT 03 0000 [.const] gShRegisters_vi_LinGenDstRepackCopy_CS 0000000000194708 long 0e SECT 03 0000 [.const] gContextRegisters_vi_LinGenDstRepackCopy_CS 0000000000194710 long 0e SECT 03 0000 [.const] gUserElementTable_vi_LinGenDstRepackCopy_CS 0000000000194760 long 0e SECT 03 0000 [.const] gShaderCode_vi_VolumeTexCopy_CS 0000000000194800 long 0e SECT 03 0000 [.const] gShRegisters_vi_VolumeTexCopy_CS 0000000000194828 long 0e SECT 03 0000 [.const] gContextRegisters_vi_VolumeTexCopy_CS 0000000000194830 long 0e SECT 03 0000 [.const] gUserElementTable_vi_VolumeTexCopy_CS 0000000000194880 long 0e SECT 03 0000 [.const] gShaderCode_vi_GenerateHiS_PS 0000000000194930 long 0e SECT 03 0000 [.const] gShRegisters_vi_GenerateHiS_PS 0000000000194940 long 0e SECT 03 0000 [.const] gContextRegisters_vi_GenerateHiS_PS 0000000000194980 long 0e SECT 03 0000 [.const] gUserElementTable_vi_GenerateHiS_PS 00000000001949d0 long 0e SECT 03 0000 [.const] gInSemantics_vi_GenerateHiS_PS 00000000001949e4 long 0e SECT 03 0000 [.const] gPatchInfoOffset_vi_GenerateHiS_PS 00000000001949f0 long 0e SECT 03 0000 [.const] gPatchInfoCode_vi_GenerateHiS_PS 0000000000194ae0 long 0e SECT 03 0000 [.const] gShaderCode_vi_AdvAARes1_PS 0000000000194b60 long 0e SECT 03 0000 [.const] gShRegisters_vi_AdvAARes1_PS 0000000000194b70 long 0e SECT 03 0000 [.const] gContextRegisters_vi_AdvAARes1_PS 0000000000194bb0 long 0e SECT 03 0000 [.const] gUserElementTable_vi_AdvAARes1_PS 0000000000194be0 long 0e SECT 03 0000 [.const] gInSemantics_vi_AdvAARes1_PS 0000000000194bf4 long 0e SECT 03 0000 [.const] gPatchInfoOffset_vi_AdvAARes1_PS 0000000000194c00 long 0e SECT 03 0000 [.const] gPatchInfoCode_vi_AdvAARes1_PS 0000000000194de0 long 0e SECT 03 0000 [.const] gShaderCode_vi_AdvAAEdgeMask4Samp_PS 0000000000194ff0 long 0e SECT 03 0000 [.const] gShRegisters_vi_AdvAAEdgeMask4Samp_PS 0000000000195000 long 0e SECT 03 0000 [.const] gContextRegisters_vi_AdvAAEdgeMask4Samp_PS 0000000000195040 long 0e SECT 03 0000 [.const] gUserElementTable_vi_AdvAAEdgeMask4Samp_PS 0000000000195070 long 0e SECT 03 0000 [.const] gInSemantics_vi_AdvAAEdgeMask4Samp_PS 0000000000195084 long 0e SECT 03 0000 [.const] gPatchInfoOffset_vi_AdvAAEdgeMask4Samp_PS 0000000000195090 long 0e SECT 03 0000 [.const] gPatchInfoCode_vi_AdvAAEdgeMask4Samp_PS 0000000000195360 long 0e SECT 03 0000 [.const] gShaderCode_vi_AdvAAEdgeMask8Samp_PS 00000000001956b0 long 0e SECT 03 0000 [.const] gShRegisters_vi_AdvAAEdgeMask8Samp_PS 00000000001956c0 long 0e SECT 03 0000 [.const] gContextRegisters_vi_AdvAAEdgeMask8Samp_PS 0000000000195700 long 0e SECT 03 0000 [.const] gUserElementTable_vi_AdvAAEdgeMask8Samp_PS 0000000000195730 long 0e SECT 03 0000 [.const] gInSemantics_vi_AdvAAEdgeMask8Samp_PS 0000000000195744 long 0e SECT 03 0000 [.const] gPatchInfoOffset_vi_AdvAAEdgeMask8Samp_PS 0000000000195750 long 0e SECT 03 0000 [.const] gPatchInfoCode_vi_AdvAAEdgeMask8Samp_PS 0000000000195a20 long 0e SECT 03 0000 [.const] gShaderCode_vi_AdvAAFilterMaskFast_PS 0000000000195c70 long 0e SECT 03 0000 [.const] gShRegisters_vi_AdvAAFilterMaskFast_PS 0000000000195c80 long 0e SECT 03 0000 [.const] gContextRegisters_vi_AdvAAFilterMaskFast_PS 0000000000195cc0 long 0e SECT 03 0000 [.const] gUserElementTable_vi_AdvAAFilterMaskFast_PS 0000000000195ce0 long 0e SECT 03 0000 [.const] gInSemantics_vi_AdvAAFilterMaskFast_PS 0000000000195cf4 long 0e SECT 03 0000 [.const] gPatchInfoOffset_vi_AdvAAFilterMaskFast_PS 0000000000195d00 long 0e SECT 03 0000 [.const] gPatchInfoCode_vi_AdvAAFilterMaskFast_PS 0000000000195df0 long 0e SECT 03 0000 [.const] gShaderCode_vi_AdvAAGrad4SampNoReZ_PS 00000000001976f0 long 0e SECT 03 0000 [.const] gShRegisters_vi_AdvAAGrad4SampNoReZ_PS 0000000000197700 long 0e SECT 03 0000 [.const] gContextRegisters_vi_AdvAAGrad4SampNoReZ_PS 0000000000197740 long 0e SECT 03 0000 [.const] gUserElementTable_vi_AdvAAGrad4SampNoReZ_PS 0000000000197770 long 0e SECT 03 0000 [.const] gInSemantics_vi_AdvAAGrad4SampNoReZ_PS 0000000000197784 long 0e SECT 03 0000 [.const] gPatchInfoOffset_vi_AdvAAGrad4SampNoReZ_PS 0000000000197790 long 0e SECT 03 0000 [.const] gPatchInfoCode_vi_AdvAAGrad4SampNoReZ_PS 0000000000197880 long 0e SECT 03 0000 [.const] gShaderCode_vi_AdvAAGrad8SampNoReZ_PS 000000000019af50 long 0e SECT 03 0000 [.const] gShRegisters_vi_AdvAAGrad8SampNoReZ_PS 000000000019af60 long 0e SECT 03 0000 [.const] gContextRegisters_vi_AdvAAGrad8SampNoReZ_PS 000000000019afa0 long 0e SECT 03 0000 [.const] gUserElementTable_vi_AdvAAGrad8SampNoReZ_PS 000000000019afd0 long 0e SECT 03 0000 [.const] gInSemantics_vi_AdvAAGrad8SampNoReZ_PS 000000000019afe4 long 0e SECT 03 0000 [.const] gPatchInfoOffset_vi_AdvAAGrad8SampNoReZ_PS 000000000019aff0 long 0e SECT 03 0000 [.const] gPatchInfoCode_vi_AdvAAGrad8SampNoReZ_PS 000000000019b0e0 long 0e SECT 03 0000 [.const] gShaderCode_vi_AdvAAEdG4SampNoReZ_PS 000000000019d160 long 0e SECT 03 0000 [.const] gShRegisters_vi_AdvAAEdG4SampNoReZ_PS 000000000019d170 long 0e SECT 03 0000 [.const] gContextRegisters_vi_AdvAAEdG4SampNoReZ_PS 000000000019d1b0 long 0e SECT 03 0000 [.const] gUserElementTable_vi_AdvAAEdG4SampNoReZ_PS 000000000019d1e0 long 0e SECT 03 0000 [.const] gInSemantics_vi_AdvAAEdG4SampNoReZ_PS 000000000019d1f4 long 0e SECT 03 0000 [.const] gPatchInfoOffset_vi_AdvAAEdG4SampNoReZ_PS 000000000019d200 long 0e SECT 03 0000 [.const] gPatchInfoCode_vi_AdvAAEdG4SampNoReZ_PS 000000000019d2f0 long 0e SECT 03 0000 [.const] gShaderCode_vi_AdvAAEdG8SampNoReZ_PS 00000000001a12e0 long 0e SECT 03 0000 [.const] gShRegisters_vi_AdvAAEdG8SampNoReZ_PS 00000000001a12f0 long 0e SECT 03 0000 [.const] gContextRegisters_vi_AdvAAEdG8SampNoReZ_PS 00000000001a1330 long 0e SECT 03 0000 [.const] gUserElementTable_vi_AdvAAEdG8SampNoReZ_PS 00000000001a1360 long 0e SECT 03 0000 [.const] gInSemantics_vi_AdvAAEdG8SampNoReZ_PS 00000000001a1374 long 0e SECT 03 0000 [.const] gPatchInfoOffset_vi_AdvAAEdG8SampNoReZ_PS 00000000001a1380 long 0e SECT 03 0000 [.const] gPatchInfoCode_vi_AdvAAEdG8SampNoReZ_PS 00000000001a1470 long 0e SECT 03 0000 [.const] gShaderCode_vi_AdvAAFMaskEdgeMask4Samp_PS 00000000001a1720 long 0e SECT 03 0000 [.const] gShRegisters_vi_AdvAAFMaskEdgeMask4Samp_PS 00000000001a1730 long 0e SECT 03 0000 [.const] gContextRegisters_vi_AdvAAFMaskEdgeMask4Samp_PS 00000000001a1770 long 0e SECT 03 0000 [.const] gUserElementTable_vi_AdvAAFMaskEdgeMask4Samp_PS 00000000001a17a0 long 0e SECT 03 0000 [.const] gInSemantics_vi_AdvAAFMaskEdgeMask4Samp_PS 00000000001a17b4 long 0e SECT 03 0000 [.const] gPatchInfoOffset_vi_AdvAAFMaskEdgeMask4Samp_PS 00000000001a17c0 long 0e SECT 03 0000 [.const] gPatchInfoCode_vi_AdvAAFMaskEdgeMask4Samp_PS 00000000001a1a90 long 0e SECT 03 0000 [.const] gShaderCode_vi_AdvAAFMaskEdgeMask8Samp_PS 00000000001a1f70 long 0e SECT 03 0000 [.const] gShRegisters_vi_AdvAAFMaskEdgeMask8Samp_PS 00000000001a1f80 long 0e SECT 03 0000 [.const] gContextRegisters_vi_AdvAAFMaskEdgeMask8Samp_PS 00000000001a1fc0 long 0e SECT 03 0000 [.const] gUserElementTable_vi_AdvAAFMaskEdgeMask8Samp_PS 00000000001a1ff0 long 0e SECT 03 0000 [.const] gInSemantics_vi_AdvAAFMaskEdgeMask8Samp_PS 00000000001a2004 long 0e SECT 03 0000 [.const] gPatchInfoOffset_vi_AdvAAFMaskEdgeMask8Samp_PS 00000000001a2010 long 0e SECT 03 0000 [.const] gPatchInfoCode_vi_AdvAAFMaskEdgeMask8Samp_PS 00000000001a22e0 long 0e SECT 03 0000 [.const] gShaderCode_vi_AdvAAFMaskEdG4SampNoReZ_PS 00000000001a4510 long 0e SECT 03 0000 [.const] gShRegisters_vi_AdvAAFMaskEdG4SampNoReZ_PS 00000000001a4520 long 0e SECT 03 0000 [.const] gContextRegisters_vi_AdvAAFMaskEdG4SampNoReZ_PS 00000000001a4560 long 0e SECT 03 0000 [.const] gUserElementTable_vi_AdvAAFMaskEdG4SampNoReZ_PS 00000000001a4590 long 0e SECT 03 0000 [.const] gInSemantics_vi_AdvAAFMaskEdG4SampNoReZ_PS 00000000001a45a4 long 0e SECT 03 0000 [.const] gPatchInfoOffset_vi_AdvAAFMaskEdG4SampNoReZ_PS 00000000001a45b0 long 0e SECT 03 0000 [.const] gPatchInfoCode_vi_AdvAAFMaskEdG4SampNoReZ_PS 00000000001a46a0 long 0e SECT 03 0000 [.const] gShaderCode_vi_AdvAAFMaskEdG8SampNoReZ_PS 00000000001a8910 long 0e SECT 03 0000 [.const] gShRegisters_vi_AdvAAFMaskEdG8SampNoReZ_PS 00000000001a8920 long 0e SECT 03 0000 [.const] gContextRegisters_vi_AdvAAFMaskEdG8SampNoReZ_PS 00000000001a8960 long 0e SECT 03 0000 [.const] gUserElementTable_vi_AdvAAFMaskEdG8SampNoReZ_PS 00000000001a8990 long 0e SECT 03 0000 [.const] gInSemantics_vi_AdvAAFMaskEdG8SampNoReZ_PS 00000000001a89a4 long 0e SECT 03 0000 [.const] gPatchInfoOffset_vi_AdvAAFMaskEdG8SampNoReZ_PS 00000000001a89b0 long 0e SECT 03 0000 [.const] gPatchInfoCode_vi_AdvAAFMaskEdG8SampNoReZ_PS 00000000001a90f0 long 0e SECT 03 0000 [.const] R800AddrLib::HwlSetupTileInfo(_AddrTileMode, _ADDR_SURFACE_FLAGS, unsigned int, unsigned int, unsigned int, unsigned int, _ADDR_TILEINFO*, _ADDR_TILEINFO*, _AddrTileType, _ADDR_COMPUTE_SURFACE_INFO_OUTPUT*) const::tileInfoDef 00000000001a9110 long 0e SECT 03 0000 [.const] R800AddrLib::HwlSetupTileInfo(_AddrTileMode, _ADDR_SURFACE_FLAGS, unsigned int, unsigned int, unsigned int, unsigned int, _ADDR_TILEINFO*, _ADDR_TILEINFO*, _AddrTileType, _ADDR_COMPUTE_SURFACE_INFO_OUTPUT*) const::sCompressZTileSplit 00000000001a9190 long 0e SECT 03 0000 [.const] EgBasedAddrLib::HwlComputeBaseSwizzle(_ADDR_COMPUTE_BASE_SWIZZLE_INPUT const*, _ADDR_COMPUTE_BASE_SWIZZLE_OUTPUT*) const::bankRotationArray 00000000001a9230 long 0e SECT 03 0000 [.const] _BONAIRE_CRTC_OFFSETS 00000000001a9250 long 0e SECT 03 0000 [.const] _BONAIRE_CRTC_STATUS_FRAME_COUNT 00000000001a96e0 long 0e SECT 03 0000 [.const] _ulTrinityEyefinityNotsupportedDidTbl 00000000001a9718 long 0e SECT 03 0000 [.const] _EmbeddedBoardGroup 00000000001acd90 long 0e SECT 03 0000 [.const] _LB_TYPE 00000000001ace40 long 0e SECT 03 0000 [.const] _P2P_BAR_2 00000000001acea0 long 0e SECT 03 0000 [.const] _P2P_BAR_4 00000000001ad000 long 0e SECT 03 0000 [.const] _WCB_NUM 00000000001ad060 long 0e SECT 03 0000 [.const] _MAIL_BOX_FOR_CLIENT 00000000001ad0d0 long 0e SECT 03 0000 [.const] _CAIL_Encoded_PCIELanes 00000000001ad0f0 long 0e SECT 03 0000 [.const] _ulEngineIndexTbl 00000000001ad150 long 0e SECT 03 0000 [.const] _ulNoOfChannel 00000000001ad180 long 0e SECT 03 0000 [.const] _PowerControlOppositeActionTbl 00000000001ad1b0 long 0e SECT 03 0000 [.const] _CARRIZO_DCP_OFFSETS 00000000001ad210 long 0e SECT 03 0000 [.const] _MC_XPB_CLG_CFGn_CAYMAN 00000000001ad2d0 long 0e SECT 03 0000 [.const] _DCIO_OFFSETS 00000000001ad2f0 long 0e SECT 03 0000 [.const] _CRTC_STATUS_FRAME_COUNT 00000000001ad310 long 0e SECT 03 0000 [.const] _CaymanBankMap 00000000001ad320 long 0e SECT 03 0000 [.const] _DCP_OFFSETS 00000000001ad360 long 0e SECT 03 0000 [.const] _CypressSpiPerfCounter 00000000001ad3a0 long 0e SECT 03 0000 [.const] _MC_XPB_CLG_CFGn_CYPRESS 00000000001ad460 long 0e SECT 03 0000 [.const] _DCP_OFFSETS 00000000001ad480 long 0e SECT 03 0000 [.const] _CypressBankMap 00000000001ad490 long 0e SECT 03 0000 [.const] _SECT_CTRLCONST_def_1 00000000001ad498 long 0e SECT 03 0000 [.const] _SECT_CLEAR_def_1 00000000001ad4b0 long 0e SECT 03 0000 [.const] _SECT_CONTEXT_def_1 00000000001adc50 long 0e SECT 03 0000 [.const] _SECT_CONTEXT_def_2 00000000001adc70 long 0e SECT 03 0000 [.const] _SECT_CONTEXT_def_3 00000000001add50 long 0e SECT 03 0000 [.const] _SECT_CONTEXT_def_4 00000000001adee0 long 0e SECT 03 0000 [.const] _SECT_CONTEXT_def_5 00000000001adf00 long 0e SECT 03 0000 [.const] _SECT_CONTEXT_def_6 00000000001adfe0 long 0e SECT 03 0000 [.const] _SECT_CONTEXT_def_7 00000000001ae490 long 0e SECT 03 0000 [.const] _SECT_CTRLCONST_def_1 00000000001ae498 long 0e SECT 03 0000 [.const] _SECT_CLEAR_def_1 00000000001ae4b0 long 0e SECT 03 0000 [.const] _SECT_CONTEXT_def_1 00000000001aec50 long 0e SECT 03 0000 [.const] _SECT_CONTEXT_def_2 00000000001aec70 long 0e SECT 03 0000 [.const] _SECT_CONTEXT_def_3 00000000001aed50 long 0e SECT 03 0000 [.const] _SECT_CONTEXT_def_4 00000000001aeee0 long 0e SECT 03 0000 [.const] _SECT_CONTEXT_def_5 00000000001aef00 long 0e SECT 03 0000 [.const] _SECT_CONTEXT_def_6 00000000001aefe0 long 0e SECT 03 0000 [.const] _SECT_CONTEXT_def_7 00000000001af4c0 long 0e SECT 03 0000 [.const] _DCP_OFFSETS 00000000001af4e0 long 0e SECT 03 0000 [.const] _CRTC_STATUS_FRAME_COUNT 00000000001af500 long 0e SECT 03 0000 [.const] _TONGA_RLC_SRM_INDEX_CNTL_DATA_OFFSETS 00000000001af520 long 0e SECT 03 0000 [.const] _TONGA_DCP_OFFSETS 00000000001af560 long 0e SECT 03 0000 [.const] _TONGA_CRTC_OFFSETS 00000000001af580 long 0e SECT 03 0000 [.const] _TONGA_CRTC_STATUS_FRAME_COUNT 00000000001af5c0 long 0e SECT 03 0000 [.const] _si_SECT_CONTEXT_def_1 00000000001af910 long 0e SECT 03 0000 [.const] _si_SECT_CONTEXT_def_2 00000000001afd50 long 0e SECT 03 0000 [.const] _si_SECT_CONTEXT_def_3 00000000001afd70 long 0e SECT 03 0000 [.const] _si_SECT_CONTEXT_def_4 00000000001affe4 long 0e SECT 03 0000 [.const] _si_SECT_CONTEXT_def_5 00000000001affe8 long 0e SECT 03 0000 [.const] _si_SECT_CONTEXT_def_6 00000000001afff0 long 0e SECT 03 0000 [.const] _si_SECT_CONTEXT_def_7 00000000001b03a0 long 0e SECT 03 0000 [.const] _ci_SECT_CONTEXT_def_1 00000000001b06f0 long 0e SECT 03 0000 [.const] _ci_SECT_CONTEXT_def_2 00000000001b0b40 long 0e SECT 03 0000 [.const] _ci_SECT_CONTEXT_def_3 00000000001b0b60 long 0e SECT 03 0000 [.const] _ci_SECT_CONTEXT_def_4 00000000001b0dd4 long 0e SECT 03 0000 [.const] _ci_SECT_CONTEXT_def_5 00000000001b0ddc long 0e SECT 03 0000 [.const] _ci_SECT_CONTEXT_def_6 00000000001b0de0 long 0e SECT 03 0000 [.const] _ci_SECT_CONTEXT_def_7 00000000001b1190 long 0e SECT 03 0000 [.const] _vi_SECT_CONTEXT_def_1 00000000001b14e0 long 0e SECT 03 0000 [.const] _vi_SECT_CONTEXT_def_2 00000000001b1930 long 0e SECT 03 0000 [.const] _vi_SECT_CONTEXT_def_3 00000000001b1950 long 0e SECT 03 0000 [.const] _vi_SECT_CONTEXT_def_4 00000000001b1bc4 long 0e SECT 03 0000 [.const] _vi_SECT_CONTEXT_def_5 00000000001b1bcc long 0e SECT 03 0000 [.const] _vi_SECT_CONTEXT_def_6 00000000001b1bd0 long 0e SECT 03 0000 [.const] _vi_SECT_CONTEXT_def_7 00000000001b1f80 long 0e SECT 03 0000 [.const] va_data_6 00000000001e7b90 long 0e SECT 03 0000 [.const] stSPUKernel_SI 0000000000227bd0 long 0e SECT 03 0000 [.const] fair_play_si_app 000000000022a220 long 0e SECT 03 0000 [.const] hdcp_si_app 000000000022c770 long 0e SECT 03 0000 [.const] aucSI_Firmware 0000000000239760 long 0e SECT 03 0000 [.const] va_data_cik 00000000002724c0 long 0e SECT 03 0000 [.const] stSPUKernel_CI 00000000002b2500 long 0e SECT 03 0000 [.const] kapp_ci_app 00000000002ba210 long 0e SECT 03 0000 [.const] fair_play_ci_app 00000000002bd840 long 0e SECT 03 0000 [.const] hdcp_ci_app 00000000002c0e70 long 0e SECT 03 0000 [.const] aucCI_Firmware 00000000002d65b0 long 0e SECT 03 0000 [.const] va_data_vi 0000000000321308 long 0e SECT 03 0000 [.const] stSPUKernel_VI 0000000000361340 long 0e SECT 03 0000 [.const] aucVI_Firmware 0000000000387fd0 long 0e SECT 04 0000 [__TEXT.__ustring] _bmask 0000000000389980 long 0e SECT 08 0000 [.const_data] gATYModelNames 0000000000389d00 long 0e SECT 08 0000 [.const_data] vtable for IOAccelCommandDescriptor 000000000038a7b0 long 0e SECT 08 0000 [.const_data] AMDRadeonX4000_AMDAccelDevice::deviceStart()::methodDescs 000000000038b200 long 0e SECT 08 0000 [.const_data] vtable for IOAccelCommandDescriptor 000000000038c700 long 0e SECT 08 0000 [.const_data] AMDRadeonX4000_AMDAccelSharedUserClient::getTargetAndMethodForIndex(IOService**, unsigned int)::methodDescs 000000000038f250 long 0e SECT 08 0000 [.const_data] AMDRadeonX4000_AMDAccelVideoContext::contextStart()::methodDescs 000000000039a060 long 0e SECT 08 0000 [.const_data] AMDSIGLContext::getTargetAndMethodForIndex(IOService**, unsigned int)::methodDescs 000000000039a0c0 long 0e SECT 08 0000 [.const_data] vtable for IOAccelCommandDescriptor 000000000039ad60 long 0e SECT 08 0000 [.const_data] AMDSICLContext::contextStart()::methodDescs 000000000039e190 long 0e SECT 08 0000 [.const_data] AMDCICLContext::contextStart()::methodDescs 00000000003bddc0 long 0e SECT 08 0000 [.const_data] vtable for BltDevice 00000000003be450 long 0e SECT 08 0000 [.const_data] vtable for SiBltComputeShader 00000000003be4a0 long 0e SECT 08 0000 [.const_data] vtable for SiBltVertexShader 00000000003bee90 long 0e SECT 08 0000 [.const_data] _CailControlInfo1 00000000003bf240 long 0e SECT 08 0000 [.const_data] _CailDisableFlag1 00000000003bf3a0 long 0e SECT 08 0000 [.const_data] _CailDisableFlag2 00000000003bf410 long 0e SECT 08 0000 [.const_data] _CailEnableFlag1 00000000003bf510 long 0e SECT 08 0000 [.const_data] _CailDisableClockGatingFlags 00000000003bf6b0 long 0e SECT 08 0000 [.const_data] _CailDisablePowerGatingFlags 00000000003bf7c0 long 0e SECT 08 0000 [.const_data] _CailCapOverride 00000000003bfb40 long 0e SECT 08 0000 [.const_data] _AcfMemberTbl 00000000003bfd50 long 0e SECT 08 0000 [.const_data] _CAIL_IRI_Services 00000000003bfeb0 long 0e SECT 08 0000 [.const_data] _SECT_CONTEXT_defs 00000000003bff30 long 0e SECT 08 0000 [.const_data] _SECT_CLEAR_defs 00000000003bff50 long 0e SECT 08 0000 [.const_data] _SECT_CTRLCONST_defs 00000000003bff70 long 0e SECT 08 0000 [.const_data] _SECT_CONTEXT_defs 00000000003bfff0 long 0e SECT 08 0000 [.const_data] _SECT_CLEAR_defs 00000000003c0010 long 0e SECT 08 0000 [.const_data] _SECT_CTRLCONST_defs 00000000003c0030 long 0e SECT 08 0000 [.const_data] _si_SECT_CONTEXT_defs 00000000003c00b0 long 0e SECT 08 0000 [.const_data] _si_cs_data 00000000003c00d0 long 0e SECT 08 0000 [.const_data] _ci_SECT_CONTEXT_defs 00000000003c0150 long 0e SECT 08 0000 [.const_data] _ci_cs_data 00000000003c0170 long 0e SECT 08 0000 [.const_data] _vi_SECT_CONTEXT_defs 00000000003c01f0 long 0e SECT 08 0000 [.const_data] _vi_cs_data 00000000003c41d8 long 0e SECT 08 0000 [.const_data] stVCEFW_SouthernIsland 00000000003c5f20 long 0e SECT 09 0000 [.data] AMDHWChannelStatsNames 00000000003c7510 long 0e SECT 09 0000 [.data] gShaderCode_si_TexAlphaOne_PS 00000000003c7560 long 0e SECT 09 0000 [.data] gShRegisters_si_TexAlphaOne_PS 00000000003c7570 long 0e SECT 09 0000 [.data] gContextRegisters_si_TexAlphaOne_PS 00000000003c75b0 long 0e SECT 09 0000 [.data] gUserElementTable_si_TexAlphaOne_PS 00000000003c75e0 long 0e SECT 09 0000 [.data] gInSemantics_si_TexAlphaOne_PS 00000000003c75f4 long 0e SECT 09 0000 [.data] gPatchInfoOffset_si_TexAlphaOne_PS 00000000003c7600 long 0e SECT 09 0000 [.data] gPatchInfoCode_si_TexAlphaOne_PS 00000000003c76a0 long 0e SECT 09 0000 [.data] gShaderCode_si_TexAlphaOneInt_PS 00000000003c76f0 long 0e SECT 09 0000 [.data] gShRegisters_si_TexAlphaOneInt_PS 00000000003c7700 long 0e SECT 09 0000 [.data] gContextRegisters_si_TexAlphaOneInt_PS 00000000003c7740 long 0e SECT 09 0000 [.data] gUserElementTable_si_TexAlphaOneInt_PS 00000000003c7770 long 0e SECT 09 0000 [.data] gInSemantics_si_TexAlphaOneInt_PS 00000000003c7784 long 0e SECT 09 0000 [.data] gPatchInfoOffset_si_TexAlphaOneInt_PS 00000000003c7790 long 0e SECT 09 0000 [.data] gPatchInfoCode_si_TexAlphaOneInt_PS 00000000003c7830 long 0e SECT 09 0000 [.data] gShaderCode_vi_TexAlphaOne_PS 00000000003c7880 long 0e SECT 09 0000 [.data] _aRLC_Ucode 00000000003c84a0 long 0e SECT 09 0000 [.data] _aBARTS_GoldenRegisterSettings_A11 00000000003c86f0 long 0e SECT 09 0000 [.data] _BARTS_HwConstants 00000000003c8760 long 0e SECT 09 0000 [.data] _aRLC_Ucode 00000000003ca790 long 0e SECT 09 0000 [.data] _aF32_SDMA0_Ucode 00000000003cb820 long 0e SECT 09 0000 [.data] _aF32_SDMA1_Ucode 00000000003cc8b0 long 0e SECT 09 0000 [.data] _aF32_PFP_Ucode 00000000003cea60 long 0e SECT 09 0000 [.data] _aF32_CE_Ucode 00000000003d0c10 long 0e SECT 09 0000 [.data] _aF32_ME_Ucode 00000000003d2dc0 long 0e SECT 09 0000 [.data] _aF32_MEC_Ucode 00000000003d7070 long 0e SECT 09 0000 [.data] _BonaireAsicStateCheckRegList 00000000003d7630 long 0e SECT 09 0000 [.data] _aBONAIRE_GoldenRegisterSettings_A0 00000000003d8160 long 0e SECT 09 0000 [.data] _aBONAIRE_GoldenRegisterSettings_A1 00000000003d8cc0 long 0e SECT 09 0000 [.data] _Bonaire_UcodeInfo 00000000003d8d00 long 0e SECT 09 0000 [.data] _sRlcScratchRamInfo 00000000003d8d20 long 0e SECT 09 0000 [.data] _Bonaire_HwConstants 00000000003d8dd0 long 0e SECT 09 0000 [.data] _sBonaireGbMacroTileModeRecords 00000000003d8e10 long 0e SECT 09 0000 [.data] _sBonaireGbTileModeRecords 00000000003d8f10 long 0e SECT 09 0000 [.data] _BonaireAsicSetupTable 00000000003d9040 long 0e SECT 09 0000 [.data] _aRLC_Ucode 00000000003d9c60 long 0e SECT 09 0000 [.data] _aCAICOS_GoldenRegisterSettings_A11 00000000003d9ec8 long 0e SECT 09 0000 [.data] _CAICOS_HwConstants 00000000003e2370 long 0e SECT 09 0000 [.data] _SumoId1 00000000003e2380 long 0e SECT 09 0000 [.data] _SumoBtcGroup1 00000000003e23a0 long 0e SECT 09 0000 [.data] _SumoId2 00000000003e23ac long 0e SECT 09 0000 [.data] _SumoBtcGroup2 00000000003e23b8 long 0e SECT 09 0000 [.data] _SumoId3 00000000003e23d0 long 0e SECT 09 0000 [.data] _SumoEgBtcGroup1 00000000003e2408 long 0e SECT 09 0000 [.data] _SumoId4 00000000003e2420 long 0e SECT 09 0000 [.data] _SumoEgBtcGroup2 00000000003e2440 long 0e SECT 09 0000 [.data] _TrinityId1 00000000003e2490 long 0e SECT 09 0000 [.data] _TrinityBtcGroup1 00000000003e24d0 long 0e SECT 09 0000 [.data] _TrinityId2 00000000003e2510 long 0e SECT 09 0000 [.data] _TrinityBtcGroup2 00000000003e2574 long 0e SECT 09 0000 [.data] _TrinityId3 00000000003e2580 long 0e SECT 09 0000 [.data] _TrinityBtcGroup3 00000000003e2590 long 0e SECT 09 0000 [.data] _TrinityId4 00000000003e25bc long 0e SECT 09 0000 [.data] _TrinityCaicosGroup 00000000003e25d0 long 0e SECT 09 0000 [.data] _TrinitySolarSystemGroup 00000000003e2630 long 0e SECT 09 0000 [.data] _TrinitySIGroup 00000000003e2650 long 0e SECT 09 0000 [.data] _KaveriMobileId1 00000000003e2660 long 0e SECT 09 0000 [.data] _KaveriMobileGroup1 00000000003e2680 long 0e SECT 09 0000 [.data] _KaveriMobileId2 00000000003e2690 long 0e SECT 09 0000 [.data] _KaveriMobileGroup2 00000000003e26b0 long 0e SECT 09 0000 [.data] _KaveriMobileId3 00000000003e26c0 long 0e SECT 09 0000 [.data] _KaveriMobileGroup3 00000000003e26d8 long 0e SECT 09 0000 [.data] _KaveriMobileId4 00000000003e26e0 long 0e SECT 09 0000 [.data] _KaveriMobileGroup4 00000000003e26f0 long 0e SECT 09 0000 [.data] _KaveriAIOId1 00000000003e2700 long 0e SECT 09 0000 [.data] _KaveriAIOGroup1 00000000003e2718 long 0e SECT 09 0000 [.data] _KaveriAIOId2 00000000003e2730 long 0e SECT 09 0000 [.data] _KaveriAIOGroup2 00000000003e2750 long 0e SECT 09 0000 [.data] _KaveriEmbeddedId 00000000003e2758 long 0e SECT 09 0000 [.data] _KaveriEmbeddedGroup 00000000003e2760 long 0e SECT 09 0000 [.data] _KaveriDesktopId 00000000003e2770 long 0e SECT 09 0000 [.data] _KaveriDesktopGroup 00000000003e2790 long 0e SECT 09 0000 [.data] _easfBinaryTable 00000000003e2ed0 long 0e SECT 09 0000 [.data] _CapeVerdeRLCSaveRestoreRegisterList 00000000003e3290 long 0e SECT 09 0000 [.data] _CAPEVERDE_GoldenRegisterSettingsA11 00000000003e3fc0 long 0e SECT 09 0000 [.data] _CAPEVERDE_GoldenRegisterSettingsA12 00000000003e4cf0 long 0e SECT 09 0000 [.data] _CapeVerde_HwConstants 00000000003e4d70 long 0e SECT 09 0000 [.data] _aRLC_Ucode 00000000003e6d70 long 0e SECT 09 0000 [.data] _CapeVerde_RLC 00000000003e6d90 long 0e SECT 09 0000 [.data] _sCapeVerdeGbTileModeRecords 00000000003e6e90 long 0e SECT 09 0000 [.data] _CarrizoAsicSetupTable 00000000003e6fa0 long 0e SECT 09 0000 [.data] _aCarrizo_GoldenRegisterSettings 00000000003e7148 long 0e SECT 09 0000 [.data] _Carrizo_UcodeInfo 00000000003e71a0 long 0e SECT 09 0000 [.data] _Carrizo_RLC_UCODE 00000000003e71c8 long 0e SECT 09 0000 [.data] _Carrizo_SDMA0_UCODE 00000000003e71f0 long 0e SECT 09 0000 [.data] _Carrizo_SDMA1_UCODE 00000000003e7218 long 0e SECT 09 0000 [.data] _Carrizo_CE_UCODE 00000000003e7240 long 0e SECT 09 0000 [.data] _Carrizo_PFP_UCODE 00000000003e7268 long 0e SECT 09 0000 [.data] _Carrizo_ME_UCODE 00000000003e7290 long 0e SECT 09 0000 [.data] _Carrizo_MEC1_UCODE 00000000003e72b8 long 0e SECT 09 0000 [.data] _Carrizo_MEC2_UCODE 00000000003e72e0 long 0e SECT 09 0000 [.data] _aF32_MEC_Ucode 0000000000427460 long 0e SECT 09 0000 [.data] _aF32_ME_Ucode 000000000042b5e0 long 0e SECT 09 0000 [.data] _aF32_PFP_Ucode 000000000042f760 long 0e SECT 09 0000 [.data] _aF32_CE_Ucode 00000000004318e0 long 0e SECT 09 0000 [.data] _aF32_SDMA1_Ucode 0000000000434160 long 0e SECT 09 0000 [.data] _aF32_SDMA0_Ucode 00000000004369e0 long 0e SECT 09 0000 [.data] _aRLC_Ucode 00000000004399e0 long 0e SECT 09 0000 [.data] _sRlcScratchRamInfo 0000000000439a48 long 0e SECT 09 0000 [.data] _CzCsTaskList 0000000000439a58 long 0e SECT 09 0000 [.data] _Carrizo_HwConstants_8812 0000000000439b10 long 0e SECT 09 0000 [.data] _CzCsTaskArray 0000000000439b60 long 0e SECT 09 0000 [.data] _SysClockGatingTaskTable 0000000000439d30 long 0e SECT 09 0000 [.data] _SdmaRingRegSaveRestore 0000000000439e10 long 0e SECT 09 0000 [.data] _ReinitGnbNonGfxReg 0000000000439f10 long 0e SECT 09 0000 [.data] _HaltSDMA 0000000000439f50 long 0e SECT 09 0000 [.data] _StartSDMA 0000000000439fa0 long 0e SECT 09 0000 [.data] _register_restore 000000000043b5f0 long 0e SECT 09 0000 [.data] _register_list_format 000000000043b690 long 0e SECT 09 0000 [.data] _register_restore_separate 000000000043b700 long 0e SECT 09 0000 [.data] _register_list_format_separate 000000000043b730 long 0e SECT 09 0000 [.data] _sCarrizoGbMacroTileModeRecords 000000000043b7b0 long 0e SECT 09 0000 [.data] _sCarrizoGbTileModeRecords 000000000043b8c0 long 0e SECT 09 0000 [.data] _CaymanAsicSetupTable 000000000043b980 long 0e SECT 09 0000 [.data] _MEMORY_CLIENT_GROUP_CAYMAN 000000000043ba40 long 0e SECT 09 0000 [.data] _MAIL_BOX_CAYMAN 000000000043bb00 long 0e SECT 09 0000 [.data] _WCB_NUM_CAYMAN 000000000043bbc0 long 0e SECT 09 0000 [.data] _P2P_BAR_2_CAYMAN 000000000043bc80 long 0e SECT 09 0000 [.data] _P2P_BAR_4_CAYMAN 000000000043bf70 long 0e SECT 09 0000 [.data] _CF_MEM_CLT_GUP_RANGE_CAYMAN 000000000043c090 long 0e SECT 09 0000 [.data] _aRLC_Ucode 000000000043d0b0 long 0e SECT 09 0000 [.data] _CaymanAsicStateCheckRegList 000000000043d5b0 long 0e SECT 09 0000 [.data] _aCAYMAN_GoldenRegisterSettings_A11 000000000043d838 long 0e SECT 09 0000 [.data] _CAYMAN_HwConstants 000000000043d8a0 long 0e SECT 09 0000 [.data] _aCEDAR_GoldenRegisterSettings 000000000043dd98 long 0e SECT 09 0000 [.data] _CEDAR_HwConstants 000000000043de20 long 0e SECT 09 0000 [.data] _CypressAsicSetupTable 000000000043deb0 long 0e SECT 09 0000 [.data] _MEMORY_CLIENT_GROUP_CYPRESS 000000000043df70 long 0e SECT 09 0000 [.data] _MAIL_BOX_CYPRESS 000000000043e030 long 0e SECT 09 0000 [.data] _WCB_NUM_CYPRESS 000000000043e0f0 long 0e SECT 09 0000 [.data] _P2P_BAR_2_CYPRESS 000000000043e1b0 long 0e SECT 09 0000 [.data] _P2P_BAR_4_CYPRESS 000000000043e4a0 long 0e SECT 09 0000 [.data] _CF_MEM_CLT_GUP_RANGE_CYPRESS 000000000043e5c0 long 0e SECT 09 0000 [.data] _aRLC_Ucode 000000000043f1e0 long 0e SECT 09 0000 [.data] _CypressAsicStateCheckRegList 000000000043f5f0 long 0e SECT 09 0000 [.data] _aCYPRESS_GoldenRegisterSettings_A11 000000000043ffc0 long 0e SECT 09 0000 [.data] _aCYPRESS_GoldenRegisterSettings_A12 0000000000441330 long 0e SECT 09 0000 [.data] _CYPRESS_HwConstants 00000000004413e0 long 0e SECT 09 0000 [.data] _DevastatorRLCSaveRestoreRegisterList 0000000000441850 long 0e SECT 09 0000 [.data] _aDevastator_GoldenRegisterSettings 0000000000441b30 long 0e SECT 09 0000 [.data] _aScrapper_GoldenRegisterSettings 0000000000442058 long 0e SECT 09 0000 [.data] _Devastator_RLC 0000000000442070 long 0e SECT 09 0000 [.data] _Devastator_HwConstants 00000000004420e0 long 0e SECT 09 0000 [.data] _aRLC_Ucode 0000000000443fd0 long 0e SECT 09 0000 [.data] _aGodavari_GoldenRegisterSettings 0000000000444558 long 0e SECT 09 0000 [.data] _Godavari_UcodeInfo 0000000000444598 long 0e SECT 09 0000 [.data] _sRlcScratchRamInfo 00000000004445b8 long 0e SECT 09 0000 [.data] _Godavari_HwConstants_2411 0000000000444670 long 0e SECT 09 0000 [.data] _GodavariRLCSaveRestoreRegisterList 0000000000444b78 long 0e SECT 09 0000 [.data] _Godavari_RLC_UCODE 0000000000444ba0 long 0e SECT 09 0000 [.data] _aRLC_Ucode 00000000004473e0 long 0e SECT 09 0000 [.data] _HAINAN_GoldenRegisterSettingsA0 00000000004478e8 long 0e SECT 09 0000 [.data] _Hainan_HwConstants 0000000000447970 long 0e SECT 09 0000 [.data] _aRLC_Ucode 0000000000449970 long 0e SECT 09 0000 [.data] _Hainan_RLC 00000000004499f0 long 0e SECT 09 0000 [.data] _aHAWAII_GoldenRegisterSettings 000000000044ae80 long 0e SECT 09 0000 [.data] _Hawaii_UcodeInfo 000000000044aec0 long 0e SECT 09 0000 [.data] _sRlcScratchRamInfo 000000000044aee0 long 0e SECT 09 0000 [.data] _Hawaii_HwConstants 000000000044af90 long 0e SECT 09 0000 [.data] _Hawaii_RLC_UCODE 000000000044afb8 long 0e SECT 09 0000 [.data] _Hawaii_SDMA0_UCODE 000000000044afe0 long 0e SECT 09 0000 [.data] _Hawaii_SDMA1_UCODE 000000000044b008 long 0e SECT 09 0000 [.data] _Hawaii_CE_UCODE 000000000044b030 long 0e SECT 09 0000 [.data] _Hawaii_PFP_UCODE 000000000044b058 long 0e SECT 09 0000 [.data] _Hawaii_ME_UCODE 000000000044b080 long 0e SECT 09 0000 [.data] _Hawaii_MEC1_UCODE 000000000044b0b0 long 0e SECT 09 0000 [.data] _aF32_MEC_Ucode 000000000044f230 long 0e SECT 09 0000 [.data] _aF32_ME_Ucode 00000000004513b0 long 0e SECT 09 0000 [.data] _aF32_PFP_Ucode 0000000000453530 long 0e SECT 09 0000 [.data] _aF32_CE_Ucode 00000000004556b0 long 0e SECT 09 0000 [.data] _aF32_SDMA1_Ucode 0000000000456720 long 0e SECT 09 0000 [.data] _aF32_SDMA0_Ucode 0000000000457790 long 0e SECT 09 0000 [.data] _aRLC_Ucode 0000000000459790 long 0e SECT 09 0000 [.data] _sHawaiiGbMacroTileModeRecords 00000000004597d0 long 0e SECT 09 0000 [.data] _sHawaiiGbTileModeRecords 00000000004598d0 long 0e SECT 09 0000 [.data] _IcelandAsicSetupTable 0000000000459af0 long 0e SECT 09 0000 [.data] _IcelandAsicStateCheckRegList 0000000000459ff0 long 0e SECT 09 0000 [.data] _aICELAND_GoldenRegisterSettings_A0 000000000045a4b8 long 0e SECT 09 0000 [.data] _Iceland_UcodeInfo 000000000045a510 long 0e SECT 09 0000 [.data] _Iceland_RLC_UCODE 000000000045a538 long 0e SECT 09 0000 [.data] _Iceland_SDMA0_UCODE 000000000045a560 long 0e SECT 09 0000 [.data] _Iceland_SDMA1_UCODE 000000000045a588 long 0e SECT 09 0000 [.data] _Iceland_CE_UCODE 000000000045a5b0 long 0e SECT 09 0000 [.data] _Iceland_PFP_UCODE 000000000045a5d8 long 0e SECT 09 0000 [.data] _Iceland_ME_UCODE 000000000045a600 long 0e SECT 09 0000 [.data] _Iceland_MEC1_UCODE 000000000045a628 long 0e SECT 09 0000 [.data] _Iceland_MEC2_UCODE 000000000045a650 long 0e SECT 09 0000 [.data] _aF32_MEC_Ucode 000000000049a7d0 long 0e SECT 09 0000 [.data] _aF32_ME_Ucode 000000000049e950 long 0e SECT 09 0000 [.data] _aF32_PFP_Ucode 00000000004a2ad0 long 0e SECT 09 0000 [.data] _aF32_CE_Ucode 00000000004a4c50 long 0e SECT 09 0000 [.data] _aF32_SDMA0_Ucode 00000000004a6cd0 long 0e SECT 09 0000 [.data] _aRLC_Ucode 00000000004a8cd0 long 0e SECT 09 0000 [.data] _Iceland_HwConstants 00000000004a8d90 long 0e SECT 09 0000 [.data] _sIcelandGbMacroTileModeRecords 00000000004a8e10 long 0e SECT 09 0000 [.data] _sIcelandGbTileModeRecords 00000000004a8f00 long 0e SECT 09 0000 [.data] _aRLC_Ucode 00000000004a9b20 long 0e SECT 09 0000 [.data] _aJUNIPER_GoldenRegisterSettings_A11 00000000004aa260 long 0e SECT 09 0000 [.data] _aJUNIPER_GoldenRegisterSettings_A12 00000000004aa9b8 long 0e SECT 09 0000 [.data] _JUNIPER_HwConstants 00000000004aaa20 long 0e SECT 09 0000 [.data] _aF32_SDMA0_Ucode 00000000004abab0 long 0e SECT 09 0000 [.data] _aF32_SDMA1_Ucode 00000000004acb40 long 0e SECT 09 0000 [.data] _aF32_PFP_Ucode 00000000004aecf0 long 0e SECT 09 0000 [.data] _aF32_CE_Ucode 00000000004b0ea0 long 0e SECT 09 0000 [.data] _aF32_ME_Ucode 00000000004b3050 long 0e SECT 09 0000 [.data] _aF32_MEC_Ucode 00000000004b7960 long 0e SECT 09 0000 [.data] _aKalindi_GoldenRegisterSettings 00000000004b7ef8 long 0e SECT 09 0000 [.data] _Kalindi_UcodeInfo 00000000004b7f38 long 0e SECT 09 0000 [.data] _sRlcScratchRamInfo 00000000004b7f58 long 0e SECT 09 0000 [.data] _Kalindi_HwConstants_4882 00000000004b8010 long 0e SECT 09 0000 [.data] _KalindiRLCSaveRestoreRegisterList 00000000004b8518 long 0e SECT 09 0000 [.data] _Kalindi_RLC_UCODE 00000000004b8540 long 0e SECT 09 0000 [.data] _aRLC_Ucode 00000000004bad90 long 0e SECT 09 0000 [.data] _OLAND_GoldenRegisterSettingsA0 00000000004bb2e0 long 0e SECT 09 0000 [.data] _Oland_HwConstants 00000000004bb360 long 0e SECT 09 0000 [.data] _aRLC_Ucode 00000000004bd360 long 0e SECT 09 0000 [.data] _Oland_RLC 00000000004bd380 long 0e SECT 09 0000 [.data] _sOlandGbTileModeRecords 00000000004bd4c0 long 0e SECT 09 0000 [.data] _aPITCAIRN_GoldenRegisterSettingsA11 00000000004bdaf0 long 0e SECT 09 0000 [.data] _aPITCAIRN_GoldenRegisterSettingsA12 00000000004be1e8 long 0e SECT 09 0000 [.data] _Pitcairn_HwConstants 00000000004be270 long 0e SECT 09 0000 [.data] _aRLC_Ucode 00000000004c0270 long 0e SECT 09 0000 [.data] _Pitcairn_RLC 00000000004c0290 long 0e SECT 09 0000 [.data] _SiNi_EngineDependencyTbl 00000000004c0380 long 0e SECT 09 0000 [.data] _aRLC_Ucode 00000000004c0fa0 long 0e SECT 09 0000 [.data] _aREDWOOD_GoldenRegisterSettings 00000000004c1598 long 0e SECT 09 0000 [.data] _REDWOOD_HwConstants 00000000004c1660 long 0e SECT 09 0000 [.data] _aSpectre_GoldenRegisterSettings 00000000004c1ec8 long 0e SECT 09 0000 [.data] _Spectre_UcodeInfo 00000000004c1f08 long 0e SECT 09 0000 [.data] _sRlcScratchRamInfo 00000000004c1f28 long 0e SECT 09 0000 [.data] _Spectre_HwConstants_8812 00000000004c1fe0 long 0e SECT 09 0000 [.data] _SpectreRLCSaveRestoreRegisterList 00000000004c26d0 long 0e SECT 09 0000 [.data] _Spectre_RLC_UCODE 00000000004c26f8 long 0e SECT 09 0000 [.data] _Spectre_SDMA0_UCODE 00000000004c2720 long 0e SECT 09 0000 [.data] _Spectre_SDMA1_UCODE 00000000004c2748 long 0e SECT 09 0000 [.data] _Spectre_CE_UCODE 00000000004c2770 long 0e SECT 09 0000 [.data] _Spectre_PFP_UCODE 00000000004c2798 long 0e SECT 09 0000 [.data] _Spectre_ME_UCODE 00000000004c27c0 long 0e SECT 09 0000 [.data] _Spectre_MEC1_UCODE 00000000004c27e8 long 0e SECT 09 0000 [.data] _Spectre_MEC2_UCODE 00000000004c2810 long 0e SECT 09 0000 [.data] _aF32_MEC_Ucode 00000000004c6990 long 0e SECT 09 0000 [.data] _aF32_ME_Ucode 00000000004c8b10 long 0e SECT 09 0000 [.data] _aF32_PFP_Ucode 00000000004cac90 long 0e SECT 09 0000 [.data] _aF32_CE_Ucode 00000000004cce10 long 0e SECT 09 0000 [.data] _aF32_SDMA1_Ucode 00000000004cde80 long 0e SECT 09 0000 [.data] _aF32_SDMA0_Ucode 00000000004ceef0 long 0e SECT 09 0000 [.data] _aRLC_Ucode 00000000004d16f0 long 0e SECT 09 0000 [.data] _sSpectreGbMacroTileModeRecords 00000000004d1730 long 0e SECT 09 0000 [.data] _sSpectreGbTileModeRecords 00000000004d1870 long 0e SECT 09 0000 [.data] _SumoRLCSaveRestoreRegisterList 00000000004d19c0 long 0e SECT 09 0000 [.data] _aRLC_Ucode 00000000004d2630 long 0e SECT 09 0000 [.data] _aSuperSUMO_GoldenRegisterSettings 00000000004d29e0 long 0e SECT 09 0000 [.data] _aSUMO_GoldenRegisterSettings 00000000004d2db0 long 0e SECT 09 0000 [.data] _aWrestler_GoldenRegisterSettings 00000000004d3038 long 0e SECT 09 0000 [.data] _Wrestler_HwConstants 00000000004d30a0 long 0e SECT 09 0000 [.data] _SumoAsicStateCheckRegListWithUVD 00000000004d3218 long 0e SECT 09 0000 [.data] _SumoAsicStateRegInfo 00000000004d3228 long 0e SECT 09 0000 [.data] _StrippedSumo_HwConstants 00000000004d3290 long 0e SECT 09 0000 [.data] _Sumo_HwConstants 00000000004d32f8 long 0e SECT 09 0000 [.data] _SuperSumo3Simd_HwConstants 00000000004d3360 long 0e SECT 09 0000 [.data] _SuperSumo4Simd_HwConstants 00000000004d33c8 long 0e SECT 09 0000 [.data] _SuperSumo_HwConstants 00000000004d3c30 long 0e SECT 09 0000 [.data] _TahitiAsicSetupTable 00000000004d3d50 long 0e SECT 09 0000 [.data] _TahitiAsicStateCheckRegList 00000000004d4400 long 0e SECT 09 0000 [.data] _aTAHITI_GoldenRegisterSettingsA11 00000000004d4bf0 long 0e SECT 09 0000 [.data] _aTAHITI_GoldenRegisterSettingsA21 00000000004d5488 long 0e SECT 09 0000 [.data] _Tahiti_HwConstants 00000000004d5510 long 0e SECT 09 0000 [.data] _aRLC_Ucode 00000000004d7510 long 0e SECT 09 0000 [.data] _Tahiti_RLC 00000000004d7530 long 0e SECT 09 0000 [.data] _sTahitiGbTileModeRecords 00000000004d7630 long 0e SECT 09 0000 [.data] _TongaAsicSetupTable 00000000004d7860 long 0e SECT 09 0000 [.data] _TongaAsicStateCheckRegList 00000000004d7de0 long 0e SECT 09 0000 [.data] _aTONGA_GoldenRegisterSettings_A1 00000000004d83f0 long 0e SECT 09 0000 [.data] _Tonga_UcodeInfo 00000000004d8450 long 0e SECT 09 0000 [.data] _aTONGA_GoldenRegisterSettings_A0 00000000004d8a60 long 0e SECT 09 0000 [.data] _Tonga_UcodeInfo_A0 00000000004d8ab8 long 0e SECT 09 0000 [.data] _Tonga_RLC_UCODE_A0 00000000004d8ae0 long 0e SECT 09 0000 [.data] _Tonga_SDMA0_UCODE 00000000004d8b08 long 0e SECT 09 0000 [.data] _Tonga_SDMA1_UCODE 00000000004d8b30 long 0e SECT 09 0000 [.data] _Tonga_CE_UCODE 00000000004d8b58 long 0e SECT 09 0000 [.data] _Tonga_PFP_UCODE 00000000004d8b80 long 0e SECT 09 0000 [.data] _Tonga_ME_UCODE 00000000004d8ba8 long 0e SECT 09 0000 [.data] _Tonga_MEC1_UCODE 00000000004d8bd0 long 0e SECT 09 0000 [.data] _Tonga_MEC2_UCODE 00000000004d8c00 long 0e SECT 09 0000 [.data] _aF32_MEC_Ucode 0000000000518d80 long 0e SECT 09 0000 [.data] _aF32_ME_Ucode 000000000051cf00 long 0e SECT 09 0000 [.data] _aF32_PFP_Ucode 0000000000521080 long 0e SECT 09 0000 [.data] _aF32_CE_Ucode 0000000000523200 long 0e SECT 09 0000 [.data] _aF32_SDMA0_Ucode 0000000000525a80 long 0e SECT 09 0000 [.data] _aRLC_Ucode_A0 0000000000527a80 long 0e SECT 09 0000 [.data] _Tonga_RLC_UCODE 0000000000527ab0 long 0e SECT 09 0000 [.data] _aRLC_Ucode 0000000000529ab0 long 0e SECT 09 0000 [.data] _sRlcScratchRamInfo 0000000000529b18 long 0e SECT 09 0000 [.data] _Tonga_HwConstants 0000000000529bd0 long 0e SECT 09 0000 [.data] _register_restore 000000000052b2f0 long 0e SECT 09 0000 [.data] _register_list_format 000000000052b390 long 0e SECT 09 0000 [.data] _register_restore_separate 000000000052b468 long 0e SECT 09 0000 [.data] _register_list_format_separate 000000000052b480 long 0e SECT 09 0000 [.data] _sTongaGbMacroTileModeRecords 000000000052b500 long 0e SECT 09 0000 [.data] _sTongaGbTileModeRecords 000000000052b600 long 0e SECT 09 0000 [.data] _aRLC_Ucode 000000000052c220 long 0e SECT 09 0000 [.data] _aTURKS_GoldenRegisterSettings_A11 000000000052c488 long 0e SECT 09 0000 [.data] _TURKS_HwConstants 000000000052ec88 __float128 e SECT 0a 0000 [__DATA.__common] __realmain 000000000052ec90 __float128 e SECT 0a 0000 [__DATA.__common] __antimain 000000000052f320 long 0e SECT 0b 0000 [.bss] bindingDoesWriteBitfield 000000000052f340 long 0e SECT 0b 0000 [.bss] gl_assert_wait_timeout_event 000000000052f344 long 0e SECT 0b 0000 [.bss] gl_assert_wait_timeout_event 000000000052f348 long 0e SECT 0b 0000 [.bss] gl_assert_wait_timeout_event 000000000052f34c long 0e SECT 0b 0000 [.bss] gl_assert_wait_timeout_event 000000000052f350 long 0e SECT 0b 0000 [.bss] gl_assert_wait_timeout_event 000000000052f354 long 0e SECT 0b 0000 [.bss] gl_assert_wait_timeout_event 000000000052f358 long 0e SECT 0b 0000 [.bss] gl_assert_wait_timeout_event 000000000052f35c long 0e SECT 0b 0000 [.bss] gl_assert_wait_timeout_event 000000000052f360 long 0e SECT 0b 0000 [.bss] gl_assert_wait_timeout_event 000000000052f368 long 0e SECT 0b 0000 [.bss] _sRlcScratchRamInfo 0000000000146250 __float128 0f SECT 03 0000 [.const] _AMDRadeonAccelerator_VERS_NUM 0000000000146150 __float128 0f SECT 03 0000 [.const] _AMDRadeonAccelerator_VERS_STRING 00000000003e2360 __float128 0f SECT 09 0000 [.data] _APUNotSupportDualGraphicsBranding 00000000000dab3f __float128 0f SECT 01 0000 [.text] _ATI_Read_AGP 00000000000dab91 __float128 0f SECT 01 0000 [.text] _ATI_Write_AGP 00000000000dabfb __float128 0f SECT 01 0000 [.text] _ATI_Write_AGP_BusCntl 00000000000dbfbf __float128 0f SECT 01 0000 [.text] _ATOM_CheckExtPwrConnect 00000000000dc0d7 __float128 0f SECT 01 0000 [.text] _ATOM_CheckForFireGLBoard 00000000000dc1ba __float128 0f SECT 01 0000 [.text] _ATOM_CheckInternalSSInfo 00000000000dc38b __float128 0f SECT 01 0000 [.text] _ATOM_CheckSdiSupport 00000000000db2ea __float128 0f SECT 01 0000 [.text] _ATOM_CheckVBIOSInfo 00000000000db4f1 __float128 0f SECT 01 0000 [.text] _ATOM_CheckVBIOSTableRevision 00000000000db582 __float128 0f SECT 01 0000 [.text] _ATOM_Check_BIOSReserveFB_BLOCK 00000000000db80a __float128 0f SECT 01 0000 [.text] _ATOM_Check_BIOSSupportInfo 00000000000db6a1 __float128 0f SECT 01 0000 [.text] _ATOM_ExecuteBIOSTable 00000000000dc280 __float128 0f SECT 01 0000 [.text] _ATOM_GetPLLDividers 00000000000db536 __float128 0f SECT 01 0000 [.text] _ATOM_GetTablePointer 00000000000dc02b __float128 0f SECT 01 0000 [.text] _ATOM_InitFanCntl 00000000000db080 __float128 0f SECT 01 0000 [.text] _ATOM_InitParser 00000000000dbe72 __float128 0f SECT 01 0000 [.text] _ATOM_NoBiosInitializeAdapter 00000000000db309 __float128 0f SECT 01 0000 [.text] _ATOM_PostVBIOS 00000000000db5cf __float128 0f SECT 01 0000 [.text] _ATOM_QueryBIOSReserveFB 00000000000db7b0 __float128 0f SECT 01 0000 [.text] _ATOM_QueryTableRevision 00000000000f9e4c __float128 0f SECT 01 0000 [.text] _AddAlignment 00000000000f9f70 __float128 0f SECT 01 0000 [.text] _AddPowerOf2Alignment 00000000000cd25a __float128 0f SECT 01 0000 [.text] _AddrCombineBankPipeSwizzle 00000000000cd2c0 __float128 0f SECT 01 0000 [.text] _AddrComputeBaseSwizzle 00000000000cd0a4 __float128 0f SECT 01 0000 [.text] _AddrComputeCmaskAddrFromCoord 00000000000cd0d7 __float128 0f SECT 01 0000 [.text] _AddrComputeCmaskCoordFromAddr 00000000000cd071 __float128 0f SECT 01 0000 [.text] _AddrComputeCmaskInfo 00000000000cd1a3 __float128 0f SECT 01 0000 [.text] _AddrComputeDccInfo 00000000000cd13d __float128 0f SECT 01 0000 [.text] _AddrComputeFmaskAddrFromCoord 00000000000cd170 __float128 0f SECT 01 0000 [.text] _AddrComputeFmaskCoordFromAddr 00000000000cd10a __float128 0f SECT 01 0000 [.text] _AddrComputeFmaskInfo 00000000000cd00b __float128 0f SECT 01 0000 [.text] _AddrComputeHtileAddrFromCoord 00000000000cd03e __float128 0f SECT 01 0000 [.text] _AddrComputeHtileCoordFromAddr 00000000000ccfd8 __float128 0f SECT 01 0000 [.text] _AddrComputeHtileInfo 00000000000cd452 __float128 0f SECT 01 0000 [.text] _AddrComputePrtInfo 00000000000cd28d __float128 0f SECT 01 0000 [.text] _AddrComputeSliceSwizzle 00000000000ccf72 __float128 0f SECT 01 0000 [.text] _AddrComputeSurfaceAddrFromCoord 00000000000ccfa5 __float128 0f SECT 01 0000 [.text] _AddrComputeSurfaceCoordFromAddr 00000000000ccf3f __float128 0f SECT 01 0000 [.text] _AddrComputeSurfaceInfo 00000000000cd3b9 __float128 0f SECT 01 0000 [.text] _AddrConvertTileIndex 00000000000cd3ec __float128 0f SECT 01 0000 [.text] _AddrConvertTileIndex1 00000000000cd386 __float128 0f SECT 01 0000 [.text] _AddrConvertTileInfoToHW 00000000000ccf07 __float128 0f SECT 01 0000 [.text] _AddrCreate 00000000000ccf11 __float128 0f SECT 01 0000 [.text] _AddrDestroy 00000000000cd227 __float128 0f SECT 01 0000 [.text] _AddrExtractBankPipeSwizzle 00000000000cd41f __float128 0f SECT 01 0000 [.text] _AddrGetTileIndex 00000000000cd1d6 __float128 0f SECT 01 0000 [.text] _AddrGetVersion 00000000000cd20a __float128 0f SECT 01 0000 [.text] _AddrUseCombinedSwizzle 00000000000cd1ed __float128 0f SECT 01 0000 [.text] _AddrUseTileIndex 00000000000f80d3 __float128 0f SECT 01 0000 [.text] _AdjustRequestedMcAddressRangeInfo 000000000052c700 __float128 0f SECT 09 0000 [.data] _AlignmentMask 0000000000121293 __float128 0f SECT 01 0000 [.text] _AllocateMemory 00000000003e1980 __float128 0f SECT 09 0000 [.data] _AsicNameTable 00000000000dbeda __float128 0f SECT 01 0000 [.text] _Atomcail_ulNoBiosMemoryConfigAndSize 00000000003c86d8 __float128 0f SECT 09 0000 [.data] _BARTS_GoldenSettings_A11 00000000003d8140 __float128 0f SECT 09 0000 [.data] _BONAIRE_GoldenSettings_A0 00000000003d8c68 __float128 0f SECT 09 0000 [.data] _BONAIRE_GoldenSettings_A1 00000000003c8480 __float128 0f SECT 09 0000 [.data] _Barts_RLC 00000000003d7358 __float128 0f SECT 09 0000 [.data] _BonaireAsicStateRegInfo 00000000003d7370 __float128 0f SECT 09 0000 [.data] _BonaireEngineRunningStateRegInfo 00000000003d75f0 __float128 0f SECT 09 0000 [.data] _BonaireFeatureSupport1 00000000003d6f70 __float128 0f SECT 09 0000 [.data] _BonaireMicroEngineRegisters 00000000003d8c80 __float128 0f SECT 09 0000 [.data] _BonaireTcpChanSteerLo 00000000003d0be0 __float128 0f SECT 09 0000 [.data] _Bonaire_CE_UCODE 00000000003d6f40 __float128 0f SECT 09 0000 [.data] _Bonaire_MEC1_UCODE 00000000003d2d90 __float128 0f SECT 09 0000 [.data] _Bonaire_ME_UCODE 00000000003cea30 __float128 0f SECT 09 0000 [.data] _Bonaire_PFP_UCODE 00000000003ca760 __float128 0f SECT 09 0000 [.data] _Bonaire_RLC_UCODE 00000000003cb7f8 __float128 0f SECT 09 0000 [.data] _Bonaire_SDMA0_UCODE 00000000003cc888 __float128 0f SECT 09 0000 [.data] _Bonaire_SDMA1_UCODE 00000000000dc414 __float128 0f SECT 01 0000 [.text] _Bonaire_SetupASIC 00000000003d9eb0 __float128 0f SECT 09 0000 [.data] _CAICOS_GoldenSettings_A11 00000000003e1970 __float128 0f SECT 09 0000 [.data] _CAILAsicCapsExceptionTable 00000000003dafb0 __float128 0f SECT 09 0000 [.data] _CAILAsicCapsInitTable 00000000000e8f88 __float128 0f SECT 01 0000 [.text] _CAILCheckForcedAGPSpeed 00000000000e848e __float128 0f SECT 01 0000 [.text] _CAILConnectedStandbyControl 00000000000e7e71 __float128 0f SECT 01 0000 [.text] _CAILCrossFireControl 00000000000e7e18 __float128 0f SECT 01 0000 [.text] _CAILCrossFireSupport 00000000000e639a __float128 0f SECT 01 0000 [.text] _CAILDoorbellApertureControl 00000000000e69e7 __float128 0f SECT 01 0000 [.text] _CAILEarlyASICInit 00000000000e7941 __float128 0f SECT 01 0000 [.text] _CAILEvaluateAsicHangState 00000000000e8480 __float128 0f SECT 01 0000 [.text] _CAILEventNotification 00000000000e73b0 __float128 0f SECT 01 0000 [.text] _CAILExit 00000000000e553c __float128 0f SECT 01 0000 [.text] _CAILFixChipsetBugs 00000000000e7378 __float128 0f SECT 01 0000 [.text] _CAILGetDynamicClockMode 00000000000e4ce4 __float128 0f SECT 01 0000 [.text] _CAILGetExtensionSize 00000000000e789d __float128 0f SECT 01 0000 [.text] _CAILGetHungBlocks 00000000000e7a31 __float128 0f SECT 01 0000 [.text] _CAILInitEasf 00000000000f2c25 __float128 0f SECT 01 0000 [.text] _CAILInitFunctionPointer 00000000000e4d5f __float128 0f SECT 01 0000 [.text] _CAILInitialize 00000000000e84ba __float128 0f SECT 01 0000 [.text] _CAILIoAccess 00000000000e756c __float128 0f SECT 01 0000 [.text] _CAILLiteResetVPU 00000000000e83b1 __float128 0f SECT 01 0000 [.text] _CAILMicroEngineControl 00000000000e4f07 __float128 0f SECT 01 0000 [.text] _CAILNoBiosInitializeAdapter 00000000000e768a __float128 0f SECT 01 0000 [.text] _CAILPerEngineReset 00000000000e4cef __float128 0f SECT 01 0000 [.text] _CAILPostVBIOS 00000000000e8388 __float128 0f SECT 01 0000 [.text] _CAILPowerControl 00000000000e4ff9 __float128 0f SECT 01 0000 [.text] _CAILQueryASICInfo 00000000000e6e69 __float128 0f SECT 01 0000 [.text] _CAILQueryASICName 00000000000e6ff5 __float128 0f SECT 01 0000 [.text] _CAILQueryASICNameEx 00000000000e751f __float128 0f SECT 01 0000 [.text] _CAILQueryASICRunningState 00000000000e7174 __float128 0f SECT 01 0000 [.text] _CAILQueryDualGraphicsBrandingName 00000000000e8355 __float128 0f SECT 01 0000 [.text] _CAILQueryEngineDependency 00000000000e7577 __float128 0f SECT 01 0000 [.text] _CAILQueryEngineRunningState 00000000000e65b2 __float128 0f SECT 01 0000 [.text] _CAILQueryMCAddressRange 00000000000e5435 __float128 0f SECT 01 0000 [.text] _CAILQuerySystemInfo 00000000000e6589 __float128 0f SECT 01 0000 [.text] _CAILReleaseMCAddressRange 00000000000e64ea __float128 0f SECT 01 0000 [.text] _CAILReserveMCAddressRange 00000000000e4ee1 __float128 0f SECT 01 0000 [.text] _CAILResetAndInitializeGUI 00000000000e7630 __float128 0f SECT 01 0000 [.text] _CAILResetEngine 00000000000e7cec __float128 0f SECT 01 0000 [.text] _CAILSamuControl 00000000000e7370 __float128 0f SECT 01 0000 [.text] _CAILSetDynamicClock 00000000000e78ab __float128 0f SECT 01 0000 [.text] _CAILSoftResetHungBlocks 00000000000e7502 __float128 0f SECT 01 0000 [.text] _CAILSurpriseRemoval 00000000000f4789 __float128 0f SECT 01 0000 [.text] _CAILSwitchPCIELane 00000000000e7a9d __float128 0f SECT 01 0000 [.text] _CAILUvdControl 00000000000e6d7c __float128 0f SECT 01 0000 [.text] _CAILVPURecoveryBegin 00000000000e6df6 __float128 0f SECT 01 0000 [.text] _CAILVPURecoveryEnd 00000000000e7bd4 __float128 0f SECT 01 0000 [.text] _CAILVceControl 00000000000e609e __float128 0f SECT 01 0000 [.text] _CAIL_ASICSetup 00000000000eb49a __float128 0f SECT 01 0000 [.text] _CAIL_AccessSpringDale 00000000000e84b4 __float128 0f SECT 01 0000 [.text] _CAIL_AsicShutDown 000000000010e58c __float128 0f SECT 01 0000 [.text] _CAIL_BridgeASPMWorkaround 000000000010e723 __float128 0f SECT 01 0000 [.text] _CAIL_CheckAspmCapability 00000000003dadf0 __float128 0f SECT 09 0000 [.data] _CAIL_DDI_CAPS_AMETHYST_A0 00000000003dae30 __float128 0f SECT 09 0000 [.data] _CAIL_DDI_CAPS_AMETHYST_A1 00000000003da5b0 __float128 0f SECT 09 0000 [.data] _CAIL_DDI_CAPS_BARTS_A11 00000000003daf30 __float128 0f SECT 09 0000 [.data] _CAIL_DDI_CAPS_BERMUDA_A0 00000000003da5f0 __float128 0f SECT 09 0000 [.data] _CAIL_DDI_CAPS_BLACKCOMB_A11 00000000003da930 __float128 0f SECT 09 0000 [.data] _CAIL_DDI_CAPS_BONAIRE_A0 00000000003da970 __float128 0f SECT 09 0000 [.data] _CAIL_DDI_CAPS_BONAIRE_A1 00000000003da030 __float128 0f SECT 09 0000 [.data] _CAIL_DDI_CAPS_BROADWAY_A11 00000000003da3b0 __float128 0f SECT 09 0000 [.data] _CAIL_DDI_CAPS_CAICOS_A11 00000000003da7b0 __float128 0f SECT 09 0000 [.data] _CAIL_DDI_CAPS_CAPEVERDE_A11 00000000003da7f0 __float128 0f SECT 09 0000 [.data] _CAIL_DDI_CAPS_CAPEVERDE_A12 00000000003daef0 __float128 0f SECT 09 0000 [.data] _CAIL_DDI_CAPS_CARRIZO_SIMNOW 00000000003da570 __float128 0f SECT 09 0000 [.data] _CAIL_DDI_CAPS_CAYMAN_A11 00000000003da0f0 __float128 0f SECT 09 0000 [.data] _CAIL_DDI_CAPS_CEDAR_A11 00000000003da130 __float128 0f SECT 09 0000 [.data] _CAIL_DDI_CAPS_CEDAR_MV_A11 00000000003d9f30 __float128 0f SECT 09 0000 [.data] _CAIL_DDI_CAPS_CYPRESS_A11 00000000003d9f70 __float128 0f SECT 09 0000 [.data] _CAIL_DDI_CAPS_CYPRESS_FS_A11 00000000003da8b0 __float128 0f SECT 09 0000 [.data] _CAIL_DDI_CAPS_DEVASTATOR_A0 00000000003da530 __float128 0f SECT 09 0000 [.data] _CAIL_DDI_CAPS_EMBEDDED_WHISTLER_A11 00000000003daf70 __float128 0f SECT 09 0000 [.data] _CAIL_DDI_CAPS_FIJI_A0 00000000003dae70 __float128 0f SECT 09 0000 [.data] _CAIL_DDI_CAPS_GODAVARI_A0 00000000003daeb0 __float128 0f SECT 09 0000 [.data] _CAIL_DDI_CAPS_GODAVARI_TABLET_A0 00000000003dacb0 __float128 0f SECT 09 0000 [.data] _CAIL_DDI_CAPS_HAWAII_A0 00000000003da830 __float128 0f SECT 09 0000 [.data] _CAIL_DDI_CAPS_HEATHROW_A11 00000000003da870 __float128 0f SECT 09 0000 [.data] _CAIL_DDI_CAPS_HEATHROW_A12 00000000003da330 __float128 0f SECT 09 0000 [.data] _CAIL_DDI_CAPS_IBIZA_A11 00000000003dad30 __float128 0f SECT 09 0000 [.data] _CAIL_DDI_CAPS_ICELAND_A0 00000000003d9ff0 __float128 0f SECT 09 0000 [.data] _CAIL_DDI_CAPS_JUNIPER_A11 00000000003daab0 __float128 0f SECT 09 0000 [.data] _CAIL_DDI_CAPS_KALINDI_A0 00000000003daaf0 __float128 0f SECT 09 0000 [.data] _CAIL_DDI_CAPS_KALINDI_A0_E 00000000003dab30 __float128 0f SECT 09 0000 [.data] _CAIL_DDI_CAPS_KALINDI_A1 00000000003dab70 __float128 0f SECT 09 0000 [.data] _CAIL_DDI_CAPS_KALINDI_A1_E 00000000003da370 __float128 0f SECT 09 0000 [.data] _CAIL_DDI_CAPS_KAUAI_A11 00000000003d9fb0 __float128 0f SECT 09 0000 [.data] _CAIL_DDI_CAPS_LEXINGTON_A11 00000000003da470 __float128 0f SECT 09 0000 [.data] _CAIL_DDI_CAPS_LOMBOK_A11 00000000003da0b0 __float128 0f SECT 09 0000 [.data] _CAIL_DDI_CAPS_MADISON_A11 00000000003dabf0 __float128 0f SECT 09 0000 [.data] _CAIL_DDI_CAPS_MARS_A0 00000000003dacf0 __float128 0f SECT 09 0000 [.data] _CAIL_DDI_CAPS_MAUI_A0 00000000003dabb0 __float128 0f SECT 09 0000 [.data] _CAIL_DDI_CAPS_OLAND_A0 00000000003dac30 __float128 0f SECT 09 0000 [.data] _CAIL_DDI_CAPS_OLAND_PRO_GL 00000000003da170 __float128 0f SECT 09 0000 [.data] _CAIL_DDI_CAPS_PARK_A11 00000000003da6b0 __float128 0f SECT 09 0000 [.data] _CAIL_DDI_CAPS_PITCAIRN_A11 00000000003da6f0 __float128 0f SECT 09 0000 [.data] _CAIL_DDI_CAPS_PITCAIRN_A12 00000000003da070 __float128 0f SECT 09 0000 [.data] _CAIL_DDI_CAPS_REDWOOD_A11 00000000003da9b0 __float128 0f SECT 09 0000 [.data] _CAIL_DDI_CAPS_SATURN_A0 00000000003da9f0 __float128 0f SECT 09 0000 [.data] _CAIL_DDI_CAPS_SATURN_A1 00000000003da8f0 __float128 0f SECT 09 0000 [.data] _CAIL_DDI_CAPS_SCRAPPER_LITE_A0 00000000003da3f0 __float128 0f SECT 09 0000 [.data] _CAIL_DDI_CAPS_SEYMOUR_A11 00000000003daa30 __float128 0f SECT 09 0000 [.data] _CAIL_DDI_CAPS_SPECTRE_A0 00000000003daa70 __float128 0f SECT 09 0000 [.data] _CAIL_DDI_CAPS_SPECTRE_A0_E 00000000003da1f0 __float128 0f SECT 09 0000 [.data] _CAIL_DDI_CAPS_SUMO_A0 00000000003da2b0 __float128 0f SECT 09 0000 [.data] _CAIL_DDI_CAPS_SUMO_B0 00000000003dac70 __float128 0f SECT 09 0000 [.data] _CAIL_DDI_CAPS_SUN_A0 00000000003da1b0 __float128 0f SECT 09 0000 [.data] _CAIL_DDI_CAPS_SUPERSUMO_A0 00000000003da270 __float128 0f SECT 09 0000 [.data] _CAIL_DDI_CAPS_SUPERSUMO_B0 00000000003da630 __float128 0f SECT 09 0000 [.data] _CAIL_DDI_CAPS_TAHITI_A11 00000000003da670 __float128 0f SECT 09 0000 [.data] _CAIL_DDI_CAPS_TAHITI_A21 00000000003da4b0 __float128 0f SECT 09 0000 [.data] _CAIL_DDI_CAPS_THAMES_A11 00000000003dad70 __float128 0f SECT 09 0000 [.data] _CAIL_DDI_CAPS_TONGA_A0 00000000003dadb0 __float128 0f SECT 09 0000 [.data] _CAIL_DDI_CAPS_TONGA_A1 00000000003da430 __float128 0f SECT 09 0000 [.data] _CAIL_DDI_CAPS_TURKS_A11 00000000003da4f0 __float128 0f SECT 09 0000 [.data] _CAIL_DDI_CAPS_WHISTLER_A11 00000000003da730 __float128 0f SECT 09 0000 [.data] _CAIL_DDI_CAPS_WIMBLEDON_A11 00000000003da770 __float128 0f SECT 09 0000 [.data] _CAIL_DDI_CAPS_WIMBLEDON_A12 00000000003da230 __float128 0f SECT 09 0000 [.data] _CAIL_DDI_CAPS_WRESTLER_A0 00000000003da2f0 __float128 0f SECT 09 0000 [.data] _CAIL_DDI_CAPS_WRESTLER_A1 00000000000e63e4 __float128 0f SECT 01 0000 [.text] _CAIL_ExecuteBIOSTable 00000000000e697c __float128 0f SECT 01 0000 [.text] _CAIL_GetGuiStatus 00000000000e65db __float128 0f SECT 01 0000 [.text] _CAIL_InitAdditionInfo 00000000000e7f10 __float128 0f SECT 01 0000 [.text] _CAIL_InitParameter 00000000000e6790 __float128 0f SECT 01 0000 [.text] _CAIL_QueryAdditionInfo 00000000000e63b3 __float128 0f SECT 01 0000 [.text] _CAIL_QueryBIOSReserveFB 00000000000e8140 __float128 0f SECT 01 0000 [.text] _CAIL_QueryParameter 00000000000e6490 __float128 0f SECT 01 0000 [.text] _CAIL_QueryTableRevision 00000000000e8340 __float128 0f SECT 01 0000 [.text] _CAIL_ReConfigUmaSpLayout 00000000000e6cf3 __float128 0f SECT 01 0000 [.text] _CAIL_TuneNorthBridge 000000000010f243 __float128 0f SECT 01 0000 [.text] _CAIL_VPURecoveryBegin 000000000010f406 __float128 0f SECT 01 0000 [.text] _CAIL_VPURecoveryEnd 00000000000e69a5 __float128 0f SECT 01 0000 [.text] _CAIL_WaitForIdle 00000000000e69c6 __float128 0f SECT 01 0000 [.text] _CAIL_WaitForMCIdle 00000000003e3fa8 __float128 0f SECT 09 0000 [.data] _CAPEVERDE_GoldenSettings_A11 00000000003e4cd8 __float128 0f SECT 09 0000 [.data] _CAPEVERDE_GoldenSettings_A12 00000000003e7188 __float128 0f SECT 09 0000 [.data] _CARRIZO_GoldenSettings_A0_8812 000000000043d7d0 __float128 0f SECT 09 0000 [.data] _CAYMAN_GoldenSettings_A11 000000000043dd80 __float128 0f SECT 09 0000 [.data] _CEDAR_GoldenSettings_A11 00000000004d3a50 __float128 0f SECT 09 0000 [.data] _CF_MEM_CLT_GUP_RANGE_TAHITI 0000000000122599 __float128 0f SECT 01 0000 [.text] _CSBGetBuffer 00000000001224fc __float128 0f SECT 01 0000 [.text] _CSBGetBufferSize 000000000043ffa8 __float128 0f SECT 09 0000 [.data] _CYPRESS_GoldenSettings_A11 0000000000440968 __float128 0f SECT 09 0000 [.data] _CYPRESS_GoldenSettings_A12 00000000003d9c40 __float128 0f SECT 09 0000 [.data] _Caicos_RLC 00000000000ed521 __float128 0f SECT 01 0000 [.text] _CailAllocatSysResource 00000000000f3e64 __float128 0f SECT 01 0000 [.text] _CailAllocateLargeMemory 00000000000f3ddb __float128 0f SECT 01 0000 [.text] _CailAllocateMemory 00000000000e84f0 __float128 0f SECT 01 0000 [.text] _CailCapsEnabled 00000000000ef9c4 __float128 0f SECT 01 0000 [.text] _CailCfCheckMaxXDMASupportedMVPUNumber 00000000000eec1f __float128 0f SECT 01 0000 [.text] _CailCfCloseTemporaryMailBox 00000000000ef8c4 __float128 0f SECT 01 0000 [.text] _CailCfConfigSetup 00000000000eea82 __float128 0f SECT 01 0000 [.text] _CailCfGetP2PFlushCommand 00000000000ef683 __float128 0f SECT 01 0000 [.text] _CailCfGetP2PFlushCommandEx 00000000000ee453 __float128 0f SECT 01 0000 [.text] _CailCfInitPeerAperture 00000000000ee7ef __float128 0f SECT 01 0000 [.text] _CailCfInitXdmaAperture 00000000000eeb37 __float128 0f SECT 01 0000 [.text] _CailCfOpenTemporaryMailBox 00000000000ef640 __float128 0f SECT 01 0000 [.text] _CailCfQueryMemoryClientGroup 00000000000ef833 __float128 0f SECT 01 0000 [.text] _CailCfResyncPeerApertureInternalState 00000000000ee72c __float128 0f SECT 01 0000 [.text] _CailCfSetPeerApertureDefault 00000000000ee9f9 __float128 0f SECT 01 0000 [.text] _CailCfSetXdmaApertureDefault 00000000000e9a50 __float128 0f SECT 01 0000 [.text] _CailCheckAGPCalibrationFix 00000000000e968c __float128 0f SECT 01 0000 [.text] _CailCheckAGPFastWrite 00000000000e982f __float128 0f SECT 01 0000 [.text] _CailCheckAGPWrite 00000000000ea8e0 __float128 0f SECT 01 0000 [.text] _CailCheckASICInfo 00000000000ea6aa __float128 0f SECT 01 0000 [.text] _CailCheckAdapterFireGLBoard 00000000000eb075 __float128 0f SECT 01 0000 [.text] _CailCheckAsic64bitBars 00000000000ebe53 __float128 0f SECT 01 0000 [.text] _CailCheckAsicResetState 00000000000eb89c __float128 0f SECT 01 0000 [.text] _CailCheckAsicState 00000000000eb2d8 __float128 0f SECT 01 0000 [.text] _CailCheckBIOSDependentASICInfo 00000000000e9aae __float128 0f SECT 01 0000 [.text] _CailCheckChipSetInfo 00000000000ef0c6 __float128 0f SECT 01 0000 [.text] _CailCheckCrossFireAsicCfg 00000000000eee48 __float128 0f SECT 01 0000 [.text] _CailCheckCrossFireAsicIDInfo 00000000000e9226 __float128 0f SECT 01 0000 [.text] _CailCheckH2PBridge 00000000000e9ee5 __float128 0f SECT 01 0000 [.text] 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0000 [.text] _CailConnectedStandbyQueryRegisterList 00000000000ed4d1 __float128 0f SECT 01 0000 [.text] _CailConnectedStandbySetMasterPacketMCAddress 00000000000f3f14 __float128 0f SECT 01 0000 [.text] _CailDelayMicroSeconds 00000000000ed08f __float128 0f SECT 01 0000 [.text] _CailDetectECCSupport 00000000000ebe9c __float128 0f SECT 01 0000 [.text] _CailDisableBridgeASPM 00000000000eb64a __float128 0f SECT 01 0000 [.text] _CailDoTuneNorthBridge 00000000000ed366 __float128 0f SECT 01 0000 [.text] _CailEnableAspmOnOtherFunction 00000000000f9b22 __float128 0f SECT 01 0000 [.text] _CailEnterCriticalSection 00000000000ebc55 __float128 0f SECT 01 0000 [.text] _CailEvaluateEnginesState 00000000000ebd24 __float128 0f SECT 01 0000 [.text] _CailEvaluateNonEngineAsicState 00000000000ea66d __float128 0f SECT 01 0000 [.text] _CailFindAsicRevID 00000000000f006b __float128 0f SECT 01 0000 [.text] _CailGetCSBBufferSize 00000000000e90a0 __float128 0f SECT 01 0000 [.text] _CailGetCapsPointer 00000000000f439b __float128 0f SECT 01 0000 [.text] _CailGetEfuseBoxBitSetting 00000000000eb25d __float128 0f SECT 01 0000 [.text] _CailGetGfxDebugBarAddr 00000000000f3766 __float128 0f SECT 01 0000 [.text] _CailGetIndReg 00000000000e953b __float128 0f SECT 01 0000 [.text] _CailGetMasterOffsetToAgpCaps 00000000000f37bb __float128 0f SECT 01 0000 [.text] _CailGetPCIEIndReg 00000000000f39ef __float128 0f SECT 01 0000 [.text] _CailGetPCIEPortPReg 00000000000f4335 __float128 0f SECT 01 0000 [.text] _CailGetParserStaticBuffer 00000000000e9dda __float128 0f SECT 01 0000 [.text] _CailGetPhysicalAddressforSpringdale 00000000000f3b09 __float128 0f SECT 01 0000 [.text] _CailGetPifPhy0IndReg 00000000000f3c23 __float128 0f SECT 01 0000 [.text] _CailGetPifPhy1IndReg 00000000000f38d5 __float128 0f SECT 01 0000 [.text] _CailGetSmcIndReg 0000000000443e00 __float128 0f SECT 09 0000 [.data] _CailGodavariMetaDataList_CP_CE_PFP_ME 0000000000443e40 __float128 0f SECT 09 0000 [.data] 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00000000004b7790 __float128 0f SECT 09 0000 [.data] _CailKalindiMetaDataList_MEC1 00000000004b75d0 __float128 0f SECT 09 0000 [.data] _CailKalindiMetaDataList_SDMA0 00000000004b7690 __float128 0f SECT 09 0000 [.data] _CailKalindiMetaDataList_SDMA1 00000000000f9b4b __float128 0f SECT 01 0000 [.text] _CailLeaveCriticalSection 000000000010fe9d __float128 0f SECT 01 0000 [.text] _CailMonitorEngineInternalState 000000000010fa6d __float128 0f SECT 01 0000 [.text] _CailMonitorEngineReadWritePointers 0000000000110176 __float128 0f SECT 01 0000 [.text] _CailMonitorPerformanceCounter 00000000000ebdf9 __float128 0f SECT 01 0000 [.text] _CailPrepareUMASPInterleaving 00000000000e6ce9 __float128 0f SECT 01 0000 [.text] _CailQuerySpecificAsicCaps 00000000000f3db7 __float128 0f SECT 01 0000 [.text] _CailReadATIRegister 00000000000f42a0 __float128 0f SECT 01 0000 [.text] _CailReadDataFromFBBlock 00000000000f4294 __float128 0f SECT 01 0000 [.text] _CailReadFBData 00000000000f3f44 __float128 0f SECT 01 0000 [.text] _CailReadFBViaMmr 00000000000e954a __float128 0f SECT 01 0000 [.text] _CailReadInRealIDforVIA 00000000000f4324 __float128 0f SECT 01 0000 [.text] _CailReadMC 00000000000f43d9 __float128 0f SECT 01 0000 [.text] _CailReadMmPciConfigRegister 00000000000f42ef __float128 0f SECT 01 0000 [.text] _CailReadPCIConfigData 00000000000f4313 __float128 0f SECT 01 0000 [.text] _CailReadPLL 00000000000f4342 __float128 0f SECT 01 0000 [.text] _CailReadRcuIndData 00000000000f455f __float128 0f SECT 01 0000 [.text] _CailReadSamIndirectRegister 00000000000f4543 __float128 0f SECT 01 0000 [.text] _CailReadSamSabIndirectRegister 00000000000e8b89 __float128 0f SECT 01 0000 [.text] _CailReadinOverrideRegistrySetting 00000000000e8627 __float128 0f SECT 01 0000 [.text] _CailReadinRegistryFlags 00000000000f3ec0 __float128 0f SECT 01 0000 [.text] _CailReleaseLargeMemory 00000000000f3e30 __float128 0f SECT 01 0000 [.text] _CailReleaseMemory 000000000010fa07 __float128 0f SECT 01 0000 [.text] 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[.text] _Cail_Cypress_MonitorSPIPerformanceCounter 0000000000104871 __float128 0f SECT 01 0000 [.text] _Cail_Cypress_PCIELane_Switch 0000000000103cf9 __float128 0f SECT 01 0000 [.text] _Cail_Cypress_Powerdown 0000000000103cc5 __float128 0f SECT 01 0000 [.text] _Cail_Cypress_Powerup 0000000000103ac3 __float128 0f SECT 01 0000 [.text] _Cail_Cypress_QueryGUIStatus 0000000000103ad6 __float128 0f SECT 01 0000 [.text] _Cail_Cypress_RestoreAdapterCfgRegisters 0000000000103a65 __float128 0f SECT 01 0000 [.text] _Cail_Cypress_SelectSPIPerfCounterEvents 0000000000106de0 __float128 0f SECT 01 0000 [.text] _Cail_Cypress_SetGen2TLS 0000000000105ba0 __float128 0f SECT 01 0000 [.text] _Cail_Cypress_SetUvdVclkDclk 0000000000103a09 __float128 0f SECT 01 0000 [.text] _Cail_Cypress_SetupASIC 00000000001068d2 __float128 0f SECT 01 0000 [.text] _Cail_Cypress_SetupCgReferenceClock 0000000000105ada __float128 0f SECT 01 0000 [.text] _Cail_Cypress_SetupUvdCacheWindowsAndFwv 0000000000106aed __float128 0f SECT 01 0000 [.text] _Cail_Cypress_UpdateAsicInfBeforeQueried 0000000000104a30 __float128 0f SECT 01 0000 [.text] _Cail_Cypress_UpdateSwConstantForHwConfig 0000000000104be9 __float128 0f SECT 01 0000 [.text] _Cail_Cypress_UvdInit 0000000000105694 __float128 0f SECT 01 0000 [.text] _Cail_Cypress_UvdSuspend 0000000000103e05 __float128 0f SECT 01 0000 [.text] _Cail_Cypress_VPURecoveryBegin 00000000001044ca __float128 0f SECT 01 0000 [.text] _Cail_Cypress_VPURecoveryEnd 0000000000102c86 __float128 0f SECT 01 0000 [.text] _Cail_Cypress_WaitForIdle 0000000000102a28 __float128 0f SECT 01 0000 [.text] _Cail_Cypress_WaitForMCIdle_Setup 0000000000107cd3 __float128 0f SECT 01 0000 [.text] _Cail_Devastator_BlackoutMC 000000000010846c __float128 0f SECT 01 0000 [.text] _Cail_Devastator_Check_VCE_State 000000000010827b __float128 0f SECT 01 0000 [.text] _Cail_Devastator_DisableUvdGfxHandshaking 00000000001082e5 __float128 0f SECT 01 0000 [.text] _Cail_Devastator_EnableCGPG 00000000001082a8 __float128 0f SECT 01 0000 [.text] _Cail_Devastator_EnableDynamicMGPG 000000000010818d __float128 0f SECT 01 0000 [.text] _Cail_Devastator_EnableF32 000000000010842c __float128 0f SECT 01 0000 [.text] _Cail_Devastator_EnableLBPW 000000000010812d __float128 0f SECT 01 0000 [.text] _Cail_Devastator_GetClearStateAndRlcSaveRestoreRegisterListInfo 0000000000107d3b __float128 0f SECT 01 0000 [.text] _Cail_Devastator_GetGpuCounterOff 0000000000107d50 __float128 0f SECT 01 0000 [.text] _Cail_Devastator_GetIntegrateAsicFbMcBaseAddr 0000000000107bd5 __float128 0f SECT 01 0000 [.text] _Cail_Devastator_HardResetSX 0000000000107e86 __float128 0f SECT 01 0000 [.text] _Cail_Devastator_InitUvdClock 00000000001084fe __float128 0f SECT 01 0000 [.text] _Cail_Devastator_InitVceClock 000000000010869c __float128 0f SECT 01 0000 [.text] _Cail_Devastator_InitVceInternalClockGating 0000000000108322 __float128 0f SECT 01 0000 [.text] _Cail_Devastator_Init_LBPW 00000000001080b5 __float128 0f SECT 01 0000 [.text] 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00000000000f7399 __float128 0f SECT 01 0000 [.text] _Cail_MCILDecryptUVDFW 00000000000f6062 __float128 0f SECT 01 0000 [.text] _Cail_MCILDelayForVPURecover 00000000000f6043 __float128 0f SECT 01 0000 [.text] _Cail_MCILDelayInMicroSecond 00000000000f7a31 __float128 0f SECT 01 0000 [.text] _Cail_MCILDisableCAC 00000000000f5814 __float128 0f SECT 01 0000 [.text] _Cail_MCILEnableTdrClock 00000000000f52d0 __float128 0f SECT 01 0000 [.text] _Cail_MCILExit 00000000000f6500 __float128 0f SECT 01 0000 [.text] _Cail_MCILFreeMemory 00000000000f5417 __float128 0f SECT 01 0000 [.text] _Cail_MCILGetGraphicsDeviceTypes 00000000000f62f7 __float128 0f SECT 01 0000 [.text] _Cail_MCILGetRegistryString 00000000000f6182 __float128 0f SECT 01 0000 [.text] _Cail_MCILGetRegistryValue 00000000000f52c4 __float128 0f SECT 01 0000 [.text] _Cail_MCILInitialize 00000000000f7728 __float128 0f SECT 01 0000 [.text] _Cail_MCILInterlockedCompareExchange 00000000000f7750 __float128 0f SECT 01 0000 [.text] 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SECT 01 0000 [.text] _Cail_MCILReadPciCfgByBusNo 00000000000f6ec4 __float128 0f SECT 01 0000 [.text] _Cail_MCILReadReg 00000000000f5ec6 __float128 0f SECT 01 0000 [.text] _Cail_MCILReadRomImage 00000000000f63ad __float128 0f SECT 01 0000 [.text] _Cail_MCILSetRegistryString 00000000000f623e __float128 0f SECT 01 0000 [.text] _Cail_MCILSetRegistryValue 00000000000f5c7c __float128 0f SECT 01 0000 [.text] _Cail_MCILSyncExecute 00000000000f7aee __float128 0f SECT 01 0000 [.text] _Cail_MCILTrace0 00000000000f7af6 __float128 0f SECT 01 0000 [.text] _Cail_MCILTrace1 00000000000f7afe __float128 0f SECT 01 0000 [.text] _Cail_MCILTrace2 00000000000f5720 __float128 0f SECT 01 0000 [.text] _Cail_MCILTurnOnAsicBlock 00000000000f670b __float128 0f SECT 01 0000 [.text] _Cail_MCILUnlockMemory 00000000000f6979 __float128 0f SECT 01 0000 [.text] _Cail_MCILUnmapMemory 00000000000f6827 __float128 0f SECT 01 0000 [.text] _Cail_MCILUnmapVirtualFromGartSpace 00000000000f58bc __float128 0f SECT 01 0000 [.text] _Cail_MCILUpdateClockGating 00000000000f6a3f __float128 0f SECT 01 0000 [.text] _Cail_MCILWaitFor 00000000000f77d6 __float128 0f SECT 01 0000 [.text] _Cail_MCILWaitForFwLoadFinished 00000000000f5ac8 __float128 0f SECT 01 0000 [.text] _Cail_MCILWritePciCfg 00000000000f5e07 __float128 0f SECT 01 0000 [.text] _Cail_MCILWritePciCfgByBusNo 00000000000f6f81 __float128 0f SECT 01 0000 [.text] _Cail_MCILWriteReg 000000000010f5ef __float128 0f SECT 01 0000 [.text] _Cail_PCICfgResetMethod 000000000010f4f5 __float128 0f SECT 01 0000 [.text] _Cail_PCIeHotResetMethod 00000000000f9781 __float128 0f SECT 01 0000 [.text] _Cail_PerformPowerControl 00000000000f8ba1 __float128 0f SECT 01 0000 [.text] _Cail_PowerControl 00000000000e624b __float128 0f SECT 01 0000 [.text] _Cail_Powerdown 00000000000e5e8a __float128 0f SECT 01 0000 [.text] _Cail_Powerup 00000000000ea5e3 __float128 0f SECT 01 0000 [.text] _Cail_PreInit_AsicCaps 000000000010e241 __float128 0f SECT 01 0000 [.text] _Cail_Radeon_QueryGUIStatus 00000000000f9964 __float128 0f SECT 01 0000 [.text] _Cail_RestoreClockPowerGating 00000000000f71a8 __float128 0f SECT 01 0000 [.text] _Cail_RestoreFloatPointState 00000000000f70f4 __float128 0f SECT 01 0000 [.text] _Cail_SaveFloatPointState 00000000000f9be4 __float128 0f SECT 01 0000 [.text] _Cail_SearchStringForPattern 00000000000f0920 __float128 0f SECT 01 0000 [.text] _Cail_SearchTableInEasfBinary 00000000000ed479 __float128 0f SECT 01 0000 [.text] _Cail_SetSmuDfsBypassMode 0000000000110d14 __float128 0f SECT 01 0000 [.text] _Cail_Spectre_GetSmuFwVersion 0000000000110375 __float128 0f SECT 01 0000 [.text] _Cail_Spectre_InitCPJumpTable 0000000000110d23 __float128 0f SECT 01 0000 [.text] _Cail_Spectre_InitFunctionPointer 000000000011033f __float128 0f SECT 01 0000 [.text] _Cail_Spectre_InitSaveRestoreBuffer 0000000000110437 __float128 0f SECT 01 0000 [.text] _Cail_Spectre_InitializePowerGating 00000000001102e4 __float128 0f SECT 01 0000 [.text] _Cail_Spectre_IsVbiosPosted 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__float128 0f SECT 01 0000 [.text] _Cail_Sumo_SetAdditionalUvdDynamicClockModeParameter 000000000011170e __float128 0f SECT 01 0000 [.text] _Cail_Sumo_SetUvdVclkDclk 0000000000111ac3 __float128 0f SECT 01 0000 [.text] _Cail_Sumo_init_additional_registers 00000000001114a2 __float128 0f SECT 01 0000 [.text] _Cail_Sumo_ulNoBiosMemoryConfigAndSize 0000000000111b0e __float128 0f SECT 01 0000 [.text] _Cail_Tahiti_AsicState 0000000000116a23 __float128 0f SECT 01 0000 [.text] _Cail_Tahiti_CfCloseTemporaryMailBox 0000000000116ae8 __float128 0f SECT 01 0000 [.text] _Cail_Tahiti_CfGetP2PFlushCommand 00000000001161ed __float128 0f SECT 01 0000 [.text] _Cail_Tahiti_CfInitPeerAperture 0000000000116e07 __float128 0f SECT 01 0000 [.text] _Cail_Tahiti_CfInitXdmaAperture 000000000011697c __float128 0f SECT 01 0000 [.text] _Cail_Tahiti_CfOpenTemporaryMailBox 0000000000116831 __float128 0f SECT 01 0000 [.text] _Cail_Tahiti_CfSetPeerApertureDefault 0000000000116f77 __float128 0f SECT 01 0000 [.text] _Cail_Tahiti_CfSetXdmaApertureDefault 0000000000111cfe __float128 0f SECT 01 0000 [.text] _Cail_Tahiti_CheckAsicDowngradeInfo 0000000000116174 __float128 0f SECT 01 0000 [.text] _Cail_Tahiti_CheckCfAsicCfg 0000000000111c98 __float128 0f SECT 01 0000 [.text] _Cail_Tahiti_CheckFireGL 000000000011238e __float128 0f SECT 01 0000 [.text] _Cail_Tahiti_CheckMemoryConfiguration 0000000000116cea __float128 0f SECT 01 0000 [.text] _Cail_Tahiti_DetectECCSupport 0000000000117400 __float128 0f SECT 01 0000 [.text] _Cail_Tahiti_Disable_ASPM 00000000001129c3 __float128 0f SECT 01 0000 [.text] _Cail_Tahiti_EnableLBPW 0000000000117d45 __float128 0f SECT 01 0000 [.text] _Cail_Tahiti_EventNotification 00000000001160bd __float128 0f SECT 01 0000 [.text] _Cail_Tahiti_ExecuteDmaCopy 0000000000111b65 __float128 0f SECT 01 0000 [.text] _Cail_Tahiti_FindAsicRevID 0000000000116cb0 __float128 0f SECT 01 0000 [.text] _Cail_Tahiti_GetDoutScratch3 0000000000111ba9 __float128 0f SECT 01 0000 [.text] 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0000000000113e55 __float128 0f SECT 01 0000 [.text] _Cail_Tahiti_LiteResetEngine 00000000001122cf __float128 0f SECT 01 0000 [.text] _Cail_Tahiti_MemoryConfigAndSize 0000000000113bc7 __float128 0f SECT 01 0000 [.text] _Cail_Tahiti_MonitorEngineInternalState 0000000000113d6c __float128 0f SECT 01 0000 [.text] _Cail_Tahiti_MonitorLBPWPerformanceCounter 000000000011751f __float128 0f SECT 01 0000 [.text] _Cail_Tahiti_PCIELane_Switch 000000000011749c __float128 0f SECT 01 0000 [.text] _Cail_Tahiti_PCIELane_Switch_With_Workaround 0000000000116fd8 __float128 0f SECT 01 0000 [.text] _Cail_Tahiti_PCIELane_Switch_Workaround 0000000000112c5a __float128 0f SECT 01 0000 [.text] _Cail_Tahiti_Powerdown 0000000000112cf7 __float128 0f SECT 01 0000 [.text] _Cail_Tahiti_QueryGUIStatus 00000000001138b8 __float128 0f SECT 01 0000 [.text] _Cail_Tahiti_ResetHW 0000000000113843 __float128 0f SECT 01 0000 [.text] _Cail_Tahiti_RestoreAdapterCfgRegisters 000000000011746a __float128 0f SECT 01 0000 [.text] _Cail_Tahiti_Restore_ASPM 0000000000115770 __float128 0f SECT 01 0000 [.text] _Cail_Tahiti_SetSmcIndReg 0000000000114fa9 __float128 0f SECT 01 0000 [.text] _Cail_Tahiti_SetUvdVclkDclk 0000000000115f07 __float128 0f SECT 01 0000 [.text] _Cail_Tahiti_SetVceEvclkEcclk 0000000000112430 __float128 0f SECT 01 0000 [.text] _Cail_Tahiti_SetupASIC 0000000000111c70 __float128 0f SECT 01 0000 [.text] _Cail_Tahiti_SetupCgReferenceClock 00000000001150cb __float128 0f SECT 01 0000 [.text] _Cail_Tahiti_SetupUvdCacheWindowsAndFwv 0000000000117fe2 __float128 0f SECT 01 0000 [.text] _Cail_Tahiti_UpdateGbTilingModeTable 0000000000111bd6 __float128 0f SECT 01 0000 [.text] _Cail_Tahiti_UpdateSwConstantForHwConfig 0000000000112b4c __float128 0f SECT 01 0000 [.text] _Cail_Tahiti_UpdateVceInternalClockGating 0000000000114142 __float128 0f SECT 01 0000 [.text] _Cail_Tahiti_UvdInit 0000000000114bcc __float128 0f SECT 01 0000 [.text] _Cail_Tahiti_UvdSuspend 0000000000112d0a __float128 0f SECT 01 0000 [.text] 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000000000011e65b __float128 0f SECT 01 0000 [.text] _Cail_Tonga_InitRlcSaveRestoreList 000000000011e2ee __float128 0f SECT 01 0000 [.text] _Cail_Tonga_InitUvdClockGating 000000000011e48d __float128 0f SECT 01 0000 [.text] _Cail_Tonga_InitVceClockGating 00000000000ebfba __float128 0f SECT 01 0000 [.text] _Cail_UpdateAsicInfBeforeQueried 00000000000f04cb __float128 0f SECT 01 0000 [.text] _Cail_ValidateEasf 000000000010f619 __float128 0f SECT 01 0000 [.text] _Cail_ValidateLinkStatus 000000000010ed70 __float128 0f SECT 01 0000 [.text] _Cail_WaitFor 000000000010e891 __float128 0f SECT 01 0000 [.text] _Cail_WaitForMCIdle_Internal 00000000000e63a8 __float128 0f SECT 01 0000 [.text] _Cail_WriteAndReadI2C 00000000000efcf1 __float128 0f SECT 01 0000 [.text] _CalcClksClkv 00000000000efd73 __float128 0f SECT 01 0000 [.text] _CalcUPllClksClkv 00000000000efae2 __float128 0f SECT 01 0000 [.text] _CalcUpllDividers 00000000000efd9e __float128 0f SECT 01 0000 [.text] _CalcVcePllClksClkv 00000000000efe8a __float128 0f SECT 01 0000 [.text] _CalcVcepllDividers 000000000052c790 __float128 0f SECT 09 0000 [.data] _CallTable 00000000001210ce __float128 0f SECT 01 0000 [.text] _CallerDebugFunc 00000000003e3250 __float128 0f SECT 09 0000 [.data] _CapeVerdeFeatureSupport1 00000000003e6f40 __float128 0f SECT 09 0000 [.data] _CarrizoFeatureSupport1 00000000000fc6fb __float128 0f SECT 01 0000 [.text] _Carrizo_set_cpg_door_bell 000000000043b8a0 __float128 0f SECT 09 0000 [.data] _CaymanAddrConfigMask 000000000043d320 __float128 0f SECT 09 0000 [.data] _CaymanAsicStateRegInfo 000000000043d330 __float128 0f SECT 09 0000 [.data] _CaymanEngineRunningStateRegInfo 000000000043d7f0 __float128 0f SECT 09 0000 [.data] _CaymanHarvestRemapTbl 000000000043d090 __float128 0f SECT 09 0000 [.data] _Cayman_RLC 00000000000fef4b __float128 0f SECT 01 0000 [.text] _Cayman_restore_display 00000000000fe925 __float128 0f SECT 01 0000 [.text] _Cayman_save_display 00000000000ef7de __float128 0f SECT 01 0000 [.text] _CheckAPUForDualGraphicsBrandingSupport 000000000010e300 __float128 0f SECT 01 0000 [.text] _CheckForStereoConnector 000000000012292c __float128 0f SECT 01 0000 [.text] _CiBuffer_GetBuffer 000000000012286e __float128 0f SECT 01 0000 [.text] _CiBuffer_GetBufferSize 00000000000f9b09 __float128 0f SECT 01 0000 [.text] _ClearMemory 000000000012044a __float128 0f SECT 01 0000 [.text] _CommonDestinationDataTransformation 0000000000120497 __float128 0f SECT 01 0000 [.text] _CommonOperationDataTransformation 0000000000120408 __float128 0f SECT 01 0000 [.text] _CommonSourceDataTransformation 00000000000f86c8 __float128 0f SECT 01 0000 [.text] _ConvertFbOffsetToMcAddr 00000000000f872b __float128 0f SECT 01 0000 [.text] _ConvertMcAddrToFbOffset 00000000000edbb1 __float128 0f SECT 01 0000 [.text] _CopyDDI_CAPS 00000000000ece63 __float128 0f SECT 01 0000 [.text] _CopyFbToFbViaCpDma 00000000000ece16 __float128 0f SECT 01 0000 [.text] _CopyFbToRegisterViaCpDma 00000000000eccf6 __float128 0f SECT 01 0000 [.text] _CopyMcToMc 00000000000ecbc6 __float128 0f SECT 01 0000 [.text] _CopyVirtualToMc 00000000000f9eb5 __float128 0f SECT 01 0000 [.text] _CreateValidBitFieldMask 00000000003e1a10 __float128 0f SECT 09 0000 [.data] _CrossFireGroupTbl 00000000003e2210 __float128 0f SECT 09 0000 [.data] _CrossFireXDMAGroupTbl 000000000043de00 __float128 0f SECT 09 0000 [.data] _CypressAddrConfigMask 000000000043f358 __float128 0f SECT 09 0000 [.data] _CypressAsicStateRegInfo 000000000043f370 __float128 0f SECT 09 0000 [.data] _CypressEngineRunningStateRegInfo 0000000000440980 __float128 0f SECT 09 0000 [.data] _CypressHarvestRemapTbl 0000000000103d35 __float128 0f SECT 01 0000 [.text] _Cypress_LinkResetWorkaround 000000000043f1c0 __float128 0f SECT 09 0000 [.data] _Cypress_RLC 0000000000121360 __float128 0f SECT 01 0000 [.text] _DBGGetMask 0000000000121318 __float128 0f SECT 01 0000 [.text] _DBGMemoryCopy 0000000000121348 __float128 0f SECT 01 0000 [.text] _DBGReadReg 0000000000121330 __float128 0f SECT 01 0000 [.text] _DBGWriteReg 0000000000441b18 __float128 0f SECT 09 0000 [.data] _DEVASTATOR_GoldenSettings_A0 00000000001224d1 __float128 0f SECT 01 0000 [.text] _DebugTrigerFunction 00000000001210b4 __float128 0f SECT 01 0000 [.text] _DelayMicroseconds 000000000012109c __float128 0f SECT 01 0000 [.text] _DelayMilliseconds 000000000052c728 __float128 0f SECT 09 0000 [.data] _DestinationAlignmentShift 00000000004415d0 __float128 0f SECT 09 0000 [.data] _DevastatorEngineRunningStateRegInfo 00000000000ebf89 __float128 0f SECT 01 0000 [.text] _DisableUVDSupportCap 00000000000f27dd __float128 0f SECT 01 0000 [.text] _DummyCailAsicState 00000000000f2c09 __float128 0f SECT 01 0000 [.text] _DummyCailCalculateVirtualizationReservedOffset 00000000000f29a7 __float128 0f SECT 01 0000 [.text] _DummyCailCfCheckAsicCfg 00000000000f299c __float128 0f SECT 01 0000 [.text] _DummyCailCfCloseTemporaryMailBox 00000000000f2b11 __float128 0f SECT 01 0000 [.text] _DummyCailCfEnableMailbox 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[.text] _DummyCailEnterRlcSafeMode 00000000000f29f3 __float128 0f SECT 01 0000 [.text] _DummyCailEventNotification 00000000000f2943 __float128 0f SECT 01 0000 [.text] _DummyCailExecuteDmaCopy 00000000000f2bf2 __float128 0f SECT 01 0000 [.text] _DummyCailExitRlcSafeMode 00000000000f2c12 __float128 0f SECT 01 0000 [.text] _DummyCailFillMetaData 00000000000f274c __float128 0f SECT 01 0000 [.text] _DummyCailFindAsicRevisionID 00000000000f2a06 __float128 0f SECT 01 0000 [.text] _DummyCailFormatSmuDramDataBuffer 00000000000f2ae4 __float128 0f SECT 01 0000 [.text] _DummyCailFunctionLevelReset 00000000000f29c5 __float128 0f SECT 01 0000 [.text] _DummyCailGetDoutScratch3 00000000000f2c1a __float128 0f SECT 01 0000 [.text] _DummyCailGetFbMcBaseAddress 00000000000f279c __float128 0f SECT 01 0000 [.text] _DummyCailGetFbMemorySize 00000000000f27d5 __float128 0f SECT 01 0000 [.text] _DummyCailGetGbMacroTileMode 00000000000f27cd __float128 0f SECT 01 0000 [.text] _DummyCailGetGbTileMode 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[.text] _GetCfP2PBarNumber 00000000000eed45 __float128 0f SECT 01 0000 [.text] _GetCfPeerBusNoBitmap 00000000000eeda5 __float128 0f SECT 01 0000 [.text] _GetCfPeerDeviceNoBitmap 00000000000eee19 __float128 0f SECT 01 0000 [.text] _GetCfPeerGupIdBitmap 00000000000ee682 __float128 0f SECT 01 0000 [.text] _GetCfPeerMcBaseAddr 00000000000eecef __float128 0f SECT 01 0000 [.text] _GetCfPeerVirtualIndex 00000000000ef536 __float128 0f SECT 01 0000 [.text] _GetCfWriteCombineNumber 00000000000ee997 __float128 0f SECT 01 0000 [.text] _GetCfXdmaPeerMcBaseAddr 000000000011fabf __float128 0f SECT 01 0000 [.text] _GetCommandMasterTablePointer 00000000001203d2 __float128 0f SECT 01 0000 [.text] _GetDWordSrcIndex 000000000011fae5 __float128 0f SECT 01 0000 [.text] _GetDataMasterTablePointer 00000000000f9e76 __float128 0f SECT 01 0000 [.text] _GetDeltaAfterAlignment 000000000052c660 __float128 0f SECT 09 0000 [.data] _GetDestination 00000000000edb1e __float128 0f SECT 01 0000 [.text] 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[.data] _HAWAII_GoldenSettings_A0 00000000004473a0 __float128 0f SECT 09 0000 [.data] _HainanFeatureSupport1 00000000004499b0 __float128 0f SECT 09 0000 [.data] _HawaiiFeatureSupport1 000000000044ae00 __float128 0f SECT 09 0000 [.data] _HawaiiRbRepaireRemappingTbl_SE0_1 000000000044ae40 __float128 0f SECT 09 0000 [.data] _HawaiiRbRepaireRemappingTbl_SE2_3 000000000045a4f8 __float128 0f SECT 09 0000 [.data] _ICELAND_GoldenSettings_A0 0000000000459d60 __float128 0f SECT 09 0000 [.data] _IcelandAsicStateRegInfo 0000000000459d70 __float128 0f SECT 09 0000 [.data] _IcelandEngineRunningStateRegInfo 0000000000459a90 __float128 0f SECT 09 0000 [.data] _IcelandFeatureSupport1 00000000004599b0 __float128 0f SECT 09 0000 [.data] _IcelandMicroEngineRegisters 0000000000120153 __float128 0f SECT 01 0000 [.text] _IndirectIOCommand 0000000000120159 __float128 0f SECT 01 0000 [.text] _IndirectIOCommand_CLEAR 00000000001201fe __float128 0f SECT 01 0000 [.text] _IndirectIOCommand_MOVE_ATTR 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SECT 01 0000 [.text] _IsVCEIdle 00000000000f1f9b __float128 0f SECT 01 0000 [.text] _IsVbiosReservedBlockUsedFor 00000000004aa240 __float128 0f SECT 09 0000 [.data] _JUNIPER_GoldenSettings_A11 00000000004aa978 __float128 0f SECT 09 0000 [.data] _JUNIPER_GoldenSettings_A12 00000000004aa990 __float128 0f SECT 09 0000 [.data] _JuniperHarvestRemapTbl 00000000004a9b00 __float128 0f SECT 09 0000 [.data] _Juniper_RLC 00000000004b7ee0 __float128 0f SECT 09 0000 [.data] _KALINDI_GoldenSettings_A0_4882 00000000004b7920 __float128 0f SECT 09 0000 [.data] _KalindiFeatureSupport1 00000000004b0e70 __float128 0f SECT 09 0000 [.data] _Kalindi_CE_UCODE 00000000004b71d0 __float128 0f SECT 09 0000 [.data] _Kalindi_MEC1_UCODE 00000000004b3020 __float128 0f SECT 09 0000 [.data] _Kalindi_ME_UCODE 00000000004aecc0 __float128 0f SECT 09 0000 [.data] _Kalindi_PFP_UCODE 00000000004aba88 __float128 0f SECT 09 0000 [.data] _Kalindi_SDMA0_UCODE 00000000004acb18 __float128 0f SECT 09 0000 [.data] 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__float128 0f SECT 09 0000 [.data] _PITCAIRN_GoldenSettings_A12 000000000012226c __float128 0f SECT 01 0000 [.text] _ParseRequest 000000000011fb45 __float128 0f SECT 01 0000 [.text] _ParseTable 00000000004bd480 __float128 0f SECT 09 0000 [.data] _PitcairnFeatureSupport1 00000000004be120 __float128 0f SECT 09 0000 [.data] _PitcairnRbRepaireRemappingTbl 00000000001210c8 __float128 0f SECT 01 0000 [.text] _PostCharOutput 00000000003e2ea0 __float128 0f SECT 09 0000 [.data] _PowerCtrlRegisterDefaultTbl 0000000000120902 __float128 0f SECT 01 0000 [.text] _ProcessADD 000000000012065a __float128 0f SECT 01 0000 [.text] _ProcessAnd 0000000000120b8f __float128 0f SECT 01 0000 [.text] _ProcessClear 000000000011f97f __float128 0f SECT 01 0000 [.text] _ProcessCommandProperties 0000000000120b0c __float128 0f SECT 01 0000 [.text] _ProcessCompare 0000000000120a8f __float128 0f SECT 01 0000 [.text] _ProcessDIV 0000000000120f6a __float128 0f SECT 01 0000 [.text] _ProcessDS 0000000000120f3d __float128 0f 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00000000000f8002 __float128 0f SECT 01 0000 [.text] _QueryMCAddressRange 00000000000f805a __float128 0f SECT 01 0000 [.text] _QueryMCAddressRangeInfo 00000000000f98ff __float128 0f SECT 01 0000 [.text] _QueryPowerControlRestoreAction 000000000010ee34 __float128 0f SECT 01 0000 [.text] _R6cail_ulWalkTable 00000000004c1580 __float128 0f SECT 09 0000 [.data] _REDWOOD_GoldenSettings_A11 00000000000db040 __float128 0f SECT 01 0000 [.text] _RadeonCheckAGPMaxIdlestatus 000000000010e408 __float128 0f SECT 01 0000 [.text] _RadeonCheckAdapterFireGLBoard 000000000010ee3c __float128 0f SECT 01 0000 [.text] _Radeoncail_GenerateDualGraphicsBrandingNameString 000000000010ed03 __float128 0f SECT 01 0000 [.text] _Radeoncail_GetAdapterString 000000000010eb73 __float128 0f SECT 01 0000 [.text] _Radeoncail_GetChipType 000000000010e997 __float128 0f SECT 01 0000 [.text] _Radeoncail_GetDeviceDescription 000000000012125c __float128 0f SECT 01 0000 [.text] _ReadFrameBuffer32 000000000052c5b0 __float128 0f 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SECT 01 0000 [.text] _ReadSysIOReg8 00000000004c0f80 __float128 0f SECT 09 0000 [.data] _Redwood_RLC 00000000000eda4c __float128 0f SECT 01 0000 [.text] _ReinitializeCapTblManager 00000000000f7c60 __float128 0f SECT 01 0000 [.text] _ReleaseMCAddressRange 00000000001212ad __float128 0f SECT 01 0000 [.text] _ReleaseMemory 0000000000122238 __float128 0f SECT 01 0000 [.text] _ReleaseRequest 00000000000ef5a0 __float128 0f SECT 01 0000 [.text] _RemapRenderBackend 00000000000f87ee __float128 0f SECT 01 0000 [.text] _ReserveFbMcAddressRange 00000000000f7d2a __float128 0f SECT 01 0000 [.text] _ReserveMCAddressRange 00000000000f1fd4 __float128 0f SECT 01 0000 [.text] _RestoreVbiosReservedBlockData 000000000052ecb0 __float128 0f SECT 0a 0000 [__DATA.__common] _RoundKey 0000000000442040 __float128 0f SECT 09 0000 [.data] _SCRAPPER_GoldenSettings_A0 0000000000094a7f __float128 0f SECT 01 0000 [.text] _SI_InitHwWorkAroundFlags 00000000004c1eb0 __float128 0f SECT 09 0000 [.data] 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[.text] _SiBuffer_GetBuffer 00000000001226cd __float128 0f SECT 01 0000 [.text] _SiBuffer_GetBufferSize 00000000004d5430 __float128 0f SECT 09 0000 [.data] _SiCpGfxResetRegisterSavingTbl 0000000000122d2e __float128 0f SECT 01 0000 [.text] _SiPacket_ClearState 0000000000122c7f __float128 0f SECT 01 0000 [.text] _SiPacket_ContextControl 0000000000122c20 __float128 0f SECT 01 0000 [.text] _SiPacket_PreambleCntl 0000000000122d0b __float128 0f SECT 01 0000 [.text] _SiPacket_SetOneContextReg 0000000000122cd9 __float128 0f SECT 01 0000 [.text] _SiPacket_SetSeqContextRegs 0000000000122d6f __float128 0f SECT 01 0000 [.text] _SiPacket_SizeClearState 0000000000122cce __float128 0f SECT 01 0000 [.text] _SiPacket_SizeContextControl 0000000000122c74 __float128 0f SECT 01 0000 [.text] _SiPacket_SizePreambleCntl 0000000000122d23 __float128 0f SECT 01 0000 [.text] _SiPacket_SizeSetOneContextReg 0000000000122d02 __float128 0f SECT 01 0000 [.text] _SiPacket_SizeSetSeqContextRegs 00000000004d53e0 __float128 0f SECT 09 0000 [.data] _SiTcpChanSteerLo 000000000052c690 __float128 0f SECT 09 0000 [.data] _SkipDestination 00000000001200d9 __float128 0f SECT 01 0000 [.text] _SkipParameters16 00000000001200f7 __float128 0f SECT 01 0000 [.text] _SkipParameters8 000000000052c720 __float128 0f SECT 09 0000 [.data] _SourceAlignmentShift 00000000004c1620 __float128 0f SECT 09 0000 [.data] _SpectreFeatureSupport1 0000000000110a9d __float128 0f SECT 01 0000 [.text] _Spectre_ResetEventNotificationManager 00000000000f9d85 __float128 0f SECT 01 0000 [.text] _StringCompare 00000000000f9d42 __float128 0f SECT 01 0000 [.text] _StringConcatenate 00000000000f9d0b __float128 0f SECT 01 0000 [.text] _StringCopy 00000000000f9db1 __float128 0f SECT 01 0000 [.text] _StringToUlong 00000000004d2d98 __float128 0f SECT 09 0000 [.data] _StrippedSUMO_GoldenSettings_A11 00000000004d3020 __float128 0f SECT 09 0000 [.data] _SumoHarvestRemapTbl 00000000004d25c0 __float128 0f SECT 09 0000 [.data] _Sumo_RLC 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[.data] _TongaEngineRunningStateRegInfo 00000000004d7800 __float128 0f SECT 09 0000 [.data] _TongaFeatureSupport1 00000000004d7740 __float128 0f SECT 09 0000 [.data] _TongaMicroEngineRegisters 000000000052c200 __float128 0f SECT 09 0000 [.data] _Turks_RLC 0000000000094e6e __float128 0f SECT 01 0000 [.text] _UBMAAResolve 0000000000094f3b __float128 0f SECT 01 0000 [.text] _UBMAATextOut 0000000000094e45 __float128 0f SECT 01 0000 [.text] _UBMClear 000000000009505a __float128 0f SECT 01 0000 [.text] _UBMClearStateInit 0000000000095031 __float128 0f SECT 01 0000 [.text] _UBMColorTransform 0000000000094ee9 __float128 0f SECT 01 0000 [.text] _UBMCompress 0000000000095071 __float128 0f SECT 01 0000 [.text] _UBMComputeStateInit 0000000000094bde __float128 0f SECT 01 0000 [.text] _UBMCreate 0000000000094fb6 __float128 0f SECT 01 0000 [.text] _UBMDesktopComposition 0000000000094d1f __float128 0f SECT 01 0000 [.text] _UBMDestroy 0000000000094d35 __float128 0f SECT 01 0000 [.text] _UBMDeviceCreate 0000000000094d62 __float128 0f SECT 01 0000 [.text] _UBMDeviceDestroy 0000000000094d4c __float128 0f SECT 01 0000 [.text] _UBMDeviceTrim 0000000000094ec0 __float128 0f SECT 01 0000 [.text] _UBMExpand 0000000000094d78 __float128 0f SECT 01 0000 [.text] _UBMGPULoadShaders 0000000000094dca __float128 0f SECT 01 0000 [.text] _UBMGenMips 0000000000094e1c __float128 0f SECT 01 0000 [.text] _UBMGenZRangeMip 0000000000094df3 __float128 0f SECT 01 0000 [.text] _UBMGenZRangeTex 0000000000094f12 __float128 0f SECT 01 0000 [.text] _UBMGradient 0000000000094f8d __float128 0f SECT 01 0000 [.text] _UBMMemcpy 0000000000094f64 __float128 0f SECT 01 0000 [.text] _UBMMemset 0000000000094e97 __float128 0f SECT 01 0000 [.text] _UBMMlaaResolve 0000000000095088 __float128 0f SECT 01 0000 [.text] _UBMNotifyShadowMemoryInfo 0000000000095008 __float128 0f SECT 01 0000 [.text] _UBMPartialUpload 0000000000094da1 __float128 0f SECT 01 0000 [.text] _UBMStretch 0000000000094fdf __float128 0f SECT 01 0000 [.text] _UBMSurfaceCopy 0000000000094d09 __float128 0f SECT 01 0000 [.text] _UBMTrim 00000000000f1f8d __float128 0f SECT 01 0000 [.text] _UnsetVbiosReservedBlockFlag 00000000000edb47 __float128 0f SECT 01 0000 [.text] _UpdateRegGroupActiveMode 0000000000122b05 __float128 0f SECT 01 0000 [.text] _ViBuffer_GetBuffer 0000000000122a47 __float128 0f SECT 01 0000 [.text] _ViBuffer_GetBufferSize 00000000004d35e0 __float128 0f SECT 09 0000 [.data] _WCB_NUM_TAHITI 0000000000121814 __float128 0f SECT 01 0000 [.text] _WaitClockAndDataChanged 00000000001217c1 __float128 0f SECT 01 0000 [.text] _WaitClockOrDataChanged 00000000000eb845 __float128 0f SECT 01 0000 [.text] _WaitForIdle 00000000000f242f __float128 0f SECT 01 0000 [.text] _WaitForLoadUcodeComplete 00000000004d3008 __float128 0f SECT 09 0000 [.data] _Wrestler_GoldenSettings_A11 0000000000121276 __float128 0f SECT 01 0000 [.text] _WriteFrameBuffer32 000000000052c530 __float128 0f SECT 09 0000 [.data] _WriteIOFunctions 000000000012213f __float128 0f SECT 01 0000 [.text] _WriteIORequest 0000000000121232 __float128 0f SECT 01 0000 [.text] _WriteIndReg32 00000000001212d6 __float128 0f SECT 01 0000 [.text] _WriteMC32 0000000000122010 __float128 0f SECT 01 0000 [.text] _WriteMemoryRequest 000000000052c4f0 __float128 0f SECT 09 0000 [.data] _WritePCIFunctions 0000000000121171 __float128 0f SECT 01 0000 [.text] _WritePCIReg16 0000000000121191 __float128 0f SECT 01 0000 [.text] _WritePCIReg32 0000000000121151 __float128 0f SECT 01 0000 [.text] _WritePCIReg8 0000000000121301 __float128 0f SECT 01 0000 [.text] _WritePLL32 0000000000121e6f __float128 0f SECT 01 0000 [.text] _WriteParserTempData 00000000001211ef __float128 0f SECT 01 0000 [.text] _WriteReg32 0000000000121256 __float128 0f SECT 01 0000 [.text] _WriteRegIO 00000000001211cf __float128 0f SECT 01 0000 [.text] _WriteSysIOReg16 00000000001211d5 __float128 0f SECT 01 0000 [.text] _WriteSysIOReg32 00000000001211c9 __float128 0f SECT 01 0000 [.text] _WriteSysIOReg8 00000000000ecd4c __float128 0f SECT 01 0000 [.text] _WriteToFbOffsetByHdp 00000000000d59f8 __float128 0f SECT 01 0000 [.text] AddrCIHwlInit(AddrClient const*) 00000000000d349c __float128 0f SECT 01 0000 [.text] AddrSIHwlInit(AddrClient const*) 000000000009ffd4 __float128 0f SECT 01 0000 [.text] GetMonitorDesc(_UBM_PACKED_PIXEL_TYPE) 00000000000d1a6c __float128 0f SECT 01 0000 [.text] AddrR800HwlInit(AddrClient const*) 00000000000bc2d3 __float128 0f SECT 01 0000 [.text] SiBltResFmtInit() 0000000000025078 __float128 0f SECT 01 0000 [.text] klogSetLogLevel(_eLOG_LEVEL_MODULE, unsigned int) 00000000000a7660 __float128 0f SECT 01 0000 [.text] SurfAttributeInit() 0000000000025067 __float128 0f SECT 01 0000 [.text] klogFreeLogLevels() 0000000000024f61 __float128 0f SECT 01 0000 [.text] klogInitLogLevels(IORegistryEntry*) 000000000002508a __float128 0f SECT 01 0000 [.text] klogUnsetLogLevel(_eLOG_LEVEL_MODULE, unsigned int) 00000000000cb244 __float128 0f SECT 01 0000 [.text] SiSurfAttributeInit() 00000000000b4694 __float128 0f SECT 01 0000 [.text] SiHwlInit() 00000000000cd65e __float128 0f SECT 01 0000 [.text] AddrObject::ClientFree(void*, AddrClient const*) 00000000000cd5ce __float128 0f SECT 01 0000 [.text] AddrObject::ClientAlloc(unsigned long, AddrClient const*) 00000000000cd4e6 __float128 0f SECT 01 0000 [.text] AddrObject::AddrObject(AddrClient const*) 00000000000cd486 __float128 0f SECT 01 0000 [.text] AddrObject::AddrObject() 00000000000cd516 __float128 0f SECT 01 0000 [.text] AddrObject::AddrObject(AddrClient const*) 00000000000cd4b6 __float128 0f SECT 01 0000 [.text] AddrObject::AddrObject() 00000000000cd546 __float128 0f SECT 01 0000 [.text] AddrObject::~AddrObject() 00000000000cd5c2 __float128 0f SECT 01 0000 [.text] AddrObject::~AddrObject() 00000000000cd5c8 __float128 0f SECT 01 0000 [.text] AddrObject::~AddrObject() 00000000000cd584 __float128 0f SECT 01 0000 [.text] AddrObject::operator delete(void*) 00000000000cd720 __float128 0f SECT 01 0000 [.text] AddrObject::operator delete(void*, AddrClient const*) 00000000000cd6d8 __float128 0f SECT 01 0000 [.text] AddrObject::operator new(unsigned long, AddrClient const*) 0000000000096a6e __float128 0f SECT 01 0000 [.text] AuxSurfMgr::EvictEntry(CachedAuxSurf*, unsigned int) 00000000000956c2 __float128 0f SECT 01 0000 [.text] AuxSurfMgr::GetHiSSurf(_UBM_SURFINFO const*, _UBM_SURFINFO**) 0000000000095350 __float128 0f SECT 01 0000 [.text] AuxSurfMgr::GenerateKey(_UBM_SURFINFO const*, unsigned int) 0000000000095970 __float128 0f SECT 01 0000 [.text] AuxSurfMgr::GetGradSurf(_UBM_SURFINFO const*, _UBM_SURFINFO**) 00000000000958a2 __float128 0f SECT 01 0000 [.text] AuxSurfMgr::GetPixPreSurf(_UBM_SURFINFO const*, _UBM_SURFINFO**) 00000000000957d6 __float128 0f SECT 01 0000 [.text] AuxSurfMgr::GetEdgeMaskSurf(_UBM_SURFINFO const*, _UBM_SURFINFO**) 000000000009609e __float128 0f SECT 01 0000 [.text] AuxSurfMgr::UpdateTimestamp() 00000000000960b2 __float128 0f SECT 01 0000 [.text] AuxSurfMgr::DestroyResources() 0000000000095560 __float128 0f SECT 01 0000 [.text] AuxSurfMgr::GetOffsetTexSurf(_UBM_SURFINFO const*, _UBM_SURFINFO**) 0000000000095390 __float128 0f SECT 01 0000 [.text] AuxSurfMgr::FindCachedAuxSurf(unsigned int, CachedAuxSurf**, unsigned int*) 0000000000095a42 __float128 0f SECT 01 0000 [.text] AuxSurfMgr::GetAdvAaDepthSurf(_UBM_SURFINFO const*, _UBM_SURFINFO**) 0000000000095288 __float128 0f SECT 01 0000 [.text] AuxSurfMgr::GetCmaskAsTexSurf(_UBM_SURFINFO const*, _UBM_SURFINFO**) 0000000000095462 __float128 0f SECT 01 0000 [.text] AuxSurfMgr::GetFmaskAsTexSurf(_UBM_SURFINFO const*, _UBM_SURFINFO**) 0000000000095e3c __float128 0f SECT 01 0000 [.text] AuxSurfMgr::GetHTileOffsetSurf(_UBM_SURFINFO const*, _UBM_SURFINFO const*, _UBM_SURFINFO**) 0000000000095c80 __float128 0f SECT 01 0000 [.text] AuxSurfMgr::GetMlaaSepEdgeSurf(_UBM_SURFINFO const*, _UBM_SURFINFO**) 00000000000955fc __float128 0f SECT 01 0000 [.text] AuxSurfMgr::GetHtileAsColorSurf(_UBM_SURFINFO const*, _UBM_SURFINFO**) 0000000000095f64 __float128 0f SECT 01 0000 [.text] AuxSurfMgr::GetHtileMappingSurf(_UBM_SURFINFO const*, _UBM_SURFINFO const*, _UBM_SURFINFO**) 0000000000095bb8 __float128 0f SECT 01 0000 [.text] AuxSurfMgr::GetNeighborMaskSurf(_UBM_SURFINFO const*, _UBM_SURFINFO**) 0000000000095d52 __float128 0f SECT 01 0000 [.text] AuxSurfMgr::GetMlaaEdgeCountSurf(_UBM_SURFINFO const*, _UBM_SURFINFO**, MlaaEdgeCountSurfDesc) 0000000000096aac __float128 0f SECT 01 0000 [.text] AuxSurfMgr::HwlGenerateFmaskTexKey(_UBM_SURFINFO const*) 0000000000096ae0 __float128 0f SECT 01 0000 [.text] AuxSurfMgr::HwlGenerateOffsetTexKey(_UBM_SURFINFO const*) 0000000000095f26 __float128 0f SECT 01 0000 [.text] AuxSurfMgr::GenerateHtileOffsetTexKey(_UBM_SURFINFO const*, _UBM_SURFINFO const*) 0000000000096058 __float128 0f SECT 01 0000 [.text] AuxSurfMgr::GenerateHtileMappingTexKey(_UBM_SURFINFO const*, _UBM_SURFINFO const*) 0000000000095272 __float128 0f SECT 01 0000 [.text] AuxSurfMgr::Init(BltMgr*) 0000000000096950 __float128 0f SECT 01 0000 [.text] AuxSurfMgr::GrowArray(CachedAuxSurf**, unsigned int*) 000000000009509e __float128 0f SECT 01 0000 [.text] AuxSurfMgr::AuxSurfMgr() 000000000052e968 __float128 0f SECT 0a 0000 [__DATA.__common] AMDVIHWGart::gMetaClass 00000000003b9908 __float128 0f SECT 08 0000 [.const_data] AMDVIHWGart::superClass 00000000000872b2 __float128 0f SECT 01 0000 [.text] AMDVIHWGart::updatePageTable(IOMemoryDescriptor*, unsigned long long, _eOP_ORIGINATOR, _eOP_TYPE, bool, bool) 0000000000087120 __float128 0f SECT 01 0000 [.text] AMDVIHWGart::MetaClass::MetaClass() 00000000000871e0 __float128 0f SECT 01 0000 [.text] AMDVIHWGart::MetaClass::MetaClass() 00000000003b9900 __float128 0f SECT 08 0000 [.const_data] AMDVIHWGart::metaClass 000000000008717c __float128 0f SECT 01 0000 [.text] AMDVIHWGart::AMDVIHWGart(OSMetaClass const*) 0000000000087252 __float128 0f SECT 01 0000 [.text] AMDVIHWGart::AMDVIHWGart() 000000000008715c __float128 0f SECT 01 0000 [.text] AMDVIHWGart::AMDVIHWGart(OSMetaClass const*) 0000000000087282 __float128 0f SECT 01 0000 [.text] AMDVIHWGart::AMDVIHWGart() 00000000000871b0 __float128 0f SECT 01 0000 [.text] AMDVIHWGart::~AMDVIHWGart() 00000000000871a6 __float128 0f SECT 01 0000 [.text] AMDVIHWGart::~AMDVIHWGart() 000000000008719c __float128 0f SECT 01 0000 [.text] AMDVIHWGart::~AMDVIHWGart() 00000000000d1a58 __float128 0f SECT 01 0000 [.text] AddrElemLib::IsExpand3x(_AddrFormat) 00000000000d165e __float128 0f SECT 01 0000 [.text] AddrElemLib::GetCompBits(unsigned int, unsigned int, unsigned int, unsigned int, ADDR_PIXEL_FORMATINFO*, AddrElemMode) 00000000000d146c __float128 0f SECT 01 0000 [.text] AddrElemLib::GetCompSwap(_AddrSurfaceSwap, ADDR_PIXEL_FORMATINFO*) 00000000000d1270 __float128 0f SECT 01 0000 [.text] AddrElemLib::GetCompType(_AddrColorFormat, _AddrSurfaceNumber, ADDR_PIXEL_FORMATINFO*) 00000000000d1a36 __float128 0f SECT 01 0000 [.text] AddrElemLib::IsCompressed(_AddrFormat) 00000000000d0b3a __float128 0f SECT 01 0000 [.text] AddrElemLib::Int32sToPixel(unsigned int, unsigned int*, unsigned int*, unsigned int*, ADDR_COMPONENT_FLAGS, unsigned int, signed char*) 00000000000d19ca __float128 0f SECT 01 0000 [.text] AddrElemLib::SetClearComps(ADDR_FLT_32*, int, int) 00000000000d0988 __float128 0f SECT 01 0000 [.text] AddrElemLib::Flt32sToInt32s(ADDR_FLT_32, unsigned int, AddrNumberType, unsigned int*) 00000000000d1950 __float128 0f SECT 01 0000 [.text] AddrElemLib::GetBitsPerPixel(_AddrFormat, AddrElemMode*, unsigned int*, unsigned int*, unsigned int*) 00000000000d1738 __float128 0f SECT 01 0000 [.text] AddrElemLib::AdjustSurfaceInfo(AddrElemMode, unsigned int, unsigned int, unsigned int*, unsigned int*, unsigned int*, unsigned int*) 00000000000d1a24 __float128 0f SECT 01 0000 [.text] AddrElemLib::IsBlockCompressed(_AddrFormat) 00000000000d1880 __float128 0f SECT 01 0000 [.text] AddrElemLib::RestoreSurfaceInfo(AddrElemMode, unsigned int, unsigned int, unsigned int*, unsigned int*, unsigned int*) 00000000000d0952 __float128 0f SECT 01 0000 [.text] AddrElemLib::Create(AddrLib const*) 00000000000d1638 __float128 0f SECT 01 0000 [.text] AddrElemLib::SwapComps(unsigned int, unsigned int, ADDR_PIXEL_FORMATINFO*) 00000000000d08ac __float128 0f SECT 01 0000 [.text] AddrElemLib::AddrElemLib(AddrLib*) 00000000000d08b6 __float128 0f SECT 01 0000 [.text] AddrElemLib::AddrElemLib(AddrLib*) 00000000000d0922 __float128 0f SECT 01 0000 [.text] AddrElemLib::~AddrElemLib() 00000000000d093e __float128 0f SECT 01 0000 [.text] AddrElemLib::~AddrElemLib() 00000000000d0948 __float128 0f SECT 01 0000 [.text] AddrElemLib::~AddrElemLib() 00000000000d210a __float128 0f SECT 01 0000 [.text] R800AddrLib::HwlInitGlobalParams(_ADDR_CREATE_INPUT const*) 00000000000d22f4 __float128 0f SECT 01 0000 [.text] R800AddrLib::HwlConvertChipFamily(unsigned int, unsigned int) 00000000000d1ad0 __float128 0f SECT 01 0000 [.text] R800AddrLib::R800AddrLib(AddrClient const*) 00000000000d1b1e __float128 0f SECT 01 0000 [.text] R800AddrLib::R800AddrLib(AddrClient const*) 00000000000d1b6c __float128 0f SECT 01 0000 [.text] R800AddrLib::~R800AddrLib() 00000000000d1b88 __float128 0f SECT 01 0000 [.text] R800AddrLib::~R800AddrLib() 00000000000d1b92 __float128 0f SECT 01 0000 [.text] R800AddrLib::~R800AddrLib() 00000000000ac56a __float128 0f SECT 01 0000 [.text] SiBltDevice::HwlDestroy() 00000000000adf50 __float128 0f SECT 01 0000 [.text] SiBltDevice::SetSeqRegs(unsigned int, unsigned int, unsigned int const*, unsigned int) 00000000000aed78 __float128 0f SECT 01 0000 [.text] SiBltDevice::WriteCpDma(void*, LARGE_INTEGER, _CPDMA_ADDR_SPACE, _CPDMA_SRC_SEL, _CPDMA_DST_SEL, unsigned int, void*, LARGE_INTEGER, _CPDMA_ADDR_SPACE, unsigned int, unsigned int, unsigned int, unsigned int) 00000000000adefe __float128 0f SECT 01 0000 [.text] SiBltDevice::SetOneShReg(unsigned int, unsigned int, PM4ShaderType) 00000000000ae00a __float128 0f SECT 01 0000 [.text] SiBltDevice::SetSeqShRegs(unsigned int, unsigned int*, unsigned int, PM4ShaderType) 00000000000ada48 __float128 0f SECT 01 0000 [.text] SiBltDevice::WaitOnCsDone() 00000000000ac9c4 __float128 0f SECT 01 0000 [.text] SiBltDevice::Init3dDrawBlt(BltInfo*) 00000000000ac67e __float128 0f SECT 01 0000 [.text] SiBltDevice::InitBltCommon(BltInfo*) 00000000000ac8ba __float128 0f SECT 01 0000 [.text] SiBltDevice::WriteVgtEvent(unsigned int) 00000000000ae076 __float128 0f SECT 01 0000 [.text] SiBltDevice::SetShRegOffset(unsigned int, unsigned int, unsigned int, PM4ShaderType) 00000000000ae57c __float128 0f SECT 01 0000 [.text] SiBltDevice::WritePfpSyncMe() 00000000000aed16 __float128 0f SECT 01 0000 [.text] SiBltDevice::WriteSkipIfEnd(unsigned int*) 00000000000ad712 __float128 0f SECT 01 0000 [.text] SiBltDevice::WriteWriteData(void*, LARGE_INTEGER, unsigned int const*, unsigned int, unsigned int, unsigned int, unsigned int, unsigned int) 00000000000ac984 __float128 0f SECT 01 0000 [.text] SiBltDevice::SetOneConfigReg(unsigned int, unsigned int) 00000000000adb08 __float128 0f SECT 01 0000 [.text] SiBltDevice::WriteReleaseMem(void*, LARGE_INTEGER, unsigned int, unsigned int) 00000000000b2082 __float128 0f SECT 01 0000 [.text] SiBltDevice::WriteSdamNopCmd() 00000000000b0c16 __float128 0f SECT 01 0000 [.text] SiBltDevice::WriteSdmaKeyCmd(unsigned char const*, unsigned char const*) 00000000000ad966 __float128 0f SECT 01 0000 [.text] SiBltDevice::WriteWaitRegMem(void*, LARGE_INTEGER, unsigned int) 00000000000ade7c __float128 0f SECT 01 0000 [.text] SiBltDevice::IsValidConfigReg(unsigned int) 00000000000ae6c2 __float128 0f SECT 01 0000 [.text] SiBltDevice::LoadShadowShRegs(PM4ShaderType) 00000000000adebe __float128 0f SECT 01 0000 [.text] SiBltDevice::SetOneContextReg(unsigned int, unsigned int) 00000000000ac944 __float128 0f SECT 01 0000 [.text] SiBltDevice::SetOneUConfigReg(unsigned int, unsigned int) 00000000000b0cee __float128 0f SECT 01 0000 [.text] SiBltDevice::SizeDrmDmaKeyCmd() 00000000000ae35c __float128 0f SECT 01 0000 [.text] SiBltDevice::WriteCondExecCmd(void*, LARGE_INTEGER, unsigned int) 00000000000af200 __float128 0f SECT 01 0000 [.text] SiBltDevice::WritePredExecCmd(unsigned int, unsigned int) 00000000000aec72 __float128 0f SECT 01 0000 [.text] SiBltDevice::WriteSkipIfStart(void*, unsigned int, unsigned int, unsigned int) 00000000000adca8 __float128 0f SECT 01 0000 [.text] SiBltDevice::WriteSurfaceSync(void*, LARGE_INTEGER, CP_COHER_CNTL, LARGE_INTEGER) 00000000000ad518 __float128 0f SECT 01 0000 [.text] SiBltDevice::Init3dDispatchBlt(BltInfo*) 00000000000ade94 __float128 0f SECT 01 0000 [.text] SiBltDevice::IsValidUConfigReg(unsigned int) 00000000000adfa4 __float128 0f SECT 01 0000 [.text] SiBltDevice::SetSeqContextRegs(unsigned int, unsigned int const*, unsigned int) 00000000000ae42e __float128 0f SECT 01 0000 [.text] SiBltDevice::WriteCondWriteCmd(void*, LARGE_INTEGER, LARGE_INTEGER, unsigned int, unsigned int, unsigned int, unsigned int, unsigned int, unsigned int) 00000000000b0cfa __float128 0f SECT 01 0000 [.text] SiBltDevice::WriteDrmDmaKeyCmd(unsigned char const*, unsigned char const*) 00000000000ae996 __float128 0f SECT 01 0000 [.text] SiBltDevice::WriteNumInstances(unsigned int) 00000000000ae8b0 __float128 0f SECT 01 0000 [.text] SiBltDevice::WritePreambleCntl(unsigned int) 00000000000ae7ee __float128 0f SECT 01 0000 [.text] SiBltDevice::LoadUserConfigRegs() 00000000000ae94c __float128 0f SECT 01 0000 [.text] SiBltDevice::WriteClearStateCmd() 00000000000ae29e __float128 0f SECT 01 0000 [.text] SiBltDevice::WriteCondExecCmdCI(void*, LARGE_INTEGER, unsigned int) 00000000000b0e60 __float128 0f SECT 01 0000 [.text] SiBltDevice::WriteSdmaOffsetCmd(unsigned int) 00000000000b0eca __float128 0f SECT 01 0000 [.text] SiBltDevice::SizeDrmDmaOffsetCmd() 00000000000acac2 __float128 0f SECT 01 0000 [.text] SiBltDevice::Write3dDrawPreamble() 00000000000ac746 __float128 0f SECT 01 0000 [.text] SiBltDevice::WriteCommonPreamble() 00000000000aec0a __float128 0f SECT 01 0000 [.text] SiBltDevice::WriteContextControl(unsigned int, unsigned int, unsigned int, unsigned int) 00000000000b0d7c __float128 0f SECT 01 0000 [.text] SiBltDevice::WriteSdmaCounterCmd(unsigned char const*) 00000000000b0df8 __float128 0f SECT 01 0000 [.text] SiBltDevice::SizeDrmDmaCounterCmd() 00000000000ae110 __float128 0f SECT 01 0000 [.text] SiBltDevice::WriteDrawPreambleCmd(VGT_PRIMITIVE_TYPE, IA_MULTI_VGT_PARAM) 00000000000b0ed6 __float128 0f SECT 01 0000 [.text] SiBltDevice::WriteDrmDmaOffsetCmd(unsigned int) 00000000000b0f92 __float128 0f SECT 01 0000 [.text] SiBltDevice::WriteSdmaCondExecCmd(void*, LARGE_INTEGER, unsigned int) 00000000000ac824 __float128 0f SECT 01 0000 [.text] SiBltDevice::PreBltSynchronization(BltInfo const*) 00000000000b1490 __float128 0f SECT 01 0000 [.text] SiBltDevice::SetupCustomTileConfig(unsigned int, unsigned int) 00000000000b0f6a __float128 0f SECT 01 0000 [.text] SiBltDevice::SizeDrmDmaCondExecCmd() 00000000000aca34 __float128 0f SECT 01 0000 [.text] SiBltDevice::WriteCustomTileConfig() 00000000000ae194 __float128 0f SECT 01 0000 [.text] SiBltDevice::WriteDrawIndexAutoCmd(unsigned int) 00000000000b0e04 __float128 0f SECT 01 0000 [.text] SiBltDevice::WriteDrmDmaCounterCmd(unsigned char const*) 00000000000af934 __float128 0f SECT 01 0000 [.text] SiBltDevice::WriteSdmaTiledCopyCmd(_UBM_SURFINFO*, unsigned int, _UBM_SURFINFO*, LARGE_INTEGER, unsigned int, unsigned int) 00000000000af290 __float128 0f SECT 01 0000 [.text] SiBltDevice::SizeDrmDmaTiledCopyCmd() 00000000000ae212 __float128 0f SECT 01 0000 [.text] SiBltDevice::WriteDispatchDirectCmd(unsigned int, unsigned int, unsigned int) 00000000000b1118 __float128 0f SECT 01 0000 [.text] SiBltDevice::WriteDrmDmaCondExecCmd(void*, LARGE_INTEGER, unsigned int) 00000000000ad544 __float128 0f SECT 01 0000 [.text] SiBltDevice::Write3dDispatchPreamble() 00000000000b08e0 __float128 0f SECT 01 0000 [.text] SiBltDevice::WriteDrmDmaTiledCopyCmd(_UBM_SURFINFO*, unsigned int, _UBM_SURFINFO*, LARGE_INTEGER, unsigned int, unsigned int) 00000000000b20d8 __float128 0f SECT 01 0000 [.text] SiBltDevice::WritePreemptionPreamble(PM4ShaderType) 00000000000ae5cc __float128 0f SECT 01 0000 [.text] SiBltDevice::LoadShadowGfxContextRegs() 00000000000af2f4 __float128 0f SECT 01 0000 [.text] SiBltDevice::SizeSdmaT2TSubWinCopyCmd() 00000000000b124c __float128 0f SECT 01 0000 [.text] SiBltDevice::WriteSdmaConstantFillCmd(void*, LARGE_INTEGER, unsigned int, unsigned int, unsigned int, _UBM_ADDHANDLE_INPUT_FLAGS) 00000000000ac59c __float128 0f SECT 01 0000 [.text] SiBltDevice::HwlNotifyShadowMemoryInfo(_UBM_STATESHADOWMEMORYINFO*) 00000000000b1230 __float128 0f SECT 01 0000 [.text] SiBltDevice::SizeDrmDmaConstantFillCmd() 00000000000ae9f8 __float128 0f SECT 01 0000 [.text] SiBltDevice::Write3dDispatchPreambleCi() 00000000000aead0 __float128 0f SECT 01 0000 [.text] SiBltDevice::Write3dDispatchPreambleSi() 00000000000ad84e __float128 0f SECT 01 0000 [.text] SiBltDevice::WriteFlushAndInvTimestamp(void*, LARGE_INTEGER, unsigned int) 00000000000b03ec __float128 0f SECT 01 0000 [.text] SiBltDevice::WriteSdmaT2TCopySubWinCmd(_UBM_SURFINFO const*, _UBM_POINTL const*, _UBM_SURFINFO const*, _UBM_POINTL const*, unsigned int, unsigned int, _UBM_ADDHANDLE_INPUT_FLAGS) 00000000000ad5d8 __float128 0f SECT 01 0000 [.text] SiBltDevice::SetupAlignedEmbeddedBuffer(unsigned int, unsigned int) 00000000000af2cc __float128 0f SECT 01 0000 [.text] SiBltDevice::SizeSdmaTiledSubWinCopyCmd() 00000000000ad688 __float128 0f SECT 01 0000 [.text] SiBltDevice::WaitOnFlushAndInvTimestamp() 00000000000b1360 __float128 0f SECT 01 0000 [.text] SiBltDevice::WriteDrmDmaConstantFillCmd(void*, LARGE_INTEGER, unsigned int, unsigned int, _UBM_ADDHANDLE_INPUT_FLAGS) 00000000000af4a6 __float128 0f SECT 01 0000 [.text] SiBltDevice::WriteSdmaLinearByteCopyCmd(void*, LARGE_INTEGER, void*, LARGE_INTEGER, unsigned int, _UBM_ADDHANDLE_INPUT_FLAGS) 00000000000af258 __float128 0f SECT 01 0000 [.text] SiBltDevice::SizeDrmDmaLinearByteCopyCmd() 00000000000af2d8 __float128 0f SECT 01 0000 [.text] SiBltDevice::SizeDrmDmaT2TPartialCopyCmd() 00000000000af31c __float128 0f SECT 01 0000 [.text] SiBltDevice::SizeSdmaLinearSubWinCopyCmd() 00000000000af604 __float128 0f SECT 01 0000 [.text] SiBltDevice::WriteSdmaLinearDwordCopyCmd(void*, LARGE_INTEGER, void*, LARGE_INTEGER, unsigned int, unsigned int, _UBM_ADDHANDLE_INPUT_FLAGS) 00000000000afcdc __float128 0f SECT 01 0000 [.text] SiBltDevice::WriteSdmaTiledCopySubWinCmd(_UBM_SURFINFO const*, _UBM_POINTL const*, _UBM_SURFINFO const*, _UBM_POINTL const*, unsigned int, unsigned int, unsigned int, _UBM_ADDHANDLE_INPUT_FLAGS) 00000000000adc14 __float128 0f SECT 01 0000 [.text] SiBltDevice::Post3dDrawBltSynchronization(BltInfo const*) 00000000000ad59c __float128 0f SECT 01 0000 [.text] SiBltDevice::SetupAndCommitEmbeddedBuffer(unsigned int, unsigned int, unsigned long*) 00000000000af274 __float128 0f SECT 01 0000 [.text] SiBltDevice::SizeDrmDmaLinearDwordCopyCmd() 00000000000af328 __float128 0f SECT 01 0000 [.text] SiBltDevice::WriteDrmDmaLinearByteCopyCmd(void*, LARGE_INTEGER, void*, LARGE_INTEGER, unsigned int, _UBM_ADDHANDLE_INPUT_FLAGS) 00000000000b1766 __float128 0f SECT 01 0000 [.text] SiBltDevice::WriteDrmDmaT2TPartialCopyCmd(_UBM_SURFINFO const*, _UBM_POINTL const*, _UBM_SURFINFO const*, _UBM_POINTL const*, unsigned int, unsigned int, _UBM_ADDHANDLE_INPUT_FLAGS) 00000000000b0108 __float128 0f SECT 01 0000 [.text] SiBltDevice::WriteSdmaLinearCopySubWinCmd(_UBM_SURFINFO const*, _UBM_POINTL const*, _UBM_SURFINFO const*, _UBM_POINTL const*, unsigned int, unsigned int, _UBM_ADDHANDLE_INPUT_FLAGS) 00000000000af2b0 __float128 0f SECT 01 0000 [.text] SiBltDevice::SizeDrmDmaTiledPartialCopyCmd() 00000000000af776 __float128 0f SECT 01 0000 [.text] SiBltDevice::WriteDrmDmaLinearDwordCopyCmd(void*, LARGE_INTEGER, void*, LARGE_INTEGER, unsigned int, unsigned int, _UBM_ADDHANDLE_INPUT_FLAGS) 00000000000ad58a __float128 0f SECT 01 0000 [.text] SiBltDevice::EstimatedEmbeddedBufferEntries(unsigned int, unsigned int) 00000000000ade40 __float128 0f SECT 01 0000 [.text] SiBltDevice::PostDispatchBltSynchronization(BltInfo const*) 00000000000af300 __float128 0f SECT 01 0000 [.text] SiBltDevice::SizeDrmDmaLinearPartialCopyCmd() 00000000000b1ba8 __float128 0f SECT 01 0000 [.text] SiBltDevice::WriteDrmDmaTiledPartialCopyCmd(_UBM_SURFINFO const*, _UBM_POINTL const*, _UBM_SURFINFO const*, _UBM_POINTL const*, unsigned int, unsigned int, unsigned int, _UBM_ADDHANDLE_INPUT_FLAGS) 00000000000b14b4 __float128 0f SECT 01 0000 [.text] SiBltDevice::WriteDrmDmaLinearPartialCopyCmd(_UBM_SURFINFO const*, _UBM_POINTL const*, _UBM_SURFINFO const*, _UBM_POINTL const*, unsigned int, unsigned int, _UBM_ADDHANDLE_INPUT_FLAGS) 00000000000ac520 __float128 0f SECT 01 0000 [.text] SiBltDevice::HwlInit(_UBM_DEVICEINFO const*) 00000000000ac532 __float128 0f SECT 01 0000 [.text] SiBltDevice::HwlTrim() 00000000000ac4fa __float128 0f SECT 01 0000 [.text] SiBltDevice::CreateObj() 00000000000b2048 __float128 0f SECT 01 0000 [.text] SiBltDevice::GetNopCmd(unsigned int) 00000000000ac4c0 __float128 0f SECT 01 0000 [.text] SiBltDevice::SiBltDevice() 00000000000ac458 __float128 0f SECT 01 0000 [.text] SiBltDevice::SiBltDevice() 00000000000ac4de __float128 0f SECT 01 0000 [.text] SiBltDevice::~SiBltDevice() 00000000000ac4d4 __float128 0f SECT 01 0000 [.text] SiBltDevice::~SiBltDevice() 00000000000ac4ca __float128 0f SECT 01 0000 [.text] SiBltDevice::~SiBltDevice() 00000000000bc2a4 __float128 0f SECT 01 0000 [.text] SiBltResFmt::CreateObject() 00000000000bc254 __float128 0f SECT 01 0000 [.text] SiBltResFmt::SiBltResFmt() 00000000000bc234 __float128 0f SECT 01 0000 [.text] SiBltResFmt::SiBltResFmt() 00000000000bc288 __float128 0f SECT 01 0000 [.text] SiBltResFmt::~SiBltResFmt() 00000000000bc27e __float128 0f SECT 01 0000 [.text] SiBltResFmt::~SiBltResFmt() 00000000000bc274 __float128 0f SECT 01 0000 [.text] SiBltResFmt::~SiBltResFmt() 00000000000bdc5c __float128 0f SECT 01 0000 [.text] SiBltShader::SetBltShaderInput(SiBltShaderInput const*) 00000000000bdca0 __float128 0f SECT 01 0000 [.text] SiBltShader::GpuLoad(BltDevice*, void*, LARGE_INTEGER) 000000000052e648 __float128 0f SECT 0a 0000 [__DATA.__common] AMDCIDisplay::gMetaClass 00000000003b4968 __float128 0f SECT 08 0000 [.const_data] AMDCIDisplay::superClass 000000000007b98e __float128 0f SECT 01 0000 [.text] AMDCIDisplay::getPixelMode(unsigned int, unsigned int) 000000000007b87a __float128 0f SECT 01 0000 [.text] AMDCIDisplay::getDisplayInfo(unsigned int, bool, bool, void*, _FRAMEBUFFER_INFO*) 000000000007b2bc __float128 0f SECT 01 0000 [.text] AMDCIDisplay::getSurfaceMask(unsigned int const&) 000000000007b2cc __float128 0f SECT 01 0000 [.text] AMDCIDisplay::getSurfaceFlags() 000000000007b16e __float128 0f SECT 01 0000 [.text] AMDCIDisplay::writeWaitForVLine(unsigned int*, unsigned int, int&, int&, bool, bool) 000000000007ba06 __float128 0f SECT 01 0000 [.text] AMDCIDisplay::writeFlipControlRegisters(unsigned int, unsigned int*, unsigned int, unsigned long long, unsigned long long) 000000000007b962 __float128 0f SECT 01 0000 [.text] AMDCIDisplay::isCurrentDisplayModeLinear(unsigned int) 000000000007b0d2 __float128 0f SECT 01 0000 [.text] AMDCIDisplay::initDisplayRegistersOffsets() 000000000007b9aa __float128 0f SECT 01 0000 [.text] AMDCIDisplay::fedsWriteClearSurfaceApertureFlags(unsigned int*, unsigned int) 000000000007c38e __float128 0f SECT 01 0000 [.text] AMDCIDisplay::getDisplayModeViewportSpecificInfo(unsigned int const&, unsigned int*, unsigned int*) 000000000007af40 __float128 0f SECT 01 0000 [.text] AMDCIDisplay::MetaClass::MetaClass() 000000000007b000 __float128 0f SECT 01 0000 [.text] AMDCIDisplay::MetaClass::MetaClass() 00000000003b4960 __float128 0f SECT 08 0000 [.const_data] AMDCIDisplay::metaClass 000000000007b2e6 __float128 0f SECT 01 0000 [.text] AMDCIDisplay::setStereo(unsigned int, bool, bool) 000000000007af9c __float128 0f SECT 01 0000 [.text] AMDCIDisplay::AMDCIDisplay(OSMetaClass const*) 000000000007b072 __float128 0f SECT 01 0000 [.text] AMDCIDisplay::AMDCIDisplay() 000000000007af7c __float128 0f SECT 01 0000 [.text] AMDCIDisplay::AMDCIDisplay(OSMetaClass const*) 000000000007b0a2 __float128 0f SECT 01 0000 [.text] AMDCIDisplay::AMDCIDisplay() 000000000007afd0 __float128 0f SECT 01 0000 [.text] AMDCIDisplay::~AMDCIDisplay() 000000000007afc6 __float128 0f SECT 01 0000 [.text] AMDCIDisplay::~AMDCIDisplay() 000000000007afbc __float128 0f SECT 01 0000 [.text] AMDCIDisplay::~AMDCIDisplay() 000000000052e878 __float128 0f SECT 0a 0000 [__DATA.__common] AMDCIVCERing::gMetaClass 00000000003b7d58 __float128 0f SECT 08 0000 [.const_data] AMDCIVCERing::superClass 0000000000082760 __float128 0f SECT 01 0000 [.text] AMDCIVCERing::writeEntries(unsigned int*, unsigned int) 0000000000082604 __float128 0f SECT 01 0000 [.text] AMDCIVCERing::registerLocation() 000000000008267a __float128 0f SECT 01 0000 [.text] AMDCIVCERing::enableReadPointerWriteBack() 0000000000082680 __float128 0f SECT 01 0000 [.text] AMDCIVCERing::disableReadPointerWriteBack() 00000000000826e4 __float128 0f SECT 01 0000 [.text] AMDCIVCERing::programReadAndWritePointers(unsigned int) 00000000000825a2 __float128 0f SECT 01 0000 [.text] AMDCIVCERing::free() 0000000000082502 __float128 0f SECT 01 0000 [.text] AMDCIVCERing::init(AMDRadeonX4000_IAMDHWInterface*, int, _eAMD_HW_ENGINE_TYPE, unsigned int, void const*) 000000000008279e __float128 0f SECT 01 0000 [.text] AMDCIVCERing::align() 0000000000082686 __float128 0f SECT 01 0000 [.text] AMDCIVCERing::reset() 000000000008273c __float128 0f SECT 01 0000 [.text] AMDCIVCERing::write(unsigned int) 00000000000825de __float128 0f SECT 01 0000 [.text] AMDCIVCERing::getHead() 0000000000082370 __float128 0f SECT 01 0000 [.text] AMDCIVCERing::MetaClass::MetaClass() 0000000000082430 __float128 0f SECT 01 0000 [.text] AMDCIVCERing::MetaClass::MetaClass() 00000000003b7d50 __float128 0f SECT 08 0000 [.const_data] AMDCIVCERing::metaClass 00000000000823cc __float128 0f SECT 01 0000 [.text] AMDCIVCERing::AMDCIVCERing(OSMetaClass const*) 00000000000824a2 __float128 0f SECT 01 0000 [.text] AMDCIVCERing::AMDCIVCERing() 00000000000823ac __float128 0f SECT 01 0000 [.text] AMDCIVCERing::AMDCIVCERing(OSMetaClass const*) 00000000000824d2 __float128 0f SECT 01 0000 [.text] AMDCIVCERing::AMDCIVCERing() 0000000000082400 __float128 0f SECT 01 0000 [.text] AMDCIVCERing::~AMDCIVCERing() 00000000000823f6 __float128 0f SECT 01 0000 [.text] AMDCIVCERing::~AMDCIVCERing() 00000000000823ec __float128 0f SECT 01 0000 [.text] AMDCIVCERing::~AMDCIVCERing() 000000000052e2d8 __float128 0f SECT 0a 0000 [__DATA.__common] AMDSIDMARing::gMetaClass 00000000003af218 __float128 0f SECT 08 0000 [.const_data] AMDSIDMARing::superClass 000000000006f0a0 __float128 0f SECT 01 0000 [.text] AMDSIDMARing::registerLocation() 000000000006f192 __float128 0f SECT 01 0000 [.text] AMDSIDMARing::programReadAndWritePointers(unsigned int) 000000000006ec92 __float128 0f SECT 01 0000 [.text] AMDSIDMARing::init(AMDRadeonX4000_IAMDHWInterface*, int, _eAMD_HW_ENGINE_TYPE, unsigned int, void const*) 000000000006f20c __float128 0f SECT 01 0000 [.text] AMDSIDMARing::align() 000000000006f12e __float128 0f SECT 01 0000 [.text] AMDSIDMARing::reset() 000000000006ee50 __float128 0f SECT 01 0000 [.text] AMDSIDMARing::enable() 000000000006efe8 __float128 0f SECT 01 0000 [.text] AMDSIDMARing::disable() 000000000006f06a __float128 0f SECT 01 0000 [.text] AMDSIDMARing::getHead() 000000000006eb00 __float128 0f SECT 01 0000 [.text] AMDSIDMARing::MetaClass::MetaClass() 000000000006ebc0 __float128 0f SECT 01 0000 [.text] AMDSIDMARing::MetaClass::MetaClass() 00000000003af210 __float128 0f SECT 08 0000 [.const_data] AMDSIDMARing::metaClass 000000000006eb5c __float128 0f SECT 01 0000 [.text] AMDSIDMARing::AMDSIDMARing(OSMetaClass const*) 000000000006ec32 __float128 0f SECT 01 0000 [.text] AMDSIDMARing::AMDSIDMARing() 000000000006eb3c __float128 0f SECT 01 0000 [.text] AMDSIDMARing::AMDSIDMARing(OSMetaClass const*) 000000000006ec62 __float128 0f SECT 01 0000 [.text] AMDSIDMARing::AMDSIDMARing() 000000000006eb90 __float128 0f SECT 01 0000 [.text] AMDSIDMARing::~AMDSIDMARing() 000000000006eb86 __float128 0f SECT 01 0000 [.text] AMDSIDMARing::~AMDSIDMARing() 000000000006eb7c __float128 0f SECT 01 0000 [.text] AMDSIDMARing::~AMDSIDMARing() 000000000052e030 __float128 0f SECT 0a 0000 [__DATA.__common] AMDSIDisplay::gMetaClass 00000000003aa9f8 __float128 0f SECT 08 0000 [.const_data] AMDSIDisplay::superClass 000000000006406e __float128 0f SECT 01 0000 [.text] AMDSIDisplay::getPixelMode(unsigned int, unsigned int) 0000000000063dc0 __float128 0f SECT 01 0000 [.text] AMDSIDisplay::FEDSRevertCRTC() 0000000000063f5a __float128 0f SECT 01 0000 [.text] AMDSIDisplay::getDisplayInfo(unsigned int, bool, bool, void*, _FRAMEBUFFER_INFO*) 000000000006408a __float128 0f SECT 01 0000 [.text] AMDSIDisplay::getPixelFormat(unsigned char) 0000000000063ea4 __float128 0f SECT 01 0000 [.text] AMDSIDisplay::getSurfaceMask(unsigned int) 0000000000063e8a __float128 0f SECT 01 0000 [.text] AMDSIDisplay::getSurfaceFlags() 0000000000064960 __float128 0f SECT 01 0000 [.text] AMDSIDisplay::writeWaitForVLine(unsigned int*, unsigned int, int&, int&, bool, bool) 0000000000063b04 __float128 0f SECT 01 0000 [.text] AMDSIDisplay::configCrtcRegisters(unsigned int, IOAccelResource2*, IOAccelMemoryMap*) 0000000000064750 __float128 0f SECT 01 0000 [.text] AMDSIDisplay::writeVblankFlipElement(AMD_VBLANK_FLIP_ELEM*, unsigned int, unsigned long long, unsigned long long, unsigned int) 00000000000640ec __float128 0f SECT 01 0000 [.text] AMDSIDisplay::writeFlipControlRegisters(unsigned int, unsigned int*, unsigned int, unsigned long long, unsigned long long) 0000000000064042 __float128 0f SECT 01 0000 [.text] AMDSIDisplay::isCurrentDisplayModeLinear(unsigned int) 0000000000064954 __float128 0f SECT 01 0000 [.text] AMDSIDisplay::getSurfaceUpdatePendingMask() 0000000000063476 __float128 0f SECT 01 0000 [.text] AMDSIDisplay::initDisplayRegistersOffsets() 0000000000063eb6 __float128 0f SECT 01 0000 [.text] AMDSIDisplay::fedsWriteClearSurfaceApertureFlags(unsigned int*, unsigned int) 0000000000063ee6 __float128 0f SECT 01 0000 [.text] AMDSIDisplay::getDisplayModeViewportSpecificInfo(unsigned int, unsigned int*, unsigned int*) 0000000000064a86 __float128 0f SECT 01 0000 [.text] AMDSIDisplay::writeDrawBufferInformationCommands(IOAccelResource2 const*, unsigned int*) 0000000000063464 __float128 0f SECT 01 0000 [.text] AMDSIDisplay::free() 0000000000063452 __float128 0f SECT 01 0000 [.text] AMDSIDisplay::init(AMDRadeonX4000_IAMDHWInterface*, _FB_PARAMETERS*) 00000000000632c0 __float128 0f SECT 01 0000 [.text] AMDSIDisplay::MetaClass::MetaClass() 0000000000063380 __float128 0f SECT 01 0000 [.text] AMDSIDisplay::MetaClass::MetaClass() 00000000003aa9f0 __float128 0f SECT 08 0000 [.const_data] AMDSIDisplay::metaClass 0000000000063512 __float128 0f SECT 01 0000 [.text] AMDSIDisplay::setStereo(unsigned int, bool, bool) 000000000006331c __float128 0f SECT 01 0000 [.text] AMDSIDisplay::AMDSIDisplay(OSMetaClass const*) 00000000000633f2 __float128 0f SECT 01 0000 [.text] AMDSIDisplay::AMDSIDisplay() 00000000000632fc __float128 0f SECT 01 0000 [.text] AMDSIDisplay::AMDSIDisplay(OSMetaClass const*) 0000000000063422 __float128 0f SECT 01 0000 [.text] AMDSIDisplay::AMDSIDisplay() 0000000000063350 __float128 0f SECT 01 0000 [.text] AMDSIDisplay::~AMDSIDisplay() 0000000000063346 __float128 0f SECT 01 0000 [.text] AMDSIDisplay::~AMDSIDisplay() 000000000006333c __float128 0f SECT 01 0000 [.text] AMDSIDisplay::~AMDSIDisplay() 000000000052e490 __float128 0f SECT 0a 0000 [__DATA.__common] AMDSISPURing::gMetaClass 00000000003b19d8 __float128 0f SECT 08 0000 [.const_data] AMDSISPURing::superClass 0000000000073636 __float128 0f SECT 01 0000 [.text] AMDSISPURing::commitBlock(unsigned int) 000000000007350c __float128 0f SECT 01 0000 [.text] AMDSISPURing::registerLocation() 0000000000073654 __float128 0f SECT 01 0000 [.text] AMDSISPURing::getSPUReadPointer() 0000000000073696 __float128 0f SECT 01 0000 [.text] AMDSISPURing::getSPUWritePointer() 0000000000073530 __float128 0f SECT 01 0000 [.text] AMDSISPURing::enableReadPointerWriteBack() 0000000000073536 __float128 0f SECT 01 0000 [.text] AMDSISPURing::disableReadPointerWriteBack() 0000000000073592 __float128 0f SECT 01 0000 [.text] AMDSISPURing::programReadAndWritePointers(unsigned int) 00000000000734c2 __float128 0f SECT 01 0000 [.text] AMDSISPURing::free() 0000000000073422 __float128 0f SECT 01 0000 [.text] AMDSISPURing::init(AMDRadeonX4000_IAMDHWInterface*, int, _eAMD_HW_ENGINE_TYPE, unsigned int, void const*) 000000000007364e __float128 0f SECT 01 0000 [.text] AMDSISPURing::align() 000000000007353c __float128 0f SECT 01 0000 [.text] AMDSISPURing::reset() 0000000000073612 __float128 0f SECT 01 0000 [.text] AMDSISPURing::write(unsigned int) 00000000000734fe __float128 0f SECT 01 0000 [.text] AMDSISPURing::getHead() 0000000000073290 __float128 0f SECT 01 0000 [.text] AMDSISPURing::MetaClass::MetaClass() 0000000000073350 __float128 0f SECT 01 0000 [.text] AMDSISPURing::MetaClass::MetaClass() 00000000003b19d0 __float128 0f SECT 08 0000 [.const_data] AMDSISPURing::metaClass 00000000000736d8 __float128 0f SECT 01 0000 [.text] AMDSISPURing::writeTail() 00000000000732ec __float128 0f SECT 01 0000 [.text] AMDSISPURing::AMDSISPURing(OSMetaClass const*) 00000000000733c2 __float128 0f SECT 01 0000 [.text] AMDSISPURing::AMDSISPURing() 00000000000732cc __float128 0f SECT 01 0000 [.text] AMDSISPURing::AMDSISPURing(OSMetaClass const*) 00000000000733f2 __float128 0f SECT 01 0000 [.text] AMDSISPURing::AMDSISPURing() 0000000000073320 __float128 0f SECT 01 0000 [.text] AMDSISPURing::~AMDSISPURing() 0000000000073316 __float128 0f SECT 01 0000 [.text] AMDSISPURing::~AMDSISPURing() 000000000007330c __float128 0f SECT 01 0000 [.text] AMDSISPURing::~AMDSISPURing() 000000000052d658 __float128 0f SECT 0a 0000 [__DATA.__common] AMDSISurface::gMetaClass 00000000003976f8 __float128 0f SECT 08 0000 [.const_data] AMDSISurface::superClass 000000000002ab82 __float128 0f SECT 01 0000 [.text] AMDSISurface::getSurfaceModeDepthFormat() 000000000002a9f0 __float128 0f SECT 01 0000 [.text] AMDSISurface::MetaClass::MetaClass() 000000000002aab0 __float128 0f SECT 01 0000 [.text] AMDSISurface::MetaClass::MetaClass() 00000000003976f0 __float128 0f SECT 08 0000 [.const_data] AMDSISurface::metaClass 000000000002aa4c __float128 0f SECT 01 0000 [.text] AMDSISurface::AMDSISurface(OSMetaClass const*) 000000000002ab22 __float128 0f SECT 01 0000 [.text] AMDSISurface::AMDSISurface() 000000000002aa2c __float128 0f SECT 01 0000 [.text] AMDSISurface::AMDSISurface(OSMetaClass const*) 000000000002ab52 __float128 0f SECT 01 0000 [.text] AMDSISurface::AMDSISurface() 000000000002aa80 __float128 0f SECT 01 0000 [.text] AMDSISurface::~AMDSISurface() 000000000002aa76 __float128 0f SECT 01 0000 [.text] AMDSISurface::~AMDSISurface() 000000000002aa6c __float128 0f SECT 01 0000 [.text] AMDSISurface::~AMDSISurface() 000000000052e418 __float128 0f SECT 0a 0000 [__DATA.__common] AMDSIUVDRing::gMetaClass 00000000003b0f38 __float128 0f SECT 08 0000 [.const_data] AMDSIUVDRing::superClass 0000000000071e68 __float128 0f SECT 01 0000 [.text] AMDSIUVDRing::registerLocation() 0000000000071f46 __float128 0f SECT 01 0000 [.text] AMDSIUVDRing::enableReadPointerWriteBack() 0000000000071f4c __float128 0f SECT 01 0000 [.text] AMDSIUVDRing::disableReadPointerWriteBack() 0000000000071fb0 __float128 0f SECT 01 0000 [.text] AMDSIUVDRing::programReadAndWritePointers(unsigned int) 0000000000071dcc __float128 0f SECT 01 0000 [.text] AMDSIUVDRing::free() 0000000000071d22 __float128 0f SECT 01 0000 [.text] AMDSIUVDRing::init(AMDRadeonX4000_IAMDHWInterface*, int, _eAMD_HW_ENGINE_TYPE, unsigned int, void const*) 000000000007200e __float128 0f SECT 01 0000 [.text] AMDSIUVDRing::align() 0000000000071f52 __float128 0f SECT 01 0000 [.text] AMDSIUVDRing::reset() 0000000000071dde __float128 0f SECT 01 0000 [.text] AMDSIUVDRing::disable() 0000000000071e36 __float128 0f SECT 01 0000 [.text] AMDSIUVDRing::getHead() 0000000000071b90 __float128 0f SECT 01 0000 [.text] AMDSIUVDRing::MetaClass::MetaClass() 0000000000071c50 __float128 0f SECT 01 0000 [.text] AMDSIUVDRing::MetaClass::MetaClass() 00000000003b0f30 __float128 0f SECT 08 0000 [.const_data] AMDSIUVDRing::metaClass 0000000000071bec __float128 0f SECT 01 0000 [.text] AMDSIUVDRing::AMDSIUVDRing(OSMetaClass const*) 0000000000071cc2 __float128 0f SECT 01 0000 [.text] AMDSIUVDRing::AMDSIUVDRing() 0000000000071bcc __float128 0f SECT 01 0000 [.text] AMDSIUVDRing::AMDSIUVDRing(OSMetaClass const*) 0000000000071cf2 __float128 0f SECT 01 0000 [.text] AMDSIUVDRing::AMDSIUVDRing() 0000000000071c20 __float128 0f SECT 01 0000 [.text] AMDSIUVDRing::~AMDSIUVDRing() 0000000000071c16 __float128 0f SECT 01 0000 [.text] AMDSIUVDRing::~AMDSIUVDRing() 0000000000071c0c __float128 0f SECT 01 0000 [.text] AMDSIUVDRing::~AMDSIUVDRing() 000000000052e378 __float128 0f SECT 0a 0000 [__DATA.__common] AMDSIVCERing::gMetaClass 00000000003b0098 __float128 0f SECT 08 0000 [.const_data] AMDSIVCERing::superClass 0000000000070740 __float128 0f SECT 01 0000 [.text] AMDSIVCERing::writeEntries(unsigned int*, unsigned int) 00000000000705e4 __float128 0f SECT 01 0000 [.text] AMDSIVCERing::registerLocation() 000000000007065a __float128 0f SECT 01 0000 [.text] AMDSIVCERing::enableReadPointerWriteBack() 0000000000070660 __float128 0f SECT 01 0000 [.text] AMDSIVCERing::disableReadPointerWriteBack() 00000000000706c4 __float128 0f SECT 01 0000 [.text] AMDSIVCERing::programReadAndWritePointers(unsigned int) 0000000000070582 __float128 0f SECT 01 0000 [.text] AMDSIVCERing::free() 00000000000704e2 __float128 0f SECT 01 0000 [.text] AMDSIVCERing::init(AMDRadeonX4000_IAMDHWInterface*, int, _eAMD_HW_ENGINE_TYPE, unsigned int, void const*) 000000000007077e __float128 0f SECT 01 0000 [.text] AMDSIVCERing::align() 0000000000070666 __float128 0f SECT 01 0000 [.text] AMDSIVCERing::reset() 000000000007071c __float128 0f SECT 01 0000 [.text] AMDSIVCERing::write(unsigned int) 00000000000705be __float128 0f SECT 01 0000 [.text] AMDSIVCERing::getHead() 0000000000070350 __float128 0f SECT 01 0000 [.text] AMDSIVCERing::MetaClass::MetaClass() 0000000000070410 __float128 0f SECT 01 0000 [.text] AMDSIVCERing::MetaClass::MetaClass() 00000000003b0090 __float128 0f SECT 08 0000 [.const_data] AMDSIVCERing::metaClass 00000000000703ac __float128 0f SECT 01 0000 [.text] AMDSIVCERing::AMDSIVCERing(OSMetaClass const*) 0000000000070482 __float128 0f SECT 01 0000 [.text] AMDSIVCERing::AMDSIVCERing() 000000000007038c __float128 0f SECT 01 0000 [.text] AMDSIVCERing::AMDSIVCERing(OSMetaClass const*) 00000000000704b2 __float128 0f SECT 01 0000 [.text] AMDSIVCERing::AMDSIVCERing() 00000000000703e0 __float128 0f SECT 01 0000 [.text] AMDSIVCERing::~AMDSIVCERing() 00000000000703d6 __float128 0f SECT 01 0000 [.text] AMDSIVCERing::~AMDSIVCERing() 00000000000703cc __float128 0f SECT 01 0000 [.text] AMDSIVCERing::~AMDSIVCERing() 000000000052ea08 __float128 0f SECT 0a 0000 [__DATA.__common] AMDVIDisplay::gMetaClass 00000000003ba548 __float128 0f SECT 08 0000 [.const_data] AMDVIDisplay::superClass 000000000008a362 __float128 0f SECT 01 0000 [.text] AMDVIDisplay::getPixelMode(unsigned int, unsigned int) 0000000000089c4e __float128 0f SECT 01 0000 [.text] AMDVIDisplay::FEDSRevertCRTC() 000000000008a386 __float128 0f SECT 01 0000 [.text] AMDVIDisplay::getDisplayInfo(unsigned int, bool, bool, void*, _FRAMEBUFFER_INFO*) 000000000008a49a __float128 0f SECT 01 0000 [.text] AMDVIDisplay::getPixelFormat(unsigned char) 0000000000089da2 __float128 0f SECT 01 0000 [.text] AMDVIDisplay::getSurfaceMask(unsigned int) 0000000000089db4 __float128 0f SECT 01 0000 [.text] AMDVIDisplay::getSurfaceFlags() 0000000000089c54 __float128 0f SECT 01 0000 [.text] AMDVIDisplay::writeWaitForVLine(unsigned int*, unsigned int, int&, int&, bool, bool) 0000000000089992 __float128 0f SECT 01 0000 [.text] AMDVIDisplay::configCrtcRegisters(unsigned int, IOAccelResource2*, IOAccelMemoryMap*) 000000000008af6c __float128 0f SECT 01 0000 [.text] AMDVIDisplay::writeVblankFlipElement(AMD_VBLANK_FLIP_ELEM*, unsigned int, unsigned long long, unsigned long long, unsigned int) 000000000008a4fc __float128 0f SECT 01 0000 [.text] AMDVIDisplay::writeFlipControlRegisters(unsigned int, unsigned int*, unsigned int, unsigned long long, unsigned long long) 000000000008a46e __float128 0f SECT 01 0000 [.text] AMDVIDisplay::isCurrentDisplayModeLinear(unsigned int) 000000000008b170 __float128 0f SECT 01 0000 [.text] AMDVIDisplay::getSurfaceUpdatePendingMask() 00000000000898f6 __float128 0f SECT 01 0000 [.text] AMDVIDisplay::initDisplayRegistersOffsets() 000000000008adca __float128 0f SECT 01 0000 [.text] AMDVIDisplay::writeTilingControlRegisters(unsigned int, unsigned int*, unsigned int) 000000000008a37e __float128 0f SECT 01 0000 [.text] AMDVIDisplay::fedsWriteClearSurfaceApertureFlags(unsigned int*, unsigned int) 000000000008aef8 __float128 0f SECT 01 0000 [.text] AMDVIDisplay::getDisplayModeViewportSpecificInfo(unsigned int, unsigned int*, unsigned int*) 000000000008b17c __float128 0f SECT 01 0000 [.text] AMDVIDisplay::writeDrawBufferInformationCommands(IOAccelResource2 const*, unsigned int*) 00000000000898e4 __float128 0f SECT 01 0000 [.text] AMDVIDisplay::free() 00000000000898d2 __float128 0f SECT 01 0000 [.text] AMDVIDisplay::init(AMDRadeonX4000_IAMDHWInterface*, _FB_PARAMETERS*) 0000000000089740 __float128 0f SECT 01 0000 [.text] AMDVIDisplay::MetaClass::MetaClass() 0000000000089800 __float128 0f SECT 01 0000 [.text] AMDVIDisplay::MetaClass::MetaClass() 00000000003ba540 __float128 0f SECT 08 0000 [.const_data] AMDVIDisplay::metaClass 0000000000089dce __float128 0f SECT 01 0000 [.text] AMDVIDisplay::setStereo(unsigned int, bool, bool) 000000000008979c __float128 0f SECT 01 0000 [.text] AMDVIDisplay::AMDVIDisplay(OSMetaClass const*) 0000000000089872 __float128 0f SECT 01 0000 [.text] AMDVIDisplay::AMDVIDisplay() 000000000008977c __float128 0f SECT 01 0000 [.text] AMDVIDisplay::AMDVIDisplay(OSMetaClass const*) 00000000000898a2 __float128 0f SECT 01 0000 [.text] AMDVIDisplay::AMDVIDisplay() 00000000000897d0 __float128 0f SECT 01 0000 [.text] AMDVIDisplay::~AMDVIDisplay() 00000000000897c6 __float128 0f SECT 01 0000 [.text] AMDVIDisplay::~AMDVIDisplay() 00000000000897bc __float128 0f SECT 01 0000 [.text] AMDVIDisplay::~AMDVIDisplay() 000000000052e670 __float128 0f SECT 0a 0000 [__DATA.__common] AMDCIHWMemory::gMetaClass 00000000003b4de8 __float128 0f SECT 08 0000 [.const_data] AMDCIHWMemory::superClass 000000000007c856 __float128 0f SECT 01 0000 [.text] AMDCIHWMemory::getHWMemorySize() 000000000007c888 __float128 0f SECT 01 0000 [.text] AMDCIHWMemory::getHWMemoryApertureSize() 000000000007c842 __float128 0f SECT 01 0000 [.text] AMDCIHWMemory::init(AMDRadeonX4000_IAMDHWInterface*) 000000000007c8ba __float128 0f SECT 01 0000 [.text] AMDCIHWMemory::prepare(AMDRadeonX4000_AMDAccelResource*, unsigned long long, unsigned long long, unsigned long long*) 000000000007cc2c __float128 0f SECT 01 0000 [.text] AMDCIHWMemory::complete(AMDRadeonX4000_AMDAccelResource*) 000000000007c6b0 __float128 0f SECT 01 0000 [.text] AMDCIHWMemory::MetaClass::MetaClass() 000000000007c770 __float128 0f SECT 01 0000 [.text] AMDCIHWMemory::MetaClass::MetaClass() 00000000003b4de0 __float128 0f SECT 08 0000 [.const_data] AMDCIHWMemory::metaClass 000000000007c70c __float128 0f SECT 01 0000 [.text] AMDCIHWMemory::AMDCIHWMemory(OSMetaClass const*) 000000000007c7e2 __float128 0f SECT 01 0000 [.text] AMDCIHWMemory::AMDCIHWMemory() 000000000007c6ec __float128 0f SECT 01 0000 [.text] AMDCIHWMemory::AMDCIHWMemory(OSMetaClass const*) 000000000007c812 __float128 0f SECT 01 0000 [.text] AMDCIHWMemory::AMDCIHWMemory() 000000000007c740 __float128 0f SECT 01 0000 [.text] AMDCIHWMemory::~AMDCIHWMemory() 000000000007c736 __float128 0f SECT 01 0000 [.text] AMDCIHWMemory::~AMDCIHWMemory() 000000000007c72c __float128 0f SECT 01 0000 [.text] AMDCIHWMemory::~AMDCIHWMemory() 0000000000077126 __float128 0f SECT 01 0000 [.text] AMDCIHardware::disableDPM() 000000000052e508 __float128 0f SECT 0a 0000 [__DATA.__common] AMDCIHardware::gMetaClass 00000000000750fc __float128 0f SECT 01 0000 [.text] AMDCIHardware::initHWInfo() 00000000003b2418 __float128 0f SECT 08 0000 [.const_data] AMDCIHardware::superClass 0000000000074b6a __float128 0f SECT 01 0000 [.text] AMDCIHardware::allocateSML() 000000000007711e __float128 0f SECT 01 0000 [.text] AMDCIHardware::isDPMEnabled() 0000000000075940 __float128 0f SECT 01 0000 [.text] AMDCIHardware::enableContext(unsigned int, bool) 0000000000074fe2 __float128 0f SECT 01 0000 [.text] AMDCIHardware::flushHDPCache() 00000000000752f4 __float128 0f SECT 01 0000 [.text] AMDCIHardware::initializeGUI() 0000000000074b90 __float128 0f SECT 01 0000 [.text] AMDCIHardware::allocateAMDHWVMM() 0000000000074a38 __float128 0f SECT 01 0000 [.text] AMDCIHardware::getOGLBundleName() 0000000000075024 __float128 0f SECT 01 0000 [.text] AMDCIHardware::initMaskSettings() 00000000000757d6 __float128 0f SECT 01 0000 [.text] AMDCIHardware::initializeVMRegs() 0000000000074e3c __float128 0f SECT 01 0000 [.text] AMDCIHardware::allocateHWEngines() 00000000000767b6 __float128 0f SECT 01 0000 [.text] AMDCIHardware::dumpASICHangState(bool) 00000000000750d2 __float128 0f SECT 01 0000 [.text] AMDCIHardware::getCoherCntrValue(bool, bool, bool) 00000000000757ae __float128 0f SECT 01 0000 [.text] AMDCIHardware::initializeTlbRegs() 0000000000075362 __float128 0f SECT 01 0000 [.text] AMDCIHardware::enableTransactions() 000000000007513a __float128 0f SECT 01 0000 [.text] AMDCIHardware::getAMDHwInfoValues(_sAMD_GET_HW_INFO_VALUES*) 0000000000074a84 __float128 0f SECT 01 0000 [.text] AMDCIHardware::getMemSizeRegister() 0000000000074fc4 __float128 0f SECT 01 0000 [.text] AMDCIHardware::readHWChipRevValue() 0000000000074aaa __float128 0f SECT 01 0000 [.text] AMDCIHardware::setMemSizeRegister(unsigned int) 00000000000755bc __float128 0f SECT 01 0000 [.text] AMDCIHardware::setupInternalSpace() 0000000000074a0c __float128 0f SECT 01 0000 [.text] AMDCIHardware::writeOCDBundleName() 0000000000074af8 __float128 0f SECT 01 0000 [.text] AMDCIHardware::allocateAMDHWMemory() 0000000000075316 __float128 0f SECT 01 0000 [.text] AMDCIHardware::disableTransactions() 00000000000753f2 __float128 0f SECT 01 0000 [.text] AMDCIHardware::fillNDRVSurfaceInfo(_AMD_SURFACE_INFO_STRUCT*, _ADDR_TILEINFO*) 000000000007629a __float128 0f SECT 01 0000 [.text] AMDCIHardware::freeWritebackMemory() 0000000000074ad2 __float128 0f SECT 01 0000 [.text] AMDCIHardware::getRegisterAperSize() 0000000000075a48 __float128 0f SECT 01 0000 [.text] AMDCIHardware::initializeCacheRegs() 0000000000075014 __float128 0f SECT 01 0000 [.text] AMDCIHardware::initializeGFXEngine() 0000000000075c0c __float128 0f SECT 01 0000 [.text] AMDCIHardware::verifyThreadsActive() 0000000000074b1e __float128 0f SECT 01 0000 [.text] AMDCIHardware::allocateAMDHWDisplay() 0000000000075004 __float128 0f SECT 01 0000 [.text] AMDCIHardware::initializeFamilyType() 0000000000074c94 __float128 0f SECT 01 0000 [.text] AMDCIHardware::readHWGBTilingConfig() 0000000000076afe __float128 0f SECT 01 0000 [.text] AMDCIHardware::writeASICHangLogInfo(_AMD_ASIC_HANG_LOG_INFO*) 0000000000076d82 __float128 0f SECT 01 0000 [.text] AMDCIHardware::writeDiagnosisReport(char*&, unsigned int&) 0000000000077084 __float128 0f SECT 01 0000 [.text] AMDCIHardware::writeQSCRegMemTimeout(unsigned int*, unsigned int) 0000000000074bfc __float128 0f SECT 01 0000 [.text] AMDCIHardware::allocateAMDHWUtilities() 0000000000074a78 __float128 0f SECT 01 0000 [.text] AMDCIHardware::getATIDisplayConfigBit() 0000000000076216 __float128 0f SECT 01 0000 [.text] AMDCIHardware::allocateWritebackMemory() 0000000000074a46 __float128 0f SECT 01 0000 [.text] AMDCIHardware::createAtomicBlitManager() 0000000000074c22 __float128 0f SECT 01 0000 [.text] AMDCIHardware::initializeHWWorkarounds() 000000000007564e __float128 0f SECT 01 0000 [.text] AMDCIHardware::initializePageTableRegs() 000000000007709e __float128 0f SECT 01 0000 [.text] AMDCIHardware::setPerformanceLevelHigh() 0000000000074cb2 __float128 0f SECT 01 0000 [.text] AMDCIHardware::getHardwareDefaultValues(_sAMD_HW_DEFAULT_VALUES*) 0000000000074bd6 __float128 0f SECT 01 0000 [.text] AMDCIHardware::allocateAMDHWAlignManager() 0000000000076742 __float128 0f SECT 01 0000 [.text] AMDCIHardware::dumpAsicHangLogIntoSyslog(_AMD_ASIC_HANG_LOG_INFO*) 0000000000074950 __float128 0f SECT 01 0000 [.text] AMDCIHardware::getFrameBufferBaseAddress() 00000000000759ae __float128 0f SECT 01 0000 [.text] AMDCIHardware::programPageTableRegisters(AMD_VM_PAGE_TABLE_INFO*, unsigned int) 000000000007496e __float128 0f SECT 01 0000 [.text] AMDCIHardware::writeWaitForRenderingPipe(unsigned int*, bool) 0000000000074b44 __float128 0f SECT 01 0000 [.text] AMDCIHardware::allocatePM4CommandsUtility() 0000000000075a70 __float128 0f SECT 01 0000 [.text] AMDCIHardware::initializeGartApertureRegs() 0000000000074f3e __float128 0f SECT 01 0000 [.text] AMDCIHardware::invalidateAllTLBsAndCaches(bool, unsigned int) 0000000000076678 __float128 0f SECT 01 0000 [.text] AMDCIHardware::asicHangReadROQandMEQStatus(amdAsicHangDumpROQMEQStatus&) 0000000000075bf6 __float128 0f SECT 01 0000 [.text] AMDCIHardware::setMemoryAllocationsEnabled(bool) 0000000000076504 __float128 0f SECT 01 0000 [.text] AMDCIHardware::asicHangLogDumpMeStateQueues(_AMD_ASIC_HANG_LOG_INFO*) 0000000000076350 __float128 0f SECT 01 0000 [.text] AMDCIHardware::asicHangLogDumpReorderQueues(_AMD_ASIC_HANG_LOG_INFO*) 000000000007562c __float128 0f SECT 01 0000 [.text] AMDCIHardware::initializeHDPPathWorkarounds() 0000000000075b12 __float128 0f SECT 01 0000 [.text] AMDCIHardware::initializeSystemApertureRegs() 00000000000762f8 __float128 0f SECT 01 0000 [.text] AMDCIHardware::getChannelWritePointerPollAddr(int) 00000000000762e0 __float128 0f SECT 01 0000 [.text] AMDCIHardware::getChannelWritePointerPollOffset(int) 0000000000074a6c __float128 0f SECT 01 0000 [.text] AMDCIHardware::getMMRPCIConfigBaseAddressOffset() 0000000000074cd6 __float128 0f SECT 01 0000 [.text] AMDCIHardware::setupAndInitializeHWCapabilities() 0000000000076f74 __float128 0f SECT 01 0000 [.text] AMDCIHardware::stallGPUDuringScanLineRangeSetup(unsigned int, unsigned int, unsigned int, unsigned int, unsigned short, unsigned short) 0000000000076314 __float128 0f SECT 01 0000 [.text] AMDCIHardware::getRequiredAsicHangLogDumpRegisters(unsigned int&) 000000000007633c __float128 0f SECT 01 0000 [.text] AMDCIHardware::getRequiredAsicHangLogDumpMeStateQueueRegisters(unsigned int&) 0000000000076328 __float128 0f SECT 01 0000 [.text] AMDCIHardware::getRequiredAsicHangLogDumpReorderQueueRegisters(unsigned int&) 0000000000074910 __float128 0f SECT 01 0000 [.text] AMDCIHardware::free() 000000000007488a __float128 0f SECT 01 0000 [.text] AMDCIHardware::init(IOPCIDevice*, AMDRadeonX4000_IAMDHWHandler*, unsigned int&, unsigned int, _GART_PARAMETERS*, _FB_PARAMETERS*) 0000000000075086 __float128 0f SECT 01 0000 [.text] AMDCIHardware::powerUp() 00000000000750c0 __float128 0f SECT 01 0000 [.text] AMDCIHardware::powerOff() 00000000000747b0 __float128 0f SECT 01 0000 [.text] AMDCIHardware::MetaClass::MetaClass() 0000000000074850 __float128 0f SECT 01 0000 [.text] AMDCIHardware::MetaClass::MetaClass() 000000000007712c __float128 0f SECT 01 0000 [.text] AMDCIHardware::enableDPM() 00000000003b2410 __float128 0f SECT 08 0000 [.const_data] AMDCIHardware::metaClass 00000000000747ec __float128 0f SECT 01 0000 [.text] AMDCIHardware::AMDCIHardware(OSMetaClass const*) 0000000000074820 __float128 0f SECT 01 0000 [.text] AMDCIHardware::~AMDCIHardware() 0000000000074816 __float128 0f SECT 01 0000 [.text] AMDCIHardware::~AMDCIHardware() 000000000007480c __float128 0f SECT 01 0000 [.text] AMDCIHardware::~AMDCIHardware() 000000000052d770 __float128 0f SECT 0a 0000 [__DATA.__common] AMDCIResource::gMetaClass 000000000039d0d8 __float128 0f SECT 08 0000 [.const_data] AMDCIResource::superClass 000000000003e21a __float128 0f SECT 01 0000 [.text] AMDCIResource::getPagingChannel(bool) 000000000003db5e __float128 0f SECT 01 0000 [.text] AMDCIResource::pageOffMSAADepthBuffer(_UBM_SURFINFO*, _UBM_SURFINFO*, IOAccelMemoryMap*, IOAccelMemoryMap*, _UBM_RECTL*, _UBM_RECTL*, unsigned int, unsigned int) 000000000003d818 __float128 0f SECT 01 0000 [.text] AMDCIResource::fillUBMSurfaceInfoInternal(_UBM_SURFINFO*, _sMASK_MEMORY_SETTINGS*, IOAccelMemoryMap*, AMDRadeonX4000_AMDAccelResource*, unsigned int, unsigned int, unsigned int) 000000000003d7e2 __float128 0f SECT 01 0000 [.text] AMDCIResource::init(IOGraphicsAccelerator2*, IOAccelShared2*, unsigned int) 000000000003d650 __float128 0f SECT 01 0000 [.text] AMDCIResource::MetaClass::MetaClass() 000000000003d710 __float128 0f SECT 01 0000 [.text] AMDCIResource::MetaClass::MetaClass() 000000000039d0d0 __float128 0f SECT 08 0000 [.const_data] AMDCIResource::metaClass 000000000003d6ac __float128 0f SECT 01 0000 [.text] AMDCIResource::AMDCIResource(OSMetaClass const*) 000000000003d782 __float128 0f SECT 01 0000 [.text] AMDCIResource::AMDCIResource() 000000000003d68c __float128 0f SECT 01 0000 [.text] AMDCIResource::AMDCIResource(OSMetaClass const*) 000000000003d7b2 __float128 0f SECT 01 0000 [.text] AMDCIResource::AMDCIResource() 000000000003d6e0 __float128 0f SECT 01 0000 [.text] AMDCIResource::~AMDCIResource() 000000000003d6d6 __float128 0f SECT 01 0000 [.text] AMDCIResource::~AMDCIResource() 000000000003d6cc __float128 0f SECT 01 0000 [.text] AMDCIResource::~AMDCIResource() 000000000052e5f8 __float128 0f SECT 0a 0000 [__DATA.__common] AMDCIsDMARing::gMetaClass 00000000003b4388 __float128 0f SECT 08 0000 [.const_data] AMDCIsDMARing::superClass 000000000007a7ba __float128 0f SECT 01 0000 [.text] AMDCIsDMARing::registerLocation() 000000000007a8f0 __float128 0f SECT 01 0000 [.text] AMDCIsDMARing::enableReadPointerWriteBack() 000000000007a8f6 __float128 0f SECT 01 0000 [.text] AMDCIsDMARing::disableReadPointerWriteBack() 000000000007a848 __float128 0f SECT 01 0000 [.text] AMDCIsDMARing::programReadAndWritePointers(unsigned int) 000000000007a6e8 __float128 0f SECT 01 0000 [.text] AMDCIsDMARing::free() 000000000007a562 __float128 0f SECT 01 0000 [.text] AMDCIsDMARing::init(AMDRadeonX4000_IAMDHWInterface*, int, _eAMD_HW_ENGINE_TYPE, unsigned int, void const*) 000000000007a8c2 __float128 0f SECT 01 0000 [.text] AMDCIsDMARing::align() 000000000007a7e4 __float128 0f SECT 01 0000 [.text] AMDCIsDMARing::reset() 000000000007a6fa __float128 0f SECT 01 0000 [.text] AMDCIsDMARing::enable() 000000000007a774 __float128 0f SECT 01 0000 [.text] AMDCIsDMARing::disable() 000000000007a784 __float128 0f SECT 01 0000 [.text] AMDCIsDMARing::getHead() 000000000007a3d0 __float128 0f SECT 01 0000 [.text] AMDCIsDMARing::MetaClass::MetaClass() 000000000007a490 __float128 0f SECT 01 0000 [.text] AMDCIsDMARing::MetaClass::MetaClass() 00000000003b4380 __float128 0f SECT 08 0000 [.const_data] AMDCIsDMARing::metaClass 000000000007a42c __float128 0f SECT 01 0000 [.text] AMDCIsDMARing::AMDCIsDMARing(OSMetaClass const*) 000000000007a502 __float128 0f SECT 01 0000 [.text] AMDCIsDMARing::AMDCIsDMARing() 000000000007a40c __float128 0f SECT 01 0000 [.text] AMDCIsDMARing::AMDCIsDMARing(OSMetaClass const*) 000000000007a532 __float128 0f SECT 01 0000 [.text] AMDCIsDMARing::AMDCIsDMARing() 000000000007a460 __float128 0f SECT 01 0000 [.text] AMDCIsDMARing::~AMDCIsDMARing() 000000000007a456 __float128 0f SECT 01 0000 [.text] AMDCIsDMARing::~AMDCIsDMARing() 000000000007a44c __float128 0f SECT 01 0000 [.text] AMDCIsDMARing::~AMDCIsDMARing() 000000000052e008 __float128 0f SECT 0a 0000 [__DATA.__common] AMDSIHWMemory::gMetaClass 00000000003aa678 __float128 0f SECT 08 0000 [.const_data] AMDSIHWMemory::superClass 0000000000062cd6 __float128 0f SECT 01 0000 [.text] AMDSIHWMemory::getHWMemorySize() 0000000000062d08 __float128 0f SECT 01 0000 [.text] AMDSIHWMemory::getHWMemoryApertureSize() 0000000000062cc2 __float128 0f SECT 01 0000 [.text] AMDSIHWMemory::init(AMDRadeonX4000_IAMDHWInterface*) 0000000000062d3a __float128 0f SECT 01 0000 [.text] AMDSIHWMemory::prepare(AMDRadeonX4000_AMDAccelResource*, unsigned long long, unsigned long long, unsigned long long*) 00000000000630ac __float128 0f SECT 01 0000 [.text] AMDSIHWMemory::complete(AMDRadeonX4000_AMDAccelResource*) 0000000000062b30 __float128 0f SECT 01 0000 [.text] AMDSIHWMemory::MetaClass::MetaClass() 0000000000062bf0 __float128 0f SECT 01 0000 [.text] AMDSIHWMemory::MetaClass::MetaClass() 00000000003aa670 __float128 0f SECT 08 0000 [.const_data] AMDSIHWMemory::metaClass 0000000000062b8c __float128 0f SECT 01 0000 [.text] AMDSIHWMemory::AMDSIHWMemory(OSMetaClass const*) 0000000000062c62 __float128 0f SECT 01 0000 [.text] AMDSIHWMemory::AMDSIHWMemory() 0000000000062b6c __float128 0f SECT 01 0000 [.text] AMDSIHWMemory::AMDSIHWMemory(OSMetaClass const*) 0000000000062c92 __float128 0f SECT 01 0000 [.text] AMDSIHWMemory::AMDSIHWMemory() 0000000000062bc0 __float128 0f SECT 01 0000 [.text] AMDSIHWMemory::~AMDSIHWMemory() 0000000000062bb6 __float128 0f SECT 01 0000 [.text] AMDSIHWMemory::~AMDSIHWMemory() 0000000000062bac __float128 0f SECT 01 0000 [.text] AMDSIHWMemory::~AMDSIHWMemory() 0000000000069824 __float128 0f SECT 01 0000 [.text] AMDSIHardware::disableDPM() 000000000052e0d0 __float128 0f SECT 0a 0000 [__DATA.__common] AMDSIHardware::gMetaClass 00000000000673e6 __float128 0f SECT 01 0000 [.text] AMDSIHardware::initHWInfo() 00000000003ab6b8 __float128 0f SECT 08 0000 [.const_data] AMDSIHardware::superClass 0000000000066e8a __float128 0f SECT 01 0000 [.text] AMDSIHardware::allocateSML() 0000000000069806 __float128 0f SECT 01 0000 [.text] AMDSIHardware::isDPMEnabled() 0000000000067bb6 __float128 0f SECT 01 0000 [.text] AMDSIHardware::enableContext(unsigned int, bool) 00000000000672cc __float128 0f SECT 01 0000 [.text] AMDSIHardware::flushHDPCache() 00000000000675ae __float128 0f SECT 01 0000 [.text] AMDSIHardware::initializeGUI() 0000000000066eb0 __float128 0f SECT 01 0000 [.text] AMDSIHardware::allocateAMDHWVMM() 0000000000066d58 __float128 0f SECT 01 0000 [.text] AMDSIHardware::getOGLBundleName() 000000000006730e __float128 0f SECT 01 0000 [.text] AMDSIHardware::initMaskSettings() 0000000000067a4c __float128 0f SECT 01 0000 [.text] AMDSIHardware::initializeVMRegs() 000000000006713c __float128 0f SECT 01 0000 [.text] AMDSIHardware::allocateHWEngines() 0000000000068a68 __float128 0f SECT 01 0000 [.text] AMDSIHardware::dumpASICHangState(bool) 00000000000673bc __float128 0f SECT 01 0000 [.text] AMDSIHardware::getCoherCntrValue(bool, bool, bool) 0000000000067a24 __float128 0f SECT 01 0000 [.text] AMDSIHardware::initializeTlbRegs() 000000000006761c __float128 0f SECT 01 0000 [.text] AMDSIHardware::enableTransactions() 0000000000067424 __float128 0f SECT 01 0000 [.text] AMDSIHardware::getAMDHwInfoValues(_sAMD_GET_HW_INFO_VALUES*) 0000000000066da4 __float128 0f SECT 01 0000 [.text] AMDSIHardware::getMemSizeRegister() 00000000000672ae __float128 0f SECT 01 0000 [.text] AMDSIHardware::readHWChipRevValue() 0000000000066dca __float128 0f SECT 01 0000 [.text] AMDSIHardware::setMemSizeRegister(unsigned int) 0000000000067876 __float128 0f SECT 01 0000 [.text] AMDSIHardware::setupInternalSpace() 0000000000066d2c __float128 0f SECT 01 0000 [.text] AMDSIHardware::writeOCDBundleName() 0000000000066e18 __float128 0f SECT 01 0000 [.text] AMDSIHardware::allocateAMDHWMemory() 00000000000675d0 __float128 0f SECT 01 0000 [.text] AMDSIHardware::disableTransactions() 00000000000676ac __float128 0f SECT 01 0000 [.text] AMDSIHardware::fillNDRVSurfaceInfo(_AMD_SURFACE_INFO_STRUCT*, _ADDR_TILEINFO*) 0000000000066df2 __float128 0f SECT 01 0000 [.text] AMDSIHardware::getRegisterAperSize() 0000000000067cbe __float128 0f SECT 01 0000 [.text] AMDSIHardware::initializeCacheRegs() 00000000000672fe __float128 0f SECT 01 0000 [.text] AMDSIHardware::initializeGFXEngine() 0000000000067f10 __float128 0f SECT 01 0000 [.text] AMDSIHardware::verifyThreadsActive() 0000000000066e3e __float128 0f SECT 01 0000 [.text] AMDSIHardware::allocateAMDHWDisplay() 00000000000672ee __float128 0f SECT 01 0000 [.text] AMDSIHardware::initializeFamilyType() 0000000000066fb4 __float128 0f SECT 01 0000 [.text] AMDSIHardware::readHWGBTilingConfig() 0000000000068e62 __float128 0f SECT 01 0000 [.text] AMDSIHardware::writeASICHangLogInfo(_AMD_ASIC_HANG_LOG_INFO*) 00000000000690e6 __float128 0f SECT 01 0000 [.text] AMDSIHardware::writeDiagnosisReport(char*&, unsigned int&) 0000000000069768 __float128 0f SECT 01 0000 [.text] AMDSIHardware::writeQSCRegMemTimeout(unsigned int*, unsigned int) 0000000000066f1c __float128 0f SECT 01 0000 [.text] AMDSIHardware::allocateAMDHWUtilities() 0000000000066d98 __float128 0f SECT 01 0000 [.text] AMDSIHardware::getATIDisplayConfigBit() 0000000000066d66 __float128 0f SECT 01 0000 [.text] AMDSIHardware::createAtomicBlitManager() 0000000000066f42 __float128 0f SECT 01 0000 [.text] AMDSIHardware::initializeHWWorkarounds() 0000000000067908 __float128 0f SECT 01 0000 [.text] AMDSIHardware::initializePageTableRegs() 0000000000069788 __float128 0f SECT 01 0000 [.text] AMDSIHardware::setPerformanceLevelHigh() 0000000000066fd2 __float128 0f SECT 01 0000 [.text] AMDSIHardware::getHardwareDefaultValues(_sAMD_HW_DEFAULT_VALUES*) 0000000000066ef6 __float128 0f SECT 01 0000 [.text] AMDSIHardware::allocateAMDHWAlignManager() 0000000000068930 __float128 0f SECT 01 0000 [.text] AMDSIHardware::dumpASicHangLogIntoSyslog(_AMD_ASIC_HANG_LOG_INFO*) 0000000000066c90 __float128 0f SECT 01 0000 [.text] AMDSIHardware::getFrameBufferBaseAddress() 0000000000067c24 __float128 0f SECT 01 0000 [.text] AMDSIHardware::programPageTableRegisters(AMD_VM_PAGE_TABLE_INFO*, unsigned int) 0000000000066cae __float128 0f SECT 01 0000 [.text] AMDSIHardware::writeWaitForRenderingPipe(unsigned int*, bool) 0000000000066e64 __float128 0f SECT 01 0000 [.text] AMDSIHardware::allocatePM4CommandsUtility() 0000000000067d74 __float128 0f SECT 01 0000 [.text] AMDSIHardware::initializeGartApertureRegs() 0000000000067228 __float128 0f SECT 01 0000 [.text] AMDSIHardware::invalidateAllTLBsAndCaches(bool, unsigned int) 000000000006886e __float128 0f SECT 01 0000 [.text] AMDSIHardware::asicHangReadROQandMEQStatus(amdAsicHangDumpROQMEQStatus&) 0000000000067efa __float128 0f SECT 01 0000 [.text] AMDSIHardware::setMemoryAllocationsEnabled(bool) 000000000006872c __float128 0f SECT 01 0000 [.text] AMDSIHardware::asicHangLogDumpMeStateQueues(_AMD_ASIC_HANG_LOG_INFO*) 0000000000068558 __float128 0f SECT 01 0000 [.text] AMDSIHardware::asicHangLogDumpReorderQueues(_AMD_ASIC_HANG_LOG_INFO*) 00000000000678e6 __float128 0f SECT 01 0000 [.text] AMDSIHardware::initializeHDPPathWorkarounds() 0000000000067e16 __float128 0f SECT 01 0000 [.text] AMDSIHardware::initializeSystemApertureRegs() 0000000000066d8c __float128 0f SECT 01 0000 [.text] AMDSIHardware::getMMRPCIConfigBaseAddressOffset() 0000000000066ff6 __float128 0f SECT 01 0000 [.text] AMDSIHardware::setupAndInitializeHWCapabilities() 0000000000069658 __float128 0f SECT 01 0000 [.text] AMDSIHardware::stallGPUDuringScanLineRangeSetup(unsigned int, unsigned int, unsigned int, unsigned int, unsigned short, unsigned short) 000000000006851c __float128 0f SECT 01 0000 [.text] AMDSIHardware::getRequiredAsicHangLogDumpRegisters(unsigned int&) 0000000000068544 __float128 0f SECT 01 0000 [.text] AMDSIHardware::getRequiredAsicHangLogDumpMeStateQueueRegisters(unsigned int&) 0000000000068530 __float128 0f SECT 01 0000 [.text] AMDSIHardware::getRequiredAsicHangLogDumpReorderQueueRegisters(unsigned int&) 0000000000066c50 __float128 0f SECT 01 0000 [.text] AMDSIHardware::free() 0000000000066bea __float128 0f SECT 01 0000 [.text] AMDSIHardware::init(IOPCIDevice*, AMDRadeonX4000_IAMDHWHandler*, unsigned int&, unsigned int, _GART_PARAMETERS*, _FB_PARAMETERS*) 0000000000067370 __float128 0f SECT 01 0000 [.text] AMDSIHardware::powerUp() 00000000000673aa __float128 0f SECT 01 0000 [.text] AMDSIHardware::powerOff() 0000000000066b10 __float128 0f SECT 01 0000 [.text] AMDSIHardware::MetaClass::MetaClass() 0000000000066bb0 __float128 0f SECT 01 0000 [.text] AMDSIHardware::MetaClass::MetaClass() 00000000000698b6 __float128 0f SECT 01 0000 [.text] AMDSIHardware::enableDPM() 00000000003ab6b0 __float128 0f SECT 08 0000 [.const_data] AMDSIHardware::metaClass 0000000000066b4c __float128 0f SECT 01 0000 [.text] AMDSIHardware::AMDSIHardware(OSMetaClass const*) 0000000000066b80 __float128 0f SECT 01 0000 [.text] AMDSIHardware::~AMDSIHardware() 0000000000066b76 __float128 0f SECT 01 0000 [.text] AMDSIHardware::~AMDSIHardware() 0000000000066b6c __float128 0f SECT 01 0000 [.text] AMDSIHardware::~AMDSIHardware() 000000000052d630 __float128 0f SECT 0a 0000 [__DATA.__common] AMDSIResource::gMetaClass 00000000003972b8 __float128 0f SECT 08 0000 [.const_data] AMDSIResource::superClass 000000000002a864 __float128 0f SECT 01 0000 [.text] AMDSIResource::getPagingChannel(bool) 000000000002a41c __float128 0f SECT 01 0000 [.text] AMDSIResource::fillUBMSurfaceInfoInternal(_UBM_SURFINFO*, _sMASK_MEMORY_SETTINGS*, IOAccelMemoryMap*, AMDRadeonX4000_AMDAccelResource*, unsigned int, unsigned int, unsigned int) 000000000002a3a2 __float128 0f SECT 01 0000 [.text] AMDSIResource::init(IOGraphicsAccelerator2*, IOAccelShared2*, unsigned int) 000000000002a210 __float128 0f SECT 01 0000 [.text] AMDSIResource::MetaClass::MetaClass() 000000000002a2d0 __float128 0f SECT 01 0000 [.text] AMDSIResource::MetaClass::MetaClass() 00000000003972b0 __float128 0f SECT 08 0000 [.const_data] AMDSIResource::metaClass 000000000002a26c __float128 0f SECT 01 0000 [.text] AMDSIResource::AMDSIResource(OSMetaClass const*) 000000000002a342 __float128 0f SECT 01 0000 [.text] AMDSIResource::AMDSIResource() 000000000002a24c __float128 0f SECT 01 0000 [.text] AMDSIResource::AMDSIResource(OSMetaClass const*) 000000000002a372 __float128 0f SECT 01 0000 [.text] AMDSIResource::AMDSIResource() 000000000002a2a0 __float128 0f SECT 01 0000 [.text] AMDSIResource::~AMDSIResource() 000000000002a296 __float128 0f SECT 01 0000 [.text] AMDSIResource::~AMDSIResource() 000000000002a28c __float128 0f SECT 01 0000 [.text] AMDSIResource::~AMDSIResource() 000000000052e990 __float128 0f SECT 0a 0000 [__DATA.__common] AMDVIHWMemory::gMetaClass 00000000003b9be8 __float128 0f SECT 08 0000 [.const_data] AMDVIHWMemory::superClass 00000000000877d4 __float128 0f SECT 01 0000 [.text] AMDVIHWMemory::getHWMemorySize() 0000000000087806 __float128 0f SECT 01 0000 [.text] AMDVIHWMemory::getHWMemoryApertureSize() 00000000000877c2 __float128 0f SECT 01 0000 [.text] AMDVIHWMemory::init(AMDRadeonX4000_IAMDHWInterface*) 0000000000087838 __float128 0f SECT 01 0000 [.text] AMDVIHWMemory::prepare(AMDRadeonX4000_AMDAccelResource*, unsigned long long, unsigned long long, unsigned long long*) 0000000000087b32 __float128 0f SECT 01 0000 [.text] AMDVIHWMemory::complete(AMDRadeonX4000_AMDAccelResource*) 0000000000087630 __float128 0f SECT 01 0000 [.text] AMDVIHWMemory::MetaClass::MetaClass() 00000000000876f0 __float128 0f SECT 01 0000 [.text] AMDVIHWMemory::MetaClass::MetaClass() 00000000003b9be0 __float128 0f SECT 08 0000 [.const_data] AMDVIHWMemory::metaClass 000000000008768c __float128 0f SECT 01 0000 [.text] AMDVIHWMemory::AMDVIHWMemory(OSMetaClass const*) 0000000000087762 __float128 0f SECT 01 0000 [.text] AMDVIHWMemory::AMDVIHWMemory() 000000000008766c __float128 0f SECT 01 0000 [.text] AMDVIHWMemory::AMDVIHWMemory(OSMetaClass const*) 0000000000087792 __float128 0f SECT 01 0000 [.text] AMDVIHWMemory::AMDVIHWMemory() 00000000000876c0 __float128 0f SECT 01 0000 [.text] AMDVIHWMemory::~AMDVIHWMemory() 00000000000876b6 __float128 0f SECT 01 0000 [.text] AMDVIHWMemory::~AMDVIHWMemory() 00000000000876ac __float128 0f SECT 01 0000 [.text] AMDVIHWMemory::~AMDVIHWMemory() 0000000000086898 __float128 0f SECT 01 0000 [.text] AMDVIHardware::disableDPM() 000000000052e918 __float128 0f SECT 0a 0000 [__DATA.__common] AMDVIHardware::gMetaClass 0000000000084780 __float128 0f SECT 01 0000 [.text] AMDVIHardware::initHWInfo() 00000000003b8aa8 __float128 0f SECT 08 0000 [.const_data] AMDVIHardware::superClass 00000000000841ea __float128 0f SECT 01 0000 [.text] AMDVIHardware::allocateSML() 0000000000086890 __float128 0f SECT 01 0000 [.text] AMDVIHardware::isDPMEnabled() 0000000000084f82 __float128 0f SECT 01 0000 [.text] AMDVIHardware::enableContext(unsigned int, bool) 000000000008468e __float128 0f SECT 01 0000 [.text] AMDVIHardware::flushHDPCache() 0000000000084984 __float128 0f SECT 01 0000 [.text] AMDVIHardware::initializeGUI() 0000000000084210 __float128 0f SECT 01 0000 [.text] AMDVIHardware::allocateAMDHWVMM() 00000000000840b8 __float128 0f SECT 01 0000 [.text] AMDVIHardware::getOGLBundleName() 00000000000846d0 __float128 0f SECT 01 0000 [.text] AMDVIHardware::initMaskSettings() 0000000000084e18 __float128 0f SECT 01 0000 [.text] AMDVIHardware::initializeVMRegs() 00000000000842a2 __float128 0f SECT 01 0000 [.text] AMDVIHardware::allocateAMDHWGart() 00000000000844e8 __float128 0f SECT 01 0000 [.text] AMDVIHardware::allocateHWEngines() 0000000000085ee8 __float128 0f SECT 01 0000 [.text] AMDVIHardware::dumpASICHangState(bool) 0000000000084756 __float128 0f SECT 01 0000 [.text] AMDVIHardware::getCoherCntrValue(bool, bool, bool) 0000000000084df0 __float128 0f SECT 01 0000 [.text] AMDVIHardware::initializeTlbRegs() 00000000000849f2 __float128 0f SECT 01 0000 [.text] AMDVIHardware::enableTransactions() 00000000000847be __float128 0f SECT 01 0000 [.text] AMDVIHardware::getAMDHwInfoValues(_sAMD_GET_HW_INFO_VALUES*) 0000000000084104 __float128 0f SECT 01 0000 [.text] AMDVIHardware::getMemSizeRegister() 0000000000084670 __float128 0f SECT 01 0000 [.text] AMDVIHardware::readHWChipRevValue() 000000000008412a __float128 0f SECT 01 0000 [.text] AMDVIHardware::setMemSizeRegister(unsigned int) 0000000000084c2c __float128 0f SECT 01 0000 [.text] AMDVIHardware::setupInternalSpace() 000000000008408c __float128 0f SECT 01 0000 [.text] AMDVIHardware::writeOCDBundleName() 0000000000084178 __float128 0f SECT 01 0000 [.text] AMDVIHardware::allocateAMDHWMemory() 00000000000849a6 __float128 0f SECT 01 0000 [.text] AMDVIHardware::disableTransactions() 0000000000084a82 __float128 0f SECT 01 0000 [.text] AMDVIHardware::fillNDRVSurfaceInfo(_AMD_SURFACE_INFO_STRUCT*, _ADDR_TILEINFO*) 00000000000859cc __float128 0f SECT 01 0000 [.text] AMDVIHardware::freeWritebackMemory() 0000000000084152 __float128 0f SECT 01 0000 [.text] AMDVIHardware::getRegisterAperSize() 000000000008508a __float128 0f SECT 01 0000 [.text] AMDVIHardware::initializeCacheRegs() 00000000000846c0 __float128 0f SECT 01 0000 [.text] AMDVIHardware::initializeGFXEngine() 000000000008533e __float128 0f SECT 01 0000 [.text] AMDVIHardware::verifyThreadsActive() 000000000008419e __float128 0f SECT 01 0000 [.text] AMDVIHardware::allocateAMDHWDisplay() 00000000000846b0 __float128 0f SECT 01 0000 [.text] AMDVIHardware::initializeFamilyType() 000000000008433a __float128 0f SECT 01 0000 [.text] AMDVIHardware::readHWGBTilingConfig() 0000000000086230 __float128 0f SECT 01 0000 [.text] AMDVIHardware::writeASICHangLogInfo(_AMD_ASIC_HANG_LOG_INFO*) 00000000000864b4 __float128 0f SECT 01 0000 [.text] AMDVIHardware::writeDiagnosisReport(char*&, unsigned int&) 00000000000867b6 __float128 0f SECT 01 0000 [.text] AMDVIHardware::writeQSCRegMemTimeout(unsigned int*, unsigned int) 000000000008427c __float128 0f SECT 01 0000 [.text] AMDVIHardware::allocateAMDHWUtilities() 00000000000840f8 __float128 0f SECT 01 0000 [.text] AMDVIHardware::getATIDisplayConfigBit() 0000000000085948 __float128 0f SECT 01 0000 [.text] AMDVIHardware::allocateWritebackMemory() 00000000000840c6 __float128 0f SECT 01 0000 [.text] AMDVIHardware::createAtomicBlitManager() 00000000000842c8 __float128 0f SECT 01 0000 [.text] AMDVIHardware::initializeHWWorkarounds() 0000000000084cbe __float128 0f SECT 01 0000 [.text] AMDVIHardware::initializePageTableRegs() 0000000000086810 __float128 0f SECT 01 0000 [.text] AMDVIHardware::setPerformanceLevelHigh() 0000000000084358 __float128 0f SECT 01 0000 [.text] AMDVIHardware::getHardwareDefaultValues(_sAMD_HW_DEFAULT_VALUES*) 0000000000084256 __float128 0f SECT 01 0000 [.text] AMDVIHardware::allocateAMDHWAlignManager() 0000000000085e74 __float128 0f SECT 01 0000 [.text] AMDVIHardware::dumpASicHangLogIntoSyslog(_AMD_ASIC_HANG_LOG_INFO*) 0000000000083fd0 __float128 0f SECT 01 0000 [.text] AMDVIHardware::getFrameBufferBaseAddress() 0000000000084ff0 __float128 0f SECT 01 0000 [.text] AMDVIHardware::programPageTableRegisters(AMD_VM_PAGE_TABLE_INFO*, unsigned int) 0000000000083fee __float128 0f SECT 01 0000 [.text] AMDVIHardware::writeWaitForRenderingPipe(unsigned int*, bool) 00000000000841c4 __float128 0f SECT 01 0000 [.text] AMDVIHardware::allocatePM4CommandsUtility() 0000000000085140 __float128 0f SECT 01 0000 [.text] AMDVIHardware::initializeGartApertureRegs() 00000000000845ea __float128 0f SECT 01 0000 [.text] AMDVIHardware::invalidateAllTLBsAndCaches(bool, unsigned int) 0000000000085daa __float128 0f SECT 01 0000 [.text] AMDVIHardware::asicHangReadROQandMEQStatus(amdAsicHangDumpROQMEQStatus&) 0000000000085328 __float128 0f SECT 01 0000 [.text] AMDVIHardware::setMemoryAllocationsEnabled(bool) 0000000000085c36 __float128 0f SECT 01 0000 [.text] AMDVIHardware::asicHangLogDumpMeStateQueues(_AMD_ASIC_HANG_LOG_INFO*) 0000000000085a82 __float128 0f SECT 01 0000 [.text] AMDVIHardware::asicHangLogDumpReorderQueues(_AMD_ASIC_HANG_LOG_INFO*) 0000000000084c9c __float128 0f SECT 01 0000 [.text] AMDVIHardware::initializeHDPPathWorkarounds() 0000000000085244 __float128 0f SECT 01 0000 [.text] AMDVIHardware::initializeSystemApertureRegs() 0000000000085a2a __float128 0f SECT 01 0000 [.text] AMDVIHardware::getChannelWritePointerPollAddr(int) 0000000000085a12 __float128 0f SECT 01 0000 [.text] AMDVIHardware::getChannelWritePointerPollOffset(int) 00000000000840ec __float128 0f SECT 01 0000 [.text] AMDVIHardware::getMMRPCIConfigBaseAddressOffset() 000000000008437c __float128 0f SECT 01 0000 [.text] AMDVIHardware::setupAndInitializeHWCapabilities() 00000000000866a6 __float128 0f SECT 01 0000 [.text] AMDVIHardware::stallGPUDuringScanLineRangeSetup(unsigned int, unsigned int, unsigned int, unsigned int, unsigned short, unsigned short) 0000000000085a46 __float128 0f SECT 01 0000 [.text] AMDVIHardware::getRequiredAsicHangLogDumpRegisters(unsigned int&) 0000000000085a6e __float128 0f SECT 01 0000 [.text] AMDVIHardware::getRequiredAsicHangLogDumpMeStateQueueRegisters(unsigned int&) 0000000000085a5a __float128 0f SECT 01 0000 [.text] AMDVIHardware::getRequiredAsicHangLogDumpReorderQueueRegisters(unsigned int&) 0000000000083f90 __float128 0f SECT 01 0000 [.text] AMDVIHardware::free() 0000000000083f0a __float128 0f SECT 01 0000 [.text] AMDVIHardware::init(IOPCIDevice*, AMDRadeonX4000_IAMDHWHandler*, unsigned int&, unsigned int, _GART_PARAMETERS*, _FB_PARAMETERS*) 0000000000084732 __float128 0f SECT 01 0000 [.text] AMDVIHardware::powerUp() 0000000000084744 __float128 0f SECT 01 0000 [.text] AMDVIHardware::powerOff() 0000000000083e30 __float128 0f SECT 01 0000 [.text] AMDVIHardware::MetaClass::MetaClass() 0000000000083ed0 __float128 0f SECT 01 0000 [.text] AMDVIHardware::MetaClass::MetaClass() 000000000008689e __float128 0f SECT 01 0000 [.text] AMDVIHardware::enableDPM() 00000000003b8aa0 __float128 0f SECT 08 0000 [.const_data] AMDVIHardware::metaClass 0000000000083e6c __float128 0f SECT 01 0000 [.text] AMDVIHardware::AMDVIHardware(OSMetaClass const*) 0000000000083ea0 __float128 0f SECT 01 0000 [.text] AMDVIHardware::~AMDVIHardware() 0000000000083e96 __float128 0f SECT 01 0000 [.text] AMDVIHardware::~AMDVIHardware() 0000000000083e8c __float128 0f SECT 01 0000 [.text] AMDVIHardware::~AMDVIHardware() 000000000052d838 __float128 0f SECT 0a 0000 [__DATA.__common] AMDVIResource::gMetaClass 00000000003a0368 __float128 0f SECT 08 0000 [.const_data] AMDVIResource::superClass 0000000000047b3e __float128 0f SECT 01 0000 [.text] AMDVIResource::getPagingChannel(bool) 0000000000047482 __float128 0f SECT 01 0000 [.text] AMDVIResource::pageOffMSAADepthBuffer(_UBM_SURFINFO*, _UBM_SURFINFO*, IOAccelMemoryMap*, IOAccelMemoryMap*, _UBM_RECTL*, _UBM_RECTL*, unsigned int, unsigned int) 0000000000047128 __float128 0f SECT 01 0000 [.text] AMDVIResource::fillUBMSurfaceInfoInternal(_UBM_SURFINFO*, _sMASK_MEMORY_SETTINGS*, IOAccelMemoryMap*, AMDRadeonX4000_AMDAccelResource*, unsigned int, unsigned int, unsigned int) 00000000000470f2 __float128 0f SECT 01 0000 [.text] AMDVIResource::init(IOGraphicsAccelerator2*, IOAccelShared2*, unsigned int) 0000000000046f60 __float128 0f SECT 01 0000 [.text] AMDVIResource::MetaClass::MetaClass() 0000000000047020 __float128 0f SECT 01 0000 [.text] AMDVIResource::MetaClass::MetaClass() 00000000003a0360 __float128 0f SECT 08 0000 [.const_data] AMDVIResource::metaClass 0000000000046fbc __float128 0f SECT 01 0000 [.text] AMDVIResource::AMDVIResource(OSMetaClass const*) 0000000000047092 __float128 0f SECT 01 0000 [.text] AMDVIResource::AMDVIResource() 0000000000046f9c __float128 0f SECT 01 0000 [.text] AMDVIResource::AMDVIResource(OSMetaClass const*) 00000000000470c2 __float128 0f SECT 01 0000 [.text] AMDVIResource::AMDVIResource() 0000000000046ff0 __float128 0f SECT 01 0000 [.text] AMDVIResource::~AMDVIResource() 0000000000046fe6 __float128 0f SECT 01 0000 [.text] AMDVIResource::~AMDVIResource() 0000000000046fdc __float128 0f SECT 01 0000 [.text] AMDVIResource::~AMDVIResource() 000000000052eaa8 __float128 0f SECT 0a 0000 [__DATA.__common] AMDVIsDMARing::gMetaClass 00000000003bb368 __float128 0f SECT 08 0000 [.const_data] AMDVIsDMARing::superClass 000000000008d1e0 __float128 0f SECT 01 0000 [.text] AMDVIsDMARing::registerLocation() 000000000008d1ce __float128 0f SECT 01 0000 [.text] AMDVIsDMARing::allocateResources() 000000000008d316 __float128 0f SECT 01 0000 [.text] AMDVIsDMARing::enableReadPointerWriteBack() 000000000008d31c __float128 0f SECT 01 0000 [.text] AMDVIsDMARing::disableReadPointerWriteBack() 000000000008d26e __float128 0f SECT 01 0000 [.text] AMDVIsDMARing::programReadAndWritePointers(unsigned int) 000000000008d0fc __float128 0f SECT 01 0000 [.text] AMDVIsDMARing::free() 000000000008d012 __float128 0f SECT 01 0000 [.text] AMDVIsDMARing::init(AMDRadeonX4000_IAMDHWInterface*, int, _eAMD_HW_ENGINE_TYPE, unsigned int, void const*) 000000000008d2e8 __float128 0f SECT 01 0000 [.text] AMDVIsDMARing::align() 000000000008d20a __float128 0f SECT 01 0000 [.text] AMDVIsDMARing::reset() 000000000008d10e __float128 0f SECT 01 0000 [.text] AMDVIsDMARing::enable() 000000000008d188 __float128 0f SECT 01 0000 [.text] AMDVIsDMARing::disable() 000000000008d198 __float128 0f SECT 01 0000 [.text] AMDVIsDMARing::getHead() 000000000008ce80 __float128 0f SECT 01 0000 [.text] AMDVIsDMARing::MetaClass::MetaClass() 000000000008cf40 __float128 0f SECT 01 0000 [.text] AMDVIsDMARing::MetaClass::MetaClass() 00000000003bb360 __float128 0f SECT 08 0000 [.const_data] AMDVIsDMARing::metaClass 000000000008d322 __float128 0f SECT 01 0000 [.text] AMDVIsDMARing::writeTail() 000000000008cedc __float128 0f SECT 01 0000 [.text] AMDVIsDMARing::AMDVIsDMARing(OSMetaClass const*) 000000000008cfb2 __float128 0f SECT 01 0000 [.text] AMDVIsDMARing::AMDVIsDMARing() 000000000008cebc __float128 0f SECT 01 0000 [.text] AMDVIsDMARing::AMDVIsDMARing(OSMetaClass const*) 000000000008cfe2 __float128 0f SECT 01 0000 [.text] AMDVIsDMARing::AMDVIsDMARing() 000000000008cf10 __float128 0f SECT 01 0000 [.text] AMDVIsDMARing::~AMDVIsDMARing() 000000000008cf06 __float128 0f SECT 01 0000 [.text] AMDVIsDMARing::~AMDVIsDMARing() 000000000008cefc __float128 0f SECT 01 0000 [.text] AMDVIsDMARing::~AMDVIsDMARing() 00000000000ab2ba __float128 0f SECT 01 0000 [.text] SiBltConstMgr::SetAluConstants(_UBM_SHADER_TYPE, unsigned int, unsigned int, _UBM_VECTOR const*, unsigned int) 00000000000ab356 __float128 0f SECT 01 0000 [.text] SiBltConstMgr::SetAluConstants(_UBM_SHADER_TYPE, unsigned int, unsigned int, _UBM_VECTORL const*, unsigned int) 00000000000abb3a __float128 0f SECT 01 0000 [.text] SiBltConstMgr::SetupUavConstant(SiBltDevice*, _UBM_SHADER_TYPE, _UBM_SURFINFO const*, unsigned int) 00000000000ab9f0 __float128 0f SECT 01 0000 [.text] SiBltConstMgr::SetSamplerDeGamma(_UBM_SHADER_TYPE, unsigned int) 00000000000ab360 __float128 0f SECT 01 0000 [.text] SiBltConstMgr::SetupRsrcConstant(SiBltDevice*, _UBM_SHADER_TYPE, _UBM_SURFINFO const*, SiBltRsrcConstInfo const*, unsigned int) 00000000000abbee __float128 0f SECT 01 0000 [.text] SiBltConstMgr::WriteImmedAluConst(SiBltDevice*, _UBM_SHADER_TYPE, unsigned int, unsigned int, unsigned int, unsigned int) 00000000000abf20 __float128 0f SECT 01 0000 [.text] SiBltConstMgr::WriteImmedUavConst(SiBltDevice*, _UBM_SHADER_TYPE, unsigned int, unsigned int, unsigned int) 00000000000aba48 __float128 0f SECT 01 0000 [.text] SiBltConstMgr::SetSamplerClampType(_UBM_SHADER_TYPE, unsigned int, SQ_TEX_CLAMP) 00000000000abdac __float128 0f SECT 01 0000 [.text] SiBltConstMgr::WriteImmedRsrcConst(SiBltDevice*, _UBM_SHADER_TYPE, unsigned int, unsigned int, unsigned int) 00000000000ac000 __float128 0f SECT 01 0000 [.text] SiBltConstMgr::WriteImmedSampConst(SiBltDevice*, _UBM_SHADER_TYPE, unsigned int, unsigned int, unsigned int) 00000000000abab8 __float128 0f SECT 01 0000 [.text] SiBltConstMgr::SetSamplerFilterMode(_UBM_SHADER_TYPE, unsigned int, unsigned int, SQ_TEX_XY_FILTER) 00000000000ab5a8 __float128 0f SECT 01 0000 [.text] SiBltConstMgr::SetupBufRsrcConstant(SiBltDevice*, _UBM_SURFINFO const*, SqBufRsrc*) 00000000000ab6fc __float128 0f SECT 01 0000 [.text] SiBltConstMgr::SetupImgRsrcConstant(SiBltDevice*, _UBM_SURFINFO const*, SiBltRsrcConstInfo const*, SqImgRsrc*, unsigned int, _UBM_MASKRAMINFO const*) 00000000000ac2f8 __float128 0f SECT 01 0000 [.text] SiBltConstMgr::WriteEmbeddedUavTable(SiBltDevice*, _UBM_SHADER_TYPE, unsigned int, unsigned int, unsigned int) 00000000000abc7a __float128 0f SECT 01 0000 [.text] SiBltConstMgr::WriteImmedConstBuffer(SiBltDevice*, _UBM_SHADER_TYPE, unsigned int, unsigned int, unsigned int) 00000000000ab50a __float128 0f SECT 01 0000 [.text] SiBltConstMgr::GetTcCompatibleMaskRam(SiBltDevice*, _UBM_SURFINFO const*) 00000000000ac04c __float128 0f SECT 01 0000 [.text] SiBltConstMgr::WriteEmbeddedRsrcTable(SiBltDevice*, _UBM_SHADER_TYPE, unsigned int, unsigned int, unsigned int) 00000000000ac256 __float128 0f SECT 01 0000 [.text] SiBltConstMgr::WriteEmbeddedSampTable(SiBltDevice*, _UBM_SHADER_TYPE, unsigned int, unsigned int, unsigned int) 00000000000ab23e __float128 0f SECT 01 0000 [.text] SiBltConstMgr::SetDefaultSamplerConstant(_UBM_SHADER_TYPE, unsigned int) 00000000000ab128 __float128 0f SECT 01 0000 [.text] SiBltConstMgr::InitBlt() 00000000000ab122 __float128 0f SECT 01 0000 [.text] SiBltConstMgr::SiBltConstMgr() 00000000000ab11c __float128 0f SECT 01 0000 [.text] SiBltConstMgr::SiBltConstMgr() 00000000000b4400 __float128 0f SECT 01 0000 [.text] SiBltDrawRegs::SetupZExpand(BltInfo const*) 00000000000b449a __float128 0f SECT 01 0000 [.text] SiBltDrawRegs::SetupZExport(BltInfo const*) 00000000000b41f6 __float128 0f SECT 01 0000 [.text] SiBltDrawRegs::SetupRasterOp(_UBM_ROP) 00000000000b4010 __float128 0f SECT 01 0000 [.text] SiBltDrawRegs::SetupCbResolve(BltInfo const*) 00000000000b4034 __float128 0f SECT 01 0000 [.text] SiBltDrawRegs::SetupDccExpand(BltInfo const*) 00000000000b4458 __float128 0f SECT 01 0000 [.text] SiBltDrawRegs::SetupTileZToCb(BltInfo const*) 00000000000b4586 __float128 0f SECT 01 0000 [.text] SiBltDrawRegs::EnableHybridHiS(BltInfo*) 00000000000b21de __float128 0f SECT 01 0000 [.text] SiBltDrawRegs::InitContextRegs() 00000000000b40ce __float128 0f SECT 01 0000 [.text] SiBltDrawRegs::SetupAlphaBlend(BltInfo const*) 00000000000b453c __float128 0f SECT 01 0000 [.text] SiBltDrawRegs::SetupResumHTile(BltInfo const*) 00000000000b4610 __float128 0f SECT 01 0000 [.text] SiBltDrawRegs::UpdateViewSlice(BltInfo const*, unsigned int) 00000000000b422e __float128 0f SECT 01 0000 [.text] SiBltDrawRegs::DbgEnableStencil(BltInfo const*) 00000000000b4022 __float128 0f SECT 01 0000 [.text] SiBltDrawRegs::SetupColorExpand(BltInfo const*) 00000000000b2262 __float128 0f SECT 01 0000 [.text] SiBltDrawRegs::WriteContextToHw(BltInfo const*) 00000000000b38cc __float128 0f SECT 01 0000 [.text] SiBltDrawRegs::SetupHTileEnables(unsigned int, unsigned int, unsigned int, unsigned int) 00000000000b3f4a __float128 0f SECT 01 0000 [.text] SiBltDrawRegs::SetupStencilClear(BltInfo const*) 00000000000b23da __float128 0f SECT 01 0000 [.text] SiBltDrawRegs::SetupAndWriteColor(BltInfo const*) 00000000000b2ec0 __float128 0f SECT 01 0000 [.text] SiBltDrawRegs::SetupAndWriteDepth(BltInfo const*) 00000000000b4046 __float128 0f SECT 01 0000 [.text] SiBltDrawRegs::SetupExpandTexture(BltInfo const*) 00000000000b4072 __float128 0f SECT 01 0000 [.text] SiBltDrawRegs::SetupColorWriteMask(BltInfo const*) 00000000000b23a4 __float128 0f SECT 01 0000 [.text] SiBltDrawRegs::SetupDestSurfScissor(BltInfo const*, _UBM_SURFINFO const*) 00000000000b4060 __float128 0f SECT 01 0000 [.text] SiBltDrawRegs::SetupFmaskDecompress() 00000000000b41be __float128 0f SECT 01 0000 [.text] SiBltDrawRegs::EnableGammaCorrection(BltInfo const*) 00000000000b3924 __float128 0f SECT 01 0000 [.text] SiBltDrawRegs::SetupAndWriteClipRects(BltInfo const*, _UBM_RECTL const*, unsigned int) 00000000000b3cc0 __float128 0f SECT 01 0000 [.text] SiBltDrawRegs::SetupAndWriteAASampleLocs(BltInfo const*) 00000000000b43b2 __float128 0f SECT 01 0000 [.text] SiBltDrawRegs::SetupDepthStencilClearDisables(BltInfo const*) 00000000000b3e52 __float128 0f SECT 01 0000 [.text] SiBltDrawRegs::SetupAndWriteCentroidPriorities(BltInfo const*) 00000000000b21d0 __float128 0f SECT 01 0000 [.text] SiBltDrawRegs::Init(SiBltDevice*, BltInfo const*) 00000000000b3bb2 __float128 0f SECT 01 0000 [.text] SiBltDrawRegs::EnableZ(unsigned int, CompareFrag, unsigned int) 00000000000b3be2 __float128 0f SECT 01 0000 [.text] SiBltDrawRegs::EnableAA(BltInfo const*) 00000000000b2258 __float128 0f SECT 01 0000 [.text] SiBltDrawRegs::WriteToHw(BltInfo const*) 00000000000b21ca __float128 0f SECT 01 0000 [.text] SiBltDrawRegs::SiBltDrawRegs() 00000000000b21c4 __float128 0f SECT 01 0000 [.text] SiBltDrawRegs::SiBltDrawRegs() 00000000000a7604 __float128 0f SECT 01 0000 [.text] SurfAttribute::CreateObject() 00000000000a7722 __float128 0f SECT 01 0000 [.text] SurfAttribute::Init(_UBM_CREATEINFO const*) 00000000000a75ac __float128 0f SECT 01 0000 [.text] SurfAttribute::Create(_UBM_CREATEINFO const*) 00000000000a75f2 __float128 0f SECT 01 0000 [.text] SurfAttribute::Destroy() 00000000000a763a __float128 0f SECT 01 0000 [.text] SurfAttribute::SurfAttribute() 00000000000a7696 __float128 0f SECT 01 0000 [.text] SurfAttribute::SurfAttribute() 00000000000a76f4 __float128 0f SECT 01 0000 [.text] SurfAttribute::~SurfAttribute() 00000000000a76d8 __float128 0f SECT 01 0000 [.text] SurfAttribute::~SurfAttribute() 00000000000a76bc __float128 0f SECT 01 0000 [.text] SurfAttribute::~SurfAttribute() 000000000052d798 __float128 0f SECT 0a 0000 [__DATA.__common] AMDCICLContext::gMetaClass 000000000039d5a8 __float128 0f SECT 08 0000 [.const_data] AMDCICLContext::superClass 0000000000043e8a __float128 0f SECT 01 0000 [.text] AMDCICLContext::contextStop() 000000000004574a __float128 0f SECT 01 0000 [.text] AMDCICLContext::setRsrcRegs(SI_HwVertexBufRsrcDescRec*, unsigned long long, unsigned int, unsigned int) 00000000000443a8 __float128 0f SECT 01 0000 [.text] AMDCICLContext::splitStream(IOAccelCommandStreamInfo&) 0000000000043c02 __float128 0f SECT 01 0000 [.text] AMDCICLContext::contextStart() 0000000000044b74 __float128 0f SECT 01 0000 [.text] AMDCICLContext::remapBuffers(unsigned int const*, _COMPUTE_INFO*, unsigned long long) 000000000004402a __float128 0f SECT 01 0000 [.text] AMDCICLContext::enableContext() 000000000004572e __float128 0f SECT 01 0000 [.text] AMDCICLContext::getPixelBytes(unsigned int, unsigned int) 000000000039d510 __float128 0f SECT 08 0000 [.const_data] AMDCICLContext::process_table 00000000000440fa __float128 0f SECT 01 0000 [.text] AMDCICLContext::disableContext() 0000000000045c60 __float128 0f SECT 01 0000 [.text] AMDCICLContext::hasProxyBuffer(IOAccelResource2*) 000000000003e47c __float128 0f SECT 01 0000 [.text] AMDCICLContext::process_Compute(IOAccelCommandStreamInfo&) 00000000000456f6 __float128 0f SECT 01 0000 [.text] AMDCICLContext::setConstBufRegs(SI_HwVertexBufRsrcDescRec*, unsigned long long, unsigned int) 000000000003e400 __float128 0f SECT 01 0000 [.text] AMDCICLContext::process_SetFence(IOAccelCommandStreamInfo&) 0000000000045cd2 __float128 0f SECT 01 0000 [.text] AMDCICLContext::setupImageRecord(unsigned int const*, IOAccelResource2*, ComputeImageRecord*, WriteImageRecord*, bool) 00000000000463a0 __float128 0f SECT 01 0000 [.text] AMDCICLContext::commonLoadBuffers(IOAccelResource2*, IOAccelResource2*, unsigned long long&, unsigned long long&) 00000000000429e4 __float128 0f SECT 01 0000 [.text] AMDCICLContext::process_CopyImage(IOAccelCommandStreamInfo&) 000000000003f9fc __float128 0f SECT 01 0000 [.text] AMDCICLContext::process_RWCBuffer(IOAccelCommandStreamInfo&) 0000000000040416 __float128 0f SECT 01 0000 [.text] AMDCICLContext::process_ReadImage(IOAccelCommandStreamInfo&) 00000000000457b4 __float128 0f SECT 01 0000 [.text] AMDCICLContext::syncWriteResource(WriteImageRecord*, unsigned char) 000000000004176c __float128 0f SECT 01 0000 [.text] AMDCICLContext::process_WriteImage(IOAccelCommandStreamInfo&) 0000000000045792 __float128 0f SECT 01 0000 [.text] AMDCICLContext::setScratchRsrcRegs(SI_HwVertexBufRsrcDescRec*, unsigned long long, unsigned int) 0000000000043f24 __float128 0f SECT 01 0000 [.text] AMDCICLContext::getDataBufferLimits() 0000000000043f82 __float128 0f SECT 01 0000 [.text] AMDCICLContext::processSidebandToken(IOAccelCommandStreamInfo&) 0000000000044584 __float128 0f SECT 01 0000 [.text] AMDCICLContext::writeAtomicComputeOp(unsigned int*, _COMPUTE_INFO const*, _clKernelInfo const*, SubmitRingBufferEntry*) 0000000000043f00 __float128 0f SECT 01 0000 [.text] AMDCICLContext::populateContextConfig(IOAccelContextConfig*) 000000000004388a __float128 0f SECT 01 0000 [.text] AMDCICLContext::process_QueuePriority(IOAccelCommandStreamInfo&) 0000000000044cd6 __float128 0f SECT 01 0000 [.text] AMDCICLContext::getGlobalBasePatchArgs(unsigned int const*, SubmitRingBufferEntry*, _clKernelInfo const*, _COMPUTE_INFO*, unsigned long long*, unsigned long long*) 0000000000043a6a __float128 0f SECT 01 0000 [.text] AMDCICLContext::process_UnhandledToken(IOAccelCommandStreamInfo&) 0000000000046362 __float128 0f SECT 01 0000 [.text] AMDCICLContext::commonProcessBufferInit(IOAccelCommandStreamInfo&) 000000000004451a __float128 0f SECT 01 0000 [.text] AMDCICLContext::getHardwareConfiguration(unsigned int*, unsigned int*, unsigned int*, unsigned int*) 0000000000043706 __float128 0f SECT 01 0000 [.text] AMDCICLContext::process_LinearWriteFlush(IOAccelCommandStreamInfo&) 00000000000441dc __float128 0f SECT 01 0000 [.text] AMDCICLContext::freeSubmitRingBufferEntry(SubmitRingBufferEntry*) 0000000000043f44 __float128 0f SECT 01 0000 [.text] AMDCICLContext::getTargetAndMethodForIndex(IOService**, unsigned int) 00000000000442c4 __float128 0f SECT 01 0000 [.text] AMDCICLContext::updateSubmitRingBufferEntries() 0000000000044216 __float128 0f SECT 01 0000 [.text] AMDCICLContext::removeConsumedSubmitRingBufferEntries() 0000000000043dc2 __float128 0f SECT 01 0000 [.text] AMDCICLContext::finish() 0000000000043a70 __float128 0f SECT 01 0000 [.text] AMDCICLContext::MetaClass::MetaClass() 0000000000043b30 __float128 0f SECT 01 0000 [.text] AMDCICLContext::MetaClass::MetaClass() 000000000039d5a0 __float128 0f SECT 08 0000 [.const_data] AMDCICLContext::metaClass 0000000000043acc __float128 0f SECT 01 0000 [.text] AMDCICLContext::AMDCICLContext(OSMetaClass const*) 0000000000043ba2 __float128 0f SECT 01 0000 [.text] AMDCICLContext::AMDCICLContext() 0000000000043aac __float128 0f SECT 01 0000 [.text] AMDCICLContext::AMDCICLContext(OSMetaClass const*) 0000000000043bd2 __float128 0f SECT 01 0000 [.text] AMDCICLContext::AMDCICLContext() 0000000000043b00 __float128 0f SECT 01 0000 [.text] AMDCICLContext::~AMDCICLContext() 0000000000043af6 __float128 0f SECT 01 0000 [.text] AMDCICLContext::~AMDCICLContext() 0000000000043aec __float128 0f SECT 01 0000 [.text] AMDCICLContext::~AMDCICLContext() 000000000052e580 __float128 0f SECT 0a 0000 [__DATA.__common] AMDCIPM4Engine::gMetaClass 00000000003b39a8 __float128 0f SECT 08 0000 [.const_data] AMDCIPM4Engine::superClass 00000000000794b4 __float128 0f SECT 01 0000 [.text] AMDCIPM4Engine::cpSoftReset() 000000000007930c __float128 0f SECT 01 0000 [.text] AMDCIPM4Engine::gfxEngineReset() 00000000000786fa __float128 0f SECT 01 0000 [.text] AMDCIPM4Engine::MicroEngineStop(_eAMD_HW_RING_TYPE) 0000000000078ff2 __float128 0f SECT 01 0000 [.text] AMDCIPM4Engine::allocateHWRings() 000000000007921c __float128 0f SECT 01 0000 [.text] AMDCIPM4Engine::stopBeforeReset() 0000000000078b06 __float128 0f SECT 01 0000 [.text] AMDCIPM4Engine::MicroEngineStart(_eAMD_HW_RING_TYPE) 00000000000790a4 __float128 0f SECT 01 0000 [.text] AMDCIPM4Engine::allocateHWChannels() 000000000007819a __float128 0f SECT 01 0000 [.text] AMDCIPM4Engine::setVirtualSpaceReady(bool) 00000000000788da __float128 0f SECT 01 0000 [.text] AMDCIPM4Engine::MicroEngineInitialize(_eAMD_HW_RING_TYPE) 0000000000078d5c __float128 0f SECT 01 0000 [.text] AMDCIPM4Engine::initializeMicroEngine() 0000000000078eda __float128 0f SECT 01 0000 [.text] AMDCIPM4Engine::allocateAndInitHWRings() 0000000000079204 __float128 0f SECT 01 0000 [.text] AMDCIPM4Engine::getTimestampIRQSourcex(_eAMD_HW_RING_TYPE) 0000000000078ebe __float128 0f SECT 01 0000 [.text] AMDCIPM4Engine::resetGRBMOnCommandStart() 0000000000079546 __float128 0f SECT 01 0000 [.text] AMDCIPM4Engine::toCailDetectHungEngines() 00000000000787ea __float128 0f SECT 01 0000 [.text] AMDCIPM4Engine::MicroEngineLoadMicrocode(_eAMD_HW_RING_TYPE) 000000000007822e __float128 0f SECT 01 0000 [.text] AMDCIPM4Engine::setMemoryAllocationsEnabled(bool) 00000000000791fe __float128 0f SECT 01 0000 [.text] AMDCIPM4Engine::initializeTimestampRegisters(unsigned int) 0000000000078bf6 __float128 0f SECT 01 0000 [.text] AMDCIPM4Engine::MicroEngineQueryMicrocodeVersion(_eAMD_HW_RING_TYPE) 0000000000078188 __float128 0f SECT 01 0000 [.text] AMDCIPM4Engine::free() 00000000000780f2 __float128 0f SECT 01 0000 [.text] AMDCIPM4Engine::init(AMDRadeonX4000_IAMDHWInterface*, _eAMD_HW_ENGINE_TYPE) 00000000000784f8 __float128 0f SECT 01 0000 [.text] AMDCIPM4Engine::stop() 0000000000079244 __float128 0f SECT 01 0000 [.text] AMDCIPM4Engine::reset(_eAMD_HW_RING_TYPE) 00000000000784a4 __float128 0f SECT 01 0000 [.text] AMDCIPM4Engine::start() 000000000007859a __float128 0f SECT 01 0000 [.text] AMDCIPM4Engine::haltME() 0000000000078e7c __float128 0f SECT 01 0000 [.text] AMDCIPM4Engine::isIdle() 0000000000078428 __float128 0f SECT 01 0000 [.text] AMDCIPM4Engine::powerUp() 0000000000078682 __float128 0f SECT 01 0000 [.text] AMDCIPM4Engine::startME() 0000000000077f60 __float128 0f SECT 01 0000 [.text] AMDCIPM4Engine::MetaClass::MetaClass() 0000000000078020 __float128 0f SECT 01 0000 [.text] AMDCIPM4Engine::MetaClass::MetaClass() 00000000003b39a0 __float128 0f SECT 08 0000 [.const_data] AMDCIPM4Engine::metaClass 000000000007917a __float128 0f SECT 01 0000 [.text] AMDCIPM4Engine::softReset(unsigned int, unsigned int) 0000000000077fbc __float128 0f SECT 01 0000 [.text] AMDCIPM4Engine::AMDCIPM4Engine(OSMetaClass const*) 0000000000078092 __float128 0f SECT 01 0000 [.text] AMDCIPM4Engine::AMDCIPM4Engine() 0000000000077f9c __float128 0f SECT 01 0000 [.text] AMDCIPM4Engine::AMDCIPM4Engine(OSMetaClass const*) 00000000000780c2 __float128 0f SECT 01 0000 [.text] AMDCIPM4Engine::AMDCIPM4Engine() 0000000000077ff0 __float128 0f SECT 01 0000 [.text] AMDCIPM4Engine::~AMDCIPM4Engine() 0000000000077fe6 __float128 0f SECT 01 0000 [.text] AMDCIPM4Engine::~AMDCIPM4Engine() 0000000000077fdc __float128 0f SECT 01 0000 [.text] AMDCIPM4Engine::~AMDCIPM4Engine() 000000000052d6d0 __float128 0f SECT 0a 0000 [__DATA.__common] AMDSICLContext::gMetaClass 000000000039a178 __float128 0f SECT 08 0000 [.const_data] AMDSICLContext::superClass 000000000003a778 __float128 0f SECT 01 0000 [.text] AMDSICLContext::contextStop() 000000000003befa __float128 0f SECT 01 0000 [.text] AMDSICLContext::setRsrcRegs(SI_HwVertexBufRsrcDescRec*, unsigned long long, unsigned int, unsigned int) 000000000003ac96 __float128 0f SECT 01 0000 [.text] AMDSICLContext::splitStream(IOAccelCommandStreamInfo&) 000000000003a54a __float128 0f SECT 01 0000 [.text] AMDSICLContext::contextStart() 000000000003b35c __float128 0f SECT 01 0000 [.text] AMDSICLContext::remapBuffers(unsigned int const*, _COMPUTE_INFO*, unsigned long long) 000000000003a918 __float128 0f SECT 01 0000 [.text] AMDSICLContext::enableContext() 000000000003bede __float128 0f SECT 01 0000 [.text] AMDSICLContext::getPixelBytes(unsigned int, unsigned int) 000000000039a0e0 __float128 0f SECT 08 0000 [.const_data] AMDSICLContext::process_table 000000000003a9e8 __float128 0f SECT 01 0000 [.text] AMDSICLContext::disableContext() 000000000003c406 __float128 0f SECT 01 0000 [.text] AMDSICLContext::hasProxyBuffer(IOAccelResource2*) 0000000000034efc __float128 0f SECT 01 0000 [.text] AMDSICLContext::process_Compute(IOAccelCommandStreamInfo&) 000000000003bebc __float128 0f SECT 01 0000 [.text] AMDSICLContext::setConstBufRegs(SI_HwVertexBufRsrcDescRec*, unsigned long long, unsigned int) 0000000000034e80 __float128 0f SECT 01 0000 [.text] AMDSICLContext::process_SetFence(IOAccelCommandStreamInfo&) 000000000003c478 __float128 0f SECT 01 0000 [.text] AMDSICLContext::setupImageRecord(unsigned int const*, IOAccelResource2*, ComputeImageRecord*, WriteImageRecord*, bool) 000000000003cb46 __float128 0f SECT 01 0000 [.text] AMDSICLContext::commonLoadBuffers(IOAccelResource2*, IOAccelResource2*, unsigned long long&, unsigned long long&) 000000000003932c __float128 0f SECT 01 0000 [.text] AMDSICLContext::process_CopyImage(IOAccelCommandStreamInfo&) 0000000000036344 __float128 0f SECT 01 0000 [.text] AMDSICLContext::process_RWCBuffer(IOAccelCommandStreamInfo&) 0000000000036d5e __float128 0f SECT 01 0000 [.text] AMDSICLContext::process_ReadImage(IOAccelCommandStreamInfo&) 000000000003bf5a __float128 0f SECT 01 0000 [.text] AMDSICLContext::syncWriteResource(WriteImageRecord*, unsigned char) 00000000000380b4 __float128 0f SECT 01 0000 [.text] AMDSICLContext::process_WriteImage(IOAccelCommandStreamInfo&) 000000000003bf38 __float128 0f SECT 01 0000 [.text] AMDSICLContext::setScratchRsrcRegs(SI_HwVertexBufRsrcDescRec*, unsigned long long, unsigned int) 000000000003a812 __float128 0f SECT 01 0000 [.text] AMDSICLContext::getDataBufferLimits() 000000000003a870 __float128 0f SECT 01 0000 [.text] AMDSICLContext::processSidebandToken(IOAccelCommandStreamInfo&) 000000000003addc __float128 0f SECT 01 0000 [.text] AMDSICLContext::writeAtomicComputeOp(unsigned int*, _COMPUTE_INFO const*, _clKernelInfo const*, SubmitRingBufferEntry*) 000000000003a7ee __float128 0f SECT 01 0000 [.text] AMDSICLContext::populateContextConfig(IOAccelContextConfig*) 000000000003a1d2 __float128 0f SECT 01 0000 [.text] AMDSICLContext::process_QueuePriority(IOAccelCommandStreamInfo&) 000000000003b4be __float128 0f SECT 01 0000 [.text] AMDSICLContext::getGlobalBasePatchArgs(unsigned int const*, SubmitRingBufferEntry*, _clKernelInfo const*, _COMPUTE_INFO*, unsigned long long*, unsigned long long*) 000000000003a3b2 __float128 0f SECT 01 0000 [.text] AMDSICLContext::process_UnhandledToken(IOAccelCommandStreamInfo&) 000000000003cb08 __float128 0f SECT 01 0000 [.text] AMDSICLContext::commonProcessBufferInit(IOAccelCommandStreamInfo&) 000000000003ad72 __float128 0f SECT 01 0000 [.text] AMDSICLContext::getHardwareConfiguration(unsigned int*, unsigned int*, unsigned int*, unsigned int*) 000000000003a04e __float128 0f SECT 01 0000 [.text] AMDSICLContext::process_LinearWriteFlush(IOAccelCommandStreamInfo&) 000000000003aaca __float128 0f SECT 01 0000 [.text] AMDSICLContext::freeSubmitRingBufferEntry(SubmitRingBufferEntry*) 000000000003a832 __float128 0f SECT 01 0000 [.text] AMDSICLContext::getTargetAndMethodForIndex(IOService**, unsigned int) 000000000003abb2 __float128 0f SECT 01 0000 [.text] AMDSICLContext::updateSubmitRingBufferEntries() 000000000003ab04 __float128 0f SECT 01 0000 [.text] AMDSICLContext::removeConsumedSubmitRingBufferEntries() 000000000003a6b0 __float128 0f SECT 01 0000 [.text] AMDSICLContext::finish() 000000000003a3b8 __float128 0f SECT 01 0000 [.text] AMDSICLContext::MetaClass::MetaClass() 000000000003a478 __float128 0f SECT 01 0000 [.text] AMDSICLContext::MetaClass::MetaClass() 000000000039a170 __float128 0f SECT 08 0000 [.const_data] AMDSICLContext::metaClass 000000000003a414 __float128 0f SECT 01 0000 [.text] AMDSICLContext::AMDSICLContext(OSMetaClass const*) 000000000003a4ea __float128 0f SECT 01 0000 [.text] AMDSICLContext::AMDSICLContext() 000000000003a3f4 __float128 0f SECT 01 0000 [.text] AMDSICLContext::AMDSICLContext(OSMetaClass const*) 000000000003a51a __float128 0f SECT 01 0000 [.text] AMDSICLContext::AMDSICLContext() 000000000003a448 __float128 0f SECT 01 0000 [.text] AMDSICLContext::~AMDSICLContext() 000000000003a43e __float128 0f SECT 01 0000 [.text] AMDSICLContext::~AMDSICLContext() 000000000003a434 __float128 0f SECT 01 0000 [.text] AMDSICLContext::~AMDSICLContext() 000000000052e288 __float128 0f SECT 0a 0000 [__DATA.__common] AMDSIDMAEngine::gMetaClass 00000000003aeae8 __float128 0f SECT 08 0000 [.const_data] AMDSIDMAEngine::superClass 000000000006d7fe __float128 0f SECT 01 0000 [.text] AMDSIDMAEngine::allocateHWRings() 000000000006d83a __float128 0f SECT 01 0000 [.text] AMDSIDMAEngine::allocateHWChannels() 000000000006d964 __float128 0f SECT 01 0000 [.text] AMDSIDMAEngine::dumpEngineHangState(bool) 000000000006d782 __float128 0f SECT 01 0000 [.text] AMDSIDMAEngine::free() 000000000006d702 __float128 0f SECT 01 0000 [.text] AMDSIDMAEngine::init(AMDRadeonX4000_IAMDHWInterface*, _eAMD_HW_ENGINE_TYPE) 000000000006d8fc __float128 0f SECT 01 0000 [.text] AMDSIDMAEngine::stop() 000000000006d886 __float128 0f SECT 01 0000 [.text] AMDSIDMAEngine::start() 000000000006d794 __float128 0f SECT 01 0000 [.text] AMDSIDMAEngine::isIdle() 000000000006d7c4 __float128 0f SECT 01 0000 [.text] AMDSIDMAEngine::powerUp() 000000000006d570 __float128 0f SECT 01 0000 [.text] AMDSIDMAEngine::MetaClass::MetaClass() 000000000006d630 __float128 0f SECT 01 0000 [.text] AMDSIDMAEngine::MetaClass::MetaClass() 00000000003aeae0 __float128 0f SECT 08 0000 [.const_data] AMDSIDMAEngine::metaClass 000000000006d5cc __float128 0f SECT 01 0000 [.text] AMDSIDMAEngine::AMDSIDMAEngine(OSMetaClass const*) 000000000006d6a2 __float128 0f SECT 01 0000 [.text] AMDSIDMAEngine::AMDSIDMAEngine() 000000000006d5ac __float128 0f SECT 01 0000 [.text] AMDSIDMAEngine::AMDSIDMAEngine(OSMetaClass const*) 000000000006d6d2 __float128 0f SECT 01 0000 [.text] AMDSIDMAEngine::AMDSIDMAEngine() 000000000006d600 __float128 0f SECT 01 0000 [.text] AMDSIDMAEngine::~AMDSIDMAEngine() 000000000006d5f6 __float128 0f SECT 01 0000 [.text] AMDSIDMAEngine::~AMDSIDMAEngine() 000000000006d5ec __float128 0f SECT 01 0000 [.text] AMDSIDMAEngine::~AMDSIDMAEngine() 000000000052d6a8 __float128 0f SECT 0a 0000 [__DATA.__common] AMDSIGLContext::gMetaClass 0000000000032444 __float128 0f SECT 01 0000 [.text] AMDSIGLContext::invalidate() 0000000000399468 __float128 0f SECT 08 0000 [.const_data] AMDSIGLContext::superClass 00000000000338cc __float128 0f SECT 01 0000 [.text] AMDSIGLContext::SurfaceCopy(unsigned int*, unsigned long long) 000000000003236c __float128 0f SECT 01 0000 [.text] AMDSIGLContext::contextStop() 0000000000032d64 __float128 0f SECT 01 0000 [.text] AMDSIGLContext::bindResource(IOAccelCommandStreamInfo&, IOAccelResource2*, bool, IOAccelChannel2*, unsigned int) 000000000003210c __float128 0f SECT 01 0000 [.text] AMDSIGLContext::contextStart() 00000000000339c0 __float128 0f SECT 01 0000 [.text] AMDSIGLContext::build_scissor() 000000000003327e __float128 0f SECT 01 0000 [.text] AMDSIGLContext::readPixelsFBO(sATIGLContextReadPixelsFBOData*, unsigned long long) 0000000000032814 __float128 0f SECT 01 0000 [.text] AMDSIGLContext::restore_state(IOAccelCommandStreamInfo&) 0000000000399230 __float128 0f SECT 08 0000 [.const_data] AMDSIGLContext::prefetch_table 000000000003111a __float128 0f SECT 01 0000 [.text] AMDSIGLContext::process_Expand(IOAccelCommandStreamInfo&) 0000000000033230 __float128 0f SECT 01 0000 [.text] AMDSIGLContext::unbindResource(IOAccelCommandStreamInfo&, IOAccelResource2*, IOAccelChannel2*) 0000000000033b02 __float128 0f SECT 01 0000 [.text] AMDSIGLContext::prefetch_object(PrefetchInfo&, AMDRadeonX4000_AMDAccelResource*) 0000000000031c92 __float128 0f SECT 01 0000 [.text] AMDSIGLContext::process_Kprintf(IOAccelCommandStreamInfo&) 00000000000328ce __float128 0f SECT 01 0000 [.text] AMDSIGLContext::endCommandStream(IOAccelCommandStreamInfo&) 0000000000033bc0 __float128 0f SECT 01 0000 [.text] AMDSIGLContext::prefetch_BindFBO(IOAccelCommandStreamInfo&, unsigned int*) 0000000000030e04 __float128 0f SECT 01 0000 [.text] AMDSIGLContext::process_Compress(IOAccelCommandStreamInfo&) 0000000000031ce2 __float128 0f SECT 01 0000 [.text] AMDSIGLContext::process_EndBlits(IOAccelCommandStreamInfo&) 000000000002f80c __float128 0f SECT 01 0000 [.text] AMDSIGLContext::process_SetFence(IOAccelCommandStreamInfo&) 000000000002ce44 __float128 0f SECT 01 0000 [.text] AMDSIGLContext::process_AAResolve(IOAccelCommandStreamInfo&) 00000000000327f8 __float128 0f SECT 01 0000 [.text] AMDSIGLContext::beginCommandStream(IOAccelCommandStreamInfo&) 000000000002b404 __float128 0f SECT 01 0000 [.text] AMDSIGLContext::handle_BindObjects(IOAccelCommandStreamInfo&) 000000000002fa8a __float128 0f SECT 01 0000 [.text] AMDSIGLContext::process_ClearColor(IOAccelCommandStreamInfo&) 000000000002bd7c __float128 0f SECT 01 0000 [.text] AMDSIGLContext::process_DrawBuffer(IOAccelCommandStreamInfo&) 0000000000031cc2 __float128 0f SECT 01 0000 [.text] AMDSIGLContext::process_StartBlits(IOAccelCommandStreamInfo&) 0000000000031cf4 __float128 0f SECT 01 0000 [.text] AMDSIGLContext::discard_SimpleToken(IOAccelCommandStreamInfo&) 0000000000032b92 __float128 0f SECT 01 0000 [.text] AMDSIGLContext::getDataBufferLimits() 0000000000032cb2 __float128 0f SECT 01 0000 [.text] AMDSIGLContext::addDrawableToChannel(IOAccelDrawable2*) 00000000000326cc __float128 0f SECT 01 0000 [.text] AMDSIGLContext::discardSidebandToken(IOAccelCommandStreamInfo&) 0000000000031df4 __float128 0f SECT 01 0000 [.text] AMDSIGLContext::discard_IgnoredToken(IOAccelCommandStreamInfo&) 000000000002afa4 __float128 0f SECT 01 0000 [.text] AMDSIGLContext::free_scratch_texture(AMDRadeonX4000_AMDAccelResource*) 000000000002b6ba __float128 0f SECT 01 0000 [.text] AMDSIGLContext::handle_UnbindObjects(IOAccelCommandStreamInfo&) 0000000000031ef2 __float128 0f SECT 01 0000 [.text] AMDSIGLContext::prefetch_BindObjects(IOAccelCommandStreamInfo&, unsigned int*) 0000000000031ec0 __float128 0f SECT 01 0000 [.text] AMDSIGLContext::prefetch_SimpleToken(IOAccelCommandStreamInfo&, unsigned int*) 000000000003258a __float128 0f SECT 01 0000 [.text] AMDSIGLContext::processSidebandToken(IOAccelCommandStreamInfo&) 000000000002f8c8 __float128 0f SECT 01 0000 [.text] AMDSIGLContext::process_BufferMemcpy(IOAccelCommandStreamInfo&) 000000000002af5c __float128 0f SECT 01 0000 [.text] AMDSIGLContext::alloc_scratch_texture() 0000000000032566 __float128 0f SECT 01 0000 [.text] AMDSIGLContext::populateContextConfig(IOAccelContextConfig*) 0000000000031eea __float128 0f SECT 01 0000 [.text] AMDSIGLContext::prefetch_IgnoredToken(IOAccelCommandStreamInfo&, unsigned int*) 0000000000032cee __float128 0f SECT 01 0000 [.text] AMDSIGLContext::processSidebandBuffer(IOAccelCommandDescriptor*, bool) 0000000000032c40 __float128 0f SECT 01 0000 [.text] AMDSIGLContext::addDataBufferToChannel(IOAccelResource2*, unsigned int) 0000000000031dfa __float128 0f SECT 01 0000 [.text] AMDSIGLContext::discard_StretchTex2Tex(IOAccelCommandStreamInfo&) 0000000000031de4 __float128 0f SECT 01 0000 [.text] AMDSIGLContext::discard_UnhandledToken(IOAccelCommandStreamInfo&) 000000000002c988 __float128 0f SECT 01 0000 [.text] AMDSIGLContext::process_CopyColorScale(IOAccelCommandStreamInfo&) 000000000002bed4 __float128 0f SECT 01 0000 [.text] AMDSIGLContext::process_StretchTex2Tex(IOAccelCommandStreamInfo&) 000000000002b7e4 __float128 0f SECT 01 0000 [.text] AMDSIGLContext::process_UnhandledToken(IOAccelCommandStreamInfo&) 000000000002ae80 __float128 0f SECT 01 0000 [.text] AMDSIGLContext::createStateShadowBuffer(unsigned int) 000000000002b7c8 __float128 0f SECT 01 0000 [.text] AMDSIGLContext::handle_UnusedDataBuffer(IOAccelCommandStreamInfo&) 0000000000031f46 __float128 0f SECT 01 0000 [.text] AMDSIGLContext::prefetch_StretchTex2Tex(IOAccelCommandStreamInfo&, unsigned int*) 0000000000031f34 __float128 0f SECT 01 0000 [.text] AMDSIGLContext::prefetch_UnhandledToken(IOAccelCommandStreamInfo&, unsigned int*) 0000000000032e8a __float128 0f SECT 01 0000 [.text] AMDSIGLContext::prefetch_command_buffer(IOAccelCommandStreamInfo const&) 000000000002b1b8 __float128 0f SECT 01 0000 [.text] AMDSIGLContext::process_StateShadowInfo(IOAccelCommandStreamInfo&) 000000000002d9ea __float128 0f SECT 01 0000 [.text] AMDSIGLContext::process_StretchSurf2Tex(IOAccelCommandStreamInfo&) 0000000000031d5c __float128 0f SECT 01 0000 [.text] AMDSIGLContext::discard_InvalidateObject(IOAccelCommandStreamInfo&) 000000000003253a __float128 0f SECT 01 0000 [.text] AMDSIGLContext::get_temp_allocation_info(IOAccelDrawable2*, unsigned int*, unsigned int*) 000000000002b37a __float128 0f SECT 01 0000 [.text] AMDSIGLContext::process_InvalidateObject(IOAccelCommandStreamInfo&) 000000000002afba __float128 0f SECT 01 0000 [.text] AMDSIGLContext::reset_scratch_maskmemory() 000000000003244a __float128 0f SECT 01 0000 [.text] AMDSIGLContext::setCompatibleSurfaceMode(unsigned long long*, unsigned long long, int) 0000000000399010 __float128 0f SECT 08 0000 [.const_data] AMDSIGLContext::ati_token_discard_methods 0000000000398df0 __float128 0f SECT 08 0000 [.const_data] AMDSIGLContext::ati_token_process_methods 000000000002f080 __float128 0f SECT 01 0000 [.text] AMDSIGLContext::process_ClearDepthStencil(IOAccelCommandStreamInfo&) 000000000002b998 __float128 0f SECT 01 0000 [.text] AMDSIGLContext::process_PatchStreamTexBuf(IOAccelCommandStreamInfo&) 0000000000032cd0 __float128 0f SECT 01 0000 [.text] AMDSIGLContext::removeDrawableFromChannel(IOAccelDrawable2*) 0000000000033242 __float128 0f SECT 01 0000 [.text] AMDSIGLContext::getTargetAndMethodForIndex(IOService**, unsigned int) 000000000002b7f4 __float128 0f SECT 01 0000 [.text] AMDSIGLContext::process_PatchStreamDataBuf(IOAccelCommandStreamInfo&) 000000000002b1b0 __float128 0f SECT 01 0000 [.text] AMDSIGLContext::setup_temp_resolve_surface(AMDRadeonX4000_AMDAccelResource*) 0000000000032c60 __float128 0f SECT 01 0000 [.text] AMDSIGLContext::removeDataBufferFromChannel(IOAccelResource2*, unsigned int) 00000000000338e8 __float128 0f SECT 01 0000 [.text] AMDSIGLContext::setup_scratch_maskmemory_info(AMDRadeonX4000_AMDAccelResource*) 000000000002b01a __float128 0f SECT 01 0000 [.text] AMDSIGLContext::update_scratch_maskmemory_info(AMDRadeonX4000_AMDAccelResource*) 000000000003455e __float128 0f SECT 01 0000 [.text] AMDSIGLContext::write_kernel_render_target_regs(unsigned int*) 0000000000032c7e __float128 0f SECT 01 0000 [.text] AMDSIGLContext::removeCurrentResourceFromChannel(IOAccelResource2*, unsigned int) 000000000002fe82 __float128 0f SECT 01 0000 [.text] AMDSIGLContext::process_FramebufferBlitDepthStencil(IOAccelCommandStreamInfo&) 0000000000033c50 __float128 0f SECT 01 0000 [.text] AMDSIGLContext::write_kernel_depth_render_target_regs(unsigned int*) 0000000000031f7a __float128 0f SECT 01 0000 [.text] AMDSIGLContext::MetaClass::MetaClass() 000000000003203a __float128 0f SECT 01 0000 [.text] AMDSIGLContext::MetaClass::MetaClass() 0000000000399460 __float128 0f SECT 08 0000 [.const_data] AMDSIGLContext::metaClass 0000000000031fd6 __float128 0f SECT 01 0000 [.text] AMDSIGLContext::AMDSIGLContext(OSMetaClass const*) 00000000000320ac __float128 0f SECT 01 0000 [.text] AMDSIGLContext::AMDSIGLContext() 0000000000031fb6 __float128 0f SECT 01 0000 [.text] AMDSIGLContext::AMDSIGLContext(OSMetaClass const*) 00000000000320dc __float128 0f SECT 01 0000 [.text] AMDSIGLContext::AMDSIGLContext() 000000000003200a __float128 0f SECT 01 0000 [.text] AMDSIGLContext::~AMDSIGLContext() 0000000000032000 __float128 0f SECT 01 0000 [.text] AMDSIGLContext::~AMDSIGLContext() 0000000000031ff6 __float128 0f SECT 01 0000 [.text] AMDSIGLContext::~AMDSIGLContext() 000000000052e198 __float128 0f SECT 0a 0000 [__DATA.__common] AMDSIPM4Engine::gMetaClass 00000000003ad658 __float128 0f SECT 08 0000 [.const_data] AMDSIPM4Engine::superClass 000000000006b568 __float128 0f SECT 01 0000 [.text] AMDSIPM4Engine::allocateHWRings() 000000000006b28a __float128 0f SECT 01 0000 [.text] AMDSIPM4Engine::loadPM4Microcode() 000000000006b5f4 __float128 0f SECT 01 0000 [.text] AMDSIPM4Engine::allocateHWChannels() 000000000006b518 __float128 0f SECT 01 0000 [.text] AMDSIPM4Engine::getRevVersionNumber(char const*) 000000000006b4a0 __float128 0f SECT 01 0000 [.text] AMDSIPM4Engine::initializeMicroEngine() 000000000006b54c __float128 0f SECT 01 0000 [.text] AMDSIPM4Engine::resetGRBMOnCommandStart() 000000000006b91e __float128 0f SECT 01 0000 [.text] AMDSIPM4Engine::systemWillChangeSpeedEvent() 000000000006b26c __float128 0f SECT 01 0000 [.text] AMDSIPM4Engine::initializeTimestampRegisters(unsigned int) 000000000006b816 __float128 0f SECT 01 0000 [.text] AMDSIPM4Engine::stop() 000000000006b782 __float128 0f SECT 01 0000 [.text] AMDSIPM4Engine::start() 000000000006b404 __float128 0f SECT 01 0000 [.text] AMDSIPM4Engine::haltME() 000000000006b1ca __float128 0f SECT 01 0000 [.text] AMDSIPM4Engine::isIdle() 000000000006b698 __float128 0f SECT 01 0000 [.text] AMDSIPM4Engine::powerUp() 000000000006b464 __float128 0f SECT 01 0000 [.text] AMDSIPM4Engine::startME() 000000000006b0d0 __float128 0f SECT 01 0000 [.text] AMDSIPM4Engine::MetaClass::MetaClass() 000000000006b190 __float128 0f SECT 01 0000 [.text] AMDSIPM4Engine::MetaClass::MetaClass() 00000000003ad650 __float128 0f SECT 08 0000 [.const_data] AMDSIPM4Engine::metaClass 000000000006b1e8 __float128 0f SECT 01 0000 [.text] AMDSIPM4Engine::softReset(unsigned int, unsigned int) 000000000006b12c __float128 0f SECT 01 0000 [.text] AMDSIPM4Engine::AMDSIPM4Engine(OSMetaClass const*) 000000000006b10c __float128 0f SECT 01 0000 [.text] AMDSIPM4Engine::AMDSIPM4Engine(OSMetaClass const*) 000000000006b160 __float128 0f SECT 01 0000 [.text] AMDSIPM4Engine::~AMDSIPM4Engine() 000000000006b156 __float128 0f SECT 01 0000 [.text] AMDSIPM4Engine::~AMDSIPM4Engine() 000000000006b14c __float128 0f SECT 01 0000 [.text] AMDSIPM4Engine::~AMDSIPM4Engine() 000000000052e440 __float128 0f SECT 0a 0000 [__DATA.__common] AMDSISPUEngine::gMetaClass 00000000003b1258 __float128 0f SECT 08 0000 [.const_data] AMDSISPUEngine::superClass 0000000000072aa6 __float128 0f SECT 01 0000 [.text] AMDSISPUEngine::suspendSPU() 00000000000724ba __float128 0f SECT 01 0000 [.text] AMDSISPUEngine::setUVDState(bool) 00000000000725e4 __float128 0f SECT 01 0000 [.text] AMDSISPUEngine::initHardware() 00000000000726de __float128 0f SECT 01 0000 [.text] AMDSISPUEngine::initializeSPU() 0000000000072b8c __float128 0f SECT 01 0000 [.text] AMDSISPUEngine::prepareSuspend() 0000000000072ca2 __float128 0f SECT 01 0000 [.text] AMDSISPUEngine::allocateHWRings() 0000000000072bbc __float128 0f SECT 01 0000 [.text] AMDSISPUEngine::enableSPUClocks() 0000000000072668 __float128 0f SECT 01 0000 [.text] AMDSISPUEngine::releaseHardware() 0000000000072c0e __float128 0f SECT 01 0000 [.text] AMDSISPUEngine::disableSPUClocks() 0000000000072594 __float128 0f SECT 01 0000 [.text] AMDSISPUEngine::waitForKernelIdle() 0000000000072cde __float128 0f SECT 01 0000 [.text] AMDSISPUEngine::allocateHWChannels() 0000000000072d1a __float128 0f SECT 01 0000 [.text] AMDSISPUEngine::readIndirectSPUReg(unsigned int) 0000000000072d9e __float128 0f SECT 01 0000 [.text] AMDSISPUEngine::dumpEngineHangState(bool) 0000000000072d5a __float128 0f SECT 01 0000 [.text] AMDSISPUEngine::writeIndirectSPUReg(unsigned int, unsigned int) 00000000000724a4 __float128 0f SECT 01 0000 [.text] AMDSISPUEngine::setPowerRegistrationState(bool) 0000000000072390 __float128 0f SECT 01 0000 [.text] AMDSISPUEngine::free() 0000000000072312 __float128 0f SECT 01 0000 [.text] AMDSISPUEngine::init(AMDRadeonX4000_IAMDHWInterface*, _eAMD_HW_ENGINE_TYPE) 000000000007246e __float128 0f SECT 01 0000 [.text] AMDSISPUEngine::stop() 0000000000072416 __float128 0f SECT 01 0000 [.text] AMDSISPUEngine::start() 00000000000723cc __float128 0f SECT 01 0000 [.text] AMDSISPUEngine::isIdle() 0000000000072180 __float128 0f SECT 01 0000 [.text] AMDSISPUEngine::MetaClass::MetaClass() 0000000000072240 __float128 0f SECT 01 0000 [.text] AMDSISPUEngine::MetaClass::MetaClass() 00000000003b1250 __float128 0f SECT 08 0000 [.const_data] AMDSISPUEngine::metaClass 00000000000721dc __float128 0f SECT 01 0000 [.text] AMDSISPUEngine::AMDSISPUEngine(OSMetaClass const*) 00000000000722b2 __float128 0f SECT 01 0000 [.text] AMDSISPUEngine::AMDSISPUEngine() 00000000000721bc __float128 0f SECT 01 0000 [.text] AMDSISPUEngine::AMDSISPUEngine(OSMetaClass const*) 00000000000722e2 __float128 0f SECT 01 0000 [.text] AMDSISPUEngine::AMDSISPUEngine() 0000000000072210 __float128 0f SECT 01 0000 [.text] AMDSISPUEngine::~AMDSISPUEngine() 0000000000072206 __float128 0f SECT 01 0000 [.text] AMDSISPUEngine::~AMDSISPUEngine() 00000000000721fc __float128 0f SECT 01 0000 [.text] AMDSISPUEngine::~AMDSISPUEngine() 000000000052e080 __float128 0f SECT 0a 0000 [__DATA.__common] AMDSIVMContext::gMetaClass 00000000003ab0d8 __float128 0f SECT 08 0000 [.const_data] AMDSIVMContext::superClass 0000000000065292 __float128 0f SECT 01 0000 [.text] AMDSIVMContext::mapVA(unsigned long long, unsigned long long, IOMemoryDescriptor*, unsigned long long, unsigned long long, bool) 0000000000066156 __float128 0f SECT 01 0000 [.text] AMDSIVMContext::unmapVA(unsigned long long, unsigned long long) 0000000000065100 __float128 0f SECT 01 0000 [.text] AMDSIVMContext::MetaClass::MetaClass() 00000000000651c0 __float128 0f SECT 01 0000 [.text] AMDSIVMContext::MetaClass::MetaClass() 00000000003ab0d0 __float128 0f SECT 08 0000 [.const_data] AMDSIVMContext::metaClass 000000000006515c __float128 0f SECT 01 0000 [.text] AMDSIVMContext::AMDSIVMContext(OSMetaClass const*) 0000000000065232 __float128 0f SECT 01 0000 [.text] AMDSIVMContext::AMDSIVMContext() 000000000006513c __float128 0f SECT 01 0000 [.text] AMDSIVMContext::AMDSIVMContext(OSMetaClass const*) 0000000000065262 __float128 0f SECT 01 0000 [.text] AMDSIVMContext::AMDSIVMContext() 0000000000065190 __float128 0f SECT 01 0000 [.text] AMDSIVMContext::~AMDSIVMContext() 0000000000065186 __float128 0f SECT 01 0000 [.text] AMDSIVMContext::~AMDSIVMContext() 000000000006517c __float128 0f SECT 01 0000 [.text] AMDSIVMContext::~AMDSIVMContext() 000000000052eb70 __float128 0f SECT 0a 0000 [__DATA.__common] AMDVIPM4Engine::gMetaClass 00000000003bc398 __float128 0f SECT 08 0000 [.const_data] AMDVIPM4Engine::superClass 000000000009140c __float128 0f SECT 01 0000 [.text] AMDVIPM4Engine::cpSoftReset() 0000000000091138 __float128 0f SECT 01 0000 [.text] AMDVIPM4Engine::gfxEngineReset() 000000000008f650 __float128 0f SECT 01 0000 [.text] AMDVIPM4Engine::InitMapQueueMQD(_eAMD_HW_RING_TYPE) 000000000008fdea __float128 0f SECT 01 0000 [.text] AMDVIPM4Engine::MicroEngineStop(_eAMD_HW_RING_TYPE) 0000000000090d1a __float128 0f SECT 01 0000 [.text] AMDVIPM4Engine::allocateHWRings() 000000000009103a __float128 0f SECT 01 0000 [.text] AMDVIPM4Engine::stopBeforeReset() 0000000000090494 __float128 0f SECT 01 0000 [.text] AMDVIPM4Engine::MicroEngineStart(_eAMD_HW_RING_TYPE) 0000000000090dcc __float128 0f SECT 01 0000 [.text] AMDVIPM4Engine::allocateHWChannels() 0000000000091392 __float128 0f SECT 01 0000 [.text] AMDVIPM4Engine::computeEngineReset(_eAMD_HW_RING_TYPE) 000000000008f582 __float128 0f SECT 01 0000 [.text] AMDVIPM4Engine::setVirtualSpaceReady(bool) 0000000000090268 __float128 0f SECT 01 0000 [.text] AMDVIPM4Engine::MicroEngineInitialize(_eAMD_HW_RING_TYPE) 0000000000090762 __float128 0f SECT 01 0000 [.text] AMDVIPM4Engine::SubmitMapQueuesPacket(_eAMD_HW_RING_TYPE) 0000000000090878 __float128 0f SECT 01 0000 [.text] AMDVIPM4Engine::initializeMicroEngine() 0000000000090c02 __float128 0f SECT 01 0000 [.text] AMDVIPM4Engine::allocateAndInitHWRings() 0000000000090f2c __float128 0f SECT 01 0000 [.text] AMDVIPM4Engine::getTimestampIRQSourcex(_eAMD_HW_RING_TYPE) 00000000000914bc __float128 0f SECT 01 0000 [.text] AMDVIPM4Engine::toCailDetectHungBlocks() 0000000000090a1a __float128 0f SECT 01 0000 [.text] AMDVIPM4Engine::QueryComputeQueueStatus(_eAMD_HW_RING_TYPE) 0000000000090f44 __float128 0f SECT 01 0000 [.text] AMDVIPM4Engine::SubmitQueryStatusPacket(_eAMD_HW_RING_TYPE, unsigned long long) 000000000008fd2a __float128 0f SECT 01 0000 [.text] AMDVIPM4Engine::SubmitUnmapQueuesPacket(_eAMD_HW_RING_TYPE) 0000000000090be6 __float128 0f SECT 01 0000 [.text] AMDVIPM4Engine::resetGRBMOnCommandStart() 0000000000090178 __float128 0f SECT 01 0000 [.text] AMDVIPM4Engine::MicroEngineLoadMicrocode(_eAMD_HW_RING_TYPE) 00000000000906ea __float128 0f SECT 01 0000 [.text] AMDVIPM4Engine::SubmitSetResourcesPacket() 000000000008f870 __float128 0f SECT 01 0000 [.text] AMDVIPM4Engine::setMemoryAllocationsEnabled(bool) 0000000000090f26 __float128 0f SECT 01 0000 [.text] AMDVIPM4Engine::initializeTimestampRegisters(unsigned int) 00000000000912e0 __float128 0f SECT 01 0000 [.text] AMDVIPM4Engine::isComputeQueueUnmapCompleted(_eAMD_HW_RING_TYPE) 0000000000090584 __float128 0f SECT 01 0000 [.text] AMDVIPM4Engine::MicroEngineQueryMicrocodeVersion(_eAMD_HW_RING_TYPE) 000000000008f570 __float128 0f SECT 01 0000 [.text] AMDVIPM4Engine::free() 000000000008f4d2 __float128 0f SECT 01 0000 [.text] AMDVIPM4Engine::init(AMDRadeonX4000_IAMDHWInterface*, _eAMD_HW_ENGINE_TYPE) 000000000008faa2 __float128 0f SECT 01 0000 [.text] AMDVIPM4Engine::stop() 000000000009106c __float128 0f SECT 01 0000 [.text] AMDVIPM4Engine::reset(_eAMD_HW_RING_TYPE) 000000000008fa30 __float128 0f SECT 01 0000 [.text] AMDVIPM4Engine::start() 000000000008fb44 __float128 0f SECT 01 0000 [.text] AMDVIPM4Engine::haltME() 0000000000090998 __float128 0f SECT 01 0000 [.text] AMDVIPM4Engine::isIdle() 000000000008f9c0 __float128 0f SECT 01 0000 [.text] AMDVIPM4Engine::powerUp() 000000000008feda __float128 0f SECT 01 0000 [.text] AMDVIPM4Engine::startME() 000000000008f340 __float128 0f SECT 01 0000 [.text] AMDVIPM4Engine::MetaClass::MetaClass() 000000000008f400 __float128 0f SECT 01 0000 [.text] AMDVIPM4Engine::MetaClass::MetaClass() 00000000003bc390 __float128 0f SECT 08 0000 [.const_data] AMDVIPM4Engine::metaClass 0000000000090ea2 __float128 0f SECT 01 0000 [.text] AMDVIPM4Engine::softReset(unsigned int, unsigned int) 000000000008f39c __float128 0f SECT 01 0000 [.text] AMDVIPM4Engine::AMDVIPM4Engine(OSMetaClass const*) 000000000008f472 __float128 0f SECT 01 0000 [.text] AMDVIPM4Engine::AMDVIPM4Engine() 000000000008f37c __float128 0f SECT 01 0000 [.text] AMDVIPM4Engine::AMDVIPM4Engine(OSMetaClass const*) 000000000008f4a2 __float128 0f SECT 01 0000 [.text] AMDVIPM4Engine::AMDVIPM4Engine() 000000000008f3d0 __float128 0f SECT 01 0000 [.text] AMDVIPM4Engine::~AMDVIPM4Engine() 000000000008f3c6 __float128 0f SECT 01 0000 [.text] AMDVIPM4Engine::~AMDVIPM4Engine() 000000000008f3bc __float128 0f SECT 01 0000 [.text] AMDVIPM4Engine::~AMDVIPM4Engine() 000000000052e9b8 __float128 0f SECT 0a 0000 [__DATA.__common] AMDVIVMContext::gMetaClass 00000000003b9f68 __float128 0f SECT 08 0000 [.const_data] AMDVIVMContext::superClass 0000000000087ed2 __float128 0f SECT 01 0000 [.text] AMDVIVMContext::mapVA(unsigned long long, unsigned long long, IOMemoryDescriptor*, unsigned long long, unsigned long long, bool) 0000000000088d90 __float128 0f SECT 01 0000 [.text] AMDVIVMContext::unmapVA(unsigned long long, unsigned long long) 0000000000087d40 __float128 0f SECT 01 0000 [.text] AMDVIVMContext::MetaClass::MetaClass() 0000000000087e00 __float128 0f SECT 01 0000 [.text] AMDVIVMContext::MetaClass::MetaClass() 00000000003b9f60 __float128 0f SECT 08 0000 [.const_data] AMDVIVMContext::metaClass 0000000000087d9c __float128 0f SECT 01 0000 [.text] AMDVIVMContext::AMDVIVMContext(OSMetaClass const*) 0000000000087e72 __float128 0f SECT 01 0000 [.text] AMDVIVMContext::AMDVIVMContext() 0000000000087d7c __float128 0f SECT 01 0000 [.text] AMDVIVMContext::AMDVIVMContext(OSMetaClass const*) 0000000000087ea2 __float128 0f SECT 01 0000 [.text] AMDVIVMContext::AMDVIVMContext() 0000000000087dd0 __float128 0f SECT 01 0000 [.text] AMDVIVMContext::~AMDVIVMContext() 0000000000087dc6 __float128 0f SECT 01 0000 [.text] AMDVIVMContext::~AMDVIVMContext() 0000000000087dbc __float128 0f SECT 01 0000 [.text] AMDVIVMContext::~AMDVIVMContext() 00000000000da226 __float128 0f SECT 01 0000 [.text] EgBasedAddrLib::IsTileInfoAllZero(_ADDR_TILEINFO*) 00000000000da130 __float128 0f SECT 01 0000 [.text] EgBasedAddrLib::HwlComputeFmaskInfo(_ADDR_COMPUTE_FMASK_INFO_INPUT const*, _ADDR_COMPUTE_FMASK_INFO_OUTPUT*) 00000000000d9f08 __float128 0f SECT 01 0000 [.text] EgBasedAddrLib::DispatchComputeFmaskInfo(_ADDR_COMPUTE_FMASK_INFO_INPUT const*, _ADDR_COMPUTE_FMASK_INFO_OUTPUT*) 00000000000da1d8 __float128 0f SECT 01 0000 [.text] EgBasedAddrLib::ComputeFmaskNumPlanesFromNumSamples(unsigned int) 00000000000da202 __float128 0f SECT 01 0000 [.text] EgBasedAddrLib::ComputeFmaskResolvedBppFromNumSamples(unsigned int) 00000000000d7070 __float128 0f SECT 01 0000 [.text] EgBasedAddrLib::EgBasedAddrLib(AddrClient const*) 00000000000d709e __float128 0f SECT 01 0000 [.text] EgBasedAddrLib::~EgBasedAddrLib() 00000000000d70ba __float128 0f SECT 01 0000 [.text] EgBasedAddrLib::~EgBasedAddrLib() 00000000000d70c4 __float128 0f SECT 01 0000 [.text] EgBasedAddrLib::~EgBasedAddrLib() 000000000052e6e8 __float128 0f SECT 0a 0000 [__DATA.__common] AMDCIDMAChannel::gMetaClass 00000000003b57e8 __float128 0f SECT 08 0000 [.const_data] AMDCIDMAChannel::superClass 000000000007ec8e __float128 0f SECT 01 0000 [.text] AMDCIDMAChannel::submitVMInvalidate(unsigned int, unsigned long long, unsigned int) 000000000007eebe __float128 0f SECT 01 0000 [.text] AMDCIDMAChannel::initializeDmaPktInfo() 000000000007e7b2 __float128 0f SECT 01 0000 [.text] AMDCIDMAChannel::writeProfilingCommand(unsigned int*, unsigned long long, unsigned int, bool) 000000000007eb2e __float128 0f SECT 01 0000 [.text] AMDCIDMAChannel::writeSRBMWriteCommand(unsigned int*, unsigned int, unsigned int, unsigned int) 000000000007ee9a __float128 0f SECT 01 0000 [.text] AMDCIDMAChannel::timeStampInterruptType() 000000000007ea76 __float128 0f SECT 01 0000 [.text] AMDCIDMAChannel::writeCopyLinearCommand(unsigned int*, unsigned long long, unsigned long long, unsigned int) 000000000007ebbe __float128 0f SECT 01 0000 [.text] AMDCIDMAChannel::writePollRegMemCommand(unsigned int*, bool, unsigned long long, unsigned int, unsigned int, unsigned int, unsigned int, unsigned int) 000000000007e8ae __float128 0f SECT 01 0000 [.text] AMDCIDMAChannel::writeWriteLinearCommand(unsigned int*, unsigned long long, unsigned int, unsigned int*) 000000000007e99a __float128 0f SECT 01 0000 [.text] AMDCIDMAChannel::writeWritePTEPDECommand(unsigned int*, unsigned long long, unsigned int, unsigned long long, unsigned long long, unsigned long long) 000000000007e808 __float128 0f SECT 01 0000 [.text] AMDCIDMAChannel::writeConstantFillCommand(unsigned int*, unsigned long long, unsigned int, unsigned int) 000000000007e436 __float128 0f SECT 01 0000 [.text] AMDCIDMAChannel::commitIndirectCommandBuffer(AMD_SUBMIT_COMMAND_BUFFER_INFO*) 000000000007e622 __float128 0f SECT 01 0000 [.text] AMDCIDMAChannel::initializeVMInvalidateFrame() 000000000007ee5e __float128 0f SECT 01 0000 [.text] AMDCIDMAChannel::releaseIndirectCommandBufferFrame() 000000000007edd6 __float128 0f SECT 01 0000 [.text] AMDCIDMAChannel::initializeIndirectCommandBufferFrame() 000000000007e3ea __float128 0f SECT 01 0000 [.text] AMDCIDMAChannel::free() 000000000007e392 __float128 0f SECT 01 0000 [.text] AMDCIDMAChannel::init(int, AMDRadeonX4000_IAMDHWInterface*, AMDRadeonX4000_IAMDHWEngine*, AMDRadeonX4000_IAMDHWRing*, char const*) 000000000007e200 __float128 0f SECT 01 0000 [.text] AMDCIDMAChannel::MetaClass::MetaClass() 000000000007e2c0 __float128 0f SECT 01 0000 [.text] AMDCIDMAChannel::MetaClass::MetaClass() 00000000003b57e0 __float128 0f SECT 08 0000 [.const_data] AMDCIDMAChannel::metaClass 000000000007e25c __float128 0f SECT 01 0000 [.text] AMDCIDMAChannel::AMDCIDMAChannel(OSMetaClass const*) 000000000007e332 __float128 0f SECT 01 0000 [.text] AMDCIDMAChannel::AMDCIDMAChannel() 000000000007e23c __float128 0f SECT 01 0000 [.text] AMDCIDMAChannel::AMDCIDMAChannel(OSMetaClass const*) 000000000007e362 __float128 0f SECT 01 0000 [.text] AMDCIDMAChannel::AMDCIDMAChannel() 000000000007e290 __float128 0f SECT 01 0000 [.text] AMDCIDMAChannel::~AMDCIDMAChannel() 000000000007e286 __float128 0f SECT 01 0000 [.text] AMDCIDMAChannel::~AMDCIDMAChannel() 000000000007e27c __float128 0f SECT 01 0000 [.text] AMDCIDMAChannel::~AMDCIDMAChannel() 000000000052e6c0 __float128 0f SECT 0a 0000 [__DATA.__common] AMDCIPM4Channel::gMetaClass 00000000003b53d8 __float128 0f SECT 08 0000 [.const_data] AMDCIPM4Channel::superClass 000000000007e068 __float128 0f SECT 01 0000 [.text] AMDCIPM4Channel::clearResetEOPFence() 000000000007dbf4 __float128 0f SECT 01 0000 [.text] AMDCIPM4Channel::initializeCSBFrame() 000000000007d528 __float128 0f SECT 01 0000 [.text] AMDCIPM4Channel::writeDataCmdPacket(_PM4_WRITE_DATA*, WRITE_DATA_dst_sel_enum, WRITE_DATA_addr_incr_enum, WRITE_DATA_wr_confirm_enum, WRITE_DATA_cache_policy_enum, WRITE_DATA_engine_sel_enum, unsigned long long, unsigned int const*, unsigned int) 000000000007debe __float128 0f SECT 01 0000 [.text] AMDCIPM4Channel::eventWriteCmdPacket(_PM4_EVENT_WRITE*, EVENT_WRITE_event_index_enum, unsigned int) 000000000007d880 __float128 0f SECT 01 0000 [.text] AMDCIPM4Channel::releaseSubmitFrames() 000000000007dede __float128 0f SECT 01 0000 [.text] AMDCIPM4Channel::getIBAlignmentFactor() 000000000007d5e0 __float128 0f SECT 01 0000 [.text] AMDCIPM4Channel::surfaceSyncCmdPacket(_PM4_SURFACE_SYNC*, unsigned int, unsigned long long, unsigned long long, unsigned int) 000000000007dd42 __float128 0f SECT 01 0000 [.text] AMDCIPM4Channel::writeProfilingCommand(unsigned int*, unsigned long long, unsigned int, bool) 000000000007d97e __float128 0f SECT 01 0000 [.text] AMDCIPM4Channel::eventWriteEOPCmdPacket(_PM4_EVENT_WRITE_EOP*, unsigned int, EVENT_WRITE_EOP_event_index_enum, EVENT_WRITE_EOP_cache_policy_enum, EVENT_WRITE_EOP_dst_sel_enum, EVENT_WRITE_EOP_int_sel_enum, EVENT_WRITE_EOP_data_sel_enum, unsigned long long, unsigned long long) 000000000007d832 __float128 0f SECT 01 0000 [.text] AMDCIPM4Channel::initializeSubmitFrames() 000000000007df4c __float128 0f SECT 01 0000 [.text] AMDCIPM4Channel::writeEventWriteCommand(unsigned int*, unsigned int, unsigned int) 000000000007e084 __float128 0f SECT 01 0000 [.text] AMDCIPM4Channel::isResetEOPFenceFinished() 000000000007deea __float128 0f SECT 01 0000 [.text] AMDCIPM4Channel::writeSurfaceSyncCommand(unsigned int*, unsigned int, unsigned long long, unsigned long long, unsigned int) 000000000007d8bc __float128 0f SECT 01 0000 [.text] AMDCIPM4Channel::initializeTimestampFrame() 000000000007df6a __float128 0f SECT 01 0000 [.text] AMDCIPM4Channel::writeEventWriteEOPCommand(unsigned int*, unsigned int, unsigned int, unsigned long long, unsigned int, unsigned int, unsigned long long) 000000000007d642 __float128 0f SECT 01 0000 [.text] AMDCIPM4Channel::commitIndirectCommandBuffer(AMD_SUBMIT_COMMAND_BUFFER_INFO*) 000000000007dfa2 __float128 0f SECT 01 0000 [.text] AMDCIPM4Channel::prepareAndFlushResetEOPFence() 000000000007da32 __float128 0f SECT 01 0000 [.text] AMDCIPM4Channel::initializeIndirectCommandBufferFrame() 000000000007d3e4 __float128 0f SECT 01 0000 [.text] AMDCIPM4Channel::writeFlushAndInvalidateDestinationCachesCommands() 000000000007d3d2 __float128 0f SECT 01 0000 [.text] AMDCIPM4Channel::free() 000000000007d362 __float128 0f SECT 01 0000 [.text] AMDCIPM4Channel::init(int, AMDRadeonX4000_IAMDHWInterface*, AMDRadeonX4000_IAMDHWEngine*, AMDRadeonX4000_IAMDHWRing*, char const*) 000000000007d1d0 __float128 0f SECT 01 0000 [.text] AMDCIPM4Channel::MetaClass::MetaClass() 000000000007d290 __float128 0f SECT 01 0000 [.text] AMDCIPM4Channel::MetaClass::MetaClass() 00000000003b53d0 __float128 0f SECT 08 0000 [.const_data] AMDCIPM4Channel::metaClass 000000000007d22c __float128 0f SECT 01 0000 [.text] AMDCIPM4Channel::AMDCIPM4Channel(OSMetaClass const*) 000000000007d302 __float128 0f SECT 01 0000 [.text] AMDCIPM4Channel::AMDCIPM4Channel() 000000000007d20c __float128 0f SECT 01 0000 [.text] AMDCIPM4Channel::AMDCIPM4Channel(OSMetaClass const*) 000000000007d332 __float128 0f SECT 01 0000 [.text] AMDCIPM4Channel::AMDCIPM4Channel() 000000000007d260 __float128 0f SECT 01 0000 [.text] AMDCIPM4Channel::~AMDCIPM4Channel() 000000000007d256 __float128 0f SECT 01 0000 [.text] AMDCIPM4Channel::~AMDCIPM4Channel() 000000000007d24c __float128 0f SECT 01 0000 [.text] AMDCIPM4Channel::~AMDCIPM4Channel() 000000000052e710 __float128 0f SECT 0a 0000 [__DATA.__common] AMDCISAMUEngine::gMetaClass 00000000003b5be8 __float128 0f SECT 08 0000 [.const_data] AMDCISAMUEngine::superClass 000000000007f630 __float128 0f SECT 01 0000 [.text] AMDCISAMUEngine::suspendSPU() 000000000007f36c __float128 0f SECT 01 0000 [.text] AMDCISAMUEngine::initHardware() 000000000007f526 __float128 0f SECT 01 0000 [.text] AMDCISAMUEngine::initializeSPU() 000000000007f674 __float128 0f SECT 01 0000 [.text] AMDCISAMUEngine::allocateHWRings() 000000000007f778 __float128 0f SECT 01 0000 [.text] AMDCISAMUEngine::enableSPUClocks() 000000000007f448 __float128 0f SECT 01 0000 [.text] AMDCISAMUEngine::releaseHardware() 000000000007f77e __float128 0f SECT 01 0000 [.text] AMDCISAMUEngine::disableSPUClocks() 000000000007f6fa __float128 0f SECT 01 0000 [.text] AMDCISAMUEngine::allocateHWChannels() 000000000007f784 __float128 0f SECT 01 0000 [.text] AMDCISAMUEngine::readIndirectSPUReg(unsigned int) 000000000007f88c __float128 0f SECT 01 0000 [.text] AMDCISAMUEngine::dumpEngineHangState(bool) 000000000007f7c4 __float128 0f SECT 01 0000 [.text] AMDCISAMUEngine::writeIndirectSPUReg(unsigned int, unsigned int) 000000000007f2fa __float128 0f SECT 01 0000 [.text] AMDCISAMUEngine::setMemoryAllocations(bool) 000000000007f27a __float128 0f SECT 01 0000 [.text] AMDCISAMUEngine::setSuspendResumeState(bool) 000000000007f808 __float128 0f SECT 01 0000 [.text] AMDCISAMUEngine::readIndirectSAMUSABReg(unsigned int) 000000000007f848 __float128 0f SECT 01 0000 [.text] AMDCISAMUEngine::writeIndirectSAMUSABReg(unsigned int, unsigned int) 000000000007f242 __float128 0f SECT 01 0000 [.text] AMDCISAMUEngine::init(AMDRadeonX4000_IAMDHWInterface*, _eAMD_HW_ENGINE_TYPE) 000000000007f770 __float128 0f SECT 01 0000 [.text] AMDCISAMUEngine::isIdle() 000000000007f0b0 __float128 0f SECT 01 0000 [.text] AMDCISAMUEngine::MetaClass::MetaClass() 000000000007f170 __float128 0f SECT 01 0000 [.text] AMDCISAMUEngine::MetaClass::MetaClass() 00000000003b5be0 __float128 0f SECT 08 0000 [.const_data] AMDCISAMUEngine::metaClass 000000000007f10c __float128 0f SECT 01 0000 [.text] AMDCISAMUEngine::AMDCISAMUEngine(OSMetaClass const*) 000000000007f1e2 __float128 0f SECT 01 0000 [.text] AMDCISAMUEngine::AMDCISAMUEngine() 000000000007f0ec __float128 0f SECT 01 0000 [.text] AMDCISAMUEngine::AMDCISAMUEngine(OSMetaClass const*) 000000000007f212 __float128 0f SECT 01 0000 [.text] AMDCISAMUEngine::AMDCISAMUEngine() 000000000007f140 __float128 0f SECT 01 0000 [.text] AMDCISAMUEngine::~AMDCISAMUEngine() 000000000007f136 __float128 0f SECT 01 0000 [.text] AMDCISAMUEngine::~AMDCISAMUEngine() 000000000007f12c __float128 0f SECT 01 0000 [.text] AMDCISAMUEngine::~AMDCISAMUEngine() 000000000052e828 __float128 0f SECT 0a 0000 [__DATA.__common] AMDCIVCEChannel::gMetaClass 00000000003b75f8 __float128 0f SECT 08 0000 [.const_data] AMDCIVCEChannel::superClass 0000000000081d60 __float128 0f SECT 01 0000 [.text] AMDCIVCEChannel::getIndirectCommandSize() 0000000000081e1c __float128 0f SECT 01 0000 [.text] AMDCIVCEChannel::commitIndirectCommandBuffer(AMD_SUBMIT_COMMAND_BUFFER_INFO*) 0000000000081db2 __float128 0f SECT 01 0000 [.text] AMDCIVCEChannel::initializeIndirectCommandBufferFrame() 0000000000081d4e __float128 0f SECT 01 0000 [.text] AMDCIVCEChannel::free() 0000000000081d32 __float128 0f SECT 01 0000 [.text] AMDCIVCEChannel::init(int, AMDRadeonX4000_IAMDHWInterface*, AMDRadeonX4000_IAMDHWEngine*, AMDRadeonX4000_IAMDHWRing*, char const*) 0000000000081ba0 __float128 0f SECT 01 0000 [.text] AMDCIVCEChannel::MetaClass::MetaClass() 0000000000081c60 __float128 0f SECT 01 0000 [.text] AMDCIVCEChannel::MetaClass::MetaClass() 00000000003b75f0 __float128 0f SECT 08 0000 [.const_data] AMDCIVCEChannel::metaClass 0000000000081bfc __float128 0f SECT 01 0000 [.text] AMDCIVCEChannel::AMDCIVCEChannel(OSMetaClass const*) 0000000000081cd2 __float128 0f SECT 01 0000 [.text] AMDCIVCEChannel::AMDCIVCEChannel() 0000000000081bdc __float128 0f SECT 01 0000 [.text] AMDCIVCEChannel::AMDCIVCEChannel(OSMetaClass const*) 0000000000081d02 __float128 0f SECT 01 0000 [.text] AMDCIVCEChannel::AMDCIVCEChannel() 0000000000081c30 __float128 0f SECT 01 0000 [.text] AMDCIVCEChannel::~AMDCIVCEChannel() 0000000000081c26 __float128 0f SECT 01 0000 [.text] AMDCIVCEChannel::~AMDCIVCEChannel() 0000000000081c1c __float128 0f SECT 01 0000 [.text] AMDCIVCEChannel::~AMDCIVCEChannel() 000000000052e8a0 __float128 0f SECT 0a 0000 [__DATA.__common] AMDCIVCELLQRing::gMetaClass 00000000003b8078 __float128 0f SECT 08 0000 [.const_data] AMDCIVCELLQRing::superClass 0000000000082b44 __float128 0f SECT 01 0000 [.text] AMDCIVCELLQRing::registerLocation() 0000000000082b32 __float128 0f SECT 01 0000 [.text] AMDCIVCELLQRing::free() 0000000000082a92 __float128 0f SECT 01 0000 [.text] AMDCIVCELLQRing::init(AMDRadeonX4000_IAMDHWInterface*, int, _eAMD_HW_ENGINE_TYPE, unsigned int, void const*) 0000000000082900 __float128 0f SECT 01 0000 [.text] AMDCIVCELLQRing::MetaClass::MetaClass() 00000000000829c0 __float128 0f SECT 01 0000 [.text] AMDCIVCELLQRing::MetaClass::MetaClass() 00000000003b8070 __float128 0f SECT 08 0000 [.const_data] AMDCIVCELLQRing::metaClass 000000000008295c __float128 0f SECT 01 0000 [.text] AMDCIVCELLQRing::AMDCIVCELLQRing(OSMetaClass const*) 0000000000082a32 __float128 0f SECT 01 0000 [.text] AMDCIVCELLQRing::AMDCIVCELLQRing() 000000000008293c __float128 0f SECT 01 0000 [.text] AMDCIVCELLQRing::AMDCIVCELLQRing(OSMetaClass const*) 0000000000082a62 __float128 0f SECT 01 0000 [.text] AMDCIVCELLQRing::AMDCIVCELLQRing() 0000000000082990 __float128 0f SECT 01 0000 [.text] AMDCIVCELLQRing::~AMDCIVCELLQRing() 0000000000082986 __float128 0f SECT 01 0000 [.text] AMDCIVCELLQRing::~AMDCIVCELLQRing() 000000000008297c __float128 0f SECT 01 0000 [.text] AMDCIVCELLQRing::~AMDCIVCELLQRing() 000000000052e5d0 __float128 0f SECT 0a 0000 [__DATA.__common] AMDCIsDMAEngine::gMetaClass 00000000003b4048 __float128 0f SECT 08 0000 [.const_data] AMDCIsDMAEngine::superClass 0000000000079e0a __float128 0f SECT 01 0000 [.text] AMDCIsDMAEngine::allocateHWRings() 0000000000079e46 __float128 0f SECT 01 0000 [.text] AMDCIsDMAEngine::allocateHWChannels() 000000000007a2ce __float128 0f SECT 01 0000 [.text] AMDCIsDMAEngine::dumpEngineHangState(bool) 0000000000079d22 __float128 0f SECT 01 0000 [.text] AMDCIsDMAEngine::init(AMDRadeonX4000_IAMDHWInterface*, _eAMD_HW_ENGINE_TYPE) 000000000007a164 __float128 0f SECT 01 0000 [.text] AMDCIsDMAEngine::stop() 0000000000079e92 __float128 0f SECT 01 0000 [.text] AMDCIsDMAEngine::start() 0000000000079dbe __float128 0f SECT 01 0000 [.text] AMDCIsDMAEngine::isIdle() 0000000000079b90 __float128 0f SECT 01 0000 [.text] AMDCIsDMAEngine::MetaClass::MetaClass() 0000000000079c50 __float128 0f SECT 01 0000 [.text] AMDCIsDMAEngine::MetaClass::MetaClass() 00000000003b4040 __float128 0f SECT 08 0000 [.const_data] AMDCIsDMAEngine::metaClass 0000000000079bec __float128 0f SECT 01 0000 [.text] AMDCIsDMAEngine::AMDCIsDMAEngine(OSMetaClass const*) 0000000000079cc2 __float128 0f SECT 01 0000 [.text] AMDCIsDMAEngine::AMDCIsDMAEngine() 0000000000079bcc __float128 0f SECT 01 0000 [.text] AMDCIsDMAEngine::AMDCIsDMAEngine(OSMetaClass const*) 0000000000079cf2 __float128 0f SECT 01 0000 [.text] AMDCIsDMAEngine::AMDCIsDMAEngine() 0000000000079c20 __float128 0f SECT 01 0000 [.text] AMDCIsDMAEngine::~AMDCIsDMAEngine() 0000000000079c16 __float128 0f SECT 01 0000 [.text] AMDCIsDMAEngine::~AMDCIsDMAEngine() 0000000000079c0c __float128 0f SECT 01 0000 [.text] AMDCIsDMAEngine::~AMDCIsDMAEngine() 000000000052e2b0 __float128 0f SECT 0a 0000 [__DATA.__common] AMDSIDMAChannel::gMetaClass 00000000003aee18 __float128 0f SECT 08 0000 [.const_data] AMDSIDMAChannel::superClass 000000000006e170 __float128 0f SECT 01 0000 [.text] AMDSIDMAChannel::submitVMInvalidate(unsigned int, unsigned long long, unsigned int) 000000000006e90e __float128 0f SECT 01 0000 [.text] AMDSIDMAChannel::initializeDmaPktInfo() 000000000006e89a __float128 0f SECT 01 0000 [.text] AMDSIDMAChannel::writeProfilingCommand(unsigned int*, unsigned long long, unsigned int, bool) 000000000006dfb6 __float128 0f SECT 01 0000 [.text] AMDSIDMAChannel::writeSRBMWriteCommand(unsigned int*, unsigned int, unsigned int, unsigned int) 000000000006e8ea __float128 0f SECT 01 0000 [.text] AMDSIDMAChannel::timeStampInterruptType() 000000000006df08 __float128 0f SECT 01 0000 [.text] AMDSIDMAChannel::writeCopyLinearCommand(unsigned int*, unsigned long long, unsigned long long, unsigned int) 000000000006e066 __float128 0f SECT 01 0000 [.text] AMDSIDMAChannel::writePollRegMemCommand(unsigned int*, bool, unsigned long long, unsigned int, unsigned int, unsigned int, unsigned int, unsigned int) 000000000006dd2c __float128 0f SECT 01 0000 [.text] AMDSIDMAChannel::writeWriteLinearCommand(unsigned int*, unsigned long long, unsigned int, unsigned int*) 000000000006de18 __float128 0f SECT 01 0000 [.text] AMDSIDMAChannel::writeWritePTEPDECommand(unsigned int*, unsigned long long, unsigned int, unsigned long long, unsigned long long, unsigned long long) 000000000006dc92 __float128 0f SECT 01 0000 [.text] AMDSIDMAChannel::writeConstantFillCommand(unsigned int*, unsigned long long, unsigned int, unsigned int) 000000000006e2f2 __float128 0f SECT 01 0000 [.text] AMDSIDMAChannel::commitIndirectCommandBuffer(AMD_SUBMIT_COMMAND_BUFFER_INFO*) 000000000006e6c0 __float128 0f SECT 01 0000 [.text] AMDSIDMAChannel::initializeVMInvalidateFrame() 000000000006e684 __float128 0f SECT 01 0000 [.text] AMDSIDMAChannel::releaseIndirectCommandBufferFrame() 000000000006e55a __float128 0f SECT 01 0000 [.text] AMDSIDMAChannel::initializeIndirectCommandBufferFrame() 000000000006dc4a __float128 0f SECT 01 0000 [.text] AMDSIDMAChannel::free() 000000000006dbf2 __float128 0f SECT 01 0000 [.text] AMDSIDMAChannel::init(int, AMDRadeonX4000_IAMDHWInterface*, AMDRadeonX4000_IAMDHWEngine*, AMDRadeonX4000_IAMDHWRing*, char const*) 000000000006da60 __float128 0f SECT 01 0000 [.text] AMDSIDMAChannel::MetaClass::MetaClass() 000000000006db20 __float128 0f SECT 01 0000 [.text] AMDSIDMAChannel::MetaClass::MetaClass() 00000000003aee10 __float128 0f SECT 08 0000 [.const_data] AMDSIDMAChannel::metaClass 000000000006dabc __float128 0f SECT 01 0000 [.text] AMDSIDMAChannel::AMDSIDMAChannel(OSMetaClass const*) 000000000006db92 __float128 0f SECT 01 0000 [.text] AMDSIDMAChannel::AMDSIDMAChannel() 000000000006da9c __float128 0f SECT 01 0000 [.text] AMDSIDMAChannel::AMDSIDMAChannel(OSMetaClass const*) 000000000006dbc2 __float128 0f SECT 01 0000 [.text] AMDSIDMAChannel::AMDSIDMAChannel() 000000000006daf0 __float128 0f SECT 01 0000 [.text] AMDSIDMAChannel::~AMDSIDMAChannel() 000000000006dae6 __float128 0f SECT 01 0000 [.text] AMDSIDMAChannel::~AMDSIDMAChannel() 000000000006dadc __float128 0f SECT 01 0000 [.text] AMDSIDMAChannel::~AMDSIDMAChannel() 000000000052e238 __float128 0f SECT 0a 0000 [__DATA.__common] AMDSIPM4Channel::gMetaClass 00000000003ae3d8 __float128 0f SECT 08 0000 [.const_data] AMDSIPM4Channel::superClass 000000000006ca78 __float128 0f SECT 01 0000 [.text] AMDSIPM4Channel::releaseSubmitFrames() 000000000006cafe __float128 0f SECT 01 0000 [.text] AMDSIPM4Channel::resetPerFramePacket() 000000000006cab4 __float128 0f SECT 01 0000 [.text] AMDSIPM4Channel::setupPerFramePacket(unsigned int, unsigned int, unsigned int, unsigned int) 000000000006cdb2 __float128 0f SECT 01 0000 [.text] AMDSIPM4Channel::getIBAlignmentFactor() 000000000006ccd6 __float128 0f SECT 01 0000 [.text] AMDSIPM4Channel::writeProfilingCommand(unsigned int*, unsigned long long, unsigned int, bool) 000000000006c898 __float128 0f SECT 01 0000 [.text] AMDSIPM4Channel::initializeSubmitFrames() 000000000006c8da __float128 0f SECT 01 0000 [.text] AMDSIPM4Channel::initializeTimestampFrame() 000000000006c6fe __float128 0f SECT 01 0000 [.text] AMDSIPM4Channel::commitIndirectCommandBuffer(AMD_SUBMIT_COMMAND_BUFFER_INFO*) 000000000006cb98 __float128 0f SECT 01 0000 [.text] AMDSIPM4Channel::enableScratchRegisterWriteback() 000000000006cb1e __float128 0f SECT 01 0000 [.text] AMDSIPM4Channel::disableScratchRegisterWriteback() 000000000006c948 __float128 0f SECT 01 0000 [.text] AMDSIPM4Channel::initializeIndirectCommandBufferFrame() 000000000006c6b0 __float128 0f SECT 01 0000 [.text] AMDSIPM4Channel::writeFlushAndInvalidateDestinationCachesCommands() 000000000006c69e __float128 0f SECT 01 0000 [.text] AMDSIPM4Channel::free() 000000000006c682 __float128 0f SECT 01 0000 [.text] AMDSIPM4Channel::init(int, AMDRadeonX4000_IAMDHWInterface*, AMDRadeonX4000_IAMDHWEngine*, AMDRadeonX4000_IAMDHWRing*, char const*) 000000000006c4f0 __float128 0f SECT 01 0000 [.text] AMDSIPM4Channel::MetaClass::MetaClass() 000000000006c5b0 __float128 0f SECT 01 0000 [.text] AMDSIPM4Channel::MetaClass::MetaClass() 00000000003ae3d0 __float128 0f SECT 08 0000 [.const_data] AMDSIPM4Channel::metaClass 000000000006c54c __float128 0f SECT 01 0000 [.text] AMDSIPM4Channel::AMDSIPM4Channel(OSMetaClass const*) 000000000006c622 __float128 0f SECT 01 0000 [.text] AMDSIPM4Channel::AMDSIPM4Channel() 000000000006c52c __float128 0f SECT 01 0000 [.text] AMDSIPM4Channel::AMDSIPM4Channel(OSMetaClass const*) 000000000006c652 __float128 0f SECT 01 0000 [.text] AMDSIPM4Channel::AMDSIPM4Channel() 000000000006c580 __float128 0f SECT 01 0000 [.text] AMDSIPM4Channel::~AMDSIPM4Channel() 000000000006c576 __float128 0f SECT 01 0000 [.text] AMDSIPM4Channel::~AMDSIPM4Channel() 000000000006c56c __float128 0f SECT 01 0000 [.text] AMDSIPM4Channel::~AMDSIPM4Channel() 000000000052e468 __float128 0f SECT 0a 0000 [__DATA.__common] AMDSISPUChannel::gMetaClass 00000000003b1638 __float128 0f SECT 08 0000 [.const_data] AMDSISPUChannel::superClass 000000000007308c __float128 0f SECT 01 0000 [.text] AMDSISPUChannel::commitIndirectCommandBuffer(AMD_SUBMIT_COMMAND_BUFFER_INFO*) 000000000007307a __float128 0f SECT 01 0000 [.text] AMDSISPUChannel::free() 0000000000073022 __float128 0f SECT 01 0000 [.text] AMDSISPUChannel::init(int, AMDRadeonX4000_IAMDHWInterface*, AMDRadeonX4000_IAMDHWEngine*, AMDRadeonX4000_IAMDHWRing*, char const*) 0000000000072e90 __float128 0f SECT 01 0000 [.text] AMDSISPUChannel::MetaClass::MetaClass() 0000000000072f50 __float128 0f SECT 01 0000 [.text] AMDSISPUChannel::MetaClass::MetaClass() 00000000003b1630 __float128 0f SECT 08 0000 [.const_data] AMDSISPUChannel::metaClass 0000000000072eec __float128 0f SECT 01 0000 [.text] AMDSISPUChannel::AMDSISPUChannel(OSMetaClass const*) 0000000000072fc2 __float128 0f SECT 01 0000 [.text] AMDSISPUChannel::AMDSISPUChannel() 0000000000072ecc __float128 0f SECT 01 0000 [.text] AMDSISPUChannel::AMDSISPUChannel(OSMetaClass const*) 0000000000072ff2 __float128 0f SECT 01 0000 [.text] AMDSISPUChannel::AMDSISPUChannel() 0000000000072f20 __float128 0f SECT 01 0000 [.text] AMDSISPUChannel::~AMDSISPUChannel() 0000000000072f16 __float128 0f SECT 01 0000 [.text] AMDSISPUChannel::~AMDSISPUChannel() 0000000000072f0c __float128 0f SECT 01 0000 [.text] AMDSISPUChannel::~AMDSISPUChannel() 000000000052e3c8 __float128 0f SECT 0a 0000 [__DATA.__common] AMDSIUVDChannel::gMetaClass 00000000003b06d8 __float128 0f SECT 08 0000 [.const_data] AMDSIUVDChannel::superClass 0000000000070fda __float128 0f SECT 01 0000 [.text] AMDSIUVDChannel::initializeTrapCmd() 0000000000070f92 __float128 0f SECT 01 0000 [.text] AMDSIUVDChannel::initializeFenceCmd() 000000000007112c __float128 0f SECT 01 0000 [.text] AMDSIUVDChannel::getOneDwordNOPCommand() 0000000000071138 __float128 0f SECT 01 0000 [.text] AMDSIUVDChannel::capPerfTableStatesForUVD(bool) 0000000000071048 __float128 0f SECT 01 0000 [.text] AMDSIUVDChannel::commitIndirectCommandBuffer(AMD_SUBMIT_COMMAND_BUFFER_INFO*) 0000000000070f70 __float128 0f SECT 01 0000 [.text] AMDSIUVDChannel::initializeIndirectBufferCmd() 0000000000070ed8 __float128 0f SECT 01 0000 [.text] AMDSIUVDChannel::initializeIndirectCommandBufferFrame() 0000000000070ec6 __float128 0f SECT 01 0000 [.text] AMDSIUVDChannel::free() 0000000000070e62 __float128 0f SECT 01 0000 [.text] AMDSIUVDChannel::init(int, AMDRadeonX4000_IAMDHWInterface*, AMDRadeonX4000_IAMDHWEngine*, AMDRadeonX4000_IAMDHWRing*, char const*) 0000000000070cd0 __float128 0f SECT 01 0000 [.text] AMDSIUVDChannel::MetaClass::MetaClass() 0000000000070d90 __float128 0f SECT 01 0000 [.text] AMDSIUVDChannel::MetaClass::MetaClass() 00000000003b06d0 __float128 0f SECT 08 0000 [.const_data] AMDSIUVDChannel::metaClass 0000000000070d2c __float128 0f SECT 01 0000 [.text] AMDSIUVDChannel::AMDSIUVDChannel(OSMetaClass const*) 0000000000070e02 __float128 0f SECT 01 0000 [.text] AMDSIUVDChannel::AMDSIUVDChannel() 0000000000070d0c __float128 0f SECT 01 0000 [.text] AMDSIUVDChannel::AMDSIUVDChannel(OSMetaClass const*) 0000000000070e32 __float128 0f SECT 01 0000 [.text] AMDSIUVDChannel::AMDSIUVDChannel() 0000000000070d60 __float128 0f SECT 01 0000 [.text] AMDSIUVDChannel::~AMDSIUVDChannel() 0000000000070d56 __float128 0f SECT 01 0000 [.text] AMDSIUVDChannel::~AMDSIUVDChannel() 0000000000070d4c __float128 0f SECT 01 0000 [.text] AMDSIUVDChannel::~AMDSIUVDChannel() 000000000052e328 __float128 0f SECT 0a 0000 [__DATA.__common] AMDSIVCEChannel::gMetaClass 00000000003af938 __float128 0f SECT 08 0000 [.const_data] AMDSIVCEChannel::superClass 000000000006fd40 __float128 0f SECT 01 0000 [.text] AMDSIVCEChannel::getIndirectCommandSize() 000000000006fdfc __float128 0f SECT 01 0000 [.text] AMDSIVCEChannel::commitIndirectCommandBuffer(AMD_SUBMIT_COMMAND_BUFFER_INFO*) 000000000006fd92 __float128 0f SECT 01 0000 [.text] AMDSIVCEChannel::initializeIndirectCommandBufferFrame() 000000000006fd2e __float128 0f SECT 01 0000 [.text] AMDSIVCEChannel::free() 000000000006fd12 __float128 0f SECT 01 0000 [.text] AMDSIVCEChannel::init(int, AMDRadeonX4000_IAMDHWInterface*, AMDRadeonX4000_IAMDHWEngine*, AMDRadeonX4000_IAMDHWRing*, char const*) 000000000006fb80 __float128 0f SECT 01 0000 [.text] AMDSIVCEChannel::MetaClass::MetaClass() 000000000006fc40 __float128 0f SECT 01 0000 [.text] AMDSIVCEChannel::MetaClass::MetaClass() 00000000003af930 __float128 0f SECT 08 0000 [.const_data] AMDSIVCEChannel::metaClass 000000000006fbdc __float128 0f SECT 01 0000 [.text] AMDSIVCEChannel::AMDSIVCEChannel(OSMetaClass const*) 000000000006fcb2 __float128 0f SECT 01 0000 [.text] AMDSIVCEChannel::AMDSIVCEChannel() 000000000006fbbc __float128 0f SECT 01 0000 [.text] AMDSIVCEChannel::AMDSIVCEChannel(OSMetaClass const*) 000000000006fce2 __float128 0f SECT 01 0000 [.text] AMDSIVCEChannel::AMDSIVCEChannel() 000000000006fc10 __float128 0f SECT 01 0000 [.text] AMDSIVCEChannel::~AMDSIVCEChannel() 000000000006fc06 __float128 0f SECT 01 0000 [.text] AMDSIVCEChannel::~AMDSIVCEChannel() 000000000006fbfc __float128 0f SECT 01 0000 [.text] AMDSIVCEChannel::~AMDSIVCEChannel() 000000000052e3a0 __float128 0f SECT 0a 0000 [__DATA.__common] AMDSIVCELLQRing::gMetaClass 00000000003b03b8 __float128 0f SECT 08 0000 [.const_data] AMDSIVCELLQRing::superClass 0000000000070b24 __float128 0f SECT 01 0000 [.text] AMDSIVCELLQRing::registerLocation() 0000000000070b12 __float128 0f SECT 01 0000 [.text] AMDSIVCELLQRing::free() 0000000000070a72 __float128 0f SECT 01 0000 [.text] AMDSIVCELLQRing::init(AMDRadeonX4000_IAMDHWInterface*, int, _eAMD_HW_ENGINE_TYPE, unsigned int, void const*) 00000000000708e0 __float128 0f SECT 01 0000 [.text] AMDSIVCELLQRing::MetaClass::MetaClass() 00000000000709a0 __float128 0f SECT 01 0000 [.text] AMDSIVCELLQRing::MetaClass::MetaClass() 00000000003b03b0 __float128 0f SECT 08 0000 [.const_data] AMDSIVCELLQRing::metaClass 000000000007093c __float128 0f SECT 01 0000 [.text] AMDSIVCELLQRing::AMDSIVCELLQRing(OSMetaClass const*) 0000000000070a12 __float128 0f SECT 01 0000 [.text] AMDSIVCELLQRing::AMDSIVCELLQRing() 000000000007091c __float128 0f SECT 01 0000 [.text] AMDSIVCELLQRing::AMDSIVCELLQRing(OSMetaClass const*) 0000000000070a42 __float128 0f SECT 01 0000 [.text] AMDSIVCELLQRing::AMDSIVCELLQRing() 0000000000070970 __float128 0f SECT 01 0000 [.text] AMDSIVCELLQRing::~AMDSIVCELLQRing() 0000000000070966 __float128 0f SECT 01 0000 [.text] AMDSIVCELLQRing::~AMDSIVCELLQRing() 000000000007095c __float128 0f SECT 01 0000 [.text] AMDSIVCELLQRing::~AMDSIVCELLQRing() 000000000052eb20 __float128 0f SECT 0a 0000 [__DATA.__common] AMDVIPM4Channel::gMetaClass 00000000003bbcc8 __float128 0f SECT 08 0000 [.const_data] AMDVIPM4Channel::superClass 000000000008ed5a __float128 0f SECT 01 0000 [.text] AMDVIPM4Channel::clearResetEOPFence() 000000000008e8e6 __float128 0f SECT 01 0000 [.text] AMDVIPM4Channel::initializeCSBFrame() 000000000008ebb0 __float128 0f SECT 01 0000 [.text] AMDVIPM4Channel::eventWriteCmdPacket(PM4_ME_EVENT_WRITE*, ME_EVENT_WRITE_event_index_enum, unsigned int) 000000000008e572 __float128 0f SECT 01 0000 [.text] AMDVIPM4Channel::releaseSubmitFrames() 000000000008ebd0 __float128 0f SECT 01 0000 [.text] AMDVIPM4Channel::getIBAlignmentFactor() 000000000008e2d2 __float128 0f SECT 01 0000 [.text] AMDVIPM4Channel::surfaceSyncCmdPacket(PM4_ME_SURFACE_SYNC*, unsigned int, unsigned long long, unsigned long long, unsigned int) 000000000008ea34 __float128 0f SECT 01 0000 [.text] AMDVIPM4Channel::writeProfilingCommand(unsigned int*, unsigned long long, unsigned int, bool) 000000000008e218 __float128 0f SECT 01 0000 [.text] AMDVIPM4Channel::writeRegDataCmdPacket(PM4_ME_WRITE_DATA*, ME_WRITE_DATA_dst_sel_enum, ME_WRITE_DATA_addr_incr_enum, ME_WRITE_DATA_wr_confirm_enum, ME_WRITE_DATA_cache_policy_enum, ME_WRITE_DATA_engine_sel_enum, unsigned short, unsigned int const*, unsigned int) 000000000008e670 __float128 0f SECT 01 0000 [.text] AMDVIPM4Channel::eventWriteEOPCmdPacket(PM4_ME_EVENT_WRITE_EOP*, unsigned int, ME_EVENT_WRITE_EOP_event_index_enum, ME_EVENT_WRITE_EOP_cache_policy_enum, ME_EVENT_WRITE_EOP_dst_sel_enum, ME_EVENT_WRITE_EOP_int_sel_enum, ME_EVENT_WRITE_EOP_data_sel_enum, unsigned long long, unsigned long long) 000000000008e524 __float128 0f SECT 01 0000 [.text] AMDVIPM4Channel::initializeSubmitFrames() 000000000008ec3e __float128 0f SECT 01 0000 [.text] AMDVIPM4Channel::writeEventWriteCommand(unsigned int*, unsigned int, unsigned int) 000000000008ed76 __float128 0f SECT 01 0000 [.text] AMDVIPM4Channel::isResetEOPFenceFinished() 000000000008ebdc __float128 0f SECT 01 0000 [.text] AMDVIPM4Channel::writeSurfaceSyncCommand(unsigned int*, unsigned int, unsigned long long, unsigned long long, unsigned int) 000000000008e5ae __float128 0f SECT 01 0000 [.text] AMDVIPM4Channel::initializeTimestampFrame() 000000000008ec5c __float128 0f SECT 01 0000 [.text] AMDVIPM4Channel::writeEventWriteEOPCommand(unsigned int*, unsigned int, unsigned int, unsigned long long, unsigned int, unsigned int, unsigned long long) 000000000008e334 __float128 0f SECT 01 0000 [.text] AMDVIPM4Channel::commitIndirectCommandBuffer(AMD_SUBMIT_COMMAND_BUFFER_INFO*) 000000000008ec94 __float128 0f SECT 01 0000 [.text] AMDVIPM4Channel::prepareAndFlushResetEOPFence() 000000000008e724 __float128 0f SECT 01 0000 [.text] AMDVIPM4Channel::initializeIndirectCommandBufferFrame() 000000000008e0d4 __float128 0f SECT 01 0000 [.text] AMDVIPM4Channel::writeFlushAndInvalidateDestinationCachesCommands() 000000000008e0c2 __float128 0f SECT 01 0000 [.text] AMDVIPM4Channel::free() 000000000008e052 __float128 0f SECT 01 0000 [.text] AMDVIPM4Channel::init(int, AMDRadeonX4000_IAMDHWInterface*, AMDRadeonX4000_IAMDHWEngine*, AMDRadeonX4000_IAMDHWRing*, char const*) 000000000008dec0 __float128 0f SECT 01 0000 [.text] AMDVIPM4Channel::MetaClass::MetaClass() 000000000008df80 __float128 0f SECT 01 0000 [.text] AMDVIPM4Channel::MetaClass::MetaClass() 00000000003bbcc0 __float128 0f SECT 08 0000 [.const_data] AMDVIPM4Channel::metaClass 000000000008df1c __float128 0f SECT 01 0000 [.text] AMDVIPM4Channel::AMDVIPM4Channel(OSMetaClass const*) 000000000008dff2 __float128 0f SECT 01 0000 [.text] AMDVIPM4Channel::AMDVIPM4Channel() 000000000008defc __float128 0f SECT 01 0000 [.text] AMDVIPM4Channel::AMDVIPM4Channel(OSMetaClass const*) 000000000008e022 __float128 0f SECT 01 0000 [.text] AMDVIPM4Channel::AMDVIPM4Channel() 000000000008df50 __float128 0f SECT 01 0000 [.text] AMDVIPM4Channel::~AMDVIPM4Channel() 000000000008df46 __float128 0f SECT 01 0000 [.text] AMDVIPM4Channel::~AMDVIPM4Channel() 000000000008df3c __float128 0f SECT 01 0000 [.text] AMDVIPM4Channel::~AMDVIPM4Channel() 000000000052ebc0 __float128 0f SECT 0a 0000 [__DATA.__common] AMDVISAMUEngine::gMetaClass 00000000003bcb18 __float128 0f SECT 08 0000 [.const_data] AMDVISAMUEngine::superClass 0000000000092464 __float128 0f SECT 01 0000 [.text] AMDVISAMUEngine::allocateHWRings() 00000000000924ea __float128 0f SECT 01 0000 [.text] AMDVISAMUEngine::allocateHWChannels() 0000000000092560 __float128 0f SECT 01 0000 [.text] AMDVISAMUEngine::readIndirectSPUReg(unsigned int) 0000000000092668 __float128 0f SECT 01 0000 [.text] AMDVISAMUEngine::dumpEngineHangState(bool) 00000000000925a0 __float128 0f SECT 01 0000 [.text] AMDVISAMUEngine::writeIndirectSPUReg(unsigned int, unsigned int) 00000000000925e4 __float128 0f SECT 01 0000 [.text] AMDVISAMUEngine::readIndirectSAMUSABReg(unsigned int) 0000000000092624 __float128 0f SECT 01 0000 [.text] AMDVISAMUEngine::writeIndirectSAMUSABReg(unsigned int, unsigned int) 0000000000092452 __float128 0f SECT 01 0000 [.text] AMDVISAMUEngine::init(AMDRadeonX4000_IAMDHWInterface*, _eAMD_HW_ENGINE_TYPE) 00000000000922c0 __float128 0f SECT 01 0000 [.text] AMDVISAMUEngine::MetaClass::MetaClass() 0000000000092380 __float128 0f SECT 01 0000 [.text] AMDVISAMUEngine::MetaClass::MetaClass() 00000000003bcb10 __float128 0f SECT 08 0000 [.const_data] AMDVISAMUEngine::metaClass 000000000009231c __float128 0f SECT 01 0000 [.text] AMDVISAMUEngine::AMDVISAMUEngine(OSMetaClass const*) 00000000000923f2 __float128 0f SECT 01 0000 [.text] AMDVISAMUEngine::AMDVISAMUEngine() 00000000000922fc __float128 0f SECT 01 0000 [.text] AMDVISAMUEngine::AMDVISAMUEngine(OSMetaClass const*) 0000000000092422 __float128 0f SECT 01 0000 [.text] AMDVISAMUEngine::AMDVISAMUEngine() 0000000000092350 __float128 0f SECT 01 0000 [.text] AMDVISAMUEngine::~AMDVISAMUEngine() 0000000000092346 __float128 0f SECT 01 0000 [.text] AMDVISAMUEngine::~AMDVISAMUEngine() 000000000009233c __float128 0f SECT 01 0000 [.text] AMDVISAMUEngine::~AMDVISAMUEngine() 000000000052ea80 __float128 0f SECT 0a 0000 [__DATA.__common] AMDVIsDMAEngine::gMetaClass 00000000003bb028 __float128 0f SECT 08 0000 [.const_data] AMDVIsDMAEngine::superClass 000000000008c8b6 __float128 0f SECT 01 0000 [.text] AMDVIsDMAEngine::allocateHWRings() 000000000008c8f2 __float128 0f SECT 01 0000 [.text] AMDVIsDMAEngine::allocateHWChannels() 000000000008cd7a __float128 0f SECT 01 0000 [.text] AMDVIsDMAEngine::dumpEngineHangState(bool) 000000000008c7f2 __float128 0f SECT 01 0000 [.text] AMDVIsDMAEngine::init(AMDRadeonX4000_IAMDHWInterface*, _eAMD_HW_ENGINE_TYPE) 000000000008cc10 __float128 0f SECT 01 0000 [.text] AMDVIsDMAEngine::stop() 000000000008c93e __float128 0f SECT 01 0000 [.text] AMDVIsDMAEngine::start() 000000000008c838 __float128 0f SECT 01 0000 [.text] AMDVIsDMAEngine::isIdle() 000000000008c660 __float128 0f SECT 01 0000 [.text] AMDVIsDMAEngine::MetaClass::MetaClass() 000000000008c720 __float128 0f SECT 01 0000 [.text] AMDVIsDMAEngine::MetaClass::MetaClass() 00000000003bb020 __float128 0f SECT 08 0000 [.const_data] AMDVIsDMAEngine::metaClass 000000000008c6bc __float128 0f SECT 01 0000 [.text] AMDVIsDMAEngine::AMDVIsDMAEngine(OSMetaClass const*) 000000000008c792 __float128 0f SECT 01 0000 [.text] AMDVIsDMAEngine::AMDVIsDMAEngine() 000000000008c69c __float128 0f SECT 01 0000 [.text] AMDVIsDMAEngine::AMDVIsDMAEngine(OSMetaClass const*) 000000000008c7c2 __float128 0f SECT 01 0000 [.text] AMDVIsDMAEngine::AMDVIsDMAEngine() 000000000008c6f0 __float128 0f SECT 01 0000 [.text] AMDVIsDMAEngine::~AMDVIsDMAEngine() 000000000008c6e6 __float128 0f SECT 01 0000 [.text] AMDVIsDMAEngine::~AMDVIsDMAEngine() 000000000008c6dc __float128 0f SECT 01 0000 [.text] AMDVIsDMAEngine::~AMDVIsDMAEngine() 00000000000a7446 __float128 0f SECT 01 0000 [.text] ShaderVidMemMgr::CpuLoadSingleShader(BltShader*) 00000000000a7510 __float128 0f SECT 01 0000 [.text] ShaderVidMemMgr::AllocVidMemForShaders(_UBM_ALLOCVIDMEM_OUTPUT*, unsigned int, unsigned int, _UBM_ALLOCVIDMEM_INPUT*) 00000000000a7324 __float128 0f SECT 01 0000 [.text] ShaderVidMemMgr::ShaderVidMemMgr(BltMgr*) 00000000000a742a __float128 0f SECT 01 0000 [.text] ShaderVidMemMgr::~ShaderVidMemMgr() 00000000000a73ea __float128 0f SECT 01 0000 [.text] ShaderVidMemMgr::~ShaderVidMemMgr() 00000000000a73aa __float128 0f SECT 01 0000 [.text] ShaderVidMemMgr::~ShaderVidMemMgr() 00000000000aa82c __float128 0f SECT 01 0000 [.text] SiBltAuxSurfMgr::HwlInitHiSSurf(_UBM_SURFINFO const*, CachedAuxSurf*) 00000000000aa0dc __float128 0f SECT 01 0000 [.text] SiBltAuxSurfMgr::HwlInitGradSurf(_UBM_SURFINFO const*, CachedAuxSurf*) 00000000000aaac0 __float128 0f SECT 01 0000 [.text] SiBltAuxSurfMgr::GetCmaskAsTexSize(_UBM_SURFINFO const*, unsigned int*, unsigned int*) 00000000000a9ea2 __float128 0f SECT 01 0000 [.text] SiBltAuxSurfMgr::HwlInitPixPreSurf(_UBM_SURFINFO const*, CachedAuxSurf*) 00000000000a84be __float128 0f SECT 01 0000 [.text] SiBltAuxSurfMgr::SetupOffsetTexData(_UBM_SURFINFO const*, unsigned int, CachedAuxSurf*) 00000000000a7f36 __float128 0f SECT 01 0000 [.text] SiBltAuxSurfMgr::UseHtileLinearMode(_UBM_SURFINFO const*) 00000000000a7f66 __float128 0f SECT 01 0000 [.text] SiBltAuxSurfMgr::GetHtileActualWidth(_ADDR_COMPUTE_HTILE_INFO_OUTPUT*) 00000000000a7f88 __float128 0f SECT 01 0000 [.text] SiBltAuxSurfMgr::GetHtileSizeInBytes(_ADDR_COMPUTE_HTILE_INFO_OUTPUT*) 00000000000a9c7a __float128 0f SECT 01 0000 [.text] SiBltAuxSurfMgr::HwlInitEdgeMaskSurf(_UBM_SURFINFO const*, CachedAuxSurf*) 00000000000a7f72 __float128 0f SECT 01 0000 [.text] SiBltAuxSurfMgr::GetHtileActualHeight(_ADDR_COMPUTE_HTILE_INFO_OUTPUT*) 00000000000a7f9c __float128 0f SECT 01 0000 [.text] SiBltAuxSurfMgr::HwlInitOffsetTexSurf(_UBM_SURFINFO const*, CachedAuxSurf*) 00000000000aa2ce __float128 0f SECT 01 0000 [.text] SiBltAuxSurfMgr::HwlInitAdvAaDepthSurf(_UBM_SURFINFO const*, CachedAuxSurf*) 00000000000a8ede __float128 0f SECT 01 0000 [.text] SiBltAuxSurfMgr::HwlInitCmaskAsTexSurf(_UBM_SURFINFO const*, CachedAuxSurf*) 00000000000a9086 __float128 0f SECT 01 0000 [.text] SiBltAuxSurfMgr::HwlInitFmaskAsTexSurf(_UBM_SURFINFO const*, CachedAuxSurf*) 00000000000a92b2 __float128 0f SECT 01 0000 [.text] SiBltAuxSurfMgr::HwlGenerateFmaskTexKey(_UBM_SURFINFO const*) 00000000000a978e __float128 0f SECT 01 0000 [.text] SiBltAuxSurfMgr::HwlInitHTileOffsetSurf(_UBM_SURFINFO const*, _UBM_SURFINFO const*, CachedAuxSurf*) 00000000000a9566 __float128 0f SECT 01 0000 [.text] SiBltAuxSurfMgr::HwlInitMlaaSepEdgeSurf(_UBM_SURFINFO const*, CachedAuxSurf*) 00000000000a8c20 __float128 0f SECT 01 0000 [.text] SiBltAuxSurfMgr::HwlDestroyOffsetTexSurf(CachedAuxSurf*) 00000000000aac54 __float128 0f SECT 01 0000 [.text] SiBltAuxSurfMgr::HwlGenerateOffsetTexKey(_UBM_SURFINFO const*) 00000000000a8c56 __float128 0f SECT 01 0000 [.text] SiBltAuxSurfMgr::HwlInitHtileAsColorSurf(_UBM_SURFINFO const*, CachedAuxSurf*) 00000000000aa5fa __float128 0f SECT 01 0000 [.text] SiBltAuxSurfMgr::HwlInitNeighborMaskSurf(_UBM_SURFINFO const*, CachedAuxSurf*) 00000000000a92f0 __float128 0f SECT 01 0000 [.text] SiBltAuxSurfMgr::HwlInitMlaaEdgeCountSurf(_UBM_SURFINFO const*, CachedAuxSurf*, MlaaEdgeCountSurfDesc) 00000000000a82a6 __float128 0f SECT 01 0000 [.text] SiBltAuxSurfMgr::DepthWidthHeightFromColor(_UBM_SURFINFO const*, unsigned int*, unsigned int*, int*) 00000000000a9c44 __float128 0f SECT 01 0000 [.text] SiBltAuxSurfMgr::HwlDestroyHTileOffsetSurf(CachedAuxSurf*) 00000000000a7ecc __float128 0f SECT 01 0000 [.text] SiBltAuxSurfMgr::Create(SiBltMgr*) 00000000000a7f24 __float128 0f SECT 01 0000 [.text] SiBltAuxSurfMgr::Destroy() 00000000000a7f1c __float128 0f SECT 01 0000 [.text] SiBltAuxSurfMgr::HwlInit() 00000000000a7eac __float128 0f SECT 01 0000 [.text] SiBltAuxSurfMgr::SiBltAuxSurfMgr() 00000000000a7e8c __float128 0f SECT 01 0000 [.text] SiBltAuxSurfMgr::SiBltAuxSurfMgr() 00000000000cbae6 __float128 0f SECT 01 0000 [.text] SiSurfAttribute::GetPipeNum(PipeConfig) 00000000000cb18c __float128 0f SECT 01 0000 [.text] SiSurfAttribute::CreateObject() 00000000000cb414 __float128 0f SECT 01 0000 [.text] SiSurfAttribute::Init(_UBM_CREATEINFO const*) 00000000000cb1f0 __float128 0f SECT 01 0000 [.text] SiSurfAttribute::SiSurfAttribute() 00000000000cb2a8 __float128 0f SECT 01 0000 [.text] SiSurfAttribute::SiSurfAttribute() 00000000000cb3f8 __float128 0f SECT 01 0000 [.text] SiSurfAttribute::~SiSurfAttribute() 00000000000cb37a __float128 0f SECT 01 0000 [.text] SiSurfAttribute::~SiSurfAttribute() 00000000000cb2fc __float128 0f SECT 01 0000 [.text] SiSurfAttribute::~SiSurfAttribute() 000000000052e8c8 __float128 0f SECT 0a 0000 [__DATA.__common] AMDCIComputeRing::gMetaClass 00000000003b8398 __float128 0f SECT 08 0000 [.const_data] AMDCIComputeRing::superClass 0000000000082f68 __float128 0f SECT 01 0000 [.text] AMDCIComputeRing::registerLocation() 0000000000082f28 __float128 0f SECT 01 0000 [.text] AMDCIComputeRing::allocateResources() 0000000000082f70 __float128 0f SECT 01 0000 [.text] AMDCIComputeRing::enableReadPointerWriteBack() 0000000000082f76 __float128 0f SECT 01 0000 [.text] AMDCIComputeRing::disableReadPointerWriteBack() 0000000000082f90 __float128 0f SECT 01 0000 [.text] AMDCIComputeRing::programReadAndWritePointers(unsigned int) 0000000000082e82 __float128 0f SECT 01 0000 [.text] AMDCIComputeRing::init(AMDRadeonX4000_IAMDHWInterface*, int, _eAMD_HW_ENGINE_TYPE, unsigned int, void const*) 00000000000830c4 __float128 0f SECT 01 0000 [.text] AMDCIComputeRing::align() 0000000000082f7c __float128 0f SECT 01 0000 [.text] AMDCIComputeRing::reset() 0000000000082cf0 __float128 0f SECT 01 0000 [.text] AMDCIComputeRing::MetaClass::MetaClass() 0000000000082db0 __float128 0f SECT 01 0000 [.text] AMDCIComputeRing::MetaClass::MetaClass() 00000000003b8390 __float128 0f SECT 08 0000 [.const_data] AMDCIComputeRing::metaClass 00000000000830f4 __float128 0f SECT 01 0000 [.text] AMDCIComputeRing::writeTail() 0000000000082d4c __float128 0f SECT 01 0000 [.text] AMDCIComputeRing::AMDCIComputeRing(OSMetaClass const*) 0000000000082e22 __float128 0f SECT 01 0000 [.text] AMDCIComputeRing::AMDCIComputeRing() 0000000000082d2c __float128 0f SECT 01 0000 [.text] AMDCIComputeRing::AMDCIComputeRing(OSMetaClass const*) 0000000000082e52 __float128 0f SECT 01 0000 [.text] AMDCIComputeRing::AMDCIComputeRing() 0000000000082d80 __float128 0f SECT 01 0000 [.text] AMDCIComputeRing::~AMDCIComputeRing() 0000000000082d76 __float128 0f SECT 01 0000 [.text] AMDCIComputeRing::~AMDCIComputeRing() 0000000000082d6c __float128 0f SECT 01 0000 [.text] AMDCIComputeRing::~AMDCIComputeRing() 000000000052e698 __float128 0f SECT 0a 0000 [__DATA.__common] AMDCIHWUtilities::gMetaClass 00000000003b5168 __float128 0f SECT 08 0000 [.const_data] AMDCIHWUtilities::superClass 000000000007cfd2 __float128 0f SECT 01 0000 [.text] AMDCIHWUtilities::setupUBMChipInfo(_UBM_CHIPINFO*) 000000000007d06e __float128 0f SECT 01 0000 [.text] AMDCIHWUtilities::filterUBMFormatForOCL(_UBM_FORMAT) 000000000007ce40 __float128 0f SECT 01 0000 [.text] AMDCIHWUtilities::MetaClass::MetaClass() 000000000007cf00 __float128 0f SECT 01 0000 [.text] AMDCIHWUtilities::MetaClass::MetaClass() 00000000003b5160 __float128 0f SECT 08 0000 [.const_data] AMDCIHWUtilities::metaClass 000000000007ce9c __float128 0f SECT 01 0000 [.text] AMDCIHWUtilities::AMDCIHWUtilities(OSMetaClass const*) 000000000007cf72 __float128 0f SECT 01 0000 [.text] AMDCIHWUtilities::AMDCIHWUtilities() 000000000007ce7c __float128 0f SECT 01 0000 [.text] AMDCIHWUtilities::AMDCIHWUtilities(OSMetaClass const*) 000000000007cfa2 __float128 0f SECT 01 0000 [.text] AMDCIHWUtilities::AMDCIHWUtilities() 000000000007ced0 __float128 0f SECT 01 0000 [.text] AMDCIHWUtilities::~AMDCIHWUtilities() 000000000007cec6 __float128 0f SECT 01 0000 [.text] AMDCIHWUtilities::~AMDCIHWUtilities() 000000000007cebc __float128 0f SECT 01 0000 [.text] AMDCIHWUtilities::~AMDCIHWUtilities() 000000000052e738 __float128 0f SECT 0a 0000 [__DATA.__common] AMDCISAMURBIRing::gMetaClass 00000000003b5fb8 __float128 0f SECT 08 0000 [.const_data] AMDCISAMURBIRing::superClass 000000000007fd6e __float128 0f SECT 01 0000 [.text] AMDCISAMURBIRing::commitBlock(unsigned int) 000000000007fc0c __float128 0f SECT 01 0000 [.text] AMDCISAMURBIRing::getFreeSpace() 000000000007fd88 __float128 0f SECT 01 0000 [.text] AMDCISAMURBIRing::getReadPointer() 000000000007fda8 __float128 0f SECT 01 0000 [.text] AMDCISAMURBIRing::getWritePointer() 000000000007fc44 __float128 0f SECT 01 0000 [.text] AMDCISAMURBIRing::registerLocation() 000000000007fc68 __float128 0f SECT 01 0000 [.text] AMDCISAMURBIRing::enableReadPointerWriteBack() 000000000007fc6e __float128 0f SECT 01 0000 [.text] AMDCISAMURBIRing::disableReadPointerWriteBack() 000000000007fccc __float128 0f SECT 01 0000 [.text] AMDCISAMURBIRing::programReadAndWritePointers(unsigned int) 000000000007fbb2 __float128 0f SECT 01 0000 [.text] AMDCISAMURBIRing::free() 000000000007fb12 __float128 0f SECT 01 0000 [.text] AMDCISAMURBIRing::init(AMDRadeonX4000_IAMDHWInterface*, int, _eAMD_HW_ENGINE_TYPE, unsigned int, void const*) 000000000007fd82 __float128 0f SECT 01 0000 [.text] AMDCISAMURBIRing::align() 000000000007fc74 __float128 0f SECT 01 0000 [.text] AMDCISAMURBIRing::reset() 000000000007fd4e __float128 0f SECT 01 0000 [.text] AMDCISAMURBIRing::write(unsigned int) 000000000007fbee __float128 0f SECT 01 0000 [.text] AMDCISAMURBIRing::getHead() 000000000007fbfc __float128 0f SECT 01 0000 [.text] AMDCISAMURBIRing::getTail() 000000000007f980 __float128 0f SECT 01 0000 [.text] AMDCISAMURBIRing::MetaClass::MetaClass() 000000000007fa40 __float128 0f SECT 01 0000 [.text] AMDCISAMURBIRing::MetaClass::MetaClass() 00000000003b5fb0 __float128 0f SECT 08 0000 [.const_data] AMDCISAMURBIRing::metaClass 000000000007fdc8 __float128 0f SECT 01 0000 [.text] AMDCISAMURBIRing::writeTail() 000000000007f9dc __float128 0f SECT 01 0000 [.text] AMDCISAMURBIRing::AMDCISAMURBIRing(OSMetaClass const*) 000000000007fab2 __float128 0f SECT 01 0000 [.text] AMDCISAMURBIRing::AMDCISAMURBIRing() 000000000007f9bc __float128 0f SECT 01 0000 [.text] AMDCISAMURBIRing::AMDCISAMURBIRing(OSMetaClass const*) 000000000007fae2 __float128 0f SECT 01 0000 [.text] AMDCISAMURBIRing::AMDCISAMURBIRing() 000000000007fa10 __float128 0f SECT 01 0000 [.text] AMDCISAMURBIRing::~AMDCISAMURBIRing() 000000000007fa06 __float128 0f SECT 01 0000 [.text] AMDCISAMURBIRing::~AMDCISAMURBIRing() 000000000007f9fc __float128 0f SECT 01 0000 [.text] AMDCISAMURBIRing::~AMDCISAMURBIRing() 000000000052e7d8 __float128 0f SECT 0a 0000 [__DATA.__common] AMDCIUVDHWEngine::gMetaClass 0000000000081136 __float128 0f SECT 01 0000 [.text] AMDCIUVDHWEngine::getUVDDclk() 0000000000081108 __float128 0f SECT 01 0000 [.text] AMDCIUVDHWEngine::getUVDVclk() 00000000003b6d68 __float128 0f SECT 08 0000 [.const_data] AMDCIUVDHWEngine::superClass 0000000000081100 __float128 0f SECT 01 0000 [.text] AMDCIUVDHWEngine::setVclkDclk(unsigned int, unsigned int) 000000000008105e __float128 0f SECT 01 0000 [.text] AMDCIUVDHWEngine::initHardware() 0000000000081164 __float128 0f SECT 01 0000 [.text] AMDCIUVDHWEngine::queryClockInfo(unsigned int*, unsigned int*, unsigned int*) 000000000008123c __float128 0f SECT 01 0000 [.text] AMDCIUVDHWEngine::getActualDivider(unsigned int) 0000000000081002 __float128 0f SECT 01 0000 [.text] AMDCIUVDHWEngine::init(AMDRadeonX4000_IAMDHWInterface*, _eAMD_HW_ENGINE_TYPE) 0000000000080e70 __float128 0f SECT 01 0000 [.text] AMDCIUVDHWEngine::MetaClass::MetaClass() 0000000000080f30 __float128 0f SECT 01 0000 [.text] AMDCIUVDHWEngine::MetaClass::MetaClass() 00000000003b6d60 __float128 0f SECT 08 0000 [.const_data] AMDCIUVDHWEngine::metaClass 0000000000080ecc __float128 0f SECT 01 0000 [.text] AMDCIUVDHWEngine::AMDCIUVDHWEngine(OSMetaClass const*) 0000000000080fa2 __float128 0f SECT 01 0000 [.text] AMDCIUVDHWEngine::AMDCIUVDHWEngine() 0000000000080eac __float128 0f SECT 01 0000 [.text] AMDCIUVDHWEngine::AMDCIUVDHWEngine(OSMetaClass const*) 0000000000080fd2 __float128 0f SECT 01 0000 [.text] AMDCIUVDHWEngine::AMDCIUVDHWEngine() 0000000000080f00 __float128 0f SECT 01 0000 [.text] AMDCIUVDHWEngine::~AMDCIUVDHWEngine() 0000000000080ef6 __float128 0f SECT 01 0000 [.text] AMDCIUVDHWEngine::~AMDCIUVDHWEngine() 0000000000080eec __float128 0f SECT 01 0000 [.text] AMDCIUVDHWEngine::~AMDCIUVDHWEngine() 000000000052e800 __float128 0f SECT 0a 0000 [__DATA.__common] AMDCIVCEHWEngine::gMetaClass 0000000000081988 __float128 0f SECT 01 0000 [.text] AMDCIVCEHWEngine::getVCECClk() 00000000003b71f8 __float128 0f SECT 08 0000 [.const_data] AMDCIVCEHWEngine::superClass 00000000000815ce __float128 0f SECT 01 0000 [.text] AMDCIVCEHWEngine::initHardware() 0000000000081980 __float128 0f SECT 01 0000 [.text] AMDCIVCEHWEngine::setEVClkECClk(unsigned int, unsigned int) 00000000000819b6 __float128 0f SECT 01 0000 [.text] AMDCIVCEHWEngine::queryClockInfo(unsigned int*, unsigned int*, unsigned int*) 000000000008179a __float128 0f SECT 01 0000 [.text] AMDCIVCEHWEngine::allocateHWRings() 000000000008163a __float128 0f SECT 01 0000 [.text] AMDCIVCEHWEngine::releaseHardware() 0000000000081a54 __float128 0f SECT 01 0000 [.text] AMDCIVCEHWEngine::getActualDivider(unsigned int) 0000000000081704 __float128 0f SECT 01 0000 [.text] AMDCIVCEHWEngine::initHardwareRings() 0000000000081806 __float128 0f SECT 01 0000 [.text] AMDCIVCEHWEngine::allocateHWChannels() 0000000000081886 __float128 0f SECT 01 0000 [.text] AMDCIVCEHWEngine::configCacheWindows() 0000000000081a86 __float128 0f SECT 01 0000 [.text] AMDCIVCEHWEngine::dumpEngineHangState(bool) 0000000000081770 __float128 0f SECT 01 0000 [.text] AMDCIVCEHWEngine::releaseHardwareRings() 00000000000815bc __float128 0f SECT 01 0000 [.text] AMDCIVCEHWEngine::free() 0000000000081532 __float128 0f SECT 01 0000 [.text] AMDCIVCEHWEngine::init(AMDRadeonX4000_IAMDHWInterface*, _eAMD_HW_ENGINE_TYPE) 000000000008157e __float128 0f SECT 01 0000 [.text] AMDCIVCEHWEngine::isIdle() 00000000000813a0 __float128 0f SECT 01 0000 [.text] AMDCIVCEHWEngine::MetaClass::MetaClass() 0000000000081460 __float128 0f SECT 01 0000 [.text] AMDCIVCEHWEngine::MetaClass::MetaClass() 00000000003b71f0 __float128 0f SECT 08 0000 [.const_data] AMDCIVCEHWEngine::metaClass 00000000000813fc __float128 0f SECT 01 0000 [.text] AMDCIVCEHWEngine::AMDCIVCEHWEngine(OSMetaClass const*) 00000000000814d2 __float128 0f SECT 01 0000 [.text] AMDCIVCEHWEngine::AMDCIVCEHWEngine() 00000000000813dc __float128 0f SECT 01 0000 [.text] AMDCIVCEHWEngine::AMDCIVCEHWEngine(OSMetaClass const*) 0000000000081502 __float128 0f SECT 01 0000 [.text] AMDCIVCEHWEngine::AMDCIVCEHWEngine() 0000000000081430 __float128 0f SECT 01 0000 [.text] AMDCIVCEHWEngine::~AMDCIVCEHWEngine() 0000000000081426 __float128 0f SECT 01 0000 [.text] AMDCIVCEHWEngine::~AMDCIVCEHWEngine() 000000000008141c __float128 0f SECT 01 0000 [.text] AMDCIVCEHWEngine::~AMDCIVCEHWEngine() 000000000052e4b8 __float128 0f SECT 0a 0000 [__DATA.__common] AMDSIComputeRing::gMetaClass 00000000003b1d08 __float128 0f SECT 08 0000 [.const_data] AMDSIComputeRing::superClass 0000000000073b06 __float128 0f SECT 01 0000 [.text] AMDSIComputeRing::getCpRbCntlValue() 0000000000073b18 __float128 0f SECT 01 0000 [.text] AMDSIComputeRing::registerLocation() 0000000000073c3a __float128 0f SECT 01 0000 [.text] AMDSIComputeRing::enableReadPointerWriteBack() 0000000000073cb2 __float128 0f SECT 01 0000 [.text] AMDSIComputeRing::disableReadPointerWriteBack() 0000000000073d46 __float128 0f SECT 01 0000 [.text] AMDSIComputeRing::programReadAndWritePointers(unsigned int) 00000000000739e2 __float128 0f SECT 01 0000 [.text] AMDSIComputeRing::init(AMDRadeonX4000_IAMDHWInterface*, int, _eAMD_HW_ENGINE_TYPE, unsigned int, void const*) 0000000000073dde __float128 0f SECT 01 0000 [.text] AMDSIComputeRing::align() 0000000000073ce8 __float128 0f SECT 01 0000 [.text] AMDSIComputeRing::reset() 0000000000073850 __float128 0f SECT 01 0000 [.text] AMDSIComputeRing::MetaClass::MetaClass() 0000000000073910 __float128 0f SECT 01 0000 [.text] AMDSIComputeRing::MetaClass::MetaClass() 00000000003b1d00 __float128 0f SECT 08 0000 [.const_data] AMDSIComputeRing::metaClass 00000000000738ac __float128 0f SECT 01 0000 [.text] AMDSIComputeRing::AMDSIComputeRing(OSMetaClass const*) 0000000000073982 __float128 0f SECT 01 0000 [.text] AMDSIComputeRing::AMDSIComputeRing() 000000000007388c __float128 0f SECT 01 0000 [.text] AMDSIComputeRing::AMDSIComputeRing(OSMetaClass const*) 00000000000739b2 __float128 0f SECT 01 0000 [.text] AMDSIComputeRing::AMDSIComputeRing() 00000000000738e0 __float128 0f SECT 01 0000 [.text] AMDSIComputeRing::~AMDSIComputeRing() 00000000000738d6 __float128 0f SECT 01 0000 [.text] AMDSIComputeRing::~AMDSIComputeRing() 00000000000738cc __float128 0f SECT 01 0000 [.text] AMDSIComputeRing::~AMDSIComputeRing() 000000000052e058 __float128 0f SECT 0a 0000 [__DATA.__common] AMDSIHWUtilities::gMetaClass 00000000003aae68 __float128 0f SECT 08 0000 [.const_data] AMDSIHWUtilities::superClass 0000000000065058 __float128 0f SECT 01 0000 [.text] AMDSIHWUtilities::getUBMEndian(unsigned int) 0000000000064fa0 __float128 0f SECT 01 0000 [.text] AMDSIHWUtilities::setupUBMChipInfo(_UBM_CHIPINFO*) 0000000000064ed2 __float128 0f SECT 01 0000 [.text] AMDSIHWUtilities::filterUBMFormatForOCL(_UBM_FORMAT) 0000000000064d40 __float128 0f SECT 01 0000 [.text] AMDSIHWUtilities::MetaClass::MetaClass() 0000000000064e00 __float128 0f SECT 01 0000 [.text] AMDSIHWUtilities::MetaClass::MetaClass() 00000000003aae60 __float128 0f SECT 08 0000 [.const_data] AMDSIHWUtilities::metaClass 0000000000064d9c __float128 0f SECT 01 0000 [.text] AMDSIHWUtilities::AMDSIHWUtilities(OSMetaClass const*) 0000000000064e72 __float128 0f SECT 01 0000 [.text] AMDSIHWUtilities::AMDSIHWUtilities() 0000000000064d7c __float128 0f SECT 01 0000 [.text] AMDSIHWUtilities::AMDSIHWUtilities(OSMetaClass const*) 0000000000064ea2 __float128 0f SECT 01 0000 [.text] AMDSIHWUtilities::AMDSIHWUtilities() 0000000000064dd0 __float128 0f SECT 01 0000 [.text] AMDSIHWUtilities::~AMDSIHWUtilities() 0000000000064dc6 __float128 0f SECT 01 0000 [.text] AMDSIHWUtilities::~AMDSIHWUtilities() 0000000000064dbc __float128 0f SECT 01 0000 [.text] AMDSIHWUtilities::~AMDSIHWUtilities() 000000000052e3f0 __float128 0f SECT 0a 0000 [__DATA.__common] AMDSIUVDHWEngine::gMetaClass 00000000003b0aa8 __float128 0f SECT 08 0000 [.const_data] AMDSIUVDHWEngine::superClass 000000000007170e __float128 0f SECT 01 0000 [.text] AMDSIUVDHWEngine::initHardware() 0000000000071842 __float128 0f SECT 01 0000 [.text] AMDSIUVDHWEngine::commitUVDFWMsg(_SML_UVD_MSG*, unsigned long long, unsigned long long) 000000000007166c __float128 0f SECT 01 0000 [.text] AMDSIUVDHWEngine::getFwvFunction() 00000000000715f4 __float128 0f SECT 01 0000 [.text] AMDSIUVDHWEngine::allocateHWRings() 00000000000717aa __float128 0f SECT 01 0000 [.text] AMDSIUVDHWEngine::releaseHardware() 0000000000071630 __float128 0f SECT 01 0000 [.text] AMDSIUVDHWEngine::allocateHWChannels() 0000000000071a36 __float128 0f SECT 01 0000 [.text] AMDSIUVDHWEngine::dumpEngineHangState(bool) 00000000000719ea __float128 0f SECT 01 0000 [.text] AMDSIUVDHWEngine::saveNONCACHE_SIZE1_val() 000000000007167a __float128 0f SECT 01 0000 [.text] AMDSIUVDHWEngine::startFirmwareValidation(void*, _IRI_CALL_INPUT*, _IRI_CALL_OUTPUT*) 0000000000071a12 __float128 0f SECT 01 0000 [.text] AMDSIUVDHWEngine::restoreNONCACHE_SIZE1_val() 0000000000071512 __float128 0f SECT 01 0000 [.text] AMDSIUVDHWEngine::init(AMDRadeonX4000_IAMDHWInterface*, _eAMD_HW_ENGINE_TYPE) 00000000000715ba __float128 0f SECT 01 0000 [.text] AMDSIUVDHWEngine::isIdle() 0000000000071380 __float128 0f SECT 01 0000 [.text] AMDSIUVDHWEngine::MetaClass::MetaClass() 0000000000071440 __float128 0f SECT 01 0000 [.text] AMDSIUVDHWEngine::MetaClass::MetaClass() 00000000003b0aa0 __float128 0f SECT 08 0000 [.const_data] AMDSIUVDHWEngine::metaClass 00000000000713dc __float128 0f SECT 01 0000 [.text] AMDSIUVDHWEngine::AMDSIUVDHWEngine(OSMetaClass const*) 00000000000714b2 __float128 0f SECT 01 0000 [.text] AMDSIUVDHWEngine::AMDSIUVDHWEngine() 00000000000713bc __float128 0f SECT 01 0000 [.text] AMDSIUVDHWEngine::AMDSIUVDHWEngine(OSMetaClass const*) 00000000000714e2 __float128 0f SECT 01 0000 [.text] AMDSIUVDHWEngine::AMDSIUVDHWEngine() 0000000000071410 __float128 0f SECT 01 0000 [.text] AMDSIUVDHWEngine::~AMDSIUVDHWEngine() 0000000000071406 __float128 0f SECT 01 0000 [.text] AMDSIUVDHWEngine::~AMDSIUVDHWEngine() 00000000000713fc __float128 0f SECT 01 0000 [.text] AMDSIUVDHWEngine::~AMDSIUVDHWEngine() 000000000052e300 __float128 0f SECT 0a 0000 [__DATA.__common] AMDSIVCEHWEngine::gMetaClass 00000000003af538 __float128 0f SECT 08 0000 [.const_data] AMDSIVCEHWEngine::superClass 000000000006f5ae __float128 0f SECT 01 0000 [.text] AMDSIVCEHWEngine::initHardware() 000000000006f77a __float128 0f SECT 01 0000 [.text] AMDSIVCEHWEngine::allocateHWRings() 000000000006f61a __float128 0f SECT 01 0000 [.text] AMDSIVCEHWEngine::releaseHardware() 000000000006f6e4 __float128 0f SECT 01 0000 [.text] AMDSIVCEHWEngine::initHardwareRings() 000000000006f7e6 __float128 0f SECT 01 0000 [.text] AMDSIVCEHWEngine::allocateHWChannels() 000000000006f866 __float128 0f SECT 01 0000 [.text] AMDSIVCEHWEngine::configCacheWindows() 000000000006fa54 __float128 0f SECT 01 0000 [.text] AMDSIVCEHWEngine::dumpEngineHangState(bool) 000000000006f750 __float128 0f SECT 01 0000 [.text] AMDSIVCEHWEngine::releaseHardwareRings() 000000000006f59c __float128 0f SECT 01 0000 [.text] AMDSIVCEHWEngine::free() 000000000006f512 __float128 0f SECT 01 0000 [.text] AMDSIVCEHWEngine::init(AMDRadeonX4000_IAMDHWInterface*, _eAMD_HW_ENGINE_TYPE) 000000000006f55e __float128 0f SECT 01 0000 [.text] AMDSIVCEHWEngine::isIdle() 000000000006f380 __float128 0f SECT 01 0000 [.text] AMDSIVCEHWEngine::MetaClass::MetaClass() 000000000006f440 __float128 0f SECT 01 0000 [.text] AMDSIVCEHWEngine::MetaClass::MetaClass() 00000000003af530 __float128 0f SECT 08 0000 [.const_data] AMDSIVCEHWEngine::metaClass 000000000006f3dc __float128 0f SECT 01 0000 [.text] AMDSIVCEHWEngine::AMDSIVCEHWEngine(OSMetaClass const*) 000000000006f4b2 __float128 0f SECT 01 0000 [.text] AMDSIVCEHWEngine::AMDSIVCEHWEngine() 000000000006f3bc __float128 0f SECT 01 0000 [.text] AMDSIVCEHWEngine::AMDSIVCEHWEngine(OSMetaClass const*) 000000000006f4e2 __float128 0f SECT 01 0000 [.text] AMDSIVCEHWEngine::AMDSIVCEHWEngine() 000000000006f410 __float128 0f SECT 01 0000 [.text] AMDSIVCEHWEngine::~AMDSIVCEHWEngine() 000000000006f406 __float128 0f SECT 01 0000 [.text] AMDSIVCEHWEngine::~AMDSIVCEHWEngine() 000000000006f3fc __float128 0f SECT 01 0000 [.text] AMDSIVCEHWEngine::~AMDSIVCEHWEngine() 000000000052e940 __float128 0f SECT 0a 0000 [__DATA.__common] AMDTongaHardware::gMetaClass 00000000003b91d8 __float128 0f SECT 08 0000 [.const_data] AMDTongaHardware::superClass 0000000000086d48 __float128 0f SECT 01 0000 [.text] AMDTongaHardware::getATIChipConfigBit() 0000000000086d24 __float128 0f SECT 01 0000 [.text] AMDTongaHardware::readChipRevFromRegister() 0000000000086e14 __float128 0f SECT 01 0000 [.text] AMDTongaHardware::setupAndInitializeHWCapabilities() 0000000000086d12 __float128 0f SECT 01 0000 [.text] AMDTongaHardware::init(IOPCIDevice*, AMDRadeonX4000_IAMDHWHandler*, unsigned int&, unsigned int, _GART_PARAMETERS*, _FB_PARAMETERS*) 0000000000086d54 __float128 0f SECT 01 0000 [.text] AMDTongaHardware::powerUp() 0000000000086b80 __float128 0f SECT 01 0000 [.text] AMDTongaHardware::MetaClass::MetaClass() 0000000000086c40 __float128 0f SECT 01 0000 [.text] AMDTongaHardware::MetaClass::MetaClass() 00000000003b91d0 __float128 0f SECT 08 0000 [.const_data] AMDTongaHardware::metaClass 0000000000086bdc __float128 0f SECT 01 0000 [.text] AMDTongaHardware::AMDTongaHardware(OSMetaClass const*) 0000000000086cb2 __float128 0f SECT 01 0000 [.text] AMDTongaHardware::AMDTongaHardware() 0000000000086bbc __float128 0f SECT 01 0000 [.text] AMDTongaHardware::AMDTongaHardware(OSMetaClass const*) 0000000000086ce2 __float128 0f SECT 01 0000 [.text] AMDTongaHardware::AMDTongaHardware() 0000000000086c10 __float128 0f SECT 01 0000 [.text] AMDTongaHardware::~AMDTongaHardware() 0000000000086c06 __float128 0f SECT 01 0000 [.text] AMDTongaHardware::~AMDTongaHardware() 0000000000086bfc __float128 0f SECT 01 0000 [.text] AMDTongaHardware::~AMDTongaHardware() 000000000052eaf8 __float128 0f SECT 0a 0000 [__DATA.__common] AMDVIComputeRing::gMetaClass 00000000003bb9a8 __float128 0f SECT 08 0000 [.const_data] AMDVIComputeRing::superClass 000000000008dbb8 __float128 0f SECT 01 0000 [.text] AMDVIComputeRing::registerLocation() 000000000008db78 __float128 0f SECT 01 0000 [.text] AMDVIComputeRing::allocateResources() 000000000008dbc0 __float128 0f SECT 01 0000 [.text] AMDVIComputeRing::enableReadPointerWriteBack() 000000000008dbc6 __float128 0f SECT 01 0000 [.text] AMDVIComputeRing::disableReadPointerWriteBack() 000000000008dbfe __float128 0f SECT 01 0000 [.text] AMDVIComputeRing::programReadAndWritePointers(unsigned int) 000000000008dad2 __float128 0f SECT 01 0000 [.text] AMDVIComputeRing::init(AMDRadeonX4000_IAMDHWInterface*, int, _eAMD_HW_ENGINE_TYPE, unsigned int, void const*) 000000000008dd32 __float128 0f SECT 01 0000 [.text] AMDVIComputeRing::align() 000000000008dbcc __float128 0f SECT 01 0000 [.text] AMDVIComputeRing::reset() 000000000008d940 __float128 0f SECT 01 0000 [.text] AMDVIComputeRing::MetaClass::MetaClass() 000000000008da00 __float128 0f SECT 01 0000 [.text] AMDVIComputeRing::MetaClass::MetaClass() 00000000003bb9a0 __float128 0f SECT 08 0000 [.const_data] AMDVIComputeRing::metaClass 000000000008dd62 __float128 0f SECT 01 0000 [.text] AMDVIComputeRing::writeTail() 000000000008d99c __float128 0f SECT 01 0000 [.text] AMDVIComputeRing::AMDVIComputeRing(OSMetaClass const*) 000000000008da72 __float128 0f SECT 01 0000 [.text] AMDVIComputeRing::AMDVIComputeRing() 000000000008d97c __float128 0f SECT 01 0000 [.text] AMDVIComputeRing::AMDVIComputeRing(OSMetaClass const*) 000000000008daa2 __float128 0f SECT 01 0000 [.text] AMDVIComputeRing::AMDVIComputeRing() 000000000008d9d0 __float128 0f SECT 01 0000 [.text] AMDVIComputeRing::~AMDVIComputeRing() 000000000008d9c6 __float128 0f SECT 01 0000 [.text] AMDVIComputeRing::~AMDVIComputeRing() 000000000008d9bc __float128 0f SECT 01 0000 [.text] AMDVIComputeRing::~AMDVIComputeRing() 000000000052ea30 __float128 0f SECT 0a 0000 [__DATA.__common] AMDVIHWUtilities::gMetaClass 00000000003ba9b8 __float128 0f SECT 08 0000 [.const_data] AMDVIHWUtilities::superClass 000000000008b65e __float128 0f SECT 01 0000 [.text] AMDVIHWUtilities::getUBMEndian(unsigned int) 000000000008b5c2 __float128 0f SECT 01 0000 [.text] AMDVIHWUtilities::setupUBMChipInfo(_UBM_CHIPINFO*) 000000000008b67c __float128 0f SECT 01 0000 [.text] AMDVIHWUtilities::filterUBMFormatForOCL(_UBM_FORMAT) 000000000008b430 __float128 0f SECT 01 0000 [.text] AMDVIHWUtilities::MetaClass::MetaClass() 000000000008b4f0 __float128 0f SECT 01 0000 [.text] AMDVIHWUtilities::MetaClass::MetaClass() 00000000003ba9b0 __float128 0f SECT 08 0000 [.const_data] AMDVIHWUtilities::metaClass 000000000008b48c __float128 0f SECT 01 0000 [.text] AMDVIHWUtilities::AMDVIHWUtilities(OSMetaClass const*) 000000000008b562 __float128 0f SECT 01 0000 [.text] AMDVIHWUtilities::AMDVIHWUtilities() 000000000008b46c __float128 0f SECT 01 0000 [.text] AMDVIHWUtilities::AMDVIHWUtilities(OSMetaClass const*) 000000000008b592 __float128 0f SECT 01 0000 [.text] AMDVIHWUtilities::AMDVIHWUtilities() 000000000008b4c0 __float128 0f SECT 01 0000 [.text] AMDVIHWUtilities::~AMDVIHWUtilities() 000000000008b4b6 __float128 0f SECT 01 0000 [.text] AMDVIHWUtilities::~AMDVIHWUtilities() 000000000008b4ac __float128 0f SECT 01 0000 [.text] AMDVIHWUtilities::~AMDVIHWUtilities() 000000000052ebe8 __float128 0f SECT 0a 0000 [__DATA.__common] AMDVISAMURBIRing::gMetaClass 00000000003bcee8 __float128 0f SECT 08 0000 [.const_data] AMDVISAMURBIRing::superClass 00000000000929f0 __float128 0f SECT 01 0000 [.text] AMDVISAMURBIRing::getReadPointer() 0000000000092a10 __float128 0f SECT 01 0000 [.text] AMDVISAMURBIRing::getWritePointer() 000000000009296e __float128 0f SECT 01 0000 [.text] AMDVISAMURBIRing::programReadAndWritePointers(unsigned int) 0000000000092904 __float128 0f SECT 01 0000 [.text] AMDVISAMURBIRing::free() 00000000000928f2 __float128 0f SECT 01 0000 [.text] AMDVISAMURBIRing::init(AMDRadeonX4000_IAMDHWInterface*, int, _eAMD_HW_ENGINE_TYPE, unsigned int, void const*) 0000000000092916 __float128 0f SECT 01 0000 [.text] AMDVISAMURBIRing::reset() 0000000000092760 __float128 0f SECT 01 0000 [.text] AMDVISAMURBIRing::MetaClass::MetaClass() 0000000000092820 __float128 0f SECT 01 0000 [.text] AMDVISAMURBIRing::MetaClass::MetaClass() 00000000003bcee0 __float128 0f SECT 08 0000 [.const_data] AMDVISAMURBIRing::metaClass 0000000000092a30 __float128 0f SECT 01 0000 [.text] AMDVISAMURBIRing::writeTail() 00000000000927bc __float128 0f SECT 01 0000 [.text] AMDVISAMURBIRing::AMDVISAMURBIRing(OSMetaClass const*) 0000000000092892 __float128 0f SECT 01 0000 [.text] AMDVISAMURBIRing::AMDVISAMURBIRing() 000000000009279c __float128 0f SECT 01 0000 [.text] AMDVISAMURBIRing::AMDVISAMURBIRing(OSMetaClass const*) 00000000000928c2 __float128 0f SECT 01 0000 [.text] AMDVISAMURBIRing::AMDVISAMURBIRing() 00000000000927f0 __float128 0f SECT 01 0000 [.text] AMDVISAMURBIRing::~AMDVISAMURBIRing() 00000000000927e6 __float128 0f SECT 01 0000 [.text] AMDVISAMURBIRing::~AMDVISAMURBIRing() 00000000000927dc __float128 0f SECT 01 0000 [.text] AMDVISAMURBIRing::~AMDVISAMURBIRing() 000000000052ea58 __float128 0f SECT 0a 0000 [__DATA.__common] AMDVIsDMAChannel::gMetaClass 00000000003bac28 __float128 0f SECT 08 0000 [.const_data] AMDVIsDMAChannel::superClass 000000000008c23e __float128 0f SECT 01 0000 [.text] AMDVIsDMAChannel::submitVMInvalidate(unsigned int, unsigned long long, unsigned int) 000000000008c46e __float128 0f SECT 01 0000 [.text] AMDVIsDMAChannel::initializeDmaPktInfo() 000000000008bd62 __float128 0f SECT 01 0000 [.text] AMDVIsDMAChannel::writeProfilingCommand(unsigned int*, unsigned long long, unsigned int, bool) 000000000008c0de __float128 0f SECT 01 0000 [.text] AMDVIsDMAChannel::writeSRBMWriteCommand(unsigned int*, unsigned int, unsigned int, unsigned int) 000000000008c44a __float128 0f SECT 01 0000 [.text] AMDVIsDMAChannel::timeStampInterruptType() 000000000008c026 __float128 0f SECT 01 0000 [.text] AMDVIsDMAChannel::writeCopyLinearCommand(unsigned int*, unsigned long long, unsigned long long, unsigned int) 000000000008c16e __float128 0f SECT 01 0000 [.text] AMDVIsDMAChannel::writePollRegMemCommand(unsigned int*, bool, unsigned long long, unsigned int, unsigned int, unsigned int, unsigned int, unsigned int) 000000000008be5e __float128 0f SECT 01 0000 [.text] AMDVIsDMAChannel::writeWriteLinearCommand(unsigned int*, unsigned long long, unsigned int, unsigned int*) 000000000008bf4a __float128 0f SECT 01 0000 [.text] AMDVIsDMAChannel::writeWritePTEPDECommand(unsigned int*, unsigned long long, unsigned int, unsigned long long, unsigned long long, unsigned long long) 000000000008bdb8 __float128 0f SECT 01 0000 [.text] AMDVIsDMAChannel::writeConstantFillCommand(unsigned int*, unsigned long long, unsigned int, unsigned int) 000000000008b9e6 __float128 0f SECT 01 0000 [.text] AMDVIsDMAChannel::commitIndirectCommandBuffer(AMD_SUBMIT_COMMAND_BUFFER_INFO*) 000000000008bbd2 __float128 0f SECT 01 0000 [.text] AMDVIsDMAChannel::initializeVMInvalidateFrame() 000000000008c40e __float128 0f SECT 01 0000 [.text] AMDVIsDMAChannel::releaseIndirectCommandBufferFrame() 000000000008c386 __float128 0f SECT 01 0000 [.text] AMDVIsDMAChannel::initializeIndirectCommandBufferFrame() 000000000008b99a __float128 0f SECT 01 0000 [.text] AMDVIsDMAChannel::free() 000000000008b942 __float128 0f SECT 01 0000 [.text] AMDVIsDMAChannel::init(int, AMDRadeonX4000_IAMDHWInterface*, AMDRadeonX4000_IAMDHWEngine*, AMDRadeonX4000_IAMDHWRing*, char const*) 000000000008b7b0 __float128 0f SECT 01 0000 [.text] AMDVIsDMAChannel::MetaClass::MetaClass() 000000000008b870 __float128 0f SECT 01 0000 [.text] AMDVIsDMAChannel::MetaClass::MetaClass() 00000000003bac20 __float128 0f SECT 08 0000 [.const_data] AMDVIsDMAChannel::metaClass 000000000008b80c __float128 0f SECT 01 0000 [.text] AMDVIsDMAChannel::AMDVIsDMAChannel(OSMetaClass const*) 000000000008b8e2 __float128 0f SECT 01 0000 [.text] AMDVIsDMAChannel::AMDVIsDMAChannel() 000000000008b7ec __float128 0f SECT 01 0000 [.text] AMDVIsDMAChannel::AMDVIsDMAChannel(OSMetaClass const*) 000000000008b912 __float128 0f SECT 01 0000 [.text] AMDVIsDMAChannel::AMDVIsDMAChannel() 000000000008b840 __float128 0f SECT 01 0000 [.text] AMDVIsDMAChannel::~AMDVIsDMAChannel() 000000000008b836 __float128 0f SECT 01 0000 [.text] AMDVIsDMAChannel::~AMDVIsDMAChannel() 000000000008b82c __float128 0f SECT 01 0000 [.text] AMDVIsDMAChannel::~AMDVIsDMAChannel() 000000000052e148 __float128 0f SECT 0a 0000 [__DATA.__common] AMDVerdeHardware::gMetaClass 00000000003acc48 __float128 0f SECT 08 0000 [.const_data] AMDVerdeHardware::superClass 000000000006a9b4 __float128 0f SECT 01 0000 [.text] AMDVerdeHardware::allocateSML() 000000000006aac4 __float128 0f SECT 01 0000 [.text] AMDVerdeHardware::allocatePM4Engine() 000000000006a9a8 __float128 0f SECT 01 0000 [.text] AMDVerdeHardware::getATIChipConfigBit() 000000000006a984 __float128 0f SECT 01 0000 [.text] AMDVerdeHardware::readChipRevFromRegister() 000000000006aa9a __float128 0f SECT 01 0000 [.text] AMDVerdeHardware::setupAndInitializeHWCapabilities() 000000000006a972 __float128 0f SECT 01 0000 [.text] AMDVerdeHardware::init(IOPCIDevice*, AMDRadeonX4000_IAMDHWHandler*, unsigned int&, unsigned int, _GART_PARAMETERS*, _FB_PARAMETERS*) 000000000006a9da __float128 0f SECT 01 0000 [.text] AMDVerdeHardware::powerUp() 000000000006a7e0 __float128 0f SECT 01 0000 [.text] AMDVerdeHardware::MetaClass::MetaClass() 000000000006a8a0 __float128 0f SECT 01 0000 [.text] AMDVerdeHardware::MetaClass::MetaClass() 00000000003acc40 __float128 0f SECT 08 0000 [.const_data] AMDVerdeHardware::metaClass 000000000006a83c __float128 0f SECT 01 0000 [.text] AMDVerdeHardware::AMDVerdeHardware(OSMetaClass const*) 000000000006a912 __float128 0f SECT 01 0000 [.text] AMDVerdeHardware::AMDVerdeHardware() 000000000006a81c __float128 0f SECT 01 0000 [.text] AMDVerdeHardware::AMDVerdeHardware(OSMetaClass const*) 000000000006a942 __float128 0f SECT 01 0000 [.text] AMDVerdeHardware::AMDVerdeHardware() 000000000006a870 __float128 0f SECT 01 0000 [.text] AMDVerdeHardware::~AMDVerdeHardware() 000000000006a866 __float128 0f SECT 01 0000 [.text] AMDVerdeHardware::~AMDVerdeHardware() 000000000006a85c __float128 0f SECT 01 0000 [.text] AMDVerdeHardware::~AMDVerdeHardware() 00000000000bb57c __float128 0f SECT 01 0000 [.text] SiBltPixelShader::SetShaderInput(SiBltPixelShaderInput const*) 00000000000bb680 __float128 0f SECT 01 0000 [.text] SiBltPixelShader::CpuLoad(void*, LARGE_INTEGER, unsigned char*) 00000000000bb7f6 __float128 0f SECT 01 0000 [.text] SiBltPixelShader::GpuLoad(BltDevice*, void*, LARGE_INTEGER) 000000000052e5a8 __float128 0f SECT 0a 0000 [__DATA.__common] AMDCICommandsRing::gMetaClass 00000000003b3d28 __float128 0f SECT 08 0000 [.const_data] AMDCICommandsRing::superClass 0000000000079902 __float128 0f SECT 01 0000 [.text] AMDCICommandsRing::registerLocation() 000000000007992a __float128 0f SECT 01 0000 [.text] AMDCICommandsRing::enableReadPointerWriteBack() 0000000000079930 __float128 0f SECT 01 0000 [.text] AMDCICommandsRing::disableReadPointerWriteBack() 0000000000079994 __float128 0f SECT 01 0000 [.text] AMDCICommandsRing::programReadAndWritePointers(unsigned int) 00000000000798f0 __float128 0f SECT 01 0000 [.text] AMDCICommandsRing::free() 0000000000079852 __float128 0f SECT 01 0000 [.text] AMDCICommandsRing::init(AMDRadeonX4000_IAMDHWInterface*, int, _eAMD_HW_ENGINE_TYPE, unsigned int, void const*) 0000000000079a1e __float128 0f SECT 01 0000 [.text] AMDCICommandsRing::align() 0000000000079936 __float128 0f SECT 01 0000 [.text] AMDCICommandsRing::reset() 00000000000796c0 __float128 0f SECT 01 0000 [.text] AMDCICommandsRing::MetaClass::MetaClass() 0000000000079780 __float128 0f SECT 01 0000 [.text] AMDCICommandsRing::MetaClass::MetaClass() 00000000003b3d20 __float128 0f SECT 08 0000 [.const_data] AMDCICommandsRing::metaClass 000000000007971c __float128 0f SECT 01 0000 [.text] AMDCICommandsRing::AMDCICommandsRing(OSMetaClass const*) 00000000000797f2 __float128 0f SECT 01 0000 [.text] AMDCICommandsRing::AMDCICommandsRing() 00000000000796fc __float128 0f SECT 01 0000 [.text] AMDCICommandsRing::AMDCICommandsRing(OSMetaClass const*) 0000000000079822 __float128 0f SECT 01 0000 [.text] AMDCICommandsRing::AMDCICommandsRing() 0000000000079750 __float128 0f SECT 01 0000 [.text] AMDCICommandsRing::~AMDCICommandsRing() 0000000000079746 __float128 0f SECT 01 0000 [.text] AMDCICommandsRing::~AMDCICommandsRing() 000000000007973c __float128 0f SECT 01 0000 [.text] AMDCICommandsRing::~AMDCICommandsRing() 000000000052e558 __float128 0f SECT 0a 0000 [__DATA.__common] AMDHawaiiHardware::gMetaClass 00000000003b3278 __float128 0f SECT 08 0000 [.const_data] AMDHawaiiHardware::superClass 0000000000077b80 __float128 0f SECT 01 0000 [.text] AMDHawaiiHardware::getATIChipConfigBit() 0000000000077b64 __float128 0f SECT 01 0000 [.text] AMDHawaiiHardware::readChipRevFromRegister() 0000000000077c4c __float128 0f SECT 01 0000 [.text] AMDHawaiiHardware::setupAndInitializeHWCapabilities() 0000000000077b52 __float128 0f SECT 01 0000 [.text] AMDHawaiiHardware::init(IOPCIDevice*, AMDRadeonX4000_IAMDHWHandler*, unsigned int&, unsigned int, _GART_PARAMETERS*, _FB_PARAMETERS*) 0000000000077b8c __float128 0f SECT 01 0000 [.text] AMDHawaiiHardware::powerUp() 00000000000779c0 __float128 0f SECT 01 0000 [.text] AMDHawaiiHardware::MetaClass::MetaClass() 0000000000077a80 __float128 0f SECT 01 0000 [.text] AMDHawaiiHardware::MetaClass::MetaClass() 00000000003b3270 __float128 0f SECT 08 0000 [.const_data] AMDHawaiiHardware::metaClass 0000000000077a1c __float128 0f SECT 01 0000 [.text] AMDHawaiiHardware::AMDHawaiiHardware(OSMetaClass const*) 0000000000077af2 __float128 0f SECT 01 0000 [.text] AMDHawaiiHardware::AMDHawaiiHardware() 00000000000779fc __float128 0f SECT 01 0000 [.text] AMDHawaiiHardware::AMDHawaiiHardware(OSMetaClass const*) 0000000000077b22 __float128 0f SECT 01 0000 [.text] AMDHawaiiHardware::AMDHawaiiHardware() 0000000000077a50 __float128 0f SECT 01 0000 [.text] AMDHawaiiHardware::~AMDHawaiiHardware() 0000000000077a46 __float128 0f SECT 01 0000 [.text] AMDHawaiiHardware::~AMDHawaiiHardware() 0000000000077a3c __float128 0f SECT 01 0000 [.text] AMDHawaiiHardware::~AMDHawaiiHardware() 000000000052e260 __float128 0f SECT 0a 0000 [__DATA.__common] AMDSICommandsRing::gMetaClass 00000000003ae7c8 __float128 0f SECT 08 0000 [.const_data] AMDSICommandsRing::superClass 000000000006d152 __float128 0f SECT 01 0000 [.text] AMDSICommandsRing::getCpRbCntlValue() 000000000006d164 __float128 0f SECT 01 0000 [.text] AMDSICommandsRing::registerLocation() 000000000006d26a __float128 0f SECT 01 0000 [.text] AMDSICommandsRing::enableReadPointerWriteBack() 000000000006d2dc __float128 0f SECT 01 0000 [.text] AMDSICommandsRing::disableReadPointerWriteBack() 000000000006d366 __float128 0f SECT 01 0000 [.text] AMDSICommandsRing::programReadAndWritePointers(unsigned int) 000000000006d140 __float128 0f SECT 01 0000 [.text] AMDSICommandsRing::free() 000000000006d0a2 __float128 0f SECT 01 0000 [.text] AMDSICommandsRing::init(AMDRadeonX4000_IAMDHWInterface*, int, _eAMD_HW_ENGINE_TYPE, unsigned int, void const*) 000000000006d3f0 __float128 0f SECT 01 0000 [.text] AMDSICommandsRing::align() 000000000006d308 __float128 0f SECT 01 0000 [.text] AMDSICommandsRing::reset() 000000000006cf10 __float128 0f SECT 01 0000 [.text] AMDSICommandsRing::MetaClass::MetaClass() 000000000006cfd0 __float128 0f SECT 01 0000 [.text] AMDSICommandsRing::MetaClass::MetaClass() 00000000003ae7c0 __float128 0f SECT 08 0000 [.const_data] AMDSICommandsRing::metaClass 000000000006cf6c __float128 0f SECT 01 0000 [.text] AMDSICommandsRing::AMDSICommandsRing(OSMetaClass const*) 000000000006d042 __float128 0f SECT 01 0000 [.text] AMDSICommandsRing::AMDSICommandsRing() 000000000006cf4c __float128 0f SECT 01 0000 [.text] AMDSICommandsRing::AMDSICommandsRing(OSMetaClass const*) 000000000006d072 __float128 0f SECT 01 0000 [.text] AMDSICommandsRing::AMDSICommandsRing() 000000000006cfa0 __float128 0f SECT 01 0000 [.text] AMDSICommandsRing::~AMDSICommandsRing() 000000000006cf96 __float128 0f SECT 01 0000 [.text] AMDSICommandsRing::~AMDSICommandsRing() 000000000006cf8c __float128 0f SECT 01 0000 [.text] AMDSICommandsRing::~AMDSICommandsRing() 000000000052d680 __float128 0f SECT 0a 0000 [__DATA.__common] AMDSIVideoContext::gMetaClass 00000000003981f8 __float128 0f SECT 08 0000 [.const_data] AMDSIVideoContext::superClass 000000000002ac30 __float128 0f SECT 01 0000 [.text] AMDSIVideoContext::MetaClass::MetaClass() 000000000002acf0 __float128 0f SECT 01 0000 [.text] AMDSIVideoContext::MetaClass::MetaClass() 00000000003981f0 __float128 0f SECT 08 0000 [.const_data] AMDSIVideoContext::metaClass 000000000002ac8c __float128 0f SECT 01 0000 [.text] AMDSIVideoContext::AMDSIVideoContext(OSMetaClass const*) 000000000002ad62 __float128 0f SECT 01 0000 [.text] AMDSIVideoContext::AMDSIVideoContext() 000000000002ac6c __float128 0f SECT 01 0000 [.text] AMDSIVideoContext::AMDSIVideoContext(OSMetaClass const*) 000000000002ad92 __float128 0f SECT 01 0000 [.text] AMDSIVideoContext::AMDSIVideoContext() 000000000002acc0 __float128 0f SECT 01 0000 [.text] AMDSIVideoContext::~AMDSIVideoContext() 000000000002acb6 __float128 0f SECT 01 0000 [.text] AMDSIVideoContext::~AMDSIVideoContext() 000000000002acac __float128 0f SECT 01 0000 [.text] AMDSIVideoContext::~AMDSIVideoContext() 000000000052e0f8 __float128 0f SECT 0a 0000 [__DATA.__common] AMDTahitiHardware::gMetaClass 00000000003abde8 __float128 0f SECT 08 0000 [.const_data] AMDTahitiHardware::superClass 0000000000069d90 __float128 0f SECT 01 0000 [.text] AMDTahitiHardware::allocateSML() 0000000000069ea0 __float128 0f SECT 01 0000 [.text] AMDTahitiHardware::allocatePM4Engine() 0000000000069d84 __float128 0f SECT 01 0000 [.text] AMDTahitiHardware::getATIChipConfigBit() 0000000000069d64 __float128 0f SECT 01 0000 [.text] AMDTahitiHardware::readChipRevFromRegister() 0000000000069e76 __float128 0f SECT 01 0000 [.text] AMDTahitiHardware::setupAndInitializeHWCapabilities() 0000000000069d52 __float128 0f SECT 01 0000 [.text] AMDTahitiHardware::init(IOPCIDevice*, AMDRadeonX4000_IAMDHWHandler*, unsigned int&, unsigned int, _GART_PARAMETERS*, _FB_PARAMETERS*) 0000000000069db6 __float128 0f SECT 01 0000 [.text] AMDTahitiHardware::powerUp() 0000000000069bc0 __float128 0f SECT 01 0000 [.text] AMDTahitiHardware::MetaClass::MetaClass() 0000000000069c80 __float128 0f SECT 01 0000 [.text] AMDTahitiHardware::MetaClass::MetaClass() 00000000003abde0 __float128 0f SECT 08 0000 [.const_data] AMDTahitiHardware::metaClass 0000000000069c1c __float128 0f SECT 01 0000 [.text] AMDTahitiHardware::AMDTahitiHardware(OSMetaClass const*) 0000000000069cf2 __float128 0f SECT 01 0000 [.text] AMDTahitiHardware::AMDTahitiHardware() 0000000000069bfc __float128 0f SECT 01 0000 [.text] AMDTahitiHardware::AMDTahitiHardware(OSMetaClass const*) 0000000000069d22 __float128 0f SECT 01 0000 [.text] AMDTahitiHardware::AMDTahitiHardware() 0000000000069c50 __float128 0f SECT 01 0000 [.text] AMDTahitiHardware::~AMDTahitiHardware() 0000000000069c46 __float128 0f SECT 01 0000 [.text] AMDTahitiHardware::~AMDTahitiHardware() 0000000000069c3c __float128 0f SECT 01 0000 [.text] AMDTahitiHardware::~AMDTahitiHardware() 000000000052ead0 __float128 0f SECT 0a 0000 [__DATA.__common] AMDVICommandsRing::gMetaClass 00000000003bb688 __float128 0f SECT 08 0000 [.const_data] AMDVICommandsRing::superClass 000000000008d6b2 __float128 0f SECT 01 0000 [.text] AMDVICommandsRing::registerLocation() 000000000008d6da __float128 0f SECT 01 0000 [.text] AMDVICommandsRing::enableReadPointerWriteBack() 000000000008d6e0 __float128 0f SECT 01 0000 [.text] AMDVICommandsRing::disableReadPointerWriteBack() 000000000008d744 __float128 0f SECT 01 0000 [.text] AMDVICommandsRing::programReadAndWritePointers(unsigned int) 000000000008d6a0 __float128 0f SECT 01 0000 [.text] AMDVICommandsRing::free() 000000000008d602 __float128 0f SECT 01 0000 [.text] AMDVICommandsRing::init(AMDRadeonX4000_IAMDHWInterface*, int, _eAMD_HW_ENGINE_TYPE, unsigned int, void const*) 000000000008d7ce __float128 0f SECT 01 0000 [.text] AMDVICommandsRing::align() 000000000008d6e6 __float128 0f SECT 01 0000 [.text] AMDVICommandsRing::reset() 000000000008d470 __float128 0f SECT 01 0000 [.text] AMDVICommandsRing::MetaClass::MetaClass() 000000000008d530 __float128 0f SECT 01 0000 [.text] AMDVICommandsRing::MetaClass::MetaClass() 00000000003bb680 __float128 0f SECT 08 0000 [.const_data] AMDVICommandsRing::metaClass 000000000008d4cc __float128 0f SECT 01 0000 [.text] AMDVICommandsRing::AMDVICommandsRing(OSMetaClass const*) 000000000008d5a2 __float128 0f SECT 01 0000 [.text] AMDVICommandsRing::AMDVICommandsRing() 000000000008d4ac __float128 0f SECT 01 0000 [.text] AMDVICommandsRing::AMDVICommandsRing(OSMetaClass const*) 000000000008d5d2 __float128 0f SECT 01 0000 [.text] AMDVICommandsRing::AMDVICommandsRing() 000000000008d500 __float128 0f SECT 01 0000 [.text] AMDVICommandsRing::~AMDVICommandsRing() 000000000008d4f6 __float128 0f SECT 01 0000 [.text] AMDVICommandsRing::~AMDVICommandsRing() 000000000008d4ec __float128 0f SECT 01 0000 [.text] AMDVICommandsRing::~AMDVICommandsRing() 000000000052e210 __float128 0f SECT 0a 0000 [__DATA.__common] AMDVerdePM4Engine::gMetaClass 00000000003ae078 __float128 0f SECT 08 0000 [.const_data] AMDVerdePM4Engine::superClass 000000000006c322 __float128 0f SECT 01 0000 [.text] AMDVerdePM4Engine::init(AMDRadeonX4000_IAMDHWInterface*, _eAMD_HW_ENGINE_TYPE) 000000000006c190 __float128 0f SECT 01 0000 [.text] AMDVerdePM4Engine::MetaClass::MetaClass() 000000000006c250 __float128 0f SECT 01 0000 [.text] AMDVerdePM4Engine::MetaClass::MetaClass() 00000000003ae070 __float128 0f SECT 08 0000 [.const_data] AMDVerdePM4Engine::metaClass 000000000006c1ec __float128 0f SECT 01 0000 [.text] AMDVerdePM4Engine::AMDVerdePM4Engine(OSMetaClass const*) 000000000006c2c2 __float128 0f SECT 01 0000 [.text] AMDVerdePM4Engine::AMDVerdePM4Engine() 000000000006c1cc __float128 0f SECT 01 0000 [.text] AMDVerdePM4Engine::AMDVerdePM4Engine(OSMetaClass const*) 000000000006c2f2 __float128 0f SECT 01 0000 [.text] AMDVerdePM4Engine::AMDVerdePM4Engine() 000000000006c220 __float128 0f SECT 01 0000 [.text] AMDVerdePM4Engine::~AMDVerdePM4Engine() 000000000006c216 __float128 0f SECT 01 0000 [.text] AMDVerdePM4Engine::~AMDVerdePM4Engine() 000000000006c20c __float128 0f SECT 01 0000 [.text] AMDVerdePM4Engine::~AMDVerdePM4Engine() 00000000000ca2c0 __float128 0f SECT 01 0000 [.text] SiBltVertexShader::SetShaderInput(SiBltVertexShaderInput const*) 00000000000ca320 __float128 0f SECT 01 0000 [.text] SiBltVertexShader::GetImmVbRsrcRegCount(unsigned int) 00000000000ca2e8 __float128 0f SECT 01 0000 [.text] SiBltVertexShader::GetImmVbRsrcStartReg(unsigned int) 00000000000caccc __float128 0f SECT 01 0000 [.text] SiShaderVidMemMgr::SetupShader(unsigned int, SiBltShaderInput*) 00000000000cb0c4 __float128 0f SECT 01 0000 [.text] SiShaderVidMemMgr::GetPixelShader(unsigned int) 00000000000cb098 __float128 0f SECT 01 0000 [.text] SiShaderVidMemMgr::GetVertexShader(unsigned int) 00000000000cb0f8 __float128 0f SECT 01 0000 [.text] SiShaderVidMemMgr::GetComputeShader(unsigned int) 00000000000caf30 __float128 0f SECT 01 0000 [.text] SiShaderVidMemMgr::GpuLoadAllShaders(BltDevice*) 00000000000cad7c __float128 0f SECT 01 0000 [.text] SiShaderVidMemMgr::CpuLoadInitialShaders() 00000000000caf22 __float128 0f SECT 01 0000 [.text] SiShaderVidMemMgr::GpuLoadInitialShaders(BltDevice*) 00000000000ca5ee __float128 0f SECT 01 0000 [.text] SiShaderVidMemMgr::InitializeShaderGroupMapping() 00000000000caa32 __float128 0f SECT 01 0000 [.text] SiShaderVidMemMgr::SiShaderVidMemMgr(SiBltMgr*) 00000000000ca93a __float128 0f SECT 01 0000 [.text] SiShaderVidMemMgr::SiShaderVidMemMgr(SiBltMgr*) 00000000000cacb0 __float128 0f SECT 01 0000 [.text] SiShaderVidMemMgr::~SiShaderVidMemMgr() 00000000000cab76 __float128 0f SECT 01 0000 [.text] SiShaderVidMemMgr::~SiShaderVidMemMgr() 00000000000caa3c __float128 0f SECT 01 0000 [.text] SiShaderVidMemMgr::~SiShaderVidMemMgr() 000000000052e530 __float128 0f SECT 0a 0000 [__DATA.__common] AMDBonaireHardware::gMetaClass 00000000003b2b48 __float128 0f SECT 08 0000 [.const_data] AMDBonaireHardware::superClass 00000000000775d8 __float128 0f SECT 01 0000 [.text] AMDBonaireHardware::getATIChipConfigBit() 00000000000775b4 __float128 0f SECT 01 0000 [.text] AMDBonaireHardware::readChipRevFromRegister() 00000000000776a4 __float128 0f SECT 01 0000 [.text] AMDBonaireHardware::setupAndInitializeHWCapabilities() 00000000000775a2 __float128 0f SECT 01 0000 [.text] AMDBonaireHardware::init(IOPCIDevice*, AMDRadeonX4000_IAMDHWHandler*, unsigned int&, unsigned int, _GART_PARAMETERS*, _FB_PARAMETERS*) 00000000000775e4 __float128 0f SECT 01 0000 [.text] AMDBonaireHardware::powerUp() 0000000000077410 __float128 0f SECT 01 0000 [.text] AMDBonaireHardware::MetaClass::MetaClass() 00000000000774d0 __float128 0f SECT 01 0000 [.text] AMDBonaireHardware::MetaClass::MetaClass() 00000000003b2b40 __float128 0f SECT 08 0000 [.const_data] AMDBonaireHardware::metaClass 000000000007746c __float128 0f SECT 01 0000 [.text] AMDBonaireHardware::AMDBonaireHardware(OSMetaClass const*) 0000000000077542 __float128 0f SECT 01 0000 [.text] AMDBonaireHardware::AMDBonaireHardware() 000000000007744c __float128 0f SECT 01 0000 [.text] AMDBonaireHardware::AMDBonaireHardware(OSMetaClass const*) 0000000000077572 __float128 0f SECT 01 0000 [.text] AMDBonaireHardware::AMDBonaireHardware() 00000000000774a0 __float128 0f SECT 01 0000 [.text] AMDBonaireHardware::~AMDBonaireHardware() 0000000000077496 __float128 0f SECT 01 0000 [.text] AMDBonaireHardware::~AMDBonaireHardware() 000000000007748c __float128 0f SECT 01 0000 [.text] AMDBonaireHardware::~AMDBonaireHardware() 000000000052e788 __float128 0f SECT 0a 0000 [__DATA.__common] AMDCISAMUGPCOMRing::gMetaClass 00000000003b6688 __float128 0f SECT 08 0000 [.const_data] AMDCISAMUGPCOMRing::superClass 000000000008072a __float128 0f SECT 01 0000 [.text] AMDCISAMUGPCOMRing::commitBlock(unsigned int) 0000000000080654 __float128 0f SECT 01 0000 [.text] AMDCISAMUGPCOMRing::freeResources() 0000000000080744 __float128 0f SECT 01 0000 [.text] AMDCISAMUGPCOMRing::getReadPointer() 00000000000807cc __float128 0f SECT 01 0000 [.text] AMDCISAMUGPCOMRing::getWritePointer() 00000000000806cc __float128 0f SECT 01 0000 [.text] AMDCISAMUGPCOMRing::registerLocation() 000000000008056e __float128 0f SECT 01 0000 [.text] AMDCISAMUGPCOMRing::allocateResources() 0000000000080786 __float128 0f SECT 01 0000 [.text] AMDCISAMUGPCOMRing::readIndirectSAMUSABReg(unsigned int) 00000000000808ec __float128 0f SECT 01 0000 [.text] AMDCISAMUGPCOMRing::writeIndirectSAMUSABReg(unsigned int, unsigned int) 00000000000806f0 __float128 0f SECT 01 0000 [.text] AMDCISAMUGPCOMRing::enableReadPointerWriteBack() 00000000000806f6 __float128 0f SECT 01 0000 [.text] AMDCISAMUGPCOMRing::disableReadPointerWriteBack() 0000000000080702 __float128 0f SECT 01 0000 [.text] AMDCISAMUGPCOMRing::programReadAndWritePointers(unsigned int) 0000000000080532 __float128 0f SECT 01 0000 [.text] AMDCISAMUGPCOMRing::free() 0000000000080492 __float128 0f SECT 01 0000 [.text] AMDCISAMUGPCOMRing::init(AMDRadeonX4000_IAMDHWInterface*, int, _eAMD_HW_ENGINE_TYPE, unsigned int, void const*) 000000000008073e __float128 0f SECT 01 0000 [.text] AMDCISAMUGPCOMRing::align() 00000000000806fc __float128 0f SECT 01 0000 [.text] AMDCISAMUGPCOMRing::reset() 000000000008070a __float128 0f SECT 01 0000 [.text] AMDCISAMUGPCOMRing::write(unsigned int) 00000000000806be __float128 0f SECT 01 0000 [.text] AMDCISAMUGPCOMRing::getHead() 0000000000080300 __float128 0f SECT 01 0000 [.text] AMDCISAMUGPCOMRing::MetaClass::MetaClass() 00000000000803c0 __float128 0f SECT 01 0000 [.text] AMDCISAMUGPCOMRing::MetaClass::MetaClass() 00000000003b6680 __float128 0f SECT 08 0000 [.const_data] AMDCISAMUGPCOMRing::metaClass 000000000008080e __float128 0f SECT 01 0000 [.text] AMDCISAMUGPCOMRing::writeTail() 000000000008035c __float128 0f SECT 01 0000 [.text] AMDCISAMUGPCOMRing::AMDCISAMUGPCOMRing(OSMetaClass const*) 0000000000080432 __float128 0f SECT 01 0000 [.text] AMDCISAMUGPCOMRing::AMDCISAMUGPCOMRing() 000000000008033c __float128 0f SECT 01 0000 [.text] AMDCISAMUGPCOMRing::AMDCISAMUGPCOMRing(OSMetaClass const*) 0000000000080462 __float128 0f SECT 01 0000 [.text] AMDCISAMUGPCOMRing::AMDCISAMUGPCOMRing() 0000000000080390 __float128 0f SECT 01 0000 [.text] AMDCISAMUGPCOMRing::~AMDCISAMUGPCOMRing() 0000000000080386 __float128 0f SECT 01 0000 [.text] AMDCISAMUGPCOMRing::~AMDCISAMUGPCOMRing() 000000000008037c __float128 0f SECT 01 0000 [.text] AMDCISAMUGPCOMRing::~AMDCISAMUGPCOMRing() 000000000052e850 __float128 0f SECT 0a 0000 [__DATA.__common] AMDCIVCELLQChannel::gMetaClass 00000000003b79a8 __float128 0f SECT 08 0000 [.const_data] AMDCIVCELLQChannel::superClass 0000000000082206 __float128 0f SECT 01 0000 [.text] AMDCIVCELLQChannel::timeStampInterruptType() 00000000000821f4 __float128 0f SECT 01 0000 [.text] AMDCIVCELLQChannel::free() 00000000000821e2 __float128 0f SECT 01 0000 [.text] AMDCIVCELLQChannel::init(int, AMDRadeonX4000_IAMDHWInterface*, AMDRadeonX4000_IAMDHWEngine*, AMDRadeonX4000_IAMDHWRing*, char const*) 0000000000082050 __float128 0f SECT 01 0000 [.text] AMDCIVCELLQChannel::MetaClass::MetaClass() 0000000000082110 __float128 0f SECT 01 0000 [.text] AMDCIVCELLQChannel::MetaClass::MetaClass() 00000000003b79a0 __float128 0f SECT 08 0000 [.const_data] AMDCIVCELLQChannel::metaClass 00000000000820ac __float128 0f SECT 01 0000 [.text] AMDCIVCELLQChannel::AMDCIVCELLQChannel(OSMetaClass const*) 0000000000082182 __float128 0f SECT 01 0000 [.text] AMDCIVCELLQChannel::AMDCIVCELLQChannel() 000000000008208c __float128 0f SECT 01 0000 [.text] AMDCIVCELLQChannel::AMDCIVCELLQChannel(OSMetaClass const*) 00000000000821b2 __float128 0f SECT 01 0000 [.text] AMDCIVCELLQChannel::AMDCIVCELLQChannel() 00000000000820e0 __float128 0f SECT 01 0000 [.text] AMDCIVCELLQChannel::~AMDCIVCELLQChannel() 00000000000820d6 __float128 0f SECT 01 0000 [.text] AMDCIVCELLQChannel::~AMDCIVCELLQChannel() 00000000000820cc __float128 0f SECT 01 0000 [.text] AMDCIVCELLQChannel::~AMDCIVCELLQChannel() 000000000052e350 __float128 0f SECT 0a 0000 [__DATA.__common] AMDSIVCELLQChannel::gMetaClass 00000000003afce8 __float128 0f SECT 08 0000 [.const_data] AMDSIVCELLQChannel::superClass 00000000000701e6 __float128 0f SECT 01 0000 [.text] AMDSIVCELLQChannel::timeStampInterruptType() 00000000000701d4 __float128 0f SECT 01 0000 [.text] AMDSIVCELLQChannel::free() 00000000000701c2 __float128 0f SECT 01 0000 [.text] AMDSIVCELLQChannel::init(int, AMDRadeonX4000_IAMDHWInterface*, AMDRadeonX4000_IAMDHWEngine*, AMDRadeonX4000_IAMDHWRing*, char const*) 0000000000070030 __float128 0f SECT 01 0000 [.text] AMDSIVCELLQChannel::MetaClass::MetaClass() 00000000000700f0 __float128 0f SECT 01 0000 [.text] AMDSIVCELLQChannel::MetaClass::MetaClass() 00000000003afce0 __float128 0f SECT 08 0000 [.const_data] AMDSIVCELLQChannel::metaClass 000000000007008c __float128 0f SECT 01 0000 [.text] AMDSIVCELLQChannel::AMDSIVCELLQChannel(OSMetaClass const*) 0000000000070162 __float128 0f SECT 01 0000 [.text] AMDSIVCELLQChannel::AMDSIVCELLQChannel() 000000000007006c __float128 0f SECT 01 0000 [.text] AMDSIVCELLQChannel::AMDSIVCELLQChannel(OSMetaClass const*) 0000000000070192 __float128 0f SECT 01 0000 [.text] AMDSIVCELLQChannel::AMDSIVCELLQChannel() 00000000000700c0 __float128 0f SECT 01 0000 [.text] AMDSIVCELLQChannel::~AMDSIVCELLQChannel() 00000000000700b6 __float128 0f SECT 01 0000 [.text] AMDSIVCELLQChannel::~AMDSIVCELLQChannel() 00000000000700ac __float128 0f SECT 01 0000 [.text] AMDSIVCELLQChannel::~AMDSIVCELLQChannel() 000000000052e1c0 __float128 0f SECT 0a 0000 [__DATA.__common] AMDTahitiPM4Engine::gMetaClass 00000000003ad9b8 __float128 0f SECT 08 0000 [.const_data] AMDTahitiPM4Engine::superClass 000000000006bc62 __float128 0f SECT 01 0000 [.text] AMDTahitiPM4Engine::init(AMDRadeonX4000_IAMDHWInterface*, _eAMD_HW_ENGINE_TYPE) 000000000006bad0 __float128 0f SECT 01 0000 [.text] AMDTahitiPM4Engine::MetaClass::MetaClass() 000000000006bb90 __float128 0f SECT 01 0000 [.text] AMDTahitiPM4Engine::MetaClass::MetaClass() 00000000003ad9b0 __float128 0f SECT 08 0000 [.const_data] AMDTahitiPM4Engine::metaClass 000000000006bb2c __float128 0f SECT 01 0000 [.text] AMDTahitiPM4Engine::AMDTahitiPM4Engine(OSMetaClass const*) 000000000006bc02 __float128 0f SECT 01 0000 [.text] AMDTahitiPM4Engine::AMDTahitiPM4Engine() 000000000006bb0c __float128 0f SECT 01 0000 [.text] AMDTahitiPM4Engine::AMDTahitiPM4Engine(OSMetaClass const*) 000000000006bc32 __float128 0f SECT 01 0000 [.text] AMDTahitiPM4Engine::AMDTahitiPM4Engine() 000000000006bb60 __float128 0f SECT 01 0000 [.text] AMDTahitiPM4Engine::~AMDTahitiPM4Engine() 000000000006bb56 __float128 0f SECT 01 0000 [.text] AMDTahitiPM4Engine::~AMDTahitiPM4Engine() 000000000006bb4c __float128 0f SECT 01 0000 [.text] AMDTahitiPM4Engine::~AMDTahitiPM4Engine() 000000000052ec38 __float128 0f SECT 0a 0000 [__DATA.__common] AMDVISAMUGPCOMRing::gMetaClass 00000000003bd5b8 __float128 0f SECT 08 0000 [.const_data] AMDVISAMUGPCOMRing::superClass 0000000000093056 __float128 0f SECT 01 0000 [.text] AMDVISAMUGPCOMRing::getReadPointer() 00000000000930de __float128 0f SECT 01 0000 [.text] AMDVISAMUGPCOMRing::getWritePointer() 0000000000093098 __float128 0f SECT 01 0000 [.text] AMDVISAMUGPCOMRing::readIndirectSAMUSABReg(unsigned int) 00000000000931fe __float128 0f SECT 01 0000 [.text] AMDVISAMUGPCOMRing::writeIndirectSAMUSABReg(unsigned int, unsigned int) 0000000000093044 __float128 0f SECT 01 0000 [.text] AMDVISAMUGPCOMRing::free() 0000000000093032 __float128 0f SECT 01 0000 [.text] AMDVISAMUGPCOMRing::init(AMDRadeonX4000_IAMDHWInterface*, int, _eAMD_HW_ENGINE_TYPE, unsigned int, void const*) 0000000000092ea0 __float128 0f SECT 01 0000 [.text] AMDVISAMUGPCOMRing::MetaClass::MetaClass() 0000000000092f60 __float128 0f SECT 01 0000 [.text] AMDVISAMUGPCOMRing::MetaClass::MetaClass() 00000000003bd5b0 __float128 0f SECT 08 0000 [.const_data] AMDVISAMUGPCOMRing::metaClass 0000000000093120 __float128 0f SECT 01 0000 [.text] AMDVISAMUGPCOMRing::writeTail() 0000000000092efc __float128 0f SECT 01 0000 [.text] AMDVISAMUGPCOMRing::AMDVISAMUGPCOMRing(OSMetaClass const*) 0000000000092fd2 __float128 0f SECT 01 0000 [.text] AMDVISAMUGPCOMRing::AMDVISAMUGPCOMRing() 0000000000092edc __float128 0f SECT 01 0000 [.text] AMDVISAMUGPCOMRing::AMDVISAMUGPCOMRing(OSMetaClass const*) 0000000000093002 __float128 0f SECT 01 0000 [.text] AMDVISAMUGPCOMRing::AMDVISAMUGPCOMRing() 0000000000092f30 __float128 0f SECT 01 0000 [.text] AMDVISAMUGPCOMRing::~AMDVISAMUGPCOMRing() 0000000000092f26 __float128 0f SECT 01 0000 [.text] AMDVISAMUGPCOMRing::~AMDVISAMUGPCOMRing() 0000000000092f1c __float128 0f SECT 01 0000 [.text] AMDVISAMUGPCOMRing::~AMDVISAMUGPCOMRing() 00000000000aad38 __float128 0f SECT 01 0000 [.text] SiBltComputeShader::SetShaderInput(SiBltComputeShaderInput const*) 00000000000aad46 __float128 0f SECT 01 0000 [.text] SiBltComputeShader::GetThreadGroupSize(unsigned int*, unsigned int*, unsigned int*) 00000000000bddec __float128 0f SECT 01 0000 [.text] SiBltShaderLibrary::SetupShaders() 00000000000bde14 __float128 0f SECT 01 0000 [.text] SiBltShaderLibrary::CpuLoadShaders() 00000000000bde24 __float128 0f SECT 01 0000 [.text] SiBltShaderLibrary::GpuLoadShaders(SiBltDevice*) 00000000000c26d0 __float128 0f SECT 01 0000 [.text] SiBltShaderLibrary::SetupCiShaders() 00000000000be8d8 __float128 0f SECT 01 0000 [.text] SiBltShaderLibrary::SetupSiShaders() 00000000000c64c8 __float128 0f SECT 01 0000 [.text] SiBltShaderLibrary::SetupViShaders() 00000000000be8ca __float128 0f SECT 01 0000 [.text] SiBltShaderLibrary::PsPatchingDisabled(PsType) 00000000000bdda8 __float128 0f SECT 01 0000 [.text] SiBltShaderLibrary::Init(SiBltMgr*) 00000000000bdd6e __float128 0f SECT 01 0000 [.text] SiBltShaderLibrary::SiBltShaderLibrary() 00000000000bdd60 __float128 0f SECT 01 0000 [.text] SiBltShaderLibrary::SiBltShaderLibrary() 00000000000bdd92 __float128 0f SECT 01 0000 [.text] SiBltShaderLibrary::~SiBltShaderLibrary() 00000000000bdd7c __float128 0f SECT 01 0000 [.text] SiBltShaderLibrary::~SiBltShaderLibrary() 000000000052e760 __float128 0f SECT 0a 0000 [__DATA.__common] AMDCISAMURBIChannel::gMetaClass 00000000003b62e8 __float128 0f SECT 08 0000 [.const_data] AMDCISAMURBIChannel::superClass 00000000000800fc __float128 0f SECT 01 0000 [.text] AMDCISAMURBIChannel::commitIndirectCommandBuffer(AMD_SUBMIT_COMMAND_BUFFER_INFO*) 00000000000800ea __float128 0f SECT 01 0000 [.text] AMDCISAMURBIChannel::free() 0000000000080092 __float128 0f SECT 01 0000 [.text] AMDCISAMURBIChannel::init(int, AMDRadeonX4000_IAMDHWInterface*, AMDRadeonX4000_IAMDHWEngine*, AMDRadeonX4000_IAMDHWRing*, char const*) 000000000007ff00 __float128 0f SECT 01 0000 [.text] AMDCISAMURBIChannel::MetaClass::MetaClass() 000000000007ffc0 __float128 0f SECT 01 0000 [.text] AMDCISAMURBIChannel::MetaClass::MetaClass() 00000000003b62e0 __float128 0f SECT 08 0000 [.const_data] AMDCISAMURBIChannel::metaClass 000000000007ff5c __float128 0f SECT 01 0000 [.text] AMDCISAMURBIChannel::AMDCISAMURBIChannel(OSMetaClass const*) 0000000000080032 __float128 0f SECT 01 0000 [.text] AMDCISAMURBIChannel::AMDCISAMURBIChannel() 000000000007ff3c __float128 0f SECT 01 0000 [.text] AMDCISAMURBIChannel::AMDCISAMURBIChannel(OSMetaClass const*) 0000000000080062 __float128 0f SECT 01 0000 [.text] AMDCISAMURBIChannel::AMDCISAMURBIChannel() 000000000007ff90 __float128 0f SECT 01 0000 [.text] AMDCISAMURBIChannel::~AMDCISAMURBIChannel() 000000000007ff86 __float128 0f SECT 01 0000 [.text] AMDCISAMURBIChannel::~AMDCISAMURBIChannel() 000000000007ff7c __float128 0f SECT 01 0000 [.text] AMDCISAMURBIChannel::~AMDCISAMURBIChannel() 000000000052e120 __float128 0f SECT 0a 0000 [__DATA.__common] AMDPitcairnHardware::gMetaClass 00000000003ac518 __float128 0f SECT 08 0000 [.const_data] AMDPitcairnHardware::superClass 000000000006a3a4 __float128 0f SECT 01 0000 [.text] AMDPitcairnHardware::allocateSML() 000000000006a4b4 __float128 0f SECT 01 0000 [.text] AMDPitcairnHardware::allocatePM4Engine() 000000000006a398 __float128 0f SECT 01 0000 [.text] AMDPitcairnHardware::getATIChipConfigBit() 000000000006a374 __float128 0f SECT 01 0000 [.text] AMDPitcairnHardware::readChipRevFromRegister() 000000000006a48a __float128 0f SECT 01 0000 [.text] AMDPitcairnHardware::setupAndInitializeHWCapabilities() 000000000006a362 __float128 0f SECT 01 0000 [.text] AMDPitcairnHardware::init(IOPCIDevice*, AMDRadeonX4000_IAMDHWHandler*, unsigned int&, unsigned int, _GART_PARAMETERS*, _FB_PARAMETERS*) 000000000006a3ca __float128 0f SECT 01 0000 [.text] AMDPitcairnHardware::powerUp() 000000000006a1d0 __float128 0f SECT 01 0000 [.text] AMDPitcairnHardware::MetaClass::MetaClass() 000000000006a290 __float128 0f SECT 01 0000 [.text] AMDPitcairnHardware::MetaClass::MetaClass() 00000000003ac510 __float128 0f SECT 08 0000 [.const_data] AMDPitcairnHardware::metaClass 000000000006a22c __float128 0f SECT 01 0000 [.text] AMDPitcairnHardware::AMDPitcairnHardware(OSMetaClass const*) 000000000006a302 __float128 0f SECT 01 0000 [.text] AMDPitcairnHardware::AMDPitcairnHardware() 000000000006a20c __float128 0f SECT 01 0000 [.text] AMDPitcairnHardware::AMDPitcairnHardware(OSMetaClass const*) 000000000006a332 __float128 0f SECT 01 0000 [.text] AMDPitcairnHardware::AMDPitcairnHardware() 000000000006a260 __float128 0f SECT 01 0000 [.text] AMDPitcairnHardware::~AMDPitcairnHardware() 000000000006a256 __float128 0f SECT 01 0000 [.text] AMDPitcairnHardware::~AMDPitcairnHardware() 000000000006a24c __float128 0f SECT 01 0000 [.text] AMDPitcairnHardware::~AMDPitcairnHardware() 000000000052d608 __float128 0f SECT 0a 0000 [__DATA.__common] AMDSIDisplayMachine::gMetaClass 0000000000396898 __float128 0f SECT 08 0000 [.const_data] AMDSIDisplayMachine::superClass 000000000002a010 __float128 0f SECT 01 0000 [.text] AMDSIDisplayMachine::MetaClass::MetaClass() 000000000002a0d0 __float128 0f SECT 01 0000 [.text] AMDSIDisplayMachine::MetaClass::MetaClass() 0000000000396890 __float128 0f SECT 08 0000 [.const_data] AMDSIDisplayMachine::metaClass 000000000002a06c __float128 0f SECT 01 0000 [.text] AMDSIDisplayMachine::AMDSIDisplayMachine(OSMetaClass const*) 000000000002a142 __float128 0f SECT 01 0000 [.text] AMDSIDisplayMachine::AMDSIDisplayMachine() 000000000002a04c __float128 0f SECT 01 0000 [.text] AMDSIDisplayMachine::AMDSIDisplayMachine(OSMetaClass const*) 000000000002a172 __float128 0f SECT 01 0000 [.text] AMDSIDisplayMachine::AMDSIDisplayMachine() 000000000002a0a0 __float128 0f SECT 01 0000 [.text] AMDSIDisplayMachine::~AMDSIDisplayMachine() 000000000002a096 __float128 0f SECT 01 0000 [.text] AMDSIDisplayMachine::~AMDSIDisplayMachine() 000000000002a08c __float128 0f SECT 01 0000 [.text] AMDSIDisplayMachine::~AMDSIDisplayMachine() 000000000052e170 __float128 0f SECT 0a 0000 [__DATA.__common] AMDSIHWAlignManager::gMetaClass 00000000003ad378 __float128 0f SECT 08 0000 [.const_data] AMDSIHWAlignManager::superClass 000000000006af82 __float128 0f SECT 01 0000 [.text] AMDSIHWAlignManager::getAddrFormat(unsigned int) 000000000006adf0 __float128 0f SECT 01 0000 [.text] AMDSIHWAlignManager::MetaClass::MetaClass() 000000000006aeb0 __float128 0f SECT 01 0000 [.text] AMDSIHWAlignManager::MetaClass::MetaClass() 00000000003ad370 __float128 0f SECT 08 0000 [.const_data] AMDSIHWAlignManager::metaClass 000000000006ae4c __float128 0f SECT 01 0000 [.text] AMDSIHWAlignManager::AMDSIHWAlignManager(OSMetaClass const*) 000000000006af22 __float128 0f SECT 01 0000 [.text] AMDSIHWAlignManager::AMDSIHWAlignManager() 000000000006ae2c __float128 0f SECT 01 0000 [.text] AMDSIHWAlignManager::AMDSIHWAlignManager(OSMetaClass const*) 000000000006af52 __float128 0f SECT 01 0000 [.text] AMDSIHWAlignManager::AMDSIHWAlignManager() 000000000006ae80 __float128 0f SECT 01 0000 [.text] AMDSIHWAlignManager::~AMDSIHWAlignManager() 000000000006ae76 __float128 0f SECT 01 0000 [.text] AMDSIHWAlignManager::~AMDSIHWAlignManager() 000000000006ae6c __float128 0f SECT 01 0000 [.text] AMDSIHWAlignManager::~AMDSIHWAlignManager() 000000000052d810 __float128 0f SECT 0a 0000 [__DATA.__common] AMDVIDisplayMachine::gMetaClass 000000000039f948 __float128 0f SECT 08 0000 [.const_data] AMDVIDisplayMachine::superClass 0000000000046d60 __float128 0f SECT 01 0000 [.text] AMDVIDisplayMachine::MetaClass::MetaClass() 0000000000046e20 __float128 0f SECT 01 0000 [.text] AMDVIDisplayMachine::MetaClass::MetaClass() 000000000039f940 __float128 0f SECT 08 0000 [.const_data] AMDVIDisplayMachine::metaClass 0000000000046dbc __float128 0f SECT 01 0000 [.text] AMDVIDisplayMachine::AMDVIDisplayMachine(OSMetaClass const*) 0000000000046e92 __float128 0f SECT 01 0000 [.text] AMDVIDisplayMachine::AMDVIDisplayMachine() 0000000000046d9c __float128 0f SECT 01 0000 [.text] AMDVIDisplayMachine::AMDVIDisplayMachine(OSMetaClass const*) 0000000000046ec2 __float128 0f SECT 01 0000 [.text] AMDVIDisplayMachine::AMDVIDisplayMachine() 0000000000046df0 __float128 0f SECT 01 0000 [.text] AMDVIDisplayMachine::~AMDVIDisplayMachine() 0000000000046de6 __float128 0f SECT 01 0000 [.text] AMDVIDisplayMachine::~AMDVIDisplayMachine() 0000000000046ddc __float128 0f SECT 01 0000 [.text] AMDVIDisplayMachine::~AMDVIDisplayMachine() 000000000052ec10 __float128 0f SECT 0a 0000 [__DATA.__common] AMDVISAMURBIChannel::gMetaClass 00000000003bd218 __float128 0f SECT 08 0000 [.const_data] AMDVISAMURBIChannel::superClass 0000000000092d14 __float128 0f SECT 01 0000 [.text] AMDVISAMURBIChannel::free() 0000000000092d02 __float128 0f SECT 01 0000 [.text] AMDVISAMURBIChannel::init(int, AMDRadeonX4000_IAMDHWInterface*, AMDRadeonX4000_IAMDHWEngine*, AMDRadeonX4000_IAMDHWRing*, char const*) 0000000000092b70 __float128 0f SECT 01 0000 [.text] AMDVISAMURBIChannel::MetaClass::MetaClass() 0000000000092c30 __float128 0f SECT 01 0000 [.text] AMDVISAMURBIChannel::MetaClass::MetaClass() 00000000003bd210 __float128 0f SECT 08 0000 [.const_data] AMDVISAMURBIChannel::metaClass 0000000000092bcc __float128 0f SECT 01 0000 [.text] AMDVISAMURBIChannel::AMDVISAMURBIChannel(OSMetaClass const*) 0000000000092ca2 __float128 0f SECT 01 0000 [.text] AMDVISAMURBIChannel::AMDVISAMURBIChannel() 0000000000092bac __float128 0f SECT 01 0000 [.text] AMDVISAMURBIChannel::AMDVISAMURBIChannel(OSMetaClass const*) 0000000000092cd2 __float128 0f SECT 01 0000 [.text] AMDVISAMURBIChannel::AMDVISAMURBIChannel() 0000000000092c00 __float128 0f SECT 01 0000 [.text] AMDVISAMURBIChannel::~AMDVISAMURBIChannel() 0000000000092bf6 __float128 0f SECT 01 0000 [.text] AMDVISAMURBIChannel::~AMDVISAMURBIChannel() 0000000000092bec __float128 0f SECT 01 0000 [.text] AMDVISAMURBIChannel::~AMDVISAMURBIChannel() 000000000052e1e8 __float128 0f SECT 0a 0000 [__DATA.__common] AMDPitcairnPM4Engine::gMetaClass 00000000003add18 __float128 0f SECT 08 0000 [.const_data] AMDPitcairnPM4Engine::superClass 000000000006bfc2 __float128 0f SECT 01 0000 [.text] AMDPitcairnPM4Engine::init(AMDRadeonX4000_IAMDHWInterface*, _eAMD_HW_ENGINE_TYPE) 000000000006be30 __float128 0f SECT 01 0000 [.text] AMDPitcairnPM4Engine::MetaClass::MetaClass() 000000000006bef0 __float128 0f SECT 01 0000 [.text] AMDPitcairnPM4Engine::MetaClass::MetaClass() 00000000003add10 __float128 0f SECT 08 0000 [.const_data] AMDPitcairnPM4Engine::metaClass 000000000006be8c __float128 0f SECT 01 0000 [.text] AMDPitcairnPM4Engine::AMDPitcairnPM4Engine(OSMetaClass const*) 000000000006bf62 __float128 0f SECT 01 0000 [.text] AMDPitcairnPM4Engine::AMDPitcairnPM4Engine() 000000000006be6c __float128 0f SECT 01 0000 [.text] AMDPitcairnPM4Engine::AMDPitcairnPM4Engine(OSMetaClass const*) 000000000006bf92 __float128 0f SECT 01 0000 [.text] AMDPitcairnPM4Engine::AMDPitcairnPM4Engine() 000000000006bec0 __float128 0f SECT 01 0000 [.text] AMDPitcairnPM4Engine::~AMDPitcairnPM4Engine() 000000000006beb6 __float128 0f SECT 01 0000 [.text] AMDPitcairnPM4Engine::~AMDPitcairnPM4Engine() 000000000006beac __float128 0f SECT 01 0000 [.text] AMDPitcairnPM4Engine::~AMDPitcairnPM4Engine() 000000000052e7b0 __float128 0f SECT 0a 0000 [__DATA.__common] AMDCISAMUGPCOMChannel::gMetaClass 00000000003b69c8 __float128 0f SECT 08 0000 [.const_data] AMDCISAMUGPCOMChannel::superClass 0000000000080c6e __float128 0f SECT 01 0000 [.text] AMDCISAMUGPCOMChannel::commitIndirectCommandBuffer(AMD_SUBMIT_COMMAND_BUFFER_INFO*) 0000000000080c5c __float128 0f SECT 01 0000 [.text] AMDCISAMUGPCOMChannel::free() 0000000000080c12 __float128 0f SECT 01 0000 [.text] AMDCISAMUGPCOMChannel::init(int, AMDRadeonX4000_IAMDHWInterface*, AMDRadeonX4000_IAMDHWEngine*, AMDRadeonX4000_IAMDHWRing*, char const*) 0000000000080a80 __float128 0f SECT 01 0000 [.text] AMDCISAMUGPCOMChannel::MetaClass::MetaClass() 0000000000080b40 __float128 0f SECT 01 0000 [.text] AMDCISAMUGPCOMChannel::MetaClass::MetaClass() 00000000003b69c0 __float128 0f SECT 08 0000 [.const_data] AMDCISAMUGPCOMChannel::metaClass 0000000000080adc __float128 0f SECT 01 0000 [.text] AMDCISAMUGPCOMChannel::AMDCISAMUGPCOMChannel(OSMetaClass const*) 0000000000080bb2 __float128 0f SECT 01 0000 [.text] AMDCISAMUGPCOMChannel::AMDCISAMUGPCOMChannel() 0000000000080abc __float128 0f SECT 01 0000 [.text] AMDCISAMUGPCOMChannel::AMDCISAMUGPCOMChannel(OSMetaClass const*) 0000000000080be2 __float128 0f SECT 01 0000 [.text] AMDCISAMUGPCOMChannel::AMDCISAMUGPCOMChannel() 0000000000080b10 __float128 0f SECT 01 0000 [.text] AMDCISAMUGPCOMChannel::~AMDCISAMUGPCOMChannel() 0000000000080b06 __float128 0f SECT 01 0000 [.text] AMDCISAMUGPCOMChannel::~AMDCISAMUGPCOMChannel() 0000000000080afc __float128 0f SECT 01 0000 [.text] AMDCISAMUGPCOMChannel::~AMDCISAMUGPCOMChannel() 000000000052ec60 __float128 0f SECT 0a 0000 [__DATA.__common] AMDVISAMUGPCOMChannel::gMetaClass 00000000003bd8f8 __float128 0f SECT 08 0000 [.const_data] AMDVISAMUGPCOMChannel::superClass 0000000000093534 __float128 0f SECT 01 0000 [.text] AMDVISAMUGPCOMChannel::free() 0000000000093522 __float128 0f SECT 01 0000 [.text] AMDVISAMUGPCOMChannel::init(int, AMDRadeonX4000_IAMDHWInterface*, AMDRadeonX4000_IAMDHWEngine*, AMDRadeonX4000_IAMDHWRing*, char const*) 0000000000093390 __float128 0f SECT 01 0000 [.text] AMDVISAMUGPCOMChannel::MetaClass::MetaClass() 0000000000093450 __float128 0f SECT 01 0000 [.text] AMDVISAMUGPCOMChannel::MetaClass::MetaClass() 00000000003bd8f0 __float128 0f SECT 08 0000 [.const_data] AMDVISAMUGPCOMChannel::metaClass 00000000000933ec __float128 0f SECT 01 0000 [.text] AMDVISAMUGPCOMChannel::AMDVISAMUGPCOMChannel(OSMetaClass const*) 00000000000934c2 __float128 0f SECT 01 0000 [.text] AMDVISAMUGPCOMChannel::AMDVISAMUGPCOMChannel() 00000000000933cc __float128 0f SECT 01 0000 [.text] AMDVISAMUGPCOMChannel::AMDVISAMUGPCOMChannel(OSMetaClass const*) 00000000000934f2 __float128 0f SECT 01 0000 [.text] AMDVISAMUGPCOMChannel::AMDVISAMUGPCOMChannel() 0000000000093420 __float128 0f SECT 01 0000 [.text] AMDVISAMUGPCOMChannel::~AMDVISAMUGPCOMChannel() 0000000000093416 __float128 0f SECT 01 0000 [.text] AMDVISAMUGPCOMChannel::~AMDVISAMUGPCOMChannel() 000000000009340c __float128 0f SECT 01 0000 [.text] AMDVISAMUGPCOMChannel::~AMDVISAMUGPCOMChannel() 000000000052e8f0 __float128 0f SECT 0a 0000 [__DATA.__common] AMDCIPM4ComputeChannel::gMetaClass 00000000003b86b8 __float128 0f SECT 08 0000 [.const_data] AMDCIPM4ComputeChannel::superClass 000000000008354e __float128 0f SECT 01 0000 [.text] AMDCIPM4ComputeChannel::writeDataCmdPacket(_PM4_MEC_WRITE_DATA*, MEC_WRITE_DATA_dst_sel_enum, MEC_WRITE_DATA_addr_incr_enum, MEC_WRITE_DATA_wr_confirm_enum, MEC_WRITE_DATA_cache_policy_enum, unsigned long long, unsigned int const*, unsigned int) 000000000008360a __float128 0f SECT 01 0000 [.text] AMDCIPM4ComputeChannel::acquireMemCmdPacket(_PM4_MEC_ACQUIRE_MEM*, unsigned int, unsigned long long, unsigned long long, unsigned short) 0000000000083c4e __float128 0f SECT 01 0000 [.text] AMDCIPM4ComputeChannel::eventWriteCmdPacket(_PM4_MEC_EVENT_WRITE*, MEC_EVENT_WRITE_event_index_enum, unsigned int) 00000000000839d2 __float128 0f SECT 01 0000 [.text] AMDCIPM4ComputeChannel::releaseMemCmdPacket(_PM4_MEC_RELEASE_MEM*, unsigned int, MEC_RELEASE_MEM_event_index_enum, MEC_RELEASE_MEM_cache_policy_enum, MEC_RELEASE_MEM_dst_sel_enum, MEC_RELEASE_MEM_int_sel_enum, MEC_RELEASE_MEM_data_sel_enum, unsigned long long, unsigned long long) 0000000000083ba6 __float128 0f SECT 01 0000 [.text] AMDCIPM4ComputeChannel::releaseSubmitFrames() 0000000000083a9e __float128 0f SECT 01 0000 [.text] AMDCIPM4ComputeChannel::initializeSubmitFrames() 0000000000083be2 __float128 0f SECT 01 0000 [.text] AMDCIPM4ComputeChannel::timeStampInterruptType() 0000000000083c30 __float128 0f SECT 01 0000 [.text] AMDCIPM4ComputeChannel::writeEventWriteCommand(unsigned int*, unsigned int, unsigned int) 00000000000837d0 __float128 0f SECT 01 0000 [.text] AMDCIPM4ComputeChannel::indirectBufferCmdPacket(_PM4_MEC_INDIRECT_BUFFER*, unsigned long long, unsigned int, unsigned int, bool) 0000000000083c12 __float128 0f SECT 01 0000 [.text] AMDCIPM4ComputeChannel::writeSurfaceSyncCommand(unsigned int*, unsigned int, unsigned long long, unsigned long long, unsigned int) 0000000000083ae0 __float128 0f SECT 01 0000 [.text] AMDCIPM4ComputeChannel::initializeTimestampFrame() 0000000000083c6e __float128 0f SECT 01 0000 [.text] AMDCIPM4ComputeChannel::writeEventWriteEOPCommand(unsigned int*, unsigned int, unsigned int, unsigned long long, unsigned int, unsigned int, unsigned long long) 0000000000083698 __float128 0f SECT 01 0000 [.text] AMDCIPM4ComputeChannel::commitIndirectCommandBuffer(AMD_SUBMIT_COMMAND_BUFFER_INFO*) 0000000000083866 __float128 0f SECT 01 0000 [.text] AMDCIPM4ComputeChannel::initializeIndirectCommandBufferFrame() 0000000000083410 __float128 0f SECT 01 0000 [.text] AMDCIPM4ComputeChannel::writeFlushAndInvalidateDestinationCachesCommands() 00000000000833fe __float128 0f SECT 01 0000 [.text] AMDCIPM4ComputeChannel::free() 00000000000833e2 __float128 0f SECT 01 0000 [.text] AMDCIPM4ComputeChannel::init(int, AMDRadeonX4000_IAMDHWInterface*, AMDRadeonX4000_IAMDHWEngine*, AMDRadeonX4000_IAMDHWRing*, char const*) 0000000000083250 __float128 0f SECT 01 0000 [.text] AMDCIPM4ComputeChannel::MetaClass::MetaClass() 0000000000083310 __float128 0f SECT 01 0000 [.text] AMDCIPM4ComputeChannel::MetaClass::MetaClass() 00000000003b86b0 __float128 0f SECT 08 0000 [.const_data] AMDCIPM4ComputeChannel::metaClass 00000000000832ac __float128 0f SECT 01 0000 [.text] AMDCIPM4ComputeChannel::AMDCIPM4ComputeChannel(OSMetaClass const*) 0000000000083382 __float128 0f SECT 01 0000 [.text] AMDCIPM4ComputeChannel::AMDCIPM4ComputeChannel() 000000000008328c __float128 0f SECT 01 0000 [.text] AMDCIPM4ComputeChannel::AMDCIPM4ComputeChannel(OSMetaClass const*) 00000000000833b2 __float128 0f SECT 01 0000 [.text] AMDCIPM4ComputeChannel::AMDCIPM4ComputeChannel() 00000000000832e0 __float128 0f SECT 01 0000 [.text] AMDCIPM4ComputeChannel::~AMDCIPM4ComputeChannel() 00000000000832d6 __float128 0f SECT 01 0000 [.text] AMDCIPM4ComputeChannel::~AMDCIPM4ComputeChannel() 00000000000832cc __float128 0f SECT 01 0000 [.text] AMDCIPM4ComputeChannel::~AMDCIPM4ComputeChannel() 000000000052d5e0 __float128 0f SECT 0a 0000 [__DATA.__common] AMDSIAtomicBlitManager::gMetaClass 00000000003965d8 __float128 0f SECT 08 0000 [.const_data] AMDSIAtomicBlitManager::superClass 0000000000029cdc __float128 0f SECT 01 0000 [.text] AMDSIAtomicBlitManager::profilingWriteEnd(unsigned int*, unsigned int, LARGE_INTEGER, _UBM_ENGINE) 0000000000029c82 __float128 0f SECT 01 0000 [.text] AMDSIAtomicBlitManager::profilingWriteStart(unsigned int*, unsigned int, LARGE_INTEGER, _UBM_ENGINE) 0000000000029d34 __float128 0f SECT 01 0000 [.text] AMDSIAtomicBlitManager::handlePreBlitOptions(ABM_OPTIONS const*, AMDRadeonX4000_AMDAtomicBlitManager::CommandBufferInfo&) 0000000000029e5e __float128 0f SECT 01 0000 [.text] AMDSIAtomicBlitManager::handlePostBlitOptions(ABM_OPTIONS const*, AMDRadeonX4000_AMDAtomicBlitManager::CommandBufferInfo&) 0000000000029af0 __float128 0f SECT 01 0000 [.text] AMDSIAtomicBlitManager::MetaClass::MetaClass() 0000000000029bb0 __float128 0f SECT 01 0000 [.text] AMDSIAtomicBlitManager::MetaClass::MetaClass() 00000000003965d0 __float128 0f SECT 08 0000 [.const_data] AMDSIAtomicBlitManager::metaClass 0000000000029b4c __float128 0f SECT 01 0000 [.text] AMDSIAtomicBlitManager::AMDSIAtomicBlitManager(OSMetaClass const*) 0000000000029c22 __float128 0f SECT 01 0000 [.text] AMDSIAtomicBlitManager::AMDSIAtomicBlitManager() 0000000000029b2c __float128 0f SECT 01 0000 [.text] AMDSIAtomicBlitManager::AMDSIAtomicBlitManager(OSMetaClass const*) 0000000000029c52 __float128 0f SECT 01 0000 [.text] AMDSIAtomicBlitManager::AMDSIAtomicBlitManager() 0000000000029b80 __float128 0f SECT 01 0000 [.text] AMDSIAtomicBlitManager::~AMDSIAtomicBlitManager() 0000000000029b76 __float128 0f SECT 01 0000 [.text] AMDSIAtomicBlitManager::~AMDSIAtomicBlitManager() 0000000000029b6c __float128 0f SECT 01 0000 [.text] AMDSIAtomicBlitManager::~AMDSIAtomicBlitManager() 000000000052e4e0 __float128 0f SECT 0a 0000 [__DATA.__common] AMDSIPM4ComputeChannel::gMetaClass 00000000003b2028 __float128 0f SECT 08 0000 [.const_data] AMDSIPM4ComputeChannel::superClass 00000000000745e4 __float128 0f SECT 01 0000 [.text] AMDSIPM4ComputeChannel::releaseSubmitFrames() 0000000000074626 __float128 0f SECT 01 0000 [.text] AMDSIPM4ComputeChannel::resetPerFramePacket() 0000000000074620 __float128 0f SECT 01 0000 [.text] AMDSIPM4ComputeChannel::setupPerFramePacket(unsigned int, unsigned int, unsigned int, unsigned int) 0000000000074658 __float128 0f SECT 01 0000 [.text] AMDSIPM4ComputeChannel::getIBAlignmentFactor() 000000000007462c __float128 0f SECT 01 0000 [.text] AMDSIPM4ComputeChannel::writeProfilingCommand(unsigned int*, unsigned long long, unsigned int, bool) 0000000000074534 __float128 0f SECT 01 0000 [.text] AMDSIPM4ComputeChannel::initializeSubmitFrames() 0000000000074634 __float128 0f SECT 01 0000 [.text] AMDSIPM4ComputeChannel::timeStampInterruptType() 0000000000074576 __float128 0f SECT 01 0000 [.text] AMDSIPM4ComputeChannel::initializeTimestampFrame() 0000000000074286 __float128 0f SECT 01 0000 [.text] AMDSIPM4ComputeChannel::commitIndirectCommandBuffer(AMD_SUBMIT_COMMAND_BUFFER_INFO*) 00000000000741d8 __float128 0f SECT 01 0000 [.text] AMDSIPM4ComputeChannel::enableScratchRegisterWriteback() 00000000000741de __float128 0f SECT 01 0000 [.text] AMDSIPM4ComputeChannel::disableScratchRegisterWriteback() 00000000000743f4 __float128 0f SECT 01 0000 [.text] AMDSIPM4ComputeChannel::initializeIndirectCommandBufferFrame() 00000000000741e4 __float128 0f SECT 01 0000 [.text] AMDSIPM4ComputeChannel::writeFlushAndInvalidateDestinationCachesCommands() 00000000000740e2 __float128 0f SECT 01 0000 [.text] AMDSIPM4ComputeChannel::init(int, AMDRadeonX4000_IAMDHWInterface*, AMDRadeonX4000_IAMDHWEngine*, AMDRadeonX4000_IAMDHWRing*, char const*) 00000000000740fe __float128 0f SECT 01 0000 [.text] AMDSIPM4ComputeChannel::isIdle() 0000000000073f50 __float128 0f SECT 01 0000 [.text] AMDSIPM4ComputeChannel::MetaClass::MetaClass() 0000000000074010 __float128 0f SECT 01 0000 [.text] AMDSIPM4ComputeChannel::MetaClass::MetaClass() 00000000003b2020 __float128 0f SECT 08 0000 [.const_data] AMDSIPM4ComputeChannel::metaClass 0000000000073fac __float128 0f SECT 01 0000 [.text] AMDSIPM4ComputeChannel::AMDSIPM4ComputeChannel(OSMetaClass const*) 0000000000074082 __float128 0f SECT 01 0000 [.text] AMDSIPM4ComputeChannel::AMDSIPM4ComputeChannel() 0000000000073f8c __float128 0f SECT 01 0000 [.text] AMDSIPM4ComputeChannel::AMDSIPM4ComputeChannel(OSMetaClass const*) 00000000000740b2 __float128 0f SECT 01 0000 [.text] AMDSIPM4ComputeChannel::AMDSIPM4ComputeChannel() 0000000000073fe0 __float128 0f SECT 01 0000 [.text] AMDSIPM4ComputeChannel::~AMDSIPM4ComputeChannel() 0000000000073fd6 __float128 0f SECT 01 0000 [.text] AMDSIPM4ComputeChannel::~AMDSIPM4ComputeChannel() 0000000000073fcc __float128 0f SECT 01 0000 [.text] AMDSIPM4ComputeChannel::~AMDSIPM4ComputeChannel() 000000000052eb98 __float128 0f SECT 0a 0000 [__DATA.__common] AMDVIPM4ComputeChannel::gMetaClass 00000000003bc728 __float128 0f SECT 08 0000 [.const_data] AMDVIPM4ComputeChannel::superClass 000000000009190e __float128 0f SECT 01 0000 [.text] AMDVIPM4ComputeChannel::writeDataCmdPacket(PM4_MEC_WRITE_DATA*, MEC_WRITE_DATA_dst_sel_enum, MEC_WRITE_DATA_addr_incr_enum, MEC_WRITE_DATA_wr_confirm_enum, MEC_WRITE_DATA_cache_policy_enum, unsigned long long, unsigned int const*, unsigned int) 0000000000091a06 __float128 0f SECT 01 0000 [.text] AMDVIPM4ComputeChannel::acquireMemCmdPacket(PM4_MEC_ACQUIRE_MEM*, unsigned int, unsigned long long, unsigned long long, unsigned short) 00000000000920d6 __float128 0f SECT 01 0000 [.text] AMDVIPM4ComputeChannel::eventWriteCmdPacket(PM4_MEC_EVENT_WRITE*, MEC_EVENT_WRITE_event_index_enum, unsigned int) 0000000000091dce __float128 0f SECT 01 0000 [.text] AMDVIPM4ComputeChannel::releaseMemCmdPacket(PM4_MEC_RELEASE_MEM*, unsigned int, MEC_RELEASE_MEM_event_index_enum, MEC_RELEASE_MEM_cache_policy_enum, MEC_RELEASE_MEM_dst_sel_enum, MEC_RELEASE_MEM_int_sel_enum, MEC_RELEASE_MEM_data_sel_enum, unsigned long long, unsigned long long) 0000000000091fa2 __float128 0f SECT 01 0000 [.text] AMDVIPM4ComputeChannel::releaseSubmitFrames() 0000000000091e9a __float128 0f SECT 01 0000 [.text] AMDVIPM4ComputeChannel::initializeSubmitFrames() 0000000000091fde __float128 0f SECT 01 0000 [.text] AMDVIPM4ComputeChannel::timeStampInterruptType() 00000000000920b8 __float128 0f SECT 01 0000 [.text] AMDVIPM4ComputeChannel::writeEventWriteCommand(unsigned int*, unsigned int, unsigned int) 0000000000091bcc __float128 0f SECT 01 0000 [.text] AMDVIPM4ComputeChannel::indirectBufferCmdPacket(PM4_MEC_INDIRECT_BUFFER*, unsigned long long, unsigned int, unsigned int, bool) 000000000009209a __float128 0f SECT 01 0000 [.text] AMDVIPM4ComputeChannel::writeSurfaceSyncCommand(unsigned int*, unsigned int, unsigned long long, unsigned long long, unsigned int) 0000000000091edc __float128 0f SECT 01 0000 [.text] AMDVIPM4ComputeChannel::initializeTimestampFrame() 00000000000920f6 __float128 0f SECT 01 0000 [.text] AMDVIPM4ComputeChannel::writeEventWriteEOPCommand(unsigned int*, unsigned int, unsigned int, unsigned long long, unsigned int, unsigned int, unsigned long long) 0000000000091a94 __float128 0f SECT 01 0000 [.text] AMDVIPM4ComputeChannel::commitIndirectCommandBuffer(AMD_SUBMIT_COMMAND_BUFFER_INFO*) 0000000000091c62 __float128 0f SECT 01 0000 [.text] AMDVIPM4ComputeChannel::initializeIndirectCommandBufferFrame() 00000000000917d0 __float128 0f SECT 01 0000 [.text] AMDVIPM4ComputeChannel::writeFlushAndInvalidateDestinationCachesCommands() 00000000000917be __float128 0f SECT 01 0000 [.text] AMDVIPM4ComputeChannel::free() 00000000000917a2 __float128 0f SECT 01 0000 [.text] AMDVIPM4ComputeChannel::init(int, AMDRadeonX4000_IAMDHWInterface*, AMDRadeonX4000_IAMDHWEngine*, AMDRadeonX4000_IAMDHWRing*, char const*) 0000000000091610 __float128 0f SECT 01 0000 [.text] AMDVIPM4ComputeChannel::MetaClass::MetaClass() 00000000000916d0 __float128 0f SECT 01 0000 [.text] AMDVIPM4ComputeChannel::MetaClass::MetaClass() 00000000003bc720 __float128 0f SECT 08 0000 [.const_data] AMDVIPM4ComputeChannel::metaClass 000000000009166c __float128 0f SECT 01 0000 [.text] AMDVIPM4ComputeChannel::AMDVIPM4ComputeChannel(OSMetaClass const*) 0000000000091742 __float128 0f SECT 01 0000 [.text] AMDVIPM4ComputeChannel::AMDVIPM4ComputeChannel() 000000000009164c __float128 0f SECT 01 0000 [.text] AMDVIPM4ComputeChannel::AMDVIPM4ComputeChannel(OSMetaClass const*) 0000000000091772 __float128 0f SECT 01 0000 [.text] AMDVIPM4ComputeChannel::AMDVIPM4ComputeChannel() 00000000000916a0 __float128 0f SECT 01 0000 [.text] AMDVIPM4ComputeChannel::~AMDVIPM4ComputeChannel() 0000000000091696 __float128 0f SECT 01 0000 [.text] AMDVIPM4ComputeChannel::~AMDVIPM4ComputeChannel() 000000000009168c __float128 0f SECT 01 0000 [.text] AMDVIPM4ComputeChannel::~AMDVIPM4ComputeChannel() 000000000052e620 __float128 0f SECT 0a 0000 [__DATA.__common] AMDCIPM4CommandsUtility::gMetaClass 00000000003b46a8 __float128 0f SECT 08 0000 [.const_data] AMDCIPM4CommandsUtility::superClass 000000000007abc2 __float128 0f SECT 01 0000 [.text] AMDCIPM4CommandsUtility::buildPM4Type0Cmd(unsigned int*, unsigned int, unsigned int) 000000000007ae74 __float128 0f SECT 01 0000 [.text] AMDCIPM4CommandsUtility::buildMemWriteCommand(unsigned int*, unsigned long long, unsigned int, unsigned int) 000000000007ae7c __float128 0f SECT 01 0000 [.text] AMDCIPM4CommandsUtility::buildPFPSyncMECommand(unsigned int*) 000000000007abd2 __float128 0f SECT 01 0000 [.text] AMDCIPM4CommandsUtility::buildWaitRegMemCommand(unsigned int*, unsigned int, unsigned int, unsigned int, unsigned int, unsigned int, unsigned int) 000000000007abca __float128 0f SECT 01 0000 [.text] AMDCIPM4CommandsUtility::writePM4Type0CmdToRing(AMDRadeonX4000_IAMDHWRing*, unsigned int, unsigned int) 000000000007ac54 __float128 0f SECT 01 0000 [.text] AMDCIPM4CommandsUtility::buildSurfaceSyncCommand(unsigned int*, unsigned int, unsigned int) 000000000007ad1c __float128 0f SECT 01 0000 [.text] AMDCIPM4CommandsUtility::buildEventWriteEOPCommand(unsigned int*, unsigned int, unsigned long long, unsigned long long, unsigned int, bool, unsigned int) 000000000007add6 __float128 0f SECT 01 0000 [.text] AMDCIPM4CommandsUtility::buildIndirectBufferCommand(unsigned int*, unsigned long long, unsigned int, _eAMD_INDIRECT_BUFFER_TYPE, unsigned int, bool, unsigned int) 000000000007aca4 __float128 0f SECT 01 0000 [.text] AMDCIPM4CommandsUtility::writeSurfaceSyncCommandToRing(AMDRadeonX4000_IAMDHWRing*, unsigned int) 000000000007aa30 __float128 0f SECT 01 0000 [.text] AMDCIPM4CommandsUtility::MetaClass::MetaClass() 000000000007aaf0 __float128 0f SECT 01 0000 [.text] AMDCIPM4CommandsUtility::MetaClass::MetaClass() 00000000003b46a0 __float128 0f SECT 08 0000 [.const_data] AMDCIPM4CommandsUtility::metaClass 000000000007aa8c __float128 0f SECT 01 0000 [.text] AMDCIPM4CommandsUtility::AMDCIPM4CommandsUtility(OSMetaClass const*) 000000000007ab62 __float128 0f SECT 01 0000 [.text] AMDCIPM4CommandsUtility::AMDCIPM4CommandsUtility() 000000000007aa6c __float128 0f SECT 01 0000 [.text] AMDCIPM4CommandsUtility::AMDCIPM4CommandsUtility(OSMetaClass const*) 000000000007ab92 __float128 0f SECT 01 0000 [.text] AMDCIPM4CommandsUtility::AMDCIPM4CommandsUtility() 000000000007aac0 __float128 0f SECT 01 0000 [.text] AMDCIPM4CommandsUtility::~AMDCIPM4CommandsUtility() 000000000007aab6 __float128 0f SECT 01 0000 [.text] AMDCIPM4CommandsUtility::~AMDCIPM4CommandsUtility() 000000000007aaac __float128 0f SECT 01 0000 [.text] AMDCIPM4CommandsUtility::~AMDCIPM4CommandsUtility() 0000000000059476 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHWVMM::allocVMPTB(GLKMemoryElement*) 0000000000059590 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHWVMM::assignVMID(AMDRadeonX4000_IAMDHWVMContext*, unsigned int&, AMDRadeonX4000_IAMDHWChannel*, IOAccelEvent**, bool*) 000000000052de50 __float128 0f SECT 0a 0000 [__DATA.__common] AMDRadeonX4000_AMDHWVMM::gMetaClass 00000000003a7c28 __float128 0f SECT 08 0000 [.const_data] AMDRadeonX4000_AMDHWVMM::superClass 000000000005978e __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHWVMM::getCurrentVMID(AMDRadeonX4000_IAMDHWVMContext*) 00000000000597d0 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHWVMM::createVMContext() 0000000000059842 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHWVMM::releaseVMContext(AMDRadeonX4000_IAMDHWVMContext*) 00000000000597b0 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHWVMM::isInVMReservedPool(unsigned long long) 0000000000059338 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHWVMM::removeFromVMIDList(AMDRadeonX4000_IAMDHWVMContext*) 0000000000058f84 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHWVMM::setVirtualSpaceReady(bool) 0000000000058fcc __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHWVMM::setMemoryAllocationsEnabled(bool) 0000000000058eb0 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHWVMM::free() 0000000000058d3a __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHWVMM::init(AMDRadeonX4000_IAMDHWInterface*) 0000000000059420 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHWVMM::freeVMPD(GLKMemoryElement*) 0000000000058c60 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHWVMM::MetaClass::MetaClass() 0000000000058d00 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHWVMM::MetaClass::MetaClass() 000000000005935c __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHWVMM::allocVMPD(GLKMemoryElement*) 000000000005953a __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHWVMM::freeVMPTB(GLKMemoryElement*) 00000000003a7c20 __float128 0f SECT 08 0000 [.const_data] AMDRadeonX4000_AMDHWVMM::metaClass 0000000000058c9c __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHWVMM::AMDRadeonX4000_AMDHWVMM(OSMetaClass const*) 0000000000058cd0 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHWVMM::~AMDRadeonX4000_AMDHWVMM() 0000000000058cc6 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHWVMM::~AMDRadeonX4000_AMDHWVMM() 0000000000058cbc __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHWVMM::~AMDRadeonX4000_AMDHWVMM() 000000000052f110 __float128 0f SECT 0a 0000 [__DATA.__common] AMDRadeonX4000_AMDSIDRM::gMetaClass 00000000003c3a88 __float128 0f SECT 08 0000 [.const_data] AMDRadeonX4000_AMDSIDRM::superClass 00000000001284a2 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDSIDRM::writeAESCmd(unsigned int*, unsigned int*, unsigned long long, unsigned long long, unsigned int, _DRMDMA_AES*, unsigned int) 00000000001288e8 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDSIDRM::writeCBCCmds(unsigned int*, unsigned int, unsigned long long, unsigned long long, unsigned int, _DRMDMA_AES*, bool) 00000000001286cc __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDSIDRM::writeCTRCmds(unsigned int*, unsigned int, unsigned long long, unsigned long long, unsigned int, _DRMDMA_AES*, bool) 0000000000128b04 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDSIDRM::writeCBCCTRCmds(unsigned int*, unsigned int, unsigned long long, unsigned long long, unsigned int, _DRMDMA_AES*) 0000000000128490 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDSIDRM::free() 0000000000128462 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDSIDRM::init() 00000000001282d0 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDSIDRM::MetaClass::MetaClass() 0000000000128390 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDSIDRM::MetaClass::MetaClass() 00000000003c3a80 __float128 0f SECT 08 0000 [.const_data] AMDRadeonX4000_AMDSIDRM::metaClass 000000000012832c __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDSIDRM::AMDRadeonX4000_AMDSIDRM(OSMetaClass const*) 0000000000128402 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDSIDRM::AMDRadeonX4000_AMDSIDRM() 000000000012830c __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDSIDRM::AMDRadeonX4000_AMDSIDRM(OSMetaClass const*) 0000000000128432 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDSIDRM::AMDRadeonX4000_AMDSIDRM() 0000000000128360 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDSIDRM::~AMDRadeonX4000_AMDSIDRM() 0000000000128356 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDSIDRM::~AMDRadeonX4000_AMDSIDRM() 000000000012834c __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDSIDRM::~AMDRadeonX4000_AMDSIDRM() 000000000052f138 __float128 0f SECT 0a 0000 [__DATA.__common] AMDRadeonX4000_AMDSISPU::gMetaClass 0000000000128eda __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDSISPU::getAppSize(_AMD_SPU_APP_TYPE, unsigned int*, unsigned int*) 00000000003c3ce8 __float128 0f SECT 08 0000 [.const_data] AMDRadeonX4000_AMDSISPU::superClass 00000000001290f4 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDSISPU::writeAppCmd(_SML_SPU_CMD*, bool) 000000000012906a __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDSISPU::writeInitCmd(_SML_SPU_CMD*) 000000000012922c __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDSISPU::writeAppMsgCmd(_SML_SPU_CMD*) 0000000000128ecc __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDSISPU::getFeedBackSize(unsigned int*) 0000000000128e66 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDSISPU::getKernelMemReq(unsigned int*, unsigned int*, unsigned int*) 0000000000128e54 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDSISPU::free() 0000000000128e42 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDSISPU::init() 000000000012902c __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDSISPU::getApp(_AMD_SPU_APP_TYPE, unsigned int*, unsigned int*) 0000000000128cb0 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDSISPU::MetaClass::MetaClass() 0000000000128d70 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDSISPU::MetaClass::MetaClass() 0000000000128f02 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDSISPU::getAppMsg(_AMD_SPU_MSG_TYPE) 0000000000128e80 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDSISPU::getKernel(unsigned int*, unsigned int*, unsigned int*, unsigned int*) 00000000003c3ce0 __float128 0f SECT 08 0000 [.const_data] AMDRadeonX4000_AMDSISPU::metaClass 0000000000128d0c __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDSISPU::AMDRadeonX4000_AMDSISPU(OSMetaClass const*) 0000000000128de2 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDSISPU::AMDRadeonX4000_AMDSISPU() 0000000000128cec __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDSISPU::AMDRadeonX4000_AMDSISPU(OSMetaClass const*) 0000000000128e12 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDSISPU::AMDRadeonX4000_AMDSISPU() 0000000000128d40 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDSISPU::~AMDRadeonX4000_AMDSISPU() 0000000000128d36 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDSISPU::~AMDRadeonX4000_AMDSISPU() 0000000000128d2c __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDSISPU::~AMDRadeonX4000_AMDSISPU() 000000000052f160 __float128 0f SECT 0a 0000 [__DATA.__common] AMDRadeonX4000_AMDSIVCE::gMetaClass 0000000000129630 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDSIVCE::roundupVal(unsigned int, unsigned int) 00000000003c3f78 __float128 0f SECT 08 0000 [.const_data] AMDRadeonX4000_AMDSIVCE::superClass 00000000001295fc __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDSIVCE::getFWMemReq(unsigned int*, unsigned int*) 0000000000129660 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDSIVCE::getFWCacheInfo(_SML_VCEFWINFO*) 000000000012964c __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDSIVCE::getFWMemConfig(unsigned int*, unsigned int*) 00000000001295ea __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDSIVCE::free() 0000000000129582 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDSIVCE::init(unsigned int) 000000000012969c __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDSIVCE::getFW(_SML_VCEFW*) 00000000001293f0 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDSIVCE::MetaClass::MetaClass() 00000000001294b0 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDSIVCE::MetaClass::MetaClass() 00000000003c3f70 __float128 0f SECT 08 0000 [.const_data] AMDRadeonX4000_AMDSIVCE::metaClass 000000000012944c __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDSIVCE::AMDRadeonX4000_AMDSIVCE(OSMetaClass const*) 0000000000129522 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDSIVCE::AMDRadeonX4000_AMDSIVCE() 000000000012942c __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDSIVCE::AMDRadeonX4000_AMDSIVCE(OSMetaClass const*) 0000000000129552 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDSIVCE::AMDRadeonX4000_AMDSIVCE() 0000000000129480 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDSIVCE::~AMDRadeonX4000_AMDSIVCE() 0000000000129476 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDSIVCE::~AMDRadeonX4000_AMDSIVCE() 000000000012946c __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDSIVCE::~AMDRadeonX4000_AMDSIVCE() 000000000052f278 __float128 0f SECT 0a 0000 [__DATA.__common] AMDRadeonX4000_AMDUVDVI::gMetaClass 00000000003c52a8 __float128 0f SECT 08 0000 [.const_data] AMDRadeonX4000_AMDUVDVI::superClass 000000000012b8d2 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDUVDVI::init(unsigned int) 000000000012b740 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDUVDVI::MetaClass::MetaClass() 000000000012b800 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDUVDVI::MetaClass::MetaClass() 00000000003c52a0 __float128 0f SECT 08 0000 [.const_data] AMDRadeonX4000_AMDUVDVI::metaClass 000000000012b79c __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDUVDVI::AMDRadeonX4000_AMDUVDVI(OSMetaClass const*) 000000000012b872 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDUVDVI::AMDRadeonX4000_AMDUVDVI() 000000000012b77c __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDUVDVI::AMDRadeonX4000_AMDUVDVI(OSMetaClass const*) 000000000012b8a2 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDUVDVI::AMDRadeonX4000_AMDUVDVI() 000000000012b7d0 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDUVDVI::~AMDRadeonX4000_AMDUVDVI() 000000000012b7c6 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDUVDVI::~AMDRadeonX4000_AMDUVDVI() 000000000012b7bc __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDUVDVI::~AMDRadeonX4000_AMDUVDVI() 000000000052f2a0 __float128 0f SECT 0a 0000 [__DATA.__common] AMDRadeonX4000_AMDVIDRM::gMetaClass 00000000003c5528 __float128 0f SECT 08 0000 [.const_data] AMDRadeonX4000_AMDVIDRM::superClass 000000000012bb62 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDVIDRM::writeAESCmd(unsigned int*, unsigned int*, unsigned long long, unsigned long long, unsigned int, _DRMDMA_AES*, unsigned int) 000000000012bfe4 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDVIDRM::writeCBCCmds(unsigned int*, unsigned int, unsigned long long, unsigned long long, unsigned int, _DRMDMA_AES*, bool) 000000000012bd72 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDVIDRM::writeCTRCmds(unsigned int*, unsigned int, unsigned long long, unsigned long long, unsigned int, _DRMDMA_AES*, bool) 000000000012c26a __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDVIDRM::writeCBCCTRCmds(unsigned int*, unsigned int, unsigned long long, unsigned long long, unsigned int, _DRMDMA_AES*) 000000000012bb50 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDVIDRM::free() 000000000012bb22 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDVIDRM::init() 000000000012b990 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDVIDRM::MetaClass::MetaClass() 000000000012ba50 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDVIDRM::MetaClass::MetaClass() 00000000003c5520 __float128 0f SECT 08 0000 [.const_data] AMDRadeonX4000_AMDVIDRM::metaClass 000000000012b9ec __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDVIDRM::AMDRadeonX4000_AMDVIDRM(OSMetaClass const*) 000000000012bac2 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDVIDRM::AMDRadeonX4000_AMDVIDRM() 000000000012b9cc __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDVIDRM::AMDRadeonX4000_AMDVIDRM(OSMetaClass const*) 000000000012baf2 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDVIDRM::AMDRadeonX4000_AMDVIDRM() 000000000012ba20 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDVIDRM::~AMDRadeonX4000_AMDVIDRM() 000000000012ba16 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDVIDRM::~AMDRadeonX4000_AMDVIDRM() 000000000012ba0c __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDVIDRM::~AMDRadeonX4000_AMDVIDRM() 000000000052f2c8 __float128 0f SECT 0a 0000 [__DATA.__common] AMDRadeonX4000_AMDVISPU::gMetaClass 00000000003c5788 __float128 0f SECT 08 0000 [.const_data] AMDRadeonX4000_AMDVISPU::superClass 000000000012c5b6 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDVISPU::getKernelMemReq(unsigned int*, unsigned int*, unsigned int*) 000000000012c5a4 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDVISPU::free() 000000000012c592 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDVISPU::init() 000000000012c400 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDVISPU::MetaClass::MetaClass() 000000000012c4c0 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDVISPU::MetaClass::MetaClass() 000000000012c5d0 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDVISPU::getKernel(unsigned int*, unsigned int*, unsigned int*, unsigned int*) 00000000003c5780 __float128 0f SECT 08 0000 [.const_data] AMDRadeonX4000_AMDVISPU::metaClass 000000000012c45c __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDVISPU::AMDRadeonX4000_AMDVISPU(OSMetaClass const*) 000000000012c532 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDVISPU::AMDRadeonX4000_AMDVISPU() 000000000012c43c __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDVISPU::AMDRadeonX4000_AMDVISPU(OSMetaClass const*) 000000000012c562 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDVISPU::AMDRadeonX4000_AMDVISPU() 000000000012c490 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDVISPU::~AMDRadeonX4000_AMDVISPU() 000000000012c486 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDVISPU::~AMDRadeonX4000_AMDVISPU() 000000000012c47c __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDVISPU::~AMDRadeonX4000_AMDVISPU() 000000000052f2f0 __float128 0f SECT 0a 0000 [__DATA.__common] AMDRadeonX4000_AMDVIVCE::gMetaClass 00000000003c5a18 __float128 0f SECT 08 0000 [.const_data] AMDRadeonX4000_AMDVIVCE::superClass 000000000012c874 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDVIVCE::getFWMemReq(unsigned int*, unsigned int*) 000000000012c8b2 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDVIVCE::getFWCacheInfo(_SML_VCEFWINFO*) 000000000012c89e __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDVIVCE::getFWMemConfig(unsigned int*, unsigned int*) 000000000012c862 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDVIVCE::free() 000000000012c822 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDVIVCE::init(unsigned int) 000000000012c690 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDVIVCE::MetaClass::MetaClass() 000000000012c750 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDVIVCE::MetaClass::MetaClass() 00000000003c5a10 __float128 0f SECT 08 0000 [.const_data] AMDRadeonX4000_AMDVIVCE::metaClass 000000000012c6ec __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDVIVCE::AMDRadeonX4000_AMDVIVCE(OSMetaClass const*) 000000000012c7c2 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDVIVCE::AMDRadeonX4000_AMDVIVCE() 000000000012c6cc __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDVIVCE::AMDRadeonX4000_AMDVIVCE(OSMetaClass const*) 000000000012c7f2 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDVIVCE::AMDRadeonX4000_AMDVIVCE() 000000000012c720 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDVIVCE::~AMDRadeonX4000_AMDVIVCE() 000000000012c716 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDVIVCE::~AMDRadeonX4000_AMDVIVCE() 000000000012c70c __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDVIVCE::~AMDRadeonX4000_AMDVIVCE() 000000000052eb48 __float128 0f SECT 0a 0000 [__DATA.__common] AMDVIPM4CommandsUtility::gMetaClass 00000000003bc0d8 __float128 0f SECT 08 0000 [.const_data] AMDVIPM4CommandsUtility::superClass 000000000008f0a4 __float128 0f SECT 01 0000 [.text] AMDVIPM4CommandsUtility::buildPM4Type0Cmd(unsigned int*, unsigned int, unsigned int) 000000000008f284 __float128 0f SECT 01 0000 [.text] AMDVIPM4CommandsUtility::buildMemWriteCommand(unsigned int*, unsigned long long, unsigned int, unsigned int) 000000000008f28c __float128 0f SECT 01 0000 [.text] AMDVIPM4CommandsUtility::buildPFPSyncMECommand(unsigned int*) 000000000008f0b4 __float128 0f SECT 01 0000 [.text] AMDVIPM4CommandsUtility::buildWaitRegMemCommand(unsigned int*, unsigned int, unsigned int, unsigned int, unsigned int, unsigned int, unsigned int) 000000000008f0ac __float128 0f SECT 01 0000 [.text] AMDVIPM4CommandsUtility::writePM4Type0CmdToRing(AMDRadeonX4000_IAMDHWRing*, unsigned int, unsigned int) 000000000008f136 __float128 0f SECT 01 0000 [.text] AMDVIPM4CommandsUtility::buildSurfaceSyncCommand(unsigned int*, unsigned int, unsigned int) 000000000008f146 __float128 0f SECT 01 0000 [.text] AMDVIPM4CommandsUtility::buildEventWriteEOPCommand(unsigned int*, unsigned int, unsigned long long, unsigned long long, unsigned int, bool, unsigned int) 000000000008f1f2 __float128 0f SECT 01 0000 [.text] AMDVIPM4CommandsUtility::buildIndirectBufferCommand(unsigned int*, unsigned long long, unsigned int, _eAMD_INDIRECT_BUFFER_TYPE, unsigned int, bool, unsigned int) 000000000008f13e __float128 0f SECT 01 0000 [.text] AMDVIPM4CommandsUtility::writeSurfaceSyncCommandToRing(AMDRadeonX4000_IAMDHWRing*, unsigned int) 000000000008f092 __float128 0f SECT 01 0000 [.text] AMDVIPM4CommandsUtility::init() 000000000008ef00 __float128 0f SECT 01 0000 [.text] AMDVIPM4CommandsUtility::MetaClass::MetaClass() 000000000008efc0 __float128 0f SECT 01 0000 [.text] AMDVIPM4CommandsUtility::MetaClass::MetaClass() 00000000003bc0d0 __float128 0f SECT 08 0000 [.const_data] AMDVIPM4CommandsUtility::metaClass 000000000008ef5c __float128 0f SECT 01 0000 [.text] AMDVIPM4CommandsUtility::AMDVIPM4CommandsUtility(OSMetaClass const*) 000000000008f032 __float128 0f SECT 01 0000 [.text] AMDVIPM4CommandsUtility::AMDVIPM4CommandsUtility() 000000000008ef3c __float128 0f SECT 01 0000 [.text] AMDVIPM4CommandsUtility::AMDVIPM4CommandsUtility(OSMetaClass const*) 000000000008f062 __float128 0f SECT 01 0000 [.text] AMDVIPM4CommandsUtility::AMDVIPM4CommandsUtility() 000000000008ef90 __float128 0f SECT 01 0000 [.text] AMDVIPM4CommandsUtility::~AMDVIPM4CommandsUtility() 000000000008ef86 __float128 0f SECT 01 0000 [.text] AMDVIPM4CommandsUtility::~AMDVIPM4CommandsUtility() 000000000008ef7c __float128 0f SECT 01 0000 [.text] AMDVIPM4CommandsUtility::~AMDVIPM4CommandsUtility() 000000000052d6f8 __float128 0f SECT 0a 0000 [__DATA.__common] AMDCIGraphicsAccelerator::gMetaClass 000000000003cf8c __float128 0f SECT 01 0000 [.text] AMDCIGraphicsAccelerator::newSurface() 000000000039ad98 __float128 0f SECT 08 0000 [.const_data] AMDCIGraphicsAccelerator::superClass 000000000003cfec __float128 0f SECT 01 0000 [.text] AMDCIGraphicsAccelerator::newResource() 000000000003cf5c __float128 0f SECT 01 0000 [.text] AMDCIGraphicsAccelerator::newCLContext() 000000000003cf20 __float128 0f SECT 01 0000 [.text] AMDCIGraphicsAccelerator::newGLContext() 000000000003cfbc __float128 0f SECT 01 0000 [.text] AMDCIGraphicsAccelerator::newVideoContext() 000000000003cefa __float128 0f SECT 01 0000 [.text] AMDCIGraphicsAccelerator::newDisplayMachine() 000000000003d012 __float128 0f SECT 01 0000 [.text] AMDCIGraphicsAccelerator::initCommandBufferPool(IOAccelCommandBufferPool2*, IOAccelTask*, IOAccelChannel2*) 000000000003ce20 __float128 0f SECT 01 0000 [.text] AMDCIGraphicsAccelerator::MetaClass::MetaClass() 000000000003cec0 __float128 0f SECT 01 0000 [.text] AMDCIGraphicsAccelerator::MetaClass::MetaClass() 000000000039ad90 __float128 0f SECT 08 0000 [.const_data] AMDCIGraphicsAccelerator::metaClass 000000000003ce5c __float128 0f SECT 01 0000 [.text] AMDCIGraphicsAccelerator::AMDCIGraphicsAccelerator(OSMetaClass const*) 000000000003ce90 __float128 0f SECT 01 0000 [.text] AMDCIGraphicsAccelerator::~AMDCIGraphicsAccelerator() 000000000003ce86 __float128 0f SECT 01 0000 [.text] AMDCIGraphicsAccelerator::~AMDCIGraphicsAccelerator() 000000000003ce7c __float128 0f SECT 01 0000 [.text] AMDCIGraphicsAccelerator::~AMDCIGraphicsAccelerator() 000000000002363e __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDBltMgr::FreeSysMem(void*) 0000000000023834 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDBltMgr::FreeVidMem(void*, void*) 00000000000238ec __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDBltMgr::LockVidMem(void*, _UBM_LOCKVIDMEM_INPUT const*) 000000000052d1d8 __float128 0f SECT 0a 0000 [__DATA.__common] AMDRadeonX4000_AMDBltMgr::gMetaClass 0000000000390af8 __float128 0f SECT 08 0000 [.const_data] AMDRadeonX4000_AMDBltMgr::superClass 00000000000235f6 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDBltMgr::AllocSysMem(_UBM_ALLOCSYSMEM_INPUT const*) 0000000000023658 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDBltMgr::AllocVidMem(void*, _UBM_ALLOCVIDMEM_INPUT const*, _UBM_ALLOCVIDMEM_OUTPUT*) 0000000000023aae __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDBltMgr::GetCmdSpace(void*, unsigned int) 0000000000023fda __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDBltMgr::SurfaceCopy(_UBM_SURFACECOPYINFO*, _UBM_E_RETURNCODE*) 0000000000023996 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDBltMgr::UnlockVidMem(void*, void*) 0000000000024318 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDBltMgr::addPatchData(unsigned int, unsigned int) 0000000000023a5e __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDBltMgr::AddWideHandle(void*, _UBM_ADDWIDEHANDLE_INPUT const*) 0000000000023acc __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDBltMgr::GetCmdBufBase(void*) 0000000000024028 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDBltMgr::processHandle(void*, bool, unsigned int, _VCOP_RESOURCE_TYPE, unsigned int, unsigned int, _VCOP_RESOURCE_TYPE, unsigned int) 00000000000239ee __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDBltMgr::VerifyCmdSpace(void*, _UBM_VERIFYCMDSPACE_INPUT const*) 0000000000023b7c __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDBltMgr::clearPatchData() 0000000000023be2 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDBltMgr::clearStateInit() 0000000000024422 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDBltMgr::releaseMappings(IOAccelTask*) 00000000000243b8 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDBltMgr::patchCommandBuffer(IOAccelChannel2*) 0000000000023ade __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDBltMgr::GetCmdBufFreeEntries(void*) 0000000000023af2 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDBltMgr::free() 0000000000023222 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDBltMgr::init(AMDRadeonX4000_AMDGraphicsAccelerator*) 0000000000023d48 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDBltMgr::Clear(_UBM_CLEARINFO*, _UBM_E_RETURNCODE*) 0000000000023e3c __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDBltMgr::Expand(_UBM_EXPANDINFO*, _UBM_E_RETURNCODE*) 0000000000023f4c __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDBltMgr::Memcpy(_UBM_MEMCPYINFO*, _UBM_E_RETURNCODE*) 0000000000023ed8 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDBltMgr::Memset(_UBM_MEMSETINFO*, _UBM_E_RETURNCODE*) 0000000000023c7e __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDBltMgr::Stretch(_UBM_STRETCHINFO*, _UBM_E_RETURNCODE*) 0000000000023dee __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDBltMgr::AAResolve(_UBM_AARESOLVEINFO*, _UBM_E_RETURNCODE*) 0000000000023a10 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDBltMgr::AddHandle(void*, _UBM_ADDHANDLE_INPUT const*) 0000000000023090 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDBltMgr::MetaClass::MetaClass() 0000000000023150 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDBltMgr::MetaClass::MetaClass() 0000000000023c20 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDBltMgr::SetPM4Buf(unsigned int*, unsigned int, unsigned int, IOAccelTask*) 0000000000023e8a __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDBltMgr::TileCBToZ(_UBM_COMPRESSINFO*, _UBM_E_RETURNCODE*) 0000000000390af0 __float128 0f SECT 08 0000 [.const_data] AMDRadeonX4000_AMDBltMgr::metaClass 00000000000230ec __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDBltMgr::AMDRadeonX4000_AMDBltMgr(OSMetaClass const*) 00000000000231c2 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDBltMgr::AMDRadeonX4000_AMDBltMgr() 00000000000230cc __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDBltMgr::AMDRadeonX4000_AMDBltMgr(OSMetaClass const*) 00000000000231f2 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDBltMgr::AMDRadeonX4000_AMDBltMgr() 0000000000023120 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDBltMgr::~AMDRadeonX4000_AMDBltMgr() 0000000000023116 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDBltMgr::~AMDRadeonX4000_AMDBltMgr() 000000000002310c __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDBltMgr::~AMDRadeonX4000_AMDBltMgr() 000000000052f1d8 __float128 0f SECT 0a 0000 [__DATA.__common] AMDRadeonX4000_AMDCIKDRM::gMetaClass 00000000003c47f8 __float128 0f SECT 08 0000 [.const_data] AMDRadeonX4000_AMDCIKDRM::superClass 000000000012a102 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDCIKDRM::writeAESCmd(unsigned int*, unsigned int*, unsigned long long, unsigned long long, unsigned int, _DRMDMA_AES*, unsigned int) 000000000012a584 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDCIKDRM::writeCBCCmds(unsigned int*, unsigned int, unsigned long long, unsigned long long, unsigned int, _DRMDMA_AES*, bool) 000000000012a312 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDCIKDRM::writeCTRCmds(unsigned int*, unsigned int, unsigned long long, unsigned long long, unsigned int, _DRMDMA_AES*, bool) 000000000012a80a __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDCIKDRM::writeCBCCTRCmds(unsigned int*, unsigned int, unsigned long long, unsigned long long, unsigned int, _DRMDMA_AES*) 000000000012a0f0 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDCIKDRM::free() 000000000012a0c2 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDCIKDRM::init() 0000000000129f30 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDCIKDRM::MetaClass::MetaClass() 0000000000129ff0 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDCIKDRM::MetaClass::MetaClass() 00000000003c47f0 __float128 0f SECT 08 0000 [.const_data] AMDRadeonX4000_AMDCIKDRM::metaClass 0000000000129f8c __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDCIKDRM::AMDRadeonX4000_AMDCIKDRM(OSMetaClass const*) 000000000012a062 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDCIKDRM::AMDRadeonX4000_AMDCIKDRM() 0000000000129f6c __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDCIKDRM::AMDRadeonX4000_AMDCIKDRM(OSMetaClass const*) 000000000012a092 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDCIKDRM::AMDRadeonX4000_AMDCIKDRM() 0000000000129fc0 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDCIKDRM::~AMDRadeonX4000_AMDCIKDRM() 0000000000129fb6 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDCIKDRM::~AMDRadeonX4000_AMDCIKDRM() 0000000000129fac __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDCIKDRM::~AMDRadeonX4000_AMDCIKDRM() 000000000052f200 __float128 0f SECT 0a 0000 [__DATA.__common] AMDRadeonX4000_AMDCIKSPU::gMetaClass 000000000012ac04 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDCIKSPU::getAppSize(_AMD_SPU_APP_TYPE, unsigned int*, unsigned int*) 00000000003c4a58 __float128 0f SECT 08 0000 [.const_data] AMDRadeonX4000_AMDCIKSPU::superClass 000000000012abca __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDCIKSPU::getKappSize(unsigned int*, unsigned int*) 000000000012adf6 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDCIKSPU::writeAppCmd(_SML_SPU_CMD*, bool) 000000000012ad6c __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDCIKSPU::writeInitCmd(_SML_SPU_CMD*) 000000000012af2e __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDCIKSPU::writeAppMsgCmd(_SML_SPU_CMD*) 000000000012abbc __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDCIKSPU::getFeedBackSize(unsigned int*) 000000000012ab56 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDCIKSPU::getKernelMemReq(unsigned int*, unsigned int*, unsigned int*) 000000000012b080 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDCIKSPU::writeSetPremContentCmd(_SAMU_GPCOM_CMD*) 000000000012ab44 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDCIKSPU::free() 000000000012ab32 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDCIKSPU::init() 000000000012ac24 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDCIKSPU::getApp(_AMD_SPU_APP_TYPE, unsigned int*, unsigned int*) 000000000012abde __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDCIKSPU::getKapp(unsigned int*, unsigned int*) 000000000012a9a0 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDCIKSPU::MetaClass::MetaClass() 000000000012aa60 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDCIKSPU::MetaClass::MetaClass() 000000000012ac60 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDCIKSPU::getAppMsg(_AMD_SPU_MSG_TYPE) 000000000012ab70 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDCIKSPU::getKernel(unsigned int*, unsigned int*, unsigned int*, unsigned int*) 00000000003c4a50 __float128 0f SECT 08 0000 [.const_data] AMDRadeonX4000_AMDCIKSPU::metaClass 000000000012a9fc __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDCIKSPU::AMDRadeonX4000_AMDCIKSPU(OSMetaClass const*) 000000000012aad2 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDCIKSPU::AMDRadeonX4000_AMDCIKSPU() 000000000012a9dc __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDCIKSPU::AMDRadeonX4000_AMDCIKSPU(OSMetaClass const*) 000000000012ab02 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDCIKSPU::AMDRadeonX4000_AMDCIKSPU() 000000000012aa30 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDCIKSPU::~AMDRadeonX4000_AMDCIKSPU() 000000000012aa26 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDCIKSPU::~AMDRadeonX4000_AMDCIKSPU() 000000000012aa1c __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDCIKSPU::~AMDRadeonX4000_AMDCIKSPU() 000000000052f228 __float128 0f SECT 0a 0000 [__DATA.__common] AMDRadeonX4000_AMDCIKVCE::gMetaClass 00000000003c4ce8 __float128 0f SECT 08 0000 [.const_data] AMDRadeonX4000_AMDCIKVCE::superClass 000000000012b34e __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDCIKVCE::getFWMemReq(unsigned int*, unsigned int*) 000000000012b384 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDCIKVCE::getFWCacheInfo(_SML_VCEFWINFO*) 000000000012b370 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDCIKVCE::getFWMemConfig(unsigned int*, unsigned int*) 000000000012b33c __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDCIKVCE::free() 000000000012b302 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDCIKVCE::init(unsigned int) 000000000012b170 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDCIKVCE::MetaClass::MetaClass() 000000000012b230 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDCIKVCE::MetaClass::MetaClass() 00000000003c4ce0 __float128 0f SECT 08 0000 [.const_data] AMDRadeonX4000_AMDCIKVCE::metaClass 000000000012b1cc __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDCIKVCE::AMDRadeonX4000_AMDCIKVCE(OSMetaClass const*) 000000000012b2a2 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDCIKVCE::AMDRadeonX4000_AMDCIKVCE() 000000000012b1ac __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDCIKVCE::AMDRadeonX4000_AMDCIKVCE(OSMetaClass const*) 000000000012b2d2 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDCIKVCE::AMDRadeonX4000_AMDCIKVCE() 000000000012b200 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDCIKVCE::~AMDRadeonX4000_AMDCIKVCE() 000000000012b1f6 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDCIKVCE::~AMDRadeonX4000_AMDCIKVCE() 000000000012b1ec __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDCIKVCE::~AMDRadeonX4000_AMDCIKVCE() 000000000052da40 __float128 0f SECT 0a 0000 [__DATA.__common] AMDRadeonX4000_AMDHWGart::gMetaClass 00000000003a3068 __float128 0f SECT 08 0000 [.const_data] AMDRadeonX4000_AMDHWGart::superClass 0000000000051fa0 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHWGart::mapGartMemory() 00000000000515ea __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHWGart::setParameters(_GART_PARAMETERS*) 0000000000051e38 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHWGart::clearPageTable(unsigned long long, unsigned long long) 000000000005208c __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHWGart::unmapGartMemory() 0000000000051b1a __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHWGart::updatePageTable(IOMemoryDescriptor*, unsigned long long, _eOP_ORIGINATOR, _eOP_TYPE, bool, bool) 0000000000052342 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHWGart::setVirtualSpaceReady(bool) 00000000000516fc __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHWGart::fillMemoryWithEmptyValue(unsigned long long*, unsigned long long, unsigned int) 0000000000051de4 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHWGart::flushAndInvalidateCaches(unsigned int) 0000000000052360 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHWGart::setMemoryAllocationsEnabled(bool) 00000000000520d4 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHWGart::add(IOMemoryDescriptor*, unsigned long long*, unsigned int, _eOP_ORIGINATOR, _eOP_TYPE, bool, bool) 000000000005172c __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHWGart::free() 0000000000051a22 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHWGart::free(unsigned long long, unsigned long long) 0000000000051442 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHWGart::init(AMDRadeonX4000_IAMDHWInterface*, _GART_PARAMETERS*) 00000000000522de __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHWGart::clear(unsigned long long) 0000000000052446 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHWGart::pageOn() 00000000000521dc __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHWGart::remove(IOMemoryDescriptor*, unsigned long long) 0000000000052410 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHWGart::pageOff() 0000000000052268 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHWGart::reserve(unsigned long long) 00000000000518f4 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHWGart::reserve(unsigned long long, unsigned long long, _eOP_ORIGINATOR, _eOP_TYPE) 00000000000517b6 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHWGart::allocate(unsigned long long&, unsigned long long, unsigned int, _eOP_ORIGINATOR, _eOP_TYPE) 00000000000512b0 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHWGart::MetaClass::MetaClass() 0000000000051370 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHWGart::MetaClass::MetaClass() 00000000003a3060 __float128 0f SECT 08 0000 [.const_data] AMDRadeonX4000_AMDHWGart::metaClass 000000000005130c __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHWGart::AMDRadeonX4000_AMDHWGart(OSMetaClass const*) 00000000000513e2 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHWGart::AMDRadeonX4000_AMDHWGart() 00000000000512ec __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHWGart::AMDRadeonX4000_AMDHWGart(OSMetaClass const*) 0000000000051412 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHWGart::AMDRadeonX4000_AMDHWGart() 0000000000051340 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHWGart::~AMDRadeonX4000_AMDHWGart() 0000000000051336 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHWGart::~AMDRadeonX4000_AMDHWGart() 000000000005132c __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHWGart::~AMDRadeonX4000_AMDHWGart() 000000000052dd60 __float128 0f SECT 0a 0000 [__DATA.__common] AMDRadeonX4000_AMDHWRing::gMetaClass 0000000000055cba __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHWRing::initialize(AMDRadeonX4000_IAMDHWInterface*, _HW_RING_INFO const&, int, _eAMD_HW_ENGINE_TYPE, unsigned int) 00000000003a6c48 __float128 0f SECT 08 0000 [.const_data] AMDRadeonX4000_AMDHWRing::superClass 0000000000056050 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHWRing::writeEntries(unsigned int*, unsigned int) 0000000000055f3a __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHWRing::freeResources() 0000000000055e12 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHWRing::allocateResources() 0000000000056200 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHWRing::syncTailWriteback() 00000000000560c8 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHWRing::flushWithoutSubmit() 000000000005622a __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHWRing::writeDiagnosisReport(char*&, unsigned int&) 0000000000055dbc __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHWRing::free() 0000000000056032 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHWRing::write(unsigned int) 0000000000055fb2 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHWRing::enable() 0000000000056160 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHWRing::submit() 0000000000055ffe __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHWRing::disable() 0000000000055be0 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHWRing::MetaClass::MetaClass() 0000000000055c80 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHWRing::MetaClass::MetaClass() 00000000003a6c40 __float128 0f SECT 08 0000 [.const_data] AMDRadeonX4000_AMDHWRing::metaClass 000000000005608e __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHWRing::writeTail() 0000000000055c1c __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHWRing::AMDRadeonX4000_AMDHWRing(OSMetaClass const*) 0000000000055c50 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHWRing::~AMDRadeonX4000_AMDHWRing() 0000000000055c46 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHWRing::~AMDRadeonX4000_AMDHWRing() 0000000000055c3c __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHWRing::~AMDRadeonX4000_AMDHWRing() 000000000052eeb8 __float128 0f SECT 0a 0000 [__DATA.__common] AMDRadeonX4000_AMDSMLDRM::gMetaClass 00000000003c13d8 __float128 0f SECT 08 0000 [.const_data] AMDRadeonX4000_AMDSMLDRM::superClass 000000000012560e __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDSMLDRM::writeAESCmd(unsigned int*, unsigned int*, unsigned long long, unsigned long long, unsigned int, _DRMDMA_AES*, unsigned int) 00000000001255fc __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDSMLDRM::free() 00000000001255ea __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDSMLDRM::init() 0000000000125616 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDSMLDRM::inc_cntr(unsigned char*, unsigned int) 00000000001254f0 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDSMLDRM::MetaClass::MetaClass() 00000000001255b0 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDSMLDRM::MetaClass::MetaClass() 00000000003c13d0 __float128 0f SECT 08 0000 [.const_data] AMDRadeonX4000_AMDSMLDRM::metaClass 000000000012554c __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDSMLDRM::AMDRadeonX4000_AMDSMLDRM(OSMetaClass const*) 000000000012552c __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDSMLDRM::AMDRadeonX4000_AMDSMLDRM(OSMetaClass const*) 0000000000125580 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDSMLDRM::~AMDRadeonX4000_AMDSMLDRM() 0000000000125576 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDSMLDRM::~AMDRadeonX4000_AMDSMLDRM() 000000000012556c __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDSMLDRM::~AMDRadeonX4000_AMDSMLDRM() 000000000052eee0 __float128 0f SECT 0a 0000 [__DATA.__common] AMDRadeonX4000_AMDSMLSPU::gMetaClass 0000000000125896 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDSMLSPU::getAppSize(_AMD_SPU_APP_TYPE, unsigned int*, unsigned int*) 00000000003c1618 __float128 0f SECT 08 0000 [.const_data] AMDRadeonX4000_AMDSMLSPU::superClass 0000000000125886 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDSMLSPU::getKappSize(unsigned int*, unsigned int*) 00000000001258b6 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDSMLSPU::writeAppCmd(_SML_SPU_CMD*, bool) 00000000001258ae __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDSMLSPU::writeInitCmd(_SML_SPU_CMD*) 00000000001258be __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDSMLSPU::writeAppMsgCmd(_SML_SPU_CMD*) 000000000012587e __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDSMLSPU::getFeedBackSize(unsigned int*) 000000000012586e __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDSMLSPU::getKernelMemReq(unsigned int*, unsigned int*, unsigned int*) 000000000012585c __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDSMLSPU::free() 000000000012584a __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDSMLSPU::init() 000000000012589e __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDSMLSPU::getApp(_AMD_SPU_APP_TYPE, unsigned int*, unsigned int*) 000000000012588e __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDSMLSPU::getKapp(unsigned int*, unsigned int*) 0000000000125750 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDSMLSPU::MetaClass::MetaClass() 0000000000125810 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDSMLSPU::MetaClass::MetaClass() 00000000001258a6 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDSMLSPU::getAppMsg(_AMD_SPU_MSG_TYPE) 0000000000125876 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDSMLSPU::getKernel(unsigned int*, unsigned int*, unsigned int*, unsigned int*) 00000000003c1610 __float128 0f SECT 08 0000 [.const_data] AMDRadeonX4000_AMDSMLSPU::metaClass 00000000001257ac __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDSMLSPU::AMDRadeonX4000_AMDSMLSPU(OSMetaClass const*) 000000000012578c __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDSMLSPU::AMDRadeonX4000_AMDSMLSPU(OSMetaClass const*) 00000000001257e0 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDSMLSPU::~AMDRadeonX4000_AMDSMLSPU() 00000000001257d6 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDSMLSPU::~AMDRadeonX4000_AMDSMLSPU() 00000000001257cc __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDSMLSPU::~AMDRadeonX4000_AMDSMLSPU() 000000000052ee90 __float128 0f SECT 0a 0000 [__DATA.__common] AMDRadeonX4000_AMDSMLUVD::gMetaClass 00000000003c1158 __float128 0f SECT 08 0000 [.const_data] AMDRadeonX4000_AMDSMLUVD::superClass 0000000000124e20 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDSMLUVD::getFWMemReq(unsigned int*, unsigned int*, unsigned int*) 0000000000124e40 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDSMLUVD::getFWCacheInfo(_SML_UVDFWInfo*) 0000000000125430 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDSMLUVD::writeDestroyMsg(unsigned int, _SML_UVD_MSG*) 000000000012539c __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDSMLUVD::writeUVDSaveState(unsigned int, _SML_UVD_MSG*) 00000000001253fc __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDSMLUVD::writeUVDRestoreState(unsigned int, _SML_UVD_MSG*) 0000000000124e0e __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDSMLUVD::free() 0000000000124dba __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDSMLUVD::init(unsigned int) 000000000012546c __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDSMLUVD::doTest(unsigned int, unsigned int, unsigned int) 0000000000124cc0 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDSMLUVD::MetaClass::MetaClass() 0000000000124d80 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDSMLUVD::MetaClass::MetaClass() 0000000000124e8a __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDSMLUVD::loadUVDFW(_SML_UVDFW*) 00000000003c1150 __float128 0f SECT 08 0000 [.const_data] AMDRadeonX4000_AMDSMLUVD::metaClass 00000000001250d8 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDSMLUVD::prepUVDFW(_SML_UVDFW*) 0000000000124d1c __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDSMLUVD::AMDRadeonX4000_AMDSMLUVD(OSMetaClass const*) 0000000000124cfc __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDSMLUVD::AMDRadeonX4000_AMDSMLUVD(OSMetaClass const*) 0000000000124d50 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDSMLUVD::~AMDRadeonX4000_AMDSMLUVD() 0000000000124d46 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDSMLUVD::~AMDRadeonX4000_AMDSMLUVD() 0000000000124d3c __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDSMLUVD::~AMDRadeonX4000_AMDSMLUVD() 000000000052ef30 __float128 0f SECT 0a 0000 [__DATA.__common] AMDRadeonX4000_AMDSMLVCE::gMetaClass 0000000000125fcc __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDSMLVCE::getCmdSize(unsigned int*, _SML_VCE_CMD_TYPE) 00000000003c1b38 __float128 0f SECT 08 0000 [.const_data] AMDRadeonX4000_AMDSMLVCE::superClass 0000000000125da2 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDSMLVCE::getFWMemReq(unsigned int*, unsigned int*) 0000000000125db2 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDSMLVCE::getFWCacheInfo(_SML_VCEFWINFO*) 0000000000125daa __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDSMLVCE::getFWMemConfig(unsigned int*, unsigned int*) 0000000000125e8e __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDSMLVCE::writeCreateCmd(unsigned int*, void*) 0000000000125fee __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDSMLVCE::getFeedbackSize(unsigned int*) 0000000000125fa0 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDSMLVCE::writeDestroyCmd(unsigned int*, void*) 0000000000125d90 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDSMLVCE::free() 0000000000125d5a __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDSMLVCE::init(unsigned int) 0000000000125dba __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDSMLVCE::getFW(_SML_VCEFW*) 0000000000125e38 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDSMLVCE::writeCmd(unsigned int*, unsigned int*, _SML_VCE_CMD_TYPE, void*) 0000000000125c60 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDSMLVCE::MetaClass::MetaClass() 0000000000125d20 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDSMLVCE::MetaClass::MetaClass() 00000000003c1b30 __float128 0f SECT 08 0000 [.const_data] AMDRadeonX4000_AMDSMLVCE::metaClass 0000000000125cbc __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDSMLVCE::AMDRadeonX4000_AMDSMLVCE(OSMetaClass const*) 0000000000125c9c __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDSMLVCE::AMDRadeonX4000_AMDSMLVCE(OSMetaClass const*) 0000000000125cf0 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDSMLVCE::~AMDRadeonX4000_AMDSMLVCE() 0000000000125ce6 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDSMLVCE::~AMDRadeonX4000_AMDSMLVCE() 0000000000125cdc __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDSMLVCE::~AMDRadeonX4000_AMDSMLVCE() 000000000052f1b0 __float128 0f SECT 0a 0000 [__DATA.__common] AMDRadeonX4000_AMDUVDCIK::gMetaClass 00000000003c4578 __float128 0f SECT 08 0000 [.const_data] AMDRadeonX4000_AMDUVDCIK::superClass 0000000000129cb0 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDUVDCIK::getFWMemReq(unsigned int*, unsigned int*, unsigned int*) 0000000000129cd0 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDUVDCIK::getFWCacheInfo(_SML_UVDFWInfo*) 0000000000129c72 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDUVDCIK::init(unsigned int) 0000000000129ae0 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDUVDCIK::MetaClass::MetaClass() 0000000000129ba0 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDUVDCIK::MetaClass::MetaClass() 0000000000129d1a __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDUVDCIK::loadUVDFW(_SML_UVDFW*) 00000000003c4570 __float128 0f SECT 08 0000 [.const_data] AMDRadeonX4000_AMDUVDCIK::metaClass 0000000000129b3c __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDUVDCIK::AMDRadeonX4000_AMDUVDCIK(OSMetaClass const*) 0000000000129c12 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDUVDCIK::AMDRadeonX4000_AMDUVDCIK() 0000000000129b1c __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDUVDCIK::AMDRadeonX4000_AMDUVDCIK(OSMetaClass const*) 0000000000129c42 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDUVDCIK::AMDRadeonX4000_AMDUVDCIK() 0000000000129b70 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDUVDCIK::~AMDRadeonX4000_AMDUVDCIK() 0000000000129b66 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDUVDCIK::~AMDRadeonX4000_AMDUVDCIK() 0000000000129b5c __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDUVDCIK::~AMDRadeonX4000_AMDUVDCIK() 000000000052dcc0 __float128 0f SECT 0a 0000 [__DATA.__common] AMDRadeonX4000_IAMDHWVMM::gMetaClass 00000000003a6070 __float128 0f SECT 08 0000 [.const_data] AMDRadeonX4000_IAMDHWVMM::superClass 0000000000053226 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_IAMDHWVMM::MetaClass::MetaClass() 00000000000532c6 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_IAMDHWVMM::MetaClass::MetaClass() 00000000003a6068 __float128 0f SECT 08 0000 [.const_data] AMDRadeonX4000_IAMDHWVMM::metaClass 0000000000053262 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_IAMDHWVMM::AMDRadeonX4000_IAMDHWVMM(OSMetaClass const*) 0000000000053296 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_IAMDHWVMM::~AMDRadeonX4000_IAMDHWVMM() 000000000005328c __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_IAMDHWVMM::~AMDRadeonX4000_IAMDHWVMM() 0000000000053282 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_IAMDHWVMM::~AMDRadeonX4000_IAMDHWVMM() 000000000052d540 __float128 0f SECT 0a 0000 [__DATA.__common] AMDSIGraphicsAccelerator::gMetaClass 000000000002900c __float128 0f SECT 01 0000 [.text] AMDSIGraphicsAccelerator::newSurface() 00000000003936d8 __float128 0f SECT 08 0000 [.const_data] AMDSIGraphicsAccelerator::superClass 000000000002906c __float128 0f SECT 01 0000 [.text] AMDSIGraphicsAccelerator::newResource() 0000000000028fdc __float128 0f SECT 01 0000 [.text] AMDSIGraphicsAccelerator::newCLContext() 0000000000028fa0 __float128 0f SECT 01 0000 [.text] AMDSIGraphicsAccelerator::newGLContext() 000000000002903c __float128 0f SECT 01 0000 [.text] AMDSIGraphicsAccelerator::newVideoContext() 0000000000028f7a __float128 0f SECT 01 0000 [.text] AMDSIGraphicsAccelerator::newDisplayMachine() 0000000000029092 __float128 0f SECT 01 0000 [.text] AMDSIGraphicsAccelerator::initCommandBufferPool(IOAccelCommandBufferPool2*, IOAccelTask*, IOAccelChannel2*) 0000000000028ea0 __float128 0f SECT 01 0000 [.text] AMDSIGraphicsAccelerator::MetaClass::MetaClass() 0000000000028f40 __float128 0f SECT 01 0000 [.text] AMDSIGraphicsAccelerator::MetaClass::MetaClass() 00000000003936d0 __float128 0f SECT 08 0000 [.const_data] AMDSIGraphicsAccelerator::metaClass 0000000000028edc __float128 0f SECT 01 0000 [.text] AMDSIGraphicsAccelerator::AMDSIGraphicsAccelerator(OSMetaClass const*) 0000000000028f10 __float128 0f SECT 01 0000 [.text] AMDSIGraphicsAccelerator::~AMDSIGraphicsAccelerator() 0000000000028f06 __float128 0f SECT 01 0000 [.text] AMDSIGraphicsAccelerator::~AMDSIGraphicsAccelerator() 0000000000028efc __float128 0f SECT 01 0000 [.text] AMDSIGraphicsAccelerator::~AMDSIGraphicsAccelerator() 000000000052d7c0 __float128 0f SECT 0a 0000 [__DATA.__common] AMDVIGraphicsAccelerator::gMetaClass 00000000000467ec __float128 0f SECT 01 0000 [.text] AMDVIGraphicsAccelerator::newSurface() 000000000039e1c8 __float128 0f SECT 08 0000 [.const_data] AMDVIGraphicsAccelerator::superClass 000000000004684c __float128 0f SECT 01 0000 [.text] AMDVIGraphicsAccelerator::newResource() 00000000000467bc __float128 0f SECT 01 0000 [.text] AMDVIGraphicsAccelerator::newCLContext() 0000000000046780 __float128 0f SECT 01 0000 [.text] AMDVIGraphicsAccelerator::newGLContext() 000000000004681c __float128 0f SECT 01 0000 [.text] AMDVIGraphicsAccelerator::newVideoContext() 000000000004675a __float128 0f SECT 01 0000 [.text] AMDVIGraphicsAccelerator::newDisplayMachine() 0000000000046872 __float128 0f SECT 01 0000 [.text] AMDVIGraphicsAccelerator::initCommandBufferPool(IOAccelCommandBufferPool2*, IOAccelTask*, IOAccelChannel2*) 0000000000046680 __float128 0f SECT 01 0000 [.text] AMDVIGraphicsAccelerator::MetaClass::MetaClass() 0000000000046720 __float128 0f SECT 01 0000 [.text] AMDVIGraphicsAccelerator::MetaClass::MetaClass() 000000000039e1c0 __float128 0f SECT 08 0000 [.const_data] AMDVIGraphicsAccelerator::metaClass 00000000000466bc __float128 0f SECT 01 0000 [.text] AMDVIGraphicsAccelerator::AMDVIGraphicsAccelerator(OSMetaClass const*) 00000000000466f0 __float128 0f SECT 01 0000 [.text] AMDVIGraphicsAccelerator::~AMDVIGraphicsAccelerator() 00000000000466e6 __float128 0f SECT 01 0000 [.text] AMDVIGraphicsAccelerator::~AMDVIGraphicsAccelerator() 00000000000466dc __float128 0f SECT 01 0000 [.text] AMDVIGraphicsAccelerator::~AMDVIGraphicsAccelerator() 000000000052de78 __float128 0f SECT 0a 0000 [__DATA.__common] AMDRadeonX4000_AMDNULLVMM::gMetaClass 00000000003a7f58 __float128 0f SECT 08 0000 [.const_data] AMDRadeonX4000_AMDNULLVMM::superClass 0000000000059a00 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDNULLVMM::MetaClass::MetaClass() 0000000000059ac0 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDNULLVMM::MetaClass::MetaClass() 00000000003a7f50 __float128 0f SECT 08 0000 [.const_data] AMDRadeonX4000_AMDNULLVMM::metaClass 0000000000059a5c __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDNULLVMM::AMDRadeonX4000_AMDNULLVMM(OSMetaClass const*) 0000000000059b32 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDNULLVMM::AMDRadeonX4000_AMDNULLVMM() 0000000000059a3c __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDNULLVMM::AMDRadeonX4000_AMDNULLVMM(OSMetaClass const*) 0000000000059b62 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDNULLVMM::AMDRadeonX4000_AMDNULLVMM() 0000000000059a90 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDNULLVMM::~AMDRadeonX4000_AMDNULLVMM() 0000000000059a86 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDNULLVMM::~AMDRadeonX4000_AMDNULLVMM() 0000000000059a7c __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDNULLVMM::~AMDRadeonX4000_AMDNULLVMM() 000000000052db58 __float128 0f SECT 0a 0000 [__DATA.__common] AMDRadeonX4000_IAMDHWGart::gMetaClass 00000000003a4870 __float128 0f SECT 08 0000 [.const_data] AMDRadeonX4000_IAMDHWGart::superClass 0000000000052a7c __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_IAMDHWGart::MetaClass::MetaClass() 0000000000052b1c __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_IAMDHWGart::MetaClass::MetaClass() 00000000003a4868 __float128 0f SECT 08 0000 [.const_data] AMDRadeonX4000_IAMDHWGart::metaClass 0000000000052ab8 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_IAMDHWGart::AMDRadeonX4000_IAMDHWGart(OSMetaClass const*) 0000000000052aec __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_IAMDHWGart::~AMDRadeonX4000_IAMDHWGart() 0000000000052ae2 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_IAMDHWGart::~AMDRadeonX4000_IAMDHWGart() 0000000000052ad8 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_IAMDHWGart::~AMDRadeonX4000_IAMDHWGart() 000000000052db80 __float128 0f SECT 0a 0000 [__DATA.__common] AMDRadeonX4000_IAMDHWRing::gMetaClass 00000000003a4b20 __float128 0f SECT 08 0000 [.const_data] AMDRadeonX4000_IAMDHWRing::superClass 0000000000052b56 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_IAMDHWRing::MetaClass::MetaClass() 0000000000052bf6 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_IAMDHWRing::MetaClass::MetaClass() 00000000003a4b18 __float128 0f SECT 08 0000 [.const_data] AMDRadeonX4000_IAMDHWRing::metaClass 0000000000052b92 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_IAMDHWRing::AMDRadeonX4000_IAMDHWRing(OSMetaClass const*) 0000000000052bc6 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_IAMDHWRing::~AMDRadeonX4000_IAMDHWRing() 0000000000052bbc __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_IAMDHWRing::~AMDRadeonX4000_IAMDHWRing() 0000000000052bb2 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_IAMDHWRing::~AMDRadeonX4000_IAMDHWRing() 000000000052edc8 __float128 0f SECT 0a 0000 [__DATA.__common] AMDRadeonX4000_IAMDSMLDRM::gMetaClass 00000000003c0440 __float128 0f SECT 08 0000 [.const_data] AMDRadeonX4000_IAMDSMLDRM::superClass 0000000000123f9a __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_IAMDSMLDRM::MetaClass::MetaClass() 000000000012405a __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_IAMDSMLDRM::MetaClass::MetaClass() 00000000003c0438 __float128 0f SECT 08 0000 [.const_data] AMDRadeonX4000_IAMDSMLDRM::metaClass 0000000000123ff6 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_IAMDSMLDRM::AMDRadeonX4000_IAMDSMLDRM(OSMetaClass const*) 0000000000123fd6 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_IAMDSMLDRM::AMDRadeonX4000_IAMDSMLDRM(OSMetaClass const*) 000000000012402a __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_IAMDSMLDRM::~AMDRadeonX4000_IAMDSMLDRM() 0000000000124020 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_IAMDSMLDRM::~AMDRadeonX4000_IAMDSMLDRM() 0000000000124016 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_IAMDSMLDRM::~AMDRadeonX4000_IAMDSMLDRM() 000000000052edf0 __float128 0f SECT 0a 0000 [__DATA.__common] AMDRadeonX4000_IAMDSMLSPU::gMetaClass 00000000003c0670 __float128 0f SECT 08 0000 [.const_data] AMDRadeonX4000_IAMDSMLSPU::superClass 0000000000124094 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_IAMDSMLSPU::MetaClass::MetaClass() 0000000000124154 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_IAMDSMLSPU::MetaClass::MetaClass() 00000000003c0668 __float128 0f SECT 08 0000 [.const_data] AMDRadeonX4000_IAMDSMLSPU::metaClass 00000000001240f0 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_IAMDSMLSPU::AMDRadeonX4000_IAMDSMLSPU(OSMetaClass const*) 00000000001240d0 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_IAMDSMLSPU::AMDRadeonX4000_IAMDSMLSPU(OSMetaClass const*) 0000000000124124 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_IAMDSMLSPU::~AMDRadeonX4000_IAMDSMLSPU() 000000000012411a __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_IAMDSMLSPU::~AMDRadeonX4000_IAMDSMLSPU() 0000000000124110 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_IAMDSMLSPU::~AMDRadeonX4000_IAMDSMLSPU() 000000000052eda0 __float128 0f SECT 0a 0000 [__DATA.__common] AMDRadeonX4000_IAMDSMLUVD::gMetaClass 00000000003c0218 __float128 0f SECT 08 0000 [.const_data] AMDRadeonX4000_IAMDSMLUVD::superClass 0000000000123ea0 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_IAMDSMLUVD::MetaClass::MetaClass() 0000000000123f60 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_IAMDSMLUVD::MetaClass::MetaClass() 00000000003c0210 __float128 0f SECT 08 0000 [.const_data] AMDRadeonX4000_IAMDSMLUVD::metaClass 0000000000123efc __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_IAMDSMLUVD::AMDRadeonX4000_IAMDSMLUVD(OSMetaClass const*) 0000000000123edc __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_IAMDSMLUVD::AMDRadeonX4000_IAMDSMLUVD(OSMetaClass const*) 0000000000123f30 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_IAMDSMLUVD::~AMDRadeonX4000_IAMDSMLUVD() 0000000000123f26 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_IAMDSMLUVD::~AMDRadeonX4000_IAMDSMLUVD() 0000000000123f1c __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_IAMDSMLUVD::~AMDRadeonX4000_IAMDSMLUVD() 000000000052ee18 __float128 0f SECT 0a 0000 [__DATA.__common] AMDRadeonX4000_IAMDSMLVCE::gMetaClass 00000000003c08a0 __float128 0f SECT 08 0000 [.const_data] AMDRadeonX4000_IAMDSMLVCE::superClass 000000000012418e __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_IAMDSMLVCE::MetaClass::MetaClass() 000000000012424e __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_IAMDSMLVCE::MetaClass::MetaClass() 00000000003c0898 __float128 0f SECT 08 0000 [.const_data] AMDRadeonX4000_IAMDSMLVCE::metaClass 00000000001241ea __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_IAMDSMLVCE::AMDRadeonX4000_IAMDSMLVCE(OSMetaClass const*) 00000000001241ca __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_IAMDSMLVCE::AMDRadeonX4000_IAMDSMLVCE(OSMetaClass const*) 000000000012421e __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_IAMDSMLVCE::~AMDRadeonX4000_IAMDSMLVCE() 0000000000124214 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_IAMDSMLVCE::~AMDRadeonX4000_IAMDSMLVCE() 000000000012420a __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_IAMDSMLVCE::~AMDRadeonX4000_IAMDSMLVCE() 000000000052d200 __float128 0f SECT 0a 0000 [__DATA.__common] AMDRadeonX4000_VendorGart::gMetaClass 0000000000390d38 __float128 0f SECT 08 0000 [.const_data] AMDRadeonX4000_VendorGart::superClass 0000000000024896 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_VendorGart::freeVendorGartEntry(_VENDOR_GART_ENTRY*) 0000000000024818 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_VendorGart::allocVendorGartEntry() 00000000000246c6 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_VendorGart::free() 0000000000024672 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_VendorGart::init() 0000000000024792 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_VendorGart::alloc(unsigned long long*, unsigned long long, unsigned int) 00000000000248d2 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_VendorGart::dealloc(unsigned long long, unsigned int) 0000000000024926 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_VendorGart::reserve(unsigned long long, unsigned long long) 00000000000244e0 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_VendorGart::MetaClass::MetaClass() 00000000000245a0 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_VendorGart::MetaClass::MetaClass() 0000000000024736 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_VendorGart::init_pool(unsigned long long) 0000000000390d30 __float128 0f SECT 08 0000 [.const_data] AMDRadeonX4000_VendorGart::metaClass 000000000002453c __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_VendorGart::AMDRadeonX4000_VendorGart(OSMetaClass const*) 0000000000024612 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_VendorGart::AMDRadeonX4000_VendorGart() 000000000002451c __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_VendorGart::AMDRadeonX4000_VendorGart(OSMetaClass const*) 0000000000024642 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_VendorGart::AMDRadeonX4000_VendorGart() 0000000000024570 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_VendorGart::~AMDRadeonX4000_VendorGart() 0000000000024566 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_VendorGart::~AMDRadeonX4000_VendorGart() 000000000002455c __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_VendorGart::~AMDRadeonX4000_VendorGart() 000000000052d9f0 __float128 0f SECT 0a 0000 [__DATA.__common] AMDRadeonX4000_AMDHWEngine::gMetaClass 00000000003a2a38 __float128 0f SECT 08 0000 [.const_data] AMDRadeonX4000_AMDHWEngine::superClass 00000000000508ba __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHWEngine::waitForIdle() 0000000000050992 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHWEngine::getHWChannel(_eAMD_HW_RING_TYPE) 0000000000050b1a __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHWEngine::releaseHWRings() 0000000000050a3c __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHWEngine::releaseHWChannels() 00000000000508da __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHWEngine::limitedWaitForIdle(unsigned int, unsigned int) 0000000000050b70 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHWEngine::writeDiagnosisReport(char*&, unsigned int&) 0000000000050a7a __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHWEngine::allocateAndInitHWRings() 00000000000509a0 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHWEngine::allocateAndInitHWChannels() 0000000000050b58 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHWEngine::initializeSubmitCommandBufferInfo(AMD_SUBMIT_COMMAND_BUFFER_INFO*) 0000000000050812 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHWEngine::free() 00000000000506fa __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHWEngine::init(AMDRadeonX4000_IAMDHWInterface*, _eAMD_HW_ENGINE_TYPE) 0000000000050d9e __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHWEngine::reset(_eAMD_HW_RING_TYPE) 0000000000050620 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHWEngine::MetaClass::MetaClass() 00000000000506c0 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHWEngine::MetaClass::MetaClass() 00000000003a2a30 __float128 0f SECT 08 0000 [.const_data] AMDRadeonX4000_AMDHWEngine::metaClass 000000000005065c __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHWEngine::AMDRadeonX4000_AMDHWEngine(OSMetaClass const*) 0000000000050690 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHWEngine::~AMDRadeonX4000_AMDHWEngine() 0000000000050686 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHWEngine::~AMDRadeonX4000_AMDHWEngine() 000000000005067c __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHWEngine::~AMDRadeonX4000_AMDHWEngine() 000000000052dd10 __float128 0f SECT 0a 0000 [__DATA.__common] AMDRadeonX4000_AMDHWMemory::gMetaClass 00000000003a6648 __float128 0f SECT 08 0000 [.const_data] AMDRadeonX4000_AMDHWMemory::superClass 000000000005482a __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHWMemory::canAllocate(unsigned long long, unsigned long long, bool) 00000000000547a2 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHWMemory::free_legacy(GLKMemoryElement*, IOAccelEvent*) 0000000000055526 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHWMemory::waitForIdle() 00000000000545cc __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHWMemory::getRangeInfo(eAMD_MEMORY_RANGE_TYPE, AMD_MEMORY_RANGE_INFO*) 00000000000548fa __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHWMemory::getAllocBytes(GLKMemoryElement*) 00000000000548a6 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHWMemory::getAllocBytes(AMDMemoryElement const*) 000000000005491a __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHWMemory::hasAllocation(AMDMemoryElement const*) 0000000000054552 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHWMemory::initRangeInfo() 000000000005474e __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHWMemory::reserve_legacy(GLKMemoryElement*, unsigned long long, unsigned long long, bool, _eOP_ORIGINATOR) 00000000000546ec __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHWMemory::allocate_legacy(GLKMemoryElement*, unsigned long long, unsigned long long, _eAMD_MEMORY_ALLOCATION_TYPE, bool, _eOP_ORIGINATOR, _eOP_TYPE) 0000000000054682 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHWMemory::allocate_legacy(GLKMemoryElement*, unsigned long long, unsigned long long, unsigned long long, unsigned long long, bool, _eOP_ORIGINATOR, _eOP_TYPE) 0000000000053ff4 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHWMemory::setVirtualSpace(IOMemoryDescriptor*) 0000000000054fe2 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHWMemory::totalFreeMemory() 000000000005409e __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHWMemory::enableAllocations() 000000000005460c __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHWMemory::getRangeStartSize(eAMD_MEMORY_RANGE_TYPE, unsigned long long*, unsigned long long*) 000000000005464c __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHWMemory::configureRangeInfo(eAMD_MEMORY_RANGE_TYPE, AMD_MEMORY_RANGE_INFO const*) 0000000000054190 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHWMemory::disableAllocations(bool) 00000000000550b4 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHWMemory::freeUnusedAperture(unsigned int) 0000000000054546 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHWMemory::setVirtualSpaceReady(bool) 0000000000054fb8 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHWMemory::totalFreeFixedMemory() 0000000000054b9a __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHWMemory::tryWaitForAllocation(GLKMemoryElement*, unsigned long long, unsigned long long, unsigned long long, unsigned long long) 0000000000054ff0 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHWMemory::allocateUnusedAperture(unsigned long long*, unsigned long long) 0000000000054fc6 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHWMemory::computeTotalFreeMemory(bool) 0000000000054434 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHWMemory::freeInUseMemoryElement(_sAMD_IN_USE_HW_MEMORY_DESCRIPTOR*, unsigned int) 00000000000547e6 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHWMemory::findInUseMemoryDescriptor(unsigned long long, unsigned int*) 00000000000544aa __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHWMemory::freeInUseMemoryDescriptor(_sAMD_IN_USE_HW_MEMORY_DESCRIPTOR*) 00000000000554f2 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHWMemory::handlepCleanupThreadTimer(OSObject*, IOTimerEventSource*) 00000000000552f8 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHWMemory::initInUseMemoryDescriptor(_sAMD_IN_USE_HW_MEMORY_DESCRIPTOR*) 000000000005538a __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHWMemory::waitForFreedMemoryToFinish(unsigned long long, unsigned long long) 000000000005454c __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHWMemory::setMemoryAllocationsEnabled(bool) 0000000000054acc __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHWMemory::allocateInUseMemoryDescriptor() 0000000000053fb2 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHWMemory::freeInUseMemoryDataStructures() 0000000000053e4e __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHWMemory::initInUseMemoryDataStructures() 00000000000543a6 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHWMemory::cleanupFinishedInUseMemoryElements() 0000000000054c44 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHWMemory::addInUseMemoryDescriptorToHashTable(_sAMD_IN_USE_HW_MEMORY_DESCRIPTOR*) 0000000000055100 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHWMemory::map(unsigned long long, unsigned long long, IOMemoryMap**, unsigned int) 0000000000054e2e __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHWMemory::free(AMDMemoryElement const*, IOAccelEvent*) 0000000000053e8a __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHWMemory::free() 0000000000053b6a __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHWMemory::init(AMDRadeonX4000_IAMDHWInterface*, unsigned int, unsigned int) 00000000000551cc __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHWMemory::read(unsigned long long, unsigned long long, unsigned char*, _eAMD_MEMORY_HDP_CLIENT) 00000000000551a2 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHWMemory::unmap(IOMemoryMap**) 00000000000552b2 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHWMemory::write(unsigned long long, unsigned long long, unsigned char*) 0000000000054d44 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHWMemory::reserve(AMDMemoryElement*, unsigned long long, unsigned long long, bool, _eOP_ORIGINATOR) 0000000000054c8a __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHWMemory::allocate(AMDMemoryElement*, unsigned long long, unsigned long long, _eAMD_MEMORY_ALLOCATION_TYPE, bool, _eOP_ORIGINATOR, _eOP_TYPE) 000000000005495c __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHWMemory::allocate(AMDMemoryElement*, unsigned long long, unsigned long long, unsigned long long, unsigned long long, bool, _eOP_ORIGINATOR, _eOP_TYPE) 0000000000053a90 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHWMemory::MetaClass::MetaClass() 0000000000053b30 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHWMemory::MetaClass::MetaClass() 00000000003a6640 __float128 0f SECT 08 0000 [.const_data] AMDRadeonX4000_AMDHWMemory::metaClass 0000000000053acc __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHWMemory::AMDRadeonX4000_AMDHWMemory(OSMetaClass const*) 0000000000053b00 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHWMemory::~AMDRadeonX4000_AMDHWMemory() 0000000000053af6 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHWMemory::~AMDRadeonX4000_AMDHWMemory() 0000000000053aec __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHWMemory::~AMDRadeonX4000_AMDHWMemory() 000000000052dea0 __float128 0f SECT 0a 0000 [__DATA.__common] AMDRadeonX4000_AMDHardware::gMetaClass 000000000005d0d6 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHardware::releaseIri(void*, _IRI_RELEASE_INPUT*) 00000000003a8278 __float128 0f SECT 08 0000 [.const_data] AMDRadeonX4000_AMDHardware::superClass 000000000005bf2e __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHardware::powerUpCAIL() 000000000005d2c8 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHardware::setRefClock(unsigned int) 000000000005ce86 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHardware::MCIL_WaitFor(void*, _MCIL_WAITFOR_INFO*) 000000000005b2bc __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHardware::getHWChannel(_eAMD_HW_ENGINE_TYPE, _eAMD_HW_RING_TYPE) 000000000005b2f2 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHardware::getHWChannel(int) 000000000005bdba __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHardware::cailIRIObtain() 000000000005c0c4 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHardware::postVBIOSCAIL() 000000000005bef6 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHardware::powerDownCAIL() 000000000005b3b6 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHardware::resetHardware(unsigned int) 000000000005ab84 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHardware::stopHWEngines() 000000000005d0ce __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHardware::MCIL_DebugPost(void*, unsigned int) 000000000005ab4a __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHardware::startHWEngines() 000000000005d3ae __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHardware::uvdControlCail(unsigned long, void*, void*) 000000000005d3c0 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHardware::vceControlCail(unsigned long, void*, void*) 000000000005ccc2 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHardware::MCIL_CopyMemory(void*, _MCIL_COPYMEM_INFO*) 000000000005cf66 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHardware::MCIL_IRI_Obtain(void*, _MCIL_IRI_OBTAIN_INPUT*, _MCIL_IRI_OBTAIN_OUTPUT*) 000000000005b796 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHardware::MCIL_Initialize(_MCIL_SERVICE_CALLBACKS*) 000000000005ccfc __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHardware::MCIL_ZeroMemory(void*, _MCIL_ZEROMEM_INFO*) 000000000005c10e __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHardware::getOSObjectData(OSObject*, void*, unsigned int) 000000000005be6a __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHardware::initAdapterCAIL() 000000000005b304 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHardware::registerChannel(AMDRadeonX4000_IAMDHWChannel*) 000000000005d3d2 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHardware::samuControlCail(unsigned long, void*, void*) 000000000005aa14 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHardware::allocateAMDHWVMM() 000000000005b516 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHardware::getASICHangState() 000000000005aad6 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHardware::powerUpHWEngines() 000000000005d0f8 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHardware::pplibIriFunction(void*, _IRI_CALL_INPUT*, _IRI_CALL_OUTPUT*) 000000000005c73a __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHardware::MCIL_ReadRomImage(void*, _MCIL_DATA_INFO*) 000000000005a9ee __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHardware::allocateAMDHWGart() 000000000005d730 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHardware::flushSystemCaches(void const*, unsigned int) 000000000005b39a __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHardware::getCailEngineType(_eAMD_HW_ENGINE_TYPE) 000000000005bb08 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHardware::initCAILParameter(unsigned long, long long) 000000000005ab10 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHardware::powerOffHWEngines() 000000000005a91a __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHardware::releaseHWChannels() 000000000005cb9a __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHardware::MCIL_ReleaseMemory(void*, _MCIL_MEMBLOCK_INFO*) 000000000005ca30 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHardware::MCIL_SyncExecution(void*, _MCIL_SYNEXECUTION_INFO*) 000000000005cc86 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHardware::MCIL_WaitForMCIdle(void*) 000000000005d644 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHardware::engineEnabledEvent(AMDRadeonX4000_IAMDHWEngine*) 000000000005d23a __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHardware::setStallParameters(unsigned int, unsigned int) 000000000005ca5e __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHardware::MCIL_AllocateMemory(void*, _MCIL_MEMBLOCK_INFO*) 000000000005c7f6 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHardware::MCIL_GetRegistrykey(void*, _MCIL_REGISTRY_INFO*) 000000000005ccaa __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHardware::MCIL_MapToGartSpace(void*, _MCIL_MEMBLOCK_INFO*) 000000000005cd3a __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHardware::MCIL_ModifyRegister(void*, _MCIL_MODIFYREGISTER_INFO*) 000000000005c998 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHardware::MCIL_SetRegistrykey(void*, _MCIL_REGISTRY_INFO*) 000000000005cc36 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHardware::MCIL_WaitForGUIIdle(void*) 000000000005aa3a __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHardware::allocateNullEngines() 000000000005d67e __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHardware::engineDisabledEvent(AMDRadeonX4000_IAMDHWEngine*) 000000000005d1c0 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHardware::enterDiagnosticMode() 000000000005ac8a __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHardware::freeWritebackMemory() 000000000005aa98 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHardware::initializeHWEngines() 000000000005b1d0 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHardware::freeCailReservations() 000000000005af72 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHardware::setVirtualSpaceReady(bool) 000000000005d94a __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHardware::writeDiagnosisReport(char*&, unsigned int&) 000000000005c36c __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHardware::MCIL_GetPciConfigData(void*, _MCIL_PCICONFIG_DATA*) 000000000005c47c __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHardware::MCIL_SetPciConfigData(void*, _MCIL_PCICONFIG_DATA*) 000000000005d6b8 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHardware::enableMultiEngineSync() 000000000005d604 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHardware::getEnabledEngineCount() 000000000005d3f8 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHardware::setReservedVRAMOffset(unsigned long long, unsigned long long) 000000000005a9c8 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHardware::allocateAMDHWRegisters() 000000000005a48a __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHardware::allocateNullHWChannels() 000000000005d6ec __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHardware::disableMultiEngineSync() 000000000005c0cc __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHardware::getAMDHardwareFromCail(void*) 000000000005a5c6 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHardware::getAllCailReservations(unsigned int, CAIL_BIOS_RESERVE_BLOCK*) 000000000005d3e4 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHardware::isValidCailReservation(unsigned int) 000000000005ccb6 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHardware::MCIL_UnmapFromGartSpace(void*, _MCIL_MEMBLOCK_INFO*) 000000000005abbe __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHardware::allocateWritebackMemory() 000000000005b108 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHardware::reserveCailReservations() 000000000005c782 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHardware::MCIL_DelayInMicroseconds(void*, unsigned int) 000000000005c7ea __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHardware::MCIL_SleepInMilliseconds(void*, unsigned int) 000000000005a95e __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHardware::allocateDiagReportBuffer() 000000000005a50a __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHardware::getNumOfCailReservations() 000000000005c560 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHardware::MCIL_GetAISCPciConfigData(void*, _MCIL_PCICONFIG_DATA*) 000000000005c64c __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHardware::MCIL_SetAISCPciConfigData(void*, _MCIL_PCICONFIG_DATA*) 000000000005a9a2 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHardware::allocateAMDHWAlignManager() 000000000005d5a2 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHardware::getReservedVRAMBaseOffset(_eAMD_MEMORY_ALLOCATION_TYPE) 000000000005b28c __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHardware::systemDidChangeSpeedEvent() 000000000005d4b4 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHardware::appendToReservedVRAMOffset(_eAMD_MEMORY_ALLOCATION_TYPE, unsigned long long, unsigned int) 000000000005b252 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHardware::systemWillChangeSpeedEvent() 000000000005aef2 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHardware::initializeHardwareRegisters() 000000000005b078 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHardware::setMemoryAllocationsEnabled(bool) 000000000005b37a __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHardware::getChannelWriteBackFrameAddr(int) 000000000005d2d4 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHardware::updateStallDisplayParameters() 000000000005b35a __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHardware::getChannelWriteBackFrameOffset(int) 000000000005bf66 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHardware::setupAndInitializeHWCapabilities() 000000000005d746 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHardware::writeASICHangLogInfoToDiagnosisReport(char*&, unsigned int&) 000000000005a6a0 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHardware::free() 0000000000059dea __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHardware::init(IOPCIDevice*, AMDRadeonX4000_IAMDHWHandler*, unsigned int&, unsigned int, _GART_PARAMETERS*, _FB_PARAMETERS*) 000000000005d20c __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHardware::initQSC() 000000000005acf8 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHardware::powerUp() 000000000005bb3c __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHardware::initCAIL() 000000000005ae32 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHardware::powerOff() 000000000005af34 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHardware::willWake() 0000000000059d10 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHardware::MetaClass::MetaClass() 0000000000059db0 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHardware::MetaClass::MetaClass() 00000000003a8270 __float128 0f SECT 08 0000 [.const_data] AMDRadeonX4000_AMDHardware::metaClass 000000000005b61e __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHardware::setupCAIL() 0000000000059d4c __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHardware::AMDRadeonX4000_AMDHardware(OSMetaClass const*) 0000000000059d80 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHardware::~AMDRadeonX4000_AMDHardware() 0000000000059d76 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHardware::~AMDRadeonX4000_AMDHardware() 0000000000059d6c __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHardware::~AMDRadeonX4000_AMDHardware() 000000000052d0e8 __float128 0f SECT 0a 0000 [__DATA.__common] AMDRadeonX4000_AMDSPUEvent::gMetaClass 000000000038fb60 __float128 0f SECT 08 0000 [.const_data] AMDRadeonX4000_AMDSPUEvent::superClass 000000000001b9b0 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDSPUEvent::timerHandler(OSObject*, IOTimerEventSource*) 000000000001ba20 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDSPUEvent::addTimedEvent(void (*)(OSObject*, void*), void*, unsigned int) 000000000001ba62 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDSPUEvent::removeTimedEvent() 000000000001b9d4 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDSPUEvent::free() 000000000001b96c __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDSPUEvent::init(IOWorkLoop*) 000000000001b7da __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDSPUEvent::MetaClass::MetaClass() 000000000001b89a __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDSPUEvent::MetaClass::MetaClass() 000000000038fb58 __float128 0f SECT 08 0000 [.const_data] AMDRadeonX4000_AMDSPUEvent::metaClass 000000000001b836 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDSPUEvent::AMDRadeonX4000_AMDSPUEvent(OSMetaClass const*) 000000000001b90c __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDSPUEvent::AMDRadeonX4000_AMDSPUEvent() 000000000001b816 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDSPUEvent::AMDRadeonX4000_AMDSPUEvent(OSMetaClass const*) 000000000001b93c __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDSPUEvent::AMDRadeonX4000_AMDSPUEvent() 000000000001b86a __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDSPUEvent::~AMDRadeonX4000_AMDSPUEvent() 000000000001b860 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDSPUEvent::~AMDRadeonX4000_AMDSPUEvent() 000000000001b856 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDSPUEvent::~AMDRadeonX4000_AMDSPUEvent() 00000000000277a4 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelTask::deallocate(IOAccelMemoryMap const*, unsigned long long) 000000000052d4a0 __float128 0f SECT 0a 0000 [__DATA.__common] AMDRadeonX4000_AMDAccelTask::gMetaClass 0000000000392c08 __float128 0f SECT 08 0000 [.const_data] AMDRadeonX4000_AMDAccelTask::superClass 00000000000278fa __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelTask::remapMappings(IOAccelMemoryMap**, unsigned int, unsigned long long) 00000000000278b2 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelTask::freeAllGPUMappings() 0000000000027870 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelTask::getCommandBufferPool(IOAccelChannel2*) 000000000002767c __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelTask::releaseCommandBufferPools() 000000000002759a __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelTask::free() 0000000000027432 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelTask::init(IOGraphicsAccelerator2*, bool) 0000000000027844 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelTask::reserve(unsigned int, unsigned long long, unsigned long long) 00000000000276b6 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelTask::allocate(IOAccelMemoryMap const*) 00000000000272a0 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelTask::MetaClass::MetaClass() 0000000000027360 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelTask::MetaClass::MetaClass() 0000000000392c00 __float128 0f SECT 08 0000 [.const_data] AMDRadeonX4000_AMDAccelTask::metaClass 00000000000272fc __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelTask::AMDRadeonX4000_AMDAccelTask(OSMetaClass const*) 00000000000273d2 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelTask::AMDRadeonX4000_AMDAccelTask() 00000000000272dc __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelTask::AMDRadeonX4000_AMDAccelTask(OSMetaClass const*) 0000000000027402 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelTask::AMDRadeonX4000_AMDAccelTask() 0000000000027330 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelTask::~AMDRadeonX4000_AMDAccelTask() 0000000000027326 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelTask::~AMDRadeonX4000_AMDAccelTask() 000000000002731c __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelTask::~AMDRadeonX4000_AMDAccelTask() 000000000052d888 __float128 0f SECT 0a 0000 [__DATA.__common] AMDRadeonX4000_AMDHWChannel::gMetaClass 00000000003a0b28 __float128 0f SECT 08 0000 [.const_data] AMDRadeonX4000_AMDHWChannel::superClass 0000000000049272 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHWChannel::waitForIdle() 000000000004a09c __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHWChannel::setDebugFlags(unsigned int) 000000000004a0a8 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHWChannel::clearDebugFlags(unsigned int) 0000000000049d02 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHWChannel::processAllWaits(unsigned int, vendevtBarrierRec*, unsigned int, unsigned int*, unsigned int) 000000000004909a __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHWChannel::setEventMachine(IOAccelEventMachine2*) 0000000000049a58 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHWChannel::getSemaphoreData(unsigned int) 0000000000049318 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHWChannel::waitForTimestamp(unsigned int, unsigned long long*, bool) 000000000004963c __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHWChannel::checkForTimestamp(unsigned int) 0000000000049bc8 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHWChannel::writeWaitCommands(int, unsigned int, unsigned int*, unsigned int) 000000000004a1ac __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHWChannel::isTimeStampExpired(unsigned int) 0000000000049118 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHWChannel::limitedWaitForIdle(unsigned int, unsigned int) 000000000004a1de __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHWChannel::vblEnableInterrupt() 0000000000049702 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHWChannel::submitCommandBuffer(AMD_SUBMIT_COMMAND_BUFFER_INFO*, unsigned int*) 000000000004a264 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHWChannel::vblDisableInterrupt() 000000000004904e __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHWChannel::alignIBCommandBuffer(unsigned int*, unsigned int) 0000000000048c96 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHWChannel::getWaitSemaphoreData(unsigned int) 0000000000048cbc __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHWChannel::initStatisticsGroups() 000000000004a6b6 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHWChannel::writeDiagnosisReport(char*&, unsigned int&) 000000000004a60a __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHWChannel::hasPendingWaitCommands(unsigned int) 000000000004a58c __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHWChannel::timeStampInterruptType() 000000000004a088 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHWChannel::writeEventWriteCommand(unsigned int*, unsigned int, unsigned int) 0000000000049e76 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHWChannel::waitForCommandRingSpace(unsigned int, unsigned int) 000000000004a07e __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHWChannel::writeSurfaceSyncCommand(unsigned int*, unsigned int, unsigned long long, unsigned long long, unsigned int) 00000000000496ca __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHWChannel::setCommandTimestampPairs(unsigned int*, unsigned int*) 00000000000496a2 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHWChannel::getCommandSubmitTimestamp() 000000000004a4ae __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHWChannel::timeStampDisableInterrupt() 000000000004a092 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHWChannel::writeEventWriteEOPCommand(unsigned int*, unsigned int, unsigned int, unsigned long long, unsigned int, unsigned int, unsigned long long) 000000000004a594 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHWChannel::registerTimestampInterrupt() 000000000004a0b6 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHWChannel::timeStampInterruptCallback(OSObject*, void*) 00000000000496b2 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHWChannel::getCommandLastReadTimestamp() 0000000000049a72 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHWChannel::recordAndWriteChannelSignal(unsigned int, unsigned int*, unsigned int) 0000000000049672 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHWChannel::waitForLastSubmittedTimestamp() 000000000004a2da __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHWChannel::timeStampEnableInterruptAndSleep(unsigned int) 0000000000048db6 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHWChannel::free() 00000000000488fa __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHWChannel::init(int, AMDRadeonX4000_IAMDHWInterface*, AMDRadeonX4000_IAMDHWEngine*, AMDRadeonX4000_IAMDHWRing*, char const*) 0000000000049106 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHWChannel::isIdle() 00000000000490f4 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHWChannel::isEmpty() 0000000000048820 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHWChannel::MetaClass::MetaClass() 00000000000488c0 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHWChannel::MetaClass::MetaClass() 00000000000490e2 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHWChannel::isEnabled() 00000000003a0b20 __float128 0f SECT 08 0000 [.const_data] AMDRadeonX4000_AMDHWChannel::metaClass 000000000004885c __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHWChannel::AMDRadeonX4000_AMDHWChannel(OSMetaClass const*) 0000000000048890 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHWChannel::~AMDRadeonX4000_AMDHWChannel() 0000000000048886 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHWChannel::~AMDRadeonX4000_AMDHWChannel() 000000000004887c __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHWChannel::~AMDRadeonX4000_AMDHWChannel() 000000000052d8b0 __float128 0f SECT 0a 0000 [__DATA.__common] AMDRadeonX4000_AMDHWDisplay::gMetaClass 00000000003a0ec8 __float128 0f SECT 08 0000 [.const_data] AMDRadeonX4000_AMDHWDisplay::superClass 000000000004c52c __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHWDisplay::FEDSShutdown() 000000000004d278 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHWDisplay::addVblankFlip(unsigned int, IOAccelResource2*, IOAccelResource2*, unsigned int) 000000000004ce06 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHWDisplay::canVblankFlip(unsigned int) 000000000004be5c __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHWDisplay::detectBuiltIn() 000000000004dc0e __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHWDisplay::getDesktopSize() 000000000004b29a __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHWDisplay::getDisplayInfo(unsigned int, bool, bool, void*, _FRAMEBUFFER_INFO*) 000000000004d9ee __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHWDisplay::setFrameBuffer(unsigned int) 000000000004da4c __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHWDisplay::resetDisplayMap() 000000000004bd02 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHWDisplay::configureDisplay(unsigned int, unsigned int, _FRAMEBUFFER_INFO*, IOAccelResource2*) 000000000004b250 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHWDisplay::isDisplayEnabled(unsigned int) 000000000004b0c8 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHWDisplay::restoreRegisters(unsigned int, unsigned long long) 000000000004c10a __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHWDisplay::setAMDBltManager(AMDRadeonX4000_AMDBltMgr*) 000000000004ceca __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHWDisplay::submitVblankFlip(unsigned int) 000000000004c5bc __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHWDisplay::FEDSUpdateDisplay() 000000000004c14e __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHWDisplay::allocateScanoutFB(unsigned int, IOAccelResource2*, IOAccelResource2*, unsigned long long*) 000000000004d9a6 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHWDisplay::setDisplayMirrored(unsigned int, unsigned int) 000000000004c980 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHWDisplay::FEDSResetFullScreen(unsigned int) 000000000004c7be __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHWDisplay::FEDSSetupFullScreen(unsigned int, unsigned int) 000000000004da78 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHWDisplay::getMirroredDisplays(unsigned int, unsigned int*) 000000000004b01a __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHWDisplay::initializeRegisters() 000000000004d608 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHWDisplay::clearVblankFlipQueue(unsigned int) 000000000004cb58 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHWDisplay::updateCombinedStatus() 000000000004d7da __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHWDisplay::addVblankFlipRegister(AMD_VBLANK_FLIP_ELEM*, unsigned int, unsigned int, unsigned int) 000000000004c772 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHWDisplay::FEDSUpdateSwapTimestamp(unsigned int, unsigned int) 000000000004d950 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHWDisplay::getCurrentDisplayOffset(unsigned int) 000000000004c792 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHWDisplay::FEDSUpdateBufferDirtyBit(unsigned int, bool) 000000000004c5b4 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHWDisplay::FEDSWriteUBMBlitToCmdBuf(unsigned int*, unsigned int, bool, unsigned int, IOAccelResource2*) 000000000004d814 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHWDisplay::savePrimarySurfaceOffsets() 000000000004cdf0 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHWDisplay::getNumScheduledVblankFlips(unsigned int) 000000000004dae2 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHWDisplay::getTimingDisplayParameters(unsigned int, unsigned int*, unsigned int*, unsigned int*) 000000000004d7f6 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHWDisplay::isBufferScheduledForDisplay(unsigned int, unsigned long long) 000000000004d8cc __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHWDisplay::restorePrimarySurfaceOffsets() 000000000004cd1e __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHWDisplay::writeUpdateTilingControlRegisters(unsigned int, unsigned int*, unsigned int, IOAccelResource2*, bool) 000000000004cb86 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHWDisplay::writeUpdateFrameBufferOffsetCommands(unsigned int, unsigned int*, unsigned int, unsigned int, IOAccelResource2*, IOAccelResource2*, IOAccelResource2*) 000000000004ae28 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHWDisplay::free() 000000000004aaaa __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHWDisplay::init(AMDRadeonX4000_IAMDHWInterface*, _FB_PARAMETERS*) 000000000004a9d0 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHWDisplay::MetaClass::MetaClass() 000000000004aa70 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHWDisplay::MetaClass::MetaClass() 00000000003a0ec0 __float128 0f SECT 08 0000 [.const_data] AMDRadeonX4000_AMDHWDisplay::metaClass 000000000004aa0c __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHWDisplay::AMDRadeonX4000_AMDHWDisplay(OSMetaClass const*) 000000000004aa40 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHWDisplay::~AMDRadeonX4000_AMDHWDisplay() 000000000004aa36 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHWDisplay::~AMDRadeonX4000_AMDHWDisplay() 000000000004aa2c __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHWDisplay::~AMDRadeonX4000_AMDHWDisplay() 000000000052d860 __float128 0f SECT 0a 0000 [__DATA.__common] AMDRadeonX4000_AMDHWHandler::gMetaClass 00000000003a07a8 __float128 0f SECT 08 0000 [.const_data] AMDRadeonX4000_AMDHWHandler::superClass 0000000000048546 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHWHandler::addStatsGroup(AMDRadeonX4000_AMDAccelStatisticsGroup*) 0000000000048020 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHWHandler::sendPMCommand(void*) 000000000004809a __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHWHandler::doAtomicMemcpy(unsigned long long, unsigned long long, unsigned int, bool, bool) 00000000000482a6 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHWHandler::doAtomicMemset(unsigned long long, unsigned int, unsigned int, bool) 0000000000048562 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHWHandler::freeStatsGroup(AMDRadeonX4000_AMDAccelStatisticsGroup*) 00000000000484e2 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHWHandler::setupWritebackSync(int, unsigned int*) 000000000004852a __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHWHandler::validateStatsGroup(char const*) 00000000000484d4 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHWHandler::initPlistProperties(char const*) 0000000000047f0a __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHWHandler::resetRenderingContext() 0000000000047f10 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHWHandler::createCommandBufferPool(AMDRadeonX4000_IAMDHWChannel*, int, int) 0000000000048494 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHWHandler::hasTripleBufferedSurface(unsigned int) 000000000004802e __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHWHandler::getUVDReservedAreaAddress() 0000000000048004 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHWHandler::setTimestampInterruptState(void*, unsigned int) 0000000000048012 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHWHandler::unregisterTimestampInterrupt(void*) 0000000000047ff6 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHWHandler::registerForTimestampInterrupt(unsigned int, void (*)(OSObject*, void*), OSObject*, void*, void**) 0000000000047ef8 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHWHandler::free() 0000000000047ec2 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHWHandler::init(AMDRadeonX4000_AMDGraphicsAccelerator*) 0000000000047d30 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHWHandler::MetaClass::MetaClass() 0000000000047df0 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHWHandler::MetaClass::MetaClass() 00000000003a07a0 __float128 0f SECT 08 0000 [.const_data] AMDRadeonX4000_AMDHWHandler::metaClass 0000000000047d8c __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHWHandler::AMDRadeonX4000_AMDHWHandler(OSMetaClass const*) 0000000000047e62 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHWHandler::AMDRadeonX4000_AMDHWHandler() 0000000000047d6c __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHWHandler::AMDRadeonX4000_AMDHWHandler(OSMetaClass const*) 0000000000047e92 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHWHandler::AMDRadeonX4000_AMDHWHandler() 0000000000047dc0 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHWHandler::~AMDRadeonX4000_AMDHWHandler() 0000000000047db6 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHWHandler::~AMDRadeonX4000_AMDHWHandler() 0000000000047dac __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHWHandler::~AMDRadeonX4000_AMDHWHandler() 000000000052d228 __float128 0f SECT 0a 0000 [__DATA.__common] AMDRadeonX4000_AMDHashTable::gMetaClass 0000000000390f68 __float128 0f SECT 08 0000 [.const_data] AMDRadeonX4000_AMDHashTable::superClass 0000000000024e5e __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHashTable::startIterator() 0000000000024ea8 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHashTable::getNextIterator() 0000000000024e32 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHashTable::freeTableElement(_sAMD_HASH_TABLE_ELEMENT*) 0000000000024d20 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHashTable::allocateTableElement() 0000000000024cc6 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHashTable::add(unsigned int, void*, unsigned int) 0000000000024bf0 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHashTable::free() 0000000000024b92 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHashTable::init() 0000000000024c3e __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHashTable::clear() 0000000000024d78 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHashTable::remove(unsigned int) 0000000000024a00 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHashTable::MetaClass::MetaClass() 0000000000024ac0 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHashTable::MetaClass::MetaClass() 0000000000390f60 __float128 0f SECT 08 0000 [.const_data] AMDRadeonX4000_AMDHashTable::metaClass 0000000000024a5c __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHashTable::AMDRadeonX4000_AMDHashTable(OSMetaClass const*) 0000000000024b32 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHashTable::AMDRadeonX4000_AMDHashTable() 0000000000024a3c __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHashTable::AMDRadeonX4000_AMDHashTable(OSMetaClass const*) 0000000000024b62 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHashTable::AMDRadeonX4000_AMDHashTable() 0000000000024a90 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHashTable::~AMDRadeonX4000_AMDHashTable() 0000000000024a86 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHashTable::~AMDRadeonX4000_AMDHashTable() 0000000000024a7c __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHashTable::~AMDRadeonX4000_AMDHashTable() 000000000052ef08 __float128 0f SECT 0a 0000 [__DATA.__common] AMDRadeonX4000_AMDSMLSPUMsg::gMetaClass 00000000003c18a8 __float128 0f SECT 08 0000 [.const_data] AMDRadeonX4000_AMDSMLSPUMsg::superClass 0000000000125b52 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDSMLSPUMsg::free() 0000000000125ad2 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDSMLSPUMsg::init(void*) 0000000000125b64 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDSMLSPUMsg::getEvent() 0000000000125940 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDSMLSPUMsg::MetaClass::MetaClass() 0000000000125a00 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDSMLSPUMsg::MetaClass::MetaClass() 00000000003c18a0 __float128 0f SECT 08 0000 [.const_data] AMDRadeonX4000_AMDSMLSPUMsg::metaClass 000000000012599c __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDSMLSPUMsg::AMDRadeonX4000_AMDSMLSPUMsg(OSMetaClass const*) 0000000000125a72 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDSMLSPUMsg::AMDRadeonX4000_AMDSMLSPUMsg() 000000000012597c __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDSMLSPUMsg::AMDRadeonX4000_AMDSMLSPUMsg(OSMetaClass const*) 0000000000125aa2 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDSMLSPUMsg::AMDRadeonX4000_AMDSMLSPUMsg() 00000000001259d0 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDSMLSPUMsg::~AMDRadeonX4000_AMDSMLSPUMsg() 00000000001259c6 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDSMLSPUMsg::~AMDRadeonX4000_AMDSMLSPUMsg() 00000000001259bc __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDSMLSPUMsg::~AMDRadeonX4000_AMDSMLSPUMsg() 000000000052dc70 __float128 0f SECT 0a 0000 [__DATA.__common] AMDRadeonX4000_IAMDHWEngine::gMetaClass 00000000003a5a20 __float128 0f SECT 08 0000 [.const_data] AMDRadeonX4000_IAMDHWEngine::superClass 0000000000053072 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_IAMDHWEngine::MetaClass::MetaClass() 0000000000053112 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_IAMDHWEngine::MetaClass::MetaClass() 00000000003a5a18 __float128 0f SECT 08 0000 [.const_data] AMDRadeonX4000_IAMDHWEngine::metaClass 00000000000530ae __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_IAMDHWEngine::AMDRadeonX4000_IAMDHWEngine(OSMetaClass const*) 00000000000530e2 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_IAMDHWEngine::~AMDRadeonX4000_IAMDHWEngine() 00000000000530d8 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_IAMDHWEngine::~AMDRadeonX4000_IAMDHWEngine() 00000000000530ce __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_IAMDHWEngine::~AMDRadeonX4000_IAMDHWEngine() 000000000052db30 __float128 0f SECT 0a 0000 [__DATA.__common] AMDRadeonX4000_IAMDHWMemory::gMetaClass 00000000003a4530 __float128 0f SECT 08 0000 [.const_data] AMDRadeonX4000_IAMDHWMemory::superClass 00000000000529a2 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_IAMDHWMemory::MetaClass::MetaClass() 0000000000052a42 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_IAMDHWMemory::MetaClass::MetaClass() 00000000003a4528 __float128 0f SECT 08 0000 [.const_data] AMDRadeonX4000_IAMDHWMemory::metaClass 00000000000529de __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_IAMDHWMemory::AMDRadeonX4000_IAMDHWMemory(OSMetaClass const*) 0000000000052a12 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_IAMDHWMemory::~AMDRadeonX4000_IAMDHWMemory() 0000000000052a08 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_IAMDHWMemory::~AMDRadeonX4000_IAMDHWMemory() 00000000000529fe __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_IAMDHWMemory::~AMDRadeonX4000_IAMDHWMemory() 000000000052d7e8 __float128 0f SECT 0a 0000 [__DATA.__common] AMDTongaGraphicsAccelerator::gMetaClass 000000000039ed88 __float128 0f SECT 08 0000 [.const_data] AMDTongaGraphicsAccelerator::superClass 0000000000046c08 __float128 0f SECT 01 0000 [.text] AMDTongaGraphicsAccelerator::setDeviceType(IOPCIDevice*) 0000000000046be2 __float128 0f SECT 01 0000 [.text] AMDTongaGraphicsAccelerator::newHWInterface() 0000000000046a50 __float128 0f SECT 01 0000 [.text] AMDTongaGraphicsAccelerator::MetaClass::MetaClass() 0000000000046b10 __float128 0f SECT 01 0000 [.text] AMDTongaGraphicsAccelerator::MetaClass::MetaClass() 000000000039ed80 __float128 0f SECT 08 0000 [.const_data] AMDTongaGraphicsAccelerator::metaClass 0000000000046aac __float128 0f SECT 01 0000 [.text] AMDTongaGraphicsAccelerator::AMDTongaGraphicsAccelerator(OSMetaClass const*) 0000000000046b82 __float128 0f SECT 01 0000 [.text] AMDTongaGraphicsAccelerator::AMDTongaGraphicsAccelerator() 0000000000046a8c __float128 0f SECT 01 0000 [.text] AMDTongaGraphicsAccelerator::AMDTongaGraphicsAccelerator(OSMetaClass const*) 0000000000046bb2 __float128 0f SECT 01 0000 [.text] AMDTongaGraphicsAccelerator::AMDTongaGraphicsAccelerator() 0000000000046ae0 __float128 0f SECT 01 0000 [.text] AMDTongaGraphicsAccelerator::~AMDTongaGraphicsAccelerator() 0000000000046ad6 __float128 0f SECT 01 0000 [.text] AMDTongaGraphicsAccelerator::~AMDTongaGraphicsAccelerator() 0000000000046acc __float128 0f SECT 01 0000 [.text] AMDTongaGraphicsAccelerator::~AMDTongaGraphicsAccelerator() 000000000052d5b8 __float128 0f SECT 0a 0000 [__DATA.__common] AMDVerdeGraphicsAccelerator::gMetaClass 0000000000395a18 __float128 0f SECT 08 0000 [.const_data] AMDVerdeGraphicsAccelerator::superClass 0000000000029a52 __float128 0f SECT 01 0000 [.text] AMDVerdeGraphicsAccelerator::newHWInterface() 00000000000298c0 __float128 0f SECT 01 0000 [.text] AMDVerdeGraphicsAccelerator::MetaClass::MetaClass() 0000000000029980 __float128 0f SECT 01 0000 [.text] AMDVerdeGraphicsAccelerator::MetaClass::MetaClass() 0000000000395a10 __float128 0f SECT 08 0000 [.const_data] AMDVerdeGraphicsAccelerator::metaClass 000000000002991c __float128 0f SECT 01 0000 [.text] AMDVerdeGraphicsAccelerator::AMDVerdeGraphicsAccelerator(OSMetaClass const*) 00000000000299f2 __float128 0f SECT 01 0000 [.text] AMDVerdeGraphicsAccelerator::AMDVerdeGraphicsAccelerator() 00000000000298fc __float128 0f SECT 01 0000 [.text] AMDVerdeGraphicsAccelerator::AMDVerdeGraphicsAccelerator(OSMetaClass const*) 0000000000029a22 __float128 0f SECT 01 0000 [.text] AMDVerdeGraphicsAccelerator::AMDVerdeGraphicsAccelerator() 0000000000029950 __float128 0f SECT 01 0000 [.text] AMDVerdeGraphicsAccelerator::~AMDVerdeGraphicsAccelerator() 0000000000029946 __float128 0f SECT 01 0000 [.text] AMDVerdeGraphicsAccelerator::~AMDVerdeGraphicsAccelerator() 000000000002993c __float128 0f SECT 01 0000 [.text] AMDVerdeGraphicsAccelerator::~AMDVerdeGraphicsAccelerator() 000000000052d748 __float128 0f SECT 0a 0000 [__DATA.__common] AMDHawaiiGraphicsAccelerator::gMetaClass 000000000039c518 __float128 0f SECT 08 0000 [.const_data] AMDHawaiiGraphicsAccelerator::superClass 000000000003d5b2 __float128 0f SECT 01 0000 [.text] AMDHawaiiGraphicsAccelerator::newHWInterface() 000000000003d420 __float128 0f SECT 01 0000 [.text] AMDHawaiiGraphicsAccelerator::MetaClass::MetaClass() 000000000003d4e0 __float128 0f SECT 01 0000 [.text] AMDHawaiiGraphicsAccelerator::MetaClass::MetaClass() 000000000039c510 __float128 0f SECT 08 0000 [.const_data] AMDHawaiiGraphicsAccelerator::metaClass 000000000003d47c __float128 0f SECT 01 0000 [.text] AMDHawaiiGraphicsAccelerator::AMDHawaiiGraphicsAccelerator(OSMetaClass const*) 000000000003d552 __float128 0f SECT 01 0000 [.text] AMDHawaiiGraphicsAccelerator::AMDHawaiiGraphicsAccelerator() 000000000003d45c __float128 0f SECT 01 0000 [.text] AMDHawaiiGraphicsAccelerator::AMDHawaiiGraphicsAccelerator(OSMetaClass const*) 000000000003d582 __float128 0f SECT 01 0000 [.text] AMDHawaiiGraphicsAccelerator::AMDHawaiiGraphicsAccelerator() 000000000003d4b0 __float128 0f SECT 01 0000 [.text] AMDHawaiiGraphicsAccelerator::~AMDHawaiiGraphicsAccelerator() 000000000003d4a6 __float128 0f SECT 01 0000 [.text] AMDHawaiiGraphicsAccelerator::~AMDHawaiiGraphicsAccelerator() 000000000003d49c __float128 0f SECT 01 0000 [.text] AMDHawaiiGraphicsAccelerator::~AMDHawaiiGraphicsAccelerator() 000000000052d388 __float128 0f SECT 0a 0000 [__DATA.__common] AMDRadeonX4000_AMDLinkedList::gMetaClass 0000000000391198 __float128 0f SECT 08 0000 [.const_data] AMDRadeonX4000_AMDLinkedList::superClass 0000000000025488 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDLinkedList::startIterator() 00000000000254aa __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDLinkedList::fini{censored}erator() 0000000000025456 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDLinkedList::freeListElement(_sAMD_LINKED_LIST_ELEMENT*) 00000000000254c0 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDLinkedList::getNextIterator() 0000000000025396 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDLinkedList::allocateListElement(void const*) 00000000000254dc __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDLinkedList::deleteCurrentIterator() 000000000002531a __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDLinkedList::add(void*) 000000000002528c __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDLinkedList::free() 0000000000025232 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDLinkedList::init() 00000000000253c8 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDLinkedList::push(void*) 00000000000252ba __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDLinkedList::clear() 00000000000250a0 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDLinkedList::MetaClass::MetaClass() 0000000000025160 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDLinkedList::MetaClass::MetaClass() 0000000000391190 __float128 0f SECT 08 0000 [.const_data] AMDRadeonX4000_AMDLinkedList::metaClass 00000000000250fc __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDLinkedList::AMDRadeonX4000_AMDLinkedList(OSMetaClass const*) 00000000000251d2 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDLinkedList::AMDRadeonX4000_AMDLinkedList() 00000000000250dc __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDLinkedList::AMDRadeonX4000_AMDLinkedList(OSMetaClass const*) 0000000000025202 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDLinkedList::AMDRadeonX4000_AMDLinkedList() 0000000000025130 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDLinkedList::~AMDRadeonX4000_AMDLinkedList() 0000000000025126 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDLinkedList::~AMDRadeonX4000_AMDLinkedList() 000000000002511c __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDLinkedList::~AMDRadeonX4000_AMDLinkedList() 000000000052d110 __float128 0f SECT 0a 0000 [__DATA.__common] AMDRadeonX4000_AMDSPUContext::gMetaClass 000000000001d77a __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDSPUContext::hdcpUnLoad(unsigned int) 000000000001d1a4 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDSPUContext::sendAppMsg(AMDRadeonX4000_AMDSPUAppContext*, AMDRadeonX4000_AMDSMLSPUMsg*) 000000000038fda0 __float128 0f SECT 08 0000 [.const_data] AMDRadeonX4000_AMDSPUContext::superClass 000000000001ccf2 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDSPUContext::loadAppCode(_AMD_SPU_APP_TYPE, unsigned long long, unsigned int) 000000000001d09c __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDSPUContext::createAppMsg(_AMD_SPU_MSG_TYPE, void*) 000000000001e168 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDSPUContext::fairplayLoad(unsigned int*) 000000000001d104 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDSPUContext::destroyAppMsg(AMDRadeonX4000_AMDSMLSPUMsg*) 000000000001c758 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDSPUContext::getAppContext(unsigned int) 000000000001bf8c __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDSPUContext::initSPUThread() 000000000001d1dc __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDSPUContext::processAppMsg(AMDRadeonX4000_AMDSPUAppContext*, AMDRadeonX4000_AMDSMLSPUMsg*) 000000000001dce4 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDSPUContext::processFPInit(sAMDSPUContextMsgIn*, sAMDSPUContextMsgOut*) 000000000001cb4a __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDSPUContext::processSPUMsg(IOFramebuffer*, void*) 000000000001d416 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDSPUContext::setTimedEvent(AMDRadeonX4000_AMDSPUEvent*, void*, _SPUEventType, unsigned int) 000000000001d172 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDSPUContext::waitForAppMsg(AMDRadeonX4000_AMDSMLSPUMsg*) 000000000001c568 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDSPUContext::checkStatusErr() 000000000001e1fa __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDSPUContext::fairplayUnload(unsigned int) 000000000001ccc2 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDSPUContext::findAppContext(_AMD_SPU_APP_TYPE, unsigned int*) 000000000001daa4 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDSPUContext::hdcpLinkStatus(_AmdHdcpMessageSPU*) 000000000001e7dc __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDSPUContext::processMailbox(sAMDSPUContextMsgIn*) 000000000001e054 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDSPUContext::releaseMailbox() 000000000001e7f6 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDSPUContext::allocateMailbox(unsigned int) 000000000001c3c6 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDSPUContext::enableSPUThread() 000000000001e698 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDSPUContext::fairplayEncrypt(_SPUCMDPARAM_FP_ENCRYPT*) 000000000001e21e __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDSPUContext::fairplayGetCert(_SPUCMDPARAM_FP_GET_CERT*) 000000000001d468 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDSPUContext::processhdcpInit(_SPUHDCPEventParam*) 000000000001cbc2 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDSPUContext::createAppContext(_AMD_SPU_APP_TYPE, unsigned int*, AMDRadeonX4000_AMDSPUAppContext**) 000000000001c4a6 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDSPUContext::disableSPUThread() 000000000001c9bc __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDSPUContext::getCommandBuffer() 000000000001d9c8 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDSPUContext::hdcpCloseSession(_SPUCMDPARAM_HDCP_CLOSE_SESSION*) 000000000001e094 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDSPUContext::processFPEncrypt(sAMDSPUContextMsgIn*, unsigned long long, unsigned long long, unsigned long long*) 000000000001dd4c __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDSPUContext::processFPGetCert(sAMDSPUContextMsgIn*, unsigned long long) 000000000001dfd0 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDSPUContext::processFPRelease() 000000000001c2b0 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDSPUContext::releaseSPUThread() 000000000001c686 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDSPUContext::handleSPUMsgEvent(OSObject*, void*) 000000000001cc8c __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDSPUContext::releaseAppContext(unsigned int) 000000000001e866 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDSPUContext::setPremiumContent(bool) 000000000001e366 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDSPUContext::fairplayGenASMFKey(_SPUCMDPARAM_FP_GEN_ASMF_KEY*) 000000000001c770 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDSPUContext::handleSPUHDCPEvent(OSObject*, void*) 000000000001c976 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDSPUContext::clientMemoryForType(unsigned int, unsigned int*, IOMemoryDescriptor**) 000000000001e554 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDSPUContext::fairplayTestASMFKey(_SPUCMDPARAM_FP_TEST_ASMF_KEY*) 000000000001d79e __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDSPUContext::hdcpOpenSessionInit(AMDRadeonX4000_AMDSMLSPUMsg*, _AmdHdcpMessageSPU*) 000000000001de0c __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDSPUContext::processFPGenASMFKey(sAMDSPUContextMsgIn*, unsigned long long, unsigned long long, unsigned long long*) 000000000001caa6 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDSPUContext::submitCommandBuffer(_SPUCmdBuffers*) 000000000001c588 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDSPUContext::handleSPUThreadTimer(OSObject*, IOTimerEventSource*) 000000000001defc __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDSPUContext::processFPTestASMFKey(sAMDSPUContextMsgIn*, unsigned long long, unsigned long long, unsigned long long*) 000000000001ca2e __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDSPUContext::getGPCOMCommandBuffer() 000000000001d664 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDSPUContext::processhdcpLinkStatus(_SPUHDCPEventParam*) 000000000001c52a __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDSPUContext::setSuspendResumeState(bool) 000000000001e4ae __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDSPUContext::fairplayReleaseSession(_SPUCMDPARAM_FP_RELEASE_HW_SESSION*) 000000000001d936 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDSPUContext::hdcpOpenSessionComplete(AMDRadeonX4000_AMDSMLSPUMsg*) 000000000001cafc __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDSPUContext::submitGPCOMCommandBuffer(_SPUCmdBuffers*) 000000000001c83e __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDSPUContext::setMemoryAllocationsEnabled(bool) 000000000001c060 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDSPUContext::free() 000000000001bc28 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDSPUContext::init(AMDRadeonX4000_AMDGraphicsAccelerator*, AMDRadeonX4000_IAMDHWInterface*) 000000000001c40a __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDSPUContext::stop(bool) 000000000001c360 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDSPUContext::start() 000000000001ce3e __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDSPUContext::loadApp(AMDRadeonX4000_AMDSPUAppContext*) 000000000001d6f6 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDSPUContext::hdcpLoad(unsigned int*) 000000000001d368 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDSPUContext::setEvent(void*, _SPUEventType) 000000000001ba96 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDSPUContext::MetaClass::MetaClass() 000000000001bb56 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDSPUContext::MetaClass::MetaClass() 000000000038fd98 __float128 0f SECT 08 0000 [.const_data] AMDRadeonX4000_AMDSPUContext::metaClass 000000000001cfbc __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDSPUContext::unloadApp(AMDRadeonX4000_AMDSPUAppContext*) 000000000001baf2 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDSPUContext::AMDRadeonX4000_AMDSPUContext(OSMetaClass const*) 000000000001bbc8 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDSPUContext::AMDRadeonX4000_AMDSPUContext() 000000000001bad2 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDSPUContext::AMDRadeonX4000_AMDSPUContext(OSMetaClass const*) 000000000001bbf8 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDSPUContext::AMDRadeonX4000_AMDSPUContext() 000000000001bb26 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDSPUContext::~AMDRadeonX4000_AMDSPUContext() 000000000001bb1c __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDSPUContext::~AMDRadeonX4000_AMDSPUContext() 000000000001bb12 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDSPUContext::~AMDRadeonX4000_AMDSPUContext() 000000000001fb4c __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDTPTManager::fillBuffer(unsigned long long, unsigned int, unsigned int) 000000000052d160 __float128 0f SECT 0a 0000 [__DATA.__common] AMDRadeonX4000_AMDTPTManager::gMetaClass 0000000000390378 __float128 0f SECT 08 0000 [.const_data] AMDRadeonX4000_AMDTPTManager::superClass 000000000001fb96 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDTPTManager::doSurfaceCopy(sDTCParametersIn*, sDTCParametersOut*, _AMDTPTMemory*, _AMDTPTMemory*) 000000000001faae __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDTPTManager::releaseBuffer(_AMDTPTMemory*, unsigned int) 00000000000211f0 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDTPTManager::doBiDirMemCopy(sDTCParametersIn*, sDTCParametersOut*, _AMDTPTMemory*, _AMDTPTMemory*) 000000000002160c __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDTPTManager::doDRMDMAMemcpy(sDTCParametersIn*, sDTCParametersOut*, _AMDTPTMemory*, _AMDTPTMemory*, _DRMDMA_AES*) 000000000001f394 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDTPTManager::processDTCVector(sDTCParametersIn*, sDTCParametersOut*) 000000000001f978 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDTPTManager::allocateSysBuffer(_AMDTPTMemory*, unsigned int) 000000000001fa54 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDTPTManager::allocateVRAMBuffer(_AMDTPTMemory*, unsigned int) 00000000000204a8 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDTPTManager::doBiDirSurfaceCopy(sDTCParametersIn*, sDTCParametersOut*, _AMDTPTMemory*, _AMDTPTMemory*) 000000000001f328 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDTPTManager::free() 000000000001f2b2 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDTPTManager::init(AMDRadeonX4000_AMDGraphicsAccelerator*) 000000000001f120 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDTPTManager::MetaClass::MetaClass() 000000000001f1e0 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDTPTManager::MetaClass::MetaClass() 0000000000020df4 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDTPTManager::doMemCopy(sDTCParametersIn*, sDTCParametersOut*, _AMDTPTMemory*, _AMDTPTMemory*) 0000000000390370 __float128 0f SECT 08 0000 [.const_data] AMDRadeonX4000_AMDTPTManager::metaClass 000000000001f17c __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDTPTManager::AMDRadeonX4000_AMDTPTManager(OSMetaClass const*) 000000000001f252 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDTPTManager::AMDRadeonX4000_AMDTPTManager() 000000000001f15c __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDTPTManager::AMDRadeonX4000_AMDTPTManager(OSMetaClass const*) 000000000001f282 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDTPTManager::AMDRadeonX4000_AMDTPTManager() 000000000001f1b0 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDTPTManager::~AMDRadeonX4000_AMDTPTManager() 000000000001f1a6 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDTPTManager::~AMDRadeonX4000_AMDTPTManager() 000000000001f19c __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDTPTManager::~AMDRadeonX4000_AMDTPTManager() 000000000052f0e8 __float128 0f SECT 0a 0000 [__DATA.__common] AMDRadeonX4000_AMDUVDTrinity::gMetaClass 00000000003c3808 __float128 0f SECT 08 0000 [.const_data] AMDRadeonX4000_AMDUVDTrinity::superClass 0000000000128236 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDUVDTrinity::free() 00000000001281c2 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDUVDTrinity::init(unsigned int) 0000000000128030 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDUVDTrinity::MetaClass::MetaClass() 00000000001280f0 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDUVDTrinity::MetaClass::MetaClass() 00000000003c3800 __float128 0f SECT 08 0000 [.const_data] AMDRadeonX4000_AMDUVDTrinity::metaClass 000000000012808c __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDUVDTrinity::AMDRadeonX4000_AMDUVDTrinity(OSMetaClass const*) 0000000000128162 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDUVDTrinity::AMDRadeonX4000_AMDUVDTrinity() 000000000012806c __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDUVDTrinity::AMDRadeonX4000_AMDUVDTrinity(OSMetaClass const*) 0000000000128192 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDUVDTrinity::AMDRadeonX4000_AMDUVDTrinity() 00000000001280c0 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDUVDTrinity::~AMDRadeonX4000_AMDUVDTrinity() 00000000001280b6 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDUVDTrinity::~AMDRadeonX4000_AMDUVDTrinity() 00000000001280ac __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDUVDTrinity::~AMDRadeonX4000_AMDUVDTrinity() 000000000052dc98 __float128 0f SECT 0a 0000 [__DATA.__common] AMDRadeonX4000_IAMDHWChannel::gMetaClass 00000000003a5d10 __float128 0f SECT 08 0000 [.const_data] AMDRadeonX4000_IAMDHWChannel::superClass 000000000005314c __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_IAMDHWChannel::MetaClass::MetaClass() 00000000000531ec __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_IAMDHWChannel::MetaClass::MetaClass() 00000000003a5d08 __float128 0f SECT 08 0000 [.const_data] AMDRadeonX4000_IAMDHWChannel::metaClass 0000000000053188 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_IAMDHWChannel::AMDRadeonX4000_IAMDHWChannel(OSMetaClass const*) 00000000000531bc __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_IAMDHWChannel::~AMDRadeonX4000_IAMDHWChannel() 00000000000531b2 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_IAMDHWChannel::~AMDRadeonX4000_IAMDHWChannel() 00000000000531a8 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_IAMDHWChannel::~AMDRadeonX4000_IAMDHWChannel() 000000000052da90 __float128 0f SECT 0a 0000 [__DATA.__common] AMDRadeonX4000_IAMDHWDisplay::gMetaClass 00000000003a3860 __float128 0f SECT 08 0000 [.const_data] AMDRadeonX4000_IAMDHWDisplay::superClass 000000000005263a __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_IAMDHWDisplay::MetaClass::MetaClass() 00000000000526da __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_IAMDHWDisplay::MetaClass::MetaClass() 00000000003a3858 __float128 0f SECT 08 0000 [.const_data] AMDRadeonX4000_IAMDHWDisplay::metaClass 0000000000052676 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_IAMDHWDisplay::AMDRadeonX4000_IAMDHWDisplay(OSMetaClass const*) 00000000000526aa __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_IAMDHWDisplay::~AMDRadeonX4000_IAMDHWDisplay() 00000000000526a0 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_IAMDHWDisplay::~AMDRadeonX4000_IAMDHWDisplay() 0000000000052696 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_IAMDHWDisplay::~AMDRadeonX4000_IAMDHWDisplay() 000000000052dab8 __float128 0f SECT 0a 0000 [__DATA.__common] AMDRadeonX4000_IAMDHWHandler::gMetaClass 00000000003a3c70 __float128 0f SECT 08 0000 [.const_data] AMDRadeonX4000_IAMDHWHandler::superClass 0000000000052714 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_IAMDHWHandler::MetaClass::MetaClass() 00000000000527b4 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_IAMDHWHandler::MetaClass::MetaClass() 00000000003a3c68 __float128 0f SECT 08 0000 [.const_data] AMDRadeonX4000_IAMDHWHandler::metaClass 0000000000052750 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_IAMDHWHandler::AMDRadeonX4000_IAMDHWHandler(OSMetaClass const*) 0000000000052784 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_IAMDHWHandler::~AMDRadeonX4000_IAMDHWHandler() 000000000005277a __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_IAMDHWHandler::~AMDRadeonX4000_IAMDHWHandler() 0000000000052770 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_IAMDHWHandler::~AMDRadeonX4000_IAMDHWHandler() 000000000052d590 __float128 0f SECT 0a 0000 [__DATA.__common] AMDTahitiGraphicsAccelerator::gMetaClass 0000000000394e58 __float128 0f SECT 08 0000 [.const_data] AMDTahitiGraphicsAccelerator::superClass 0000000000029768 __float128 0f SECT 01 0000 [.text] AMDTahitiGraphicsAccelerator::setDeviceType(IOPCIDevice*) 0000000000029742 __float128 0f SECT 01 0000 [.text] AMDTahitiGraphicsAccelerator::newHWInterface() 00000000000295b0 __float128 0f SECT 01 0000 [.text] AMDTahitiGraphicsAccelerator::MetaClass::MetaClass() 0000000000029670 __float128 0f SECT 01 0000 [.text] AMDTahitiGraphicsAccelerator::MetaClass::MetaClass() 0000000000394e50 __float128 0f SECT 08 0000 [.const_data] AMDTahitiGraphicsAccelerator::metaClass 000000000002960c __float128 0f SECT 01 0000 [.text] AMDTahitiGraphicsAccelerator::AMDTahitiGraphicsAccelerator(OSMetaClass const*) 00000000000296e2 __float128 0f SECT 01 0000 [.text] AMDTahitiGraphicsAccelerator::AMDTahitiGraphicsAccelerator() 00000000000295ec __float128 0f SECT 01 0000 [.text] AMDTahitiGraphicsAccelerator::AMDTahitiGraphicsAccelerator(OSMetaClass const*) 0000000000029712 __float128 0f SECT 01 0000 [.text] AMDTahitiGraphicsAccelerator::AMDTahitiGraphicsAccelerator() 0000000000029640 __float128 0f SECT 01 0000 [.text] AMDTahitiGraphicsAccelerator::~AMDTahitiGraphicsAccelerator() 0000000000029636 __float128 0f SECT 01 0000 [.text] AMDTahitiGraphicsAccelerator::~AMDTahitiGraphicsAccelerator() 000000000002962c __float128 0f SECT 01 0000 [.text] AMDTahitiGraphicsAccelerator::~AMDTahitiGraphicsAccelerator() 000000000052d720 __float128 0f SECT 0a 0000 [__DATA.__common] AMDBonaireGraphicsAccelerator::gMetaClass 000000000039b958 __float128 0f SECT 08 0000 [.const_data] AMDBonaireGraphicsAccelerator::superClass 000000000003d382 __float128 0f SECT 01 0000 [.text] AMDBonaireGraphicsAccelerator::newHWInterface() 000000000003d1f0 __float128 0f SECT 01 0000 [.text] AMDBonaireGraphicsAccelerator::MetaClass::MetaClass() 000000000003d2b0 __float128 0f SECT 01 0000 [.text] AMDBonaireGraphicsAccelerator::MetaClass::MetaClass() 000000000039b950 __float128 0f SECT 08 0000 [.const_data] AMDBonaireGraphicsAccelerator::metaClass 000000000003d24c __float128 0f SECT 01 0000 [.text] AMDBonaireGraphicsAccelerator::AMDBonaireGraphicsAccelerator(OSMetaClass const*) 000000000003d322 __float128 0f SECT 01 0000 [.text] AMDBonaireGraphicsAccelerator::AMDBonaireGraphicsAccelerator() 000000000003d22c __float128 0f SECT 01 0000 [.text] AMDBonaireGraphicsAccelerator::AMDBonaireGraphicsAccelerator(OSMetaClass const*) 000000000003d352 __float128 0f SECT 01 0000 [.text] AMDBonaireGraphicsAccelerator::AMDBonaireGraphicsAccelerator() 000000000003d280 __float128 0f SECT 01 0000 [.text] AMDBonaireGraphicsAccelerator::~AMDBonaireGraphicsAccelerator() 000000000003d276 __float128 0f SECT 01 0000 [.text] AMDBonaireGraphicsAccelerator::~AMDBonaireGraphicsAccelerator() 000000000003d26c __float128 0f SECT 01 0000 [.text] AMDBonaireGraphicsAccelerator::~AMDBonaireGraphicsAccelerator() 000000000000580c __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelDevice::deviceStop() 000000000052ceb8 __float128 0f SECT 0a 0000 [__DATA.__common] AMDRadeonX4000_AMDAccelDevice::gMetaClass 0000000000389d28 __float128 0f SECT 08 0000 [.const_data] AMDRadeonX4000_AMDAccelDevice::superClass 00000000000056b2 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelDevice::deviceStart() 00000000000056e8 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelDevice::getHardwareInfo(_sAMD_GET_HW_INFO_VALUES*) 000000000000581e __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelDevice::getTargetAndMethodForIndex(IOService**, unsigned int) 0000000000005520 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelDevice::MetaClass::MetaClass() 00000000000055e0 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelDevice::MetaClass::MetaClass() 0000000000389d20 __float128 0f SECT 08 0000 [.const_data] AMDRadeonX4000_AMDAccelDevice::metaClass 000000000000557c __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelDevice::AMDRadeonX4000_AMDAccelDevice(OSMetaClass const*) 0000000000005652 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelDevice::AMDRadeonX4000_AMDAccelDevice() 000000000000555c __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelDevice::AMDRadeonX4000_AMDAccelDevice(OSMetaClass const*) 0000000000005682 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelDevice::AMDRadeonX4000_AMDAccelDevice() 00000000000055b0 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelDevice::~AMDRadeonX4000_AMDAccelDevice() 00000000000055a6 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelDevice::~AMDRadeonX4000_AMDAccelDevice() 000000000000559c __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelDevice::~AMDRadeonX4000_AMDAccelDevice() 000000000052cf58 __float128 0f SECT 0a 0000 [__DATA.__common] AMDRadeonX4000_AMDAccelShared::gMetaClass 000000000038ba38 __float128 0f SECT 08 0000 [.const_data] AMDRadeonX4000_AMDAccelShared::superClass 0000000000011b06 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelShared::SurfaceCopy(unsigned int*, unsigned long long, IOAccelEvent*) 0000000000011af4 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelShared::free() 0000000000011ae2 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelShared::init(IOGraphicsAccelerator2*, task*) 0000000000011950 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelShared::MetaClass::MetaClass() 0000000000011a10 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelShared::MetaClass::MetaClass() 000000000038ba30 __float128 0f SECT 08 0000 [.const_data] AMDRadeonX4000_AMDAccelShared::metaClass 00000000000119ac __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelShared::AMDRadeonX4000_AMDAccelShared(OSMetaClass const*) 0000000000011a82 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelShared::AMDRadeonX4000_AMDAccelShared() 000000000001198c __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelShared::AMDRadeonX4000_AMDAccelShared(OSMetaClass const*) 0000000000011ab2 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelShared::AMDRadeonX4000_AMDAccelShared() 00000000000119e0 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelShared::~AMDRadeonX4000_AMDAccelShared() 00000000000119d6 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelShared::~AMDRadeonX4000_AMDAccelShared() 00000000000119cc __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelShared::~AMDRadeonX4000_AMDAccelShared() 000000000052d978 __float128 0f SECT 0a 0000 [__DATA.__common] AMDRadeonX4000_AMDDMAHWEngine::gMetaClass 00000000003a20c8 __float128 0f SECT 08 0000 [.const_data] AMDRadeonX4000_AMDDMAHWEngine::superClass 000000000004f21c __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDDMAHWEngine::free() 000000000004f17a __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDDMAHWEngine::init(AMDRadeonX4000_IAMDHWInterface*, _eAMD_HW_ENGINE_TYPE) 000000000004f292 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDDMAHWEngine::powerUp() 000000000004f2bc __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDDMAHWEngine::doMemcpy(unsigned long long, unsigned long long, unsigned int, _DRMDMA_AES*) 000000000004f29a __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDDMAHWEngine::powerOff() 000000000004f0a0 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDDMAHWEngine::MetaClass::MetaClass() 000000000004f140 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDDMAHWEngine::MetaClass::MetaClass() 00000000003a20c0 __float128 0f SECT 08 0000 [.const_data] AMDRadeonX4000_AMDDMAHWEngine::metaClass 000000000004f0dc __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDDMAHWEngine::AMDRadeonX4000_AMDDMAHWEngine(OSMetaClass const*) 000000000004f110 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDDMAHWEngine::~AMDRadeonX4000_AMDDMAHWEngine() 000000000004f106 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDDMAHWEngine::~AMDRadeonX4000_AMDDMAHWEngine() 000000000004f0fc __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDDMAHWEngine::~AMDRadeonX4000_AMDDMAHWEngine() 000000000052f020 __float128 0f SECT 0a 0000 [__DATA.__common] AMDRadeonX4000_AMDFPGenKeyMsg::gMetaClass 00000000003c2a70 __float128 0f SECT 08 0000 [.const_data] AMDRadeonX4000_AMDFPGenKeyMsg::superClass 00000000001270f2 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDFPGenKeyMsg::setOutBuffer(int, unsigned long long, unsigned char*) 00000000001270e0 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDFPGenKeyMsg::free() 0000000000126fca __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDFPGenKeyMsg::init(void*) 0000000000126e38 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDFPGenKeyMsg::MetaClass::MetaClass() 0000000000126ef8 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDFPGenKeyMsg::MetaClass::MetaClass() 0000000000127132 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDFPGenKeyMsg::getOutput() 00000000003c2a68 __float128 0f SECT 08 0000 [.const_data] AMDRadeonX4000_AMDFPGenKeyMsg::metaClass 0000000000126e94 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDFPGenKeyMsg::AMDRadeonX4000_AMDFPGenKeyMsg(OSMetaClass const*) 0000000000126f6a __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDFPGenKeyMsg::AMDRadeonX4000_AMDFPGenKeyMsg() 0000000000126e74 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDFPGenKeyMsg::AMDRadeonX4000_AMDFPGenKeyMsg(OSMetaClass const*) 0000000000126f9a __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDFPGenKeyMsg::AMDRadeonX4000_AMDFPGenKeyMsg() 0000000000126ec8 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDFPGenKeyMsg::~AMDRadeonX4000_AMDFPGenKeyMsg() 0000000000126ebe __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDFPGenKeyMsg::~AMDRadeonX4000_AMDFPGenKeyMsg() 0000000000126eb4 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDFPGenKeyMsg::~AMDRadeonX4000_AMDFPGenKeyMsg() 000000000052dd38 __float128 0f SECT 0a 0000 [__DATA.__common] AMDRadeonX4000_AMDHWRegisters::gMetaClass 00000000003a69c8 __float128 0f SECT 08 0000 [.const_data] AMDRadeonX4000_AMDHWRegisters::superClass 0000000000055a28 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHWRegisters::readOrModifyWrite(unsigned int, unsigned int) 0000000000055a66 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHWRegisters::readAndModifyWrite(unsigned int, unsigned int) 0000000000055aa4 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHWRegisters::readAndOrModifyWrite(unsigned int, unsigned int, unsigned int) 0000000000055ae6 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHWRegisters::readOrAndModifyWrite(unsigned int, unsigned int, unsigned int) 0000000000055882 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHWRegisters::free() 00000000000557a2 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHWRegisters::init(IOPCIDevice*, AMDRadeonX4000_IAMDHWInterface*) 00000000000558ee __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHWRegisters::read(unsigned int) 0000000000055980 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHWRegisters::write(unsigned int, unsigned int) 0000000000055b28 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHWRegisters::enable() 0000000000055b40 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHWRegisters::disable() 0000000000055610 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHWRegisters::MetaClass::MetaClass() 00000000000556d0 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHWRegisters::MetaClass::MetaClass() 00000000003a69c0 __float128 0f SECT 08 0000 [.const_data] AMDRadeonX4000_AMDHWRegisters::metaClass 000000000005566c __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHWRegisters::AMDRadeonX4000_AMDHWRegisters(OSMetaClass const*) 0000000000055742 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHWRegisters::AMDRadeonX4000_AMDHWRegisters() 000000000005564c __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHWRegisters::AMDRadeonX4000_AMDHWRegisters(OSMetaClass const*) 0000000000055772 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHWRegisters::AMDRadeonX4000_AMDHWRegisters() 00000000000556a0 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHWRegisters::~AMDRadeonX4000_AMDHWRegisters() 0000000000055696 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHWRegisters::~AMDRadeonX4000_AMDHWRegisters() 000000000005568c __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHWRegisters::~AMDRadeonX4000_AMDHWRegisters() 000000000052dd88 __float128 0f SECT 0a 0000 [__DATA.__common] AMDRadeonX4000_AMDHWSemaphore::gMetaClass 00000000003a6f68 __float128 0f SECT 08 0000 [.const_data] AMDRadeonX4000_AMDHWSemaphore::superClass 0000000000056bd0 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHWSemaphore::done() 00000000000569ca __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHWSemaphore::free() 00000000000568f2 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHWSemaphore::init(AMDRadeonX4000_IAMDHWInterface*, unsigned long long, unsigned long long*, unsigned long long) 0000000000056a9a __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHWSemaphore::wait(IOAccelEvent*, int, unsigned int*, unsigned int&) 0000000000056c08 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHWSemaphore::reset() 0000000000056b1a __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHWSemaphore::signal(IOAccelEvent*, int, unsigned int*, unsigned int&) 0000000000056c4a __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHWSemaphore::setState(bool) 0000000000056760 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHWSemaphore::MetaClass::MetaClass() 0000000000056820 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHWSemaphore::MetaClass::MetaClass() 00000000003a6f60 __float128 0f SECT 08 0000 [.const_data] AMDRadeonX4000_AMDHWSemaphore::metaClass 00000000000567bc __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHWSemaphore::AMDRadeonX4000_AMDHWSemaphore(OSMetaClass const*) 0000000000056892 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHWSemaphore::AMDRadeonX4000_AMDHWSemaphore() 000000000005679c __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHWSemaphore::AMDRadeonX4000_AMDHWSemaphore(OSMetaClass const*) 00000000000568c2 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHWSemaphore::AMDRadeonX4000_AMDHWSemaphore() 00000000000567f0 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHWSemaphore::~AMDRadeonX4000_AMDHWSemaphore() 00000000000567e6 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHWSemaphore::~AMDRadeonX4000_AMDHWSemaphore() 00000000000567dc __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHWSemaphore::~AMDRadeonX4000_AMDHWSemaphore() 000000000052d8d8 __float128 0f SECT 0a 0000 [__DATA.__common] AMDRadeonX4000_AMDHWUtilities::gMetaClass 00000000003a1338 __float128 0f SECT 08 0000 [.const_data] AMDRadeonX4000_AMDHWUtilities::superClass 000000000004e1f4 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHWUtilities::setupUBMChipInfo(_UBM_CHIPINFO*) 000000000004e1da __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHWUtilities::validateMemCpyDMA(_UBM_MEMCPYINFO*) 000000000004e130 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHWUtilities::validateSurfaceCopyDMA(_UBM_SURFACECOPYINFO*, unsigned int) 000000000004e0fa __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHWUtilities::free() 000000000004e0ba __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHWUtilities::init(AMDRadeonX4000_IAMDHWInterface*) 000000000004dfe0 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHWUtilities::MetaClass::MetaClass() 000000000004e080 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHWUtilities::MetaClass::MetaClass() 00000000003a1330 __float128 0f SECT 08 0000 [.const_data] AMDRadeonX4000_AMDHWUtilities::metaClass 000000000004e01c __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHWUtilities::AMDRadeonX4000_AMDHWUtilities(OSMetaClass const*) 000000000004e050 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHWUtilities::~AMDRadeonX4000_AMDHWUtilities() 000000000004e046 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHWUtilities::~AMDRadeonX4000_AMDHWUtilities() 000000000004e03c __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHWUtilities::~AMDRadeonX4000_AMDHWUtilities() 00000000000580aa __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHWVMContext::assignVMID(unsigned int&, AMDRadeonX4000_IAMDHWChannel*, IOAccelEvent**, bool*) 000000000052de28 __float128 0f SECT 0a 0000 [__DATA.__common] AMDRadeonX4000_AMDHWVMContext::gMetaClass 00000000003a7978 __float128 0f SECT 08 0000 [.const_data] AMDRadeonX4000_AMDHWVMContext::superClass 0000000000058526 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHWVMContext::clearWithDMA(unsigned long long, unsigned long long) 0000000000058414 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHWVMContext::endDMAUpdates() 0000000000058154 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHWVMContext::setDMAUpdates(bool, IOAccelEventMachine2*, IOAccelCommandBufferPool2**) 00000000000583fa __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHWVMContext::beginDMAUpdates() 000000000005862c __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHWVMContext::clearPDEWithDMA(unsigned long long) 0000000000058646 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHWVMContext::clearPTEsWithDMA(unsigned long long, unsigned long long, unsigned long long) 0000000000058676 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHWVMContext::updatePDEWithDMA(unsigned long long, unsigned long long*) 000000000005844c __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHWVMContext::invalidateVMWithDMA(unsigned int, bool) 00000000000584cc __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHWVMContext::getDMABufferPtrNoInc(unsigned int) 00000000000581f6 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHWVMContext::preparePDForCPUAccess(IOMemoryMap**) 00000000000586f6 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHWVMContext::updateLocalPTEWithDMA(unsigned long long, unsigned long long, unsigned long long, unsigned long long, unsigned long long) 0000000000058296 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHWVMContext::completePDForCPUAccess(IOMemoryMap**) 00000000000582e4 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHWVMContext::preparePTBForCPUAccess(IOMemoryMap**, unsigned long long) 000000000005888e __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHWVMContext::updateSystemPTEWithDMA(unsigned long long, unsigned long long, unsigned long long, unsigned long long) 00000000000583a4 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHWVMContext::completePTBForCPUAccess(IOMemoryMap**, unsigned long long) 00000000000581ec __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHWVMContext::getPageTableUpdateEvent() 0000000000057f32 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHWVMContext::free() 0000000000057dca __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHWVMContext::init(AMDRadeonX4000_IAMDHWInterface*, AMDRadeonX4000_IAMDHWVMM*) 0000000000058b1e __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHWVMContext::pageOnPD() 0000000000057cf0 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHWVMContext::MetaClass::MetaClass() 0000000000057d90 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHWVMContext::MetaClass::MetaClass() 00000000003a7970 __float128 0f SECT 08 0000 [.const_data] AMDRadeonX4000_AMDHWVMContext::metaClass 00000000000589e0 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHWVMContext::pageOffPD() 0000000000057d2c __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHWVMContext::AMDRadeonX4000_AMDHWVMContext(OSMetaClass const*) 0000000000057d60 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHWVMContext::~AMDRadeonX4000_AMDHWVMContext() 0000000000057d56 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHWVMContext::~AMDRadeonX4000_AMDHWVMContext() 0000000000057d4c __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHWVMContext::~AMDRadeonX4000_AMDHWVMContext() 000000000052def0 __float128 0f SECT 0a 0000 [__DATA.__common] AMDRadeonX4000_AMDPM4HWEngine::gMetaClass 00000000003a8b98 __float128 0f SECT 08 0000 [.const_data] AMDRadeonX4000_AMDPM4HWEngine::superClass 000000000005eaf0 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDPM4HWEngine::systemWillChangeSpeedEvent() 000000000005eb1c __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDPM4HWEngine::initializeSubmitCommandBufferInfo(AMD_SUBMIT_COMMAND_BUFFER_INFO*) 000000000005e8fc __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDPM4HWEngine::free() 000000000005e8da __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDPM4HWEngine::init(AMDRadeonX4000_IAMDHWInterface*, _eAMD_HW_ENGINE_TYPE) 000000000005ea3c __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDPM4HWEngine::stop() 000000000005e9c2 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDPM4HWEngine::start() 000000000005e90e __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDPM4HWEngine::powerUp() 000000000005e9b4 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDPM4HWEngine::powerOff() 000000000005e800 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDPM4HWEngine::MetaClass::MetaClass() 000000000005e8a0 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDPM4HWEngine::MetaClass::MetaClass() 00000000003a8b90 __float128 0f SECT 08 0000 [.const_data] AMDRadeonX4000_AMDPM4HWEngine::metaClass 000000000005e83c __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDPM4HWEngine::AMDRadeonX4000_AMDPM4HWEngine(OSMetaClass const*) 000000000005e870 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDPM4HWEngine::~AMDRadeonX4000_AMDPM4HWEngine() 000000000005e866 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDPM4HWEngine::~AMDRadeonX4000_AMDPM4HWEngine() 000000000005e85c __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDPM4HWEngine::~AMDRadeonX4000_AMDPM4HWEngine() 000000000052df40 __float128 0f SECT 0a 0000 [__DATA.__common] AMDRadeonX4000_AMDSPUHWEngine::gMetaClass 00000000003a92d8 __float128 0f SECT 08 0000 [.const_data] AMDRadeonX4000_AMDSPUHWEngine::superClass 000000000005f92a __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDSPUHWEngine::initSPUMemory() 000000000005f972 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDSPUHWEngine::loadSPUKernel() 000000000005f8e8 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDSPUHWEngine::releaseSPUMemory() 000000000005f654 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDSPUHWEngine::allocateSPUMemory() 000000000005f9d8 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDSPUHWEngine::initSPUBootControl() 000000000005f54c __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDSPUHWEngine::pageSPUReservedArea(bool, unsigned int) 000000000005f4a0 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDSPUHWEngine::setMemoryAllocations(bool) 000000000005f4be __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDSPUHWEngine::setupSPUReservedArea() 000000000005f402 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDSPUHWEngine::setSuspendResumeState(bool) 000000000005f50a __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDSPUHWEngine::releaseSPUReservedArea() 000000000005f370 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDSPUHWEngine::setPowerRegistrationState(bool) 000000000005f49a __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDSPUHWEngine::setMemoryAllocationsEnabled(bool) 000000000005f228 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDSPUHWEngine::free() 000000000005f12a __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDSPUHWEngine::init(AMDRadeonX4000_IAMDHWInterface*, _eAMD_HW_ENGINE_TYPE) 000000000005f324 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDSPUHWEngine::stop() 000000000005f2d0 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDSPUHWEngine::start() 000000000005f2c0 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDSPUHWEngine::powerUp() 000000000005f2c8 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDSPUHWEngine::powerOff() 000000000005f050 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDSPUHWEngine::MetaClass::MetaClass() 000000000005f0f0 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDSPUHWEngine::MetaClass::MetaClass() 00000000003a92d0 __float128 0f SECT 08 0000 [.const_data] AMDRadeonX4000_AMDSPUHWEngine::metaClass 000000000005f08c __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDSPUHWEngine::AMDRadeonX4000_AMDSPUHWEngine(OSMetaClass const*) 000000000005f0c0 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDSPUHWEngine::~AMDRadeonX4000_AMDSPUHWEngine() 000000000005f0b6 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDSPUHWEngine::~AMDRadeonX4000_AMDSPUHWEngine() 000000000005f0ac __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDSPUHWEngine::~AMDRadeonX4000_AMDSPUHWEngine() 0000000000061bf6 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDUVDHWEngine::findClient(unsigned int) 000000000052dfe0 __float128 0f SECT 0a 0000 [__DATA.__common] AMDRadeonX4000_AMDUVDHWEngine::gMetaClass 00000000003aa1e8 __float128 0f SECT 08 0000 [.const_data] AMDRadeonX4000_AMDUVDHWEngine::superClass 0000000000062656 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDUVDHWEngine::setVclkDclk(unsigned int, unsigned int) 0000000000061b9a __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDUVDHWEngine::removeClient(unsigned int) 000000000006229a __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDUVDHWEngine::restoreState(unsigned int, _SML_UVD_MSG*, bool) 000000000006132c __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDUVDHWEngine::start_Engine() 000000000006157c __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDUVDHWEngine::stopRBEngine() 00000000000619d0 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDUVDHWEngine::hasCapability(_sUVD_CAPABILITY*) 0000000000062856 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDUVDHWEngine::setPowerState(unsigned int) 0000000000061528 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDUVDHWEngine::startRBEngine() 00000000000626c6 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDUVDHWEngine::queryClockInfo(unsigned int*, unsigned int*, unsigned int*) 000000000006238c __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDUVDHWEngine::submitUVDFWMsg(_SML_UVD_MSG*, bool) 0000000000061778 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDUVDHWEngine::releaseFWMemory() 0000000000061684 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDUVDHWEngine::allocateFWMemory() 0000000000061fb4 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDUVDHWEngine::copyCacheWindows() 000000000006259e __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDUVDHWEngine::initHardwareCail() 0000000000061b22 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDUVDHWEngine::updateCapability(_sUVD_CAPABILITY*) 000000000006275e __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDUVDHWEngine::updatePowerState() 0000000000061a94 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDUVDHWEngine::releaseCapability(unsigned int) 00000000000619f4 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDUVDHWEngine::requestCapability(_sUVD_CAPABILITY*, unsigned int*) 00000000000617d8 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDUVDHWEngine::setupFirmwareArea() 00000000000615d6 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDUVDHWEngine::setFWMemoryAddress() 0000000000062634 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDUVDHWEngine::releaseHardwareCail() 00000000000620f2 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDUVDHWEngine::restoreCacheWindows(bool) 000000000006296a __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDUVDHWEngine::setUVDSPUPowerState(unsigned int) 00000000000615b6 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDUVDHWEngine::setVirtualSpaceReady(bool) 0000000000062350 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDUVDHWEngine::submitDestroyCommand(unsigned int, _SML_UVD_MSG*) 00000000000628f2 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDUVDHWEngine::setHighPerformanceDecode(unsigned int) 0000000000061652 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDUVDHWEngine::setMemoryAllocationsEnabled(bool) 0000000000061856 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDUVDHWEngine::setTimestampWritebackMemory(bool) 0000000000062508 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDUVDHWEngine::setupCacheWindowsAndFwvCail() 0000000000061250 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDUVDHWEngine::free() 000000000006114a __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDUVDHWEngine::init(AMDRadeonX4000_IAMDHWInterface*, _eAMD_HW_ENGINE_TYPE) 000000000006142a __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDUVDHWEngine::stop() 00000000000612b8 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDUVDHWEngine::start() 000000000006128c __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDUVDHWEngine::powerUp() 0000000000061294 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDUVDHWEngine::powerOff() 0000000000061070 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDUVDHWEngine::MetaClass::MetaClass() 0000000000061110 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDUVDHWEngine::MetaClass::MetaClass() 0000000000061b7c __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDUVDHWEngine::addClient(AMDHWUVDClient*) 000000000006141a __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDUVDHWEngine::isEnabled() 0000000000061c1e __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDUVDHWEngine::loadUVDFW() 00000000003aa1e0 __float128 0f SECT 08 0000 [.const_data] AMDRadeonX4000_AMDUVDHWEngine::metaClass 0000000000062242 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDUVDHWEngine::saveState(unsigned int, _SML_UVD_MSG*) 00000000000612fc __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDUVDHWEngine::start_DMA() 00000000000610ac __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDUVDHWEngine::AMDRadeonX4000_AMDUVDHWEngine(OSMetaClass const*) 00000000000610e0 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDUVDHWEngine::~AMDRadeonX4000_AMDUVDHWEngine() 00000000000610d6 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDUVDHWEngine::~AMDRadeonX4000_AMDUVDHWEngine() 00000000000610cc __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDUVDHWEngine::~AMDRadeonX4000_AMDUVDHWEngine() 000000000052df90 __float128 0f SECT 0a 0000 [__DATA.__common] AMDRadeonX4000_AMDVCEHWEngine::gMetaClass 0000000000060b58 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDVCEHWEngine::powerOnOff(bool) 00000000003a9a38 __float128 0f SECT 08 0000 [.const_data] AMDRadeonX4000_AMDVCEHWEngine::superClass 0000000000060a50 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDVCEHWEngine::setEVClkECClk(unsigned int, unsigned int) 0000000000060ac0 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDVCEHWEngine::queryClockInfo(unsigned int*, unsigned int*, unsigned int*) 0000000000060380 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDVCEHWEngine::releaseFWMemory() 00000000000605fc __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDVCEHWEngine::releaseFeedBack() 00000000000601f2 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDVCEHWEngine::allocateFWMemory() 00000000000604f6 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDVCEHWEngine::allocateFeedBack() 000000000006087a __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDVCEHWEngine::initHardwareCail() 00000000000606ec __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDVCEHWEngine::releaseCapability(unsigned int) 000000000006066a __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDVCEHWEngine::requestCapability(_sVCE_CAPABILITY*, unsigned int*) 000000000006094e __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDVCEHWEngine::pageVCEReservedArea(bool) 000000000006092c __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDVCEHWEngine::releaseHardwareCail() 0000000000060ba0 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDVCEHWEngine::setSaveRestoreState(bool) 0000000000060a22 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDVCEHWEngine::setupVCEReservedArea() 0000000000060bc0 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDVCEHWEngine::setSuspendResumeState(bool) 0000000000060a3e __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDVCEHWEngine::releaseVCEReservedArea() 00000000000601d8 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDVCEHWEngine::setMemoryAllocationsEnabled(bool) 000000000006001a __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDVCEHWEngine::free() 000000000005feea __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDVCEHWEngine::init(AMDRadeonX4000_IAMDHWInterface*, _eAMD_HW_ENGINE_TYPE) 000000000006016e __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDVCEHWEngine::stop() 00000000000600e0 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDVCEHWEngine::start() 00000000000603c2 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDVCEHWEngine::loadFW() 00000000000600d0 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDVCEHWEngine::powerUp() 00000000000600d8 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDVCEHWEngine::powerOff() 000000000005fe10 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDVCEHWEngine::MetaClass::MetaClass() 000000000005feb0 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDVCEHWEngine::MetaClass::MetaClass() 00000000003a9a30 __float128 0f SECT 08 0000 [.const_data] AMDRadeonX4000_AMDVCEHWEngine::metaClass 0000000000060738 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDVCEHWEngine::submitCmd(_SML_VCE_CMD_TYPE, void*, _eAMD_HW_RING_TYPE) 000000000005fe4c __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDVCEHWEngine::AMDRadeonX4000_AMDVCEHWEngine(OSMetaClass const*) 000000000005fe80 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDVCEHWEngine::~AMDRadeonX4000_AMDVCEHWEngine() 000000000005fe76 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDVCEHWEngine::~AMDRadeonX4000_AMDVCEHWEngine() 000000000005fe6c __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDVCEHWEngine::~AMDRadeonX4000_AMDVCEHWEngine() 000000000052d568 __float128 0f SECT 0a 0000 [__DATA.__common] AMDPitcairnGraphicsAccelerator::gMetaClass 0000000000394298 __float128 0f SECT 08 0000 [.const_data] AMDPitcairnGraphicsAccelerator::superClass 0000000000029458 __float128 0f SECT 01 0000 [.text] AMDPitcairnGraphicsAccelerator::setDeviceType(IOPCIDevice*) 0000000000029432 __float128 0f SECT 01 0000 [.text] AMDPitcairnGraphicsAccelerator::newHWInterface() 00000000000292a0 __float128 0f SECT 01 0000 [.text] AMDPitcairnGraphicsAccelerator::MetaClass::MetaClass() 0000000000029360 __float128 0f SECT 01 0000 [.text] AMDPitcairnGraphicsAccelerator::MetaClass::MetaClass() 0000000000394290 __float128 0f SECT 08 0000 [.const_data] AMDPitcairnGraphicsAccelerator::metaClass 00000000000292fc __float128 0f SECT 01 0000 [.text] AMDPitcairnGraphicsAccelerator::AMDPitcairnGraphicsAccelerator(OSMetaClass const*) 00000000000293d2 __float128 0f SECT 01 0000 [.text] AMDPitcairnGraphicsAccelerator::AMDPitcairnGraphicsAccelerator() 00000000000292dc __float128 0f SECT 01 0000 [.text] AMDPitcairnGraphicsAccelerator::AMDPitcairnGraphicsAccelerator(OSMetaClass const*) 0000000000029402 __float128 0f SECT 01 0000 [.text] AMDPitcairnGraphicsAccelerator::AMDPitcairnGraphicsAccelerator() 0000000000029330 __float128 0f SECT 01 0000 [.text] AMDPitcairnGraphicsAccelerator::~AMDPitcairnGraphicsAccelerator() 0000000000029326 __float128 0f SECT 01 0000 [.text] AMDPitcairnGraphicsAccelerator::~AMDPitcairnGraphicsAccelerator() 000000000002931c __float128 0f SECT 01 0000 [.text] AMDPitcairnGraphicsAccelerator::~AMDPitcairnGraphicsAccelerator() 000000000052ce90 __float128 0f SECT 0a 0000 [__DATA.__common] AMDRadeonX4000_AMDAccelChannel::gMetaClass 00000000003899f8 __float128 0f SECT 08 0000 [.const_data] AMDRadeonX4000_AMDAccelChannel::superClass 0000000000004b40 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelChannel::submitFlush() 00000000000052e0 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelChannel::addToBarrier(IOAccelEvent*) 00000000000048d2 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelChannel::submitBuffer(IOAccelCommandDescriptor*) 0000000000004be8 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelChannel::replayBuffers() 00000000000052ae __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelChannel::initBarrierData() 000000000000534e __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelChannel::SubmitClearState() 0000000000004b9e __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelChannel::submitVMInvalidate(unsigned int, unsigned long long) 000000000000532a __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelChannel::vblEnableInterrupt() 000000000000533c __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelChannel::vblDisableInterrupt() 0000000000004eea __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelChannel::writeDiagnosisReport() 0000000000004dae __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelChannel::resetHardwareAndReplay() 0000000000004e52 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelChannel::getHardwareDiagnosisReport(unsigned int*) 0000000000004840 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelChannel::free() 0000000000004732 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelChannel::init(IOGraphicsAccelerator2*, AMDRadeonX4000_IAMDHWChannel*) 00000000000045a0 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelChannel::MetaClass::MetaClass() 0000000000004660 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelChannel::MetaClass::MetaClass() 00000000003899f0 __float128 0f SECT 08 0000 [.const_data] AMDRadeonX4000_AMDAccelChannel::metaClass 00000000000045fc __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelChannel::AMDRadeonX4000_AMDAccelChannel(OSMetaClass const*) 00000000000046d2 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelChannel::AMDRadeonX4000_AMDAccelChannel() 00000000000045dc __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelChannel::AMDRadeonX4000_AMDAccelChannel(OSMetaClass const*) 0000000000004702 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelChannel::AMDRadeonX4000_AMDAccelChannel() 0000000000004630 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelChannel::~AMDRadeonX4000_AMDAccelChannel() 0000000000004626 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelChannel::~AMDRadeonX4000_AMDAccelChannel() 000000000000461c __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelChannel::~AMDRadeonX4000_AMDAccelChannel() 000000000052cfd0 __float128 0f SECT 0a 0000 [__DATA.__common] AMDRadeonX4000_AMDAccelSurface::gMetaClass 000000000038c9b8 __float128 0f SECT 08 0000 [.const_data] AMDRadeonX4000_AMDAccelSurface::superClass 0000000000014706 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelSurface::canTmpAlloc(unsigned int) 0000000000014692 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelSurface::surfaceStop() 0000000000013442 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelSurface::copyToBuffer(int, int, int, int, unsigned int, unsigned int, IOAccelEvent*, IOAccelResource2*, IOAccelSysMemory*, unsigned int, unsigned long long, unsigned int) 0000000000014748 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelSurface::shapeSurface(unsigned int, unsigned short, unsigned short) 00000000000142fc __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelSurface::submitUpdate(unsigned int, IOAccelBounds*, unsigned int) 0000000000014604 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelSurface::surfaceStart() 0000000000014308 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelSurface::didSubmitSwap(unsigned int, unsigned int) 00000000000129da __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelSurface::copyFromBuffer(int, int, int, int, unsigned int, unsigned int, IOAccelEvent*, IOAccelResource2*, IOAccelSysMemory*, unsigned int, unsigned long long, unsigned int) 00000000000134de __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelSurface::submitSwapCopy(IOAccelEvent*, IOAccelResource2*, IOAccelResource2*) 0000000000012ac8 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelSurface::copy_buffer_gpu(int, int, int, int, unsigned int, unsigned int, IOAccelEvent*, IOAccelResource2*, IOAccelSysMemory*, unsigned long long, unsigned long long, unsigned int, unsigned int) 000000000001398c __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelSurface::submitSwapFlush(IOAccelEvent*, IOAccelResource2*, IOAccelResource2*, IOAccelSwapFlushRec const*, unsigned int, unsigned int, unsigned int, IOAccelBounds const*) 0000000000015dae __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelSurface::isBackBufferReady(unsigned int) 0000000000013e5c __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelSurface::submitCopyForward(IOAccelEvent*, unsigned int, IOAccelResource2*, IOAccelResource2*, IOAccelBounds const*, unsigned int) 00000000000150ae __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelSurface::getMultisampleCount() 0000000000015142 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelSurface::shapeSurfaceBuffers(unsigned char, unsigned char*, void*, unsigned char, bool, unsigned int, unsigned short, unsigned short) 0000000000015d7a __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelSurface::getDirtyBufferBitsFromPrivateModeBits(unsigned long long) 0000000000012900 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelSurface::MetaClass::MetaClass() 00000000000129a0 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelSurface::MetaClass::MetaClass() 000000000038c9b0 __float128 0f SECT 08 0000 [.const_data] AMDRadeonX4000_AMDAccelSurface::metaClass 000000000001293c __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelSurface::AMDRadeonX4000_AMDAccelSurface(OSMetaClass const*) 0000000000012970 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelSurface::~AMDRadeonX4000_AMDAccelSurface() 0000000000012966 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelSurface::~AMDRadeonX4000_AMDAccelSurface() 000000000001295c __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelSurface::~AMDRadeonX4000_AMDAccelSurface() 000000000052d950 __float128 0f SECT 0a 0000 [__DATA.__common] AMDRadeonX4000_AMDDMAHWChannel::gMetaClass 00000000003a1cc8 __float128 0f SECT 08 0000 [.const_data] AMDRadeonX4000_AMDDMAHWChannel::superClass 000000000004ef16 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDDMAHWChannel::submitCommandBuffer(AMD_SUBMIT_COMMAND_BUFFER_INFO*, unsigned int*) 000000000004ef28 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDDMAHWChannel::timeStampInterruptType() 000000000004eeee __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDDMAHWChannel::free() 000000000004eeba __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDDMAHWChannel::init(int, AMDRadeonX4000_IAMDHWInterface*, AMDRadeonX4000_IAMDHWEngine*, AMDRadeonX4000_IAMDHWRing*, char const*) 000000000004ede0 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDDMAHWChannel::MetaClass::MetaClass() 000000000004ee80 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDDMAHWChannel::MetaClass::MetaClass() 00000000003a1cc0 __float128 0f SECT 08 0000 [.const_data] AMDRadeonX4000_AMDDMAHWChannel::metaClass 000000000004ee1c __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDDMAHWChannel::AMDRadeonX4000_AMDDMAHWChannel(OSMetaClass const*) 000000000004ee50 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDDMAHWChannel::~AMDRadeonX4000_AMDDMAHWChannel() 000000000004ee46 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDDMAHWChannel::~AMDRadeonX4000_AMDDMAHWChannel() 000000000004ee3c __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDDMAHWChannel::~AMDRadeonX4000_AMDDMAHWChannel() 000000000052f098 __float128 0f SECT 0a 0000 [__DATA.__common] AMDRadeonX4000_AMDFPEncryptMsg::gMetaClass 00000000003c3220 __float128 0f SECT 08 0000 [.const_data] AMDRadeonX4000_AMDFPEncryptMsg::superClass 0000000000127984 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDFPEncryptMsg::setOutBuffer(int, unsigned long long, unsigned char*) 0000000000127972 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDFPEncryptMsg::free() 000000000012782e __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDFPEncryptMsg::init(void*) 000000000012769c __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDFPEncryptMsg::MetaClass::MetaClass() 000000000012775c __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDFPEncryptMsg::MetaClass::MetaClass() 00000000001279c4 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDFPEncryptMsg::getOutput() 00000000003c3218 __float128 0f SECT 08 0000 [.const_data] AMDRadeonX4000_AMDFPEncryptMsg::metaClass 00000000001276f8 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDFPEncryptMsg::AMDRadeonX4000_AMDFPEncryptMsg(OSMetaClass const*) 00000000001277ce __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDFPEncryptMsg::AMDRadeonX4000_AMDFPEncryptMsg() 00000000001276d8 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDFPEncryptMsg::AMDRadeonX4000_AMDFPEncryptMsg(OSMetaClass const*) 00000000001277fe __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDFPEncryptMsg::AMDRadeonX4000_AMDFPEncryptMsg() 000000000012772c __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDFPEncryptMsg::~AMDRadeonX4000_AMDFPEncryptMsg() 0000000000127722 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDFPEncryptMsg::~AMDRadeonX4000_AMDFPEncryptMsg() 0000000000127718 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDFPEncryptMsg::~AMDRadeonX4000_AMDFPEncryptMsg() 000000000052eff8 __float128 0f SECT 0a 0000 [__DATA.__common] AMDRadeonX4000_AMDFPGetCertMsg::gMetaClass 00000000003c27e0 __float128 0f SECT 08 0000 [.const_data] AMDRadeonX4000_AMDFPGetCertMsg::superClass 0000000000126dce __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDFPGetCertMsg::setOutBuffer(int, unsigned long long, unsigned char*) 0000000000126dbc __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDFPGetCertMsg::free() 0000000000126ce8 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDFPGetCertMsg::init(void*) 0000000000126b56 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDFPGetCertMsg::MetaClass::MetaClass() 0000000000126c16 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDFPGetCertMsg::MetaClass::MetaClass() 0000000000126e06 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDFPGetCertMsg::getOutput() 00000000003c27d8 __float128 0f SECT 08 0000 [.const_data] AMDRadeonX4000_AMDFPGetCertMsg::metaClass 0000000000126bb2 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDFPGetCertMsg::AMDRadeonX4000_AMDFPGetCertMsg(OSMetaClass const*) 0000000000126c88 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDFPGetCertMsg::AMDRadeonX4000_AMDFPGetCertMsg() 0000000000126b92 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDFPGetCertMsg::AMDRadeonX4000_AMDFPGetCertMsg(OSMetaClass const*) 0000000000126cb8 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDFPGetCertMsg::AMDRadeonX4000_AMDFPGetCertMsg() 0000000000126be6 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDFPGetCertMsg::~AMDRadeonX4000_AMDFPGetCertMsg() 0000000000126bdc __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDFPGetCertMsg::~AMDRadeonX4000_AMDFPGetCertMsg() 0000000000126bd2 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDFPGetCertMsg::~AMDRadeonX4000_AMDFPGetCertMsg() 000000000052f048 __float128 0f SECT 0a 0000 [__DATA.__common] AMDRadeonX4000_AMDFPTestKeyMsg::gMetaClass 00000000003c2d00 __float128 0f SECT 08 0000 [.const_data] AMDRadeonX4000_AMDFPTestKeyMsg::superClass 00000000001273fc __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDFPTestKeyMsg::setOutBuffer(int, unsigned long long, unsigned char*) 00000000001273ea __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDFPTestKeyMsg::free() 0000000000127310 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDFPTestKeyMsg::init(void*) 000000000012717e __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDFPTestKeyMsg::MetaClass::MetaClass() 000000000012723e __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDFPTestKeyMsg::MetaClass::MetaClass() 000000000012743c __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDFPTestKeyMsg::getOutput() 00000000003c2cf8 __float128 0f SECT 08 0000 [.const_data] AMDRadeonX4000_AMDFPTestKeyMsg::metaClass 00000000001271da __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDFPTestKeyMsg::AMDRadeonX4000_AMDFPTestKeyMsg(OSMetaClass const*) 00000000001272b0 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDFPTestKeyMsg::AMDRadeonX4000_AMDFPTestKeyMsg() 00000000001271ba __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDFPTestKeyMsg::AMDRadeonX4000_AMDFPTestKeyMsg(OSMetaClass const*) 00000000001272e0 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDFPTestKeyMsg::AMDRadeonX4000_AMDFPTestKeyMsg() 000000000012720e __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDFPTestKeyMsg::~AMDRadeonX4000_AMDFPTestKeyMsg() 0000000000127204 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDFPTestKeyMsg::~AMDRadeonX4000_AMDFPTestKeyMsg() 00000000001271fa __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDFPTestKeyMsg::~AMDRadeonX4000_AMDFPTestKeyMsg() 000000000052da18 __float128 0f SECT 0a 0000 [__DATA.__common] AMDRadeonX4000_AMDNullHWEngine::gMetaClass 00000000003a2d68 __float128 0f SECT 08 0000 [.const_data] AMDRadeonX4000_AMDNullHWEngine::superClass 0000000000050fc0 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDNullHWEngine::MetaClass::MetaClass() 0000000000051080 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDNullHWEngine::MetaClass::MetaClass() 00000000003a2d60 __float128 0f SECT 08 0000 [.const_data] AMDRadeonX4000_AMDNullHWEngine::metaClass 000000000005101c __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDNullHWEngine::AMDRadeonX4000_AMDNullHWEngine(OSMetaClass const*) 00000000000510f2 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDNullHWEngine::AMDRadeonX4000_AMDNullHWEngine() 0000000000050ffc __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDNullHWEngine::AMDRadeonX4000_AMDNullHWEngine(OSMetaClass const*) 0000000000051122 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDNullHWEngine::AMDRadeonX4000_AMDNullHWEngine() 0000000000051050 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDNullHWEngine::~AMDRadeonX4000_AMDNullHWEngine() 0000000000051046 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDNullHWEngine::~AMDRadeonX4000_AMDNullHWEngine() 000000000005103c __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDNullHWEngine::~AMDRadeonX4000_AMDNullHWEngine() 000000000052df18 __float128 0f SECT 0a 0000 [__DATA.__common] AMDRadeonX4000_AMDPM4HWChannel::gMetaClass 00000000003a8ef8 __float128 0f SECT 08 0000 [.const_data] AMDRadeonX4000_AMDPM4HWChannel::superClass 000000000005ee50 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDPM4HWChannel::submitCommandBuffer(AMD_SUBMIT_COMMAND_BUFFER_INFO*, unsigned int*) 000000000005eeea __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDPM4HWChannel::getOneDwordNOPCommand() 000000000005eede __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDPM4HWChannel::timeStampInterruptType() 000000000005ee7c __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDPM4HWChannel::executeFlushAndInvalidateDestinationCaches() 000000000005ed72 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDPM4HWChannel::free() 000000000005ed1a __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDPM4HWChannel::init(int, AMDRadeonX4000_IAMDHWInterface*, AMDRadeonX4000_IAMDHWEngine*, AMDRadeonX4000_IAMDHWRing*, char const*) 000000000005ec40 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDPM4HWChannel::MetaClass::MetaClass() 000000000005ece0 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDPM4HWChannel::MetaClass::MetaClass() 00000000003a8ef0 __float128 0f SECT 08 0000 [.const_data] AMDRadeonX4000_AMDPM4HWChannel::metaClass 000000000005ec7c __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDPM4HWChannel::AMDRadeonX4000_AMDPM4HWChannel(OSMetaClass const*) 000000000005ecb0 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDPM4HWChannel::~AMDRadeonX4000_AMDPM4HWChannel() 000000000005eca6 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDPM4HWChannel::~AMDRadeonX4000_AMDPM4HWChannel() 000000000005ec9c __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDPM4HWChannel::~AMDRadeonX4000_AMDPM4HWChannel() 000000000052ee68 __float128 0f SECT 0a 0000 [__DATA.__common] AMDRadeonX4000_AMDSMLInterface::gMetaClass 00000000001249f8 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDSMLInterface::getSPUKapp(unsigned int*, unsigned int*) 00000000003c0e08 __float128 0f SECT 08 0000 [.const_data] AMDRadeonX4000_AMDSMLInterface::superClass 0000000000124934 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDSMLInterface::writeAESCmd(unsigned int*, unsigned int*, unsigned long long, unsigned long long, unsigned int, _DRMDMA_AES*, unsigned int) 0000000000124b80 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDSMLInterface::writeVCECmd(unsigned int*, unsigned int*, _SML_VCE_CMD_TYPE, void*) 0000000000124a64 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDSMLInterface::getSPUAppMsg(_AMD_SPU_MSG_TYPE) 0000000000124986 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDSMLInterface::getSPUKernel(unsigned int*, unsigned int*, unsigned int*, unsigned int*) 00000000001248d4 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDSMLInterface::saveUVDState(unsigned int, _SML_UVD_MSG*) 0000000000124a1c __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDSMLInterface::getSPUAppSize(_AMD_SPU_APP_TYPE, unsigned int*, unsigned int*) 0000000000124ba4 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDSMLInterface::getVCECmdSize(unsigned int*, _SML_VCE_CMD_TYPE) 00000000001249d4 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDSMLInterface::getSPUKappSize(unsigned int*, unsigned int*) 0000000000124870 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDSMLInterface::getUVDFWMemReq(unsigned int*, unsigned int*, unsigned int*) 0000000000124b08 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDSMLInterface::getVCEFWMemReq(unsigned int*, unsigned int*) 0000000000124aa6 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDSMLInterface::writeSPUAppCmd(_SML_SPU_CMD*, bool) 00000000001248f4 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDSMLInterface::restoreUVDState(unsigned int, _SML_UVD_MSG*) 0000000000124a86 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDSMLInterface::writeSPUInitCmd(_SML_SPU_CMD*) 0000000000124894 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDSMLInterface::getUVDFWCacheInfo(_SML_UVDFWInfo*) 0000000000124b40 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDSMLInterface::getVCEFWCacheInfo(_SML_VCEFWINFO*) 0000000000124b24 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDSMLInterface::getVCEFWMemConfig(unsigned int*, unsigned int*) 0000000000124ac8 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDSMLInterface::writeSPUAppMsgCmd(_SML_SPU_CMD*) 00000000001249b4 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDSMLInterface::getSPUFeedBackSize(unsigned int*) 000000000012496a __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDSMLInterface::getSPUKernelMemReq(unsigned int*, unsigned int*, unsigned int*) 0000000000124bc0 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDSMLInterface::getVCEFeedbackSize(unsigned int*) 0000000000124914 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDSMLInterface::writeUVDDestroyMsg(unsigned int, _SML_UVD_MSG*) 0000000000124ae8 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDSMLInterface::writeSAMUSetPremContentCmd(_SAMU_GPCOM_CMD*) 00000000001247f4 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDSMLInterface::free() 0000000000124722 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDSMLInterface::init(unsigned int) 0000000000124be6 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDSMLInterface::getDRM() 0000000000124bf0 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDSMLInterface::getSPU() 0000000000124bdc __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDSMLInterface::getUVD() 0000000000124bfa __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDSMLInterface::getVCE() 00000000001248b4 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDSMLInterface::getUVDFW(_SML_UVDFW*) 0000000000124b60 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDSMLInterface::getVCEFW(_SML_VCEFW*) 0000000000124590 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDSMLInterface::MetaClass::MetaClass() 0000000000124650 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDSMLInterface::MetaClass::MetaClass() 0000000000124c04 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDSMLInterface::doUVDTest(unsigned int, unsigned int, unsigned int) 0000000000124a40 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDSMLInterface::getSPUApp(_AMD_SPU_APP_TYPE, unsigned int*, unsigned int*) 00000000003c0e00 __float128 0f SECT 08 0000 [.const_data] AMDRadeonX4000_AMDSMLInterface::metaClass 00000000001245ec __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDSMLInterface::AMDRadeonX4000_AMDSMLInterface(OSMetaClass const*) 00000000001246c2 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDSMLInterface::AMDRadeonX4000_AMDSMLInterface() 00000000001245cc __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDSMLInterface::AMDRadeonX4000_AMDSMLInterface(OSMetaClass const*) 00000000001246f2 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDSMLInterface::AMDRadeonX4000_AMDSMLInterface() 0000000000124620 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDSMLInterface::~AMDRadeonX4000_AMDSMLInterface() 0000000000124616 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDSMLInterface::~AMDRadeonX4000_AMDSMLInterface() 000000000012460c __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDSMLInterface::~AMDRadeonX4000_AMDSMLInterface() 000000000052df68 __float128 0f SECT 0a 0000 [__DATA.__common] AMDRadeonX4000_AMDSPUHWChannel::gMetaClass 00000000003a9698 __float128 0f SECT 08 0000 [.const_data] AMDRadeonX4000_AMDSPUHWChannel::superClass 000000000005fc8a __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDSPUHWChannel::submitCommandBuffer(AMD_SUBMIT_COMMAND_BUFFER_INFO*, unsigned int*) 000000000005fc7e __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDSPUHWChannel::timeStampInterruptType() 000000000005fc6c __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDSPUHWChannel::free() 000000000005fc3a __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDSPUHWChannel::init(int, AMDRadeonX4000_IAMDHWInterface*, AMDRadeonX4000_IAMDHWEngine*, AMDRadeonX4000_IAMDHWRing*, char const*) 000000000005fb60 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDSPUHWChannel::MetaClass::MetaClass() 000000000005fc00 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDSPUHWChannel::MetaClass::MetaClass() 00000000003a9690 __float128 0f SECT 08 0000 [.const_data] AMDRadeonX4000_AMDSPUHWChannel::metaClass 000000000005fb9c __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDSPUHWChannel::AMDRadeonX4000_AMDSPUHWChannel(OSMetaClass const*) 000000000005fbd0 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDSPUHWChannel::~AMDRadeonX4000_AMDSPUHWChannel() 000000000005fbc6 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDSPUHWChannel::~AMDRadeonX4000_AMDSPUHWChannel() 000000000005fbbc __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDSPUHWChannel::~AMDRadeonX4000_AMDSPUHWChannel() 000000000052d928 __float128 0f SECT 0a 0000 [__DATA.__common] AMDRadeonX4000_AMDUVDHWChannel::gMetaClass 00000000003a18f0 __float128 0f SECT 08 0000 [.const_data] AMDRadeonX4000_AMDUVDHWChannel::superClass 000000000004e6d2 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDUVDHWChannel::initUVDThread() 000000000004e7d4 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDUVDHWChannel::setPowerState(unsigned int) 000000000004e7a8 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDUVDHWChannel::enableUVDThread() 000000000004e77c __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDUVDHWChannel::disableUVDThread() 000000000004e644 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDUVDHWChannel::releaseUVDThread() 000000000004e882 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDUVDHWChannel::waitForTimestamp(unsigned int, unsigned int, unsigned long long*, bool) 000000000004e5f6 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDUVDHWChannel::setPollingInterval(unsigned int) 000000000004e924 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDUVDHWChannel::submitCommandBuffer(AMD_SUBMIT_COMMAND_BUFFER_INFO*, unsigned int*) 000000000004e8c4 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDUVDHWChannel::setTimestampWriteback(unsigned int*, unsigned long long) 000000000004e876 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDUVDHWChannel::timeStampInterruptType() 000000000004eb4e __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDUVDHWChannel::timeStampDisableInterrupt() 000000000004e728 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDUVDHWChannel::handleUVDThreadPMInterrupt(OSObject*, IOInterruptEventSource*, int) 000000000004ead8 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDUVDHWChannel::registerTimestampInterrupt() 000000000004ec0e __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDUVDHWChannel::uvdTimestampDisableInterrupt() 000000000004e990 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDUVDHWChannel::uvdtimeStampInterruptCallback(OSObject*, void*) 000000000004e620 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDUVDHWChannel::free() 000000000004e55e __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDUVDHWChannel::init(int, AMDRadeonX4000_IAMDHWInterface*, AMDRadeonX4000_IAMDHWEngine*, AMDRadeonX4000_IAMDHWRing*, char const*) 000000000004e484 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDUVDHWChannel::MetaClass::MetaClass() 000000000004e524 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDUVDHWChannel::MetaClass::MetaClass() 00000000003a18e8 __float128 0f SECT 08 0000 [.const_data] AMDRadeonX4000_AMDUVDHWChannel::metaClass 000000000004e4c0 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDUVDHWChannel::AMDRadeonX4000_AMDUVDHWChannel(OSMetaClass const*) 000000000004e4f4 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDUVDHWChannel::~AMDRadeonX4000_AMDUVDHWChannel() 000000000004e4ea __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDUVDHWChannel::~AMDRadeonX4000_AMDUVDHWChannel() 000000000004e4e0 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDUVDHWChannel::~AMDRadeonX4000_AMDUVDHWChannel() 000000000052dfb8 __float128 0f SECT 0a 0000 [__DATA.__common] AMDRadeonX4000_AMDVCEHWChannel::gMetaClass 00000000003a9e38 __float128 0f SECT 08 0000 [.const_data] AMDRadeonX4000_AMDVCEHWChannel::superClass 0000000000060eec __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDVCEHWChannel::submitCommandBuffer(AMD_SUBMIT_COMMAND_BUFFER_INFO*, unsigned int*) 0000000000060ed8 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDVCEHWChannel::alignIBCommandBuffer(unsigned int*, unsigned int) 0000000000060ee0 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDVCEHWChannel::timeStampInterruptType() 0000000000060e9c __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDVCEHWChannel::free() 0000000000060e3a __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDVCEHWChannel::init(int, AMDRadeonX4000_IAMDHWInterface*, AMDRadeonX4000_IAMDHWEngine*, AMDRadeonX4000_IAMDHWRing*, char const*) 0000000000060d60 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDVCEHWChannel::MetaClass::MetaClass() 0000000000060e00 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDVCEHWChannel::MetaClass::MetaClass() 00000000003a9e30 __float128 0f SECT 08 0000 [.const_data] AMDRadeonX4000_AMDVCEHWChannel::metaClass 0000000000060d9c __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDVCEHWChannel::AMDRadeonX4000_AMDVCEHWChannel(OSMetaClass const*) 0000000000060dd0 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDVCEHWChannel::~AMDRadeonX4000_AMDVCEHWChannel() 0000000000060dc6 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDVCEHWChannel::~AMDRadeonX4000_AMDVCEHWChannel() 0000000000060dbc __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDVCEHWChannel::~AMDRadeonX4000_AMDVCEHWChannel() 000000000052da68 __float128 0f SECT 0a 0000 [__DATA.__common] AMDRadeonX4000_IAMDHWInterface::gMetaClass 00000000003a3348 __float128 0f SECT 08 0000 [.const_data] AMDRadeonX4000_IAMDHWInterface::superClass 0000000000052560 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_IAMDHWInterface::MetaClass::MetaClass() 0000000000052600 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_IAMDHWInterface::MetaClass::MetaClass() 00000000003a3340 __float128 0f SECT 08 0000 [.const_data] AMDRadeonX4000_IAMDHWInterface::metaClass 000000000005259c __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_IAMDHWInterface::AMDRadeonX4000_IAMDHWInterface(OSMetaClass const*) 00000000000525d0 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_IAMDHWInterface::~AMDRadeonX4000_IAMDHWInterface() 00000000000525c6 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_IAMDHWInterface::~AMDRadeonX4000_IAMDHWInterface() 00000000000525bc __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_IAMDHWInterface::~AMDRadeonX4000_IAMDHWInterface() 000000000052db08 __float128 0f SECT 0a 0000 [__DATA.__common] AMDRadeonX4000_IAMDHWRegisters::gMetaClass 00000000003a42b0 __float128 0f SECT 08 0000 [.const_data] AMDRadeonX4000_IAMDHWRegisters::superClass 00000000000528c8 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_IAMDHWRegisters::MetaClass::MetaClass() 0000000000052968 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_IAMDHWRegisters::MetaClass::MetaClass() 00000000003a42a8 __float128 0f SECT 08 0000 [.const_data] AMDRadeonX4000_IAMDHWRegisters::metaClass 0000000000052904 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_IAMDHWRegisters::AMDRadeonX4000_IAMDHWRegisters(OSMetaClass const*) 0000000000052938 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_IAMDHWRegisters::~AMDRadeonX4000_IAMDHWRegisters() 000000000005292e __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_IAMDHWRegisters::~AMDRadeonX4000_IAMDHWRegisters() 0000000000052924 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_IAMDHWRegisters::~AMDRadeonX4000_IAMDHWRegisters() 000000000052dba8 __float128 0f SECT 0a 0000 [__DATA.__common] AMDRadeonX4000_IAMDHWSemaphore::gMetaClass 00000000003a4df0 __float128 0f SECT 08 0000 [.const_data] AMDRadeonX4000_IAMDHWSemaphore::superClass 0000000000052c30 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_IAMDHWSemaphore::MetaClass::MetaClass() 0000000000052cd0 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_IAMDHWSemaphore::MetaClass::MetaClass() 00000000003a4de8 __float128 0f SECT 08 0000 [.const_data] AMDRadeonX4000_IAMDHWSemaphore::metaClass 0000000000052c6c __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_IAMDHWSemaphore::AMDRadeonX4000_IAMDHWSemaphore(OSMetaClass const*) 0000000000052ca0 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_IAMDHWSemaphore::~AMDRadeonX4000_IAMDHWSemaphore() 0000000000052c96 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_IAMDHWSemaphore::~AMDRadeonX4000_IAMDHWSemaphore() 0000000000052c8c __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_IAMDHWSemaphore::~AMDRadeonX4000_IAMDHWSemaphore() 000000000052dc20 __float128 0f SECT 0a 0000 [__DATA.__common] AMDRadeonX4000_IAMDHWUtilities::gMetaClass 00000000003a5520 __float128 0f SECT 08 0000 [.const_data] AMDRadeonX4000_IAMDHWUtilities::superClass 0000000000052ebe __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_IAMDHWUtilities::MetaClass::MetaClass() 0000000000052f5e __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_IAMDHWUtilities::MetaClass::MetaClass() 00000000003a5518 __float128 0f SECT 08 0000 [.const_data] AMDRadeonX4000_IAMDHWUtilities::metaClass 0000000000052efa __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_IAMDHWUtilities::AMDRadeonX4000_IAMDHWUtilities(OSMetaClass const*) 0000000000052f2e __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_IAMDHWUtilities::~AMDRadeonX4000_IAMDHWUtilities() 0000000000052f24 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_IAMDHWUtilities::~AMDRadeonX4000_IAMDHWUtilities() 0000000000052f1a __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_IAMDHWUtilities::~AMDRadeonX4000_IAMDHWUtilities() 000000000052dce8 __float128 0f SECT 0a 0000 [__DATA.__common] AMDRadeonX4000_IAMDHWVMContext::gMetaClass 00000000003a6390 __float128 0f SECT 08 0000 [.const_data] AMDRadeonX4000_IAMDHWVMContext::superClass 0000000000053300 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_IAMDHWVMContext::MetaClass::MetaClass() 00000000000533a0 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_IAMDHWVMContext::MetaClass::MetaClass() 00000000003a6388 __float128 0f SECT 08 0000 [.const_data] AMDRadeonX4000_IAMDHWVMContext::metaClass 000000000005333c __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_IAMDHWVMContext::AMDRadeonX4000_IAMDHWVMContext(OSMetaClass const*) 0000000000053370 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_IAMDHWVMContext::~AMDRadeonX4000_IAMDHWVMContext() 0000000000053366 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_IAMDHWVMContext::~AMDRadeonX4000_IAMDHWVMContext() 000000000005335c __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_IAMDHWVMContext::~AMDRadeonX4000_IAMDHWVMContext() 000000000052cf30 __float128 0f SECT 0a 0000 [__DATA.__common] AMDRadeonX4000_AMDAccelResource::gMetaClass 000000000000a914 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelResource::initialize(IOAccelNewResourceArgs*, unsigned long long) 000000000038b5f8 __float128 0f SECT 08 0000 [.const_data] AMDRadeonX4000_AMDAccelResource::superClass 000000000000b4dc __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelResource::allocMemory(IOAccelShared2*) 000000000000fac6 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelResource::pageTexture(bool, IOAccelMemoryMap*, IOAccelMemoryMap*) 000000000000ff0c __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelResource::addToChannel(IOAccelChannel2*, unsigned int) 000000000000a738 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelResource::addToAperture() 000000000000c836 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelResource::updateRefInfo() 000000000000bd00 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelResource::getLevelOffset(unsigned char, unsigned char, int*) 000000000000f2b8 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelResource::MSAATextureRead(AMDTextureMSAAPagingPacket*, IOAccelMemoryMap*, unsigned long long) 000000000000de38 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelResource::allocMaskMemory() 000000000000dfbe __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelResource::pageOnOffBuffer(_UBM_SURFINFO*, _UBM_SURFINFO*, IOAccelMemoryMap*, IOAccelMemoryMap*, unsigned int, _UBM_RECTL*, _UBM_RECTL*) 000000000000f820 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelResource::MSAATextureWrite(AMDTextureMSAAPagingPacket*, IOAccelMemoryMap*, unsigned long long) 000000000000a316 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelResource::getVRAMMemoryMap() 000000000000c9d4 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelResource::prepareMaskMemory(_eMaskMemoryType, IOAccelTask*) 000000000000cac2 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelResource::completeMaskMemory(_eMaskMemoryType) 000000000000ea62 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelResource::createTempResource(_UBM_SURFINFO const*, eAMDTempBufferType) 000000000000bf1a __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelResource::fillUBMSurfaceInfo(_UBM_SURFINFO*, _sMASK_MEMORY_SETTINGS*, unsigned int, unsigned int, unsigned int) 000000000000cd20 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelResource::freeVramMaskMemory(_eMaskMemoryType) 000000000000c82e __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelResource::get_texture_offset(unsigned long long) 000000000000a58a __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelResource::initMaskMemoryData() 000000000000e21c __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelResource::pageOff24d8sBuffer(_UBM_SURFINFO*, _UBM_SURFINFO*, IOAccelMemoryMap*, IOAccelMemoryMap*, _UBM_RECTL*, _UBM_RECTL*) 000000000000ee58 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelResource::pageOffDepthBuffer(_UBM_SURFINFO*, _UBM_SURFINFO*, IOAccelMemoryMap*, IOAccelMemoryMap*, _UBM_RECTL*, _UBM_RECTL*) 000000000000a844 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelResource::removeFromAperture() 000000000000cbd6 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelResource::allocVramMaskMemory(_eMaskMemoryType, unsigned int, unsigned int, _eOP_ORIGINATOR) 000000000000bcfa __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelResource::rebuildPagingBuffer() 000000000000c6f0 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelResource::getGPUVirtualAddress(unsigned int, unsigned int, unsigned int) 000000000000b876 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelResource::prepareAllMaskMemory(IOAccelTask*) 000000000000b916 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelResource::completeAllMaskMemory() 000000000000bd9a __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelResource::getBackingLevelOffset(unsigned char, unsigned char, int*) 000000000001010a __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelResource::pageTextureWithMemcpy(bool, IOAccelMemoryMap*, IOAccelMemoryMap*) 000000000000b4c4 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelResource::setAllocMappingOption(unsigned int) 0000000000010014 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelResource::switchToPagingChannel(AMDRadeonX4000_AMDAccelResource::switchPagingChannelInfo&, bool) 000000000000d20a __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelResource::generateTextureMipMaps(IOAccelMemoryMap*) 000000000000c518 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelResource::getMaskMemoryUBMHandle(_eMaskMemoryType) 000000000000e520 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelResource::pageOffMSAADepthBuffer(_UBM_SURFINFO*, _UBM_SURFINFO*, IOAccelMemoryMap*, IOAccelMemoryMap*, _UBM_RECTL*, _UBM_RECTL*, unsigned int, unsigned int) 0000000000010c1e __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelResource::pageTextureWithStretch(bool, IOAccelMemoryMap*, IOAccelMemoryMap*) 000000000000de58 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelResource::copyTheProvidedResource(AMDRadeonX4000_AMDAccelResource const*) 000000000000cd94 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelResource::freeMaskMemoryResources(bool) 000000000000a55e __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelResource::getMemoryAllocParameter() 0000000000011434 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelResource::pageTextureDepthStencil(bool, IOAccelMemoryMap*, IOAccelMemoryMap*) 000000000000ce10 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelResource::expandMaskMemoryIfNeeded(_eMaskMemoryType, IOAccelMemoryMap*) 000000000000cb96 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelResource::freeMaskMemoryDescriptor(_eMaskMemoryType) 000000000000cff0 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelResource::getAlignmentRequirements(unsigned int*, unsigned long long*) 00000000000100b6 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelResource::restoreFromPagingChannel(AMDRadeonX4000_AMDAccelResource::switchPagingChannelInfo&) 000000000000cae6 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelResource::allocMaskMemoryDescriptor(_eMaskMemoryType) 000000000000b63a __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelResource::isBackingAllocationLinear() 000000000000dace __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelResource::allocColorBufferMaskMemory() 000000000000a41c __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelResource::configureAllocationOptions() 000000000000bfb6 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelResource::fillUBMSurfaceInfoInternal(_UBM_SURFINFO*, _sMASK_MEMORY_SETTINGS*, IOAccelMemoryMap*, AMDRadeonX4000_AMDAccelResource*, unsigned int, unsigned int, unsigned int) 0000000000010824 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelResource::pageTextureWithSurfaceCopy(bool, IOAccelMemoryMap*, IOAccelMemoryMap*) 000000000000a8ce __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelResource::getApertureMemoryDescriptor(unsigned long long*) 000000000000cfb0 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelResource::determineMaskMemoryAllocBytes(unsigned int, unsigned int&, _AMD_MASK_SURFACE_BUFFER_PARAMS const*) 000000000000a6f2 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelResource::getMaskMemoryGPUVirtualAddress(_eMaskMemoryType) 000000000001053c __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelResource::pageTextureWithMemcpyNoVendBuf(bool, IOAccelMemoryMap*, IOAccelMemoryMap*) 0000000000011036 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelResource::pageTextureWithStretchNoVendBuf(bool, IOAccelMemoryMap*, IOAccelMemoryMap*) 000000000000dd6e __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelResource::allocDepthStencilBufferMaskMemory() 000000000000be34 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelResource::calculateIOSurfaceDeviceCacheVRAMBytes(unsigned long long*, unsigned int*) 000000000000d486 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelResource::determineMaskMemoryAllocBytesForColorBuffer(unsigned int, unsigned int&, bool, _AMD_MASK_SURFACE_BUFFER_PARAMS const*) 000000000000a31e __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelResource::free() 000000000000a1ba __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelResource::init(IOGraphicsAccelerator2*, IOAccelShared2*, unsigned int) 000000000000d8f0 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelResource::determineMaskMemoryAllocBytesForDepthStencilBuffer(unsigned int, unsigned int&, _AMD_MASK_SURFACE_BUFFER_PARAMS const*) 000000000000b642 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelResource::pageon(IOAccelEvent*, bool) 000000000000b95a __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelResource::pageoff(IOAccelEvent*, bool, bool*) 000000000000fe88 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelResource::prepare() 000000000000fee8 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelResource::complete() 000000000000b59c __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelResource::fallback() 000000000000a0e0 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelResource::MetaClass::MetaClass() 000000000000a180 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelResource::MetaClass::MetaClass() 000000000038b5f0 __float128 0f SECT 08 0000 [.const_data] AMDRadeonX4000_AMDAccelResource::metaClass 000000000000a11c __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelResource::AMDRadeonX4000_AMDAccelResource(OSMetaClass const*) 000000000000a150 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelResource::~AMDRadeonX4000_AMDAccelResource() 000000000000a146 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelResource::~AMDRadeonX4000_AMDAccelResource() 000000000000a13c __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelResource::~AMDRadeonX4000_AMDAccelResource() 000000000052d9c8 __float128 0f SECT 0a 0000 [__DATA.__common] AMDRadeonX4000_AMDNullHWChannel::gMetaClass 00000000003a26d8 __float128 0f SECT 08 0000 [.const_data] AMDRadeonX4000_AMDNullHWChannel::superClass 00000000000502c0 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDNullHWChannel::MetaClass::MetaClass() 0000000000050380 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDNullHWChannel::MetaClass::MetaClass() 00000000003a26d0 __float128 0f SECT 08 0000 [.const_data] AMDRadeonX4000_AMDNullHWChannel::metaClass 000000000005031c __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDNullHWChannel::AMDRadeonX4000_AMDNullHWChannel(OSMetaClass const*) 00000000000503f2 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDNullHWChannel::AMDRadeonX4000_AMDNullHWChannel() 00000000000502fc __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDNullHWChannel::AMDRadeonX4000_AMDNullHWChannel(OSMetaClass const*) 0000000000050422 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDNullHWChannel::AMDRadeonX4000_AMDNullHWChannel() 0000000000050350 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDNullHWChannel::~AMDRadeonX4000_AMDNullHWChannel() 0000000000050346 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDNullHWChannel::~AMDRadeonX4000_AMDNullHWChannel() 000000000005033c __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDNullHWChannel::~AMDRadeonX4000_AMDNullHWChannel() 000000000052d0c0 __float128 0f SECT 0a 0000 [__DATA.__common] AMDRadeonX4000_AMDSPUAppContext::gMetaClass 000000000001b5b6 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDSPUAppContext::pageBuffer(_AMDSPUMemory*, bool) 000000000001b1be __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDSPUAppContext::setSession(unsigned int, unsigned int, unsigned int) 000000000038f8e8 __float128 0f SECT 08 0000 [.const_data] AMDRadeonX4000_AMDSPUAppContext::superClass 000000000001b20c __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDSPUAppContext::findSession(unsigned int, unsigned int*) 000000000001b240 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDSPUAppContext::createSession(unsigned int*) 000000000001b67e __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDSPUAppContext::releaseBuffer(_AMDSPUMemoryType, bool) 000000000001b298 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDSPUAppContext::allocateBuffer(_AMDSPUMemoryType, unsigned int, unsigned int, bool) 000000000001b1e6 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDSPUAppContext::releaseSession(unsigned int) 000000000001b150 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDSPUAppContext::releaseFeedback() 000000000001b020 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDSPUAppContext::allocateFeedback() 000000000001b7bc __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDSPUAppContext::getFeedBackStatus() 000000000001b770 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDSPUAppContext::releaseStateBuffer(_AMDSPUMemory*) 000000000001b550 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDSPUAppContext::allocateStateBuffer(_AMDSPUMemory*) 000000000001b110 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDSPUAppContext::free() 000000000001ade2 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDSPUAppContext::init(AMDRadeonX4000_IAMDHWInterface*, unsigned int, _AMD_SPU_APP_TYPE) 000000000001ac50 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDSPUAppContext::MetaClass::MetaClass() 000000000001ad10 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDSPUAppContext::MetaClass::MetaClass() 000000000038f8e0 __float128 0f SECT 08 0000 [.const_data] AMDRadeonX4000_AMDSPUAppContext::metaClass 000000000001acac __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDSPUAppContext::AMDRadeonX4000_AMDSPUAppContext(OSMetaClass const*) 000000000001ad82 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDSPUAppContext::AMDRadeonX4000_AMDSPUAppContext() 000000000001ac8c __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDSPUAppContext::AMDRadeonX4000_AMDSPUAppContext(OSMetaClass const*) 000000000001adb2 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDSPUAppContext::AMDRadeonX4000_AMDSPUAppContext() 000000000001ace0 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDSPUAppContext::~AMDRadeonX4000_AMDSPUAppContext() 000000000001acd6 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDSPUAppContext::~AMDRadeonX4000_AMDSPUAppContext() 000000000001accc __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDSPUAppContext::~AMDRadeonX4000_AMDSPUAppContext() 000000000052ee40 __float128 0f SECT 0a 0000 [__DATA.__common] AMDRadeonX4000_IAMDSMLInterface::gMetaClass 00000000003c0ad0 __float128 0f SECT 08 0000 [.const_data] AMDRadeonX4000_IAMDSMLInterface::superClass 0000000000124288 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_IAMDSMLInterface::MetaClass::MetaClass() 0000000000124328 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_IAMDSMLInterface::MetaClass::MetaClass() 00000000003c0ac8 __float128 0f SECT 08 0000 [.const_data] AMDRadeonX4000_IAMDSMLInterface::metaClass 00000000001242c4 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_IAMDSMLInterface::AMDRadeonX4000_IAMDSMLInterface(OSMetaClass const*) 00000000001242f8 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_IAMDSMLInterface::~AMDRadeonX4000_IAMDSMLInterface() 00000000001242ee __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_IAMDSMLInterface::~AMDRadeonX4000_IAMDSMLInterface() 00000000001242e4 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_IAMDSMLInterface::~AMDRadeonX4000_IAMDSMLInterface() 000000000052cff8 __float128 0f SECT 0a 0000 [__DATA.__common] AMDRadeonX4000_AMDAccel2DContext::gMetaClass 000000000038d4b8 __float128 0f SECT 08 0000 [.const_data] AMDRadeonX4000_AMDAccel2DContext::superClass 00000000000160a4 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccel2DContext::contextStop() 0000000000016092 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccel2DContext::contextStart() 00000000000167ba __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccel2DContext::isCopyOfSourceNecessary(_UBM_STRETCHINFO*) 00000000000160b6 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccel2DContext::blitCopy(IOAccelEvent*, IOAccelResource2*, IOAccelResource2*, IOAccel2DBlitRectStruc*, unsigned int) 0000000000016826 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccel2DContext::blitFill(IOAccelEvent*, unsigned int, IOAccelResource2*, IOAccel2DBlitRectStruc*, unsigned int) 0000000000015f00 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccel2DContext::MetaClass::MetaClass() 0000000000015fc0 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccel2DContext::MetaClass::MetaClass() 000000000038d4b0 __float128 0f SECT 08 0000 [.const_data] AMDRadeonX4000_AMDAccel2DContext::metaClass 0000000000015f5c __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccel2DContext::AMDRadeonX4000_AMDAccel2DContext(OSMetaClass const*) 0000000000016032 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccel2DContext::AMDRadeonX4000_AMDAccel2DContext() 0000000000015f3c __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccel2DContext::AMDRadeonX4000_AMDAccel2DContext(OSMetaClass const*) 0000000000016062 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccel2DContext::AMDRadeonX4000_AMDAccel2DContext() 0000000000015f90 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccel2DContext::~AMDRadeonX4000_AMDAccel2DContext() 0000000000015f86 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccel2DContext::~AMDRadeonX4000_AMDAccel2DContext() 0000000000015f7c __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccel2DContext::~AMDRadeonX4000_AMDAccel2DContext() 000000000052d478 __float128 0f SECT 0a 0000 [__DATA.__common] AMDRadeonX4000_AMDAccelCLContext::gMetaClass 0000000000392018 __float128 0f SECT 08 0000 [.const_data] AMDRadeonX4000_AMDAccelCLContext::superClass 0000000000026846 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelCLContext::contextStop() 000000000002664a __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelCLContext::contextStart() 0000000000026b20 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelCLContext::enableContext() 0000000000026bde __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelCLContext::disableContext() 000000000002696e __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelCLContext::endCommandStream(IOAccelCommandStreamInfo&) 0000000000026950 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelCLContext::beginCommandStream(IOAccelCommandStreamInfo&) 0000000000026ec2 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelCLContext::allocAndLoadResources() 0000000000026abe __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelCLContext::addDataBufferToChannel(IOAccelResource2*, unsigned int) 0000000000026e4e __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelCLContext::addToKeepResourcesList(IOAccelResource2*, unsigned int) 0000000000026c86 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelCLContext::remapComputeRingBuffer() 000000000012f690 __float128 0f SECT 03 0000 [.const] AMDRadeonX4000_AMDAccelCLContext::submitRingBufferEntries 0000000000026d94 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelCLContext::checkSubmitRingBufferFull() 0000000000026be8 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelCLContext::teardownComputeRingBuffer() 0000000000026dc4 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelCLContext::finishAndCleanupAllContexts() 0000000000026b2a __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelCLContext::reallocateComputeRingBuffer() 0000000000026af4 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelCLContext::removeDataBufferFromChannel(IOAccelResource2*, unsigned int) 000000000002713a __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelCLContext::pageOffAndDeallocateKeepResources() 0000000000026570 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelCLContext::MetaClass::MetaClass() 0000000000026610 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelCLContext::MetaClass::MetaClass() 0000000000392010 __float128 0f SECT 08 0000 [.const_data] AMDRadeonX4000_AMDAccelCLContext::metaClass 00000000000265ac __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelCLContext::AMDRadeonX4000_AMDAccelCLContext(OSMetaClass const*) 00000000000265e0 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelCLContext::~AMDRadeonX4000_AMDAccelCLContext() 00000000000265d6 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelCLContext::~AMDRadeonX4000_AMDAccelCLContext() 00000000000265cc __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelCLContext::~AMDRadeonX4000_AMDAccelCLContext() 000000000052d518 __float128 0f SECT 0a 0000 [__DATA.__common] AMDRadeonX4000_AMDAccelMemoryMap::gMetaClass 0000000000393438 __float128 0f SECT 08 0000 [.const_data] AMDRadeonX4000_AMDAccelMemoryMap::superClass 0000000000028d2a __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelMemoryMap::updateGPUPageTable() 00000000000289f0 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelMemoryMap::getGPUVirtualAddress() 0000000000028a26 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelMemoryMap::getGPUPhysicalAddress() 0000000000028a9a __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelMemoryMap::commitIntoGPUPageTable() 0000000000028c74 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelMemoryMap::releaseFromGPUPageTable() 000000000002889e __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelMemoryMap::initWithVidMemoryOptions(IOGraphicsAccelerator2*, IOAccelShared2*, IOAccelTask*, unsigned int, unsigned long long, unsigned long long, _eOP_ORIGINATOR, _eOP_TYPE) 000000000002884e __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelMemoryMap::free() 00000000000286a2 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelMemoryMap::init(IOGraphicsAccelerator2*, IOAccelTask*, IOAccelMemory*, unsigned int) 0000000000028d38 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelMemoryMap::remap(unsigned long long) 0000000000028958 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelMemoryMap::prepare() 0000000000028510 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelMemoryMap::MetaClass::MetaClass() 00000000000285d0 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelMemoryMap::MetaClass::MetaClass() 0000000000393430 __float128 0f SECT 08 0000 [.const_data] AMDRadeonX4000_AMDAccelMemoryMap::metaClass 000000000002856c __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelMemoryMap::AMDRadeonX4000_AMDAccelMemoryMap(OSMetaClass const*) 0000000000028642 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelMemoryMap::AMDRadeonX4000_AMDAccelMemoryMap() 000000000002854c __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelMemoryMap::AMDRadeonX4000_AMDAccelMemoryMap(OSMetaClass const*) 0000000000028672 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelMemoryMap::AMDRadeonX4000_AMDAccelMemoryMap() 00000000000285a0 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelMemoryMap::~AMDRadeonX4000_AMDAccelMemoryMap() 0000000000028596 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelMemoryMap::~AMDRadeonX4000_AMDAccelMemoryMap() 000000000002858c __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelMemoryMap::~AMDRadeonX4000_AMDAccelMemoryMap() 000000000052d4c8 __float128 0f SECT 0a 0000 [__DATA.__common] AMDRadeonX4000_AMDAccelSysMemory::gMetaClass 0000000000392e98 __float128 0f SECT 08 0000 [.const_data] AMDRadeonX4000_AMDAccelSysMemory::superClass 0000000000027c88 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelSysMemory::free() 0000000000027c62 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelSysMemory::init(IOGraphicsAccelerator2*) 0000000000027ad0 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelSysMemory::MetaClass::MetaClass() 0000000000027b90 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelSysMemory::MetaClass::MetaClass() 0000000000392e90 __float128 0f SECT 08 0000 [.const_data] AMDRadeonX4000_AMDAccelSysMemory::metaClass 0000000000027b2c __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelSysMemory::AMDRadeonX4000_AMDAccelSysMemory(OSMetaClass const*) 0000000000027c02 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelSysMemory::AMDRadeonX4000_AMDAccelSysMemory() 0000000000027b0c __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelSysMemory::AMDRadeonX4000_AMDAccelSysMemory(OSMetaClass const*) 0000000000027c32 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelSysMemory::AMDRadeonX4000_AMDAccelSysMemory() 0000000000027b60 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelSysMemory::~AMDRadeonX4000_AMDAccelSysMemory() 0000000000027b56 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelSysMemory::~AMDRadeonX4000_AMDAccelSysMemory() 0000000000027b4c __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelSysMemory::~AMDRadeonX4000_AMDAccelSysMemory() 000000000052d4f0 __float128 0f SECT 0a 0000 [__DATA.__common] AMDRadeonX4000_AMDAccelVidMemory::gMetaClass 0000000000393158 __float128 0f SECT 08 0000 [.const_data] AMDRadeonX4000_AMDAccelVidMemory::superClass 0000000000028144 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelVidMemory::allocPhysical() 00000000000280b0 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelVidMemory::matchForReuse(void*, unsigned long long) 00000000000283e6 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelVidMemory::deallocPhysical() 0000000000028074 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelVidMemory::getPhysicalSegment(unsigned long long, unsigned long long*) 000000000002802a __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelVidMemory::withPhysicalAddress(IOGraphicsAccelerator2*, unsigned long long, unsigned long long, _AMD_VID_MEM_ALLOC_PARAMS*) 0000000000028470 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelVidMemory::setAllocMappingOption(unsigned int) 0000000000027fee __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelVidMemory::free() 0000000000027ed2 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelVidMemory::init(IOGraphicsAccelerator2*, IOAccelShared2*, IOAccelResource2*, unsigned long long, void*) 0000000000027d40 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelVidMemory::MetaClass::MetaClass() 0000000000027e00 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelVidMemory::MetaClass::MetaClass() 0000000000393150 __float128 0f SECT 08 0000 [.const_data] AMDRadeonX4000_AMDAccelVidMemory::metaClass 0000000000027d9c __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelVidMemory::AMDRadeonX4000_AMDAccelVidMemory(OSMetaClass const*) 0000000000027e72 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelVidMemory::AMDRadeonX4000_AMDAccelVidMemory() 0000000000027d7c __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelVidMemory::AMDRadeonX4000_AMDAccelVidMemory(OSMetaClass const*) 0000000000027ea2 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelVidMemory::AMDRadeonX4000_AMDAccelVidMemory() 0000000000027dd0 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelVidMemory::~AMDRadeonX4000_AMDAccelVidMemory() 0000000000027dc6 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelVidMemory::~AMDRadeonX4000_AMDAccelVidMemory() 0000000000027dbc __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelVidMemory::~AMDRadeonX4000_AMDAccelVidMemory() 000000000052efd0 __float128 0f SECT 0a 0000 [__DATA.__common] AMDRadeonX4000_AMDHDCPGetCertMsg::gMetaClass 00000000003c2550 __float128 0f SECT 08 0000 [.const_data] AMDRadeonX4000_AMDHDCPGetCertMsg::superClass 0000000000126b06 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHDCPGetCertMsg::setOutBuffer(int, unsigned long long, unsigned char*) 0000000000126af4 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHDCPGetCertMsg::free() 0000000000126a48 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHDCPGetCertMsg::init(void*) 00000000001268b6 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHDCPGetCertMsg::MetaClass::MetaClass() 0000000000126976 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHDCPGetCertMsg::MetaClass::MetaClass() 0000000000126b2a __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHDCPGetCertMsg::getOutput() 00000000003c2548 __float128 0f SECT 08 0000 [.const_data] AMDRadeonX4000_AMDHDCPGetCertMsg::metaClass 0000000000126912 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHDCPGetCertMsg::AMDRadeonX4000_AMDHDCPGetCertMsg(OSMetaClass const*) 00000000001269e8 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHDCPGetCertMsg::AMDRadeonX4000_AMDHDCPGetCertMsg() 00000000001268f2 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHDCPGetCertMsg::AMDRadeonX4000_AMDHDCPGetCertMsg(OSMetaClass const*) 0000000000126a18 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHDCPGetCertMsg::AMDRadeonX4000_AMDHDCPGetCertMsg() 0000000000126946 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHDCPGetCertMsg::~AMDRadeonX4000_AMDHDCPGetCertMsg() 000000000012693c __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHDCPGetCertMsg::~AMDRadeonX4000_AMDHDCPGetCertMsg() 0000000000126932 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHDCPGetCertMsg::~AMDRadeonX4000_AMDHDCPGetCertMsg() 000000000052d9a0 __float128 0f SECT 0a 0000 [__DATA.__common] AMDRadeonX4000_AMDHWAlignManager::gMetaClass 00000000003a23f8 __float128 0f SECT 08 0000 [.const_data] AMDRadeonX4000_AMDHWAlignManager::superClass 000000000004fdf4 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHWAlignManager::getCMaskInfo(_ADDR_COMPUTE_CMASKINFO_INPUT*, _ADDR_COMPUTE_CMASK_INFO_OUTPUT*) 000000000004fe4e __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHWAlignManager::getFMaskInfo(_ADDR_COMPUTE_FMASK_INFO_INPUT*, _ADDR_COMPUTE_FMASK_INFO_OUTPUT*, _ADDR_TILEINFO*, _ADDR_TILEINFO*) 000000000004fd9a __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHWAlignManager::getHTileInfo(_ADDR_COMPUTE_HTILE_INFO_INPUT*, _ADDR_COMPUTE_HTILE_INFO_OUTPUT*) 0000000000050002 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHWAlignManager::getTileIndex(_AddrTileMode, _AddrTileType, _ADDR_TILEINFO*) 000000000004ff7e __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHWAlignManager::getAddrFormat(unsigned int) 000000000005009e __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHWAlignManager::fillTilingInfo(AMD_TILING_INFO*, _ADDR_TILEINFO const*, _AddrTileMode, int, _AddrTileType) 000000000004fa3e __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHWAlignManager::getStencilInfo(_ADDR_COMPUTE_SURFACE_INFO_INPUT*, _ADDR_COMPUTE_SURFACE_INFO_OUTPUT*, _ADDR_TILEINFO*, _ADDR_TILEINFO*) 000000000004f97c __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHWAlignManager::getSurfaceInfo(_ADDR_COMPUTE_SURFACE_INFO_INPUT*, _ADDR_COMPUTE_SURFACE_INFO_OUTPUT*, _ADDR_TILEINFO*) 0000000000050060 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHWAlignManager::fillSurfaceInfo(_ADDR_COMPUTE_HTILE_INFO_INPUT*) 00000000000501a4 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHWAlignManager::fillAddrTileInfo(_ADDR_TILEINFO*, AMD_TILING_INFO const*) 000000000004ff68 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHWAlignManager::isTileModeLinear(unsigned int) 000000000004f924 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHWAlignManager::AddrLibDebugPrint(_ADDR_DEBUGPRINT_INPUT const*) 000000000004f90a __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHWAlignManager::AddrLibFreeSysMem(_ADDR_FREESYSMEM_INPUT const*) 000000000004f8c2 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHWAlignManager::AddrLibAllocSysMem(_ADDR_ALLOCSYSMEM_INPUT const*) 000000000004fb6e __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHWAlignManager::getMipMapSurfaceInfo(_ADDR_COMPUTE_SURFACE_INFO_INPUT*, _ADDR_COMPUTE_SURFACE_INFO_OUTPUT*, unsigned int, unsigned int*, _ADDR_TILEINFO*) 000000000004ff98 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHWAlignManager::convertSurfaceTileInfo(_ADDR_TILEINFO*, _ADDR_TILEINFO*, bool) 000000000004f92c __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHWAlignManager::free() 000000000004f6a2 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHWAlignManager::init(AMDRadeonX4000_IAMDHWInterface*) 000000000004f510 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHWAlignManager::MetaClass::MetaClass() 000000000004f5d0 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHWAlignManager::MetaClass::MetaClass() 00000000003a23f0 __float128 0f SECT 08 0000 [.const_data] AMDRadeonX4000_AMDHWAlignManager::metaClass 000000000004f56c __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHWAlignManager::AMDRadeonX4000_AMDHWAlignManager(OSMetaClass const*) 000000000004f642 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHWAlignManager::AMDRadeonX4000_AMDHWAlignManager() 000000000004f54c __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHWAlignManager::AMDRadeonX4000_AMDHWAlignManager(OSMetaClass const*) 000000000004f672 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHWAlignManager::AMDRadeonX4000_AMDHWAlignManager() 000000000004f5a0 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHWAlignManager::~AMDRadeonX4000_AMDHWAlignManager() 000000000004f596 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHWAlignManager::~AMDRadeonX4000_AMDHWAlignManager() 000000000004f58c __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHWAlignManager::~AMDRadeonX4000_AMDHWAlignManager() 000000000052f0c0 __float128 0f SECT 0a 0000 [__DATA.__common] AMDRadeonX4000_AMDSMLSIInterface::gMetaClass 00000000003c34b8 __float128 0f SECT 08 0000 [.const_data] AMDRadeonX4000_AMDSMLSIInterface::superClass 0000000000127ef4 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDSMLSIInterface::free() 0000000000127ee2 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDSMLSIInterface::init(unsigned int) 0000000000127d50 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDSMLSIInterface::MetaClass::MetaClass() 0000000000127e10 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDSMLSIInterface::MetaClass::MetaClass() 0000000000127f2e __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDSMLSIInterface::createDRM() 0000000000127f56 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDSMLSIInterface::createSPU() 0000000000127f06 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDSMLSIInterface::createUVD() 0000000000127f7e __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDSMLSIInterface::createVCE() 00000000003c34b0 __float128 0f SECT 08 0000 [.const_data] AMDRadeonX4000_AMDSMLSIInterface::metaClass 0000000000127dac __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDSMLSIInterface::AMDRadeonX4000_AMDSMLSIInterface(OSMetaClass const*) 0000000000127e82 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDSMLSIInterface::AMDRadeonX4000_AMDSMLSIInterface() 0000000000127d8c __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDSMLSIInterface::AMDRadeonX4000_AMDSMLSIInterface(OSMetaClass const*) 0000000000127eb2 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDSMLSIInterface::AMDRadeonX4000_AMDSMLSIInterface() 0000000000127de0 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDSMLSIInterface::~AMDRadeonX4000_AMDSMLSIInterface() 0000000000127dd6 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDSMLSIInterface::~AMDRadeonX4000_AMDSMLSIInterface() 0000000000127dcc __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDSMLSIInterface::~AMDRadeonX4000_AMDSMLSIInterface() 000000000052f250 __float128 0f SECT 0a 0000 [__DATA.__common] AMDRadeonX4000_AMDSMLVIInterface::gMetaClass 00000000003c4f58 __float128 0f SECT 08 0000 [.const_data] AMDRadeonX4000_AMDSMLVIInterface::superClass 000000000012b604 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDSMLVIInterface::free() 000000000012b5f2 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDSMLVIInterface::init(unsigned int) 000000000012b460 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDSMLVIInterface::MetaClass::MetaClass() 000000000012b520 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDSMLVIInterface::MetaClass::MetaClass() 000000000012b63e __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDSMLVIInterface::createDRM() 000000000012b666 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDSMLVIInterface::createSPU() 000000000012b616 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDSMLVIInterface::createUVD() 000000000012b68e __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDSMLVIInterface::createVCE() 00000000003c4f50 __float128 0f SECT 08 0000 [.const_data] AMDRadeonX4000_AMDSMLVIInterface::metaClass 000000000012b4bc __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDSMLVIInterface::AMDRadeonX4000_AMDSMLVIInterface(OSMetaClass const*) 000000000012b592 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDSMLVIInterface::AMDRadeonX4000_AMDSMLVIInterface() 000000000012b49c __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDSMLVIInterface::AMDRadeonX4000_AMDSMLVIInterface(OSMetaClass const*) 000000000012b5c2 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDSMLVIInterface::AMDRadeonX4000_AMDSMLVIInterface() 000000000012b4f0 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDSMLVIInterface::~AMDRadeonX4000_AMDSMLVIInterface() 000000000012b4e6 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDSMLVIInterface::~AMDRadeonX4000_AMDSMLVIInterface() 000000000012b4dc __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDSMLVIInterface::~AMDRadeonX4000_AMDSMLVIInterface() 000000000052cfa8 __float128 0f SECT 0a 0000 [__DATA.__common] AMDRadeonX4000_AMDAccelStatistics::gMetaClass 000000000038c768 __float128 0f SECT 08 0000 [.const_data] AMDRadeonX4000_AMDAccelStatistics::superClass 0000000000012764 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelStatistics::writeInternalStats(OSDictionary*, bool) 000000000001287e __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelStatistics::writePerformanceStats(OSDictionary*, bool) 0000000000012752 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelStatistics::init(IOGraphicsAccelerator2*) 00000000000125c0 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelStatistics::MetaClass::MetaClass() 0000000000012680 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelStatistics::MetaClass::MetaClass() 000000000038c760 __float128 0f SECT 08 0000 [.const_data] AMDRadeonX4000_AMDAccelStatistics::metaClass 000000000001261c __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelStatistics::AMDRadeonX4000_AMDAccelStatistics(OSMetaClass const*) 00000000000126f2 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelStatistics::AMDRadeonX4000_AMDAccelStatistics() 00000000000125fc __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelStatistics::AMDRadeonX4000_AMDAccelStatistics(OSMetaClass const*) 0000000000012722 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelStatistics::AMDRadeonX4000_AMDAccelStatistics() 0000000000012650 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelStatistics::~AMDRadeonX4000_AMDAccelStatistics() 0000000000012646 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelStatistics::~AMDRadeonX4000_AMDAccelStatistics() 000000000001263c __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelStatistics::~AMDRadeonX4000_AMDAccelStatistics() 000000000052d098 __float128 0f SECT 0a 0000 [__DATA.__common] AMDRadeonX4000_AMDAccelUVDContext::gMetaClass 000000000038f6a8 __float128 0f SECT 08 0000 [.const_data] AMDRadeonX4000_AMDAccelUVDContext::superClass 000000000001ab5a __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelUVDContext::saveUVDSession() 000000000001ab38 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelUVDContext::releaseCapability() 000000000001aac8 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelUVDContext::requestCapability(sUvdContextReturnInfo*) 000000000001ab84 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelUVDContext::restoreUVDSession(bool) 000000000001abb4 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelUVDContext::destroyUVDSSession() 000000000001aa0a __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelUVDContext::free() 000000000001a8a2 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelUVDContext::init(AMDRadeonX4000_AMDGraphicsAccelerator*, AMDRadeonX4000_AMDAccelVideoContext*, sUvdContextCreateInfo*) 000000000001aa86 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelUVDContext::stop() 000000000001a710 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelUVDContext::MetaClass::MetaClass() 000000000001a7d0 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelUVDContext::MetaClass::MetaClass() 000000000038f6a0 __float128 0f SECT 08 0000 [.const_data] AMDRadeonX4000_AMDAccelUVDContext::metaClass 000000000001a76c __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelUVDContext::AMDRadeonX4000_AMDAccelUVDContext(OSMetaClass const*) 000000000001a842 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelUVDContext::AMDRadeonX4000_AMDAccelUVDContext() 000000000001a74c __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelUVDContext::AMDRadeonX4000_AMDAccelUVDContext(OSMetaClass const*) 000000000001a872 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelUVDContext::AMDRadeonX4000_AMDAccelUVDContext() 000000000001a7a0 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelUVDContext::~AMDRadeonX4000_AMDAccelUVDContext() 000000000001a796 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelUVDContext::~AMDRadeonX4000_AMDAccelUVDContext() 000000000001a78c __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelUVDContext::~AMDRadeonX4000_AMDAccelUVDContext() 000000000052d138 __float128 0f SECT 0a 0000 [__DATA.__common] AMDRadeonX4000_AMDAccelVCEContext::gMetaClass 0000000000390138 __float128 0f SECT 08 0000 [.const_data] AMDRadeonX4000_AMDAccelVCEContext::superClass 000000000001efcc __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelVCEContext::setEncProperties(encode_properties_info*) 000000000001ee88 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelVCEContext::releaseCapability() 000000000001ee18 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelVCEContext::requestCapability(sVceContextReturnInfo*) 000000000001eeaa __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelVCEContext::restorePowerState() 000000000001ed40 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelVCEContext::free() 000000000001eb92 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelVCEContext::init(AMDRadeonX4000_AMDGraphicsAccelerator*, AMDRadeonX4000_AMDAccelVideoContext*, sVceContextCreateInfo*) 000000000001edb8 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelVCEContext::stop() 000000000001ea00 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelVCEContext::MetaClass::MetaClass() 000000000001eac0 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelVCEContext::MetaClass::MetaClass() 0000000000390130 __float128 0f SECT 08 0000 [.const_data] AMDRadeonX4000_AMDAccelVCEContext::metaClass 000000000001ea5c __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelVCEContext::AMDRadeonX4000_AMDAccelVCEContext(OSMetaClass const*) 000000000001eb32 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelVCEContext::AMDRadeonX4000_AMDAccelVCEContext() 000000000001ea3c __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelVCEContext::AMDRadeonX4000_AMDAccelVCEContext(OSMetaClass const*) 000000000001eb62 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelVCEContext::AMDRadeonX4000_AMDAccelVCEContext() 000000000001ea90 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelVCEContext::~AMDRadeonX4000_AMDAccelVCEContext() 000000000001ea86 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelVCEContext::~AMDRadeonX4000_AMDAccelVCEContext() 000000000001ea7c __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelVCEContext::~AMDRadeonX4000_AMDAccelVCEContext() 000000000052ddd8 __float128 0f SECT 0a 0000 [__DATA.__common] AMDRadeonX4000_AMDHWSemaphorePool::gMetaClass 00000000003a74b8 __float128 0f SECT 08 0000 [.const_data] AMDRadeonX4000_AMDHWSemaphorePool::superClass 0000000000057398 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHWSemaphorePool::allocSemaphore(bool) 00000000000575e8 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHWSemaphorePool::initializePool() 0000000000057524 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHWSemaphorePool::releaseSemaphore(AMDRadeonX4000_IAMDHWSemaphore*) 000000000005759c __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHWSemaphorePool::addSemaphoreToPool(AMDRadeonX4000_IAMDHWSemaphore*) 0000000000057312 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHWSemaphorePool::free() 00000000000571b2 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHWSemaphorePool::init(AMDRadeonX4000_IAMDHWInterface*) 00000000000576d8 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHWSemaphorePool::freePool() 0000000000057020 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHWSemaphorePool::MetaClass::MetaClass() 00000000000570e0 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHWSemaphorePool::MetaClass::MetaClass() 00000000003a74b0 __float128 0f SECT 08 0000 [.const_data] AMDRadeonX4000_AMDHWSemaphorePool::metaClass 000000000005707c __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHWSemaphorePool::AMDRadeonX4000_AMDHWSemaphorePool(OSMetaClass const*) 0000000000057152 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHWSemaphorePool::AMDRadeonX4000_AMDHWSemaphorePool() 000000000005705c __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHWSemaphorePool::AMDRadeonX4000_AMDHWSemaphorePool(OSMetaClass const*) 0000000000057182 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHWSemaphorePool::AMDRadeonX4000_AMDHWSemaphorePool() 00000000000570b0 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHWSemaphorePool::~AMDRadeonX4000_AMDHWSemaphorePool() 00000000000570a6 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHWSemaphorePool::~AMDRadeonX4000_AMDHWSemaphorePool() 000000000005709c __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHWSemaphorePool::~AMDRadeonX4000_AMDHWSemaphorePool() 000000000052ddb0 __float128 0f SECT 0a 0000 [__DATA.__common] AMDRadeonX4000_AMDNullHWSemaphore::gMetaClass 00000000003a7208 __float128 0f SECT 08 0000 [.const_data] AMDRadeonX4000_AMDNullHWSemaphore::superClass 0000000000056d90 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDNullHWSemaphore::MetaClass::MetaClass() 0000000000056e50 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDNullHWSemaphore::MetaClass::MetaClass() 00000000003a7200 __float128 0f SECT 08 0000 [.const_data] AMDRadeonX4000_AMDNullHWSemaphore::metaClass 0000000000056dec __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDNullHWSemaphore::AMDRadeonX4000_AMDNullHWSemaphore(OSMetaClass const*) 0000000000056ec2 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDNullHWSemaphore::AMDRadeonX4000_AMDNullHWSemaphore() 0000000000056dcc __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDNullHWSemaphore::AMDRadeonX4000_AMDNullHWSemaphore(OSMetaClass const*) 0000000000056ef2 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDNullHWSemaphore::AMDRadeonX4000_AMDNullHWSemaphore() 0000000000056e20 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDNullHWSemaphore::~AMDRadeonX4000_AMDNullHWSemaphore() 0000000000056e16 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDNullHWSemaphore::~AMDRadeonX4000_AMDNullHWSemaphore() 0000000000056e0c __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDNullHWSemaphore::~AMDRadeonX4000_AMDNullHWSemaphore() 000000000052f188 __float128 0f SECT 0a 0000 [__DATA.__common] AMDRadeonX4000_AMDSMLCIKInterface::gMetaClass 00000000003c4228 __float128 0f SECT 08 0000 [.const_data] AMDRadeonX4000_AMDSMLCIKInterface::superClass 00000000001299a4 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDSMLCIKInterface::free() 0000000000129992 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDSMLCIKInterface::init(unsigned int) 0000000000129800 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDSMLCIKInterface::MetaClass::MetaClass() 00000000001298c0 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDSMLCIKInterface::MetaClass::MetaClass() 00000000001299de __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDSMLCIKInterface::createDRM() 0000000000129a06 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDSMLCIKInterface::createSPU() 00000000001299b6 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDSMLCIKInterface::createUVD() 0000000000129a2e __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDSMLCIKInterface::createVCE() 00000000003c4220 __float128 0f SECT 08 0000 [.const_data] AMDRadeonX4000_AMDSMLCIKInterface::metaClass 000000000012985c __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDSMLCIKInterface::AMDRadeonX4000_AMDSMLCIKInterface(OSMetaClass const*) 0000000000129932 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDSMLCIKInterface::AMDRadeonX4000_AMDSMLCIKInterface() 000000000012983c __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDSMLCIKInterface::AMDRadeonX4000_AMDSMLCIKInterface(OSMetaClass const*) 0000000000129962 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDSMLCIKInterface::AMDRadeonX4000_AMDSMLCIKInterface() 0000000000129890 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDSMLCIKInterface::~AMDRadeonX4000_AMDSMLCIKInterface() 0000000000129886 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDSMLCIKInterface::~AMDRadeonX4000_AMDSMLCIKInterface() 000000000012987c __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDSMLCIKInterface::~AMDRadeonX4000_AMDSMLCIKInterface() 000000000052dae0 __float128 0f SECT 0a 0000 [__DATA.__common] AMDRadeonX4000_IAMDHWAlignManager::gMetaClass 00000000003a3fe0 __float128 0f SECT 08 0000 [.const_data] AMDRadeonX4000_IAMDHWAlignManager::superClass 00000000000527ee __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_IAMDHWAlignManager::MetaClass::MetaClass() 000000000005288e __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_IAMDHWAlignManager::MetaClass::MetaClass() 00000000003a3fd8 __float128 0f SECT 08 0000 [.const_data] AMDRadeonX4000_IAMDHWAlignManager::metaClass 000000000005282a __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_IAMDHWAlignManager::AMDRadeonX4000_IAMDHWAlignManager(OSMetaClass const*) 000000000005285e __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_IAMDHWAlignManager::~AMDRadeonX4000_IAMDHWAlignManager() 0000000000052854 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_IAMDHWAlignManager::~AMDRadeonX4000_IAMDHWAlignManager() 000000000005284a __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_IAMDHWAlignManager::~AMDRadeonX4000_IAMDHWAlignManager() 000000000052efa8 __float128 0f SECT 0a 0000 [__DATA.__common] AMDRadeonX4000_AMDHDCPGetStatusMsg::gMetaClass 00000000003c22c0 __float128 0f SECT 08 0000 [.const_data] AMDRadeonX4000_AMDHDCPGetStatusMsg::superClass 000000000012685a __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHDCPGetStatusMsg::setOutBuffer(int, unsigned long long, unsigned char*) 0000000000126848 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHDCPGetStatusMsg::free() 000000000012673a __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHDCPGetStatusMsg::init(void*) 00000000001265a8 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHDCPGetStatusMsg::MetaClass::MetaClass() 0000000000126668 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHDCPGetStatusMsg::MetaClass::MetaClass() 000000000012688a __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHDCPGetStatusMsg::getOutput() 00000000003c22b8 __float128 0f SECT 08 0000 [.const_data] AMDRadeonX4000_AMDHDCPGetStatusMsg::metaClass 0000000000126604 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHDCPGetStatusMsg::AMDRadeonX4000_AMDHDCPGetStatusMsg(OSMetaClass const*) 00000000001266da __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHDCPGetStatusMsg::AMDRadeonX4000_AMDHDCPGetStatusMsg() 00000000001265e4 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHDCPGetStatusMsg::AMDRadeonX4000_AMDHDCPGetStatusMsg(OSMetaClass const*) 000000000012670a __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHDCPGetStatusMsg::AMDRadeonX4000_AMDHDCPGetStatusMsg() 0000000000126638 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHDCPGetStatusMsg::~AMDRadeonX4000_AMDHDCPGetStatusMsg() 000000000012662e __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHDCPGetStatusMsg::~AMDRadeonX4000_AMDHDCPGetStatusMsg() 0000000000126624 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHDCPGetStatusMsg::~AMDRadeonX4000_AMDHDCPGetStatusMsg() 000000000052dbd0 __float128 0f SECT 0a 0000 [__DATA.__common] AMDRadeonX4000_IAMDHWSemaphorePool::gMetaClass 00000000003a5080 __float128 0f SECT 08 0000 [.const_data] AMDRadeonX4000_IAMDHWSemaphorePool::superClass 0000000000052d0a __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_IAMDHWSemaphorePool::MetaClass::MetaClass() 0000000000052daa __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_IAMDHWSemaphorePool::MetaClass::MetaClass() 00000000003a5078 __float128 0f SECT 08 0000 [.const_data] AMDRadeonX4000_IAMDHWSemaphorePool::metaClass 0000000000052d46 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_IAMDHWSemaphorePool::AMDRadeonX4000_IAMDHWSemaphorePool(OSMetaClass const*) 0000000000052d7a __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_IAMDHWSemaphorePool::~AMDRadeonX4000_IAMDHWSemaphorePool() 0000000000052d70 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_IAMDHWSemaphorePool::~AMDRadeonX4000_IAMDHWSemaphorePool() 0000000000052d66 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_IAMDHWSemaphorePool::~AMDRadeonX4000_IAMDHWSemaphorePool() 000000000052d400 __float128 0f SECT 0a 0000 [__DATA.__common] AMDRadeonX4000_IAMDStatisticsGroup::gMetaClass 00000000003918c8 __float128 0f SECT 08 0000 [.const_data] AMDRadeonX4000_IAMDStatisticsGroup::superClass 0000000000025cf0 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_IAMDStatisticsGroup::MetaClass::MetaClass() 0000000000025d90 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_IAMDStatisticsGroup::MetaClass::MetaClass() 00000000003918c0 __float128 0f SECT 08 0000 [.const_data] AMDRadeonX4000_IAMDStatisticsGroup::metaClass 0000000000025d2c __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_IAMDStatisticsGroup::AMDRadeonX4000_IAMDStatisticsGroup(OSMetaClass const*) 0000000000025d60 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_IAMDStatisticsGroup::~AMDRadeonX4000_IAMDStatisticsGroup() 0000000000025d56 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_IAMDStatisticsGroup::~AMDRadeonX4000_IAMDStatisticsGroup() 0000000000025d4c __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_IAMDStatisticsGroup::~AMDRadeonX4000_IAMDStatisticsGroup() 000000000052cf08 __float128 0f SECT 0a 0000 [__DATA.__common] AMDRadeonX4000_AMDAccelEventMachine::gMetaClass 000000000038b228 __float128 0f SECT 08 0000 [.const_data] AMDRadeonX4000_AMDAccelEventMachine::superClass 0000000000009c4a __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelEventMachine::writeStamp(int, vendevtCommandRec*, unsigned int) 000000000000986e __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelEventMachine::finishEvent(IOAccelEvent*) 000000000000973a __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelEventMachine::finishStamp(int) 0000000000009c8c __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelEventMachine::eventTimeout(int) 00000000000099a0 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelEventMachine::waitForStamp(int, unsigned int, unsigned int*) 0000000000009710 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelEventMachine::getStampOffset(int) 0000000000009c58 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelEventMachine::prepareBarrier(vendevtBarrierRec*) 0000000000009c66 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelEventMachine::completeBarrier(vendevtBarrierRec*) 000000000000974c __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelEventMachine::finishAllStamps() 0000000000009fb2 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelEventMachine::setupWritebackSync(int, unsigned int*) 00000000000097d8 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelEventMachine::finishEventUnlocked(IOAccelEvent*) 0000000000009c72 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelEventMachine::writeBarrierElement(vendevtBarrierRec*, int, unsigned int) 0000000000009904 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelEventMachine::finishEventExcluding(IOAccelEvent*, int) 000000000000a01e __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelEventMachine::isEventEmptyExcluding(IOAccelEvent const*, int) 00000000000096b4 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelEventMachine::free() 0000000000009622 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelEventMachine::init(IOGraphicsAccelerator2*, unsigned int, int) 0000000000009490 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelEventMachine::MetaClass::MetaClass() 0000000000009550 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelEventMachine::MetaClass::MetaClass() 000000000038b220 __float128 0f SECT 08 0000 [.const_data] AMDRadeonX4000_AMDAccelEventMachine::metaClass 00000000000094ec __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelEventMachine::AMDRadeonX4000_AMDAccelEventMachine(OSMetaClass const*) 00000000000095c2 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelEventMachine::AMDRadeonX4000_AMDAccelEventMachine() 00000000000094cc __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelEventMachine::AMDRadeonX4000_AMDAccelEventMachine(OSMetaClass const*) 00000000000095f2 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelEventMachine::AMDRadeonX4000_AMDAccelEventMachine() 0000000000009520 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelEventMachine::~AMDRadeonX4000_AMDAccelEventMachine() 0000000000009516 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelEventMachine::~AMDRadeonX4000_AMDAccelEventMachine() 000000000000950c __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelEventMachine::~AMDRadeonX4000_AMDAccelEventMachine() 000000000052d070 __float128 0f SECT 0a 0000 [__DATA.__common] AMDRadeonX4000_AMDAccelVideoContext::gMetaClass 0000000000016fd0 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelVideoContext::setChannel(IOAccelCommandStreamInfo&) 000000000038e658 __float128 0f SECT 08 0000 [.const_data] AMDRadeonX4000_AMDAccelVideoContext::superClass 0000000000019364 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelVideoContext::contextStop() 0000000000019aa8 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelVideoContext::bindResource(IOAccelCommandStreamInfo&, IOAccelResource2*, bool, IOAccelChannel2*, unsigned int) 0000000000017f76 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelVideoContext::contextStart() 00000000000190ca __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelVideoContext::getVCEPSInfo(void*, void*, unsigned long long, unsigned long long*) 0000000000018884 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelVideoContext::submitSPUMsg(sAMDSPUContextMsgIn*, sAMDSPUContextMsgOut*, unsigned long long, unsigned long long*) 000000000001a3fa __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelVideoContext::enableContext() 0000000000019d86 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelVideoContext::fetchResource(_AMDVideoResourceParam*, _AMDVideoResourceInfo*) 00000000000182a8 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelVideoContext::newUVDContext(sUvdContextCreateInfo*, sUvdContextReturnInfo*, unsigned long long, unsigned long long*) 0000000000018d4c __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelVideoContext::newVCEContext(sVceContextCreateInfo*, sVceContextReturnInfo*, unsigned long long, unsigned long long*) 000000000001a294 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelVideoContext::sendPMCommand(void*, void*, unsigned long long, unsigned long long*) 000000000001a49c __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelVideoContext::disableContext() 0000000000019b50 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelVideoContext::processCommand(IOAccelCommandStreamInfo&, unsigned int*) 000000000001914c __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelVideoContext::setEncCropping(cropping_info*, unsigned long long) 000000000001852a __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelVideoContext::startUVDEngine(unsigned int) 0000000000018fd8 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelVideoContext::startVCEEngine() 0000000000019abe __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelVideoContext::unbindResource(IOAccelCommandStreamInfo&, IOAccelResource2*, IOAccelChannel2*) 000000000001a62c __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelVideoContext::find_uvd_for_id(unsigned int) 0000000000019f30 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelVideoContext::find_vce_for_id(unsigned int) 000000000001a302 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelVideoContext::notifyPMContext(unsigned int, unsigned int, unsigned int) 00000000000186be __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelVideoContext::createSPUSession() 00000000000197d8 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelVideoContext::endCommandStream(IOAccelCommandStreamInfo&) 000000000001a21c __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelVideoContext::getUVDCapability(sAMDUVDCapability*, unsigned long long*) 000000000001a258 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelVideoContext::getVCECapability(sAMDVCECapability*, unsigned long long*) 00000000000183c0 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelVideoContext::removeUVDContext(unsigned int) 0000000000018e88 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelVideoContext::removeVCEContext(unsigned int) 0000000000019190 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelVideoContext::setEncProperties(encode_properties_info*, unsigned long long) 00000000000187a4 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelVideoContext::destroySPUSession() 000000000001702c __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelVideoContext::processUVDCommand(IOAccelCommandStreamInfo&) 0000000000017130 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelVideoContext::processVCECommand(IOAccelCommandStreamInfo&) 0000000000019756 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelVideoContext::beginCommandStream(IOAccelCommandStreamInfo&) 000000000001a524 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelVideoContext::clientMemoryForType(unsigned int, unsigned int*, IOMemoryDescriptor**) 00000000000196a8 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelVideoContext::getDataBufferLimits() 000000000001a204 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelVideoContext::getIOSurfaceAccelId(sIOSurfaceAccelIdInfo*) 0000000000018690 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelVideoContext::getUVDBandwidthLimit(sAMDUVDBandwidthLimit*) 00000000000199d8 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelVideoContext::processSidebandToken(IOAccelCommandStreamInfo&) 000000000001863a __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelVideoContext::setUVDBandwidthLimit(sAMDUVDBandwidthLimit*, unsigned long long) 0000000000019638 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelVideoContext::populateContextConfig(IOAccelContextConfig*) 000000000001a3c4 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelVideoContext::setSuspendResumeState(bool) 000000000038e610 __float128 0f SECT 08 0000 [.const_data] AMDRadeonX4000_AMDAccelVideoContext::token_process_methods 0000000000019ad0 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelVideoContext::addDataBufferToChannel(IOAccelResource2*, unsigned int) 0000000000017598 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelVideoContext::processGraphicsCommand(IOAccelCommandStreamInfo&) 0000000000018246 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelVideoContext::setMaxPerformanceLevel(unsigned int) 00000000000185dc __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelVideoContext::setHighPerformanceDecode(unsigned int) 000000000001965c __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelVideoContext::getTargetAndMethodForIndex(IOService**, unsigned int) 0000000000019b16 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelVideoContext::removeDataBufferFromChannel(IOAccelResource2*, unsigned int) 00000000000191c0 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelVideoContext::startTPT(sDTCParametersIn*, sDTCParametersOut*, unsigned long long, unsigned long long*) 0000000000017e7c __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelVideoContext::MetaClass::MetaClass() 0000000000017f3c __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelVideoContext::MetaClass::MetaClass() 0000000000019f5a __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelVideoContext::getHWInfo(sHardwareInfo*) 000000000038e650 __float128 0f SECT 08 0000 [.const_data] AMDRadeonX4000_AMDAccelVideoContext::metaClass 000000000001a130 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelVideoContext::setClocks(set_clock_info*, unsigned long long) 0000000000017ed8 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelVideoContext::AMDRadeonX4000_AMDAccelVideoContext(OSMetaClass const*) 0000000000017eb8 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelVideoContext::AMDRadeonX4000_AMDAccelVideoContext(OSMetaClass const*) 0000000000017f0c __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelVideoContext::~AMDRadeonX4000_AMDAccelVideoContext() 0000000000017f02 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelVideoContext::~AMDRadeonX4000_AMDAccelVideoContext() 0000000000017ef8 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelVideoContext::~AMDRadeonX4000_AMDAccelVideoContext() 0000000000022732 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAtomicBlitManager::doCompress(_UBM_COMPRESSINFO*, ABM_OPTIONS const*) 000000000052d1b0 __float128 0f SECT 0a 0000 [__DATA.__common] AMDRadeonX4000_AMDAtomicBlitManager::gMetaClass 0000000000390830 __float128 0f SECT 08 0000 [.const_data] AMDRadeonX4000_AMDAtomicBlitManager::superClass 0000000000021ffa __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAtomicBlitManager::doAAResolve(_UBM_AARESOLVEINFO*, ABM_OPTIONS const*) 0000000000022f12 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAtomicBlitManager::SubmitBuffer(AMDRadeonX4000_AMDAtomicBlitManager::CommandBufferInfo&, ABM_OPTIONS const*) 0000000000022c1a __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAtomicBlitManager::doSurfaceCopy(_UBM_SURFACECOPYINFO*, ABM_OPTIONS const*) 0000000000021c9a __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAtomicBlitManager::preBlitUpdate(ABM_OPTIONS const*, AMDRadeonX4000_AMDAccelChannel*) 0000000000021d6a __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAtomicBlitManager::postBlitUpdate(ABM_OPTIONS const*, AMDRadeonX4000_AMDAccelChannel*) 0000000000022db2 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAtomicBlitManager::GetCommandBuffer(AMDRadeonX4000_AMDAtomicBlitManager::CommandBufferInfo&, _UBM_ENGINE, ABM_OPTIONS const*) 0000000000022172 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAtomicBlitManager::doWaitForVLineAndStretch(_UBM_STRETCHINFO*, ABM_OPTIONS const*, AMDRadeonX4000_AMDAccelSurface const*, _AMDSurfaceSwapSyncOptions const&) 0000000000021c4c __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAtomicBlitManager::free() 0000000000021b44 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAtomicBlitManager::init(AMDRadeonX4000_AMDGraphicsAccelerator*) 0000000000021e82 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAtomicBlitManager::doClear(_UBM_CLEARINFO*, ABM_OPTIONS const*) 00000000000225ba __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAtomicBlitManager::doExpand(_UBM_EXPANDINFO*, ABM_OPTIONS const*) 0000000000022a40 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAtomicBlitManager::doMemcpy(_UBM_MEMCPYINFO*, ABM_OPTIONS const*) 00000000000228aa __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAtomicBlitManager::doMemset(_UBM_MEMSETINFO*, ABM_OPTIONS const*) 0000000000021a6a __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAtomicBlitManager::MetaClass::MetaClass() 0000000000021b0a __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAtomicBlitManager::MetaClass::MetaClass() 000000000002231e __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAtomicBlitManager::doStretch(_UBM_STRETCHINFO*, ABM_OPTIONS const*) 0000000000390828 __float128 0f SECT 08 0000 [.const_data] AMDRadeonX4000_AMDAtomicBlitManager::metaClass 0000000000021aa6 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAtomicBlitManager::AMDRadeonX4000_AMDAtomicBlitManager(OSMetaClass const*) 0000000000021ada __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAtomicBlitManager::~AMDRadeonX4000_AMDAtomicBlitManager() 0000000000021ad0 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAtomicBlitManager::~AMDRadeonX4000_AMDAtomicBlitManager() 0000000000021ac6 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAtomicBlitManager::~AMDRadeonX4000_AMDAtomicBlitManager() 000000000052de00 __float128 0f SECT 0a 0000 [__DATA.__common] AMDRadeonX4000_AMDHWSemaphoreMemMgr::gMetaClass 00000000003a7728 __float128 0f SECT 08 0000 [.const_data] AMDRadeonX4000_AMDHWSemaphoreMemMgr::superClass 0000000000057c40 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHWSemaphoreMemMgr::getVirtualAddress(unsigned long long) 0000000000057c10 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHWSemaphoreMemMgr::releaseSemaphoreData(unsigned long long) 0000000000057bc4 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHWSemaphoreMemMgr::allocateSemaphoreData(unsigned long long**, unsigned long long*) 0000000000057b30 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHWSemaphoreMemMgr::free() 0000000000057962 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHWSemaphoreMemMgr::init(AMDRadeonX4000_IAMDHWInterface*, unsigned int) 00000000000577d0 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHWSemaphoreMemMgr::MetaClass::MetaClass() 0000000000057890 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHWSemaphoreMemMgr::MetaClass::MetaClass() 00000000003a7720 __float128 0f SECT 08 0000 [.const_data] AMDRadeonX4000_AMDHWSemaphoreMemMgr::metaClass 000000000005782c __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHWSemaphoreMemMgr::AMDRadeonX4000_AMDHWSemaphoreMemMgr(OSMetaClass const*) 0000000000057902 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHWSemaphoreMemMgr::AMDRadeonX4000_AMDHWSemaphoreMemMgr() 000000000005780c __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHWSemaphoreMemMgr::AMDRadeonX4000_AMDHWSemaphoreMemMgr(OSMetaClass const*) 0000000000057932 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHWSemaphoreMemMgr::AMDRadeonX4000_AMDHWSemaphoreMemMgr() 0000000000057860 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHWSemaphoreMemMgr::~AMDRadeonX4000_AMDHWSemaphoreMemMgr() 0000000000057856 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHWSemaphoreMemMgr::~AMDRadeonX4000_AMDHWSemaphoreMemMgr() 000000000005784c __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHWSemaphoreMemMgr::~AMDRadeonX4000_AMDHWSemaphoreMemMgr() 000000000052ef58 __float128 0f SECT 0a 0000 [__DATA.__common] AMDRadeonX4000_AMDHDCPOpenSessionMsg::gMetaClass 00000000003c1da8 __float128 0f SECT 08 0000 [.const_data] AMDRadeonX4000_AMDHDCPOpenSessionMsg::superClass 00000000001262ea __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHDCPOpenSessionMsg::setOutBuffer(int, unsigned long long, unsigned char*) 00000000001262d8 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHDCPOpenSessionMsg::free() 0000000000126212 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHDCPOpenSessionMsg::init(void*) 0000000000126080 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHDCPOpenSessionMsg::MetaClass::MetaClass() 0000000000126140 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHDCPOpenSessionMsg::MetaClass::MetaClass() 000000000012630e __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHDCPOpenSessionMsg::getOutput() 00000000003c1da0 __float128 0f SECT 08 0000 [.const_data] AMDRadeonX4000_AMDHDCPOpenSessionMsg::metaClass 00000000001260dc __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHDCPOpenSessionMsg::AMDRadeonX4000_AMDHDCPOpenSessionMsg(OSMetaClass const*) 00000000001261b2 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHDCPOpenSessionMsg::AMDRadeonX4000_AMDHDCPOpenSessionMsg() 00000000001260bc __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHDCPOpenSessionMsg::AMDRadeonX4000_AMDHDCPOpenSessionMsg(OSMetaClass const*) 00000000001261e2 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHDCPOpenSessionMsg::AMDRadeonX4000_AMDHDCPOpenSessionMsg() 0000000000126110 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHDCPOpenSessionMsg::~AMDRadeonX4000_AMDHDCPOpenSessionMsg() 0000000000126106 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHDCPOpenSessionMsg::~AMDRadeonX4000_AMDHDCPOpenSessionMsg() 00000000001260fc __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHDCPOpenSessionMsg::~AMDRadeonX4000_AMDHDCPOpenSessionMsg() 000000000052dec8 __float128 0f SECT 0a 0000 [__DATA.__common] AMDRadeonX4000_AMDPM4CommandsUtility::gMetaClass 00000000003a88f8 __float128 0f SECT 08 0000 [.const_data] AMDRadeonX4000_AMDPM4CommandsUtility::superClass 000000000005e166 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDPM4CommandsUtility::buildPM4Type0Cmd(unsigned int*, unsigned int, unsigned int) 000000000005e3a8 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDPM4CommandsUtility::buildSetDataCommand(unsigned int*, unsigned int, unsigned int, unsigned int, unsigned int, unsigned int) 000000000005e56e __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDPM4CommandsUtility::buildMemWriteCommand(unsigned int*, unsigned long long, unsigned int, unsigned int) 000000000005e502 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDPM4CommandsUtility::buildPerFrameCommand(unsigned int*, unsigned int, unsigned int, unsigned int, unsigned int) 000000000005e762 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDPM4CommandsUtility::buildPFPSyncMECommand(unsigned int*) 000000000005e5dc __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDPM4CommandsUtility::buildWriteDataCommand(unsigned int*, unsigned long long, unsigned int, unsigned int, unsigned int, unsigned int, unsigned int const*, unsigned int, unsigned int) 000000000005e28e __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDPM4CommandsUtility::buildEventWriteCommand(unsigned int*, unsigned int, unsigned int) 000000000005e3d0 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDPM4CommandsUtility::buildWaitRegMemCommand(unsigned int*, unsigned int, unsigned int, unsigned int, unsigned int, unsigned int, unsigned int, unsigned int) 000000000005e176 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDPM4CommandsUtility::writePM4Type0CmdToRing(AMDRadeonX4000_IAMDHWRing*, unsigned int, unsigned int) 000000000005e1aa __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDPM4CommandsUtility::buildSurfaceSyncCommand(unsigned int*, unsigned int, unsigned int) 000000000005e2e2 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDPM4CommandsUtility::buildEventWriteEOPCommand(unsigned int*, unsigned int, unsigned long long, unsigned long long, unsigned int, bool, unsigned int, unsigned int) 000000000005e458 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDPM4CommandsUtility::buildIndirectBufferCommand(unsigned int*, unsigned long long, unsigned int, _eAMD_INDIRECT_BUFFER_TYPE, unsigned int, bool, unsigned int) 000000000005e6a6 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDPM4CommandsUtility::writeWriteDataCommandToRing(AMDRadeonX4000_IAMDHWRing*, unsigned long long, unsigned int, unsigned int, unsigned int, unsigned int, unsigned int const*, unsigned int, unsigned int) 000000000005e218 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDPM4CommandsUtility::writeSurfaceSyncCommandToRing(AMDRadeonX4000_IAMDHWRing*, unsigned int, unsigned int) 000000000005e154 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDPM4CommandsUtility::free() 000000000005e142 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDPM4CommandsUtility::init() 000000000005dfb0 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDPM4CommandsUtility::MetaClass::MetaClass() 000000000005e070 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDPM4CommandsUtility::MetaClass::MetaClass() 00000000003a88f0 __float128 0f SECT 08 0000 [.const_data] AMDRadeonX4000_AMDPM4CommandsUtility::metaClass 000000000005e00c __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDPM4CommandsUtility::AMDRadeonX4000_AMDPM4CommandsUtility(OSMetaClass const*) 000000000005e0e2 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDPM4CommandsUtility::AMDRadeonX4000_AMDPM4CommandsUtility() 000000000005dfec __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDPM4CommandsUtility::AMDRadeonX4000_AMDPM4CommandsUtility(OSMetaClass const*) 000000000005e112 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDPM4CommandsUtility::AMDRadeonX4000_AMDPM4CommandsUtility() 000000000005e040 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDPM4CommandsUtility::~AMDRadeonX4000_AMDPM4CommandsUtility() 000000000005e036 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDPM4CommandsUtility::~AMDRadeonX4000_AMDPM4CommandsUtility() 000000000005e02c __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDPM4CommandsUtility::~AMDRadeonX4000_AMDPM4CommandsUtility() 000000000052d188 __float128 0f SECT 0a 0000 [__DATA.__common] AMDRadeonX4000_IAMDAtomicBlitManager::gMetaClass 00000000003905a8 __float128 0f SECT 08 0000 [.const_data] AMDRadeonX4000_IAMDAtomicBlitManager::superClass 0000000000021990 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_IAMDAtomicBlitManager::MetaClass::MetaClass() 0000000000021a30 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_IAMDAtomicBlitManager::MetaClass::MetaClass() 00000000003905a0 __float128 0f SECT 08 0000 [.const_data] AMDRadeonX4000_IAMDAtomicBlitManager::metaClass 00000000000219cc __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_IAMDAtomicBlitManager::AMDRadeonX4000_IAMDAtomicBlitManager(OSMetaClass const*) 0000000000021a00 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_IAMDAtomicBlitManager::~AMDRadeonX4000_IAMDAtomicBlitManager() 00000000000219f6 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_IAMDAtomicBlitManager::~AMDRadeonX4000_IAMDAtomicBlitManager() 00000000000219ec __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_IAMDAtomicBlitManager::~AMDRadeonX4000_IAMDAtomicBlitManager() 000000000052dbf8 __float128 0f SECT 0a 0000 [__DATA.__common] AMDRadeonX4000_IAMDHWSemaphoreMemMgr::gMetaClass 00000000003a52d0 __float128 0f SECT 08 0000 [.const_data] AMDRadeonX4000_IAMDHWSemaphoreMemMgr::superClass 0000000000052de4 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_IAMDHWSemaphoreMemMgr::MetaClass::MetaClass() 0000000000052e84 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_IAMDHWSemaphoreMemMgr::MetaClass::MetaClass() 00000000003a52c8 __float128 0f SECT 08 0000 [.const_data] AMDRadeonX4000_IAMDHWSemaphoreMemMgr::metaClass 0000000000052e20 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_IAMDHWSemaphoreMemMgr::AMDRadeonX4000_IAMDHWSemaphoreMemMgr(OSMetaClass const*) 0000000000052e54 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_IAMDHWSemaphoreMemMgr::~AMDRadeonX4000_IAMDHWSemaphoreMemMgr() 0000000000052e4a __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_IAMDHWSemaphoreMemMgr::~AMDRadeonX4000_IAMDHWSemaphoreMemMgr() 0000000000052e40 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_IAMDHWSemaphoreMemMgr::~AMDRadeonX4000_IAMDHWSemaphoreMemMgr() 000000000052d3b0 __float128 0f SECT 0a 0000 [__DATA.__common] AMDRadeonX4000_IAMDStatisticsManager::gMetaClass 00000000003913c8 __float128 0f SECT 08 0000 [.const_data] AMDRadeonX4000_IAMDStatisticsManager::superClass 00000000000255c0 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_IAMDStatisticsManager::MetaClass::MetaClass() 0000000000025660 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_IAMDStatisticsManager::MetaClass::MetaClass() 00000000003913c0 __float128 0f SECT 08 0000 [.const_data] AMDRadeonX4000_IAMDStatisticsManager::metaClass 00000000000255fc __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_IAMDStatisticsManager::AMDRadeonX4000_IAMDStatisticsManager(OSMetaClass const*) 0000000000025630 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_IAMDStatisticsManager::~AMDRadeonX4000_IAMDStatisticsManager() 0000000000025626 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_IAMDStatisticsManager::~AMDRadeonX4000_IAMDStatisticsManager() 000000000002561c __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_IAMDStatisticsManager::~AMDRadeonX4000_IAMDStatisticsManager() 0000000000005d48 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelDisplayMachine::VblankFunc(OSObject*, IOInterruptEventSource*, int) 000000000052cee0 __float128 0f SECT 0a 0000 [__DATA.__common] AMDRadeonX4000_AMDAccelDisplayMachine::gMetaClass 000000000038a7e8 __float128 0f SECT 08 0000 [.const_data] AMDRadeonX4000_AMDAccelDisplayMachine::superClass 0000000000006304 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelDisplayMachine::FEDSShutdown() 0000000000005f34 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelDisplayMachine::idleVBLQueue(unsigned int) 0000000000008704 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelDisplayMachine::resetScanout(IOAccelEvent*, unsigned int, IOAccelResource2*, IOAccelResource2*) 0000000000008698 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelDisplayMachine::setupScanout(unsigned int, IOAccelResource2*, IOAccelResource2*) 0000000000006fda __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelDisplayMachine::FEDSConfigure() 0000000000008778 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelDisplayMachine::isTripleBuffer(unsigned int) 00000000000083e4 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelDisplayMachine::resetFullScreen(IOAccelEvent*, unsigned int, IOAccelResource2*, IOAccelResource2*) 00000000000080ac __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelDisplayMachine::setupFullScreen(unsigned int, IOAccelResource2*, IOAccelResource2*) 0000000000007124 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelDisplayMachine::reserveNDRVSpace() 000000000000868e __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelDisplayMachine::submitFlipBuffer(IOAccelEvent*, unsigned int, unsigned int, IOAccelResource2*, IOAccelResource2*) 0000000000007252 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelDisplayMachine::reserveFrameBuffer(unsigned int, unsigned long long, unsigned int, IOAccelResource2*) 0000000000009058 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelDisplayMachine::scheduleVblankFlip(unsigned int, IOAccelResource2*, IOAccelResource2*, unsigned int) 00000000000092bc __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelDisplayMachine::getScanoutTransform(unsigned int, IOAccelAffineTransform*) 000000000000708a __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelDisplayMachine::initAffineTransform(unsigned int) 000000000000797a __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelDisplayMachine::initScanoutResource(unsigned int, unsigned int, IOFramebuffer*, IOAccelResource2*) 0000000000006338 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelDisplayMachine::displayModeDidChange() 000000000000850c __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelDisplayMachine::clearFramebufferImage(unsigned int, IOAccelResource2*) 0000000000005f96 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelDisplayMachine::displayModeWillChange() 000000000000800e __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelDisplayMachine::destroyScanoutResource(unsigned int, unsigned int, IOFramebuffer*, IOAccelResource2*) 000000000000932a __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelDisplayMachine::getScanoutInvTransform(unsigned int, IOAccelAffineTransform*) 00000000000091dc __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelDisplayMachine::isBufferReadyForRender(unsigned int, unsigned long long) 00000000000071e4 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelDisplayMachine::VblankInterruptCallback(OSObject*, void*) 0000000000008a1a __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelDisplayMachine::convertFramebufferImage(unsigned int, IOAccelResource2*, bool) 000000000000741c __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelDisplayMachine::initFramebufferResource(unsigned int, unsigned int, IOFramebuffer*, IOAccelResource2*) 0000000000008766 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelDisplayMachine::submitScanoutFlipBuffer(IOAccelEvent*, unsigned int, unsigned int, IOAccelResource2*, IOAccelResource2*) 0000000000008146 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelDisplayMachine::updateFrameBufferOffset(IOAccelEvent*, unsigned int, unsigned int, IOAccelResource2*, IOAccelResource2*) 00000000000091a8 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelDisplayMachine::enableVBLChannelInterrupt() 00000000000069b6 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelDisplayMachine::set_display_mode_and_vram() 00000000000078ae __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelDisplayMachine::destroyFramebufferResource(unsigned int, unsigned int, IOFramebuffer*, IOAccelResource2*) 00000000000091c2 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelDisplayMachine::disableVBLChannelInterrupt() 0000000000008798 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelDisplayMachine::freeNextPreAllocatedTempBuffer(unsigned int) 000000000000628c __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelDisplayMachine::cleanAllPreAllocatedTempBuffers() 00000000000088d8 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelDisplayMachine::allocateNextPreAllocatedTempBuffer(unsigned int) 0000000000008770 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelDisplayMachine::needsSecondaryFramebufferResources() 0000000000005a62 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelDisplayMachine::init(IOGraphicsAccelerator2*) 0000000000005e38 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelDisplayMachine::stop() 0000000000005c56 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelDisplayMachine::FEDSFunc(OSObject*, IOTimerEventSource*) 00000000000058d0 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelDisplayMachine::MetaClass::MetaClass() 0000000000005990 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelDisplayMachine::MetaClass::MetaClass() 000000000038a7e0 __float128 0f SECT 08 0000 [.const_data] AMDRadeonX4000_AMDAccelDisplayMachine::metaClass 0000000000008070 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelDisplayMachine::setStereo(unsigned int, IOAccelStereoMode) 0000000000009398 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelDisplayMachine::signalVBL() 000000000000592c __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelDisplayMachine::AMDRadeonX4000_AMDAccelDisplayMachine(OSMetaClass const*) 0000000000005a02 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelDisplayMachine::AMDRadeonX4000_AMDAccelDisplayMachine() 000000000000590c __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelDisplayMachine::AMDRadeonX4000_AMDAccelDisplayMachine(OSMetaClass const*) 0000000000005a32 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelDisplayMachine::AMDRadeonX4000_AMDAccelDisplayMachine() 0000000000005960 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelDisplayMachine::~AMDRadeonX4000_AMDAccelDisplayMachine() 0000000000005956 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelDisplayMachine::~AMDRadeonX4000_AMDAccelDisplayMachine() 000000000000594c __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelDisplayMachine::~AMDRadeonX4000_AMDAccelDisplayMachine() 000000000052f070 __float128 0f SECT 0a 0000 [__DATA.__common] AMDRadeonX4000_AMDFPReleaseSessionMsg::gMetaClass 00000000003c2f90 __float128 0f SECT 08 0000 [.const_data] AMDRadeonX4000_AMDFPReleaseSessionMsg::superClass 000000000012768a __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDFPReleaseSessionMsg::free() 00000000001275fc __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDFPReleaseSessionMsg::init(void*) 000000000012746a __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDFPReleaseSessionMsg::MetaClass::MetaClass() 000000000012752a __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDFPReleaseSessionMsg::MetaClass::MetaClass() 00000000003c2f88 __float128 0f SECT 08 0000 [.const_data] AMDRadeonX4000_AMDFPReleaseSessionMsg::metaClass 00000000001274c6 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDFPReleaseSessionMsg::AMDRadeonX4000_AMDFPReleaseSessionMsg(OSMetaClass const*) 000000000012759c __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDFPReleaseSessionMsg::AMDRadeonX4000_AMDFPReleaseSessionMsg() 00000000001274a6 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDFPReleaseSessionMsg::AMDRadeonX4000_AMDFPReleaseSessionMsg(OSMetaClass const*) 00000000001275cc __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDFPReleaseSessionMsg::AMDRadeonX4000_AMDFPReleaseSessionMsg() 00000000001274fa __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDFPReleaseSessionMsg::~AMDRadeonX4000_AMDFPReleaseSessionMsg() 00000000001274f0 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDFPReleaseSessionMsg::~AMDRadeonX4000_AMDFPReleaseSessionMsg() 00000000001274e6 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDFPReleaseSessionMsg::~AMDRadeonX4000_AMDFPReleaseSessionMsg() 000000000052ce68 __float128 0f SECT 0a 0000 [__DATA.__common] AMDRadeonX4000_AMDGraphicsAccelerator::gMetaClass 0000000000388dc8 __float128 0f SECT 08 0000 [.const_data] AMDRadeonX4000_AMDGraphicsAccelerator::superClass 0000000000003612 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDGraphicsAccelerator::QSCCallback(OSObject*, void*) 000000000000352e __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDGraphicsAccelerator::setQSCState(void*, unsigned int) 0000000000003e9e __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDGraphicsAccelerator::createBltMgr() 0000000000003f2e __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDGraphicsAccelerator::deleteBltMgr() 0000000000003028 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDGraphicsAccelerator::new2DContext() 00000000000030a4 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDGraphicsAccelerator::newMemoryMap() 0000000000003058 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDGraphicsAccelerator::newSysMemory() 000000000000307e __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDGraphicsAccelerator::newVidMemory() 00000000000021ca __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDGraphicsAccelerator::tmpTotalVRAM() 00000000000030f2 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDGraphicsAccelerator::newStatistics() 000000000000416a __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDGraphicsAccelerator::sendPMCommand(void*) 0000000000003ca4 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDGraphicsAccelerator::setDeviceType(IOPCIDevice*) 0000000000002c68 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDGraphicsAccelerator::systemDidWake() 00000000000030ca __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDGraphicsAccelerator::createResource() 000000000000220a __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDGraphicsAccelerator::getStampMemory(unsigned int*) 00000000000027dc __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDGraphicsAccelerator::initLinkToPeer(char const*) 0000000000001976 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDGraphicsAccelerator::loadSlotNumber() 00000000000029d0 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDGraphicsAccelerator::teardownDevice(IOPCIDevice*) 000000000000245e __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDGraphicsAccelerator::configureDevice(IOPCIDevice*) 0000000000003a72 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDGraphicsAccelerator::createHWHandler() 000000000000223c __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDGraphicsAccelerator::newEventMachine() 0000000000003118 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDGraphicsAccelerator::printSlotNumber() 0000000000002ad8 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDGraphicsAccelerator::systemWillSleep() 0000000000003abc __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDGraphicsAccelerator::createHWInterface(IOPCIDevice*) 0000000000002262 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDGraphicsAccelerator::createUserGPUTask() 0000000000003d48 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDGraphicsAccelerator::getMaxGartEntries() 00000000000028d0 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDGraphicsAccelerator::NDRVGetSurfaceInfo(void*, _AMD_SURFACE_INFO_STRUCT*) 0000000000003b92 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDGraphicsAccelerator::fillGartParameters(_GART_PARAMETERS&) 0000000000003226 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDGraphicsAccelerator::getNumericProperty(char const*) 000000000000325c __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDGraphicsAccelerator::getNumericProperty(char const*, unsigned int*) 00000000000021ec __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDGraphicsAccelerator::totalTextureMemory() 0000000000001a02 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDGraphicsAccelerator::createAccelChannels() 0000000000002a72 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDGraphicsAccelerator::createKernelGPUTask() 0000000000003d7e __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDGraphicsAccelerator::initialize_hardware() 0000000000002fb6 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDGraphicsAccelerator::newSharedUserClient() 0000000000002318 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDGraphicsAccelerator::populateAccelConfig(IOAccelConfig*) 0000000000004382 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDGraphicsAccelerator::callPlatformFunction(OSSymbol const*, bool, void*, void*, void*, void*) 0000000000001b94 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDGraphicsAccelerator::newCommandBufferPool(IOAccelTask*, IOAccelChannel2*) 0000000000002f0e __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDGraphicsAccelerator::systemDidChangeSpeed() 0000000000004200 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDGraphicsAccelerator::writeDiagnosisReport(char*&, unsigned int&) 0000000000003f9c __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDGraphicsAccelerator::enableInterruptHubAgp() 00000000000041b0 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDGraphicsAccelerator::getUVDFirmwareReserve(_SRAMInfo_*) 0000000000001c00 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDGraphicsAccelerator::initCommandBufferPool(IOAccelCommandBufferPool2*, IOAccelTask*, IOAccelChannel2*) 0000000000002e5c __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDGraphicsAccelerator::systemWillChangeSpeed() 00000000000020fc __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDGraphicsAccelerator::disableInterruptHubAgp() 00000000000034c8 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDGraphicsAccelerator::registerForQSCcallback(void (*)(OSObject*, void*), OSObject*, void*, void**) 0000000000003a28 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDGraphicsAccelerator::createStatisticsManager() 0000000000003738 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDGraphicsAccelerator::iofbNotificationHandler(OSObject*, void*, IOFramebuffer*, int, void*) 00000000000036c0 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDGraphicsAccelerator::registerForIOFBCallback() 0000000000002888 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDGraphicsAccelerator::sendRequestToController(_eAMDAccelIOFBRequestType, void*, void*, void*) 0000000000003444 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDGraphicsAccelerator::setVblankInterruptState(unsigned int, void*, unsigned int) 0000000000003792 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDGraphicsAccelerator::allocateGlobalTempBuffer(IOAccelTask*, IOAccelShared2*, eAMDAccGLobalBlitTempBuffer, unsigned int, unsigned int) 000000000000348a __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDGraphicsAccelerator::unregisterVblankInterrupt(unsigned int, void*) 000000000000392a __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDGraphicsAccelerator::deallocateGlobalTempBuffer(eAMDAccGLobalBlitTempBuffer) 00000000000033a4 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDGraphicsAccelerator::registerForVblankInterrupt(unsigned int, void (*)(OSObject*, void*), OSObject*, void*, void**) 000000000000331c __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDGraphicsAccelerator::setTimestampInterruptState(void*, unsigned int) 0000000000003962 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDGraphicsAccelerator::deallocateGlobalTempBuffers() 000000000000399e __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDGraphicsAccelerator::enableHWMemoryCleanupThread(unsigned int) 00000000000039ec __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDGraphicsAccelerator::disableHWMemoryCleanupThread() 0000000000003364 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDGraphicsAccelerator::unregisterTimestampInterrupt(void*) 0000000000003150 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDGraphicsAccelerator::addPlistPropertiesToPCIDevice(char const*) 000000000000244c __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDGraphicsAccelerator::calcMaxGPUPhysicalMemoryBytes(unsigned long long) 00000000000032a8 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDGraphicsAccelerator::registerForTimestampInterrupt(unsigned int, void (*)(OSObject*, void*), OSObject*, void*, void**) 0000000000001b0e __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDGraphicsAccelerator::executeHWMemoryCleanupThreadTimer(OSObject*, IOTimerEventSource*) 0000000000001dea __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDGraphicsAccelerator::stop(IOService*) 00000000000014aa __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDGraphicsAccelerator::start(IOService*) 00000000000013d0 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDGraphicsAccelerator::MetaClass::MetaClass() 0000000000001470 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDGraphicsAccelerator::MetaClass::MetaClass() 0000000000388dc0 __float128 0f SECT 08 0000 [.const_data] AMDRadeonX4000_AMDGraphicsAccelerator::metaClass 0000000000003002 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDGraphicsAccelerator::newDevice() 0000000000002fdc __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDGraphicsAccelerator::newShared() 0000000000003d54 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDGraphicsAccelerator::signalVBL() 000000000000140c __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDGraphicsAccelerator::AMDRadeonX4000_AMDGraphicsAccelerator(OSMetaClass const*) 0000000000001440 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDGraphicsAccelerator::~AMDRadeonX4000_AMDGraphicsAccelerator() 0000000000001436 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDGraphicsAccelerator::~AMDRadeonX4000_AMDGraphicsAccelerator() 000000000000142c __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDGraphicsAccelerator::~AMDRadeonX4000_AMDGraphicsAccelerator() 000000000052ef80 __float128 0f SECT 0a 0000 [__DATA.__common] AMDRadeonX4000_AMDHDCPCloseSessionMsg::gMetaClass 00000000003c2030 __float128 0f SECT 08 0000 [.const_data] AMDRadeonX4000_AMDHDCPCloseSessionMsg::superClass 0000000000126596 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHDCPCloseSessionMsg::free() 0000000000126508 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHDCPCloseSessionMsg::init(void*) 0000000000126376 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHDCPCloseSessionMsg::MetaClass::MetaClass() 0000000000126436 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHDCPCloseSessionMsg::MetaClass::MetaClass() 00000000003c2028 __float128 0f SECT 08 0000 [.const_data] AMDRadeonX4000_AMDHDCPCloseSessionMsg::metaClass 00000000001263d2 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHDCPCloseSessionMsg::AMDRadeonX4000_AMDHDCPCloseSessionMsg(OSMetaClass const*) 00000000001264a8 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHDCPCloseSessionMsg::AMDRadeonX4000_AMDHDCPCloseSessionMsg() 00000000001263b2 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHDCPCloseSessionMsg::AMDRadeonX4000_AMDHDCPCloseSessionMsg(OSMetaClass const*) 00000000001264d8 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHDCPCloseSessionMsg::AMDRadeonX4000_AMDHDCPCloseSessionMsg() 0000000000126406 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHDCPCloseSessionMsg::~AMDRadeonX4000_AMDHDCPCloseSessionMsg() 00000000001263fc __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHDCPCloseSessionMsg::~AMDRadeonX4000_AMDHDCPCloseSessionMsg() 00000000001263f2 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHDCPCloseSessionMsg::~AMDRadeonX4000_AMDHDCPCloseSessionMsg() 000000000052d450 __float128 0f SECT 0a 0000 [__DATA.__common] AMDRadeonX4000_AMDHWChannelStatsGroup::gMetaClass 0000000000391da8 __float128 0f SECT 08 0000 [.const_data] AMDRadeonX4000_AMDHWChannelStatsGroup::superClass 0000000000026480 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHWChannelStatsGroup::dumpGroupStats(OSDictionary*, bool) 000000000002644a __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHWChannelStatsGroup::free() 00000000000263c2 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHWChannelStatsGroup::init(AMDRadeonX4000_AMDHWChannel*, char const*, char const*, unsigned int, char const**, char const**, unsigned int) 0000000000026230 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHWChannelStatsGroup::MetaClass::MetaClass() 00000000000262f0 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHWChannelStatsGroup::MetaClass::MetaClass() 0000000000391da0 __float128 0f SECT 08 0000 [.const_data] AMDRadeonX4000_AMDHWChannelStatsGroup::metaClass 000000000002628c __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHWChannelStatsGroup::AMDRadeonX4000_AMDHWChannelStatsGroup(OSMetaClass const*) 0000000000026362 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHWChannelStatsGroup::AMDRadeonX4000_AMDHWChannelStatsGroup() 000000000002626c __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHWChannelStatsGroup::AMDRadeonX4000_AMDHWChannelStatsGroup(OSMetaClass const*) 0000000000026392 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHWChannelStatsGroup::AMDRadeonX4000_AMDHWChannelStatsGroup() 00000000000262c0 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHWChannelStatsGroup::~AMDRadeonX4000_AMDHWChannelStatsGroup() 00000000000262b6 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHWChannelStatsGroup::~AMDRadeonX4000_AMDHWChannelStatsGroup() 00000000000262ac __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHWChannelStatsGroup::~AMDRadeonX4000_AMDHWChannelStatsGroup() 000000000052dc48 __float128 0f SECT 0a 0000 [__DATA.__common] AMDRadeonX4000_IAMDPM4CommandsUtility::gMetaClass 00000000003a5780 __float128 0f SECT 08 0000 [.const_data] AMDRadeonX4000_IAMDPM4CommandsUtility::superClass 0000000000052f98 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_IAMDPM4CommandsUtility::MetaClass::MetaClass() 0000000000053038 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_IAMDPM4CommandsUtility::MetaClass::MetaClass() 00000000003a5778 __float128 0f SECT 08 0000 [.const_data] AMDRadeonX4000_IAMDPM4CommandsUtility::metaClass 0000000000052fd4 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_IAMDPM4CommandsUtility::AMDRadeonX4000_IAMDPM4CommandsUtility(OSMetaClass const*) 0000000000053008 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_IAMDPM4CommandsUtility::~AMDRadeonX4000_IAMDPM4CommandsUtility() 0000000000052ffe __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_IAMDPM4CommandsUtility::~AMDRadeonX4000_IAMDPM4CommandsUtility() 0000000000052ff4 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_IAMDPM4CommandsUtility::~AMDRadeonX4000_IAMDPM4CommandsUtility() 000000000052d428 __float128 0f SECT 0a 0000 [__DATA.__common] AMDRadeonX4000_AMDAccelStatisticsGroup::gMetaClass 0000000000391b30 __float128 0f SECT 08 0000 [.const_data] AMDRadeonX4000_AMDAccelStatisticsGroup::superClass 0000000000026004 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelStatisticsGroup::dumpGroupStats(OSDictionary*, bool) 000000000002610a __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelStatisticsGroup::resetGroupStats() 0000000000025ff2 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelStatisticsGroup::free() 0000000000025f5c __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelStatisticsGroup::init(OSMetaClass const*, char const*, char const*, unsigned int, char const**, char const**, unsigned int) 0000000000025dca __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelStatisticsGroup::MetaClass::MetaClass() 0000000000025e8a __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelStatisticsGroup::MetaClass::MetaClass() 0000000000391b28 __float128 0f SECT 08 0000 [.const_data] AMDRadeonX4000_AMDAccelStatisticsGroup::metaClass 0000000000025e26 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelStatisticsGroup::AMDRadeonX4000_AMDAccelStatisticsGroup(OSMetaClass const*) 0000000000025efc __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelStatisticsGroup::AMDRadeonX4000_AMDAccelStatisticsGroup() 0000000000025e06 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelStatisticsGroup::AMDRadeonX4000_AMDAccelStatisticsGroup(OSMetaClass const*) 0000000000025f2c __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelStatisticsGroup::AMDRadeonX4000_AMDAccelStatisticsGroup() 0000000000025e5a __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelStatisticsGroup::~AMDRadeonX4000_AMDAccelStatisticsGroup() 0000000000025e50 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelStatisticsGroup::~AMDRadeonX4000_AMDAccelStatisticsGroup() 0000000000025e46 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelStatisticsGroup::~AMDRadeonX4000_AMDAccelStatisticsGroup() 000000000052d048 __float128 0f SECT 0a 0000 [__DATA.__common] AMDRadeonX4000_AMDInterruptEventSource::gMetaClass 000000000038e2c8 __float128 0f SECT 08 0000 [.const_data] AMDRadeonX4000_AMDInterruptEventSource::superClass 0000000000016f56 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDInterruptEventSource::setDisplayIndex(unsigned int) 0000000000016f32 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDInterruptEventSource::init(OSObject*, void (*)(OSObject*, IOInterruptEventSource*, int), IOService*, int) 0000000000016da0 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDInterruptEventSource::MetaClass::MetaClass() 0000000000016e60 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDInterruptEventSource::MetaClass::MetaClass() 000000000038e2c0 __float128 0f SECT 08 0000 [.const_data] AMDRadeonX4000_AMDInterruptEventSource::metaClass 0000000000016dfc __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDInterruptEventSource::AMDRadeonX4000_AMDInterruptEventSource(OSMetaClass const*) 0000000000016ed2 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDInterruptEventSource::AMDRadeonX4000_AMDInterruptEventSource() 0000000000016ddc __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDInterruptEventSource::AMDRadeonX4000_AMDInterruptEventSource(OSMetaClass const*) 0000000000016f02 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDInterruptEventSource::AMDRadeonX4000_AMDInterruptEventSource() 0000000000016e30 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDInterruptEventSource::~AMDRadeonX4000_AMDInterruptEventSource() 0000000000016e26 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDInterruptEventSource::~AMDRadeonX4000_AMDInterruptEventSource() 0000000000016e1c __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDInterruptEventSource::~AMDRadeonX4000_AMDInterruptEventSource() 000000000052cf80 __float128 0f SECT 0a 0000 [__DATA.__common] AMDRadeonX4000_AMDAccelSharedUserClient::gMetaClass 000000000001226e __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelSharedUserClient::sharedStop() 000000000038bc70 __float128 0f SECT 08 0000 [.const_data] AMDRadeonX4000_AMDAccelSharedUserClient::superClass 0000000000012512 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelSharedUserClient::SurfaceCopy(unsigned int*, unsigned long long) 000000000001225c __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelSharedUserClient::sharedStart() 00000000000122e0 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelSharedUserClient::MSAATextureReadWrite(AMDTextureMSAAPagingPacket*) 00000000000122a4 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelSharedUserClient::getTargetAndMethodForIndex(IOService**, unsigned int) 0000000000012280 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelSharedUserClient::stop(IOService*) 0000000000012292 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelSharedUserClient::start(IOService*) 00000000000120ca __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelSharedUserClient::MetaClass::MetaClass() 000000000001218a __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelSharedUserClient::MetaClass::MetaClass() 000000000038bc68 __float128 0f SECT 08 0000 [.const_data] AMDRadeonX4000_AMDAccelSharedUserClient::metaClass 0000000000012126 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelSharedUserClient::AMDRadeonX4000_AMDAccelSharedUserClient(OSMetaClass const*) 00000000000121fc __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelSharedUserClient::AMDRadeonX4000_AMDAccelSharedUserClient() 0000000000012106 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelSharedUserClient::AMDRadeonX4000_AMDAccelSharedUserClient(OSMetaClass const*) 000000000001222c __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelSharedUserClient::AMDRadeonX4000_AMDAccelSharedUserClient() 000000000001215a __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelSharedUserClient::~AMDRadeonX4000_AMDAccelSharedUserClient() 0000000000012150 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelSharedUserClient::~AMDRadeonX4000_AMDAccelSharedUserClient() 0000000000012146 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelSharedUserClient::~AMDRadeonX4000_AMDAccelSharedUserClient() 000000000052d020 __float128 0f SECT 0a 0000 [__DATA.__common] AMDRadeonX4000_AMDAccelCommandBufferPool::gMetaClass 000000000038e088 __float128 0f SECT 08 0000 [.const_data] AMDRadeonX4000_AMDAccelCommandBufferPool::superClass 0000000000016d24 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelCommandBufferPool::free() 0000000000016d12 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelCommandBufferPool::init(IOGraphicsAccelerator2*, IOAccelChannel2*, IOAccelTask*, int, int, unsigned int, unsigned int, unsigned int, unsigned int) 0000000000016b80 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelCommandBufferPool::MetaClass::MetaClass() 0000000000016c40 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelCommandBufferPool::MetaClass::MetaClass() 000000000038e080 __float128 0f SECT 08 0000 [.const_data] AMDRadeonX4000_AMDAccelCommandBufferPool::metaClass 0000000000016bdc __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelCommandBufferPool::AMDRadeonX4000_AMDAccelCommandBufferPool(OSMetaClass const*) 0000000000016cb2 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelCommandBufferPool::AMDRadeonX4000_AMDAccelCommandBufferPool() 0000000000016bbc __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelCommandBufferPool::AMDRadeonX4000_AMDAccelCommandBufferPool(OSMetaClass const*) 0000000000016ce2 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelCommandBufferPool::AMDRadeonX4000_AMDAccelCommandBufferPool() 0000000000016c10 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelCommandBufferPool::~AMDRadeonX4000_AMDAccelCommandBufferPool() 0000000000016c06 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelCommandBufferPool::~AMDRadeonX4000_AMDAccelCommandBufferPool() 0000000000016bfc __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelCommandBufferPool::~AMDRadeonX4000_AMDAccelCommandBufferPool() 000000000052d3d8 __float128 0f SECT 0a 0000 [__DATA.__common] AMDRadeonX4000_AMDAccelStatisticsManager::gMetaClass 0000000000391640 __float128 0f SECT 08 0000 [.const_data] AMDRadeonX4000_AMDAccelStatisticsManager::superClass 0000000000025a74 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelStatisticsManager::dumpAllStats(OSDictionary*, bool) 000000000002595c __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelStatisticsManager::addStatsGroup(AMDRadeonX4000_AMDAccelStatisticsGroup*) 0000000000025bda __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelStatisticsManager::allocDataPage() 0000000000025b7e __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelStatisticsManager::dumpGroupInfo(AMDStatisticsGroupInfo*, unsigned int) 0000000000025b56 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelStatisticsManager::resetAllStats() 0000000000025a5e __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelStatisticsManager::freeStatsGroup(AMDRadeonX4000_AMDAccelStatisticsGroup*) 0000000000025aba __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelStatisticsManager::dumpStatsByGroupId(OSDictionary*, unsigned int, bool) 00000000000258fe __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelStatisticsManager::validateStatsGroup(char const*) 0000000000025b16 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelStatisticsManager::resetStatsByGroupId(unsigned int) 0000000000025882 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelStatisticsManager::free() 000000000002582c __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelStatisticsManager::init(AMDRadeonX4000_AMDGraphicsAccelerator*) 000000000002569a __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelStatisticsManager::MetaClass::MetaClass() 000000000002575a __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelStatisticsManager::MetaClass::MetaClass() 0000000000391638 __float128 0f SECT 08 0000 [.const_data] AMDRadeonX4000_AMDAccelStatisticsManager::metaClass 00000000000256f6 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelStatisticsManager::AMDRadeonX4000_AMDAccelStatisticsManager(OSMetaClass const*) 00000000000257cc __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelStatisticsManager::AMDRadeonX4000_AMDAccelStatisticsManager() 00000000000256d6 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelStatisticsManager::AMDRadeonX4000_AMDAccelStatisticsManager(OSMetaClass const*) 00000000000257fc __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelStatisticsManager::AMDRadeonX4000_AMDAccelStatisticsManager() 000000000002572a __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelStatisticsManager::~AMDRadeonX4000_AMDAccelStatisticsManager() 0000000000025720 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelStatisticsManager::~AMDRadeonX4000_AMDAccelStatisticsManager() 0000000000025716 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelStatisticsManager::~AMDRadeonX4000_AMDAccelStatisticsManager() 000000000052d900 __float128 0f SECT 0a 0000 [__DATA.__common] AMDRadeonX4000_AMDUVDInterruptEventSource::gMetaClass 00000000003a15a8 __float128 0f SECT 08 0000 [.const_data] AMDRadeonX4000_AMDUVDInterruptEventSource::superClass 000000000004e472 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDUVDInterruptEventSource::init(OSObject*, void (*)(OSObject*, IOInterruptEventSource*, int), IOService*, int) 000000000004e2e0 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDUVDInterruptEventSource::MetaClass::MetaClass() 000000000004e3a0 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDUVDInterruptEventSource::MetaClass::MetaClass() 00000000003a15a0 __float128 0f SECT 08 0000 [.const_data] AMDRadeonX4000_AMDUVDInterruptEventSource::metaClass 000000000004e33c __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDUVDInterruptEventSource::AMDRadeonX4000_AMDUVDInterruptEventSource(OSMetaClass const*) 000000000004e412 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDUVDInterruptEventSource::AMDRadeonX4000_AMDUVDInterruptEventSource() 000000000004e31c __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDUVDInterruptEventSource::AMDRadeonX4000_AMDUVDInterruptEventSource(OSMetaClass const*) 000000000004e442 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDUVDInterruptEventSource::AMDRadeonX4000_AMDUVDInterruptEventSource() 000000000004e370 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDUVDInterruptEventSource::~AMDRadeonX4000_AMDUVDInterruptEventSource() 000000000004e366 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDUVDInterruptEventSource::~AMDRadeonX4000_AMDUVDInterruptEventSource() 000000000004e35c __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDUVDInterruptEventSource::~AMDRadeonX4000_AMDUVDInterruptEventSource() 000000000009fe9a __float128 0f SECT 01 0000 [.text] BltMgr::DegammaSrc(BltInfo const*, unsigned int) 000000000009d95a __float128 0f SECT 01 0000 [.text] BltMgr::AllocVidMem(_UBM_ALLOCVIDMEM_INPUT const*, _UBM_ALLOCVIDMEM_OUTPUT*) 000000000009fb14 __float128 0f SECT 01 0000 [.text] BltMgr::DbgDrawPrim(BltDevice*, _UBMDBG_DRAWPRIMINFO*) 000000000009de26 __float128 0f SECT 01 0000 [.text] BltMgr::GetCmdSpace(void*, unsigned int) 0000000000098d34 __float128 0f SECT 01 0000 [.text] BltMgr::InitBltInfo(BltInfo*, BltDevice*) 000000000009ca3a __float128 0f SECT 01 0000 [.text] BltMgr::MlaaResolve(BltDevice*, _UBM_MLAARESOLVEINFO*) 000000000009f31a __float128 0f SECT 01 0000 [.text] BltMgr::SurfaceCopy(BltDevice*, _UBM_SURFACECOPYINFO*) 000000000009a3aa __float128 0f SECT 01 0000 [.text] BltMgr::YuvToRgbBlt(BltInfo*, LARGE_INTEGER) 0000000000099026 __float128 0f SECT 01 0000 [.text] BltMgr::CreateDevice(_UBM_DEVICEINFO*) 000000000009c16c __float128 0f SECT 01 0000 [.text] BltMgr::GenZRangeMip(BltDevice*, _UBM_GENZRANGEMIPINFO*) 000000000009bc68 __float128 0f SECT 01 0000 [.text] BltMgr::GenZRangeTex(BltDevice*, _UBM_GENZRANGETEXINFO*) 000000000009dc9c __float128 0f SECT 01 0000 [.text] BltMgr::AddWideHandle(void*, void*, unsigned int, _VCOP_RESOURCE_TYPE, unsigned int, unsigned int, unsigned int, _VCOP_RESOURCE_TYPE, unsigned int, _UBM_ADDHANDLE_INPUT_FLAGS) 000000000009de70 __float128 0f SECT 01 0000 [.text] BltMgr::GetCmdBufBase(void*) 000000000009fde6 __float128 0f SECT 01 0000 [.text] BltMgr::IsAdjustedBlt(BltInfo const*) 000000000009f6a8 __float128 0f SECT 01 0000 [.text] BltMgr::PartialUpload(BltDevice*, _UBM_PARTIALUPLOADINFO*) 000000000009f914 __float128 0f SECT 01 0000 [.text] BltMgr::ColorTransform(BltDevice*, _UBM_COLORTRANSFORMINFO*) 0000000000098d16 __float128 0f SECT 01 0000 [.text] BltMgr::GpuLoadShaders(BltDevice*, _UBM_GPULOADSHADERSINFO*) 0000000000098df2 __float128 0f SECT 01 0000 [.text] BltMgr::SetupBltEngine(_UBM_BLT_ENGINE*, _UBM_ENGINE) 00000000000996a6 __float128 0f SECT 01 0000 [.text] BltMgr::YuvPackedClear(BltInfo*) 0000000000099110 __float128 0f SECT 01 0000 [.text] BltMgr::YuvPlanarClear(BltInfo*) 0000000000099904 __float128 0f SECT 01 0000 [.text] BltMgr::SetupYuvSurface(_UBM_FORMAT, LARGE_INTEGER, _UBM_SURFINFO*, unsigned int) 000000000009ab3c __float128 0f SECT 01 0000 [.text] BltMgr::StretchToMemcpy(BltInfo*) 0000000000099060 __float128 0f SECT 01 0000 [.text] BltMgr::CreateAuxSurfMgr() 000000000009ec92 __float128 0f SECT 01 0000 [.text] BltMgr::DesktopComposition(BltDevice*, _UBM_DESKTOPCOMPOSITIONINFO*) 000000000009806a __float128 0f SECT 01 0000 [.text] BltMgr::ExecuteFMaskResolve(BltInfo*) 000000000009d098 __float128 0f SECT 01 0000 [.text] BltMgr::ForcePrePostBltSync(BltInfo*) 000000000009db14 __float128 0f SECT 01 0000 [.text] BltMgr::EnterCriticalSection(void*) 0000000000098222 __float128 0f SECT 01 0000 [.text] BltMgr::ExecuteHybridResolve(BltInfo*) 000000000009db34 __float128 0f SECT 01 0000 [.text] BltMgr::LeaveCriticalSection(void*) 000000000009a474 __float128 0f SECT 01 0000 [.text] BltMgr::YuvPackedToPackedBlt(BltInfo*) 000000000009a634 __float128 0f SECT 01 0000 [.text] BltMgr::YuvPlanarToPackedBlt(BltInfo*, LARGE_INTEGER) 000000000009a790 __float128 0f SECT 01 0000 [.text] BltMgr::YuvPlanarToPlanarBlt(BltInfo*, LARGE_INTEGER, LARGE_INTEGER) 000000000009e29e __float128 0f SECT 01 0000 [.text] BltMgr::AdjustBufferBltFormat(BltInfo*) 0000000000098be6 __float128 0f SECT 01 0000 [.text] BltMgr::InitDefaultSampleLocs(_UBM_CREATEINFO const*) 000000000009fe5a __float128 0f SECT 01 0000 [.text] BltMgr::IsLinearGeneralDstBlt(BltInfo const*) 000000000009fe1a __float128 0f SECT 01 0000 [.text] BltMgr::IsLinearGeneralSrcBlt(BltInfo const*) 000000000009e520 __float128 0f SECT 01 0000 [.text] BltMgr::OptimizeBufferBltRects(BltInfo*, unsigned int) 000000000009a212 __float128 0f SECT 01 0000 [.text] BltMgr::OptimizePrePostBltSync(BltInfo*, unsigned int, unsigned int) 0000000000098e9e __float128 0f SECT 01 0000 [.text] BltMgr::SetupInterpolationRect(InterpolationDesc*) 0000000000098e3c __float128 0f SECT 01 0000 [.text] BltMgr::SetupRotMirrorTransform(unsigned int*, _UBM_ROTATION_CW, unsigned int, unsigned int) 000000000009a378 __float128 0f SECT 01 0000 [.text] BltMgr::ComputeNumRectsRemaining(BltInfo*) 000000000009743c __float128 0f SECT 01 0000 [.text] BltMgr::ExecuteEdgeDetectResolve(BltInfo*) 000000000009906c __float128 0f SECT 01 0000 [.text] BltMgr::YuvPackMacroPixelClearColor(_UBM_FORMAT, _UBM_VECTOR*) 000000000009c75e __float128 0f SECT 01 0000 [.text] BltMgr::ExecuteCompressedDepthResolve(BltInfo*) 00000000000970da __float128 0f SECT 01 0000 [.text] BltMgr::HwlExecuteEdgeDetectPrePasses(BltInfo*, _UBM_SURFINFO*) 000000000009e900 __float128 0f SECT 01 0000 [.text] BltMgr::SelectAAResolveTentFilterTaps(BltInfo*, unsigned int, float, AAResolveTapDescriptor*, unsigned int) 000000000009ff6c __float128 0f SECT 01 0000 [.text] BltMgr::SetupNonEvenLinearFilterSampleCount(unsigned int) 0000000000098dd0 __float128 0f SECT 01 0000 [.text] BltMgr::SetDefaultSkipPrePostBltSyncSettings(BltInfo*) 00000000000988e8 __float128 0f SECT 01 0000 [.text] BltMgr::Init(BltMgrInitInfo const*) 0000000000098fde __float128 0f SECT 01 0000 [.text] BltMgr::Trim() 0000000000099ac0 __float128 0f SECT 01 0000 [.text] BltMgr::Clear(BltDevice*, _UBM_CLEARINFO*) 0000000000098878 __float128 0f SECT 01 0000 [.text] BltMgr::Create(_UBM_CREATEINFO const*) 000000000009d0a2 __float128 0f SECT 01 0000 [.text] BltMgr::Expand(BltDevice*, _UBM_EXPANDINFO*) 000000000009ac9e __float128 0f SECT 01 0000 [.text] BltMgr::Memcpy(BltDevice*, _UBM_MEMCPYINFO*) 000000000009df2c __float128 0f SECT 01 0000 [.text] BltMgr::Memset(BltDevice*, _UBM_MEMSETINFO*) 0000000000098b5c __float128 0f SECT 01 0000 [.text] BltMgr::Destroy() 000000000009b8b2 __float128 0f SECT 01 0000 [.text] BltMgr::GenMips(BltDevice*, _UBM_GENMIPSINFO*) 000000000009b050 __float128 0f SECT 01 0000 [.text] BltMgr::Stretch(BltDevice*, _UBM_STRETCHINFO*) 000000000009bfa6 __float128 0f SECT 01 0000 [.text] BltMgr::Compress(BltDevice*, _UBM_COMPRESSINFO*) 000000000009d46c __float128 0f SECT 01 0000 [.text] BltMgr::Gradient(BltDevice*, _UBM_GRADIENTINFO*) 000000000009c306 __float128 0f SECT 01 0000 [.text] BltMgr::AAResolve(BltDevice*, _UBM_AARESOLVEINFO*) 000000000009d702 __float128 0f SECT 01 0000 [.text] BltMgr::AATextOut(BltDevice*, _UBM_AATEXTOUTINFO*) 000000000009dc2e __float128 0f SECT 01 0000 [.text] BltMgr::AddHandle(void*, void*, unsigned int, _VCOP_RESOURCE_TYPE, unsigned int, unsigned int, _UBM_ADDHANDLE_INPUT_FLAGS) 0000000000096b08 __float128 0f SECT 01 0000 [.text] BltMgr::GenHisBlt(BltDevice*, _UBM_SURFINFO const*) 0000000000098784 __float128 0f SECT 01 0000 [.text] BltMgr::BltMgr() 0000000000098830 __float128 0f SECT 01 0000 [.text] BltMgr::~BltMgr() 00000000000987fa __float128 0f SECT 01 0000 [.text] BltMgr::~BltMgr() 00000000000987c4 __float128 0f SECT 01 0000 [.text] BltMgr::~BltMgr() 00000000000cdb82 __float128 0f SECT 01 0000 [.text] AddrLib::GetAddrLib(void*) 00000000000d040e __float128 0f SECT 01 0000 [.text] AddrLib::Bits2Number(unsigned int, ...) 00000000001a8b10 __float128 0f SECT 03 0000 [.const] AddrLib::m_modeFlags 00000000000ce62e __float128 0f SECT 01 0000 [.text] AddrLib::IsMacroTiled(_AddrTileMode) 00000000000d03a8 __float128 0f SECT 01 0000 [.text] AddrLib::IsMicroTiled(_AddrTileMode) 00000000000d03f6 __float128 0f SECT 01 0000 [.text] AddrLib::IsPrtTileMode(_AddrTileMode) 00000000000d038e __float128 0f SECT 01 0000 [.text] AddrLib::IsMacro3dTiled(_AddrTileMode) 00000000000ce648 __float128 0f SECT 01 0000 [.text] AddrLib::ComputeFmaskInfo(_ADDR_COMPUTE_FMASK_INFO_INPUT const*, _ADDR_COMPUTE_FMASK_INFO_OUTPUT*) 00000000000cdb4c __float128 0f SECT 01 0000 [.text] AddrLib::SetAddrChipFamily(unsigned int, unsigned int) 00000000000cdb6e __float128 0f SECT 01 0000 [.text] AddrLib::SetMinPitchAlignPixels(unsigned int) 00000000000cdf6a __float128 0f SECT 01 0000 [.text] AddrLib::ComputeSurfaceThickness(_AddrTileMode) 00000000000d03dc __float128 0f SECT 01 0000 [.text] AddrLib::IsPrtNoRotationTileMode(_AddrTileMode) 00000000000cd8e0 __float128 0f SECT 01 0000 [.text] AddrLib::Create(_ADDR_CREATE_INPUT const*, _ADDR_CREATE_OUTPUT*) 00000000000d03c2 __float128 0f SECT 01 0000 [.text] AddrLib::IsLinear(_AddrTileMode) 00000000000cd7f0 __float128 0f SECT 01 0000 [.text] AddrLib::AddrLib(AddrClient const*) 00000000000cd77c __float128 0f SECT 01 0000 [.text] AddrLib::AddrLib() 00000000000cd864 __float128 0f SECT 01 0000 [.text] AddrLib::~AddrLib() 00000000000cd880 __float128 0f SECT 01 0000 [.text] AddrLib::~AddrLib() 00000000000cd8b0 __float128 0f SECT 01 0000 [.text] AddrLib::~AddrLib() 00000000000a7b6c __float128 0f SECT 01 0000 [.text] UbmMath::IsInfOrNaN(float) 00000000000a7d66 __float128 0f SECT 01 0000 [.text] UbmMath::Log2OfPow2(unsigned int) 0000000000146b7c __float128 0f SECT 03 0000 [.const] UbmMath::Float10Desc 0000000000146b44 __float128 0f SECT 03 0000 [.const] UbmMath::Float11Desc 0000000000146b0c __float128 0f SECT 03 0000 [.const] UbmMath::Float16Desc 00000000000a7d88 __float128 0f SECT 01 0000 [.text] UbmMath::ComputeCRC32(void*, unsigned int) 0000000000146b04 __float128 0f SECT 03 0000 [.const] UbmMath::FloatMinusOne 00000000000a78e2 __float128 0f SECT 01 0000 [.text] UbmMath::FloatToSFixed(float, unsigned int, unsigned int, UbmMathRoundMode) 00000000000a77dc __float128 0f SECT 01 0000 [.text] UbmMath::FloatToUFixed(float, unsigned int, unsigned int, UbmMathRoundMode) 00000000000a79f8 __float128 0f SECT 01 0000 [.text] UbmMath::SFixedToFloat(int, unsigned int, unsigned int) 00000000000a7a4e __float128 0f SECT 01 0000 [.text] UbmMath::UFixedToFloat(unsigned int, unsigned int, unsigned int) 00000000000a7ba6 __float128 0f SECT 01 0000 [.text] UbmMath::Float32ToFloatN(float, UbmMath::NBitFloatDesc const*) 00000000000a7c8c __float128 0f SECT 01 0000 [.text] UbmMath::FloatNToFloat32(unsigned int, UbmMath::NBitFloatDesc const*) 00000000000a7ad2 __float128 0f SECT 01 0000 [.text] UbmMath::Pow(float, float) 00000000000a7aea __float128 0f SECT 01 0000 [.text] UbmMath::Pow(float, int) 00000000000a7b36 __float128 0f SECT 01 0000 [.text] UbmMath::Pow2(float) 00000000000a7b52 __float128 0f SECT 01 0000 [.text] UbmMath::IsInf(float) 00000000000a78b6 __float128 0f SECT 01 0000 [.text] UbmMath::IsNaN(float) 00000000000a7aaa __float128 0f SECT 01 0000 [.text] UbmMath::fastExp(float) 0000000000146b00 __float128 0f SECT 03 0000 [.const] UbmMath::FloatOne 0000000000146b08 __float128 0f SECT 03 0000 [.const] UbmMath::FloatZero 00000000000a77ca __float128 0f SECT 01 0000 [.text] UbmMath::UbmMath() 00000000000a77c4 __float128 0f SECT 01 0000 [.text] UbmMath::UbmMath() 00000000000a77d6 __float128 0f SECT 01 0000 [.text] UbmMath::~UbmMath() 00000000000a77d0 __float128 0f SECT 01 0000 [.text] UbmMath::~UbmMath() 000000000052e0a8 __float128 0f SECT 0a 0000 [__DATA.__common] AMDSIVMM::gMetaClass 00000000003ab388 __float128 0f SECT 08 0000 [.const_data] AMDSIVMM::superClass 0000000000066864 __float128 0f SECT 01 0000 [.text] AMDSIVMM::clearWithDMA(unsigned long long, unsigned long long) 000000000006697a __float128 0f SECT 01 0000 [.text] AMDSIVMM::allocateVMContext() 00000000000667ec __float128 0f SECT 01 0000 [.text] AMDSIVMM::programPageTableRegisters(__AMD_VMID_LL_ENTRY*) 0000000000066762 __float128 0f SECT 01 0000 [.text] AMDSIVMM::init(AMDRadeonX4000_IAMDHWInterface*) 00000000000665d0 __float128 0f SECT 01 0000 [.text] AMDSIVMM::MetaClass::MetaClass() 0000000000066690 __float128 0f SECT 01 0000 [.text] AMDSIVMM::MetaClass::MetaClass() 00000000003ab380 __float128 0f SECT 08 0000 [.const_data] AMDSIVMM::metaClass 000000000006662c __float128 0f SECT 01 0000 [.text] AMDSIVMM::AMDSIVMM(OSMetaClass const*) 0000000000066702 __float128 0f SECT 01 0000 [.text] AMDSIVMM::AMDSIVMM() 000000000006660c __float128 0f SECT 01 0000 [.text] AMDSIVMM::AMDSIVMM(OSMetaClass const*) 0000000000066732 __float128 0f SECT 01 0000 [.text] AMDSIVMM::AMDSIVMM() 0000000000066660 __float128 0f SECT 01 0000 [.text] AMDSIVMM::~AMDSIVMM() 0000000000066656 __float128 0f SECT 01 0000 [.text] AMDSIVMM::~AMDSIVMM() 000000000006664c __float128 0f SECT 01 0000 [.text] AMDSIVMM::~AMDSIVMM() 000000000052e9e0 __float128 0f SECT 0a 0000 [__DATA.__common] AMDVIVMM::gMetaClass 00000000003ba218 __float128 0f SECT 08 0000 [.const_data] AMDVIVMM::superClass 0000000000089494 __float128 0f SECT 01 0000 [.text] AMDVIVMM::clearWithDMA(unsigned long long, unsigned long long) 00000000000895aa __float128 0f SECT 01 0000 [.text] AMDVIVMM::allocateVMContext() 000000000008941c __float128 0f SECT 01 0000 [.text] AMDVIVMM::programPageTableRegisters(__AMD_VMID_LL_ENTRY*) 0000000000089392 __float128 0f SECT 01 0000 [.text] AMDVIVMM::init(AMDRadeonX4000_IAMDHWInterface*) 0000000000089200 __float128 0f SECT 01 0000 [.text] AMDVIVMM::MetaClass::MetaClass() 00000000000892c0 __float128 0f SECT 01 0000 [.text] AMDVIVMM::MetaClass::MetaClass() 00000000003ba210 __float128 0f SECT 08 0000 [.const_data] AMDVIVMM::metaClass 000000000008925c __float128 0f SECT 01 0000 [.text] AMDVIVMM::AMDVIVMM(OSMetaClass const*) 0000000000089332 __float128 0f SECT 01 0000 [.text] AMDVIVMM::AMDVIVMM() 000000000008923c __float128 0f SECT 01 0000 [.text] AMDVIVMM::AMDVIVMM(OSMetaClass const*) 0000000000089362 __float128 0f SECT 01 0000 [.text] AMDVIVMM::AMDVIVMM() 0000000000089290 __float128 0f SECT 01 0000 [.text] AMDVIVMM::~AMDVIVMM() 0000000000089286 __float128 0f SECT 01 0000 [.text] AMDVIVMM::~AMDVIVMM() 000000000008927c __float128 0f SECT 01 0000 [.text] AMDVIVMM::~AMDVIVMM() 00000000000b4b22 __float128 0f SECT 01 0000 [.text] SiBltMgr::HwlDestroy() 00000000000b4d92 __float128 0f SECT 01 0000 [.text] SiBltMgr::Execute3dBlt(BltInfo*) 00000000000b48d0 __float128 0f SECT 01 0000 [.text] SiBltMgr::InitSettings() 00000000000b81be __float128 0f SECT 01 0000 [.text] SiBltMgr::SetupMlaaBlt(BltInfo const*) 00000000000b73ee __float128 0f SECT 01 0000 [.text] SiBltMgr::Init3dDrawBlt(BltInfo*) 00000000000b541e __float128 0f SECT 01 0000 [.text] SiBltMgr::AdjustZConvert(BltInfo*) 00000000000b7026 __float128 0f SECT 01 0000 [.text] SiBltMgr::GetZRangeValue(float, unsigned int) 00000000000b6518 __float128 0f SECT 01 0000 [.text] SiBltMgr::HwlInitBltInfo(BltInfo*) 00000000000b500a __float128 0f SECT 01 0000 [.text] SiBltMgr::Adjust3dBltInfo(BltInfo*) 00000000000bae50 __float128 0f SECT 01 0000 [.text] SiBltMgr::ExecuteCpDmaBlt(BltInfo*) 00000000000b4b82 __float128 0f SECT 01 0000 [.text] SiBltMgr::HwlCreateDevice() 00000000000b783c __float128 0f SECT 01 0000 [.text] SiBltMgr::SetupColorClear(BltInfo*) 00000000000b9a90 __float128 0f SECT 01 0000 [.text] SiBltMgr::Execute3dDrawBlt(BltInfo*) 00000000000ba136 __float128 0f SECT 01 0000 [.text] SiBltMgr::ExecuteCbResolve(BltInfo*) 00000000000cbb02 __float128 0f SECT 01 0000 [.text] SiBltMgr::ExecuteDrmDmaBlt(BltInfo*) 00000000000b8576 __float128 0f SECT 01 0000 [.text] SiBltMgr::SetupAdvAAEdGBlt(BltInfo*) 00000000000b7e08 __float128 0f SECT 01 0000 [.text] SiBltMgr::SetupDbgDrawPrim(BltInfo*) 00000000000b7e5e __float128 0f SECT 01 0000 [.text] SiBltMgr::SetupYuvToRgbCsc(BltInfo const*) 00000000000bb3a6 __float128 0f SECT 01 0000 [.text] SiBltMgr::ValidateCpDmaBlt(BltInfo*) 00000000000b4b60 __float128 0f SECT 01 0000 [.text] SiBltMgr::HwlGpuLoadShaders(BltDevice*) 00000000000b6574 __float128 0f SECT 01 0000 [.text] SiBltMgr::Init3dDispatchBlt(BltInfo*) 00000000000b7910 __float128 0f SECT 01 0000 [.text] SiBltMgr::SetupAATextOutBlt(BltInfo const*) 00000000000b8338 __float128 0f SECT 01 0000 [.text] SiBltMgr::SetupAdvAAGradBlt(BltInfo*) 00000000000b823c __float128 0f SECT 01 0000 [.text] SiBltMgr::SetupAdvAARes1Blt(BltInfo*) 00000000000b8210 __float128 0f SECT 01 0000 [.text] SiBltMgr::SetupGenZRangeBlt(BltInfo const*) 00000000000b9a68 __float128 0f SECT 01 0000 [.text] SiBltMgr::SetupVertexBuffer(BltInfo const*, unsigned int, unsigned int) 00000000000b9d64 __float128 0f SECT 01 0000 [.text] SiBltMgr::Validate3dDrawBlt(BltInfo const*) 00000000000cbbf0 __float128 0f SECT 01 0000 [.text] SiBltMgr::ValidateDrmDmaBlt(BltInfo*) 00000000000baa42 __float128 0f SECT 01 0000 [.text] SiBltMgr::SetupDitherTexture(BltInfo const*) 00000000000b9962 __float128 0f SECT 01 0000 [.text] SiBltMgr::ComputeNumDrawPrims(BltInfo const*, unsigned int) 00000000000b4b8c __float128 0f SECT 01 0000 [.text] SiBltMgr::HwlCreateAuxSurfMgr() 00000000000b8106 __float128 0f SECT 01 0000 [.text] SiBltMgr::SetupColorTransform(BltInfo const*) 00000000000b6a68 __float128 0f SECT 01 0000 [.text] SiBltMgr::SetupDispatchConsts(BltInfo*) 00000000000b65c6 __float128 0f SECT 01 0000 [.text] SiBltMgr::Execute3dDispatchBlt(BltInfo*) 00000000000b5b6c __float128 0f SECT 01 0000 [.text] SiBltMgr::GetDccFastClearColor(BltInfo const*) 00000000000b5c84 __float128 0f SECT 01 0000 [.text] SiBltMgr::HwlTileModeReplaceOp(BltInfo*) 00000000000b7f98 __float128 0f SECT 01 0000 [.text] SiBltMgr::SetupYuvToYuvPackBlt(BltInfo const*) 00000000000b6fd6 __float128 0f SECT 01 0000 [.text] SiBltMgr::ShouldUseCsRepackBlt(_UBM_FORMAT, _UBM_FORMAT*) 00000000000b4ea4 __float128 0f SECT 01 0000 [.text] SiBltMgr::AdjustClearColorValue(BltInfo*) 00000000000cbef8 __float128 0f SECT 01 0000 [.text] SiBltMgr::ExecuteDrmDmaClearBlt(BltInfo*) 00000000000b547a __float128 0f SECT 01 0000 [.text] SiBltMgr::ExecuteFastColorClear(BltInfo*) 00000000000b4c16 __float128 0f SECT 01 0000 [.text] SiBltMgr::ExecuteZConvertExpand(BltInfo*) 00000000000b5d94 __float128 0f SECT 01 0000 [.text] SiBltMgr::OverrideDepthSurfInfo(BltDevice*, _UBM_SURFINFO*) 00000000000b5dfe __float128 0f SECT 01 0000 [.text] SiBltMgr::OverrideTileModeTable(BltDevice*, unsigned int) 00000000000b82a8 __float128 0f SECT 01 0000 [.text] SiBltMgr::SetupAdvAAEdgeMaskBlt(BltInfo*) 00000000000b70ec __float128 0f SECT 01 0000 [.text] SiBltMgr::SetupCsRepackBltConst(BltInfo const*) 00000000000b79a2 __float128 0f SECT 01 0000 [.text] SiBltMgr::SetupDrawBltTypeState(BltInfo*) 00000000000b9080 __float128 0f SECT 01 0000 [.text] SiBltMgr::SetupRectPosConstants(BltInfo const*) 00000000000b676a __float128 0f SECT 01 0000 [.text] SiBltMgr::Validate3dDispatchBlt(BltInfo const*) 00000000000ba40c __float128 0f SECT 01 0000 [.text] SiBltMgr::ValidateDepthSurfInfo(_UBM_SURFINFO const*, unsigned int) 00000000000cc568 __float128 0f SECT 01 0000 [.text] SiBltMgr::ExecuteDrmDmaTiledCopy(BltInfo*) 00000000000b5ef4 __float128 0f SECT 01 0000 [.text] SiBltMgr::HwlCreateHtileSurfInfo(_UBM_SURFINFO*, _UBM_SURFINFO*) 00000000000b653a __float128 0f SECT 01 0000 [.text] SiBltMgr::HwlGetShadowMemorySize() 00000000000b73a8 __float128 0f SECT 01 0000 [.text] SiBltMgr::SetupAndWriteClipRects(BltInfo const*, unsigned int) 00000000000b788e __float128 0f SECT 01 0000 [.text] SiBltMgr::SetupDepthStencilClear(BltInfo*) 00000000000bac0c __float128 0f SECT 01 0000 [.text] SiBltMgr::SetupDitherTextureData(_UBM_SURFINFO const*) 00000000000ba6ea __float128 0f SECT 01 0000 [.text] SiBltMgr::SetupVertexBufferRects(BltInfo const*, unsigned int, unsigned int) 00000000000ba46c __float128 0f SECT 01 0000 [.text] SiBltMgr::SetupVertexBufferVerts(BltInfo const*) 00000000000b5b9e __float128 0f SECT 01 0000 [.text] SiBltMgr::ValidateFastColorClear(BltInfo const*) 00000000000cc962 __float128 0f SECT 01 0000 [.text] SiBltMgr::ExecuteDrmDmaLinearCopy(BltInfo*) 00000000000ba8c0 __float128 0f SECT 01 0000 [.text] SiBltMgr::HwlGetDefaultSampleLocs(unsigned int) 00000000000b5e60 __float128 0f SECT 01 0000 [.text] SiBltMgr::OverrideStencilSurfInfo(BltDevice*, _UBM_SURFINFO*) 00000000000b8304 __float128 0f SECT 01 0000 [.text] SiBltMgr::SetupAdvAAFilterMaskBlt(BltInfo*) 00000000000ccdc4 __float128 0f SECT 01 0000 [.text] SiBltMgr::ValidateDrmDmaTiledCopy(BltInfo*) 00000000000b7692 __float128 0f SECT 01 0000 [.text] SiBltMgr::ComputeDrawEntriesNeeded(BltInfo const*) 00000000000b8f64 __float128 0f SECT 01 0000 [.text] SiBltMgr::SetupAndWriteDitherState(BltInfo const*) 00000000000b7cb0 __float128 0f SECT 01 0000 [.text] SiBltMgr::SetupNonEvenLinearFilter(BltInfo const*) 00000000000cccfa __float128 0f SECT 01 0000 [.text] SiBltMgr::ValidateDrmDmaLinearCopy(BltInfo*) 00000000000ba35c __float128 0f SECT 01 0000 [.text] SiBltMgr::ValidateRenderTargetInfo(_UBM_SURFINFO const*) 00000000000b5626 __float128 0f SECT 01 0000 [.text] SiBltMgr::ExecuteFMaskTextureExpand(BltInfo*) 00000000000b89e2 __float128 0f SECT 01 0000 [.text] SiBltMgr::SetupAndWriteDrawBltState(BltInfo*) 00000000000b8b48 __float128 0f SECT 01 0000 [.text] SiBltMgr::SetupAndWriteRasterConfig(BltInfo const*) 00000000000b5a60 __float128 0f SECT 01 0000 [.text] SiBltMgr::CanUseFmaskTextureExpandCs(BltInfo*, _UBM_SURFINFO*) 00000000000cc07a __float128 0f SECT 01 0000 [.text] SiBltMgr::ExecuteDrmDmaSubWindowCopy(BltInfo*) 00000000000b8d68 __float128 0f SECT 01 0000 [.text] SiBltMgr::SetupAndWriteColorKeyState(BltInfo*) 00000000000b86d6 __float128 0f SECT 01 0000 [.text] SiBltMgr::SetupDesktopCompositionBlt(BltInfo*) 00000000000b9592 __float128 0f SECT 01 0000 [.text] SiBltMgr::SetupVertPosColorConstants(BltInfo const*) 00000000000b902a __float128 0f SECT 01 0000 [.text] SiBltMgr::SetupVertexShaderConstants(BltInfo const*) 00000000000b9168 __float128 0f SECT 01 0000 [.text] SiBltMgr::SetupRectPosTexTexConstants(BltInfo const*) 00000000000b65ba __float128 0f SECT 01 0000 [.text] SiBltMgr::ComputeDispatchEntriesNeeded(BltInfo*) 00000000000cc3b2 __float128 0f SECT 01 0000 [.text] SiBltMgr::ExecuteDrmDmaConditionalCopy(BltInfo*) 00000000000b76d6 __float128 0f SECT 01 0000 [.text] SiBltMgr::SetupAndWriteDrawBltSurfInfo(BltInfo*) 00000000000b9402 __float128 0f SECT 01 0000 [.text] SiBltMgr::SetupRectPosTexFastConstants(BltInfo const*) 00000000000b6188 __float128 0f SECT 01 0000 [.text] SiBltMgr::HwlExecuteEdgeDetectPrePasses(BltInfo*, _UBM_SURFINFO*) 00000000000b6110 __float128 0f SECT 01 0000 [.text] SiBltMgr::HwlIsOptimizedYuvBltSupported(_UBM_SURFINFO const*, unsigned int) 00000000000b7630 __float128 0f SECT 01 0000 [.text] SiBltMgr::ComputeVertexBufferDataEntries(BltInfo const*, unsigned int) 00000000000b766e __float128 0f SECT 01 0000 [.text] SiBltMgr::ComputeVertexBufferHeaderEntries(BltInfo const*) 00000000000bacba __float128 0f SECT 01 0000 [.text] SiBltMgr::SetupCompositionSamplingConstants(InterpolationDesc const*, _UBM_ROTATION_CW, unsigned int, unsigned int, _UBM_VECTOR*) 00000000000b6046 __float128 0f SECT 01 0000 [.text] SiBltMgr::HwlIsCompressedDepthResolveSupported(BltInfo*) 00000000000b95e0 __float128 0f SECT 01 0000 [.text] SiBltMgr::SetupRectPosTexTexCompositeConstants(BltInfo const*) 00000000000b7328 __float128 0f SECT 01 0000 [.text] SiBltMgr::Draw(BltInfo*, unsigned int) 00000000000b4b96 __float128 0f SECT 01 0000 [.text] SiBltMgr::HwlBlt(BltInfo*) 00000000000b47fa __float128 0f SECT 01 0000 [.text] SiBltMgr::HwlInit() 00000000000b46d0 __float128 0f SECT 01 0000 [.text] SiBltMgr::CreateObj() 00000000000b9838 __float128 0f SECT 01 0000 [.text] SiBltMgr::DrawRects(BltInfo*, unsigned int) 00000000000b473a __float128 0f SECT 01 0000 [.text] SiBltMgr::SiBltMgr() 00000000000b470c __float128 0f SECT 01 0000 [.text] SiBltMgr::SiBltMgr() 00000000000b47c4 __float128 0f SECT 01 0000 [.text] SiBltMgr::~SiBltMgr() 00000000000b4796 __float128 0f SECT 01 0000 [.text] SiBltMgr::~SiBltMgr() 00000000000b4768 __float128 0f SECT 01 0000 [.text] SiBltMgr::~SiBltMgr() 0000000000098714 __float128 0f SECT 01 0000 [.text] BltDevice::NotifyShadowMemoryInfo(_UBM_STATESHADOWMEMORYINFO*) 0000000000098652 __float128 0f SECT 01 0000 [.text] BltDevice::Init(BltMgr*, _UBM_DEVICEINFO const*) 00000000000986ac __float128 0f SECT 01 0000 [.text] BltDevice::Trim() 00000000000986da __float128 0f SECT 01 0000 [.text] BltDevice::Destroy() 00000000000985e4 __float128 0f SECT 01 0000 [.text] BltDevice::BltDevice() 0000000000098576 __float128 0f SECT 01 0000 [.text] BltDevice::BltDevice() 00000000000a6942 __float128 0f SECT 01 0000 [.text] BltResFmt::HasStencil(_UBM_FORMAT) 00000000000a69de __float128 0f SECT 01 0000 [.text] BltResFmt::IsYuvPlanar(_UBM_FORMAT) 00000000000a6a62 __float128 0f SECT 01 0000 [.text] BltResFmt::GetFMaskFormat(unsigned int, unsigned int) 00000000000a69be __float128 0f SECT 01 0000 [.text] BltResFmt::HasUnusedAlpha(_UBM_FORMAT) 00000000000a69f4 __float128 0f SECT 01 0000 [.text] BltResFmt::IsUvInterleaved(_UBM_FORMAT) 00000000000a601c __float128 0f SECT 01 0000 [.text] BltResFmt::ConvertTo_A8_SINT(_UBM_VECTOR const*, unsigned int, void*, unsigned int) 00000000000a5fb4 __float128 0f SECT 01 0000 [.text] BltResFmt::ConvertTo_A8_UINT(_UBM_VECTOR const*, unsigned int, void*, unsigned int) 00000000000a64d2 __float128 0f SECT 01 0000 [.text] BltResFmt::ConvertTo_I8_SINT(_UBM_VECTOR const*, unsigned int, void*, unsigned int) 00000000000a6474 __float128 0f SECT 01 0000 [.text] BltResFmt::ConvertTo_I8_UINT(_UBM_VECTOR const*, unsigned int, void*, unsigned int) 00000000000a6292 __float128 0f SECT 01 0000 [.text] BltResFmt::ConvertTo_L8_SINT(_UBM_VECTOR const*, unsigned int, void*, unsigned int) 00000000000a6228 __float128 0f SECT 01 0000 [.text] BltResFmt::ConvertTo_L8_UINT(_UBM_VECTOR const*, unsigned int, void*, unsigned int) 00000000000a5368 __float128 0f SECT 01 0000 [.text] BltResFmt::ConvertTo_R8_SINT(_UBM_VECTOR const*, unsigned int, void*, unsigned int) 00000000000a5282 __float128 0f SECT 01 0000 [.text] BltResFmt::ConvertTo_R8_UINT(_UBM_VECTOR const*, unsigned int, void*, unsigned int) 00000000000a6a3c __float128 0f SECT 01 0000 [.text] BltResFmt::YuvMacroPixelSize(_UBM_FORMAT) 00000000000a5f4a __float128 0f SECT 01 0000 [.text] BltResFmt::ConvertTo_A16_SINT(_UBM_VECTOR const*, unsigned int, void*, unsigned int) 00000000000a5ee0 __float128 0f SECT 01 0000 [.text] BltResFmt::ConvertTo_A16_UINT(_UBM_VECTOR const*, unsigned int, void*, unsigned int) 00000000000a5e7a __float128 0f SECT 01 0000 [.text] BltResFmt::ConvertTo_A32_SINT(_UBM_VECTOR const*, unsigned int, void*, unsigned int) 00000000000a5e14 __float128 0f SECT 01 0000 [.text] BltResFmt::ConvertTo_A32_UINT(_UBM_VECTOR const*, unsigned int, void*, unsigned int) 00000000000a53da __float128 0f SECT 01 0000 [.text] BltResFmt::ConvertTo_A8_UNORM(_UBM_VECTOR const*, unsigned int, void*, unsigned int) 00000000000a6416 __float128 0f SECT 01 0000 [.text] BltResFmt::ConvertTo_I16_SINT(_UBM_VECTOR const*, unsigned int, void*, unsigned int) 00000000000a63b8 __float128 0f SECT 01 0000 [.text] BltResFmt::ConvertTo_I16_UINT(_UBM_VECTOR const*, unsigned int, void*, unsigned int) 00000000000a635a __float128 0f SECT 01 0000 [.text] BltResFmt::ConvertTo_I32_SINT(_UBM_VECTOR const*, unsigned int, void*, unsigned int) 00000000000a62fc __float128 0f SECT 01 0000 [.text] BltResFmt::ConvertTo_I32_UINT(_UBM_VECTOR const*, unsigned int, void*, unsigned int) 00000000000a61be __float128 0f SECT 01 0000 [.text] BltResFmt::ConvertTo_L16_SINT(_UBM_VECTOR const*, unsigned int, void*, unsigned int) 00000000000a6154 __float128 0f SECT 01 0000 [.text] BltResFmt::ConvertTo_L16_UINT(_UBM_VECTOR const*, unsigned int, void*, unsigned int) 00000000000a60ec __float128 0f SECT 01 0000 [.text] BltResFmt::ConvertTo_L32_SINT(_UBM_VECTOR const*, unsigned int, void*, unsigned int) 00000000000a6084 __float128 0f SECT 01 0000 [.text] BltResFmt::ConvertTo_L32_UINT(_UBM_VECTOR const*, unsigned int, void*, unsigned int) 00000000000a519c __float128 0f SECT 01 0000 [.text] BltResFmt::ConvertTo_R16_SINT(_UBM_VECTOR const*, unsigned int, void*, unsigned int) 00000000000a50b4 __float128 0f SECT 01 0000 [.text] BltResFmt::ConvertTo_R16_UINT(_UBM_VECTOR const*, unsigned int, void*, unsigned int) 00000000000a5446 __float128 0f SECT 01 0000 [.text] BltResFmt::ConvertTo_R1_UNORM(_UBM_VECTOR const*, unsigned int, void*, unsigned int) 00000000000a4ab0 __float128 0f SECT 01 0000 [.text] BltResFmt::ConvertTo_R32_SINT(_UBM_VECTOR const*, unsigned int, void*, unsigned int) 00000000000a4a3e __float128 0f SECT 01 0000 [.text] BltResFmt::ConvertTo_R32_UINT(_UBM_VECTOR const*, unsigned int, void*, unsigned int) 00000000000a52f4 __float128 0f SECT 01 0000 [.text] BltResFmt::ConvertTo_R8_SNORM(_UBM_VECTOR const*, unsigned int, void*, unsigned int) 00000000000a520e __float128 0f SECT 01 0000 [.text] BltResFmt::ConvertTo_R8_UNORM(_UBM_VECTOR const*, unsigned int, void*, unsigned int) 00000000000a6046 __float128 0f SECT 01 0000 [.text] BltResFmt::ConvertFrom_A8_SINT(void const*, unsigned int, _UBM_VECTOR*) 00000000000a5fde __float128 0f SECT 01 0000 [.text] BltResFmt::ConvertFrom_A8_UINT(void const*, unsigned int, _UBM_VECTOR*) 00000000000a64fe __float128 0f SECT 01 0000 [.text] BltResFmt::ConvertFrom_I8_SINT(void const*, unsigned int, _UBM_VECTOR*) 00000000000a64a0 __float128 0f SECT 01 0000 [.text] BltResFmt::ConvertFrom_I8_UINT(void const*, unsigned int, _UBM_VECTOR*) 00000000000a62be __float128 0f SECT 01 0000 [.text] BltResFmt::ConvertFrom_L8_SINT(void const*, unsigned int, _UBM_VECTOR*) 00000000000a6254 __float128 0f SECT 01 0000 [.text] BltResFmt::ConvertFrom_L8_UINT(void const*, unsigned int, _UBM_VECTOR*) 00000000000a5392 __float128 0f SECT 01 0000 [.text] BltResFmt::ConvertFrom_R8_SINT(void const*, unsigned int, _UBM_VECTOR*) 00000000000a52ac __float128 0f SECT 01 0000 [.text] BltResFmt::ConvertFrom_R8_UINT(void const*, unsigned int, _UBM_VECTOR*) 00000000000a6846 __float128 0f SECT 01 0000 [.text] BltResFmt::ConvertTo_L8A8_SINT(_UBM_VECTOR const*, unsigned int, void*, unsigned int) 00000000000a67a8 __float128 0f SECT 01 0000 [.text] BltResFmt::ConvertTo_L8A8_UINT(_UBM_VECTOR const*, unsigned int, void*, unsigned int) 00000000000a4fce __float128 0f SECT 01 0000 [.text] BltResFmt::ConvertTo_R16_FLOAT(_UBM_VECTOR const*, unsigned int, void*, unsigned int) 00000000000a5126 __float128 0f SECT 01 0000 [.text] BltResFmt::ConvertTo_R16_SNORM(_UBM_VECTOR const*, unsigned int, void*, unsigned int) 00000000000a503e __float128 0f SECT 01 0000 [.text] BltResFmt::ConvertTo_R16_UNORM(_UBM_VECTOR const*, unsigned int, void*, unsigned int) 00000000000a49f6 __float128 0f SECT 01 0000 [.text] BltResFmt::ConvertTo_R32_FLOAT(_UBM_VECTOR const*, unsigned int, void*, unsigned int) 00000000000a4f1c __float128 0f SECT 01 0000 [.text] BltResFmt::ConvertTo_R8G8_SINT(_UBM_VECTOR const*, unsigned int, void*, unsigned int) 00000000000a4db2 __float128 0f SECT 01 0000 [.text] BltResFmt::ConvertTo_R8G8_UINT(_UBM_VECTOR const*, unsigned int, void*, unsigned int) 00000000000a5f76 __float128 0f SECT 01 0000 [.text] BltResFmt::ConvertFrom_A16_SINT(void const*, unsigned int, _UBM_VECTOR*) 00000000000a5f0c __float128 0f SECT 01 0000 [.text] BltResFmt::ConvertFrom_A16_UINT(void const*, unsigned int, _UBM_VECTOR*) 00000000000a5ea4 __float128 0f SECT 01 0000 [.text] BltResFmt::ConvertFrom_A32_SINT(void const*, unsigned int, _UBM_VECTOR*) 00000000000a5e3e __float128 0f SECT 01 0000 [.text] BltResFmt::ConvertFrom_A32_UINT(void const*, unsigned int, _UBM_VECTOR*) 00000000000a5408 __float128 0f SECT 01 0000 [.text] BltResFmt::ConvertFrom_A8_UNORM(void const*, unsigned int, _UBM_VECTOR*) 00000000000a6442 __float128 0f SECT 01 0000 [.text] BltResFmt::ConvertFrom_I16_SINT(void const*, unsigned int, _UBM_VECTOR*) 00000000000a63e4 __float128 0f SECT 01 0000 [.text] BltResFmt::ConvertFrom_I16_UINT(void const*, unsigned int, _UBM_VECTOR*) 00000000000a6386 __float128 0f SECT 01 0000 [.text] BltResFmt::ConvertFrom_I32_SINT(void const*, unsigned int, _UBM_VECTOR*) 00000000000a6328 __float128 0f SECT 01 0000 [.text] BltResFmt::ConvertFrom_I32_UINT(void const*, unsigned int, _UBM_VECTOR*) 00000000000a61ea __float128 0f SECT 01 0000 [.text] BltResFmt::ConvertFrom_L16_SINT(void const*, unsigned int, _UBM_VECTOR*) 00000000000a6180 __float128 0f SECT 01 0000 [.text] BltResFmt::ConvertFrom_L16_UINT(void const*, unsigned int, _UBM_VECTOR*) 00000000000a6118 __float128 0f SECT 01 0000 [.text] BltResFmt::ConvertFrom_L32_SINT(void const*, unsigned int, _UBM_VECTOR*) 00000000000a60b0 __float128 0f SECT 01 0000 [.text] BltResFmt::ConvertFrom_L32_UINT(void const*, unsigned int, _UBM_VECTOR*) 00000000000a5db2 __float128 0f SECT 01 0000 [.text] BltResFmt::ConvertFrom_L8_UNORM(void const*, unsigned int, _UBM_VECTOR*) 00000000000a51c6 __float128 0f SECT 01 0000 [.text] BltResFmt::ConvertFrom_R16_SINT(void const*, unsigned int, _UBM_VECTOR*) 00000000000a50de __float128 0f SECT 01 0000 [.text] BltResFmt::ConvertFrom_R16_UINT(void const*, unsigned int, _UBM_VECTOR*) 00000000000a5482 __float128 0f SECT 01 0000 [.text] BltResFmt::ConvertFrom_R1_UNORM(void const*, unsigned int, _UBM_VECTOR*) 00000000000a4ada __float128 0f SECT 01 0000 [.text] BltResFmt::ConvertFrom_R32_SINT(void const*, unsigned int, _UBM_VECTOR*) 00000000000a4a68 __float128 0f SECT 01 0000 [.text] BltResFmt::ConvertFrom_R32_UINT(void const*, unsigned int, _UBM_VECTOR*) 00000000000a5320 __float128 0f SECT 01 0000 [.text] BltResFmt::ConvertFrom_R8_SNORM(void const*, unsigned int, _UBM_VECTOR*) 00000000000a523a __float128 0f SECT 01 0000 [.text] BltResFmt::ConvertFrom_R8_UNORM(void const*, unsigned int, _UBM_VECTOR*) 00000000000a4e64 __float128 0f SECT 01 0000 [.text] BltResFmt::ConvertTo_R8G8_SNORM(_UBM_VECTOR const*, unsigned int, void*, unsigned int) 00000000000a4cfa __float128 0f SECT 01 0000 [.text] BltResFmt::ConvertTo_R8G8_UNORM(_UBM_VECTOR const*, unsigned int, void*, unsigned int) 00000000000a689e __float128 0f SECT 01 0000 [.text] BltResFmt::ConvertFrom_L8A8_SINT(void const*, unsigned int, _UBM_VECTOR*) 00000000000a6800 __float128 0f SECT 01 0000 [.text] BltResFmt::ConvertFrom_L8A8_UINT(void const*, unsigned int, _UBM_VECTOR*) 00000000000a4ff6 __float128 0f SECT 01 0000 [.text] BltResFmt::ConvertFrom_R16_FLOAT(void const*, unsigned int, _UBM_VECTOR*) 00000000000a5154 __float128 0f SECT 01 0000 [.text] BltResFmt::ConvertFrom_R16_SNORM(void const*, unsigned int, _UBM_VECTOR*) 00000000000a506c __float128 0f SECT 01 0000 [.text] BltResFmt::ConvertFrom_R16_UNORM(void const*, unsigned int, _UBM_VECTOR*) 00000000000a4a0a __float128 0f SECT 01 0000 [.text] BltResFmt::ConvertFrom_R32_FLOAT(void const*, unsigned int, _UBM_VECTOR*) 00000000000a4f72 __float128 0f SECT 01 0000 [.text] BltResFmt::ConvertFrom_R8G8_SINT(void const*, unsigned int, _UBM_VECTOR*) 00000000000a4e08 __float128 0f SECT 01 0000 [.text] BltResFmt::ConvertFrom_R8G8_UINT(void const*, unsigned int, _UBM_VECTOR*) 00000000000a6708 __float128 0f SECT 01 0000 [.text] BltResFmt::ConvertTo_L16A16_SINT(_UBM_VECTOR const*, unsigned int, void*, unsigned int) 00000000000a6668 __float128 0f SECT 01 0000 [.text] BltResFmt::ConvertTo_L16A16_UINT(_UBM_VECTOR const*, unsigned int, void*, unsigned int) 00000000000a65cc __float128 0f SECT 01 0000 [.text] BltResFmt::ConvertTo_L32A32_SINT(_UBM_VECTOR const*, unsigned int, void*, unsigned int) 00000000000a6530 __float128 0f SECT 01 0000 [.text] BltResFmt::ConvertTo_L32A32_UINT(_UBM_VECTOR const*, unsigned int, void*, unsigned int) 00000000000a4942 __float128 0f SECT 01 0000 [.text] BltResFmt::ConvertTo_R16G16_SINT(_UBM_VECTOR const*, unsigned int, void*, unsigned int) 00000000000a47d4 __float128 0f SECT 01 0000 [.text] BltResFmt::ConvertTo_R16G16_UINT(_UBM_VECTOR const*, unsigned int, void*, unsigned int) 00000000000a39ac __float128 0f SECT 01 0000 [.text] BltResFmt::ConvertTo_R32G32_SINT(_UBM_VECTOR const*, unsigned int, void*, unsigned int) 00000000000a38fc __float128 0f SECT 01 0000 [.text] BltResFmt::ConvertTo_R32G32_UINT(_UBM_VECTOR const*, unsigned int, void*, unsigned int) 00000000000a6a16 __float128 0f SECT 01 0000 [.text] BltResFmt::IsYuvMacroPixelFormat(_UBM_FORMAT) 00000000000a4ec0 __float128 0f SECT 01 0000 [.text] BltResFmt::ConvertFrom_R8G8_SNORM(void const*, unsigned int, _UBM_VECTOR*) 00000000000a4d56 __float128 0f SECT 01 0000 [.text] BltResFmt::ConvertFrom_R8G8_UNORM(void const*, unsigned int, _UBM_VECTOR*) 00000000000a5586 __float128 0f SECT 01 0000 [.text] BltResFmt::ConvertTo_B5G6R5_UNORM(_UBM_VECTOR const*, unsigned int, void*, unsigned int) 00000000000a4662 __float128 0f SECT 01 0000 [.text] BltResFmt::ConvertTo_R16G16_FLOAT(_UBM_VECTOR const*, unsigned int, void*, unsigned int) 00000000000a4888 __float128 0f SECT 01 0000 [.text] BltResFmt::ConvertTo_R16G16_SNORM(_UBM_VECTOR const*, unsigned int, void*, unsigned int) 00000000000a471a __float128 0f SECT 01 0000 [.text] BltResFmt::ConvertTo_R16G16_UNORM(_UBM_VECTOR const*, unsigned int, void*, unsigned int) 00000000000a38a2 __float128 0f SECT 01 0000 [.text] BltResFmt::ConvertTo_R32G32_FLOAT(_UBM_VECTOR const*, unsigned int, void*, unsigned int) 00000000000a6762 __float128 0f SECT 01 0000 [.text] BltResFmt::ConvertFrom_L16A16_SINT(void const*, unsigned int, _UBM_VECTOR*) 00000000000a66c2 __float128 0f SECT 01 0000 [.text] BltResFmt::ConvertFrom_L16A16_UINT(void const*, unsigned int, _UBM_VECTOR*) 00000000000a6624 __float128 0f SECT 01 0000 [.text] BltResFmt::ConvertFrom_L32A32_SINT(void const*, unsigned int, _UBM_VECTOR*) 00000000000a6588 __float128 0f SECT 01 0000 [.text] BltResFmt::ConvertFrom_L32A32_UINT(void const*, unsigned int, _UBM_VECTOR*) 00000000000a499a __float128 0f SECT 01 0000 [.text] BltResFmt::ConvertFrom_R16G16_SINT(void const*, unsigned int, _UBM_VECTOR*) 00000000000a482c __float128 0f SECT 01 0000 [.text] BltResFmt::ConvertFrom_R16G16_UINT(void const*, unsigned int, _UBM_VECTOR*) 00000000000a3a02 __float128 0f SECT 01 0000 [.text] BltResFmt::ConvertFrom_R32G32_SINT(void const*, unsigned int, _UBM_VECTOR*) 00000000000a3952 __float128 0f SECT 01 0000 [.text] BltResFmt::ConvertFrom_R32G32_UINT(void const*, unsigned int, _UBM_VECTOR*) 00000000000a456a __float128 0f SECT 01 0000 [.text] BltResFmt::ConvertTo_R8G8B8A8_SINT(_UBM_VECTOR const*, unsigned int, void*, unsigned int) 00000000000a436e __float128 0f SECT 01 0000 [.text] BltResFmt::ConvertTo_R8G8B8A8_UINT(_UBM_VECTOR const*, unsigned int, void*, unsigned int) 00000000000a5644 __float128 0f SECT 01 0000 [.text] BltResFmt::ConvertFrom_B5G6R5_UNORM(void const*, unsigned int, _UBM_VECTOR*) 00000000000a46b6 __float128 0f SECT 01 0000 [.text] BltResFmt::ConvertFrom_R16G16_FLOAT(void const*, unsigned int, _UBM_VECTOR*) 00000000000a48e6 __float128 0f SECT 01 0000 [.text] BltResFmt::ConvertFrom_R16G16_SNORM(void const*, unsigned int, _UBM_VECTOR*) 00000000000a4778 __float128 0f SECT 01 0000 [.text] BltResFmt::ConvertFrom_R16G16_UNORM(void const*, unsigned int, _UBM_VECTOR*) 00000000000a38c4 __float128 0f SECT 01 0000 [.text] BltResFmt::ConvertFrom_R32G32_FLOAT(void const*, unsigned int, _UBM_VECTOR*) 00000000000a5ba6 __float128 0f SECT 01 0000 [.text] BltResFmt::ConvertTo_A8B8G8R8_UNORM(_UBM_VECTOR const*, unsigned int, void*, unsigned int) 00000000000a5a30 __float128 0f SECT 01 0000 [.text] BltResFmt::ConvertTo_B4G4R4A4_UNORM(_UBM_VECTOR const*, unsigned int, void*, unsigned int) 00000000000a56bc __float128 0f SECT 01 0000 [.text] BltResFmt::ConvertTo_B5G5R5A1_UNORM(_UBM_VECTOR const*, unsigned int, void*, unsigned int) 00000000000a592c __float128 0f SECT 01 0000 [.text] BltResFmt::ConvertTo_B8G8R8A8_SNORM(_UBM_VECTOR const*, unsigned int, void*, unsigned int) 00000000000a5828 __float128 0f SECT 01 0000 [.text] BltResFmt::ConvertTo_B8G8R8A8_UNORM(_UBM_VECTOR const*, unsigned int, void*, unsigned int) 00000000000a32d4 __float128 0f SECT 01 0000 [.text] BltResFmt::ConvertTo_R32G32B32_SINT(_UBM_VECTOR const*, unsigned int, void*, unsigned int) 00000000000a3202 __float128 0f SECT 01 0000 [.text] BltResFmt::ConvertTo_R32G32B32_UINT(_UBM_VECTOR const*, unsigned int, void*, unsigned int) 00000000000a4466 __float128 0f SECT 01 0000 [.text] BltResFmt::ConvertTo_R8G8B8A8_SNORM(_UBM_VECTOR const*, unsigned int, void*, unsigned int) 00000000000a426a __float128 0f SECT 01 0000 [.text] BltResFmt::ConvertTo_R8G8B8A8_UNORM(_UBM_VECTOR const*, unsigned int, void*, unsigned int) 00000000000a45fa __float128 0f SECT 01 0000 [.text] BltResFmt::ConvertFrom_R8G8B8A8_SINT(void const*, unsigned int, _UBM_VECTOR*) 00000000000a43fe __float128 0f SECT 01 0000 [.text] BltResFmt::ConvertFrom_R8G8B8A8_UINT(void const*, unsigned int, _UBM_VECTOR*) 00000000000a414e __float128 0f SECT 01 0000 [.text] BltResFmt::ConvertTo_R11G11B10_FLOAT(_UBM_VECTOR const*, unsigned int, void*, unsigned int) 00000000000a319c __float128 0f SECT 01 0000 [.text] BltResFmt::ConvertTo_R32G32B32_FLOAT(_UBM_VECTOR const*, unsigned int, void*, unsigned int) 00000000000a5c42 __float128 0f SECT 01 0000 [.text] BltResFmt::ConvertFrom_A8B8G8R8_UNORM(void const*, unsigned int, _UBM_VECTOR*) 00000000000a5b1e __float128 0f SECT 01 0000 [.text] BltResFmt::ConvertFrom_B4G4R4A4_UNORM(void const*, unsigned int, _UBM_VECTOR*) 00000000000a579c __float128 0f SECT 01 0000 [.text] BltResFmt::ConvertFrom_B5G5R5A1_UNORM(void const*, unsigned int, _UBM_VECTOR*) 00000000000a59c8 __float128 0f SECT 01 0000 [.text] BltResFmt::ConvertFrom_B8G8R8A8_SNORM(void const*, unsigned int, _UBM_VECTOR*) 00000000000a58c4 __float128 0f SECT 01 0000 [.text] BltResFmt::ConvertFrom_B8G8R8A8_UNORM(void const*, unsigned int, _UBM_VECTOR*) 00000000000a3346 __float128 0f SECT 01 0000 [.text] BltResFmt::ConvertFrom_R32G32B32_SINT(void const*, unsigned int, _UBM_VECTOR*) 00000000000a3274 __float128 0f SECT 01 0000 [.text] BltResFmt::ConvertFrom_R32G32B32_UINT(void const*, unsigned int, _UBM_VECTOR*) 00000000000a4502 __float128 0f SECT 01 0000 [.text] BltResFmt::ConvertFrom_R8G8B8A8_SNORM(void const*, unsigned int, _UBM_VECTOR*) 00000000000a4306 __float128 0f SECT 01 0000 [.text] BltResFmt::ConvertFrom_R8G8B8A8_UNORM(void const*, unsigned int, _UBM_VECTOR*) 00000000000a3ca2 __float128 0f SECT 01 0000 [.text] BltResFmt::ConvertTo_R10G10B10A2_UINT(_UBM_VECTOR const*, unsigned int, void*, unsigned int) 00000000000a41f6 __float128 0f SECT 01 0000 [.text] BltResFmt::ConvertFrom_R11G11B10_FLOAT(void const*, unsigned int, _UBM_VECTOR*) 00000000000a31ce __float128 0f SECT 01 0000 [.text] BltResFmt::ConvertFrom_R32G32B32_FLOAT(void const*, unsigned int, _UBM_VECTOR*) 00000000000a4062 __float128 0f SECT 01 0000 [.text] BltResFmt::ConvertTo_A2B10G10R10_UNORM(_UBM_VECTOR const*, unsigned int, void*, unsigned int) 00000000000a3f76 __float128 0f SECT 01 0000 [.text] BltResFmt::ConvertTo_A2R10G10B10_UNORM(_UBM_VECTOR const*, unsigned int, void*, unsigned int) 00000000000a3dfc __float128 0f SECT 01 0000 [.text] BltResFmt::ConvertTo_B10G10R10A2_UNORM(_UBM_VECTOR const*, unsigned int, void*, unsigned int) 00000000000a4ba6 __float128 0f SECT 01 0000 [.text] BltResFmt::ConvertTo_D24_UNORM_S8_UINT(_UBM_VECTOR const*, unsigned int, void*, unsigned int) 00000000000a3b28 __float128 0f SECT 01 0000 [.text] BltResFmt::ConvertTo_R10G10B10A2_UNORM(_UBM_VECTOR const*, unsigned int, void*, unsigned int) 00000000000a37a6 __float128 0f SECT 01 0000 [.text] BltResFmt::ConvertTo_R16G16B16A16_SINT(_UBM_VECTOR const*, unsigned int, void*, unsigned int) 00000000000a35a2 __float128 0f SECT 01 0000 [.text] BltResFmt::ConvertTo_R16G16B16A16_UINT(_UBM_VECTOR const*, unsigned int, void*, unsigned int) 00000000000a30a8 __float128 0f SECT 01 0000 [.text] BltResFmt::ConvertTo_R32G32B32A32_SINT(_UBM_VECTOR const*, unsigned int, void*, unsigned int) 00000000000a2fb4 __float128 0f SECT 01 0000 [.text] BltResFmt::ConvertTo_R32G32B32A32_UINT(_UBM_VECTOR const*, unsigned int, void*, unsigned int) 00000000000a3d80 __float128 0f SECT 01 0000 [.text] BltResFmt::ConvertFrom_R10G10B10A2_UINT(void const*, unsigned int, _UBM_VECTOR*) 00000000000a5caa __float128 0f SECT 01 0000 [.text] BltResFmt::ConvertTo_B16G16R16A16_SNORM(_UBM_VECTOR const*, unsigned int, void*, unsigned int) 00000000000a33a6 __float128 0f SECT 01 0000 [.text] BltResFmt::ConvertTo_R16G16B16A16_FLOAT(_UBM_VECTOR const*, unsigned int, void*, unsigned int) 00000000000a369e __float128 0f SECT 01 0000 [.text] BltResFmt::ConvertTo_R16G16B16A16_SNORM(_UBM_VECTOR const*, unsigned int, void*, unsigned int) 00000000000a349a __float128 0f SECT 01 0000 [.text] BltResFmt::ConvertTo_R16G16B16A16_UNORM(_UBM_VECTOR const*, unsigned int, void*, unsigned int) 00000000000a2f58 __float128 0f SECT 01 0000 [.text] BltResFmt::ConvertTo_R32G32B32A32_FLOAT(_UBM_VECTOR const*, unsigned int, void*, unsigned int) 00000000000a3ee6 __float128 0f SECT 01 0000 [.text] BltResFmt::ConvertFrom_B10G10R10A2_UNORM(void const*, unsigned int, _UBM_VECTOR*) 00000000000a4c1e __float128 0f SECT 01 0000 [.text] BltResFmt::ConvertFrom_D24_UNORM_S8_UINT(void const*, unsigned int, _UBM_VECTOR*) 00000000000a3c12 __float128 0f SECT 01 0000 [.text] BltResFmt::ConvertFrom_R10G10B10A2_UNORM(void const*, unsigned int, _UBM_VECTOR*) 00000000000a383a __float128 0f SECT 01 0000 [.text] BltResFmt::ConvertFrom_R16G16B16A16_SINT(void const*, unsigned int, _UBM_VECTOR*) 00000000000a3636 __float128 0f SECT 01 0000 [.text] BltResFmt::ConvertFrom_R16G16B16A16_UINT(void const*, unsigned int, _UBM_VECTOR*) 00000000000a3138 __float128 0f SECT 01 0000 [.text] BltResFmt::ConvertFrom_R32G32B32A32_SINT(void const*, unsigned int, _UBM_VECTOR*) 00000000000a3044 __float128 0f SECT 01 0000 [.text] BltResFmt::ConvertFrom_R32G32B32A32_UINT(void const*, unsigned int, _UBM_VECTOR*) 00000000000a5d4a __float128 0f SECT 01 0000 [.text] BltResFmt::ConvertFrom_B16G16R16A16_SNORM(void const*, unsigned int, _UBM_VECTOR*) 00000000000a3432 __float128 0f SECT 01 0000 [.text] BltResFmt::ConvertFrom_R16G16B16A16_FLOAT(void const*, unsigned int, _UBM_VECTOR*) 00000000000a373e __float128 0f SECT 01 0000 [.text] BltResFmt::ConvertFrom_R16G16B16A16_SNORM(void const*, unsigned int, _UBM_VECTOR*) 00000000000a353a __float128 0f SECT 01 0000 [.text] BltResFmt::ConvertFrom_R16G16B16A16_UNORM(void const*, unsigned int, _UBM_VECTOR*) 00000000000a2f98 __float128 0f SECT 01 0000 [.text] BltResFmt::ConvertFrom_R32G32B32A32_FLOAT(void const*, unsigned int, _UBM_VECTOR*) 00000000000a54c0 __float128 0f SECT 01 0000 [.text] BltResFmt::ConvertFrom_R9G9B9E5_SHAREDEXP(void const*, unsigned int, _UBM_VECTOR*) 00000000000a3a5c __float128 0f SECT 01 0000 [.text] BltResFmt::ConvertTo_D32_FLOAT_S8X24_UINT(_UBM_VECTOR const*, unsigned int, void*, unsigned int) 00000000000a4b22 __float128 0f SECT 01 0000 [.text] BltResFmt::ConvertTo_X24_TYPELESS_G8_UINT(_UBM_VECTOR const*, unsigned int, void*, unsigned int) 00000000000a4c80 __float128 0f SECT 01 0000 [.text] BltResFmt::ConvertTo_D24_UNORM_X8_TYPELESS(_UBM_VECTOR const*, unsigned int, void*, unsigned int) 00000000000a712c __float128 0f SECT 01 0000 [.text] BltResFmt::ConvertTo_R24_UNORM_X8_TYPELESS(_UBM_VECTOR const*, unsigned int, void*, unsigned int) 00000000000a3aa4 __float128 0f SECT 01 0000 [.text] BltResFmt::ConvertFrom_D32_FLOAT_S8X24_UINT(void const*, unsigned int, _UBM_VECTOR*) 00000000000a4b52 __float128 0f SECT 01 0000 [.text] BltResFmt::ConvertFrom_X24_TYPELESS_G8_UINT(void const*, unsigned int, _UBM_VECTOR*) 00000000000a4cac __float128 0f SECT 01 0000 [.text] BltResFmt::ConvertFrom_D24_UNORM_X8_TYPELESS(void const*, unsigned int, _UBM_VECTOR*) 00000000000a718c __float128 0f SECT 01 0000 [.text] BltResFmt::ConvertFrom_R24_UNORM_X8_TYPELESS(void const*, unsigned int, _UBM_VECTOR*) 00000000000a3af8 __float128 0f SECT 01 0000 [.text] BltResFmt::ConvertTo_X32_TYPELESS_G8X24_UINT(_UBM_VECTOR const*, unsigned int, void*, unsigned int) 00000000000a7158 __float128 0f SECT 01 0000 [.text] BltResFmt::ConvertFrom_R32_FLOAT_X8X24_TYPELESS(void const*, unsigned int, _UBM_VECTOR*) 00000000000a009c __float128 0f SECT 01 0000 [.text] BltResFmt::Init(UBM_FORMAT_MISSING_COMP_DEFAULTS) 00000000000a2f44 __float128 0f SECT 01 0000 [.text] BltResFmt::IsYuv(_UBM_FORMAT) 00000000000a0064 __float128 0f SECT 01 0000 [.text] BltResFmt::Create(_UBM_CREATEINFO const*) 00000000000a2e40 __float128 0f SECT 01 0000 [.text] BltResFmt::Destroy() 00000000000a6974 __float128 0f SECT 01 0000 [.text] BltResFmt::HasAlpha(_UBM_FORMAT) 00000000000a6900 __float128 0f SECT 01 0000 [.text] BltResFmt::HasDepth(_UBM_FORMAT) 00000000000a0014 __float128 0f SECT 01 0000 [.text] BltResFmt::BltResFmt() 000000000009fff4 __float128 0f SECT 01 0000 [.text] BltResFmt::BltResFmt() 00000000000a0048 __float128 0f SECT 01 0000 [.text] BltResFmt::~BltResFmt() 00000000000a003e __float128 0f SECT 01 0000 [.text] BltResFmt::~BltResFmt() 00000000000a0034 __float128 0f SECT 01 0000 [.text] BltResFmt::~BltResFmt() 00000000000a7282 __float128 0f SECT 01 0000 [.text] BltShader::SetBltShaderInput(BltShaderInput const*) 00000000000a72b0 __float128 0f SECT 01 0000 [.text] BltShader::CpuLoad(void*, LARGE_INTEGER, unsigned char*) 00000000000a722e __float128 0f SECT 01 0000 [.text] BltShader::BltShader() 00000000000a71da __float128 0f SECT 01 0000 [.text] BltShader::BltShader() 00000000000d644c __float128 0f SECT 01 0000 [.text] CIAddrLib::HwlComputeFmaskInfo(_ADDR_COMPUTE_FMASK_INFO_INPUT const*, _ADDR_COMPUTE_FMASK_INFO_OUTPUT*) 00000000000d6004 __float128 0f SECT 01 0000 [.text] CIAddrLib::HwlInitGlobalParams(_ADDR_CREATE_INPUT const*) 00000000000d5efe __float128 0f SECT 01 0000 [.text] CIAddrLib::HwlConvertChipFamily(unsigned int, unsigned int) 00000000000d60a2 __float128 0f SECT 01 0000 [.text] CIAddrLib::InitTileSettingTable(unsigned int const*, unsigned int) 00000000000d6156 __float128 0f SECT 01 0000 [.text] CIAddrLib::InitMacroTileCfgTable(unsigned int const*, unsigned int) 00000000000d5a5e __float128 0f SECT 01 0000 [.text] CIAddrLib::CIAddrLib(AddrClient const*) 00000000000d5aae __float128 0f SECT 01 0000 [.text] CIAddrLib::CIAddrLib(AddrClient const*) 00000000000d5afe __float128 0f SECT 01 0000 [.text] CIAddrLib::~CIAddrLib() 00000000000d5b1a __float128 0f SECT 01 0000 [.text] CIAddrLib::~CIAddrLib() 00000000000d5b24 __float128 0f SECT 01 0000 [.text] CIAddrLib::~CIAddrLib() 00000000000d4e2a __float128 0f SECT 01 0000 [.text] SIAddrLib::DecodeGbRegs(_ADDR_REGISTER_VALUE const*) 00000000000d4eee __float128 0f SECT 01 0000 [.text] SIAddrLib::HwlInitGlobalParams(_ADDR_CREATE_INPUT const*) 00000000000d4946 __float128 0f SECT 01 0000 [.text] SIAddrLib::HwlConvertChipFamily(unsigned int, unsigned int) 00000000000d4f50 __float128 0f SECT 01 0000 [.text] SIAddrLib::InitTileSettingTable(unsigned int const*, unsigned int) 00000000000d34f8 __float128 0f SECT 01 0000 [.text] SIAddrLib::SIAddrLib(AddrClient const*) 00000000000d353e __float128 0f SECT 01 0000 [.text] SIAddrLib::SIAddrLib(AddrClient const*) 00000000000d3584 __float128 0f SECT 01 0000 [.text] SIAddrLib::~SIAddrLib() 00000000000d35a0 __float128 0f SECT 01 0000 [.text] SIAddrLib::~SIAddrLib() 00000000000d35aa __float128 0f SECT 01 0000 [.text] SIAddrLib::~SIAddrLib() 000000000052eca0 __float128 0f SECT 0a 0000 [__DATA.__common] UbmObject::m_freeSysMem 000000000052ec98 __float128 0f SECT 0a 0000 [__DATA.__common] UbmObject::m_allocSysMem 00000000000a7e78 __float128 0f SECT 01 0000 [.text] UbmObject::SetupSysMemFuncs(void* (*)(_UBM_ALLOCSYSMEM_INPUT const*), _UBM_E_RETURNCODE (*)(void*)) 00000000000a7dde __float128 0f SECT 01 0000 [.text] UbmObject::UbmObject() 00000000000a7dd8 __float128 0f SECT 01 0000 [.text] UbmObject::UbmObject() 00000000000a7dea __float128 0f SECT 01 0000 [.text] UbmObject::~UbmObject() 00000000000a7de4 __float128 0f SECT 01 0000 [.text] UbmObject::~UbmObject() 00000000000a7e62 __float128 0f SECT 01 0000 [.text] UbmObject::operator delete[](void*) 00000000000a7e1e __float128 0f SECT 01 0000 [.text] UbmObject::operator delete(void*) 00000000000a7e34 __float128 0f SECT 01 0000 [.text] UbmObject::operator new[](unsigned long) 00000000000a7df0 __float128 0f SECT 01 0000 [.text] UbmObject::operator new(unsigned long) 00000000000cd616 __float128 0f SECT 01 0000 [.text] AddrObject::AddrMalloc(unsigned long) const 00000000000cd75c __float128 0f SECT 01 0000 [.text] AddrObject::DebugPrint(char const*, ...) const 00000000000cd69a __float128 0f SECT 01 0000 [.text] AddrObject::AddrFree(void*) const 00000000000871d2 __float128 0f SECT 01 0000 [.text] AMDVIHWGart::getMetaClass() const 0000000000087212 __float128 0f SECT 01 0000 [.text] AMDVIHWGart::MetaClass::alloc() const 00000000000d16ca __float128 0f SECT 01 0000 [.text] AddrElemLib::PixGetExportNorm(_AddrColorFormat, _AddrSurfaceNumber, _AddrSurfaceSwap) const 00000000000d0e9c __float128 0f SECT 01 0000 [.text] AddrElemLib::Flt32ToColorPixel(_AddrColorFormat, _AddrSurfaceNumber, _AddrSurfaceSwap, ADDR_FLT_32 const*, signed char*) const 00000000000d0c06 __float128 0f SECT 01 0000 [.text] AddrElemLib::Flt32ToDepthPixel(_AddrDepthFormat, ADDR_FLT_32 const*, signed char*) const 00000000000d0fe6 __float128 0f SECT 01 0000 [.text] AddrElemLib::PixGetColorCompInfo(_AddrColorFormat, _AddrSurfaceNumber, _AddrSurfaceSwap, ADDR_PIXEL_FORMATINFO*) const 00000000000d0d00 __float128 0f SECT 01 0000 [.text] AddrElemLib::PixGetDepthCompInfo(_AddrDepthFormat, ADDR_PIXEL_FORMATINFO*) const 00000000000d284a __float128 0f SECT 01 0000 [.text] R800AddrLib::HwlSetupTileInfo(_AddrTileMode, _ADDR_SURFACE_FLAGS, unsigned int, unsigned int, unsigned int, unsigned int, _ADDR_TILEINFO*, _ADDR_TILEINFO*, _AddrTileType, _ADDR_COMPUTE_SURFACE_INFO_OUTPUT*) const 00000000000d2f9a __float128 0f SECT 01 0000 [.text] R800AddrLib::ComputeDefaultBank(_AddrTileMode, unsigned int, _ADDR_SURFACE_FLAGS, unsigned int, unsigned int, unsigned int, unsigned int) const 00000000000d20c6 __float128 0f SECT 01 0000 [.text] R800AddrLib::HwlComputeMipLevel(_ADDR_COMPUTE_SURFACE_INFO_INPUT*) const 00000000000d3168 __float128 0f SECT 01 0000 [.text] R800AddrLib::HwlComputeFmaskBits(_ADDR_COMPUTE_FMASK_INFO_INPUT const*, unsigned int*) const 00000000000d23e6 __float128 0f SECT 01 0000 [.text] R800AddrLib::ComputePipeFromCoord(unsigned int, unsigned int, unsigned int, _AddrTileMode, unsigned int, int, _ADDR_TILEINFO*) const 00000000000d2840 __float128 0f SECT 01 0000 [.text] R800AddrLib::HwlComputeHtileBytes(unsigned int, unsigned int, unsigned int, int, unsigned int, unsigned long long*, unsigned int) const 00000000000d1bfe __float128 0f SECT 01 0000 [.text] R800AddrLib::SanityCheckPowerSave(unsigned int, unsigned int, unsigned int, unsigned int) const 00000000000d1b9c __float128 0f SECT 01 0000 [.text] R800AddrLib::HwlComputeSurfaceInfo(_ADDR_COMPUTE_SURFACE_INFO_INPUT const*, _ADDR_COMPUTE_SURFACE_INFO_OUTPUT*) const 00000000000d3072 __float128 0f SECT 01 0000 [.text] R800AddrLib::HwlSanityCheckMacroTiled(_ADDR_TILEINFO*) const 00000000000d3090 __float128 0f SECT 01 0000 [.text] R800AddrLib::HwlCheckLastMacroTiledLvl(_ADDR_COMPUTE_SURFACE_INFO_INPUT const*, _ADDR_COMPUTE_SURFACE_INFO_OUTPUT*) const 00000000000d3028 __float128 0f SECT 01 0000 [.text] R800AddrLib::HwlGetPitchAlignmentLinear(unsigned int, _ADDR_SURFACE_FLAGS) const 00000000000d3048 __float128 0f SECT 01 0000 [.text] R800AddrLib::HwlGetSizeAdjustmentLinear(_AddrTileMode, unsigned int, unsigned int, unsigned int, unsigned int, unsigned int*, unsigned int*, unsigned int*) const 00000000000d1c42 __float128 0f SECT 01 0000 [.text] R800AddrLib::ComputeSurfaceInfoPowerSave(_ADDR_COMPUTE_SURFACE_INFO_INPUT const*, _ADDR_COMPUTE_SURFACE_INFO_OUTPUT*) const 00000000000d1d2a __float128 0f SECT 01 0000 [.text] R800AddrLib::HwlComputeSurfaceAddrFromCoord(_ADDR_COMPUTE_SURFACE_ADDRFROMCOORD_INPUT const*, _ADDR_COMPUTE_SURFACE_ADDRFROMCOORD_OUTPUT*) const 00000000000d1eec __float128 0f SECT 01 0000 [.text] R800AddrLib::HwlComputeSurfaceCoordFromAddr(_ADDR_COMPUTE_SURFACE_COORDFROMADDR_INPUT const*, _ADDR_COMPUTE_SURFACE_COORDFROMADDR_OUTPUT*) const 00000000000d278e __float128 0f SECT 01 0000 [.text] R800AddrLib::HwlComputeXmaskCoordYFrom8Pipe(unsigned int, unsigned int) const 00000000000d3280 __float128 0f SECT 01 0000 [.text] R800AddrLib::ComputePixelIndexWithinPowerSave(unsigned int, unsigned int, unsigned int, unsigned int) const 00000000000d3250 __float128 0f SECT 01 0000 [.text] R800AddrLib::ComputeSurfaceAlignmentsPowerSave(unsigned int, _ADDR_SURFACE_FLAGS, unsigned int*, unsigned int*, unsigned int*) const 00000000000d3346 __float128 0f SECT 01 0000 [.text] R800AddrLib::ComputePixelCoordFromOffsetPowerSave(unsigned int, unsigned int, unsigned int*, unsigned int*) const 00000000000d1d7e __float128 0f SECT 01 0000 [.text] R800AddrLib::ComputeSurfaceAddrFromCoordPowerSave(unsigned int, unsigned int, unsigned int, unsigned int, unsigned int, unsigned int, _ADDR_TILEINFO*, unsigned int*) const 00000000000d1f44 __float128 0f SECT 01 0000 [.text] R800AddrLib::ComputeSurfaceCoordFromAddrPowerSave(unsigned long long, unsigned int, unsigned int, unsigned int, unsigned int, _ADDR_TILEINFO*, unsigned int*, unsigned int*) const 00000000000d2578 __float128 0f SECT 01 0000 [.text] R800AddrLib::HwlComputeSurfaceCoord2DFromBankPipe(_AddrTileMode, unsigned int*, unsigned int*, unsigned int, unsigned int, unsigned int, unsigned int, unsigned int, unsigned int, int, _ADDR_TILEINFO*) const 00000000000bcfac __float128 0f SECT 01 0000 [.text] SiBltResFmt::AlphaIsOnMSB(_UBM_FORMAT) const 00000000000bcefa __float128 0f SECT 01 0000 [.text] SiBltResFmt::GetRoundMode(_UBM_FORMAT) const 00000000000bcf36 __float128 0f SECT 01 0000 [.text] SiBltResFmt::SupportGamma(_UBM_FORMAT) const 00000000000bceae __float128 0f SECT 01 0000 [.text] SiBltResFmt::GetBlendClamp(_UBM_FORMAT) const 00000000000bc35c __float128 0f SECT 01 0000 [.text] SiBltResFmt::GetHwColorFmt(_UBM_FORMAT, unsigned int) const 00000000000bcc8e __float128 0f SECT 01 0000 [.text] SiBltResFmt::GetNumberType(_UBM_FORMAT) const 00000000000bce2a __float128 0f SECT 01 0000 [.text] SiBltResFmt::GetBlendBypass(_UBM_FORMAT) const 00000000000bcfe8 __float128 0f SECT 01 0000 [.text] SiBltResFmt::GetCompSetting(ColorFormat, SurfaceSwap) const 00000000000bcc62 __float128 0f SECT 01 0000 [.text] SiBltResFmt::GetHwBufNumFmt(_UBM_FORMAT) const 00000000000bcc14 __float128 0f SECT 01 0000 [.text] SiBltResFmt::GetHwImgNumFmt(_UBM_FORMAT) const 00000000000bccba __float128 0f SECT 01 0000 [.text] SiBltResFmt::GetSurfaceSwap(_UBM_FORMAT, unsigned int) const 00000000000bd5de __float128 0f SECT 01 0000 [.text] SiBltResFmt::GetCompBitCount(_UBM_FORMAT, unsigned int, unsigned int) const 00000000000bcc40 __float128 0f SECT 01 0000 [.text] SiBltResFmt::GetHwBufDataFmt(_UBM_FORMAT) const 00000000000bc340 __float128 0f SECT 01 0000 [.text] SiBltResFmt::GetHwEndianMode(_UBM_ENDIAN) const 00000000000bc794 __float128 0f SECT 01 0000 [.text] SiBltResFmt::GetHwImgDataFmt(_UBM_FORMAT, unsigned int) const 00000000000bc772 __float128 0f SECT 01 0000 [.text] SiBltResFmt::GetHwStencilFmt(_UBM_FORMAT) const 00000000000bd590 __float128 0f SECT 01 0000 [.text] SiBltResFmt::DepthBytesPerPixel(_UBM_FORMAT) const 00000000000bd5fa __float128 0f SECT 01 0000 [.text] SiBltResFmt::GetDccFastClearCode(_UBM_FORMAT, _UBM_VECTORL const*) const 00000000000bd036 __float128 0f SECT 01 0000 [.text] SiBltResFmt::GetShaderExportMode(_UBM_FORMAT, unsigned int, unsigned int, unsigned int) const 00000000000bcfd8 __float128 0f SECT 01 0000 [.text] SiBltResFmt::IsTcCompatibleDepth(_UBM_FORMAT) const 00000000000bcfc4 __float128 0f SECT 01 0000 [.text] SiBltResFmt::IsFmask(_UBM_FORMAT) const 00000000000bcf10 __float128 0f SECT 01 0000 [.text] SiBltResFmt::GetDstSel(_UBM_FORMAT, unsigned int, unsigned int) const 00000000000bc708 __float128 0f SECT 01 0000 [.text] SiBltResFmt::GetHwZFmt(_UBM_FORMAT, unsigned int) const 00000000000bc302 __float128 0f SECT 01 0000 [.text] SiBltResFmt::SupportRT(_UBM_FORMAT) const 000000000007aff2 __float128 0f SECT 01 0000 [.text] AMDCIDisplay::getMetaClass() const 000000000007b032 __float128 0f SECT 01 0000 [.text] AMDCIDisplay::MetaClass::alloc() const 0000000000082422 __float128 0f SECT 01 0000 [.text] AMDCIVCERing::getMetaClass() const 0000000000082462 __float128 0f SECT 01 0000 [.text] AMDCIVCERing::MetaClass::alloc() const 000000000006ebb2 __float128 0f SECT 01 0000 [.text] AMDSIDMARing::getMetaClass() const 000000000006ebf2 __float128 0f SECT 01 0000 [.text] AMDSIDMARing::MetaClass::alloc() const 0000000000063372 __float128 0f SECT 01 0000 [.text] AMDSIDisplay::getMetaClass() const 00000000000633b2 __float128 0f SECT 01 0000 [.text] AMDSIDisplay::MetaClass::alloc() const 0000000000073342 __float128 0f SECT 01 0000 [.text] AMDSISPURing::getMetaClass() const 0000000000073382 __float128 0f SECT 01 0000 [.text] AMDSISPURing::MetaClass::alloc() const 000000000002aaa2 __float128 0f SECT 01 0000 [.text] AMDSISurface::getMetaClass() const 000000000002aae2 __float128 0f SECT 01 0000 [.text] AMDSISurface::MetaClass::alloc() const 0000000000071c42 __float128 0f SECT 01 0000 [.text] AMDSIUVDRing::getMetaClass() const 0000000000071c82 __float128 0f SECT 01 0000 [.text] AMDSIUVDRing::MetaClass::alloc() const 0000000000070402 __float128 0f SECT 01 0000 [.text] AMDSIVCERing::getMetaClass() const 0000000000070442 __float128 0f SECT 01 0000 [.text] AMDSIVCERing::MetaClass::alloc() const 00000000000897f2 __float128 0f SECT 01 0000 [.text] AMDVIDisplay::getMetaClass() const 0000000000089832 __float128 0f SECT 01 0000 [.text] AMDVIDisplay::MetaClass::alloc() const 000000000007c762 __float128 0f SECT 01 0000 [.text] AMDCIHWMemory::getMetaClass() const 000000000007c7a2 __float128 0f SECT 01 0000 [.text] AMDCIHWMemory::MetaClass::alloc() const 0000000000074842 __float128 0f SECT 01 0000 [.text] AMDCIHardware::getMetaClass() const 0000000000074882 __float128 0f SECT 01 0000 [.text] AMDCIHardware::MetaClass::alloc() const 000000000003e170 __float128 0f SECT 01 0000 [.text] AMDCIResource::getFMaskInfo(_ADDR_COMPUTE_FMASK_INFO_INPUT*, _ADDR_COMPUTE_FMASK_INFO_OUTPUT*, _ADDR_TILEINFO*) const 000000000003d702 __float128 0f SECT 01 0000 [.text] AMDCIResource::getMetaClass() const 000000000003d808 __float128 0f SECT 01 0000 [.text] AMDCIResource::isLinearGeneral(_UBM_SURFINFO*) const 000000000003e2ca __float128 0f SECT 01 0000 [.text] AMDCIResource::stencilBufferOffset(IOAccelMemoryMap*, unsigned int, unsigned int, unsigned int) const 000000000003e1bc __float128 0f SECT 01 0000 [.text] AMDCIResource::fillTilingInfoForFMask(AMD_TILING_INFO*, _ADDR_TILEINFO const*, _AddrTileMode, int, _AddrTileType) const 000000000003daaa __float128 0f SECT 01 0000 [.text] AMDCIResource::fillUBMSurfaceInfoBacking(_UBM_SURFINFO*, IOAccelMemoryMap*, unsigned int, unsigned int, unsigned int, bool*) const 000000000003d7f4 __float128 0f SECT 01 0000 [.text] AMDCIResource::getArrayMode_linear_aligned() const 000000000003d800 __float128 0f SECT 01 0000 [.text] AMDCIResource::getArrayMode_linear_general() const 000000000003d742 __float128 0f SECT 01 0000 [.text] AMDCIResource::MetaClass::alloc() const 000000000007a482 __float128 0f SECT 01 0000 [.text] AMDCIsDMARing::getMetaClass() const 000000000007a4c2 __float128 0f SECT 01 0000 [.text] AMDCIsDMARing::MetaClass::alloc() const 0000000000062be2 __float128 0f SECT 01 0000 [.text] AMDSIHWMemory::getMetaClass() const 0000000000062c22 __float128 0f SECT 01 0000 [.text] AMDSIHWMemory::MetaClass::alloc() const 0000000000066ba2 __float128 0f SECT 01 0000 [.text] AMDSIHardware::getMetaClass() const 0000000000066be2 __float128 0f SECT 01 0000 [.text] AMDSIHardware::MetaClass::alloc() const 000000000002a6e6 __float128 0f SECT 01 0000 [.text] AMDSIResource::getFMaskInfo(_ADDR_COMPUTE_FMASK_INFO_INPUT*, _ADDR_COMPUTE_FMASK_INFO_OUTPUT*, _ADDR_TILEINFO*) const 000000000002a2c2 __float128 0f SECT 01 0000 [.text] AMDSIResource::getMetaClass() const 000000000002a40c __float128 0f SECT 01 0000 [.text] AMDSIResource::isLinearGeneral(_UBM_SURFINFO*) const 000000000002a7e0 __float128 0f SECT 01 0000 [.text] AMDSIResource::stencilBufferOffset(IOAccelMemoryMap*, unsigned int, unsigned int, unsigned int) const 000000000002a732 __float128 0f SECT 01 0000 [.text] AMDSIResource::fillTilingInfoForFMask(AMD_TILING_INFO*, _ADDR_TILEINFO const*, _AddrTileMode, int, _AddrTileType) const 000000000002a632 __float128 0f SECT 01 0000 [.text] AMDSIResource::fillUBMSurfaceInfoBacking(_UBM_SURFINFO*, IOAccelMemoryMap*, unsigned int, unsigned int, unsigned int, bool*) const 000000000002a3f8 __float128 0f SECT 01 0000 [.text] AMDSIResource::getArrayMode_linear_aligned() const 000000000002a404 __float128 0f SECT 01 0000 [.text] AMDSIResource::getArrayMode_linear_general() const 000000000002a302 __float128 0f SECT 01 0000 [.text] AMDSIResource::MetaClass::alloc() const 00000000000876e2 __float128 0f SECT 01 0000 [.text] AMDVIHWMemory::getMetaClass() const 0000000000087722 __float128 0f SECT 01 0000 [.text] AMDVIHWMemory::MetaClass::alloc() const 0000000000083ec2 __float128 0f SECT 01 0000 [.text] AMDVIHardware::getMetaClass() const 0000000000083f02 __float128 0f SECT 01 0000 [.text] AMDVIHardware::MetaClass::alloc() const 0000000000047a94 __float128 0f SECT 01 0000 [.text] AMDVIResource::getFMaskInfo(_ADDR_COMPUTE_FMASK_INFO_INPUT*, _ADDR_COMPUTE_FMASK_INFO_OUTPUT*, _ADDR_TILEINFO*) const 0000000000047012 __float128 0f SECT 01 0000 [.text] AMDVIResource::getMetaClass() const 0000000000047118 __float128 0f SECT 01 0000 [.text] AMDVIResource::isLinearGeneral(_UBM_SURFINFO*) const 0000000000047bee __float128 0f SECT 01 0000 [.text] AMDVIResource::stencilBufferOffset(IOAccelMemoryMap*, unsigned int, unsigned int, unsigned int) const 0000000000047ae0 __float128 0f SECT 01 0000 [.text] AMDVIResource::fillTilingInfoForFMask(AMD_TILING_INFO*, _ADDR_TILEINFO const*, _AddrTileMode, int, _AddrTileType) const 00000000000473ce __float128 0f SECT 01 0000 [.text] AMDVIResource::fillUBMSurfaceInfoBacking(_UBM_SURFINFO*, IOAccelMemoryMap*, unsigned int, unsigned int, unsigned int, bool*) const 0000000000047104 __float128 0f SECT 01 0000 [.text] AMDVIResource::getArrayMode_linear_aligned() const 0000000000047110 __float128 0f SECT 01 0000 [.text] AMDVIResource::getArrayMode_linear_general() const 0000000000047052 __float128 0f SECT 01 0000 [.text] AMDVIResource::MetaClass::alloc() const 000000000008cf32 __float128 0f SECT 01 0000 [.text] AMDVIsDMARing::getMetaClass() const 000000000008cf72 __float128 0f SECT 01 0000 [.text] AMDVIsDMARing::MetaClass::alloc() const 00000000000b2e32 __float128 0f SECT 01 0000 [.text] SiBltDrawRegs::GetDccSetting(SiBltDevice const*, _UBM_SURFINFO const*) const 00000000000b224c __float128 0f SECT 01 0000 [.text] SiBltDrawRegs::GetNumEntriesNeeded(BltInfo const*) const 00000000000b3860 __float128 0f SECT 01 0000 [.text] SiBltDrawRegs::GetDecompressZPlaneThreshold(SiBltDevice const*, unsigned int) const 00000000000a776a __float128 0f SECT 01 0000 [.text] SurfAttribute::FreeSysMem(void*) const 00000000000a7740 __float128 0f SECT 01 0000 [.text] SurfAttribute::AllocSysMem(unsigned int) const 0000000000043b22 __float128 0f SECT 01 0000 [.text] AMDCICLContext::getMetaClass() const 0000000000043b62 __float128 0f SECT 01 0000 [.text] AMDCICLContext::MetaClass::alloc() const 0000000000078012 __float128 0f SECT 01 0000 [.text] AMDCIPM4Engine::getMetaClass() const 0000000000078052 __float128 0f SECT 01 0000 [.text] AMDCIPM4Engine::MetaClass::alloc() const 000000000003a46a __float128 0f SECT 01 0000 [.text] AMDSICLContext::getMetaClass() const 000000000003a4aa __float128 0f SECT 01 0000 [.text] AMDSICLContext::MetaClass::alloc() const 000000000006d622 __float128 0f SECT 01 0000 [.text] AMDSIDMAEngine::getMetaClass() const 000000000006d662 __float128 0f SECT 01 0000 [.text] AMDSIDMAEngine::MetaClass::alloc() const 000000000003202c __float128 0f SECT 01 0000 [.text] AMDSIGLContext::getMetaClass() const 0000000000032b1a __float128 0f SECT 01 0000 [.text] AMDSIGLContext::get_texture_offset(AMDRadeonX4000_AMDAccelResource*, unsigned int) const 00000000000326b6 __float128 0f SECT 01 0000 [.text] AMDSIGLContext::CmdBufOffsetIsValid(IOAccelCommandStreamInfo const&, unsigned int) const 0000000000033bfa __float128 0f SECT 01 0000 [.text] AMDSIGLContext::get_max_render_slices(AMDRadeonX4000_AMDAccelResource*) const 000000000003206c __float128 0f SECT 01 0000 [.text] AMDSIGLContext::MetaClass::alloc() const 000000000006b182 __float128 0f SECT 01 0000 [.text] AMDSIPM4Engine::getMetaClass() const 000000000006b1c2 __float128 0f SECT 01 0000 [.text] AMDSIPM4Engine::MetaClass::alloc() const 0000000000072232 __float128 0f SECT 01 0000 [.text] AMDSISPUEngine::getMetaClass() const 0000000000072272 __float128 0f SECT 01 0000 [.text] AMDSISPUEngine::MetaClass::alloc() const 00000000000651b2 __float128 0f SECT 01 0000 [.text] AMDSIVMContext::getMetaClass() const 00000000000651f2 __float128 0f SECT 01 0000 [.text] AMDSIVMContext::MetaClass::alloc() const 000000000008f3f2 __float128 0f SECT 01 0000 [.text] AMDVIPM4Engine::getMetaClass() const 000000000008f432 __float128 0f SECT 01 0000 [.text] AMDVIPM4Engine::MetaClass::alloc() const 0000000000087df2 __float128 0f SECT 01 0000 [.text] AMDVIVMContext::getMetaClass() const 0000000000087e32 __float128 0f SECT 01 0000 [.text] AMDVIVMContext::MetaClass::alloc() const 00000000000da25c __float128 0f SECT 01 0000 [.text] EgBasedAddrLib::HwlTileInfoEqual(_ADDR_TILEINFO const*, _ADDR_TILEINFO const*) const 00000000000d9ea4 __float128 0f SECT 01 0000 [.text] EgBasedAddrLib::ComputeHtileBytes(unsigned int, unsigned int, unsigned int, int, unsigned int, unsigned long long*, unsigned int) const 00000000000d9afe __float128 0f SECT 01 0000 [.text] EgBasedAddrLib::GetBankPipeSwizzle(unsigned int, unsigned int, unsigned long long, _ADDR_TILEINFO*) const 00000000000da8de __float128 0f SECT 01 0000 [.text] EgBasedAddrLib::HwlComputeHtileBpp(int, int) const 00000000000d94bc __float128 0f SECT 01 0000 [.text] EgBasedAddrLib::ComputeBankFromAddr(unsigned long long, unsigned int, unsigned int) const 00000000000d9a50 __float128 0f SECT 01 0000 [.text] EgBasedAddrLib::ComputeBankRotation(_AddrTileMode, unsigned int, unsigned int) const 00000000000d9a8a __float128 0f SECT 01 0000 [.text] EgBasedAddrLib::ComputePipeRotation(_AddrTileMode, unsigned int) const 00000000000d7e4c __float128 0f SECT 01 0000 [.text] EgBasedAddrLib::HwlDegradeBaseLevel(_ADDR_COMPUTE_SURFACE_INFO_INPUT const*) const 00000000000d87c6 __float128 0f SECT 01 0000 [.text] EgBasedAddrLib::ComputeBankFromCoord(unsigned int, unsigned int, unsigned int, _AddrTileMode, unsigned int, unsigned int, _ADDR_TILEINFO*) const 00000000000d9bae __float128 0f SECT 01 0000 [.text] EgBasedAddrLib::HwlComputeBaseSwizzle(_ADDR_COMPUTE_BASE_SWIZZLE_INPUT const*, _ADDR_COMPUTE_BASE_SWIZZLE_OUTPUT*) const 00000000000da740 __float128 0f SECT 01 0000 [.text] EgBasedAddrLib::HwlComputeSurfaceInfo(_ADDR_COMPUTE_SURFACE_INFO_INPUT const*, _ADDR_COMPUTE_SURFACE_INFO_OUTPUT*) const 00000000000d7dc4 __float128 0f SECT 01 0000 [.text] EgBasedAddrLib::SanityCheckMacroTiled(_ADDR_TILEINFO*) const 00000000000d8372 __float128 0f SECT 01 0000 [.text] EgBasedAddrLib::ExtractBankPipeSwizzle(unsigned int, _ADDR_TILEINFO*, unsigned int*, unsigned int*) const 00000000000da290 __float128 0f SECT 01 0000 [.text] EgBasedAddrLib::HwlConvertTileInfoToHW(_ADDR_CONVERT_TILEINFOTOHW_INPUT const*, _ADDR_CONVERT_TILEINFOTOHW_OUTPUT*) const 00000000000d9c8c __float128 0f SECT 01 0000 [.text] EgBasedAddrLib::ComputeSliceTileSwizzle(_AddrTileMode, unsigned int, unsigned int, unsigned long long, _ADDR_TILEINFO*) const 00000000000d7fd4 __float128 0f SECT 01 0000 [.text] EgBasedAddrLib::HwlDegradeThickTileMode(_AddrTileMode, unsigned int, unsigned int*) const 00000000000d7280 __float128 0f SECT 01 0000 [.text] EgBasedAddrLib::ComputeSurfaceInfoLinear(_ADDR_COMPUTE_SURFACE_INFO_INPUT const*, _ADDR_COMPUTE_SURFACE_INFO_OUTPUT*, unsigned int) const 00000000000da8ea __float128 0f SECT 01 0000 [.text] EgBasedAddrLib::HwlComputeHtileBaseAlign(int, int, _ADDR_TILEINFO*) const 00000000000d7c92 __float128 0f SECT 01 0000 [.text] EgBasedAddrLib::HwlReduceBankWidthHeight(unsigned int, unsigned int, _ADDR_SURFACE_FLAGS, unsigned int, unsigned int, unsigned int, _ADDR_TILEINFO*) const 00000000000d9ad2 __float128 0f SECT 01 0000 [.text] EgBasedAddrLib::HwlCombineBankPipeSwizzle(unsigned int, unsigned int, _ADDR_TILEINFO*, unsigned long long, unsigned int*) const 00000000000d9ab2 __float128 0f SECT 01 0000 [.text] EgBasedAddrLib::HwlExtractBankPipeSwizzle(_ADDR_EXTRACT_BANKPIPE_SWIZZLE_INPUT const*, _ADDR_EXTRACT_BANKPIPE_SWIZZLE_OUTPUT*) const 00000000000d70ce __float128 0f SECT 01 0000 [.text] EgBasedAddrLib::DispatchComputeSurfaceInfo(_ADDR_COMPUTE_SURFACE_INFO_INPUT const*, _ADDR_COMPUTE_SURFACE_INFO_OUTPUT*) const 00000000000da8a0 __float128 0f SECT 01 0000 [.text] EgBasedAddrLib::HwlComputeSliceTileSwizzle(_ADDR_COMPUTE_SLICESWIZZLE_INPUT const*, _ADDR_COMPUTE_SLICESWIZZLE_OUTPUT*) const 00000000000d7574 __float128 0f SECT 01 0000 [.text] EgBasedAddrLib::ComputeSurfaceInfoMacroTiled(_ADDR_COMPUTE_SURFACE_INFO_INPUT const*, _ADDR_COMPUTE_SURFACE_INFO_OUTPUT*, unsigned int, _AddrTileMode) const 00000000000d73d8 __float128 0f SECT 01 0000 [.text] EgBasedAddrLib::ComputeSurfaceInfoMicroTiled(_ADDR_COMPUTE_SURFACE_INFO_INPUT const*, _ADDR_COMPUTE_SURFACE_INFO_OUTPUT*, unsigned int, _AddrTileMode) const 00000000000da1c8 __float128 0f SECT 01 0000 [.text] EgBasedAddrLib::HwlComputeFmaskAddrFromCoord(_ADDR_COMPUTE_FMASK_ADDRFROMCOORD_INPUT const*, _ADDR_COMPUTE_FMASK_ADDRFROMCOORD_OUTPUT*) const 00000000000da1d0 __float128 0f SECT 01 0000 [.text] EgBasedAddrLib::HwlComputeFmaskCoordFromAddr(_ADDR_COMPUTE_FMASK_COORDFROMADDR_INPUT const*, _ADDR_COMPUTE_FMASK_COORDFROMADDR_OUTPUT*) const 00000000000d7882 __float128 0f SECT 01 0000 [.text] EgBasedAddrLib::ComputeSurfaceAlignmentsLinear(_AddrTileMode, unsigned int, _ADDR_SURFACE_FLAGS, unsigned int*, unsigned int*, unsigned int*) const 00000000000d7b6c __float128 0f SECT 01 0000 [.text] EgBasedAddrLib::ComputeSurfaceMipLevelTileMode(_AddrTileMode, unsigned int, unsigned int, unsigned int, unsigned int, unsigned int, unsigned int, unsigned int, _ADDR_TILEINFO*) const 00000000000d89ce __float128 0f SECT 01 0000 [.text] EgBasedAddrLib::HwlComputePixelCoordFromOffset(unsigned int, unsigned int, unsigned int, _AddrTileMode, unsigned int, unsigned int, unsigned int*, unsigned int*, unsigned int*, unsigned int*, _AddrTileType, int) const 00000000000d9e18 __float128 0f SECT 01 0000 [.text] EgBasedAddrLib::HwlComputeQbStereoRightSwizzle(_ADDR_COMPUTE_SURFACE_INFO_OUTPUT*) const 00000000000da844 __float128 0f SECT 01 0000 [.text] EgBasedAddrLib::HwlComputeSurfaceAddrFromCoord(_ADDR_COMPUTE_SURFACE_ADDRFROMCOORD_INPUT const*, _ADDR_COMPUTE_SURFACE_ADDRFROMCOORD_OUTPUT*) const 00000000000da880 __float128 0f SECT 01 0000 [.text] EgBasedAddrLib::HwlComputeSurfaceCoordFromAddr(_ADDR_COMPUTE_SURFACE_COORDFROMADDR_INPUT const*, _ADDR_COMPUTE_SURFACE_COORDFROMADDR_OUTPUT*) const 00000000000da926 __float128 0f SECT 01 0000 [.text] EgBasedAddrLib::HwlGetPitchAlignmentMicroTiled(_AddrTileMode, unsigned int, _ADDR_SURFACE_FLAGS, unsigned int) const 00000000000da97c __float128 0f SECT 01 0000 [.text] EgBasedAddrLib::HwlGetSizeAdjustmentMicroTiled(unsigned int, unsigned int, _ADDR_SURFACE_FLAGS, unsigned int, unsigned int, unsigned int, unsigned int*, unsigned int*) const 00000000000d94ec __float128 0f SECT 01 0000 [.text] EgBasedAddrLib::ComputeSurfaceCoord2DFromBankPipe(_AddrTileMode, unsigned int, unsigned int, unsigned int, unsigned int, unsigned int, unsigned int, unsigned int, unsigned int, _ADDR_TILEINFO*, CoordFromBankPipe*) const 00000000000d7998 __float128 0f SECT 01 0000 [.text] EgBasedAddrLib::ComputeSurfaceAlignmentsMacroTiled(_AddrTileMode, unsigned int, _ADDR_SURFACE_FLAGS, unsigned int, unsigned int, _ADDR_TILEINFO*, unsigned int*, unsigned int*, unsigned int*) const 00000000000d7906 __float128 0f SECT 01 0000 [.text] EgBasedAddrLib::ComputeSurfaceAlignmentsMicroTiled(_AddrTileMode, unsigned int, _ADDR_SURFACE_FLAGS, unsigned int, unsigned int*, unsigned int*, unsigned int*) const 00000000000d805e __float128 0f SECT 01 0000 [.text] EgBasedAddrLib::DispatchComputeSurfaceAddrFromCoord(_ADDR_COMPUTE_SURFACE_ADDRFROMCOORD_INPUT const*, _ADDR_COMPUTE_SURFACE_ADDRFROMCOORD_OUTPUT*) const 00000000000d8f6e __float128 0f SECT 01 0000 [.text] EgBasedAddrLib::DispatchComputeSurfaceCoordFromAddr(_ADDR_COMPUTE_SURFACE_COORDFROMADDR_INPUT const*, _ADDR_COMPUTE_SURFACE_COORDFROMADDR_OUTPUT*) const 00000000000d846a __float128 0f SECT 01 0000 [.text] EgBasedAddrLib::ComputeSurfaceAddrFromCoordMacroTiled(unsigned int, unsigned int, unsigned int, unsigned int, unsigned int, unsigned int, unsigned int, unsigned int, _AddrTileMode, _AddrTileType, int, int, unsigned int, unsigned int, _ADDR_TILEINFO*, unsigned int*) const 00000000000d826e __float128 0f SECT 01 0000 [.text] EgBasedAddrLib::ComputeSurfaceAddrFromCoordMicroTiled(unsigned int, unsigned int, unsigned int, unsigned int, unsigned int, unsigned int, unsigned int, unsigned int, _AddrTileMode, _AddrTileType, int, unsigned int*) const 00000000000d91d6 __float128 0f SECT 01 0000 [.text] EgBasedAddrLib::ComputeSurfaceCoordFromAddrMacroTiled(unsigned long long, unsigned int, unsigned int, unsigned int, unsigned int, unsigned int, _AddrTileMode, unsigned int, unsigned int, _AddrTileType, int, int, unsigned int, unsigned int, _ADDR_TILEINFO*, unsigned int*, unsigned int*, unsigned int*, unsigned int*) const 000000000007e2b2 __float128 0f SECT 01 0000 [.text] AMDCIDMAChannel::getMetaClass() const 000000000007e3fc __float128 0f SECT 01 0000 [.text] AMDCIDMAChannel::writeSemaphoreCommand(unsigned int*, unsigned long long, bool) const 000000000007e2f2 __float128 0f SECT 01 0000 [.text] AMDCIDMAChannel::MetaClass::alloc() const 000000000007d282 __float128 0f SECT 01 0000 [.text] AMDCIPM4Channel::getMetaClass() const 000000000007dcb6 __float128 0f SECT 01 0000 [.text] AMDCIPM4Channel::writeSemaphoreCommand(unsigned int*, unsigned long long, bool) const 000000000007d2c2 __float128 0f SECT 01 0000 [.text] AMDCIPM4Channel::MetaClass::alloc() const 000000000007f162 __float128 0f SECT 01 0000 [.text] AMDCISAMUEngine::getMetaClass() const 000000000007f1a2 __float128 0f SECT 01 0000 [.text] AMDCISAMUEngine::MetaClass::alloc() const 0000000000081c52 __float128 0f SECT 01 0000 [.text] AMDCIVCEChannel::getMetaClass() const 0000000000081d6c __float128 0f SECT 01 0000 [.text] AMDCIVCEChannel::writeSemaphoreCommand(unsigned int*, unsigned long long, bool) const 0000000000081c92 __float128 0f SECT 01 0000 [.text] AMDCIVCEChannel::MetaClass::alloc() const 00000000000829b2 __float128 0f SECT 01 0000 [.text] AMDCIVCELLQRing::getMetaClass() const 00000000000829f2 __float128 0f SECT 01 0000 [.text] AMDCIVCELLQRing::MetaClass::alloc() const 0000000000079c42 __float128 0f SECT 01 0000 [.text] AMDCIsDMAEngine::getMetaClass() const 0000000000079c82 __float128 0f SECT 01 0000 [.text] AMDCIsDMAEngine::MetaClass::alloc() const 000000000006db12 __float128 0f SECT 01 0000 [.text] AMDSIDMAChannel::getMetaClass() const 000000000006dc5c __float128 0f SECT 01 0000 [.text] AMDSIDMAChannel::writeSemaphoreCommand(unsigned int*, unsigned long long, bool) const 000000000006db52 __float128 0f SECT 01 0000 [.text] AMDSIDMAChannel::MetaClass::alloc() const 000000000006c5a2 __float128 0f SECT 01 0000 [.text] AMDSIPM4Channel::getMetaClass() const 000000000006c5e2 __float128 0f SECT 01 0000 [.text] AMDSIPM4Channel::MetaClass::alloc() const 0000000000072f42 __float128 0f SECT 01 0000 [.text] AMDSISPUChannel::getMetaClass() const 0000000000072f82 __float128 0f SECT 01 0000 [.text] AMDSISPUChannel::MetaClass::alloc() const 0000000000070d82 __float128 0f SECT 01 0000 [.text] AMDSIUVDChannel::getMetaClass() const 0000000000070ff4 __float128 0f SECT 01 0000 [.text] AMDSIUVDChannel::writeSemaphoreCommand(unsigned int*, unsigned long long, bool) const 0000000000070dc2 __float128 0f SECT 01 0000 [.text] AMDSIUVDChannel::MetaClass::alloc() const 000000000006fc32 __float128 0f SECT 01 0000 [.text] AMDSIVCEChannel::getMetaClass() const 000000000006fd4c __float128 0f SECT 01 0000 [.text] AMDSIVCEChannel::writeSemaphoreCommand(unsigned int*, unsigned long long, bool) const 000000000006fc72 __float128 0f SECT 01 0000 [.text] AMDSIVCEChannel::MetaClass::alloc() const 0000000000070992 __float128 0f SECT 01 0000 [.text] AMDSIVCELLQRing::getMetaClass() const 00000000000709d2 __float128 0f SECT 01 0000 [.text] AMDSIVCELLQRing::MetaClass::alloc() const 000000000008df72 __float128 0f SECT 01 0000 [.text] AMDVIPM4Channel::getMetaClass() const 000000000008e9a8 __float128 0f SECT 01 0000 [.text] AMDVIPM4Channel::writeSemaphoreCommand(unsigned int*, unsigned long long, bool) const 000000000008dfb2 __float128 0f SECT 01 0000 [.text] AMDVIPM4Channel::MetaClass::alloc() const 0000000000092372 __float128 0f SECT 01 0000 [.text] AMDVISAMUEngine::getMetaClass() const 00000000000923b2 __float128 0f SECT 01 0000 [.text] AMDVISAMUEngine::MetaClass::alloc() const 000000000008c712 __float128 0f SECT 01 0000 [.text] AMDVIsDMAEngine::getMetaClass() const 000000000008c752 __float128 0f SECT 01 0000 [.text] AMDVIsDMAEngine::MetaClass::alloc() const 00000000000cb5a8 __float128 0f SECT 01 0000 [.text] SiSurfAttribute::GetTileMode(_UBM_SURFINFO const*) const 00000000000cb674 __float128 0f SECT 01 0000 [.text] SiSurfAttribute::GetTileType(_UBM_SURFINFO const*) const 00000000000cb6f4 __float128 0f SECT 01 0000 [.text] SiSurfAttribute::GetArrayMode(int) const 00000000000cb830 __float128 0f SECT 01 0000 [.text] SiSurfAttribute::GetTileConfig(int) const 00000000000cb7ac __float128 0f SECT 01 0000 [.text] SiSurfAttribute::GetCBTileIndex(int, unsigned int*) const 00000000000cb8b0 __float128 0f SECT 01 0000 [.text] SiSurfAttribute::ComputeTileIndex(_UBM_TILE_MODE, _UBM_TILE_TYPE, unsigned int) const 00000000000cb6be __float128 0f SECT 01 0000 [.text] SiSurfAttribute::GetMicroTileMode(int) const 00000000000cb71c __float128 0f SECT 01 0000 [.text] SiSurfAttribute::IsValidTileIndex(int) const 00000000000cb7f8 __float128 0f SECT 01 0000 [.text] SiSurfAttribute::GetDepthTileSplitSize(int) const 00000000000cba42 __float128 0f SECT 01 0000 [.text] SiSurfAttribute::GetMacroTileDimension(unsigned int, unsigned int*, unsigned int*) const 00000000000cba14 __float128 0f SECT 01 0000 [.text] SiSurfAttribute::GetLinearAlignedTileIndex() const 00000000000cb73a __float128 0f SECT 01 0000 [.text] SiSurfAttribute::GetCICompressZResolveCBIndex(int) const 00000000000cb572 __float128 0f SECT 01 0000 [.text] SiSurfAttribute::GetLinearAlignedSurfacePitchAlign(unsigned int) const 00000000000cb58e __float128 0f SECT 01 0000 [.text] SiSurfAttribute::GetLinearAlignedSurfaceSliceAlign(unsigned int) const 0000000000082da2 __float128 0f SECT 01 0000 [.text] AMDCIComputeRing::getMetaClass() const 0000000000082de2 __float128 0f SECT 01 0000 [.text] AMDCIComputeRing::MetaClass::alloc() const 000000000007cef2 __float128 0f SECT 01 0000 [.text] AMDCIHWUtilities::getMetaClass() const 000000000007d052 __float128 0f SECT 01 0000 [.text] AMDCIHWUtilities::getUbmTileMode(unsigned int) const 000000000007cf32 __float128 0f SECT 01 0000 [.text] AMDCIHWUtilities::MetaClass::alloc() const 000000000007fa32 __float128 0f SECT 01 0000 [.text] AMDCISAMURBIRing::getMetaClass() const 000000000007fa72 __float128 0f SECT 01 0000 [.text] AMDCISAMURBIRing::MetaClass::alloc() const 0000000000080f22 __float128 0f SECT 01 0000 [.text] AMDCIUVDHWEngine::getMetaClass() const 0000000000080f62 __float128 0f SECT 01 0000 [.text] AMDCIUVDHWEngine::MetaClass::alloc() const 0000000000081452 __float128 0f SECT 01 0000 [.text] AMDCIVCEHWEngine::getMetaClass() const 0000000000081492 __float128 0f SECT 01 0000 [.text] AMDCIVCEHWEngine::MetaClass::alloc() const 0000000000073902 __float128 0f SECT 01 0000 [.text] AMDSIComputeRing::getMetaClass() const 0000000000073942 __float128 0f SECT 01 0000 [.text] AMDSIComputeRing::MetaClass::alloc() const 0000000000064df2 __float128 0f SECT 01 0000 [.text] AMDSIHWUtilities::getMetaClass() const 000000000006503c __float128 0f SECT 01 0000 [.text] AMDSIHWUtilities::getUbmTileMode(unsigned int) const 0000000000064e32 __float128 0f SECT 01 0000 [.text] AMDSIHWUtilities::MetaClass::alloc() const 0000000000071432 __float128 0f SECT 01 0000 [.text] AMDSIUVDHWEngine::getMetaClass() const 0000000000071472 __float128 0f SECT 01 0000 [.text] AMDSIUVDHWEngine::MetaClass::alloc() const 000000000006f432 __float128 0f SECT 01 0000 [.text] AMDSIVCEHWEngine::getMetaClass() const 000000000006f472 __float128 0f SECT 01 0000 [.text] AMDSIVCEHWEngine::MetaClass::alloc() const 0000000000086c32 __float128 0f SECT 01 0000 [.text] AMDTongaHardware::getMetaClass() const 0000000000086c72 __float128 0f SECT 01 0000 [.text] AMDTongaHardware::MetaClass::alloc() const 000000000008d9f2 __float128 0f SECT 01 0000 [.text] AMDVIComputeRing::getMetaClass() const 000000000008da32 __float128 0f SECT 01 0000 [.text] AMDVIComputeRing::MetaClass::alloc() const 000000000008b4e2 __float128 0f SECT 01 0000 [.text] AMDVIHWUtilities::getMetaClass() const 000000000008b642 __float128 0f SECT 01 0000 [.text] AMDVIHWUtilities::getUbmTileMode(unsigned int) const 000000000008b522 __float128 0f SECT 01 0000 [.text] AMDVIHWUtilities::MetaClass::alloc() const 0000000000092812 __float128 0f SECT 01 0000 [.text] AMDVISAMURBIRing::getMetaClass() const 0000000000092852 __float128 0f SECT 01 0000 [.text] AMDVISAMURBIRing::MetaClass::alloc() const 000000000008b862 __float128 0f SECT 01 0000 [.text] AMDVIsDMAChannel::getMetaClass() const 000000000008b9ac __float128 0f SECT 01 0000 [.text] AMDVIsDMAChannel::writeSemaphoreCommand(unsigned int*, unsigned long long, bool) const 000000000008b8a2 __float128 0f SECT 01 0000 [.text] AMDVIsDMAChannel::MetaClass::alloc() const 000000000006a892 __float128 0f SECT 01 0000 [.text] AMDVerdeHardware::getMetaClass() const 000000000006a8d2 __float128 0f SECT 01 0000 [.text] AMDVerdeHardware::MetaClass::alloc() const 00000000000bb618 __float128 0f SECT 01 0000 [.text] SiBltPixelShader::GetShaderMemSize() const 00000000000bbac0 __float128 0f SECT 01 0000 [.text] SiBltPixelShader::GetPsCbShaderMask() const 00000000000bb5d4 __float128 0f SECT 01 0000 [.text] SiBltPixelShader::GetTotalPatchCodeSize() const 00000000000bb66a __float128 0f SECT 01 0000 [.text] SiBltPixelShader::GetRoundedShaderMemSize() const 00000000000bb5ea __float128 0f SECT 01 0000 [.text] SiBltPixelShader::GetPatchTrackerDwordOffset() const 00000000000bbaee __float128 0f SECT 01 0000 [.text] SiBltPixelShader::WriteToHw(SiBltDevice*, SiBltVertexShader const*) const 0000000000079772 __float128 0f SECT 01 0000 [.text] AMDCICommandsRing::getMetaClass() const 00000000000797b2 __float128 0f SECT 01 0000 [.text] AMDCICommandsRing::MetaClass::alloc() const 0000000000077a72 __float128 0f SECT 01 0000 [.text] AMDHawaiiHardware::getMetaClass() const 0000000000077ab2 __float128 0f SECT 01 0000 [.text] AMDHawaiiHardware::MetaClass::alloc() const 000000000006cfc2 __float128 0f SECT 01 0000 [.text] AMDSICommandsRing::getMetaClass() const 000000000006d002 __float128 0f SECT 01 0000 [.text] AMDSICommandsRing::MetaClass::alloc() const 000000000002ace2 __float128 0f SECT 01 0000 [.text] AMDSIVideoContext::getMetaClass() const 000000000002ad22 __float128 0f SECT 01 0000 [.text] AMDSIVideoContext::MetaClass::alloc() const 0000000000069c72 __float128 0f SECT 01 0000 [.text] AMDTahitiHardware::getMetaClass() const 0000000000069cb2 __float128 0f SECT 01 0000 [.text] AMDTahitiHardware::MetaClass::alloc() const 000000000008d522 __float128 0f SECT 01 0000 [.text] AMDVICommandsRing::getMetaClass() const 000000000008d562 __float128 0f SECT 01 0000 [.text] AMDVICommandsRing::MetaClass::alloc() const 000000000006c242 __float128 0f SECT 01 0000 [.text] AMDVerdePM4Engine::getMetaClass() const 000000000006c282 __float128 0f SECT 01 0000 [.text] AMDVerdePM4Engine::MetaClass::alloc() const 00000000000ca358 __float128 0f SECT 01 0000 [.text] SiBltVertexShader::GetVsSemanticsOffset(unsigned int, unsigned int) const 00000000000ca390 __float128 0f SECT 01 0000 [.text] SiBltVertexShader::WriteToHw(SiBltDevice*) const 00000000000cb074 __float128 0f SECT 01 0000 [.text] SiShaderVidMemMgr::HwlVidMemAllocInfo(_UBM_ALLOCVIDMEM_INPUT*) const 00000000000774c2 __float128 0f SECT 01 0000 [.text] AMDBonaireHardware::getMetaClass() const 0000000000077502 __float128 0f SECT 01 0000 [.text] AMDBonaireHardware::MetaClass::alloc() const 00000000000803b2 __float128 0f SECT 01 0000 [.text] AMDCISAMUGPCOMRing::getMetaClass() const 00000000000803f2 __float128 0f SECT 01 0000 [.text] AMDCISAMUGPCOMRing::MetaClass::alloc() const 0000000000082102 __float128 0f SECT 01 0000 [.text] AMDCIVCELLQChannel::getMetaClass() const 0000000000082142 __float128 0f SECT 01 0000 [.text] AMDCIVCELLQChannel::MetaClass::alloc() const 00000000000700e2 __float128 0f SECT 01 0000 [.text] AMDSIVCELLQChannel::getMetaClass() const 0000000000070122 __float128 0f SECT 01 0000 [.text] AMDSIVCELLQChannel::MetaClass::alloc() const 000000000006bb82 __float128 0f SECT 01 0000 [.text] AMDTahitiPM4Engine::getMetaClass() const 000000000006bbc2 __float128 0f SECT 01 0000 [.text] AMDTahitiPM4Engine::MetaClass::alloc() const 0000000000092f52 __float128 0f SECT 01 0000 [.text] AMDVISAMUGPCOMRing::getMetaClass() const 0000000000092f92 __float128 0f SECT 01 0000 [.text] AMDVISAMUGPCOMRing::MetaClass::alloc() const 00000000000aadc2 __float128 0f SECT 01 0000 [.text] SiBltComputeShader::WriteToHw(SiBltDevice*) const 00000000000be5e2 __float128 0f SECT 01 0000 [.text] SiBltShaderLibrary::SelectExportZPs(_UBM_FORMAT, unsigned int, unsigned int) const 00000000000be3cc __float128 0f SECT 01 0000 [.text] SiBltShaderLibrary::SelectStretchPs(BltInfo const*) const 00000000000be61a __float128 0f SECT 01 0000 [.text] SiBltShaderLibrary::SelectFMaskShaderResolvePs(_UBM_MSAA_SHADER_RESOLVE_FILTER, unsigned int, unsigned int) const 00000000000be6a8 __float128 0f SECT 01 0000 [.text] SiBltShaderLibrary::SelectFastDepthClearShader(BltInfo const*) const 00000000000be5b8 __float128 0f SECT 01 0000 [.text] SiBltShaderLibrary::SelectShaderColorResolvePs(_UBM_MSAA_SHADER_RESOLVE_FILTER, unsigned int, unsigned int) const 00000000000be6f2 __float128 0f SECT 01 0000 [.text] SiBltShaderLibrary::GetCsType(BltInfo const*) const 00000000000bdf58 __float128 0f SECT 01 0000 [.text] SiBltShaderLibrary::GetPsType(BltInfo const*) const 00000000000bde36 __float128 0f SECT 01 0000 [.text] SiBltShaderLibrary::GetVsType(BltInfo const*) const 000000000007ffb2 __float128 0f SECT 01 0000 [.text] AMDCISAMURBIChannel::getMetaClass() const 000000000007fff2 __float128 0f SECT 01 0000 [.text] AMDCISAMURBIChannel::MetaClass::alloc() const 000000000006a282 __float128 0f SECT 01 0000 [.text] AMDPitcairnHardware::getMetaClass() const 000000000006a2c2 __float128 0f SECT 01 0000 [.text] AMDPitcairnHardware::MetaClass::alloc() const 000000000002a0c2 __float128 0f SECT 01 0000 [.text] AMDSIDisplayMachine::getMetaClass() const 000000000002a102 __float128 0f SECT 01 0000 [.text] AMDSIDisplayMachine::MetaClass::alloc() const 000000000006aea2 __float128 0f SECT 01 0000 [.text] AMDSIHWAlignManager::getMetaClass() const 000000000006aee2 __float128 0f SECT 01 0000 [.text] AMDSIHWAlignManager::MetaClass::alloc() const 0000000000046e12 __float128 0f SECT 01 0000 [.text] AMDVIDisplayMachine::getMetaClass() const 0000000000046e52 __float128 0f SECT 01 0000 [.text] AMDVIDisplayMachine::MetaClass::alloc() const 0000000000092c22 __float128 0f SECT 01 0000 [.text] AMDVISAMURBIChannel::getMetaClass() const 0000000000092c62 __float128 0f SECT 01 0000 [.text] AMDVISAMURBIChannel::MetaClass::alloc() const 000000000006bee2 __float128 0f SECT 01 0000 [.text] AMDPitcairnPM4Engine::getMetaClass() const 000000000006bf22 __float128 0f SECT 01 0000 [.text] AMDPitcairnPM4Engine::MetaClass::alloc() const 0000000000080b32 __float128 0f SECT 01 0000 [.text] AMDCISAMUGPCOMChannel::getMetaClass() const 0000000000080b72 __float128 0f SECT 01 0000 [.text] AMDCISAMUGPCOMChannel::MetaClass::alloc() const 0000000000093442 __float128 0f SECT 01 0000 [.text] AMDVISAMUGPCOMChannel::getMetaClass() const 0000000000093482 __float128 0f SECT 01 0000 [.text] AMDVISAMUGPCOMChannel::MetaClass::alloc() const 0000000000083302 __float128 0f SECT 01 0000 [.text] AMDCIPM4ComputeChannel::getMetaClass() const 0000000000083342 __float128 0f SECT 01 0000 [.text] AMDCIPM4ComputeChannel::MetaClass::alloc() const 0000000000029ba2 __float128 0f SECT 01 0000 [.text] AMDSIAtomicBlitManager::getMetaClass() const 0000000000029f78 __float128 0f SECT 01 0000 [.text] AMDSIAtomicBlitManager::getBufferReuseThreshold(_UBM_ENGINE) const 0000000000029be2 __float128 0f SECT 01 0000 [.text] AMDSIAtomicBlitManager::MetaClass::alloc() const 0000000000074002 __float128 0f SECT 01 0000 [.text] AMDSIPM4ComputeChannel::getMetaClass() const 0000000000074042 __float128 0f SECT 01 0000 [.text] AMDSIPM4ComputeChannel::MetaClass::alloc() const 00000000000916c2 __float128 0f SECT 01 0000 [.text] AMDVIPM4ComputeChannel::getMetaClass() const 000000000009200e __float128 0f SECT 01 0000 [.text] AMDVIPM4ComputeChannel::writeSemaphoreCommand(unsigned int*, unsigned long long, bool) const 0000000000091702 __float128 0f SECT 01 0000 [.text] AMDVIPM4ComputeChannel::MetaClass::alloc() const 000000000007aae2 __float128 0f SECT 01 0000 [.text] AMDCIPM4CommandsUtility::getMetaClass() const 000000000007ab22 __float128 0f SECT 01 0000 [.text] AMDCIPM4CommandsUtility::MetaClass::alloc() const 0000000000058cf2 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHWVMM::getMetaClass() const 0000000000058d32 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHWVMM::MetaClass::alloc() const 0000000000128382 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDSIDRM::getMetaClass() const 00000000001283c2 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDSIDRM::MetaClass::alloc() const 0000000000128d62 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDSISPU::getMetaClass() const 0000000000128da2 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDSISPU::MetaClass::alloc() const 00000000001294a2 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDSIVCE::getMetaClass() const 00000000001294e2 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDSIVCE::MetaClass::alloc() const 000000000012b7f2 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDUVDVI::getMetaClass() const 000000000012b832 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDUVDVI::MetaClass::alloc() const 000000000012ba42 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDVIDRM::getMetaClass() const 000000000012ba82 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDVIDRM::MetaClass::alloc() const 000000000012c4b2 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDVISPU::getMetaClass() const 000000000012c4f2 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDVISPU::MetaClass::alloc() const 000000000012c742 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDVIVCE::getMetaClass() const 000000000012c782 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDVIVCE::MetaClass::alloc() const 000000000008efb2 __float128 0f SECT 01 0000 [.text] AMDVIPM4CommandsUtility::getMetaClass() const 000000000008eff2 __float128 0f SECT 01 0000 [.text] AMDVIPM4CommandsUtility::MetaClass::alloc() const 000000000003ceb2 __float128 0f SECT 01 0000 [.text] AMDCIGraphicsAccelerator::getMetaClass() const 000000000003cef2 __float128 0f SECT 01 0000 [.text] AMDCIGraphicsAccelerator::MetaClass::alloc() const 0000000000023142 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDBltMgr::getMetaClass() const 0000000000023182 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDBltMgr::MetaClass::alloc() const 0000000000129fe2 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDCIKDRM::getMetaClass() const 000000000012a022 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDCIKDRM::MetaClass::alloc() const 000000000012aa52 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDCIKSPU::getMetaClass() const 000000000012aa92 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDCIKSPU::MetaClass::alloc() const 000000000012b222 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDCIKVCE::getMetaClass() const 000000000012b262 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDCIKVCE::MetaClass::alloc() const 0000000000051362 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHWGart::getMetaClass() const 00000000000513a2 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHWGart::MetaClass::alloc() const 0000000000055c72 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHWRing::getMetaClass() const 0000000000055cb2 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHWRing::MetaClass::alloc() const 00000000001255a2 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDSMLDRM::getMetaClass() const 00000000001255e2 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDSMLDRM::MetaClass::alloc() const 0000000000125802 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDSMLSPU::getMetaClass() const 0000000000125842 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDSMLSPU::MetaClass::alloc() const 0000000000124d72 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDSMLUVD::getMetaClass() const 0000000000124db2 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDSMLUVD::MetaClass::alloc() const 0000000000125d12 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDSMLVCE::getMetaClass() const 0000000000125d52 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDSMLVCE::MetaClass::alloc() const 0000000000129b92 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDUVDCIK::getMetaClass() const 0000000000129bd2 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDUVDCIK::MetaClass::alloc() const 00000000000532b8 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_IAMDHWVMM::getMetaClass() const 00000000000532f8 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_IAMDHWVMM::MetaClass::alloc() const 0000000000028f32 __float128 0f SECT 01 0000 [.text] AMDSIGraphicsAccelerator::getMetaClass() const 0000000000028f72 __float128 0f SECT 01 0000 [.text] AMDSIGraphicsAccelerator::MetaClass::alloc() const 0000000000046712 __float128 0f SECT 01 0000 [.text] AMDVIGraphicsAccelerator::getMetaClass() const 0000000000046752 __float128 0f SECT 01 0000 [.text] AMDVIGraphicsAccelerator::MetaClass::alloc() const 0000000000059ab2 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDNULLVMM::getMetaClass() const 0000000000059af2 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDNULLVMM::MetaClass::alloc() const 0000000000052b0e __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_IAMDHWGart::getMetaClass() const 0000000000052b4e __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_IAMDHWGart::MetaClass::alloc() const 0000000000052be8 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_IAMDHWRing::getMetaClass() const 0000000000052c28 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_IAMDHWRing::MetaClass::alloc() const 000000000012404c __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_IAMDSMLDRM::getMetaClass() const 000000000012408c __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_IAMDSMLDRM::MetaClass::alloc() const 0000000000124146 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_IAMDSMLSPU::getMetaClass() const 0000000000124186 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_IAMDSMLSPU::MetaClass::alloc() const 0000000000123f52 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_IAMDSMLUVD::getMetaClass() const 0000000000123f92 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_IAMDSMLUVD::MetaClass::alloc() const 0000000000124240 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_IAMDSMLVCE::getMetaClass() const 0000000000124280 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_IAMDSMLVCE::MetaClass::alloc() const 0000000000024592 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_VendorGart::getMetaClass() const 00000000000245d2 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_VendorGart::MetaClass::alloc() const 00000000000506b2 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHWEngine::getMetaClass() const 00000000000506f2 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHWEngine::MetaClass::alloc() const 0000000000053b22 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHWMemory::getMetaClass() const 0000000000053b62 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHWMemory::MetaClass::alloc() const 0000000000059da2 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHardware::getMetaClass() const 0000000000059de2 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHardware::MetaClass::alloc() const 000000000001b88c __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDSPUEvent::getMetaClass() const 000000000001b8cc __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDSPUEvent::MetaClass::alloc() const 0000000000027352 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelTask::getMetaClass() const 0000000000027392 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelTask::MetaClass::alloc() const 00000000000488b2 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHWChannel::getMetaClass() const 00000000000488f2 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHWChannel::MetaClass::alloc() const 000000000004aa62 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHWDisplay::getMetaClass() const 000000000004aaa2 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHWDisplay::MetaClass::alloc() const 0000000000047de2 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHWHandler::getMetaClass() const 0000000000047e22 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHWHandler::MetaClass::alloc() const 0000000000024ab2 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHashTable::getMetaClass() const 0000000000024af2 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHashTable::MetaClass::alloc() const 00000000001259f2 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDSMLSPUMsg::getMetaClass() const 0000000000125a32 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDSMLSPUMsg::MetaClass::alloc() const 0000000000053104 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_IAMDHWEngine::getMetaClass() const 0000000000053144 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_IAMDHWEngine::MetaClass::alloc() const 0000000000052a34 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_IAMDHWMemory::getMetaClass() const 0000000000052a74 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_IAMDHWMemory::MetaClass::alloc() const 0000000000046b02 __float128 0f SECT 01 0000 [.text] AMDTongaGraphicsAccelerator::getMetaClass() const 0000000000046b42 __float128 0f SECT 01 0000 [.text] AMDTongaGraphicsAccelerator::MetaClass::alloc() const 0000000000029972 __float128 0f SECT 01 0000 [.text] AMDVerdeGraphicsAccelerator::getMetaClass() const 00000000000299b2 __float128 0f SECT 01 0000 [.text] AMDVerdeGraphicsAccelerator::MetaClass::alloc() const 000000000003d4d2 __float128 0f SECT 01 0000 [.text] AMDHawaiiGraphicsAccelerator::getMetaClass() const 000000000003d512 __float128 0f SECT 01 0000 [.text] AMDHawaiiGraphicsAccelerator::MetaClass::alloc() const 0000000000025152 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDLinkedList::getMetaClass() const 0000000000025192 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDLinkedList::MetaClass::alloc() const 000000000001bb48 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDSPUContext::getMetaClass() const 000000000001bb88 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDSPUContext::MetaClass::alloc() const 000000000001f1d2 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDTPTManager::getMetaClass() const 000000000001f212 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDTPTManager::MetaClass::alloc() const 00000000001280e2 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDUVDTrinity::getMetaClass() const 0000000000128122 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDUVDTrinity::MetaClass::alloc() const 00000000000531de __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_IAMDHWChannel::getMetaClass() const 000000000005321e __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_IAMDHWChannel::MetaClass::alloc() const 00000000000526cc __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_IAMDHWDisplay::getMetaClass() const 000000000005270c __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_IAMDHWDisplay::MetaClass::alloc() const 00000000000527a6 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_IAMDHWHandler::getMetaClass() const 00000000000527e6 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_IAMDHWHandler::MetaClass::alloc() const 0000000000029662 __float128 0f SECT 01 0000 [.text] AMDTahitiGraphicsAccelerator::getMetaClass() const 00000000000296a2 __float128 0f SECT 01 0000 [.text] AMDTahitiGraphicsAccelerator::MetaClass::alloc() const 000000000003d2a2 __float128 0f SECT 01 0000 [.text] AMDBonaireGraphicsAccelerator::getMetaClass() const 000000000003d2e2 __float128 0f SECT 01 0000 [.text] AMDBonaireGraphicsAccelerator::MetaClass::alloc() const 00000000000055d2 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelDevice::getMetaClass() const 0000000000005612 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelDevice::MetaClass::alloc() const 0000000000011a02 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelShared::getMetaClass() const 0000000000011a42 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelShared::MetaClass::alloc() const 000000000004f132 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDDMAHWEngine::getMetaClass() const 000000000004f172 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDDMAHWEngine::MetaClass::alloc() const 0000000000126eea __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDFPGenKeyMsg::getMetaClass() const 0000000000126f2a __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDFPGenKeyMsg::MetaClass::alloc() const 00000000000556c2 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHWRegisters::getMetaClass() const 0000000000055702 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHWRegisters::MetaClass::alloc() const 0000000000056812 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHWSemaphore::getMetaClass() const 0000000000056852 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHWSemaphore::MetaClass::alloc() const 000000000004e072 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHWUtilities::getMetaClass() const 000000000004e0b2 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHWUtilities::MetaClass::alloc() const 0000000000057d82 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHWVMContext::getMetaClass() const 0000000000057dc2 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHWVMContext::MetaClass::alloc() const 000000000005e892 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDPM4HWEngine::getMetaClass() const 000000000005e8d2 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDPM4HWEngine::MetaClass::alloc() const 000000000005f0e2 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDSPUHWEngine::getMetaClass() const 000000000005f122 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDSPUHWEngine::MetaClass::alloc() const 0000000000061102 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDUVDHWEngine::getMetaClass() const 0000000000061142 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDUVDHWEngine::MetaClass::alloc() const 000000000005fea2 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDVCEHWEngine::getMetaClass() const 000000000005fee2 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDVCEHWEngine::MetaClass::alloc() const 0000000000029352 __float128 0f SECT 01 0000 [.text] AMDPitcairnGraphicsAccelerator::getMetaClass() const 0000000000029392 __float128 0f SECT 01 0000 [.text] AMDPitcairnGraphicsAccelerator::MetaClass::alloc() const 0000000000004652 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelChannel::getMetaClass() const 0000000000004692 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelChannel::MetaClass::alloc() const 0000000000012992 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelSurface::getMetaClass() const 0000000000013708 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelSurface::setSyncCommand(unsigned int*, unsigned int&, unsigned int&, _AMDSurfaceSwapSyncOptions const&) const 00000000000129d2 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelSurface::MetaClass::alloc() const 000000000004ee72 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDDMAHWChannel::getMetaClass() const 000000000004eeb2 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDDMAHWChannel::MetaClass::alloc() const 000000000012774e __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDFPEncryptMsg::getMetaClass() const 000000000012778e __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDFPEncryptMsg::MetaClass::alloc() const 0000000000126c08 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDFPGetCertMsg::getMetaClass() const 0000000000126c48 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDFPGetCertMsg::MetaClass::alloc() const 0000000000127230 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDFPTestKeyMsg::getMetaClass() const 0000000000127270 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDFPTestKeyMsg::MetaClass::alloc() const 0000000000051072 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDNullHWEngine::getMetaClass() const 00000000000510b2 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDNullHWEngine::MetaClass::alloc() const 000000000005ecd2 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDPM4HWChannel::getMetaClass() const 000000000005edb8 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDPM4HWChannel::writeSemaphoreCommand(unsigned int*, unsigned long long, bool) const 000000000005ed12 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDPM4HWChannel::MetaClass::alloc() const 0000000000124642 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDSMLInterface::getMetaClass() const 0000000000124682 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDSMLInterface::MetaClass::alloc() const 000000000005fbf2 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDSPUHWChannel::getMetaClass() const 000000000005fc32 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDSPUHWChannel::MetaClass::alloc() const 000000000004e516 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDUVDHWChannel::getMetaClass() const 000000000004e556 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDUVDHWChannel::MetaClass::alloc() const 0000000000060df2 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDVCEHWChannel::getMetaClass() const 0000000000060e32 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDVCEHWChannel::MetaClass::alloc() const 00000000000525f2 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_IAMDHWInterface::getMetaClass() const 0000000000052632 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_IAMDHWInterface::MetaClass::alloc() const 000000000005295a __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_IAMDHWRegisters::getMetaClass() const 000000000005299a __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_IAMDHWRegisters::MetaClass::alloc() const 0000000000052cc2 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_IAMDHWSemaphore::getMetaClass() const 0000000000052d02 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_IAMDHWSemaphore::MetaClass::alloc() const 0000000000052f50 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_IAMDHWUtilities::getMetaClass() const 0000000000052f90 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_IAMDHWUtilities::MetaClass::alloc() const 0000000000053392 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_IAMDHWVMContext::getMetaClass() const 00000000000533d2 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_IAMDHWVMContext::MetaClass::alloc() const 000000000000bd50 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelResource::getRowBytes(unsigned int) const 000000000000a172 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelResource::getMetaClass() const 000000000000c4a4 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelResource::getRowPixels(unsigned int) const 000000000000bdea __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelResource::getSysRowBytes(unsigned int) const 000000000000bd6a __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelResource::getBufferOffset(unsigned int, unsigned int, unsigned int) const 000000000000c7a8 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelResource::getSysRowPixels(unsigned int) const 000000000000c4da __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelResource::getHeightAligned(unsigned int) const 000000000000c798 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelResource::getMaxMipmapLevel() const 000000000000be04 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelResource::getSysBufferOffset(unsigned int, unsigned int, unsigned int) const 000000000000c7f0 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelResource::getSysHeightAligned(unsigned int) const 000000000000c52e __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelResource::fillUBMSurfaceInfoBacking(_UBM_SURFINFO*, IOAccelMemoryMap*, unsigned int, unsigned int, unsigned int, bool*) const 000000000000c458 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelResource::getWidth(unsigned int) const 000000000000a1b2 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelResource::MetaClass::alloc() const 000000000000c47e __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelResource::getHeight(unsigned int) const 0000000000050372 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDNullHWChannel::getMetaClass() const 00000000000503b2 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDNullHWChannel::MetaClass::alloc() const 000000000001ad02 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDSPUAppContext::getMetaClass() const 000000000001ad42 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDSPUAppContext::MetaClass::alloc() const 000000000012431a __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_IAMDSMLInterface::getMetaClass() const 000000000012435a __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_IAMDSMLInterface::MetaClass::alloc() const 0000000000015fb2 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccel2DContext::getMetaClass() const 0000000000015ff2 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccel2DContext::MetaClass::alloc() const 0000000000026602 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelCLContext::getMetaClass() const 0000000000026642 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelCLContext::MetaClass::alloc() const 00000000000285c2 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelMemoryMap::getMetaClass() const 0000000000028602 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelMemoryMap::MetaClass::alloc() const 00000000000289aa __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelMemoryMap::getLength() const 0000000000027b82 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelSysMemory::getMetaClass() const 0000000000027bc2 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelSysMemory::MetaClass::alloc() const 0000000000027df2 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelVidMemory::getMetaClass() const 0000000000027e32 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelVidMemory::MetaClass::alloc() const 0000000000126968 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHDCPGetCertMsg::getMetaClass() const 00000000001269a8 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHDCPGetCertMsg::MetaClass::alloc() const 000000000004f5c2 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHWAlignManager::getMetaClass() const 000000000004f602 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHWAlignManager::MetaClass::alloc() const 0000000000127e02 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDSMLSIInterface::getMetaClass() const 0000000000127e42 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDSMLSIInterface::MetaClass::alloc() const 000000000012b512 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDSMLVIInterface::getMetaClass() const 000000000012b552 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDSMLVIInterface::MetaClass::alloc() const 0000000000012672 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelStatistics::getMetaClass() const 00000000000126b2 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelStatistics::MetaClass::alloc() const 000000000001a7c2 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelUVDContext::getMetaClass() const 000000000001a802 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelUVDContext::MetaClass::alloc() const 000000000001eab2 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelVCEContext::getMetaClass() const 000000000001eaf2 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelVCEContext::MetaClass::alloc() const 00000000000570d2 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHWSemaphorePool::getMetaClass() const 0000000000057112 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHWSemaphorePool::MetaClass::alloc() const 0000000000056e42 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDNullHWSemaphore::getMetaClass() const 0000000000056e82 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDNullHWSemaphore::MetaClass::alloc() const 00000000001298b2 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDSMLCIKInterface::getMetaClass() const 00000000001298f2 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDSMLCIKInterface::MetaClass::alloc() const 0000000000052880 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_IAMDHWAlignManager::getMetaClass() const 00000000000528c0 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_IAMDHWAlignManager::MetaClass::alloc() const 000000000012665a __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHDCPGetStatusMsg::getMetaClass() const 000000000012669a __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHDCPGetStatusMsg::MetaClass::alloc() const 0000000000052d9c __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_IAMDHWSemaphorePool::getMetaClass() const 0000000000052ddc __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_IAMDHWSemaphorePool::MetaClass::alloc() const 0000000000025d82 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_IAMDStatisticsGroup::getMetaClass() const 0000000000025dc2 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_IAMDStatisticsGroup::MetaClass::alloc() const 0000000000009542 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelEventMachine::getMetaClass() const 0000000000009582 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelEventMachine::MetaClass::alloc() const 0000000000017f2e __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelVideoContext::getMetaClass() const 0000000000017f6e __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelVideoContext::MetaClass::alloc() const 0000000000021afc __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAtomicBlitManager::getMetaClass() const 0000000000021b3c __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAtomicBlitManager::MetaClass::alloc() const 0000000000057882 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHWSemaphoreMemMgr::getMetaClass() const 00000000000578c2 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHWSemaphoreMemMgr::MetaClass::alloc() const 0000000000126132 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHDCPOpenSessionMsg::getMetaClass() const 0000000000126172 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHDCPOpenSessionMsg::MetaClass::alloc() const 000000000005e062 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDPM4CommandsUtility::getMetaClass() const 000000000005e0a2 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDPM4CommandsUtility::MetaClass::alloc() const 0000000000021a22 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_IAMDAtomicBlitManager::getMetaClass() const 0000000000021a62 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_IAMDAtomicBlitManager::MetaClass::alloc() const 0000000000052e76 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_IAMDHWSemaphoreMemMgr::getMetaClass() const 0000000000052eb6 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_IAMDHWSemaphoreMemMgr::MetaClass::alloc() const 0000000000025652 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_IAMDStatisticsManager::getMetaClass() const 0000000000025692 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_IAMDStatisticsManager::MetaClass::alloc() const 0000000000005982 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelDisplayMachine::getMetaClass() const 00000000000059c2 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelDisplayMachine::MetaClass::alloc() const 000000000012751c __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDFPReleaseSessionMsg::getMetaClass() const 000000000012755c __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDFPReleaseSessionMsg::MetaClass::alloc() const 0000000000001462 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDGraphicsAccelerator::getMetaClass() const 00000000000014a2 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDGraphicsAccelerator::MetaClass::alloc() const 0000000000126428 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHDCPCloseSessionMsg::getMetaClass() const 0000000000126468 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHDCPCloseSessionMsg::MetaClass::alloc() const 00000000000262e2 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHWChannelStatsGroup::getMetaClass() const 0000000000026322 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDHWChannelStatsGroup::MetaClass::alloc() const 000000000005302a __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_IAMDPM4CommandsUtility::getMetaClass() const 000000000005306a __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_IAMDPM4CommandsUtility::MetaClass::alloc() const 0000000000025e7c __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelStatisticsGroup::getMetaClass() const 0000000000025ebc __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelStatisticsGroup::MetaClass::alloc() const 0000000000016e52 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDInterruptEventSource::getMetaClass() const 0000000000016e92 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDInterruptEventSource::MetaClass::alloc() const 000000000001217c __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelSharedUserClient::getMetaClass() const 00000000000121bc __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelSharedUserClient::MetaClass::alloc() const 0000000000016c32 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelCommandBufferPool::getMetaClass() const 0000000000016c72 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelCommandBufferPool::MetaClass::alloc() const 000000000002574c __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelStatisticsManager::getMetaClass() const 000000000002578c __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDAccelStatisticsManager::MetaClass::alloc() const 000000000004e392 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDUVDInterruptEventSource::getMetaClass() const 000000000004e3d2 __float128 0f SECT 01 0000 [.text] AMDRadeonX4000_AMDUVDInterruptEventSource::MetaClass::alloc() const 000000000009deb2 __float128 0f SECT 01 0000 [.text] BltMgr::DebugPrint(char*, ...) const 000000000009900c __float128 0f SECT 01 0000 [.text] BltMgr::FreeSysMem(void*) const 000000000009d9dc __float128 0f SECT 01 0000 [.text] BltMgr::FreeVidMem(void*) const 000000000009da06 __float128 0f SECT 01 0000 [.text] BltMgr::LockVidMem(void*, LARGE_INTEGER) const 0000000000098f5c __float128 0f SECT 01 0000 [.text] BltMgr::AllocSysMem(unsigned int) const 000000000009a252 __float128 0f SECT 01 0000 [.text] BltMgr::IsBufferBlt(BltInfo const*) const 000000000009ff06 __float128 0f SECT 01 0000 [.text] BltMgr::IsTileMode1d(_UBM_SURFINFO const*) const 000000000009ff24 __float128 0f SECT 01 0000 [.text] BltMgr::IsTileMode2d(_UBM_SURFINFO const*) const 000000000009da42 __float128 0f SECT 01 0000 [.text] BltMgr::UnlockVidMem(void*) const 0000000000098f86 __float128 0f SECT 01 0000 [.text] BltMgr::GetSampleLocs(BltInfo const*, unsigned int, unsigned int*) const 000000000009db54 __float128 0f SECT 01 0000 [.text] BltMgr::VerifyCmdSpace(void*, unsigned int, unsigned int) const 000000000009ff42 __float128 0f SECT 01 0000 [.text] BltMgr::IsTileModeThick(_UBM_SURFINFO const*) const 000000000009fee8 __float128 0f SECT 01 0000 [.text] BltMgr::IsTileModeTiled(_UBM_SURFINFO const*) const 000000000009da74 __float128 0f SECT 01 0000 [.text] BltMgr::ReportDrawCount(void*, BltInfo*) const 000000000009fece __float128 0f SECT 01 0000 [.text] BltMgr::IsTileModeLinear(_UBM_SURFINFO const*) const 000000000009dbb0 __float128 0f SECT 01 0000 [.text] BltMgr::VerifyCmdSpaceEx(void*, unsigned int, unsigned int, _UBM_CMDBUF_STATE*) const 0000000000098e1c __float128 0f SECT 01 0000 [.text] BltMgr::NumColorFragments(_UBM_SURFINFO const*) const 000000000009a2e0 __float128 0f SECT 01 0000 [.text] BltMgr::OptimizeClipRects(BltInfo*) const 000000000009dab0 __float128 0f SECT 01 0000 [.text] BltMgr::NotifyPreambleAdded(void*, _UBM_PREAMBLE_TYPE) const 00000000000970d4 __float128 0f SECT 01 0000 [.text] BltMgr::FindUnknSampReplFrag(BltInfo*, unsigned int, _UBM_VECTORL*) const 000000000009de88 __float128 0f SECT 01 0000 [.text] BltMgr::GetCmdBufFreeEntries(void*) const 0000000000096cd2 __float128 0f SECT 01 0000 [.text] BltMgr::ComputeGridNormConsts(BltInfo*, int, unsigned int, unsigned int, _UBM_VECTOR*, _UBM_VECTOR*, _UBM_VECTOR*) const 000000000009b884 __float128 0f SECT 01 0000 [.text] BltMgr::IsLinearGeneralSurface(_UBM_SURFINFO const*) const 000000000009dac8 __float128 0f SECT 01 0000 [.text] BltMgr::CreateCriticalSectionLock(void**) const 000000000009bc54 __float128 0f SECT 01 0000 [.text] BltMgr::IsVerifyCmdSpaceExSupport() const 000000000009daf4 __float128 0f SECT 01 0000 [.text] BltMgr::DestroyCriticalSectionLock(void*) const 000000000009dc14 __float128 0f SECT 01 0000 [.text] BltMgr::Flush(void*) const 000000000009da58 __float128 0f SECT 01 0000 [.text] BltMgr::BltSync(void*, _UBM_BLTSYNC_INPUT const*) const 000000000009fdb8 __float128 0f SECT 01 0000 [.text] BltMgr::IsBuffer(_UBM_SURFINFO const*) const 00000000000d0578 __float128 0f SECT 01 0000 [.text] AddrLib::HwlGetPipes(_ADDR_TILEINFO const*) const 00000000000ce9f2 __float128 0f SECT 01 0000 [.text] AddrLib::GetTileIndex(_ADDR_GET_TILEINDEX_INPUT const*, _ADDR_GET_TILEINDEX_OUTPUT*) const 00000000000d06b2 __float128 0f SECT 01 0000 [.text] AddrLib::GetExportNorm(_ELEM_GETEXPORTNORM_INPUT const*) const 00000000000d01be __float128 0f SECT 01 0000 [.text] AddrLib::PadDimensions(_AddrTileMode, unsigned int, _ADDR_SURFACE_FLAGS, unsigned int, _ADDR_TILEINFO*, unsigned int, unsigned int, unsigned int*, unsigned int, unsigned int*, unsigned int, unsigned int*, unsigned int) const 00000000000ceff0 __float128 0f SECT 01 0000 [.text] AddrLib::ComputeDccInfo(_ADDR_COMPUTE_DCCINFO_INPUT const*, _ADDR_COMPUTE_DCCINFO_OUTPUT*) const 00000000000d06da __float128 0f SECT 01 0000 [.text] AddrLib::ComputePrtInfo(_ADDR_PRT_INFO_INPUT const*, _ADDR_PRT_INFO_OUTPUT*) const 00000000000cdf80 __float128 0f SECT 01 0000 [.text] AddrLib::ComputeMipLevel(_ADDR_COMPUTE_SURFACE_INFO_INPUT*) const 00000000000d056c __float128 0f SECT 01 0000 [.text] AddrLib::HwlSetupTileCfg(int, int, _ADDR_TILEINFO*, _AddrTileMode*, _AddrTileType*) const 00000000000cee14 __float128 0f SECT 01 0000 [.text] AddrLib::ComputeCmaskInfo(_ADDR_CMASK_FLAGS, unsigned int, unsigned int, unsigned int, int, _ADDR_TILEINFO*, unsigned int*, unsigned int*, unsigned long long*, unsigned int*, unsigned int*, unsigned long long*, unsigned int*, unsigned int*) const 00000000000ced00 __float128 0f SECT 01 0000 [.text] AddrLib::ComputeCmaskInfo(_ADDR_COMPUTE_CMASKINFO_INPUT const*, _ADDR_COMPUTE_CMASK_INFO_OUTPUT*) const 00000000000ceb62 __float128 0f SECT 01 0000 [.text] AddrLib::ComputeHtileInfo(_ADDR_HTILE_FLAGS, unsigned int, unsigned int, unsigned int, int, int, int, _ADDR_TILEINFO*, unsigned int*, unsigned int*, unsigned long long*, unsigned int*, unsigned int*, unsigned long long*, unsigned int*) const 00000000000cea1a __float128 0f SECT 01 0000 [.text] AddrLib::ComputeHtileInfo(_ADDR_COMPUTE_HTILE_INFO_INPUT const*, _ADDR_COMPUTE_HTILE_INFO_OUTPUT*) const 00000000000ce88a __float128 0f SECT 01 0000 [.text] AddrLib::ConvertTileIndex(_ADDR_CONVERT_TILEINDEX_INPUT const*, _ADDR_CONVERT_TILEINDEX_OUTPUT*) const 00000000000ce098 __float128 0f SECT 01 0000 [.text] AddrLib::DegradeBaseLevel(_ADDR_COMPUTE_SURFACE_INFO_INPUT const*, _AddrTileMode*) const 00000000000cf5ec __float128 0f SECT 01 0000 [.text] AddrLib::ComputeCmaskBytes(unsigned int, unsigned int, unsigned int) const 00000000000ce930 __float128 0f SECT 01 0000 [.text] AddrLib::ConvertTileIndex1(_ADDR_CONVERT_TILEINDEX1_INPUT const*, _ADDR_CONVERT_TILEINDEX_OUTPUT*) const 00000000000d0674 __float128 0f SECT 01 0000 [.text] AddrLib::Flt32ToColorPixel(_ELEM_FLT32TOCOLORPIXEL_INPUT const*, _ELEM_FLT32TOCOLORPIXEL_OUTPUT*) const 00000000000d05ce __float128 0f SECT 01 0000 [.text] AddrLib::Flt32ToDepthPixel(_ELEM_FLT32TODEPTHPIXEL_INPUT const*, _ELEM_FLT32TODEPTHPIXEL_OUTPUT*) const 00000000000ce57e __float128 0f SECT 01 0000 [.text] AddrLib::ComputeBaseSwizzle(_ADDR_COMPUTE_BASE_SWIZZLE_INPUT const*, _ADDR_COMPUTE_BASE_SWIZZLE_OUTPUT*) const 00000000000cdb8c __float128 0f SECT 01 0000 [.text] AddrLib::ComputeSurfaceInfo(_ADDR_COMPUTE_SURFACE_INFO_INPUT const*, _ADDR_COMPUTE_SURFACE_INFO_OUTPUT*) const 00000000000cf8f2 __float128 0f SECT 01 0000 [.text] AddrLib::ComputePipeFromAddr(unsigned long long, unsigned long long) const 00000000000d0582 __float128 0f SECT 01 0000 [.text] AddrLib::ComputeQbStereoInfo(_ADDR_COMPUTE_SURFACE_INFO_OUTPUT*) const 00000000000ce7fc __float128 0f SECT 01 0000 [.text] AddrLib::ConvertTileInfoToHW(_ADDR_CONVERT_TILEINFOTOHW_INPUT const*, _ADDR_CONVERT_TILEINFOTOHW_OUTPUT*) const 00000000000cdfce __float128 0f SECT 01 0000 [.text] AddrLib::PostComputeMipLevel(_ADDR_COMPUTE_SURFACE_INFO_INPUT*, _ADDR_COMPUTE_SURFACE_INFO_OUTPUT*) const 00000000000d0188 __float128 0f SECT 01 0000 [.text] AddrLib::AdjustPitchAlignment(_ADDR_SURFACE_FLAGS, unsigned int*) const 00000000000cf5ae __float128 0f SECT 01 0000 [.text] AddrLib::ComputeCmaskBaseAlign(_ADDR_CMASK_FLAGS, _ADDR_TILEINFO*) const 00000000000d04aa __float128 0f SECT 01 0000 [.text] AddrLib::DegradeLargeThickTile(_AddrTileMode, unsigned int) const 00000000000ce4bc __float128 0f SECT 01 0000 [.text] AddrLib::CombineBankPipeSwizzle(_ADDR_COMBINE_BANKPIPE_SWIZZLE_INPUT const*, _ADDR_COMBINE_BANKPIPE_SWIZZLE_OUTPUT*) const 00000000000ce434 __float128 0f SECT 01 0000 [.text] AddrLib::ExtractBankPipeSwizzle(_ADDR_EXTRACT_BANKPIPE_SWIZZLE_INPUT const*, _ADDR_EXTRACT_BANKPIPE_SWIZZLE_OUTPUT*) const 00000000000ce39a __float128 0f SECT 01 0000 [.text] AddrLib::ComputeSliceTileSwizzle(_ADDR_COMPUTE_SLICESWIZZLE_INPUT const*, _ADDR_COMPUTE_SLICESWIZZLE_OUTPUT*) const 00000000000cf316 __float128 0f SECT 01 0000 [.text] AddrLib::ComputeCmaskAddrFromCoord(_ADDR_COMPUTE_CMASK_ADDRFROMCOORD_INPUT const*, _ADDR_COMPUTE_CMASK_ADDRFROMCOORD_OUTPUT*) const 00000000000cf416 __float128 0f SECT 01 0000 [.text] AddrLib::ComputeCmaskCoordFromAddr(_ADDR_COMPUTE_CMASK_COORDFROMADDR_INPUT const*, _ADDR_COMPUTE_CMASK_COORDFROMADDR_OUTPUT*) const 00000000000ce79c __float128 0f SECT 01 0000 [.text] AddrLib::ComputeFmaskAddrFromCoord(_ADDR_COMPUTE_FMASK_ADDRFROMCOORD_INPUT const*, _ADDR_COMPUTE_FMASK_ADDRFROMCOORD_OUTPUT*) const 00000000000ce7cc __float128 0f SECT 01 0000 [.text] AddrLib::ComputeFmaskCoordFromAddr(_ADDR_COMPUTE_FMASK_COORDFROMADDR_INPUT const*, _ADDR_COMPUTE_FMASK_COORDFROMADDR_OUTPUT*) const 00000000000cf0a4 __float128 0f SECT 01 0000 [.text] AddrLib::ComputeHtileAddrFromCoord(_ADDR_COMPUTE_HTILE_ADDRFROMCOORD_INPUT const*, _ADDR_COMPUTE_HTILE_ADDRFROMCOORD_OUTPUT*) const 00000000000cf1d8 __float128 0f SECT 01 0000 [.text] AddrLib::ComputeHtileCoordFromAddr(_ADDR_COMPUTE_HTILE_COORDFROMADDR_INPUT const*, _ADDR_COMPUTE_HTILE_COORDFROMADDR_OUTPUT*) const 00000000000cf60c __float128 0f SECT 01 0000 [.text] AddrLib::ComputeXmaskCoordYFromPipe(unsigned int, unsigned int) const 00000000000d0310 __float128 0f SECT 01 0000 [.text] AddrLib::HwlPreHandleBaseLvl3xPitch(_ADDR_COMPUTE_SURFACE_INFO_INPUT const*, unsigned int) const 00000000000ce18c __float128 0f SECT 01 0000 [.text] AddrLib::ComputeSurfaceAddrFromCoord(_ADDR_COMPUTE_SURFACE_ADDRFROMCOORD_INPUT const*, _ADDR_COMPUTE_SURFACE_ADDRFROMCOORD_OUTPUT*) const 00000000000ce29c __float128 0f SECT 01 0000 [.text] AddrLib::ComputeSurfaceCoordFromAddr(_ADDR_COMPUTE_SURFACE_COORDFROMADDR_INPUT const*, _ADDR_COMPUTE_SURFACE_COORDFROMADDR_OUTPUT*) const 00000000000d035c __float128 0f SECT 01 0000 [.text] AddrLib::HwlPostHandleBaseLvl3xPitch(_ADDR_COMPUTE_SURFACE_INFO_INPUT const*, unsigned int) const 00000000000cf91a __float128 0f SECT 01 0000 [.text] AddrLib::HwlComputeXmaskAddrFromCoord(unsigned int, unsigned int, unsigned int, unsigned int, unsigned int, unsigned int, unsigned int, int, int, int, _ADDR_TILEINFO*, unsigned int*) const 00000000000cf64e __float128 0f SECT 01 0000 [.text] AddrLib::HwlComputeXmaskCoordFromAddr(unsigned long long, unsigned int, unsigned int, unsigned int, unsigned int, unsigned int, int, int, int, _ADDR_TILEINFO*, unsigned int*, unsigned int*, unsigned int*) const 00000000000cf530 __float128 0f SECT 01 0000 [.text] AddrLib::ComputeTileDataWidthAndHeight(unsigned int, unsigned int, _ADDR_TILEINFO*, unsigned int*, unsigned int*) const 00000000000cfe10 __float128 0f SECT 01 0000 [.text] AddrLib::ComputePixelIndexWithinMicroTile(unsigned int, unsigned int, unsigned int, unsigned int, _AddrTileMode, _AddrTileType) const 00000000000cfc28 __float128 0f SECT 01 0000 [.text] AddrLib::ComputeSurfaceAddrFromCoordLinear(unsigned int, unsigned int, unsigned int, unsigned int, unsigned int, unsigned int, unsigned int, unsigned int, unsigned int*) const 00000000000cfc64 __float128 0f SECT 01 0000 [.text] AddrLib::ComputeSurfaceCoordFromAddrLinear(unsigned long long, unsigned int, unsigned int, unsigned int, unsigned int, unsigned int, unsigned int*, unsigned int*, unsigned int*, unsigned int*) const 00000000000cfcc0 __float128 0f SECT 01 0000 [.text] AddrLib::ComputeSurfaceCoordFromAddrMicroTiled(unsigned long long, unsigned int, unsigned int, unsigned int, unsigned int, unsigned int, _AddrTileMode, unsigned int, unsigned int, unsigned int*, unsigned int*, unsigned int*, unsigned int*, _AddrTileType, int) const 00000000000cf590 __float128 0f SECT 01 0000 [.text] AddrLib::HwlComputeTileDataWidthAndHeightLinear(unsigned int*, unsigned int*, unsigned int, _ADDR_TILEINFO*) const 0000000000066682 __float128 0f SECT 01 0000 [.text] AMDSIVMM::getMetaClass() const 00000000000666c2 __float128 0f SECT 01 0000 [.text] AMDSIVMM::MetaClass::alloc() const 00000000000892b2 __float128 0f SECT 01 0000 [.text] AMDVIVMM::getMetaClass() const 00000000000892f2 __float128 0f SECT 01 0000 [.text] AMDVIVMM::MetaClass::alloc() const 00000000000baa20 __float128 0f SECT 01 0000 [.text] SiBltMgr::HwlRenderWithDB(_UBM_SURFINFO const*) const 00000000000b5d7a __float128 0f SECT 01 0000 [.text] SiBltMgr::ShouldEnableGamma(BltInfo const*) const 00000000000b76ca __float128 0f SECT 01 0000 [.text] SiBltMgr::SizeWriteVgtEvent() const 00000000000bb454 __float128 0f SECT 01 0000 [.text] SiBltMgr::ClientSyncCpDmaBlt(BltInfo const*) const 00000000000ba950 __float128 0f SECT 01 0000 [.text] SiBltMgr::HwlCanUseCBResolve(_UBM_SURFINFO const*, _UBM_SURFINFO const*) const 00000000000b5d50 __float128 0f SECT 01 0000 [.text] SiBltMgr::HwlSetTilingParams(_UBM_SURFINFO*, _UBM_TILE_MODE, _UBM_TILE_TYPE, unsigned int) const 00000000000b9e8a __float128 0f SECT 01 0000 [.text] SiBltMgr::ClientSync3dDrawBlt(BltInfo const*) const 00000000000cbdf0 __float128 0f SECT 01 0000 [.text] SiBltMgr::ClientSyncDrmDmaBlt(BltInfo const*) const 00000000000b5af0 __float128 0f SECT 01 0000 [.text] SiBltMgr::GetFMaskBitsPerIndex(_UBM_SURFINFO const*) const 00000000000b6830 __float128 0f SECT 01 0000 [.text] SiBltMgr::ClientSync3dDispatchBlt(BltInfo const*) const 00000000000ba8aa __float128 0f SECT 01 0000 [.text] SiBltMgr::ComputeNumClipRectEntries(BltInfo const*) const 00000000000b76b2 __float128 0f SECT 01 0000 [.text] SiBltMgr::Compute3dDrawPreBltSyncEntries(BltInfo const*) const 00000000000b76be __float128 0f SECT 01 0000 [.text] SiBltMgr::Compute3dDrawPostBltSyncEntries(BltInfo const*) const 00000000000a2e52 __float128 0f SECT 01 0000 [.text] BltResFmt::GetResInfo(_UBM_FORMAT, unsigned int) const 00000000000a6f40 __float128 0f SECT 01 0000 [.text] BltResFmt::ConvertFrom(_UBM_FORMAT, void const*, unsigned int, _UBM_VECTOR*, unsigned int) const 00000000000a68e4 __float128 0f SECT 01 0000 [.text] BltResFmt::BytesPerPixel(_UBM_FORMAT, unsigned int) const 00000000000a6c50 __float128 0f SECT 01 0000 [.text] BltResFmt::CompBitCountMax(_UBM_FORMAT) const 00000000000a6b20 __float128 0f SECT 01 0000 [.text] BltResFmt::ConvertFormatForCopy(_UBM_FORMAT) const 00000000000a6d30 __float128 0f SECT 01 0000 [.text] BltResFmt::ConvertTo(_UBM_FORMAT, _UBM_VECTOR const*, unsigned int, void*, unsigned int, unsigned int) const 00000000000d6abc __float128 0f SECT 01 0000 [.text] CIAddrLib::ReadGbTileMode(unsigned int, ADDR_TILECONFIG*) const 00000000000d632a __float128 0f SECT 01 0000 [.text] CIAddrLib::HwlSetupTileCfg(int, int, _ADDR_TILEINFO*, _AddrTileMode*, _AddrTileType*) const 00000000000d6ede __float128 0f SECT 01 0000 [.text] CIAddrLib::HwlPadDimensions(_AddrTileMode, unsigned int, _ADDR_SURFACE_FLAGS, unsigned int, _ADDR_TILEINFO*, unsigned int, unsigned int, unsigned int*, unsigned int, unsigned int*, unsigned int, unsigned int*, unsigned int) const 00000000000d6700 __float128 0f SECT 01 0000 [.text] CIAddrLib::HwlSetupTileInfo(_AddrTileMode, _ADDR_SURFACE_FLAGS, unsigned int, unsigned int, unsigned int, unsigned int, _ADDR_TILEINFO*, _ADDR_TILEINFO*, _AddrTileType, _ADDR_COMPUTE_SURFACE_INFO_OUTPUT*) const 00000000000d5b2e __float128 0f SECT 01 0000 [.text] CIAddrLib::HwlComputeDccInfo(_ADDR_COMPUTE_DCCINFO_INPUT const*, _ADDR_COMPUTE_DCCINFO_OUTPUT*) const 00000000000d6be8 __float128 0f SECT 01 0000 [.text] CIAddrLib::ReadGbMacroTileCfg(unsigned int, _ADDR_TILEINFO*) const 00000000000d65f0 __float128 0f SECT 01 0000 [.text] CIAddrLib::HwlOverrideTileMode(_ADDR_COMPUTE_SURFACE_INFO_INPUT const*, _AddrTileMode*, _AddrTileType*) const 00000000000d6414 __float128 0f SECT 01 0000 [.text] CIAddrLib::HwlComputeSurfaceInfo(_ADDR_COMPUTE_SURFACE_INFO_INPUT const*, _ADDR_COMPUTE_SURFACE_INFO_OUTPUT*) const 00000000000d624c __float128 0f SECT 01 0000 [.text] CIAddrLib::HwlPostCheckTileIndex(_ADDR_TILEINFO const*, _AddrTileMode, _AddrTileType, int) const 00000000000d65e8 __float128 0f SECT 01 0000 [.text] CIAddrLib::HwlDegradeThickTileMode(_AddrTileMode, unsigned int, unsigned int*) const 00000000000d6c3a __float128 0f SECT 01 0000 [.text] CIAddrLib::HwlComputeMacroModeIndex(int, _ADDR_SURFACE_FLAGS, unsigned int, unsigned int, _ADDR_TILEINFO*, _AddrTileMode*, _AddrTileType*) const 00000000000d65c2 __float128 0f SECT 01 0000 [.text] CIAddrLib::HwlFmaskPreThunkSurfInfo(_ADDR_COMPUTE_FMASK_INFO_INPUT const*, _ADDR_COMPUTE_FMASK_INFO_OUTPUT const*, _ADDR_COMPUTE_SURFACE_INFO_INPUT*, _ADDR_COMPUTE_SURFACE_INFO_OUTPUT*) const 00000000000d65d6 __float128 0f SECT 01 0000 [.text] CIAddrLib::HwlFmaskPostThunkSurfInfo(_ADDR_COMPUTE_SURFACE_INFO_OUTPUT const*, _ADDR_COMPUTE_FMASK_INFO_OUTPUT*) const 00000000000d5c70 __float128 0f SECT 01 0000 [.text] CIAddrLib::HwlComputeCmaskAddrFromCoord(_ADDR_COMPUTE_CMASK_ADDRFROMCOORD_INPUT const*, _ADDR_COMPUTE_CMASK_ADDRFROMCOORD_OUTPUT*) const 00000000000d5d1e __float128 0f SECT 01 0000 [.text] CIAddrLib::HwlComputeMetadataNibbleAddress(unsigned long long, unsigned long long, unsigned long long, unsigned int, unsigned int, unsigned int, unsigned int, unsigned int, unsigned int, unsigned int) const 00000000000d6e2e __float128 0f SECT 01 0000 [.text] CIAddrLib::HwlStereoCheckRightOffsetPadding() const 00000000000d6e06 __float128 0f SECT 01 0000 [.text] CIAddrLib::HwlComputeTileDataWidthAndHeightLinear(unsigned int*, unsigned int*, unsigned int, _ADDR_TILEINFO*) const 00000000000d35b4 __float128 0f SECT 01 0000 [.text] SIAddrLib::HwlGetPipes(_ADDR_TILEINFO const*) const 00000000000d3640 __float128 0f SECT 01 0000 [.text] SIAddrLib::GetPipePerSurf(_AddrPipeCfg) const 00000000000d559c __float128 0f SECT 01 0000 [.text] SIAddrLib::GetTileSetting(unsigned int) const 00000000000d57a6 __float128 0f SECT 01 0000 [.text] SIAddrLib::ReadGbTileMode(unsigned int, ADDR_TILECONFIG*) const 00000000000d5840 __float128 0f SECT 01 0000 [.text] SIAddrLib::HwlGetTileIndex(_ADDR_GET_TILEINDEX_INPUT const*, _ADDR_GET_TILEINDEX_OUTPUT*) const 00000000000d56ac __float128 0f SECT 01 0000 [.text] SIAddrLib::HwlSetupTileCfg(int, int, _ADDR_TILEINFO*, _AddrTileMode*, _AddrTileType*) const 00000000000d540c __float128 0f SECT 01 0000 [.text] SIAddrLib::HwlPreAdjustBank(unsigned int, unsigned int, _ADDR_TILEINFO*) const 00000000000d49a6 __float128 0f SECT 01 0000 [.text] SIAddrLib::HwlSetupTileInfo(_AddrTileMode, _ADDR_SURFACE_FLAGS, unsigned int, unsigned int, unsigned int, unsigned int, _ADDR_TILEINFO*, _ADDR_TILEINFO*, _AddrTileType, _ADDR_COMPUTE_SURFACE_INFO_OUTPUT*) const 00000000000d557e __float128 0f SECT 01 0000 [.text] SIAddrLib::HwlTileInfoEqual(_ADDR_TILEINFO const*, _ADDR_TILEINFO const*) const 00000000000d5452 __float128 0f SECT 01 0000 [.text] SIAddrLib::HwlComputeMipLevel(_ADDR_COMPUTE_SURFACE_INFO_INPUT*) const 00000000000d588e __float128 0f SECT 01 0000 [.text] SIAddrLib::HwlComputeFmaskBits(_ADDR_COMPUTE_FMASK_INFO_INPUT const*, unsigned int*) const 00000000000d5948 __float128 0f SECT 01 0000 [.text] SIAddrLib::HwlOverrideTileMode(_ADDR_COMPUTE_SURFACE_INFO_INPUT const*, _AddrTileMode*, _AddrTileType*) const 00000000000d36c4 __float128 0f SECT 01 0000 [.text] SIAddrLib::ComputePipeFromCoord(unsigned int, unsigned int, unsigned int, _AddrTileMode, unsigned int, int, _ADDR_TILEINFO*) const 00000000000d4138 __float128 0f SECT 01 0000 [.text] SIAddrLib::HwlComputeHtileBytes(unsigned int, unsigned int, unsigned int, int, unsigned int, unsigned long long*, unsigned int) const 00000000000d543c __float128 0f SECT 01 0000 [.text] SIAddrLib::HwlComputeSurfaceInfo(_ADDR_COMPUTE_SURFACE_INFO_INPUT const*, _ADDR_COMPUTE_SURFACE_INFO_OUTPUT*) const 00000000000d55ae __float128 0f SECT 01 0000 [.text] SIAddrLib::HwlPostCheckTileIndex(_ADDR_TILEINFO const*, _AddrTileMode, _AddrTileType, int) const 00000000000d4fc2 __float128 0f SECT 01 0000 [.text] SIAddrLib::HwlConvertTileInfoToHW(_ADDR_CONVERT_TILEINFOTOHW_INPUT const*, _ADDR_CONVERT_TILEINFOTOHW_OUTPUT*) const 00000000000d556c __float128 0f SECT 01 0000 [.text] SIAddrLib::HwlDegradeThickTileMode(_AddrTileMode, unsigned int, unsigned int*) const 00000000000d586e __float128 0f SECT 01 0000 [.text] SIAddrLib::HwlFmaskPreThunkSurfInfo(_ADDR_COMPUTE_FMASK_INFO_INPUT const*, _ADDR_COMPUTE_FMASK_INFO_OUTPUT const*, _ADDR_COMPUTE_SURFACE_INFO_INPUT*, _ADDR_COMPUTE_SURFACE_INFO_OUTPUT*) const 00000000000d548e __float128 0f SECT 01 0000 [.text] SIAddrLib::HwlCheckLastMacroTiledLvl(_ADDR_COMPUTE_SURFACE_INFO_INPUT const*, _ADDR_COMPUTE_SURFACE_INFO_OUTPUT*) const 00000000000d587a __float128 0f SECT 01 0000 [.text] SIAddrLib::HwlFmaskPostThunkSurfInfo(_ADDR_COMPUTE_SURFACE_INFO_OUTPUT const*, _ADDR_COMPUTE_FMASK_INFO_OUTPUT*) const 00000000000d473e __float128 0f SECT 01 0000 [.text] SIAddrLib::HwlGetPitchAlignmentLinear(unsigned int, _ADDR_SURFACE_FLAGS) const 00000000000d4782 __float128 0f SECT 01 0000 [.text] SIAddrLib::HwlGetSizeAdjustmentLinear(_AddrTileMode, unsigned int, unsigned int, unsigned int, unsigned int, unsigned int*, unsigned int*, unsigned int*) const 00000000000d4824 __float128 0f SECT 01 0000 [.text] SIAddrLib::HwlPreHandleBaseLvl3xPitch(_ADDR_COMPUTE_SURFACE_INFO_INPUT const*, unsigned int) const 00000000000d484a __float128 0f SECT 01 0000 [.text] SIAddrLib::HwlPostHandleBaseLvl3xPitch(_ADDR_COMPUTE_SURFACE_INFO_INPUT const*, unsigned int) const 00000000000d3fb4 __float128 0f SECT 01 0000 [.text] SIAddrLib::TileCoordToMaskElementIndex(unsigned int, unsigned int, _AddrPipeCfg, unsigned int*, unsigned int*) const 00000000000d4142 __float128 0f SECT 01 0000 [.text] SIAddrLib::HwlComputeXmaskAddrFromCoord(unsigned int, unsigned int, unsigned int, unsigned int, unsigned int, unsigned int, unsigned int, int, int, int, _ADDR_TILEINFO*, unsigned int*) const 00000000000d4406 __float128 0f SECT 01 0000 [.text] SIAddrLib::HwlComputeXmaskCoordFromAddr(unsigned long long, unsigned int, unsigned int, unsigned int, unsigned int, unsigned int, int, int, int, _ADDR_TILEINFO*, unsigned int*, unsigned int*, unsigned int*) const 00000000000d500e __float128 0f SECT 01 0000 [.text] SIAddrLib::HwlComputeXmaskCoordYFrom8Pipe(unsigned int, unsigned int) const 00000000000d4870 __float128 0f SECT 01 0000 [.text] SIAddrLib::HwlGetPitchAlignmentMicroTiled(_AddrTileMode, unsigned int, _ADDR_SURFACE_FLAGS, unsigned int) const 00000000000d488e __float128 0f SECT 01 0000 [.text] SIAddrLib::HwlGetSizeAdjustmentMicroTiled(unsigned int, unsigned int, _ADDR_SURFACE_FLAGS, unsigned int, unsigned int, unsigned int, unsigned int*, unsigned int*) const 00000000000d3998 __float128 0f SECT 01 0000 [.text] SIAddrLib::ComputeTileCoordFromPipeAndElemIdx(unsigned int, unsigned int, _AddrPipeCfg, unsigned int, unsigned int, unsigned int, unsigned int*, unsigned int*) const 00000000000d5016 __float128 0f SECT 01 0000 [.text] SIAddrLib::HwlComputeSurfaceCoord2DFromBankPipe(_AddrTileMode, unsigned int*, unsigned int*, unsigned int, unsigned int, unsigned int, unsigned int, unsigned int, unsigned int, int, _ADDR_TILEINFO*) const 00000000000d4110 __float128 0f SECT 01 0000 [.text] SIAddrLib::HwlComputeTileDataWidthAndHeightLinear(unsigned int*, unsigned int*, unsigned int, _ADDR_TILEINFO*) const 00000000003be550 __float128 0f SECT 08 0000 [.const_data] vtable for AddrObject 00000000003bdc90 __float128 0f SECT 08 0000 [.const_data] vtable for AuxSurfMgr 00000000003b9910 __float128 0f SECT 08 0000 [.const_data] vtable for AMDVIHWGart 00000000003be6e0 __float128 0f SECT 08 0000 [.const_data] vtable for AddrElemLib 00000000003be710 __float128 0f SECT 08 0000 [.const_data] vtable for R800AddrLib 00000000003be1c0 __float128 0f SECT 08 0000 [.const_data] vtable for SiBltDevice 00000000003be360 __float128 0f SECT 08 0000 [.const_data] vtable for SiBltResFmt 00000000003be390 __float128 0f SECT 08 0000 [.const_data] vtable for SiBltShader 00000000003b4970 __float128 0f SECT 08 0000 [.const_data] vtable for AMDCIDisplay 00000000003b7d60 __float128 0f SECT 08 0000 [.const_data] vtable for AMDCIVCERing 00000000003af220 __float128 0f SECT 08 0000 [.const_data] vtable for AMDSIDMARing 00000000003aaa00 __float128 0f SECT 08 0000 [.const_data] vtable for AMDSIDisplay 00000000003b19e0 __float128 0f SECT 08 0000 [.const_data] vtable for AMDSISPURing 0000000000397700 __float128 0f SECT 08 0000 [.const_data] vtable for AMDSISurface 00000000003b0f40 __float128 0f SECT 08 0000 [.const_data] vtable for AMDSIUVDRing 00000000003b00a0 __float128 0f SECT 08 0000 [.const_data] vtable for AMDSIVCERing 00000000003ba550 __float128 0f SECT 08 0000 [.const_data] vtable for AMDVIDisplay 00000000003b4df0 __float128 0f SECT 08 0000 [.const_data] vtable for AMDCIHWMemory 00000000003b2420 __float128 0f SECT 08 0000 [.const_data] vtable for AMDCIHardware 000000000039d0e0 __float128 0f SECT 08 0000 [.const_data] vtable for AMDCIResource 00000000003b4390 __float128 0f SECT 08 0000 [.const_data] vtable for AMDCIsDMARing 00000000003aa680 __float128 0f SECT 08 0000 [.const_data] vtable for AMDSIHWMemory 00000000003ab6c0 __float128 0f SECT 08 0000 [.const_data] vtable for AMDSIHardware 00000000003972c0 __float128 0f SECT 08 0000 [.const_data] vtable for AMDSIResource 00000000003b9bf0 __float128 0f SECT 08 0000 [.const_data] vtable for AMDVIHWMemory 00000000003b8ab0 __float128 0f SECT 08 0000 [.const_data] vtable for AMDVIHardware 00000000003a0370 __float128 0f SECT 08 0000 [.const_data] vtable for AMDVIResource 00000000003bb370 __float128 0f SECT 08 0000 [.const_data] vtable for AMDVIsDMARing 00000000003be030 __float128 0f SECT 08 0000 [.const_data] vtable for SurfAttribute 000000000039d5b0 __float128 0f SECT 08 0000 [.const_data] vtable for AMDCICLContext 00000000003b39b0 __float128 0f SECT 08 0000 [.const_data] vtable for AMDCIPM4Engine 000000000039a180 __float128 0f SECT 08 0000 [.const_data] vtable for AMDSICLContext 00000000003aeaf0 __float128 0f SECT 08 0000 [.const_data] vtable for AMDSIDMAEngine 0000000000399470 __float128 0f SECT 08 0000 [.const_data] vtable for AMDSIGLContext 00000000003ad660 __float128 0f SECT 08 0000 [.const_data] vtable for AMDSIPM4Engine 00000000003b1260 __float128 0f SECT 08 0000 [.const_data] vtable for AMDSISPUEngine 00000000003ab0e0 __float128 0f SECT 08 0000 [.const_data] vtable for AMDSIVMContext 00000000003bc3a0 __float128 0f SECT 08 0000 [.const_data] vtable for AMDVIPM4Engine 00000000003b9f70 __float128 0f SECT 08 0000 [.const_data] vtable for AMDVIVMContext 00000000003becb0 __float128 0f SECT 08 0000 [.const_data] vtable for EgBasedAddrLib 00000000003b57f0 __float128 0f SECT 08 0000 [.const_data] vtable for AMDCIDMAChannel 00000000003b53e0 __float128 0f SECT 08 0000 [.const_data] vtable for AMDCIPM4Channel 00000000003b5bf0 __float128 0f SECT 08 0000 [.const_data] vtable for AMDCISAMUEngine 00000000003b7600 __float128 0f SECT 08 0000 [.const_data] vtable for AMDCIVCEChannel 00000000003b8080 __float128 0f SECT 08 0000 [.const_data] vtable for AMDCIVCELLQRing 00000000003b4050 __float128 0f SECT 08 0000 [.const_data] vtable for AMDCIsDMAEngine 00000000003aee20 __float128 0f SECT 08 0000 [.const_data] vtable for AMDSIDMAChannel 00000000003ae3e0 __float128 0f SECT 08 0000 [.const_data] vtable for AMDSIPM4Channel 00000000003b1640 __float128 0f SECT 08 0000 [.const_data] vtable for AMDSISPUChannel 00000000003b06e0 __float128 0f SECT 08 0000 [.const_data] vtable for AMDSIUVDChannel 00000000003af940 __float128 0f SECT 08 0000 [.const_data] vtable for AMDSIVCEChannel 00000000003b03c0 __float128 0f SECT 08 0000 [.const_data] vtable for AMDSIVCELLQRing 00000000003bbcd0 __float128 0f SECT 08 0000 [.const_data] vtable for AMDVIPM4Channel 00000000003bcb20 __float128 0f SECT 08 0000 [.const_data] vtable for AMDVISAMUEngine 00000000003bb030 __float128 0f SECT 08 0000 [.const_data] vtable for AMDVIsDMAEngine 00000000003bdfc0 __float128 0f SECT 08 0000 [.const_data] vtable for ShaderVidMemMgr 00000000003be090 __float128 0f SECT 08 0000 [.const_data] vtable for SiBltAuxSurfMgr 00000000003be4f0 __float128 0f SECT 08 0000 [.const_data] vtable for SiSurfAttribute 00000000003b83a0 __float128 0f SECT 08 0000 [.const_data] vtable for AMDCIComputeRing 00000000003b5170 __float128 0f SECT 08 0000 [.const_data] vtable for AMDCIHWUtilities 00000000003b5fc0 __float128 0f SECT 08 0000 [.const_data] vtable for AMDCISAMURBIRing 00000000003b6d70 __float128 0f SECT 08 0000 [.const_data] vtable for AMDCIUVDHWEngine 00000000003b7200 __float128 0f SECT 08 0000 [.const_data] vtable for AMDCIVCEHWEngine 00000000003b1d10 __float128 0f SECT 08 0000 [.const_data] vtable for AMDSIComputeRing 00000000003aae70 __float128 0f SECT 08 0000 [.const_data] vtable for AMDSIHWUtilities 00000000003b0ab0 __float128 0f SECT 08 0000 [.const_data] vtable for AMDSIUVDHWEngine 00000000003af540 __float128 0f SECT 08 0000 [.const_data] vtable for AMDSIVCEHWEngine 00000000003b91e0 __float128 0f SECT 08 0000 [.const_data] vtable for AMDTongaHardware 00000000003bb9b0 __float128 0f SECT 08 0000 [.const_data] vtable for AMDVIComputeRing 00000000003ba9c0 __float128 0f SECT 08 0000 [.const_data] vtable for AMDVIHWUtilities 00000000003bcef0 __float128 0f SECT 08 0000 [.const_data] vtable for AMDVISAMURBIRing 00000000003bac30 __float128 0f SECT 08 0000 [.const_data] vtable for AMDVIsDMAChannel 00000000003acc50 __float128 0f SECT 08 0000 [.const_data] vtable for AMDVerdeHardware 00000000003be310 __float128 0f SECT 08 0000 [.const_data] vtable for SiBltPixelShader 00000000003b3d30 __float128 0f SECT 08 0000 [.const_data] vtable for AMDCICommandsRing 00000000003b3280 __float128 0f SECT 08 0000 [.const_data] vtable for AMDHawaiiHardware 00000000003ae7d0 __float128 0f SECT 08 0000 [.const_data] vtable for AMDSICommandsRing 0000000000398200 __float128 0f SECT 08 0000 [.const_data] vtable for AMDSIVideoContext 00000000003abdf0 __float128 0f SECT 08 0000 [.const_data] vtable for AMDTahitiHardware 00000000003bb690 __float128 0f SECT 08 0000 [.const_data] vtable for AMDVICommandsRing 00000000003ae080 __float128 0f SECT 08 0000 [.const_data] vtable for AMDVerdePM4Engine 00000000003be3e0 __float128 0f SECT 08 0000 [.const_data] vtable for SiShaderVidMemMgr 00000000003b2b50 __float128 0f SECT 08 0000 [.const_data] vtable for AMDBonaireHardware 00000000003b6690 __float128 0f SECT 08 0000 [.const_data] vtable for AMDCISAMUGPCOMRing 00000000003b79b0 __float128 0f SECT 08 0000 [.const_data] vtable for AMDCIVCELLQChannel 00000000003afcf0 __float128 0f SECT 08 0000 [.const_data] vtable for AMDSIVCELLQChannel 00000000003ad9c0 __float128 0f SECT 08 0000 [.const_data] vtable for AMDTahitiPM4Engine 00000000003bd5c0 __float128 0f SECT 08 0000 [.const_data] vtable for AMDVISAMUGPCOMRing 00000000003b62f0 __float128 0f SECT 08 0000 [.const_data] vtable for AMDCISAMURBIChannel 00000000003ac520 __float128 0f SECT 08 0000 [.const_data] vtable for AMDPitcairnHardware 00000000003968a0 __float128 0f SECT 08 0000 [.const_data] vtable for AMDSIDisplayMachine 00000000003ad380 __float128 0f SECT 08 0000 [.const_data] vtable for AMDSIHWAlignManager 000000000039f950 __float128 0f SECT 08 0000 [.const_data] vtable for AMDVIDisplayMachine 00000000003bd220 __float128 0f SECT 08 0000 [.const_data] vtable for AMDVISAMURBIChannel 00000000003add20 __float128 0f SECT 08 0000 [.const_data] vtable for AMDPitcairnPM4Engine 00000000003b69d0 __float128 0f SECT 08 0000 [.const_data] vtable for AMDCISAMUGPCOMChannel 00000000003bd900 __float128 0f SECT 08 0000 [.const_data] vtable for AMDVISAMUGPCOMChannel 00000000003b86c0 __float128 0f SECT 08 0000 [.const_data] vtable for AMDCIPM4ComputeChannel 00000000003965e0 __float128 0f SECT 08 0000 [.const_data] vtable for AMDSIAtomicBlitManager 00000000003b2030 __float128 0f SECT 08 0000 [.const_data] vtable for AMDSIPM4ComputeChannel 00000000003bc730 __float128 0f SECT 08 0000 [.const_data] vtable for AMDVIPM4ComputeChannel 00000000003b46b0 __float128 0f SECT 08 0000 [.const_data] vtable for AMDCIPM4CommandsUtility 00000000003a7c30 __float128 0f SECT 08 0000 [.const_data] vtable for AMDRadeonX4000_AMDHWVMM 00000000003c3a90 __float128 0f SECT 08 0000 [.const_data] vtable for AMDRadeonX4000_AMDSIDRM 00000000003c3cf0 __float128 0f SECT 08 0000 [.const_data] vtable for AMDRadeonX4000_AMDSISPU 00000000003c3f80 __float128 0f SECT 08 0000 [.const_data] vtable for AMDRadeonX4000_AMDSIVCE 00000000003c52b0 __float128 0f SECT 08 0000 [.const_data] vtable for AMDRadeonX4000_AMDUVDVI 00000000003c5530 __float128 0f SECT 08 0000 [.const_data] vtable for AMDRadeonX4000_AMDVIDRM 00000000003c5790 __float128 0f SECT 08 0000 [.const_data] vtable for AMDRadeonX4000_AMDVISPU 00000000003c5a20 __float128 0f SECT 08 0000 [.const_data] vtable for AMDRadeonX4000_AMDVIVCE 00000000003bc0e0 __float128 0f SECT 08 0000 [.const_data] vtable for AMDVIPM4CommandsUtility 000000000039ada0 __float128 0f SECT 08 0000 [.const_data] vtable for AMDCIGraphicsAccelerator 0000000000390b00 __float128 0f SECT 08 0000 [.const_data] vtable for AMDRadeonX4000_AMDBltMgr 00000000003c4800 __float128 0f SECT 08 0000 [.const_data] vtable for AMDRadeonX4000_AMDCIKDRM 00000000003c4a60 __float128 0f SECT 08 0000 [.const_data] vtable for AMDRadeonX4000_AMDCIKSPU 00000000003c4cf0 __float128 0f SECT 08 0000 [.const_data] vtable for AMDRadeonX4000_AMDCIKVCE 00000000003a3070 __float128 0f SECT 08 0000 [.const_data] vtable for AMDRadeonX4000_AMDHWGart 00000000003a6c50 __float128 0f SECT 08 0000 [.const_data] vtable for AMDRadeonX4000_AMDHWRing 00000000003c13e0 __float128 0f SECT 08 0000 [.const_data] vtable for AMDRadeonX4000_AMDSMLDRM 00000000003c1620 __float128 0f SECT 08 0000 [.const_data] vtable for AMDRadeonX4000_AMDSMLSPU 00000000003c1160 __float128 0f SECT 08 0000 [.const_data] vtable for AMDRadeonX4000_AMDSMLUVD 00000000003c1b40 __float128 0f SECT 08 0000 [.const_data] vtable for AMDRadeonX4000_AMDSMLVCE 00000000003c4580 __float128 0f SECT 08 0000 [.const_data] vtable for AMDRadeonX4000_AMDUVDCIK 00000000003a6080 __float128 0f SECT 08 0000 [.const_data] vtable for AMDRadeonX4000_IAMDHWVMM 00000000003936e0 __float128 0f SECT 08 0000 [.const_data] vtable for AMDSIGraphicsAccelerator 000000000039e1d0 __float128 0f SECT 08 0000 [.const_data] vtable for AMDVIGraphicsAccelerator 00000000003a7f60 __float128 0f SECT 08 0000 [.const_data] vtable for AMDRadeonX4000_AMDNULLVMM 00000000003a4880 __float128 0f SECT 08 0000 [.const_data] vtable for AMDRadeonX4000_IAMDHWGart 00000000003a4b30 __float128 0f SECT 08 0000 [.const_data] vtable for AMDRadeonX4000_IAMDHWRing 00000000003c0450 __float128 0f SECT 08 0000 [.const_data] vtable for AMDRadeonX4000_IAMDSMLDRM 00000000003c0680 __float128 0f SECT 08 0000 [.const_data] vtable for AMDRadeonX4000_IAMDSMLSPU 00000000003c0220 __float128 0f SECT 08 0000 [.const_data] vtable for AMDRadeonX4000_IAMDSMLUVD 00000000003c08b0 __float128 0f SECT 08 0000 [.const_data] vtable for AMDRadeonX4000_IAMDSMLVCE 0000000000390d40 __float128 0f SECT 08 0000 [.const_data] vtable for AMDRadeonX4000_VendorGart 00000000003a2a40 __float128 0f SECT 08 0000 [.const_data] vtable for AMDRadeonX4000_AMDHWEngine 00000000003a6650 __float128 0f SECT 08 0000 [.const_data] vtable for AMDRadeonX4000_AMDHWMemory 00000000003a8280 __float128 0f SECT 08 0000 [.const_data] vtable for AMDRadeonX4000_AMDHardware 000000000038fb70 __float128 0f SECT 08 0000 [.const_data] vtable for AMDRadeonX4000_AMDSPUEvent 0000000000392c10 __float128 0f SECT 08 0000 [.const_data] vtable for AMDRadeonX4000_AMDAccelTask 00000000003a0b30 __float128 0f SECT 08 0000 [.const_data] vtable for AMDRadeonX4000_AMDHWChannel 00000000003a0ed0 __float128 0f SECT 08 0000 [.const_data] vtable for AMDRadeonX4000_AMDHWDisplay 00000000003a07b0 __float128 0f SECT 08 0000 [.const_data] vtable for AMDRadeonX4000_AMDHWHandler 0000000000390f70 __float128 0f SECT 08 0000 [.const_data] vtable for AMDRadeonX4000_AMDHashTable 00000000003c18b0 __float128 0f SECT 08 0000 [.const_data] vtable for AMDRadeonX4000_AMDSMLSPUMsg 00000000003a5a30 __float128 0f SECT 08 0000 [.const_data] vtable for AMDRadeonX4000_IAMDHWEngine 00000000003a4540 __float128 0f SECT 08 0000 [.const_data] vtable for AMDRadeonX4000_IAMDHWMemory 000000000039ed90 __float128 0f SECT 08 0000 [.const_data] vtable for AMDTongaGraphicsAccelerator 0000000000395a20 __float128 0f SECT 08 0000 [.const_data] vtable for AMDVerdeGraphicsAccelerator 000000000039c520 __float128 0f SECT 08 0000 [.const_data] vtable for AMDHawaiiGraphicsAccelerator 00000000003911a0 __float128 0f SECT 08 0000 [.const_data] vtable for AMDRadeonX4000_AMDLinkedList 000000000038fdb0 __float128 0f SECT 08 0000 [.const_data] vtable for AMDRadeonX4000_AMDSPUContext 0000000000390380 __float128 0f SECT 08 0000 [.const_data] vtable for AMDRadeonX4000_AMDTPTManager 00000000003c3810 __float128 0f SECT 08 0000 [.const_data] vtable for AMDRadeonX4000_AMDUVDTrinity 00000000003a5d20 __float128 0f SECT 08 0000 [.const_data] vtable for AMDRadeonX4000_IAMDHWChannel 00000000003a3870 __float128 0f SECT 08 0000 [.const_data] vtable for AMDRadeonX4000_IAMDHWDisplay 00000000003a3c80 __float128 0f SECT 08 0000 [.const_data] vtable for AMDRadeonX4000_IAMDHWHandler 0000000000394e60 __float128 0f SECT 08 0000 [.const_data] vtable for AMDTahitiGraphicsAccelerator 000000000039b960 __float128 0f SECT 08 0000 [.const_data] vtable for AMDBonaireGraphicsAccelerator 0000000000389d30 __float128 0f SECT 08 0000 [.const_data] vtable for AMDRadeonX4000_AMDAccelDevice 000000000038ba40 __float128 0f SECT 08 0000 [.const_data] vtable for AMDRadeonX4000_AMDAccelShared 00000000003a20d0 __float128 0f SECT 08 0000 [.const_data] vtable for AMDRadeonX4000_AMDDMAHWEngine 00000000003c2a80 __float128 0f SECT 08 0000 [.const_data] vtable for AMDRadeonX4000_AMDFPGenKeyMsg 00000000003a69d0 __float128 0f SECT 08 0000 [.const_data] vtable for AMDRadeonX4000_AMDHWRegisters 00000000003a6f70 __float128 0f SECT 08 0000 [.const_data] vtable for AMDRadeonX4000_AMDHWSemaphore 00000000003a1340 __float128 0f SECT 08 0000 [.const_data] vtable for AMDRadeonX4000_AMDHWUtilities 00000000003a7980 __float128 0f SECT 08 0000 [.const_data] vtable for AMDRadeonX4000_AMDHWVMContext 00000000003a8ba0 __float128 0f SECT 08 0000 [.const_data] vtable for AMDRadeonX4000_AMDPM4HWEngine 00000000003a92e0 __float128 0f SECT 08 0000 [.const_data] vtable for AMDRadeonX4000_AMDSPUHWEngine 00000000003aa1f0 __float128 0f SECT 08 0000 [.const_data] vtable for AMDRadeonX4000_AMDUVDHWEngine 00000000003a9a40 __float128 0f SECT 08 0000 [.const_data] vtable for AMDRadeonX4000_AMDVCEHWEngine 00000000003942a0 __float128 0f SECT 08 0000 [.const_data] vtable for AMDPitcairnGraphicsAccelerator 0000000000389a00 __float128 0f SECT 08 0000 [.const_data] vtable for AMDRadeonX4000_AMDAccelChannel 000000000038c9c0 __float128 0f SECT 08 0000 [.const_data] vtable for AMDRadeonX4000_AMDAccelSurface 00000000003a1cd0 __float128 0f SECT 08 0000 [.const_data] vtable for AMDRadeonX4000_AMDDMAHWChannel 00000000003c3230 __float128 0f SECT 08 0000 [.const_data] vtable for AMDRadeonX4000_AMDFPEncryptMsg 00000000003c27f0 __float128 0f SECT 08 0000 [.const_data] vtable for AMDRadeonX4000_AMDFPGetCertMsg 00000000003c2d10 __float128 0f SECT 08 0000 [.const_data] vtable for AMDRadeonX4000_AMDFPTestKeyMsg 00000000003a2d70 __float128 0f SECT 08 0000 [.const_data] vtable for AMDRadeonX4000_AMDNullHWEngine 00000000003a8f00 __float128 0f SECT 08 0000 [.const_data] vtable for AMDRadeonX4000_AMDPM4HWChannel 00000000003c0e10 __float128 0f SECT 08 0000 [.const_data] vtable for AMDRadeonX4000_AMDSMLInterface 00000000003a96a0 __float128 0f SECT 08 0000 [.const_data] vtable for AMDRadeonX4000_AMDSPUHWChannel 00000000003a1900 __float128 0f SECT 08 0000 [.const_data] vtable for AMDRadeonX4000_AMDUVDHWChannel 00000000003a9e40 __float128 0f SECT 08 0000 [.const_data] vtable for AMDRadeonX4000_AMDVCEHWChannel 00000000003a3350 __float128 0f SECT 08 0000 [.const_data] vtable for AMDRadeonX4000_IAMDHWInterface 00000000003a42c0 __float128 0f SECT 08 0000 [.const_data] vtable for AMDRadeonX4000_IAMDHWRegisters 00000000003a4e00 __float128 0f SECT 08 0000 [.const_data] vtable for AMDRadeonX4000_IAMDHWSemaphore 00000000003a5530 __float128 0f SECT 08 0000 [.const_data] vtable for AMDRadeonX4000_IAMDHWUtilities 00000000003a63a0 __float128 0f SECT 08 0000 [.const_data] vtable for AMDRadeonX4000_IAMDHWVMContext 000000000038b600 __float128 0f SECT 08 0000 [.const_data] vtable for AMDRadeonX4000_AMDAccelResource 00000000003a26e0 __float128 0f SECT 08 0000 [.const_data] vtable for AMDRadeonX4000_AMDNullHWChannel 000000000038f8f0 __float128 0f SECT 08 0000 [.const_data] vtable for AMDRadeonX4000_AMDSPUAppContext 00000000003c0ae0 __float128 0f SECT 08 0000 [.const_data] vtable for AMDRadeonX4000_IAMDSMLInterface 000000000038d4c0 __float128 0f SECT 08 0000 [.const_data] vtable for AMDRadeonX4000_AMDAccel2DContext 0000000000392020 __float128 0f SECT 08 0000 [.const_data] vtable for AMDRadeonX4000_AMDAccelCLContext 0000000000393440 __float128 0f SECT 08 0000 [.const_data] vtable for AMDRadeonX4000_AMDAccelMemoryMap 0000000000392ea0 __float128 0f SECT 08 0000 [.const_data] vtable for AMDRadeonX4000_AMDAccelSysMemory 0000000000393160 __float128 0f SECT 08 0000 [.const_data] vtable for AMDRadeonX4000_AMDAccelVidMemory 00000000003c2560 __float128 0f SECT 08 0000 [.const_data] vtable for AMDRadeonX4000_AMDHDCPGetCertMsg 00000000003a2400 __float128 0f SECT 08 0000 [.const_data] vtable for AMDRadeonX4000_AMDHWAlignManager 00000000003c34c0 __float128 0f SECT 08 0000 [.const_data] vtable for AMDRadeonX4000_AMDSMLSIInterface 00000000003c4f60 __float128 0f SECT 08 0000 [.const_data] vtable for AMDRadeonX4000_AMDSMLVIInterface 000000000038c770 __float128 0f SECT 08 0000 [.const_data] vtable for AMDRadeonX4000_AMDAccelStatistics 000000000038f6b0 __float128 0f SECT 08 0000 [.const_data] vtable for AMDRadeonX4000_AMDAccelUVDContext 0000000000390140 __float128 0f SECT 08 0000 [.const_data] vtable for AMDRadeonX4000_AMDAccelVCEContext 00000000003a74c0 __float128 0f SECT 08 0000 [.const_data] vtable for AMDRadeonX4000_AMDHWSemaphorePool 00000000003a7210 __float128 0f SECT 08 0000 [.const_data] vtable for AMDRadeonX4000_AMDNullHWSemaphore 00000000003c4230 __float128 0f SECT 08 0000 [.const_data] vtable for AMDRadeonX4000_AMDSMLCIKInterface 00000000003a3ff0 __float128 0f SECT 08 0000 [.const_data] vtable for AMDRadeonX4000_IAMDHWAlignManager 00000000003c22d0 __float128 0f SECT 08 0000 [.const_data] vtable for AMDRadeonX4000_AMDHDCPGetStatusMsg 00000000003a5090 __float128 0f SECT 08 0000 [.const_data] vtable for AMDRadeonX4000_IAMDHWSemaphorePool 00000000003918d0 __float128 0f SECT 08 0000 [.const_data] vtable for AMDRadeonX4000_IAMDStatisticsGroup 000000000038b230 __float128 0f SECT 08 0000 [.const_data] vtable for AMDRadeonX4000_AMDAccelEventMachine 000000000038e660 __float128 0f SECT 08 0000 [.const_data] vtable for AMDRadeonX4000_AMDAccelVideoContext 0000000000390840 __float128 0f SECT 08 0000 [.const_data] vtable for AMDRadeonX4000_AMDAtomicBlitManager 00000000003a7730 __float128 0f SECT 08 0000 [.const_data] vtable for AMDRadeonX4000_AMDHWSemaphoreMemMgr 00000000003c1db0 __float128 0f SECT 08 0000 [.const_data] vtable for AMDRadeonX4000_AMDHDCPOpenSessionMsg 00000000003a8900 __float128 0f SECT 08 0000 [.const_data] vtable for AMDRadeonX4000_AMDPM4CommandsUtility 00000000003905b0 __float128 0f SECT 08 0000 [.const_data] vtable for AMDRadeonX4000_IAMDAtomicBlitManager 00000000003a52e0 __float128 0f SECT 08 0000 [.const_data] vtable for AMDRadeonX4000_IAMDHWSemaphoreMemMgr 00000000003913d0 __float128 0f SECT 08 0000 [.const_data] vtable for AMDRadeonX4000_IAMDStatisticsManager 000000000038a7f0 __float128 0f SECT 08 0000 [.const_data] vtable for AMDRadeonX4000_AMDAccelDisplayMachine 00000000003c2fa0 __float128 0f SECT 08 0000 [.const_data] vtable for AMDRadeonX4000_AMDFPReleaseSessionMsg 0000000000388dd0 __float128 0f SECT 08 0000 [.const_data] vtable for AMDRadeonX4000_AMDGraphicsAccelerator 00000000003c2040 __float128 0f SECT 08 0000 [.const_data] vtable for AMDRadeonX4000_AMDHDCPCloseSessionMsg 0000000000391db0 __float128 0f SECT 08 0000 [.const_data] vtable for AMDRadeonX4000_AMDHWChannelStatsGroup 00000000003a5790 __float128 0f SECT 08 0000 [.const_data] vtable for AMDRadeonX4000_IAMDPM4CommandsUtility 0000000000391b40 __float128 0f SECT 08 0000 [.const_data] vtable for AMDRadeonX4000_AMDAccelStatisticsGroup 000000000038e2d0 __float128 0f SECT 08 0000 [.const_data] vtable for AMDRadeonX4000_AMDInterruptEventSource 000000000038bc80 __float128 0f SECT 08 0000 [.const_data] vtable for AMDRadeonX4000_AMDAccelSharedUserClient 000000000038e090 __float128 0f SECT 08 0000 [.const_data] vtable for AMDRadeonX4000_AMDAccelCommandBufferPool 0000000000391650 __float128 0f SECT 08 0000 [.const_data] vtable for AMDRadeonX4000_AMDAccelStatisticsManager 00000000003a15b0 __float128 0f SECT 08 0000 [.const_data] vtable for AMDRadeonX4000_AMDUVDInterruptEventSource 00000000003bde20 __float128 0f SECT 08 0000 [.const_data] vtable for BltMgr 00000000003be580 __float128 0f SECT 08 0000 [.const_data] vtable for AddrLib 00000000003ab390 __float128 0f SECT 08 0000 [.const_data] vtable for AMDSIVMM 00000000003ba220 __float128 0f SECT 08 0000 [.const_data] vtable for AMDVIVMM 00000000003be220 __float128 0f SECT 08 0000 [.const_data] vtable for SiBltMgr 00000000003bdf40 __float128 0f SECT 08 0000 [.const_data] vtable for BltResFmt 00000000003bdf70 __float128 0f SECT 08 0000 [.const_data] vtable for BltShader 00000000003bead0 __float128 0f SECT 08 0000 [.const_data] vtable for CIAddrLib 00000000003be8f0 __float128 0f SECT 08 0000 [.const_data] vtable for SIAddrLib 00000000003b9af0 __float128 0f SECT 08 0000 [.const_data] vtable for AMDVIHWGart::MetaClass 00000000003b4cf0 __float128 0f SECT 08 0000 [.const_data] vtable for AMDCIDisplay::MetaClass 00000000003b7f80 __float128 0f SECT 08 0000 [.const_data] vtable for AMDCIVCERing::MetaClass 00000000003af440 __float128 0f SECT 08 0000 [.const_data] vtable for AMDSIDMARing::MetaClass 00000000003aad70 __float128 0f SECT 08 0000 [.const_data] vtable for AMDSIDisplay::MetaClass 00000000003b1c10 __float128 0f SECT 08 0000 [.const_data] vtable for AMDSISPURing::MetaClass 0000000000398100 __float128 0f SECT 08 0000 [.const_data] vtable for AMDSISurface::MetaClass 00000000003b1160 __float128 0f SECT 08 0000 [.const_data] vtable for AMDSIUVDRing::MetaClass 00000000003b02c0 __float128 0f SECT 08 0000 [.const_data] vtable for AMDSIVCERing::MetaClass 00000000003ba8c0 __float128 0f SECT 08 0000 [.const_data] vtable for AMDVIDisplay::MetaClass 00000000003b5070 __float128 0f SECT 08 0000 [.const_data] vtable for AMDCIHWMemory::MetaClass 00000000003b2a50 __float128 0f SECT 08 0000 [.const_data] vtable for AMDCIHardware::MetaClass 000000000039d420 __float128 0f SECT 08 0000 [.const_data] vtable for AMDCIResource::MetaClass 00000000003b45b0 __float128 0f SECT 08 0000 [.const_data] vtable for AMDCIsDMARing::MetaClass 00000000003aa900 __float128 0f SECT 08 0000 [.const_data] vtable for AMDSIHWMemory::MetaClass 00000000003abcf0 __float128 0f SECT 08 0000 [.const_data] vtable for AMDSIHardware::MetaClass 0000000000397600 __float128 0f SECT 08 0000 [.const_data] vtable for AMDSIResource::MetaClass 00000000003b9e70 __float128 0f SECT 08 0000 [.const_data] vtable for AMDVIHWMemory::MetaClass 00000000003b90e0 __float128 0f SECT 08 0000 [.const_data] vtable for AMDVIHardware::MetaClass 00000000003a06b0 __float128 0f SECT 08 0000 [.const_data] vtable for AMDVIResource::MetaClass 00000000003bb590 __float128 0f SECT 08 0000 [.const_data] vtable for AMDVIsDMARing::MetaClass 000000000039e0a0 __float128 0f SECT 08 0000 [.const_data] vtable for AMDCICLContext::MetaClass 00000000003b3c30 __float128 0f SECT 08 0000 [.const_data] vtable for AMDCIPM4Engine::MetaClass 000000000039ac70 __float128 0f SECT 08 0000 [.const_data] vtable for AMDSICLContext::MetaClass 00000000003aed20 __float128 0f SECT 08 0000 [.const_data] vtable for AMDSIDMAEngine::MetaClass 0000000000399f70 __float128 0f SECT 08 0000 [.const_data] vtable for AMDSIGLContext::MetaClass 00000000003ad8c0 __float128 0f SECT 08 0000 [.const_data] vtable for AMDSIPM4Engine::MetaClass 00000000003b1540 __float128 0f SECT 08 0000 [.const_data] vtable for AMDSISPUEngine::MetaClass 00000000003ab290 __float128 0f SECT 08 0000 [.const_data] vtable for AMDSIVMContext::MetaClass 00000000003bc630 __float128 0f SECT 08 0000 [.const_data] vtable for AMDVIPM4Engine::MetaClass 00000000003ba120 __float128 0f SECT 08 0000 [.const_data] vtable for AMDVIVMContext::MetaClass 00000000003b5af0 __float128 0f SECT 08 0000 [.const_data] vtable for AMDCIDMAChannel::MetaClass 00000000003b56f0 __float128 0f SECT 08 0000 [.const_data] vtable for AMDCIPM4Channel::MetaClass 00000000003b5ec0 __float128 0f SECT 08 0000 [.const_data] vtable for AMDCISAMUEngine::MetaClass 00000000003b78b0 __float128 0f SECT 08 0000 [.const_data] vtable for AMDCIVCEChannel::MetaClass 00000000003b82a0 __float128 0f SECT 08 0000 [.const_data] vtable for AMDCIVCELLQRing::MetaClass 00000000003b4290 __float128 0f SECT 08 0000 [.const_data] vtable for AMDCIsDMAEngine::MetaClass 00000000003af120 __float128 0f SECT 08 0000 [.const_data] vtable for AMDSIDMAChannel::MetaClass 00000000003ae6d0 __float128 0f SECT 08 0000 [.const_data] vtable for AMDSIPM4Channel::MetaClass 00000000003b18e0 __float128 0f SECT 08 0000 [.const_data] vtable for AMDSISPUChannel::MetaClass 00000000003b09b0 __float128 0f SECT 08 0000 [.const_data] vtable for AMDSIUVDChannel::MetaClass 00000000003afbf0 __float128 0f SECT 08 0000 [.const_data] vtable for AMDSIVCEChannel::MetaClass 00000000003b05e0 __float128 0f SECT 08 0000 [.const_data] vtable for AMDSIVCELLQRing::MetaClass 00000000003bbfe0 __float128 0f SECT 08 0000 [.const_data] vtable for AMDVIPM4Channel::MetaClass 00000000003bcdf0 __float128 0f SECT 08 0000 [.const_data] vtable for AMDVISAMUEngine::MetaClass 00000000003bb270 __float128 0f SECT 08 0000 [.const_data] vtable for AMDVIsDMAEngine::MetaClass 00000000003b85c0 __float128 0f SECT 08 0000 [.const_data] vtable for AMDCIComputeRing::MetaClass 00000000003b52e0 __float128 0f SECT 08 0000 [.const_data] vtable for AMDCIHWUtilities::MetaClass 00000000003b61f0 __float128 0f SECT 08 0000 [.const_data] vtable for AMDCISAMURBIRing::MetaClass 00000000003b7100 __float128 0f SECT 08 0000 [.const_data] vtable for AMDCIUVDHWEngine::MetaClass 00000000003b7500 __float128 0f SECT 08 0000 [.const_data] vtable for AMDCIVCEHWEngine::MetaClass 00000000003b1f30 __float128 0f SECT 08 0000 [.const_data] vtable for AMDSIComputeRing::MetaClass 00000000003aafe0 __float128 0f SECT 08 0000 [.const_data] vtable for AMDSIHWUtilities::MetaClass 00000000003b0e40 __float128 0f SECT 08 0000 [.const_data] vtable for AMDSIUVDHWEngine::MetaClass 00000000003af840 __float128 0f SECT 08 0000 [.const_data] vtable for AMDSIVCEHWEngine::MetaClass 00000000003b9810 __float128 0f SECT 08 0000 [.const_data] vtable for AMDTongaHardware::MetaClass 00000000003bbbd0 __float128 0f SECT 08 0000 [.const_data] vtable for AMDVIComputeRing::MetaClass 00000000003bab30 __float128 0f SECT 08 0000 [.const_data] vtable for AMDVIHWUtilities::MetaClass 00000000003bd120 __float128 0f SECT 08 0000 [.const_data] vtable for AMDVISAMURBIRing::MetaClass 00000000003baf30 __float128 0f SECT 08 0000 [.const_data] vtable for AMDVIsDMAChannel::MetaClass 00000000003ad280 __float128 0f SECT 08 0000 [.const_data] vtable for AMDVerdeHardware::MetaClass 00000000003b3f50 __float128 0f SECT 08 0000 [.const_data] vtable for AMDCICommandsRing::MetaClass 00000000003b38b0 __float128 0f SECT 08 0000 [.const_data] vtable for AMDHawaiiHardware::MetaClass 00000000003ae9f0 __float128 0f SECT 08 0000 [.const_data] vtable for AMDSICommandsRing::MetaClass 0000000000398d00 __float128 0f SECT 08 0000 [.const_data] vtable for AMDSIVideoContext::MetaClass 00000000003ac420 __float128 0f SECT 08 0000 [.const_data] vtable for AMDTahitiHardware::MetaClass 00000000003bb8b0 __float128 0f SECT 08 0000 [.const_data] vtable for AMDVICommandsRing::MetaClass 00000000003ae2e0 __float128 0f SECT 08 0000 [.const_data] vtable for AMDVerdePM4Engine::MetaClass 00000000003b3180 __float128 0f SECT 08 0000 [.const_data] vtable for AMDBonaireHardware::MetaClass 00000000003b68d0 __float128 0f SECT 08 0000 [.const_data] vtable for AMDCISAMUGPCOMRing::MetaClass 00000000003b7c60 __float128 0f SECT 08 0000 [.const_data] vtable for AMDCIVCELLQChannel::MetaClass 00000000003affa0 __float128 0f SECT 08 0000 [.const_data] vtable for AMDSIVCELLQChannel::MetaClass 00000000003adc20 __float128 0f SECT 08 0000 [.const_data] vtable for AMDTahitiPM4Engine::MetaClass 00000000003bd800 __float128 0f SECT 08 0000 [.const_data] vtable for AMDVISAMUGPCOMRing::MetaClass 00000000003b6590 __float128 0f SECT 08 0000 [.const_data] vtable for AMDCISAMURBIChannel::MetaClass 00000000003acb50 __float128 0f SECT 08 0000 [.const_data] vtable for AMDPitcairnHardware::MetaClass 00000000003971c0 __float128 0f SECT 08 0000 [.const_data] vtable for AMDSIDisplayMachine::MetaClass 00000000003ad560 __float128 0f SECT 08 0000 [.const_data] vtable for AMDSIHWAlignManager::MetaClass 00000000003a0270 __float128 0f SECT 08 0000 [.const_data] vtable for AMDVIDisplayMachine::MetaClass 00000000003bd4c0 __float128 0f SECT 08 0000 [.const_data] vtable for AMDVISAMURBIChannel::MetaClass 00000000003adf80 __float128 0f SECT 08 0000 [.const_data] vtable for AMDPitcairnPM4Engine::MetaClass 00000000003b6c70 __float128 0f SECT 08 0000 [.const_data] vtable for AMDCISAMUGPCOMChannel::MetaClass 00000000003bdba0 __float128 0f SECT 08 0000 [.const_data] vtable for AMDVISAMUGPCOMChannel::MetaClass 00000000003b89b0 __float128 0f SECT 08 0000 [.const_data] vtable for AMDCIPM4ComputeChannel::MetaClass 00000000003967a0 __float128 0f SECT 08 0000 [.const_data] vtable for AMDSIAtomicBlitManager::MetaClass 00000000003b2320 __float128 0f SECT 08 0000 [.const_data] vtable for AMDSIPM4ComputeChannel::MetaClass 00000000003bca20 __float128 0f SECT 08 0000 [.const_data] vtable for AMDVIPM4ComputeChannel::MetaClass 00000000003b4870 __float128 0f SECT 08 0000 [.const_data] vtable for AMDCIPM4CommandsUtility::MetaClass 00000000003a7e60 __float128 0f SECT 08 0000 [.const_data] vtable for AMDRadeonX4000_AMDHWVMM::MetaClass 00000000003c3bf0 __float128 0f SECT 08 0000 [.const_data] vtable for AMDRadeonX4000_AMDSIDRM::MetaClass 00000000003c3e80 __float128 0f SECT 08 0000 [.const_data] vtable for AMDRadeonX4000_AMDSISPU::MetaClass 00000000003c40f0 __float128 0f SECT 08 0000 [.const_data] vtable for AMDRadeonX4000_AMDSIVCE::MetaClass 00000000003c5430 __float128 0f SECT 08 0000 [.const_data] vtable for AMDRadeonX4000_AMDUVDVI::MetaClass 00000000003c5690 __float128 0f SECT 08 0000 [.const_data] vtable for AMDRadeonX4000_AMDVIDRM::MetaClass 00000000003c5920 __float128 0f SECT 08 0000 [.const_data] vtable for AMDRadeonX4000_AMDVISPU::MetaClass 00000000003c5b90 __float128 0f SECT 08 0000 [.const_data] vtable for AMDRadeonX4000_AMDVIVCE::MetaClass 00000000003bc2a0 __float128 0f SECT 08 0000 [.const_data] vtable for AMDVIPM4CommandsUtility::MetaClass 000000000039b860 __float128 0f SECT 08 0000 [.const_data] vtable for AMDCIGraphicsAccelerator::MetaClass 0000000000390c40 __float128 0f SECT 08 0000 [.const_data] vtable for AMDRadeonX4000_AMDBltMgr::MetaClass 00000000003c4960 __float128 0f SECT 08 0000 [.const_data] vtable for AMDRadeonX4000_AMDCIKDRM::MetaClass 00000000003c4bf0 __float128 0f SECT 08 0000 [.const_data] vtable for AMDRadeonX4000_AMDCIKSPU::MetaClass 00000000003c4e60 __float128 0f SECT 08 0000 [.const_data] vtable for AMDRadeonX4000_AMDCIKVCE::MetaClass 00000000003a3250 __float128 0f SECT 08 0000 [.const_data] vtable for AMDRadeonX4000_AMDHWGart::MetaClass 00000000003a6e70 __float128 0f SECT 08 0000 [.const_data] vtable for AMDRadeonX4000_AMDHWRing::MetaClass 00000000003c1520 __float128 0f SECT 08 0000 [.const_data] vtable for AMDRadeonX4000_AMDSMLDRM::MetaClass 00000000003c17b0 __float128 0f SECT 08 0000 [.const_data] vtable for AMDRadeonX4000_AMDSMLSPU::MetaClass 00000000003c12e0 __float128 0f SECT 08 0000 [.const_data] vtable for AMDRadeonX4000_AMDSMLUVD::MetaClass 00000000003c1cb0 __float128 0f SECT 08 0000 [.const_data] vtable for AMDRadeonX4000_AMDSMLVCE::MetaClass 00000000003c4700 __float128 0f SECT 08 0000 [.const_data] vtable for AMDRadeonX4000_AMDUVDCIK::MetaClass 00000000003a62a0 __float128 0f SECT 08 0000 [.const_data] vtable for AMDRadeonX4000_IAMDHWVMM::MetaClass 00000000003941a0 __float128 0f SECT 08 0000 [.const_data] vtable for AMDSIGraphicsAccelerator::MetaClass 000000000039ec90 __float128 0f SECT 08 0000 [.const_data] vtable for AMDVIGraphicsAccelerator::MetaClass 00000000003a8180 __float128 0f SECT 08 0000 [.const_data] vtable for AMDRadeonX4000_AMDNULLVMM::MetaClass 00000000003a4a30 __float128 0f SECT 08 0000 [.const_data] vtable for AMDRadeonX4000_IAMDHWGart::MetaClass 00000000003a4d00 __float128 0f SECT 08 0000 [.const_data] vtable for AMDRadeonX4000_IAMDHWRing::MetaClass 00000000003c0580 __float128 0f SECT 08 0000 [.const_data] vtable for AMDRadeonX4000_IAMDSMLDRM::MetaClass 00000000003c07b0 __float128 0f SECT 08 0000 [.const_data] vtable for AMDRadeonX4000_IAMDSMLSPU::MetaClass 00000000003c0350 __float128 0f SECT 08 0000 [.const_data] vtable for AMDRadeonX4000_IAMDSMLUVD::MetaClass 00000000003c09e0 __float128 0f SECT 08 0000 [.const_data] vtable for AMDRadeonX4000_IAMDSMLVCE::MetaClass 0000000000390e70 __float128 0f SECT 08 0000 [.const_data] vtable for AMDRadeonX4000_VendorGart::MetaClass 00000000003a2c70 __float128 0f SECT 08 0000 [.const_data] vtable for AMDRadeonX4000_AMDHWEngine::MetaClass 00000000003a68d0 __float128 0f SECT 08 0000 [.const_data] vtable for AMDRadeonX4000_AMDHWMemory::MetaClass 00000000003a8800 __float128 0f SECT 08 0000 [.const_data] vtable for AMDRadeonX4000_AMDHardware::MetaClass 000000000038fcb0 __float128 0f SECT 08 0000 [.const_data] vtable for AMDRadeonX4000_AMDSPUEvent::MetaClass 0000000000392da0 __float128 0f SECT 08 0000 [.const_data] vtable for AMDRadeonX4000_AMDAccelTask::MetaClass 00000000003a0dd0 __float128 0f SECT 08 0000 [.const_data] vtable for AMDRadeonX4000_AMDHWChannel::MetaClass 00000000003a1240 __float128 0f SECT 08 0000 [.const_data] vtable for AMDRadeonX4000_AMDHWDisplay::MetaClass 00000000003a0a30 __float128 0f SECT 08 0000 [.const_data] vtable for AMDRadeonX4000_AMDHWHandler::MetaClass 00000000003910a0 __float128 0f SECT 08 0000 [.const_data] vtable for AMDRadeonX4000_AMDHashTable::MetaClass 00000000003c1a40 __float128 0f SECT 08 0000 [.const_data] vtable for AMDRadeonX4000_AMDSMLSPUMsg::MetaClass 00000000003a5c20 __float128 0f SECT 08 0000 [.const_data] vtable for AMDRadeonX4000_IAMDHWEngine::MetaClass 00000000003a4780 __float128 0f SECT 08 0000 [.const_data] vtable for AMDRadeonX4000_IAMDHWMemory::MetaClass 000000000039f850 __float128 0f SECT 08 0000 [.const_data] vtable for AMDTongaGraphicsAccelerator::MetaClass 00000000003964e0 __float128 0f SECT 08 0000 [.const_data] vtable for AMDVerdeGraphicsAccelerator::MetaClass 000000000039cfe0 __float128 0f SECT 08 0000 [.const_data] vtable for AMDHawaiiGraphicsAccelerator::MetaClass 00000000003912d0 __float128 0f SECT 08 0000 [.const_data] vtable for AMDRadeonX4000_AMDLinkedList::MetaClass 0000000000390040 __float128 0f SECT 08 0000 [.const_data] vtable for AMDRadeonX4000_AMDSPUContext::MetaClass 00000000003904b0 __float128 0f SECT 08 0000 [.const_data] vtable for AMDRadeonX4000_AMDTPTManager::MetaClass 00000000003c3990 __float128 0f SECT 08 0000 [.const_data] vtable for AMDRadeonX4000_AMDUVDTrinity::MetaClass 00000000003a5f80 __float128 0f SECT 08 0000 [.const_data] vtable for AMDRadeonX4000_IAMDHWChannel::MetaClass 00000000003a3b80 __float128 0f SECT 08 0000 [.const_data] vtable for AMDRadeonX4000_IAMDHWDisplay::MetaClass 00000000003a3ef0 __float128 0f SECT 08 0000 [.const_data] vtable for AMDRadeonX4000_IAMDHWHandler::MetaClass 0000000000395920 __float128 0f SECT 08 0000 [.const_data] vtable for AMDTahitiGraphicsAccelerator::MetaClass 000000000039c420 __float128 0f SECT 08 0000 [.const_data] vtable for AMDBonaireGraphicsAccelerator::MetaClass 000000000038a6c0 __float128 0f SECT 08 0000 [.const_data] vtable for AMDRadeonX4000_AMDAccelDevice::MetaClass 000000000038bb80 __float128 0f SECT 08 0000 [.const_data] vtable for AMDRadeonX4000_AMDAccelShared::MetaClass 00000000003a2300 __float128 0f SECT 08 0000 [.const_data] vtable for AMDRadeonX4000_AMDDMAHWEngine::MetaClass 00000000003c2c10 __float128 0f SECT 08 0000 [.const_data] vtable for AMDRadeonX4000_AMDFPGenKeyMsg::MetaClass 00000000003a6b50 __float128 0f SECT 08 0000 [.const_data] vtable for AMDRadeonX4000_AMDHWRegisters::MetaClass 00000000003a7110 __float128 0f SECT 08 0000 [.const_data] vtable for AMDRadeonX4000_AMDHWSemaphore::MetaClass 00000000003a14b0 __float128 0f SECT 08 0000 [.const_data] vtable for AMDRadeonX4000_AMDHWUtilities::MetaClass 00000000003a7b30 __float128 0f SECT 08 0000 [.const_data] vtable for AMDRadeonX4000_AMDHWVMContext::MetaClass 00000000003a8e00 __float128 0f SECT 08 0000 [.const_data] vtable for AMDRadeonX4000_AMDPM4HWEngine::MetaClass 00000000003a95a0 __float128 0f SECT 08 0000 [.const_data] vtable for AMDRadeonX4000_AMDSPUHWEngine::MetaClass 00000000003aa580 __float128 0f SECT 08 0000 [.const_data] vtable for AMDRadeonX4000_AMDUVDHWEngine::MetaClass 00000000003a9d40 __float128 0f SECT 08 0000 [.const_data] vtable for AMDRadeonX4000_AMDVCEHWEngine::MetaClass 0000000000394d60 __float128 0f SECT 08 0000 [.const_data] vtable for AMDPitcairnGraphicsAccelerator::MetaClass 0000000000389c10 __float128 0f SECT 08 0000 [.const_data] vtable for AMDRadeonX4000_AMDAccelChannel::MetaClass 000000000038d3c0 __float128 0f SECT 08 0000 [.const_data] vtable for AMDRadeonX4000_AMDAccelSurface::MetaClass 00000000003a1fd0 __float128 0f SECT 08 0000 [.const_data] vtable for AMDRadeonX4000_AMDDMAHWChannel::MetaClass 00000000003c33c0 __float128 0f SECT 08 0000 [.const_data] vtable for AMDRadeonX4000_AMDFPEncryptMsg::MetaClass 00000000003c2980 __float128 0f SECT 08 0000 [.const_data] vtable for AMDRadeonX4000_AMDFPGetCertMsg::MetaClass 00000000003c2ea0 __float128 0f SECT 08 0000 [.const_data] vtable for AMDRadeonX4000_AMDFPTestKeyMsg::MetaClass 00000000003a2f70 __float128 0f SECT 08 0000 [.const_data] vtable for AMDRadeonX4000_AMDNullHWEngine::MetaClass 00000000003a91e0 __float128 0f SECT 08 0000 [.const_data] vtable for AMDRadeonX4000_AMDPM4HWChannel::MetaClass 00000000003c1060 __float128 0f SECT 08 0000 [.const_data] vtable for AMDRadeonX4000_AMDSMLInterface::MetaClass 00000000003a9940 __float128 0f SECT 08 0000 [.const_data] vtable for AMDRadeonX4000_AMDSPUHWChannel::MetaClass 00000000003a1bd0 __float128 0f SECT 08 0000 [.const_data] vtable for AMDRadeonX4000_AMDUVDHWChannel::MetaClass 00000000003aa0f0 __float128 0f SECT 08 0000 [.const_data] vtable for AMDRadeonX4000_AMDVCEHWChannel::MetaClass 00000000003a3770 __float128 0f SECT 08 0000 [.const_data] vtable for AMDRadeonX4000_IAMDHWInterface::MetaClass 00000000003a4440 __float128 0f SECT 08 0000 [.const_data] vtable for AMDRadeonX4000_IAMDHWRegisters::MetaClass 00000000003a4f90 __float128 0f SECT 08 0000 [.const_data] vtable for AMDRadeonX4000_IAMDHWSemaphore::MetaClass 00000000003a5690 __float128 0f SECT 08 0000 [.const_data] vtable for AMDRadeonX4000_IAMDHWUtilities::MetaClass 00000000003a6550 __float128 0f SECT 08 0000 [.const_data] vtable for AMDRadeonX4000_IAMDHWVMContext::MetaClass 000000000038b940 __float128 0f SECT 08 0000 [.const_data] vtable for AMDRadeonX4000_AMDAccelResource::MetaClass 00000000003a2940 __float128 0f SECT 08 0000 [.const_data] vtable for AMDRadeonX4000_AMDNullHWChannel::MetaClass 000000000038fa70 __float128 0f SECT 08 0000 [.const_data] vtable for AMDRadeonX4000_AMDSPUAppContext::MetaClass 00000000003c0d10 __float128 0f SECT 08 0000 [.const_data] vtable for AMDRadeonX4000_IAMDSMLInterface::MetaClass 000000000038df90 __float128 0f SECT 08 0000 [.const_data] vtable for AMDRadeonX4000_AMDAccel2DContext::MetaClass 0000000000392b10 __float128 0f SECT 08 0000 [.const_data] vtable for AMDRadeonX4000_AMDAccelCLContext::MetaClass 00000000003935e0 __float128 0f SECT 08 0000 [.const_data] vtable for AMDRadeonX4000_AMDAccelMemoryMap::MetaClass 0000000000393060 __float128 0f SECT 08 0000 [.const_data] vtable for AMDRadeonX4000_AMDAccelSysMemory::MetaClass 0000000000393340 __float128 0f SECT 08 0000 [.const_data] vtable for AMDRadeonX4000_AMDAccelVidMemory::MetaClass 00000000003c26f0 __float128 0f SECT 08 0000 [.const_data] vtable for AMDRadeonX4000_AMDHDCPGetCertMsg::MetaClass 00000000003a25e0 __float128 0f SECT 08 0000 [.const_data] vtable for AMDRadeonX4000_AMDHWAlignManager::MetaClass 00000000003c3710 __float128 0f SECT 08 0000 [.const_data] vtable for AMDRadeonX4000_AMDSMLSIInterface::MetaClass 00000000003c51b0 __float128 0f SECT 08 0000 [.const_data] vtable for AMDRadeonX4000_AMDSMLVIInterface::MetaClass 000000000038c8c0 __float128 0f SECT 08 0000 [.const_data] vtable for AMDRadeonX4000_AMDAccelStatistics::MetaClass 000000000038f7f0 __float128 0f SECT 08 0000 [.const_data] vtable for AMDRadeonX4000_AMDAccelUVDContext::MetaClass 0000000000390280 __float128 0f SECT 08 0000 [.const_data] vtable for AMDRadeonX4000_AMDAccelVCEContext::MetaClass 00000000003a7630 __float128 0f SECT 08 0000 [.const_data] vtable for AMDRadeonX4000_AMDHWSemaphorePool::MetaClass 00000000003a73c0 __float128 0f SECT 08 0000 [.const_data] vtable for AMDRadeonX4000_AMDNullHWSemaphore::MetaClass 00000000003c4480 __float128 0f SECT 08 0000 [.const_data] vtable for AMDRadeonX4000_AMDSMLCIKInterface::MetaClass 00000000003a41c0 __float128 0f SECT 08 0000 [.const_data] vtable for AMDRadeonX4000_IAMDHWAlignManager::MetaClass 00000000003c2460 __float128 0f SECT 08 0000 [.const_data] vtable for AMDRadeonX4000_AMDHDCPGetStatusMsg::MetaClass 00000000003a51e0 __float128 0f SECT 08 0000 [.const_data] vtable for AMDRadeonX4000_IAMDHWSemaphorePool::MetaClass 0000000000391a40 __float128 0f SECT 08 0000 [.const_data] vtable for AMDRadeonX4000_IAMDStatisticsGroup::MetaClass 000000000038b500 __float128 0f SECT 08 0000 [.const_data] vtable for AMDRadeonX4000_AMDAccelEventMachine::MetaClass 000000000038f160 __float128 0f SECT 08 0000 [.const_data] vtable for AMDRadeonX4000_AMDAccelVideoContext::MetaClass 0000000000390a00 __float128 0f SECT 08 0000 [.const_data] vtable for AMDRadeonX4000_AMDAtomicBlitManager::MetaClass 00000000003a7880 __float128 0f SECT 08 0000 [.const_data] vtable for AMDRadeonX4000_AMDHWSemaphoreMemMgr::MetaClass 00000000003c1f40 __float128 0f SECT 08 0000 [.const_data] vtable for AMDRadeonX4000_AMDHDCPOpenSessionMsg::MetaClass 00000000003a8aa0 __float128 0f SECT 08 0000 [.const_data] vtable for AMDRadeonX4000_AMDPM4CommandsUtility::MetaClass 0000000000390740 __float128 0f SECT 08 0000 [.const_data] vtable for AMDRadeonX4000_IAMDAtomicBlitManager::MetaClass 00000000003a5430 __float128 0f SECT 08 0000 [.const_data] vtable for AMDRadeonX4000_IAMDHWSemaphoreMemMgr::MetaClass 0000000000391550 __float128 0f SECT 08 0000 [.const_data] vtable for AMDRadeonX4000_IAMDStatisticsManager::MetaClass 000000000038b110 __float128 0f SECT 08 0000 [.const_data] vtable for AMDRadeonX4000_AMDAccelDisplayMachine::MetaClass 00000000003c3130 __float128 0f SECT 08 0000 [.const_data] vtable for AMDRadeonX4000_AMDFPReleaseSessionMsg::MetaClass 0000000000389890 __float128 0f SECT 08 0000 [.const_data] vtable for AMDRadeonX4000_AMDGraphicsAccelerator::MetaClass 00000000003c21d0 __float128 0f SECT 08 0000 [.const_data] vtable for AMDRadeonX4000_AMDHDCPCloseSessionMsg::MetaClass 0000000000391f20 __float128 0f SECT 08 0000 [.const_data] vtable for AMDRadeonX4000_AMDHWChannelStatsGroup::MetaClass 00000000003a5930 __float128 0f SECT 08 0000 [.const_data] vtable for AMDRadeonX4000_IAMDPM4CommandsUtility::MetaClass 0000000000391cb0 __float128 0f SECT 08 0000 [.const_data] vtable for AMDRadeonX4000_AMDAccelStatisticsGroup::MetaClass 000000000038e520 __float128 0f SECT 08 0000 [.const_data] vtable for AMDRadeonX4000_AMDInterruptEventSource::MetaClass 000000000038c610 __float128 0f SECT 08 0000 [.const_data] vtable for AMDRadeonX4000_AMDAccelSharedUserClient::MetaClass 000000000038e1d0 __float128 0f SECT 08 0000 [.const_data] vtable for AMDRadeonX4000_AMDAccelCommandBufferPool::MetaClass 00000000003917d0 __float128 0f SECT 08 0000 [.const_data] vtable for AMDRadeonX4000_AMDAccelStatisticsManager::MetaClass 00000000003a1800 __float128 0f SECT 08 0000 [.const_data] vtable for AMDRadeonX4000_AMDUVDInterruptEventSource::MetaClass 00000000003ab5c0 __float128 0f SECT 08 0000 [.const_data] vtable for AMDSIVMM::MetaClass 00000000003ba450 __float128 0f SECT 08 0000 [.const_data] vtable for AMDVIVMM::MetaClass 00000000000949bf __float128 0f SECT 01 0000 [.text] ___divdi3 000000000009383c __float128 0f SECT 01 0000 [.text] ___isfinited 0000000000093822 __float128 0f SECT 01 0000 [.text] ___isfinitef 00000000000937ee __float128 0f SECT 01 0000 [.text] ___isnand 00000000000937c5 __float128 0f SECT 01 0000 [.text] ___isnanf 00000000000949fb __float128 0f SECT 01 0000 [.text] ___moddi3 0000000000094439 __float128 0f SECT 01 0000 [.text] ___qdivrem 00000000004d25e0 __float128 0f SECT 09 0000 [.data] _aDowngradeSuperSUMO_GoldenRegisterSettings 0000000000122e89 __float128 0f SECT 01 0000 [.text] _aes_byte_sub 000000000012375f __float128 0f SECT 01 0000 [.text] _aes_cbc_decrypt 0000000000123691 __float128 0f SECT 01 0000 [.text] _aes_cbc_encrypt 000000000012382e __float128 0f SECT 01 0000 [.text] _aes_cntr_encrypt 00000000001234e4 __float128 0f SECT 01 0000 [.text] _aes_dec 0000000000123995 __float128 0f SECT 01 0000 [.text] _aes_dm_hash 000000000012362d __float128 0f SECT 01 0000 [.text] _aes_ecb_decrypt 00000000001235c9 __float128 0f SECT 01 0000 [.text] _aes_ecb_encrypt 0000000000122f95 __float128 0f SECT 01 0000 [.text] _aes_enc 00000000001232a3 __float128 0f SECT 01 0000 [.text] _aes_invbyte_sub 000000000012323f __float128 0f SECT 01 0000 [.text] _aes_invshift_row 0000000000122f0f __float128 0f SECT 01 0000 [.text] _aes_mix_column 000000000052cd60 __float128 0f SECT 09 0000 [.data] _aes_rsbox 000000000052cc60 __float128 0f SECT 09 0000 [.data] _aes_sbox 0000000000122eab __float128 0f SECT 01 0000 [.text] _aes_shift_row 00000000003c60a0 __float128 0f SECT 09 0000 [.data] _ati_format_info_table 00000000003c69b0 __float128 0f SECT 09 0000 [.data] _ati_si_format_info_table 00000000003c5f80 __float128 0f SECT 09 0000 [.data] _cailEngines 00000000000f375c __float128 0f SECT 01 0000 [.text] _cailReadRomImage 000000000009385d __float128 0f SECT 01 0000 [.text] _ceil 00000000004d3430 __float128 0f SECT 09 0000 [.data] _checkFireGLValues 0000000000120f85 __float128 0f SECT 01 0000 [.text] _cmdCall_Table 0000000000120ee3 __float128 0f SECT 01 0000 [.text] _cmdDelay_Microsec 0000000000120eb6 __float128 0f SECT 01 0000 [.text] _cmdDelay_Millisec 0000000000121001 __float128 0f SECT 01 0000 [.text] _cmdNOP_ 0000000000120df3 __float128 0f SECT 01 0000 [.text] _cmdSetDataBlock 0000000000120e54 __float128 0f SECT 01 0000 [.text] _cmdSet_ATI_Port 0000000000120e71 __float128 0f SECT 01 0000 [.text] _cmdSet_Reg_Block 0000000000120e8f __float128 0f SECT 01 0000 [.text] _cmdSet_X_Port 0000000000123e4e __float128 0f SECT 01 0000 [.text] _copy128 0000000000093905 __float128 0f SECT 01 0000 [.text] _copysign 000000000012159c __float128 0f SECT 01 0000 [.text] _driveClock 000000000012166b __float128 0f SECT 01 0000 [.text] _driveData 0000000000121a36 __float128 0f SECT 01 0000 [.text] _enableClock 0000000000121add __float128 0f SECT 01 0000 [.text] _enableData 00000000004d1830 __float128 0f SECT 09 0000 [.data] _evergreen_cs_data 00000000000f098c __float128 0f SECT 01 0000 [.text] _execute_easf_bios_function 00000000000938e8 __float128 0f SECT 01 0000 [.text] _fabs 00000000000936b1 __float128 0f SECT 01 0000 [.text] _floor 0000000000093a65 __float128 0f SECT 01 0000 [.text] _frexp 00000000003c5f70 __float128 0f SECT 09 0000 [.data] _gAMDHWMemoryAllocationTypeNames 00000000003c5f30 __float128 0f SECT 09 0000 [.data] _gAMDHwEngineTypeNames 00000000003c5c80 __float128 0f SECT 09 0000 [.data] _gLogLevelModuleNames 00000000003c5e10 __float128 0f SECT 09 0000 [.data] _gLogLevelNames 000000000052ce60 __float128 0f SECT 0a 0000 [__DATA.__common] _g_acceleratorCount 000000000052d384 __float128 0f SECT 0a 0000 [__DATA.__common] _g_klogRefCount 000000000052d250 __float128 0f SECT 0a 0000 [__DATA.__common] _g_lvntProcNameBuff 000000000052d2c0 __float128 0f SECT 0a 0000 [__DATA.__common] _g_pLogLevelMasks 0000000000123129 __float128 0f SECT 01 0000 [.text] _generate_aes_round_keys 0000000000121376 __float128 0f SECT 01 0000 [.text] _getClock 0000000000121489 __float128 0f SECT 01 0000 [.text] _getData 0000000000122d7a __float128 0f SECT 01 0000 [.text] _inc_cntr 00000000000f1c9e __float128 0f SECT 01 0000 [.text] _init_rlc_clear_state_buffer_for_llano_trinity 000000000012232c __float128 0f SECT 01 0000 [.text] _isLineUp 00000000003c5fd0 __float128 0f SECT 09 0000 [.data] _kmod_info 0000000000093a40 __float128 0f SECT 01 0000 [.text] _ldexp 0000000000122def __float128 0f SECT 01 0000 [.text] _next_aes_enc_key 00000000004413a0 __float128 0f SECT 09 0000 [.data] _ni_cs_data 0000000000093bcc __float128 0f SECT 01 0000 [.text] _pow 0000000000093bb5 __float128 0f SECT 01 0000 [.text] _powf 0000000000122351 __float128 0f SECT 01 0000 [.text] _processI2CDebugRequest 000000000012196e __float128 0f SECT 01 0000 [.text] _readBit 0000000000121d02 __float128 0f SECT 01 0000 [.text] _readBuffer 0000000000121be8 __float128 0f SECT 01 0000 [.text] _readByte 00000000003d7058 __float128 0f SECT 09 0000 [.data] _sBonaireGbMacroTileModeTbl 00000000003d7048 __float128 0f SECT 09 0000 [.data] _sBonaireGbTileModeTbl 00000000003e3240 __float128 0f SECT 09 0000 [.data] _sCapeVerdeGbTileModeTbl 00000000003e6f88 __float128 0f SECT 09 0000 [.data] _sCarrizoGbMacroTileModeTbl 00000000003e6f78 __float128 0f SECT 09 0000 [.data] _sCarrizoGbTileModeTbl 00000000004438e0 __float128 0f SECT 09 0000 [.data] _sGodavariCsRegWrite 0000000000443c70 __float128 0f SECT 09 0000 [.data] _sGodavariCsRegWriteList 0000000000443f50 __float128 0f SECT 09 0000 [.data] _sGodavariMetaDataList 00000000004499a0 __float128 0f SECT 09 0000 [.data] _sHawaiiGbMacroTileModeTbl 0000000000449990 __float128 0f SECT 09 0000 [.data] _sHawaiiGbTileModeTbl 0000000000459ad8 __float128 0f SECT 09 0000 [.data] _sIcelandGbMacroTileModeTbl 0000000000459ac8 __float128 0f SECT 09 0000 [.data] _sIcelandGbTileModeTbl 00000000004b7230 __float128 0f SECT 09 0000 [.data] _sKalindiCsRegWrite 00000000004b75c0 __float128 0f SECT 09 0000 [.data] _sKalindiCsRegWriteList 00000000004b78a0 __float128 0f SECT 09 0000 [.data] _sKalindiMetaDataList 00000000004bad40 __float128 0f SECT 09 0000 [.data] _sOlandGbTileModeTbl 00000000004c1610 __float128 0f SECT 09 0000 [.data] _sSpectreGbMacroTileModeTbl 00000000004c1600 __float128 0f SECT 09 0000 [.data] _sSpectreGbTileModeTbl 00000000004d3d40 __float128 0f SECT 09 0000 [.data] _sTahitiGbTileModeTbl 00000000004d7848 __float128 0f SECT 09 0000 [.data] _sTongaGbMacroTileModeTbl 00000000004d7838 __float128 0f SECT 09 0000 [.data] _sTongaGbTileModeTbl 0000000000093931 __float128 0f SECT 01 0000 [.text] _scalbn 00000000001088e8 __float128 0f SECT 01 0000 [.text] _setup_vce_clock_gating_mode 0000000000094a5c __float128 0f SECT 01 0000 [.text] _si_window_mode_to_ati_format 0000000000123d49 __float128 0f SECT 01 0000 [.text] _simple_dm_hash 0000000000093af1 __float128 0f SECT 01 0000 [.text] _sqrt 00000000001a91d0 __float128 0f SECT 03 0000 [.const] _ulBIOSScratchRegistersPreserveMaskAtom 0000000000459a70 __float128 0f SECT 09 0000 [.data] _ulIcelandUcodeLoadOrderTbl 00000000000f35ae __float128 0f SECT 01 0000 [.text] _ulReadMmRegisterUlong 00000000000f3703 __float128 0f SECT 01 0000 [.text] _ulReadMmRegisterUlongDirectIO 00000000000f3653 __float128 0f SECT 01 0000 [.text] _ulReadMmRegisterUlongViaAddr 00000000000daa12 __float128 0f SECT 01 0000 [.text] _ulRead_RialtoMmReg 00000000000daad8 __float128 0f SECT 01 0000 [.text] _ulRead_RialtoPCIEEndPointCFGReg 00000000000daa71 __float128 0f SECT 01 0000 [.text] _ulRead_RialtoPCIERootComplexCFGReg 00000000004b7200 __float128 0f SECT 09 0000 [.data] _ulUcodeLoadOrderTbl 0000000000121370 __float128 0f SECT 01 0000 [.text] _usleep 00000000000e7a97 __float128 0f SECT 01 0000 [.text] _vGetRegulation 00000000000f3677 __float128 0f SECT 01 0000 [.text] _vWriteMmRegisterUlong 00000000000f371e __float128 0f SECT 01 0000 [.text] _vWriteMmRegisterUlongDirectIO 00000000000f3667 __float128 0f SECT 01 0000 [.text] _vWriteMmRegisterUlongViaAddr 00000000000daa3f __float128 0f SECT 01 0000 [.text] _vWrite_RialtoMmReg 00000000000dab09 __float128 0f SECT 01 0000 [.text] _vWrite_RialtoPCIEEndPointCFGReg 00000000000daaa2 __float128 0f SECT 01 0000 [.text] _vWrite_RialtoPCIERootComplexCFGReg 0000000000108794 __float128 0f SECT 01 0000 [.text] _validate_vce_firmware 000000000012173a __float128 0f SECT 01 0000 [.text] _waitClock 0000000000121784 __float128 0f SECT 01 0000 [.text] _waitData 0000000000094a39 __float128 0f SECT 01 0000 [.text] _window_mode_to_ati_format 0000000000121866 __float128 0f SECT 01 0000 [.text] _writeBit 0000000000121c62 __float128 0f SECT 01 0000 [.text] _writeBuffer 0000000000121b85 __float128 0f SECT 01 0000 [.text] _writeByte 0000000000123e65 __float128 0f SECT 01 0000 [.text] _xor128 0000000000123e7f __float128 0f SECT 01 0000 [.text] _xor32 0000000000123e39 __float128 0f SECT 01 0000 [.text] _zero128 0000000000000000 __float128 01 UND 00 fe00 _IODelay 0000000000000000 __float128 01 UND 00 fe00 _IOFlushProcessorCache 0000000000000000 __float128 01 UND 00 fe00 _IOFree 0000000000000000 __float128 01 UND 00 fe00 _IOFreeAligned 0000000000000000 __float128 01 UND 00 fe00 _IOFreePageable 0000000000000000 __float128 01 UND 00 fe00 _IOLockAlloc 0000000000000000 __float128 01 UND 00 fe00 _IOLockFree 0000000000000000 __float128 01 UND 00 fe00 _IOLockLock 0000000000000000 __float128 01 UND 00 fe00 _IOLockUnlock 0000000000000000 __float128 01 UND 00 fe00 _IOLog 0000000000000000 __float128 01 UND 00 fe00 _IOMalloc 0000000000000000 __float128 01 UND 00 fe00 _IOMallocAligned 0000000000000000 __float128 01 UND 00 fe00 _IOMallocPageable 0000000000000000 __float128 01 UND 00 fe00 _IOSleep 0000000000000000 __float128 01 UND 00 fe00 _OSAddAtomic 0000000000000000 __float128 01 UND 00 fe00 _OSDecrementAtomic 0000000000000000 __float128 01 UND 00 fe00 _OSIncrementAtomic 0000000000000000 __float128 01 UND 00 fe00 IODTFindSlotName(IORegistryEntry*, unsigned int) 0000000000000000 __float128 01 UND 00 fe00 IOWorkLoop::workLoop() 0000000000000000 __float128 01 UND 00 fe00 IOAccelTask::gMetaClass 0000000000000000 __float128 01 UND 00 fe00 IOAccelTask::freeToAllocGPUAddress(IOAccelMemoryMap*) 0000000000000000 __float128 01 UND 00 fe00 IOAccelTask::freeAllSysMemoryMappings() 0000000000000000 __float128 01 UND 00 fe00 IOAccelTask::freeAllVidMemoryMappings() 0000000000000000 __float128 01 UND 00 fe00 IOAccelTask::describeDriverAllocations(IOAccelAllocationInfo*) 0000000000000000 __float128 01 UND 00 fe00 IOAccelTask::freeWaitToAllocGPUAddress(IOAccelMemoryMap*, bool) 0000000000000000 __float128 01 UND 00 fe00 IOAccelTask::init(IOGraphicsAccelerator2*, unsigned int, IORangeAllocator**) 0000000000000000 __float128 01 UND 00 fe00 IOAccelTask::IOAccelTask(OSMetaClass const*) 0000000000000000 __float128 01 UND 00 fe00 IOAccelTask::~IOAccelTask() 0000000000000000 __float128 01 UND 00 fe00 IOMemoryMap::getPhysicalAddress() 0000000000000000 __float128 01 UND 00 fe00 IOPCIDevice::extendedConfigRead8(unsigned long long) 0000000000000000 __float128 01 UND 00 fe00 IOPCIDevice::extendedConfigRead16(unsigned long long) 0000000000000000 __float128 01 UND 00 fe00 IOPCIDevice::extendedConfigRead32(unsigned long long) 0000000000000000 __float128 01 UND 00 fe00 IOPCIDevice::extendedConfigWrite8(unsigned long long, unsigned char) 0000000000000000 __float128 01 UND 00 fe00 IOPCIDevice::extendedConfigWrite16(unsigned long long, unsigned short) 0000000000000000 __float128 01 UND 00 fe00 IOPCIDevice::extendedConfigWrite32(unsigned long long, unsigned int) 0000000000000000 __float128 01 UND 00 fe00 OSMetaClass::allocClassWithName(char const*) 0000000000000000 __float128 01 UND 00 fe00 OSMetaClass::_RESERVEDOSMetaClass0() 0000000000000000 __float128 01 UND 00 fe00 OSMetaClass::_RESERVEDOSMetaClass1() 0000000000000000 __float128 01 UND 00 fe00 OSMetaClass::_RESERVEDOSMetaClass2() 0000000000000000 __float128 01 UND 00 fe00 OSMetaClass::_RESERVEDOSMetaClass3() 0000000000000000 __float128 01 UND 00 fe00 OSMetaClass::_RESERVEDOSMetaClass4() 0000000000000000 __float128 01 UND 00 fe00 OSMetaClass::_RESERVEDOSMetaClass5() 0000000000000000 __float128 01 UND 00 fe00 OSMetaClass::_RESERVEDOSMetaClass6() 0000000000000000 __float128 01 UND 00 fe00 OSMetaClass::_RESERVEDOSMetaClass7() 0000000000000000 __float128 01 UND 00 fe00 OSMetaClass::OSMetaClass(char const*, OSMetaClass const*, unsigned int) 0000000000000000 __float128 01 UND 00 fe00 OSMetaClass::~OSMetaClass() 0000000000000000 __float128 01 UND 00 fe00 IODMACommand::OutputHost64(IODMACommand*, IODMACommand::Segment64, void*, unsigned int) 0000000000000000 __float128 01 UND 00 fe00 IOUserClient::clientDied() 0000000000000000 __float128 01 UND 00 fe00 IOUserClient::getService() 0000000000000000 __float128 01 UND 00 fe00 IOUserClient::initWithTask(task*, void*, unsigned int) 0000000000000000 __float128 01 UND 00 fe00 IOUserClient::initWithTask(task*, void*, unsigned int, OSDictionary*) 0000000000000000 __float128 01 UND 00 fe00 IOUserClient::connectClient(IOUserClient*) 0000000000000000 __float128 01 UND 00 fe00 IOUserClient::externalMethod(unsigned int, IOExternalMethodArguments*, IOExternalMethodDispatch*, OSObject*, void*) 0000000000000000 __float128 01 UND 00 fe00 IOUserClient::clientMemoryForType(unsigned int, unsigned int*, IOMemoryDescriptor**) 0000000000000000 __float128 01 UND 00 fe00 IOUserClient::exportObjectToClient(task*, OSObject*, OSObject**) 0000000000000000 __float128 01 UND 00 fe00 IOUserClient::_RESERVEDIOUserClient0() 0000000000000000 __float128 01 UND 00 fe00 IOUserClient::_RESERVEDIOUserClient1() 0000000000000000 __float128 01 UND 00 fe00 IOUserClient::_RESERVEDIOUserClient2() 0000000000000000 __float128 01 UND 00 fe00 IOUserClient::_RESERVEDIOUserClient3() 0000000000000000 __float128 01 UND 00 fe00 IOUserClient::_RESERVEDIOUserClient4() 0000000000000000 __float128 01 UND 00 fe00 IOUserClient::_RESERVEDIOUserClient5() 0000000000000000 __float128 01 UND 00 fe00 IOUserClient::_RESERVEDIOUserClient6() 0000000000000000 __float128 01 UND 00 fe00 IOUserClient::_RESERVEDIOUserClient7() 0000000000000000 __float128 01 UND 00 fe00 IOUserClient::_RESERVEDIOUserClient8() 0000000000000000 __float128 01 UND 00 fe00 IOUserClient::_RESERVEDIOUserClient9() 0000000000000000 __float128 01 UND 00 fe00 IOUserClient::_RESERVEDIOUserClient10() 0000000000000000 __float128 01 UND 00 fe00 IOUserClient::_RESERVEDIOUserClient11() 0000000000000000 __float128 01 UND 00 fe00 IOUserClient::_RESERVEDIOUserClient12() 0000000000000000 __float128 01 UND 00 fe00 IOUserClient::_RESERVEDIOUserClient13() 0000000000000000 __float128 01 UND 00 fe00 IOUserClient::_RESERVEDIOUserClient14() 0000000000000000 __float128 01 UND 00 fe00 IOUserClient::_RESERVEDIOUserClient15() 0000000000000000 __float128 01 UND 00 fe00 IOUserClient::getExternalTrapForIndex(unsigned int) 0000000000000000 __float128 01 UND 00 fe00 IOUserClient::getNotificationSemaphore(unsigned int, semaphore**) 0000000000000000 __float128 01 UND 00 fe00 IOUserClient::getTargetAndTrapForIndex(IOService**, unsigned int) 0000000000000000 __float128 01 UND 00 fe00 IOUserClient::registerNotificationPort(ipc_port*, unsigned int, unsigned int) 0000000000000000 __float128 01 UND 00 fe00 IOUserClient::registerNotificationPort(ipc_port*, unsigned int, unsigned long long) 0000000000000000 __float128 01 UND 00 fe00 IOUserClient::getExternalMethodForIndex(unsigned int) 0000000000000000 __float128 01 UND 00 fe00 IOUserClient::getExternalAsyncMethodForIndex(unsigned int) 0000000000000000 __float128 01 UND 00 fe00 IOUserClient::getAsyncTargetAndMethodForIndex(IOService**, unsigned int) 0000000000000000 __float128 01 UND 00 fe00 IOUserClient::init(OSDictionary*) 0000000000000000 __float128 01 UND 00 fe00 IOUserClient::init() 0000000000000000 __float128 01 UND 00 fe00 OSDictionary::metaClass 0000000000000000 __float128 01 UND 00 fe00 IOAccelMemory::finishAllEvent() 0000000000000000 __float128 01 UND 00 fe00 IOAccelMemory::createMappingInTask(IOAccelTask*, unsigned int) 0000000000000000 __float128 01 UND 00 fe00 IOAccelMemory::init(IOGraphicsAccelerator2*) 0000000000000000 __float128 01 UND 00 fe00 IOAccelMemory::prepare() 0000000000000000 __float128 01 UND 00 fe00 IOAccelMemory::setFlags(unsigned int) 0000000000000000 __float128 01 UND 00 fe00 IOEventSource::_RESERVEDIOEventSource0() 0000000000000000 __float128 01 UND 00 fe00 IOEventSource::_RESERVEDIOEventSource1() 0000000000000000 __float128 01 UND 00 fe00 IOEventSource::_RESERVEDIOEventSource2() 0000000000000000 __float128 01 UND 00 fe00 IOEventSource::_RESERVEDIOEventSource3() 0000000000000000 __float128 01 UND 00 fe00 IOEventSource::_RESERVEDIOEventSource4() 0000000000000000 __float128 01 UND 00 fe00 IOEventSource::_RESERVEDIOEventSource5() 0000000000000000 __float128 01 UND 00 fe00 IOEventSource::_RESERVEDIOEventSource6() 0000000000000000 __float128 01 UND 00 fe00 IOEventSource::_RESERVEDIOEventSource7() 0000000000000000 __float128 01 UND 00 fe00 IOEventSource::init(OSObject*, void (*)(OSObject*, ...)) 0000000000000000 __float128 01 UND 00 fe00 IOEventSource::setNext(IOEventSource*) 0000000000000000 __float128 01 UND 00 fe00 IOEventSource::setAction(void (*)(OSObject*, ...)) 0000000000000000 __float128 01 UND 00 fe00 IOFramebuffer::addFramebufferNotification(int (*)(OSObject*, void*, IOFramebuffer*, int, void*), OSObject*, void*) 0000000000000000 __float128 01 UND 00 fe00 IOFramebuffer::metaClass 0000000000000000 __float128 01 UND 00 fe00 IOAccelDevice2::gMetaClass 0000000000000000 __float128 01 UND 00 fe00 IOAccelDevice2::clientClose() 0000000000000000 __float128 01 UND 00 fe00 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01 UND 00 0400 _fread 0000000000000000 __float128 01 UND 00 0400 _free 0000000000000000 __float128 01 UND 00 0400 _fwrite 0000000000000000 __float128 01 UND 00 0400 _getc 0000000000000000 __float128 01 UND 00 0100 _kCFAllocatorDefault 0000000000000000 __float128 01 UND 00 0400 _ldexp 0000000000000000 __float128 01 UND 00 0400 _log 0000000000000000 __float128 01 UND 00 0400 _logf 0000000000000000 __float128 01 UND 00 0400 _longjmp 0000000000000000 __float128 01 UND 00 0400 _malloc 0000000000000000 __float128 01 UND 00 0400 _memcmp 0000000000000000 __float128 01 UND 00 0400 _memcpy 0000000000000000 __float128 01 UND 00 0400 _memmove 0000000000000000 __float128 01 UND 00 0400 _memset 0000000000000000 __float128 01 UND 00 0400 _memset_pattern16 0000000000000000 __float128 01 UND 00 0400 _pow 0000000000000000 __float128 01 UND 00 0400 _printf 0000000000000000 __float128 01 UND 00 0400 _pthread_mutex_destroy 0000000000000000 __float128 01 UND 00 0400 _pthread_mutex_init 0000000000000000 __float128 01 UND 00 0400 _pthread_mutex_lock 0000000000000000 __float128 01 UND 00 0400 _pthread_mutex_unlock 0000000000000000 __float128 01 UND 00 0400 _puts 0000000000000000 __float128 01 UND 00 0400 _realloc 0000000000000000 __float128 01 UND 00 0400 _setjmp 0000000000000000 __float128 01 UND 00 0400 _sin 0000000000000000 __float128 01 UND 00 0400 _sprintf 0000000000000000 __float128 01 UND 00 0400 _strchr 0000000000000000 __float128 01 UND 00 0400 _strcmp 0000000000000000 __float128 01 UND 00 0400 _strcpy 0000000000000000 __float128 01 UND 00 0400 _strlen 0000000000000000 __float128 01 UND 00 0400 _strncat 0000000000000000 __float128 01 UND 00 0400 _strncmp 0000000000000000 __float128 01 UND 00 0400 _strncpy 0000000000000000 __float128 01 UND 00 0400 _strnstr 0000000000000000 __float128 01 UND 00 0400 _strrchr 0000000000000000 __float128 01 UND 00 0400 _strstr 0000000000000000 __float128 01 UND 00 0400 _strtol 0000000000000000 __float128 01 UND 00 0400 _strtoul 0000000000000000 __float128 01 UND 00 0400 _vsnprintf 0000000000000000 __float128 01 UND 00 0400 dyld_stub_binder i386: file format mach-unsigned __int128-i386 SYMBOL TABLE: 05614542 double 3c OPT 00 0000 radr://5614542 0002347f __float128 0f SECT 01 0000 [.text] _assembleAMDIL 00000000 __float128 01 UND 00 0100 _CFArrayCreateCopy 00000000 __float128 01 UND 00 0100 _CFArrayGetCount 00000000 __float128 01 UND 00 0100 _CFArrayGetValueAtIndex 00000000 __float128 01 UND 00 0100 _CFDataGetBytePtr 00000000 __float128 01 UND 00 0100 _CFDataGetBytes 00000000 __float128 01 UND 00 0100 _CFDataGetLength 00000000 __float128 01 UND 00 0100 _CFDataGetTypeID 00000000 __float128 01 UND 00 0100 _CFDictionaryApplyFunction 00000000 __float128 01 UND 00 0100 _CFDictionaryGetValue 00000000 __float128 01 UND 00 0100 _CFErrorCopyDescription 00000000 __float128 01 UND 00 0100 _CFGetTypeID 00000000 __float128 01 UND 00 0100 _CFNumberGetValue 00000000 __float128 01 UND 00 0100 _CFPropertyListCreateData 00000000 __float128 01 UND 00 0100 _CFRelease 00000000 __float128 01 UND 00 0100 _CFRetain 00000000 __float128 01 UND 00 0100 _CFStringCreateWithCString 00000000 __float128 01 UND 00 0100 _CFStringGetCString 00000000 __float128 01 UND 00 0100 _CFStringGetLength 00000000 __float128 01 UND 00 0100 _CFStringGetMaximumSizeForEncoding 00000000 __float128 01 UND 00 0200 _IOMasterPort 00000000 __float128 01 UND 00 0200 _IOObjectRelease 00000000 __float128 01 UND 00 0200 _IORegistryEntryCreateCFProperties 00000000 __float128 01 UND 00 0200 _IORegistryEntryFromPath 00000000 __float128 01 UND 00 0400 __DefaultRuneLocale 00000000 __float128 01 UND 00 0400 __Unwind_Resume 00000000 __float128 01 UND 00 0300 std::__1::__vector_base_common::__throw_length_error() const 00000000 __float128 01 UND 00 0300 std::logic_error::logic_error(char const*) 00000000 __float128 01 UND 00 0300 std::out_of_range::~out_of_range() 00000000 __float128 01 UND 00 0300 std::terminate() 00000000 __float128 01 UND 00 0380 typeinfo for std::out_of_range 00000000 __float128 01 UND 00 0300 vtable for __cxxabiv1::__class_type_info 00000000 __float128 01 UND 00 0300 vtable for __cxxabiv1::__si_class_type_info 00000000 __float128 01 UND 00 0300 vtable for __cxxabiv1::__vmi_class_type_info 00000000 __float128 01 UND 00 0300 vtable for std::out_of_range 00000000 __float128 01 UND 00 0380 operator delete[](void*) 00000000 __float128 01 UND 00 0380 operator delete(void*) 00000000 __float128 01 UND 00 0380 operator new[](unsigned long) 00000000 __float128 01 UND 00 0380 operator new(unsigned long) 00000000 __float128 01 UND 00 0400 ___assert_rtn 00000000 __float128 01 UND 00 0400 ___bzero 00000000 __float128 01 UND 00 0300 ___cxa_allocate_exception 00000000 __float128 01 UND 00 0300 ___cxa_begin_catch 00000000 __float128 01 UND 00 0300 ___cxa_call_unexpected 00000000 __float128 01 UND 00 0300 ___cxa_end_catch 00000000 __float128 01 UND 00 0300 ___cxa_free_exception 00000000 __float128 01 UND 00 0300 ___cxa_pure_virtual 00000000 __float128 01 UND 00 0300 ___cxa_rethrow 00000000 __float128 01 UND 00 0300 ___cxa_throw 00000000 __float128 01 UND 00 0400 ___error 00000000 __float128 01 UND 00 0400 ___fpclassifyd 00000000 __float128 01 UND 00 0300 ___gxx_personality_v0 00000000 __float128 01 UND 00 0400 ___maskrune 00000000 __float128 01 UND 00 0400 ___memcpy_chk 00000000 __float128 01 UND 00 0400 ___sprintf_chk 00000000 __float128 01 UND 00 0400 ___stack_chk_fail 00000000 __float128 01 UND 00 0400 ___stack_chk_guard 00000000 __float128 01 UND 00 0400 ___stderrp 00000000 __float128 01 UND 00 0400 ___stdinp 00000000 __float128 01 UND 00 0400 ___stdoutp 00000000 __float128 01 UND 00 0400 ___strcat_chk 00000000 __float128 01 UND 00 0400 ___strlcat_chk 00000000 __float128 01 UND 00 0400 ___strlcpy_chk 00000000 __float128 01 UND 00 0400 ___strncpy_chk 00000000 __float128 01 UND 00 0400 ___tolower 00000000 __float128 01 UND 00 0400 ___udivdi3 00000000 __float128 01 UND 00 0400 ___umoddi3 00000000 __float128 01 UND 00 0400 ___vsprintf_chk 00000000 __float128 01 UND 00 0400 _atof 00000000 __float128 01 UND 00 0400 _atoi 00000000 __float128 01 UND 00 0400 _bootstrap_port 00000000 __float128 01 UND 00 0400 _calloc 00000000 __float128 01 UND 00 0400 _ceil 00000000 __float128 01 UND 00 0400 _ceilf 00000000 __float128 01 UND 00 0400 _clearerr 00000000 __float128 01 UND 00 0400 _cos 00000000 __float128 01 UND 00 0400 _exit 00000000 __float128 01 UND 00 0400 _exp2 00000000 __float128 01 UND 00 0400 _fclose 00000000 __float128 01 UND 00 0400 _ferror 00000000 __float128 01 UND 00 0400 _fileno 00000000 __float128 01 UND 00 0400 _floor 00000000 __float128 01 UND 00 0400 _floorf 00000000 __float128 01 UND 00 0400 _fopen$UNIX2003 00000000 __float128 01 UND 00 0400 _fprintf 00000000 __float128 01 UND 00 0400 _fread 00000000 __float128 01 UND 00 0400 _free 00000000 __float128 01 UND 00 0400 _fwrite$UNIX2003 00000000 __float128 01 UND 00 0400 _getc 00000000 __float128 01 UND 00 0100 _kCFAllocatorDefault 00000000 __float128 01 UND 00 0400 _ldexp 00000000 __float128 01 UND 00 0400 _log 00000000 __float128 01 UND 00 0400 _logf 00000000 __float128 01 UND 00 0400 _longjmp 00000000 __float128 01 UND 00 0400 _malloc 00000000 __float128 01 UND 00 0400 _memcmp 00000000 __float128 01 UND 00 0400 _memcpy 00000000 __float128 01 UND 00 0400 _memmove 00000000 __float128 01 UND 00 0400 _memset 00000000 __float128 01 UND 00 0400 _memset_pattern16 00000000 __float128 01 UND 00 0400 _pow 00000000 __float128 01 UND 00 0400 _printf 00000000 __float128 01 UND 00 0400 _pthread_mutex_destroy 00000000 __float128 01 UND 00 0400 _pthread_mutex_init 00000000 __float128 01 UND 00 0400 _pthread_mutex_lock 00000000 __float128 01 UND 00 0400 _pthread_mutex_unlock 00000000 __float128 01 UND 00 0400 _puts 00000000 __float128 01 UND 00 0400 _realloc 00000000 __float128 01 UND 00 0400 _setjmp 00000000 __float128 01 UND 00 0400 _sin 00000000 __float128 01 UND 00 0400 _sprintf 00000000 __float128 01 UND 00 0400 _strchr 00000000 __float128 01 UND 00 0400 _strcmp 00000000 __float128 01 UND 00 0400 _strcpy 00000000 __float128 01 UND 00 0400 _strlen 00000000 __float128 01 UND 00 0400 _strncat 00000000 __float128 01 UND 00 0400 _strncmp 00000000 __float128 01 UND 00 0400 _strncpy 00000000 __float128 01 UND 00 0400 _strnstr 00000000 __float128 01 UND 00 0400 _strrchr 00000000 __float128 01 UND 00 0400 _strstr 00000000 __float128 01 UND 00 0400 _strtol 00000000 __float128 01 UND 00 0400 _strtoul 00000000 __float128 01 UND 00 0400 _vsnprintf 00000000 __float128 01 UND 00 0400 dyld_stub_binder As you can see it works together in a very simple way and attaches with all the components after main IOFramebuffer attach. Must have tool to retrieve more info: https://www.dropbox.com/s/hmrkmon2qq9fiyg/IDA%20Pro%206.6.140604.iso.zip?dl=0 With all of the info above (and especially that tool since it has the best decompiler in the world) you could in fast make a graphics accelerator... One more thing... gnu binutils targetting standard architecture installed in custom path can come very much in handy... A kext (Mach-O type 0x0B) can be interchanged between a bundle (0x08) and those tools can actually make with objcopy a working linkable object... Then you would have free reign... Have fun Edited February 27, 2015 by spakk Text content in to spoiler 2 Link to comment Share on other sites More sharing options...
ameris_cyning Posted February 15, 2015 Share Posted February 15, 2015 Can you please add a spoiler tag? Danke 1 Link to comment Share on other sites More sharing options...
angelol Posted February 16, 2015 Share Posted February 16, 2015 Does this mean that we can make a kext for Intel HD 2000? Sorry if this is a stupid question. I'm asking because you referred to intel GMA 950.. Link to comment Share on other sites More sharing options...
Andy Vandijck Posted February 16, 2015 Author Share Posted February 16, 2015 Does this mean that we can make a kext for Intel HD 2000? Sorry if this is a stupid question. I'm asking because you referred to intel GMA 950.. Yes, we could make kexts for any graphics cards.... If somebody would be willing to use the info and tools posted above it is definitely possible... 2 Link to comment Share on other sites More sharing options...
Huckleberry Pie Posted February 16, 2015 Share Posted February 16, 2015 There's such a thing as Pastebin, you know that? Seriously though, with most if not all of the info you gathered, this would pretty much pave the way for at least a rudimentary graphics driver, yes? And just how difficult would it be to do 3D? With Nvidia, AMD and Intel there's at least a starting point, but for lesser-known GPUs like those from SIS and S3 it would be more of a long shot, barring the fact that few if any use those anyway. 1 Link to comment Share on other sites More sharing options...
angelol Posted February 16, 2015 Share Posted February 16, 2015 Yes, we could make kexts for any graphics cards.... If somebody would be willing to use the info and tools posted above it is definitely possible... You made my day mate!!! God bless you and congratulations for such a great deal of work!!! 1 Link to comment Share on other sites More sharing options...
gils83 Posted February 16, 2015 Share Posted February 16, 2015 woohhhhhhh !! projet ambitieux avec ma HD 8400 alias R3 kabini 0x98301002 , j'ai déjà la 2D qui fonctionne sans changement de résolution et sans CI/QE . j'ai tout de même de fonctionnel : Safari != ok MediaFlashPlayer=ok QuickTime=ok j'ai un peu regarder ce désassembleur , ça pour moi très compliqué et un coup de pouce pour quelques explications seraient le bien venu woohhhhhhh !! ambitious project: Dwith my HD 8400 R3 aka Kabini 0x98301002, I've 2D works without changing resolution and without CI / QE.I still functional: Safari! = OkMediaFlashPlayer = okQuickTime = okI have a little look at what disassembler, that for me very complicated and a boost for some explanation would be welcome :D thanks Andy Link to comment Share on other sites More sharing options...
Andy Vandijck Posted February 16, 2015 Author Share Posted February 16, 2015 woohhhhhhh !! projet ambitieux avec ma HD 8400 alias R3 kabini 0x98301002 , j'ai déjà la 2D qui fonctionne sans changement de résolution et sans CI/QE . j'ai tout de même de fonctionnel : Safari != ok MediaFlashPlayer=ok QuickTime=ok j'ai un peu regarder ce désassembleur , ça pour moi très compliqué et un coup de pouce pour quelques explications seraient le bien venu woohhhhhhh !! ambitious project: D with my HD 8400 R3 aka Kabini 0x98301002, I've 2D works without changing resolution and without CI / QE. I still functional: Safari! = Ok MediaFlashPlayer = ok QuickTime = ok I have a little look at what disassembler, that for me very complicated and a boost for some explanation would be welcome thanks Andy CTRL+F5 ou file - produce file - produce C file... Then you'll have a rudimentary C source Mwahahaha! Link to comment Share on other sites More sharing options...
gils83 Posted February 16, 2015 Share Posted February 16, 2015 CTRL+F5 ou file - produce file - produce C file... Then you'll have a rudimentary C source Mwahahaha! ce n'est pas pour moi , je n'y comprends rien mais alors rien du tout !! je sais juste charger un programme sur un TSX Premium !! le C/C+/C++ Link to comment Share on other sites More sharing options...
Huckleberry Pie Posted February 17, 2015 Share Posted February 17, 2015 What if we do a clean-room reverse-engineered version of the drivers, and if possible or feasible, use what's in the open-source Radeon Linux drivers for the 3D stuff? The latter would be a little more involved, though. Link to comment Share on other sites More sharing options...
ameris_cyning Posted February 17, 2015 Share Posted February 17, 2015 Linux kernel is too different for us to port graphics drivers Link to comment Share on other sites More sharing options...
angelol Posted June 16, 2015 Share Posted June 16, 2015 Bumping this, any progress on the Intel HD 2000 frontier? Link to comment Share on other sites More sharing options...
Andy Vandijck Posted June 20, 2015 Author Share Posted June 20, 2015 Stoten deze, enige vooruitgang op de Intel HD 2000 frontier? ***Looking on Paypal*** Still no donations... hmm... no work is done thus... sorry... Link to comment Share on other sites More sharing options...
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