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[AMD] Yosemite Kernel Testing (for help use the Help Topic)

Duran Keeley

By Duran Keeley,
in OS X 10.10 (Yosemite)

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Bronya
Bronya
Posted
Posted
PLEASE  it is not necessary test ON 10.10.2-10.10.X with kernel version 10.10.0 ! 
Because in this new 10.10.2 new SYMBOLS ! This new symbol don't compatible with old kernel ! And you can get panic ! 

 

And why do you need new systems 10.10.2 ??? Don't be how small )))
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gils83
gils83
Posted
Posted

yes, i know that, to 10.10.1 with the new kernel very well works (many thanks)

10.10.2 a few optimizing , though this new topics would be interesting.....

:)

 

il ne sert à rien de bricoler 10.10.2 , il faut attendre les sources pour compiler le bon kernel 14C109 (10.1)  ;) 

 

no use to tinker 10.10.2, wait sources to compile the kernel proper 14C109 (10.1)  ;)

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gils83
gils83
Posted
Posted

Intel FSB = AMD HT-Link

 

 

 

:)

 

DMI Processor        

    manufacturer        AuthenticAMD

    model            AMD Athlon(tm) 5350 APU with Radeon(tm) R3

    clock speed        2100.0 MHz

    FSB speed        100.0 MHz

    multiplier        21.0x

 
no HT-Link ;)
 
bus HT-link chipset north/CPU ;) = 2600 Mhz  or 5200 MT/S : exemple ATI 790 FX  
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Kaya80
Kaya80
Posted
Posted

Ok, the disaster is done.....updated to 10.10.1, replaced kernel with rev.8, but most of app deosn't work, framework error or something like this....chameleon doesn't work and i can' check my boot options....please, help me, i had a perfect machine.....why i've updated!!....noooooooooo

 

Quite every app give me the same error, something concerning to webkit framework...i try Chameleon, Kext wizard, final cut, appstore, always the same error, can you help me please?

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lpukraine
lpukraine
Posted
Posted

 

OS X 10.10 - 10.10.1

 

Try to repair cpuid L3 cache for FX & Phenom

$ sysctl machdep.cpu
Last login: Sat Feb 14 14:47:23 on console
Mac-Pro:~ andrey$ sysctl machdep.cpu
machdep.cpu.max_basic: 1
machdep.cpu.max_ext: 2147483672
machdep.cpu.vendor: AuthenticAMD
machdep.cpu.brand_string: AMD Athlon(tm) 64 X2 Dual Core Processor 4200+
machdep.cpu.family: 15
machdep.cpu.model: 75
machdep.cpu.extmodel: 4
machdep.cpu.extfamily: 0
machdep.cpu.stepping: 2
machdep.cpu.feature_bits: 35189062106111
machdep.cpu.extfeature_bits: 137099475967
machdep.cpu.signature: 266162
machdep.cpu.brand: 0
machdep.cpu.features: FPU VME DE PSE TSC MSR PAE MCE CX8 APIC SEP MTRR PGE MCA CMOV PAT PSE36 CLFSH MMX FXSR SSE SSE2 HTT SSE3 CX16
machdep.cpu.extfeatures: SYSCALL EM64T LAHF RDTSCP TSCI
machdep.cpu.logical_per_package: 2
machdep.cpu.cores_per_package: 2
machdep.cpu.microcode_version: 21
machdep.cpu.processor_flag: 1
machdep.cpu.cache.linesize: 64
machdep.cpu.cache.L2_associativity: 16
machdep.cpu.cache.size: 524288
machdep.cpu.tlb.inst.small: 32
machdep.cpu.tlb.inst.large: 8
machdep.cpu.tlb.data.small: 32
machdep.cpu.tlb.data.small_level1: 512
machdep.cpu.tlb.data.large: 8
machdep.cpu.address_bits.physical: 40
machdep.cpu.address_bits.virtual: 48
machdep.cpu.core_count: 2
machdep.cpu.thread_count: 2
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kyh3im
kyh3im
Posted
Posted

 

OS X 10.10 - 10.10.1

 

Try to repair cpuid L3 cache for FX & Phenom

$ sysctl machdep.cpu

I've been getting a glitch since safari can work without webkit from 10.9.5. Not only on this version of kernel. It usually appears after several minutes of using safari. Pages can't redraw themselves when i scroll down a page, slider in safari doesn't move visually. since then some other glitches start to appear all over the system (10.10.1) for example in finder when you create new icon(folder, etc) it doesn't appear but it does in terminal (ls command), quickview (space key) window freezes half way(you still can press buttons on it but quickview window is half oppened(i'm sorry don't have screen shot, after glitch appears it's hard to use OS). Recently i reinstalled my yosemite and did combo update to 10.10.1. I think that the best way to summon that glitch is to use youtube for a while. 

 

 

$ sysctl machdep.cpu

machdep.cpu.max_basic: 1

machdep.cpu.max_ext: 2147483672

machdep.cpu.vendor: AuthenticAMD

machdep.cpu.brand_string: AMD Athlon 64 X2 Dual Core Processor 5600+

machdep.cpu.family: 15

machdep.cpu.model: 107

machdep.cpu.extmodel: 6

machdep.cpu.extfamily: 0

machdep.cpu.stepping: 2

machdep.cpu.feature_bits: 35189062106111

machdep.cpu.extfeature_bits: 1236611103743

machdep.cpu.signature: 397234

machdep.cpu.brand: 0

machdep.cpu.features: FPU VME DE PSE TSC MSR PAE MCE CX8 APIC SEP MTRR PGE MCA CMOV PAT PSE36 CLFSH MMX FXSR SSE SSE2 HTT SSE3 CX16

machdep.cpu.extfeatures: SYSCALL EM64T LAHF PREFETCHW RDTSCP TSCI

machdep.cpu.logical_per_package: 2

machdep.cpu.cores_per_package: 2

machdep.cpu.microcode_version: 21

machdep.cpu.processor_flag: 1

machdep.cpu.cache.linesize: 64

machdep.cpu.cache.L2_associativity: 16

machdep.cpu.cache.size: 524288

machdep.cpu.tlb.inst.small: 32

machdep.cpu.tlb.inst.large: 8

machdep.cpu.tlb.data.small: 32

machdep.cpu.tlb.data.small_level1: 512

machdep.cpu.tlb.data.large: 8

machdep.cpu.address_bits.physical: 40

machdep.cpu.address_bits.virtual: 48

machdep.cpu.core_count: 2

machdep.cpu.thread_count: 2

 

post-670953-0-27753100-1423941695_thumb.png

post-670953-0-99276700-1423941710_thumb.png

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gils83
gils83
Posted
Posted

 

OS X 10.10 - 10.10.1

 

Try to repair cpuid L3 cache for FX & Phenom

$ sysctl machdep.cpu

:)

 

bad audio , bad fsb but works :)

 

thanks 

 

 

 

 

 

whoooooo !!!!!!   :w00t:  :thumbsup_anim:  :rolleyes:I finally found the right settings, I have a great audio without cracking and I have no more audio / video desync !!   :D

 

:angel:  just "fsb=100 Mhz" 

 

cool n'Quiet= enable

C6 State= enable

frequency CPU= auto 

 

 

test_audio.mp4.zip

post-1093405-0-80356300-1423942232_thumb.png

post-1093405-0-42768800-1423963367_thumb.png

ScreenFlow2.mp4.zip

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Destroya01
Destroya01
Posted
Posted

sysctl machdep.cpu output for Phenom II 1090t:

machdep.cpu.max_basic: 6
machdep.cpu.max_ext: 2147483675
machdep.cpu.vendor: AuthenticAMD
machdep.cpu.brand_string: AMD Phenom(tm) II X6 1090T Processor
machdep.cpu.family: 16
machdep.cpu.model: 10
machdep.cpu.extmodel: 0
machdep.cpu.extfamily: 1
machdep.cpu.stepping: 0
machdep.cpu.feature_bits: 36064020440808447
machdep.cpu.extfeature_bits: 2313372192472063
machdep.cpu.signature: 1052576
machdep.cpu.brand: 0
machdep.cpu.features: FPU VME DE PSE TSC MSR PAE MCE CX8 APIC SEP MTRR PGE MCA CMOV PAT PSE36 CLFSH MMX FXSR SSE SSE2 HTT SSE3 MON CX16 POPCNT
machdep.cpu.extfeatures: SYSCALL 1GBPAGE EM64T LAHF LZCNT PREFETCHW RDTSCP TSCI
machdep.cpu.logical_per_package: 6
machdep.cpu.cores_per_package: 6
machdep.cpu.microcode_version: 21
machdep.cpu.processor_flag: 1
machdep.cpu.mwait.linesize_min: 64
machdep.cpu.mwait.linesize_max: 64
machdep.cpu.mwait.extensions: 3
machdep.cpu.mwait.sub_Cstates: 0
machdep.cpu.thermal.sensor: 0
machdep.cpu.thermal.dynamic_acceleration: 0
machdep.cpu.thermal.invariant_APIC_timer: 0
machdep.cpu.thermal.thresholds: 0
machdep.cpu.thermal.ACNT_MCNT: 1
machdep.cpu.thermal.core_power_limits: 0
machdep.cpu.thermal.fine_grain_clock_mod: 0
machdep.cpu.thermal.package_thermal_intr: 0
machdep.cpu.thermal.hardware_feedback: 0
machdep.cpu.thermal.energy_policy: 0
machdep.cpu.cache.linesize: 64
machdep.cpu.cache.L2_associativity: 16
machdep.cpu.cache.size: 524288
machdep.cpu.tlb.inst.small: 32
machdep.cpu.tlb.inst.large: 16
machdep.cpu.tlb.data.small: 48
machdep.cpu.tlb.data.small_level1: 512
machdep.cpu.tlb.data.large: 48
machdep.cpu.tlb.data.large_level1: 128
machdep.cpu.address_bits.physical: 48
machdep.cpu.address_bits.virtual: 48
machdep.cpu.core_count: 6
machdep.cpu.thread_count: 6

Audio still functions well with Tora Chi Yo's 1010-Rev-8A kernel.

 

My boot flags: -v GraphicsEnabler=Yes npci=0x3000

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lpukraine
lpukraine
Posted
Posted

Hey,Tora Chi Yo's 1010 SSEPlus rev 8 Works with 10.10.2.

Its Just That You've to Use FakeSMC 6.0.1082.

You what to say that I can simply update to 10.10.2 without any kext replacements from 10.10.1 with latest kernel?

And all I need that is FakeSMC 6.0.1082.?

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Meowthra
Meowthra
Posted
Posted

Added my build of the kernel based on latest changes by Tora Chi Yo.

Sources are on github

 

hi AnV

 

I compare CPU-Z Report 0fh - 16h processors difference

 
cupid fn 0x8000001D on the 15h & 16h processors Only
 
0fh-14h processors Cache is calculated the same way From fn0x80000005 & fn0x80000006
 
15h&16h processors Should be from the 0x8000001D
 
Because 0f-14h processors No cache partitions & cache sharing
and AMD manual No description for 0f -14h processors
 
so on the 0h-14h processors cache_partitions Should be set to 0 or delete
 
cache_sharing  I think it should be replaced with cores
 
 
static
void
get_amd_cache_info(i386_cpu_info_t *info_p)
{
    uint32_t	reg[4] = {0, 0, 0, 0};
    uint32_t    cpuid_result[4];
    uint32_t	cache_level;
    uint32_t	cache_partitions;
    uint32_t	cache_sharing;
    uint32_t	cache_linesize;
    uint32_t	cache_associativity;
    uint32_t	cache_size;
    uint32_t	cache_byte;
    uint32_t	cache_sets;
    uint32_t	colors;
    uint32_t	cache_type;
    cache_type_t    type = Lnone;
    uint32_t	linesizes[LCACHE_MAX];
    bzero( linesizes, sizeof(linesizes) );
    uint32_t asso = 0;

    uint32_t    cores;
    boolean_t	cpuid_deterministic_supported = FALSE;

    cpuid_fn(0x80000008, reg);
    cores = bitfield32(reg[ecx],7,0)+1;
    info_p->cpuid_cores_per_package = cores;

    //cpuid_fn(0x80000005, reg);
    //uint32_t L1DLinesPerTag = bitfield32(reg[ecx], 11, 8);
    //uint32_t L1ILinesPerTag = bitfield32(reg[edx], 11, 8);

    cpuid_fn(0x80000006, reg);
    //uint32_t L2ULinesPerTag = bitfield32(reg[ecx], 11, 8);
    uint32_t L3ULinesPerTag = bitfield32(reg[edx], 11, 8);

    int i=0;

    if (info_p->cpuid_family < 21)
    {

    	for ( i = 1; i<5 ; i++)
    	{
    		switch (i)
    		{
    			case 1:
    			{
    				type = 1 == 1 ? L1D : Lnone;
    				cpuid_fn(0x80000005, reg);
    				cache_byte = bitfield32(reg[ecx],31,24);
    				cache_linesize = bitfield32(reg[ecx],7,0);
    				cache_associativity = bitfield32(reg[ecx],23,16);
    				//cache_partitions = 0;

    				cache_size = cache_byte * 1024;
    				cache_sets = cache_size / (cache_associativity * cache_linesize);
    				info_p->cache_size[L1D] = cache_size;
    				info_p->cache_sharing[L1D] = cores;
    				//info_p->cache_partitions[L1D] = cache_partitions;
    				linesizes[L1D] = cache_linesize;
    				info_p->cache_linesize = linesizes[L1D];

    				colors = ( cache_linesize * cache_sets ) >> 12;
    				if ( colors > vm_cache_geometry_colors )
    					vm_cache_geometry_colors = colors ;
    			}
    			break;

    			case 2:
    			{
    				type = 2 == 2 ? L1I : Lnone;
    				cpuid_fn(0x80000005, reg);
    				cache_byte = bitfield32(reg[edx],31,24);
    				cache_linesize = bitfield32(reg[edx],7,0);
    				cache_associativity = bitfield32(reg[edx],23,16);
    				//cache_partitions = 0;

    				cache_size = cache_byte * 1024;
    				cache_sets = cache_size / (cache_associativity * cache_linesize);
    				info_p->cache_size[L1I] = cache_size;
    				info_p->cache_sharing[L1I] = cores;
    				//info_p->cache_partitions[L1I] = cache_partitions;
    				linesizes[L1I] = cache_linesize;
    				info_p->cache_linesize = linesizes[L1I];

    				colors = ( cache_linesize * cache_sets ) >> 12;
    				if ( colors > vm_cache_geometry_colors )
    					vm_cache_geometry_colors = colors ;
    			}
    			break;

    			case 3:
    			{
    				type = 3 == 3 ? L2U : Lnone;
    				cpuid_fn(0x80000006, reg);
    				cache_byte = bitfield32(reg[ecx],31,16);
    				cache_linesize = bitfield32(reg[ecx],7,0);
    				asso = bitfield32(reg[ecx],15,12);
    				cache_associativity = amdGetAssociativity(asso);
    				//cache_partitions = 0;

    				cache_size = cache_byte * 1024;
    				cache_sets = cache_size / (cache_associativity * cache_linesize);
    				info_p->cache_size[L2U] = cache_size;
    				info_p->cache_sharing[L2U] = cores;
    				//info_p->cache_partitions[L2U] = cache_partitions;
    				linesizes[L2U] = cache_linesize;
    				info_p->cache_linesize = linesizes[L2U];

    				info_p->cpuid_cache_L2_associativity = cache_associativity;

    				colors = ( cache_linesize * cache_sets ) >> 12;
    				if ( colors > vm_cache_geometry_colors )
    					vm_cache_geometry_colors = colors ;
    			}
    			break;

    			case 4:
    			{
    				if (L3ULinesPerTag)
    				{
    					type = 3 == 3 ? L3U : Lnone;
    					cpuid_fn(0x80000006, reg);
    					cache_byte = bitfield32(reg[edx],31,18);
    					cache_linesize = bitfield32(reg[edx],7,0);
    					asso = bitfield32(reg[edx],15,12);
    					cache_associativity = amdGetAssociativity(asso);
    					//cache_partitions = 0;

						cache_size = cache_byte * 1024 * 128;
						cache_sets = cache_size / (cache_associativity * cache_linesize);
						info_p->cache_size[L3U] = cache_size;
						info_p->cache_sharing[L3U] = cores;
						//info_p->cache_partitions[L3U] = cache_partitions;
						linesizes[L3U] = cache_linesize;
						info_p->cache_linesize = linesizes[L2U];

    					colors = ( cache_linesize * cache_sets ) >> 12;
    					if ( colors > vm_cache_geometry_colors )
    						vm_cache_geometry_colors = colors ;
    				}
    			}
    			break;

    			case Lnone:
    			default:
    				return;
    		}
    	} 
    } //10h-14h END
	else //15h-16h
	{
    	cpuid_fn(0x8000001D, cpuid_result);
    	if (cpuid_result[eax] >= 4)
    		cpuid_deterministic_supported = TRUE;

    	for (i = 0; cpuid_deterministic_supported ; i++)
    	{
    		reg[eax] = 0x8000001D;
    		reg[ecx] = i;
    		cpuid(reg);

    		DBG("cpuid(0x8000001D) i=%d eax=0x%x\n", i, reg[eax]);
    		cache_type = bitfield32(reg[eax], 4, 0);
    		if (cache_type == 0) break;
    		cache_level = bitfield32(reg[eax],  7,  5);
    		cache_sharing = bitfield32(reg[eax], 25, 14) + 1;
    		cache_linesize = bitfield32(reg[ebx], 11,  0) + 1;
    		cache_partitions = bitfield32(reg[ebx], 21, 12) + 1;
    		cache_associativity	= bitfield32(reg[ebx], 31, 22) + 1;
    		cache_sets = bitfield32(reg[ecx], 31,  0) + 1;

    		switch (cache_level)
    		{
    			case 1:
    				type = cache_type == 1 ? L1D :
    				cache_type == 2 ? L1I : Lnone;
    				break;
    			case 2:
    				type = cache_type == 3 ? L2U : Lnone;
    				break;
    			case 3:
    				type = cache_type == 3 ? L3U : Lnone;
    				break;
    			default:
    				type = Lnone;
    		}

    		if (type != Lnone)
    		{
    			cache_size = cache_linesize * cache_sets * cache_associativity * cache_partitions;

    			info_p->cache_size[type] = cache_size;
    			info_p->cache_sharing[type] = cache_sharing;
    			info_p->cache_partitions[type] = cache_partitions;
    			linesizes[type] = cache_linesize;
    			info_p->cache_linesize = linesizes[type];

    			if (type == L2U)
    				info_p->cpuid_cache_L2_associativity = cache_associativity;

    			colors = ( cache_linesize * cache_sets ) >> 12;
    			if ( colors > vm_cache_geometry_colors )
    				vm_cache_geometry_colors = colors;
    		}
    	}
    } //15h-16h END

	if (info_p->cpuid_cores_per_package == 0)
	{
		info_p->cpuid_cores_per_package = 1;

             info_p->cache_size[L2U] = info_p->cpuid_cache_size * 1024;
             info_p->cache_sharing[L2U] = 1;
             info_p->cache_partitions[L2U] = 1;
             
             linesizes[L2U] = info_p->cpuid_cache_linesize;
             
             DBG(" cache_size[L2U]      : %d\n",
                 info_p->cache_size[L2U]);
             DBG(" cache_sharing[L2U]   : 1\n");
             DBG(" cache_partitions[L2U]: 1\n");
             DBG(" linesizes[L2U]       : %d\n",
                 info_p->cpuid_cache_linesize);
	}

    cpuid_fn(0x80000005, reg);
    // uint64_t L1DTlb2and4MAssoc = (uint32_t)bitfield(eax, 31, 24);
    uint32_t L1DTlb2and4MSize  = (uint32_t)bitfield32(reg[eax], 23, 16);
    // uint64_t L1ITlb2and4MAssoc = (uint32_t)bitfield(eax, 15, 8);
    uint32_t L1ITlb2and4MSize  = (uint32_t)bitfield32(reg[eax], 7, 0);
    // uint64_t L1DTlb4KAssoc = (uint32_t)bitfield(ebx, 31, 24);
    uint32_t L1DTlb4KSize = (uint32_t)bitfield32(reg[ebx], 23, 16);
    // uint64_t L1ITlb4KAssoc = (uint32_t)bitfield(ebx, 15, 8);
    uint32_t L1ITlb4KSize = (uint32_t)bitfield32(reg[ebx], 7, 0);

    cpuid_fn(0x80000006, reg);
    //  uint64_t L2DTlb2and4MAssoc = (uint32_t)bitfield(eax, 31, 28);
    uint32_t L2DTlb2and4MSize = (uint32_t)bitfield32(reg[eax], 27, 16);
    //  uint64_t L2ITlb2and4MAssoc = (uint32_t)bitfield(eax, 15, 12);
    uint32_t L2ITlb2and4MSize = (uint32_t)bitfield32(reg[eax], 11, 0);
    // uint64_t L2DTlb4KAssoc = (uint32_t)bitfield(ebx, 31, 28);
    uint32_t L2DTlb4KSize = (uint32_t)bitfield32(reg[ebx], 27, 16);
    // uint64_t L2ITlb4KAssoc = (uint32_t)bitfield(ebx, 15, 12);
    uint32_t L2ITlb4KSize = (uint32_t)bitfield32(reg[ebx], 11, 0);

    info_p->cpuid_tlb[0][0][0] =  L1ITlb4KSize;
    info_p->cpuid_tlb[1][0][0] =  L1DTlb4KSize;
    info_p->cpuid_tlb[0][0][1] =  L2ITlb4KSize;
    info_p->cpuid_tlb[1][0][1] =  L2DTlb4KSize;
    info_p->cpuid_tlb[0][1][0] =  L1ITlb2and4MSize;
    info_p->cpuid_tlb[1][1][0] =  L1DTlb2and4MSize;
    info_p->cpuid_tlb[0][1][1] =  L2ITlb2and4MSize;
    info_p->cpuid_tlb[1][1][1] =  L2DTlb2and4MSize;
}
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Bronya
Bronya
Posted
Posted

so on the 0h-14h processors cache_partitions Should be set to 0 or delete

 
cache_sharing  I think it should be replaced with cores
 

Hi ! 

Yes ! I know this ! You can replace cache_sharing with cores ! This no problem ! 

cache_partitions - this same that "cache lines per tag" . No problem if delete this , but OSX need use this cache_partition . 

One question to you ! Why you fix my cpuid ??? Why you delete cache_level  and emulation L3_cache???  No should delete this , because this support for cpu_topology . If delete cache_level - this can get panic … . I tried . 

For emulation L3_cache - this special , because this can work speed .

System MacOsX need support this partition and cache_level !!!

I did cpuid - this full work ! No need delete ! )))

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Meowthra
Meowthra
Posted
Posted

Hi ! 

Yes ! I know this ! You can replace cache_sharing with cores ! This no problem ! 

cache_partitions - this same that "cache lines per tag" . No problem if delete this , but OSX need use this cache_partition . 

One question to you ! Why you fix my cpuid ??? Why you delete cache_level  and emulation L3_cache???  No should delete this , because this support for cpu_topology . If delete cache_level - this can get panic … . I tried . 

For emulation L3_cache - this special , because this can work speed .

System MacOsX need support this partition and cache_level !!!

I did cpuid - this full work ! No need delete ! )))

 

21010353172l.jpg

 

 

this L3 Not 8MB

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