Pike R. Alpha Posted July 21, 2014 Share Posted July 21, 2014 For everyone looking for the Yosemite update packages, read this: Follow the URL in that blog article and search for "10.10" in it. There you'll find the OSXUpd10.10.pkg and OSXUpd10.10Patch.pkg files you are looking for. Cheers! 1 Link to comment Share on other sites More sharing options...
tanjiajun_34 Posted July 21, 2014 Share Posted July 21, 2014 I actually downloaded a delta update - so I have a separate install package with just DP2 changes. Short story is my redemption code got wasted so I signed in with my developer account to the Apple support forums and there were others in same position as me and someone on there linked to official delta update from DP1 to 2. Got it working finally! Install DP1 then update to DP2 works! 1 Link to comment Share on other sites More sharing options...
MiniHack Posted July 21, 2014 Share Posted July 21, 2014 Got it working finally! Install DP1 then update to DP2 works! Great! Maybe wait for DP4 now.....so far DP2 seemed to me to be the best for Haswell graphics. Edit: Oh, I see it is here now. Here we go again.... Link to comment Share on other sites More sharing options...
wusa Posted July 21, 2014 Author Share Posted July 21, 2014 DP4 is out, I hope the DP4 will make the HD 4600 Mobile (0x04168086) works OOB wth QE/CI. Have any of you HD 4600 Mobile users tried out the DP4 yet ? My DP1 is broken so I have to redownload everything again :\. Link to comment Share on other sites More sharing options...
General11 Posted July 21, 2014 Share Posted July 21, 2014 i will connect to our problem with HD 4600 (mobile) and QE/CI. DP4 pls give us a work for 4600 1 Link to comment Share on other sites More sharing options...
MiniHack Posted July 21, 2014 Share Posted July 21, 2014 Essentially for me DP4 is no change in terms of HD 5000 from DP3. This means I still have to reverse priority of graphics in bios to be able to boot. Also, as with DP3, I can boot fine if I revert the Azul kext to the one from DP2. Link to comment Share on other sites More sharing options...
Pike R. Alpha Posted July 21, 2014 Share Posted July 21, 2014 Essentially for me DP4 is no change in terms of HD 5000 from DP3. This means I still have to reverse priority of graphics in bios to be able to boot. Also, as with DP3, I can boot fine if I revert the Azul kext to the one from DP2. What board/UEFI BIOS (brand/version) do you have? You do know that this is THE solution i.e. that you have to figure out what changes when you change the default port 1 Link to comment Share on other sites More sharing options...
MiniHack Posted July 21, 2014 Share Posted July 21, 2014 What board/UEFI BIOS (brand/version) do you have? You do know that this is THE solution i.e. that you have to figure out what changes when you change the default port It is an Intel NUC Haswell d54250wyk. Unfortunately beyond looking at the frame buffers (which do not seem to have changed) I do not know what else to look for. I am afraid I am little more than an intelligent monkey in many respects....I cannot compare ioreg between scenarios unfortunately as the NUC reboots. Link to comment Share on other sites More sharing options...
Pike R. Alpha Posted July 21, 2014 Share Posted July 21, 2014 It is an Intel NUC Haswell d54250wyk. Unfortunately beyond looking at the frame buffers (which do not seem to have changed) I do not know what else to look for. I am afraid I am little more than an intelligent monkey in many respects....I cannot compare ioreg between scenarios unfortunately as the NUC reboots. I think that you are running into an issue with setBootPipe() in the AppleIntelFramebufferAzul binary which was changed to let it check four IGPU ports instead of three. This also changes the order and that is why you have to swap ports in your BIOS. 1 Link to comment Share on other sites More sharing options...
slayer2333 Posted July 22, 2014 Share Posted July 22, 2014 DP4 is out, I hope the DP4 will make the HD 4600 Mobile (0x04168086) works OOB wth QE/CI. Have any of you HD 4600 Mobile users tried out the DP4 yet ? My DP1 is broken so I have to redownload everything again :\. Sadly no change with DP4, still mobile Intel HD4600 not working. 1 Link to comment Share on other sites More sharing options...
ZalaDa Posted July 22, 2014 Share Posted July 22, 2014 I think that you are running into an issue with setBootPipe() in the AppleIntelFramebufferAzul binary which was changed to let it check four IGPU ports instead of three. This also changes the order and that is why you have to swap ports in your BIOS. the problem here Mr.Pike is there is many Bioses doesn't have options to control ports as mine and the whole line of Gigabyte's Z87X family there is no option for that i wish the could put it in their Bioses so i can fix color issues with IGP or at least there is a patch for the bios that unlocks this option .. even in laptops there is no option for port swapping (as some machines comes in with HDMI + DP as an option for Dual or Triple MultiScreen solution) ... Link to comment Share on other sites More sharing options...
Pike R. Alpha Posted July 22, 2014 Share Posted July 22, 2014 Sadly no change with DP4, still mobile Intel HD4600 not working. Run intel_reg_dumper (Google) and attach your output here, or e-mail me your output (see ssdtPRGen.sh for my e-mail address). the problem here Mr.Pike is there is many Bioses doesn't have options to control ports as mine and the whole line of Gigabyte's Z87X family there is no option for that i wish the could put it in their Bioses so i can fix color issues with IGP or at least there is a patch for the bios that unlocks this option .. even in laptops there is no option for port swapping (as some machines comes in with HDMI + DP as an option for Dual or Triple MultiScreen solution) ... I know, but what the (UEFI) BIOS can do… so can we with our boot loaders Link to comment Share on other sites More sharing options...
ZalaDa Posted July 22, 2014 Share Posted July 22, 2014 Run intel_reg_dumper (Google) and attach your output here, or e-mail me your output (see ssdtPRGen.sh for my e-mail address). I know, but what the (UEFI) BIOS can do… so can we with our boot loaders will if there is a feature in one of the famous bootloaders that would be great but ... when and how ? Clover still the only bootloader that can add this up to their next release .. if it's already added then please point to where to go ... that might be fix my issues with VGA monitors (that will on the fly patch for the Azul Kexts isn't right ?!) Link to comment Share on other sites More sharing options...
jsl Posted July 22, 2014 Share Posted July 22, 2014 Sadly no change with DP4, still mobile Intel HD4600 not working. There is some improvement in DP3 and DP4. After adding 0x04168086 to AppleIntelFramebufferAzul.kext and AppleIntelHD5000Graphics.kext, then connect a HDMI monitor to my Asus G750JZ laptop In DP3 AppleIntelFramebufferAzul.kext was loaded In DP4 both AppleIntelFramebufferAzul.kext and AppleIntelHD5000Graphics.kext were loaded But still no QE/CI function The following are shown in external HDMI monitor Internal Screen got abnormal pictures Link to comment Share on other sites More sharing options...
Pike R. Alpha Posted July 22, 2014 Share Posted July 22, 2014 will if there is a feature in one of the famous bootloaders that would be great but ... when and how ? Clover still the only bootloader that can add this up to their next release .. if it's already added then please point to where to go ... that might be fix my issues with VGA monitors (that will on the fly patch for the Azul Kexts isn't right ?!) If you really care about the when then at least providing the data that I asked for, so that developers can try to fix this issue. Otherwise nothing can be done, or only at a later date. Link to comment Share on other sites More sharing options...
ZalaDa Posted July 22, 2014 Share Posted July 22, 2014 If you really care about the when then at least providing the data that I asked for, so that developers can try to fix this issue. Otherwise nothing can be done, or only at a later date. What is the data you need ?! Link to comment Share on other sites More sharing options...
slayer2333 Posted July 22, 2014 Share Posted July 22, 2014 Run intel_reg_dumper (Google) and attach your output here, or e-mail me your output (see ssdtPRGen.sh for my e-mail address). Hi Pike, here's the file you asked for. Thank you in advance for your help on that. intel_reg_dumper.txt 1 Link to comment Share on other sites More sharing options...
MiniHack Posted July 22, 2014 Share Posted July 22, 2014 My dump: ubuntu@ubuntu:~$ sudo intel_reg_dumper PGETBL_CTL: 0x00000000 GEN6_INSTDONE_1: 0xffdfffff GEN6_INSTDONE_2: 0x00000000 CPU_VGACNTRL: 0x80000000 (disabled) DIGITAL_PORT_HOTPLUG_CNTRL: 0x00000000 RR_HW_CTL: 0x000c0bb8 (low 184, high 11) FDI_PLL_BIOS_0: 0x00000000 FDI_PLL_BIOS_1: 0x00000000 FDI_PLL_BIOS_2: 0x00000000 DISPLAY_PORT_PLL_BIOS_0: 0x00000000 DISPLAY_PORT_PLL_BIOS_1: 0x00000000 DISPLAY_PORT_PLL_BIOS_2: 0x00000000 FDI_PLL_FREQ_CTL: 0x00000000 PIPEACONF: 0xc0000000 (enabled, active, pf-pd, rotate 0, 8bpc) HTOTAL_A: 0x0897077f (1920 active, 2200 total) HBLANK_A: 0x0897077f (1920 start, 2200 end) HSYNC_A: 0x080307d7 (2008 start, 2052 end) VTOTAL_A: 0x04640437 (1080 active, 1125 total) VBLANK_A: 0x04640437 (1080 start, 1125 end) VSYNC_A: 0x0440043b (1084 start, 1089 end) VSYNCSHIFT_A: 0x00000000 PIPEASRC: 0x077f0437 (1920, 1080) PIPEA_DATA_M1: 0x7e3661e0 (TU 64, val 0x3661e0 3564000) PIPEA_DATA_N1: 0x0041eb00 (val 0x41eb00 4320000) PIPEA_DATA_M2: 0x00000000 (TU 1, val 0x0 0) PIPEA_DATA_N2: 0x00000000 (val 0x0 0) PIPEA_LINK_M1: 0x00024414 (val 0x24414 148500) PIPEA_LINK_N1: 0x00041eb0 (val 0x41eb0 270000) PIPEA_LINK_M2: 0x00000000 (val 0x0 0) PIPEA_LINK_N2: 0x00000000 (val 0x0 0) DSPACNTR: 0xd8004400 (enabled) DSPABASE: 0x00000000 DSPASTRIDE: 0x00001e00 (120) DSPASURF: 0x0084d000 DSPATILEOFF: 0x00000000 (0, 0) PIPEBCONF: 0x00000000 (disabled, inactive, pf-pd, rotate 0, 8bpc) HTOTAL_B: 0x031f027f (640 active, 800 total) HBLANK_B: 0x031f027f (640 start, 800 end) HSYNC_B: 0x02ef028f (656 start, 752 end) VTOTAL_B: 0x020c01df (480 active, 525 total) VBLANK_B: 0x020c01df (480 start, 525 end) VSYNC_B: 0x01eb01e9 (490 start, 492 end) VSYNCSHIFT_B: 0x00000000 PIPEBSRC: 0x027f01df (640, 480) PIPEB_DATA_M1: 0x00000000 (TU 1, val 0x0 0) PIPEB_DATA_N1: 0x00000000 (val 0x0 0) PIPEB_DATA_M2: 0x00000000 (TU 1, val 0x0 0) PIPEB_DATA_N2: 0x00000000 (val 0x0 0) PIPEB_LINK_M1: 0x00000000 (val 0x0 0) PIPEB_LINK_N1: 0x00000000 (val 0x0 0) PIPEB_LINK_M2: 0x00000000 (val 0x0 0) PIPEB_LINK_N2: 0x00000000 (val 0x0 0) DSPBCNTR: 0x00004000 (disabled) DSPBBASE: 0x00000000 DSPBSTRIDE: 0x00000500 (20) DSPBSURF: 0x00000000 DSPBTILEOFF: 0x00000000 (0, 0) PIPECCONF: 0x00000000 (disabled, inactive, pf-pd, rotate 0, 8bpc) HTOTAL_C: 0x00000000 (1 active, 1 total) HBLANK_C: 0x00000000 (1 start, 1 end) HSYNC_C: 0x00000000 (1 start, 1 end) VTOTAL_C: 0x00000000 (1 active, 1 total) VBLANK_C: 0x00000000 (1 start, 1 end) VSYNC_C: 0x00000000 (1 start, 1 end) VSYNCSHIFT_C: 0x00000000 PIPECSRC: 0x00000000 (1, 1) PIPEC_DATA_M1: 0x00000000 (TU 1, val 0x0 0) PIPEC_DATA_N1: 0x00000000 (val 0x0 0) PIPEC_DATA_M2: 0x00000000 (TU 1, val 0x0 0) PIPEC_DATA_N2: 0x00000000 (val 0x0 0) PIPEC_LINK_M1: 0x00000000 (val 0x0 0) PIPEC_LINK_N1: 0x00000000 (val 0x0 0) PIPEC_LINK_M2: 0x00000000 (val 0x0 0) PIPEC_LINK_N2: 0x00000000 (val 0x0 0) DSPCCNTR: 0x00004000 (disabled) DSPCBASE: 0x00000000 DSPCSTRIDE: 0x00000000 (0) DSPCSURF: 0x00000000 DSPCTILEOFF: 0x00000000 (0, 0) PFA_CTL_1: 0x00000000 (disable, auto_scale yes, auto_scale_cal no, v_filter enable, vadapt disable, mode least, filter_sel programmed,chroma pre-filter disable, vert3tap auto, v_inter_invert field 1) PFA_CTL_2: 0x00007de4 (vscale 0.983521) PFA_CTL_3: 0x00003ef2 (vscale initial phase 0.491760) PFA_CTL_4: 0x00007c40 (hscale 0.970703) PFA_WIN_POS: 0x00000000 (0, 0) PFA_WIN_SIZE: 0x00000000 (0, 0) PFB_CTL_1: 0x00000000 (disable, auto_scale yes, auto_scale_cal no, v_filter enable, vadapt disable, mode least, filter_sel programmed,chroma pre-filter disable, vert3tap auto, v_inter_invert field 1) PFB_CTL_2: 0x00007de4 (vscale 0.983521) PFB_CTL_3: 0x00003ef2 (vscale initial phase 0.491760) PFB_CTL_4: 0x00007c40 (hscale 0.970703) PFB_WIN_POS: 0x00000000 (0, 0) PFB_WIN_SIZE: 0x00000000 (0, 0) PFC_CTL_1: 0x00000000 (disable, auto_scale yes, auto_scale_cal no, v_filter enable, vadapt disable, mode least, filter_sel programmed,chroma pre-filter disable, vert3tap auto, v_inter_invert field 1) PFC_CTL_2: 0x00007de4 (vscale 0.983521) PFC_CTL_3: 0x00003ef2 (vscale initial phase 0.491760) PFC_CTL_4: 0x00007c40 (hscale 0.970703) PFC_WIN_POS: 0x00000000 (0, 0) PFC_WIN_SIZE: 0x00000000 (0, 0) PCH_DREF_CONTROL: 0x00000000 (cpu source disable, ssc_source disable, nonspread_source disable, superspread_source disable, ssc4_mode downspread, ssc1 disable, ssc4 disable) PCH_RAWCLK_FREQ: 0x00000018 (FDL_TP1 timer 0.5us, FDL_TP2 timer 1.5us, freq 24) PCH_DPLL_TMR_CFG: 0x00000018 PCH_SSC4_PARMS: 0x00000018 PCH_SSC4_AUX_PARMS: 0x00000018 PCH_DPLL_SEL: 0x00000018 (FDL_TP1 timer 0.5us, FDL_TP2 timer 1.5us, freq 24) PCH_DPLL_ANALOG_CTL: 0x00000018 PCH_DPLL_A: 0x00000018 (disable, sdvo high speed no, mode (null), p2 (null), FPA0 P1 0, FPA1 P1 4, refclk default 120Mhz, sdvo/hdmi mul 1) PCH_DPLL_B: 0x00000018 (disable, sdvo high speed no, mode (null), p2 (null), FPA0 P1 0, FPA1 P1 4, refclk default 120Mhz, sdvo/hdmi mul 1) PCH_FPA0: 0x00000018 (n = 0, m1 = 0, m2 = 24) PCH_FPA1: 0x00000018 (n = 0, m1 = 0, m2 = 24) PCH_FPB0: 0x00000018 (n = 0, m1 = 0, m2 = 24) PCH_FPB1: 0x00000018 (n = 0, m1 = 0, m2 = 24) TRANS_HTOTAL_A: 0x00000018 (25 active, 1 total) TRANS_HBLANK_A: 0x00000018 (25 start, 1 end) TRANS_HSYNC_A: 0x00000018 (25 start, 1 end) TRANS_VTOTAL_A: 0x00000018 (25 active, 1 total) TRANS_VBLANK_A: 0x00000018 (25 start, 1 end) TRANS_VSYNC_A: 0x00000018 (25 start, 1 end) TRANS_VSYNCSHIFT_A: 0x00000018 TRANSA_DATA_M1: 0x00000018 (TU 1, val 0x18 24) TRANSA_DATA_N1: 0x00000018 (val 0x18 24) TRANSA_DATA_M2: 0x00000018 (TU 1, val 0x18 24) TRANSA_DATA_N2: 0x00000018 (val 0x18 24) TRANSA_DP_LINK_M1: 0x00000018 (val 0x18 24) TRANSA_DP_LINK_N1: 0x00000018 (val 0x18 24) TRANSA_DP_LINK_M2: 0x00000018 (val 0x18 24) TRANSA_DP_LINK_N2: 0x00000018 (val 0x18 24) TRANS_HTOTAL_B: 0x00000018 (25 active, 1 total) TRANS_HBLANK_B: 0x00000018 (25 start, 1 end) TRANS_HSYNC_B: 0x00000018 (25 start, 1 end) TRANS_VTOTAL_B: 0x00000018 (25 active, 1 total) TRANS_VBLANK_B: 0x00000018 (25 start, 1 end) TRANS_VSYNC_B: 0x00000018 (25 start, 1 end) TRANS_VSYNCSHIFT_B: 0x00000018 TRANSB_DATA_M1: 0x00000018 (TU 1, val 0x18 24) TRANSB_DATA_N1: 0x00000018 (val 0x18 24) TRANSB_DATA_M2: 0x00000018 (TU 1, val 0x18 24) TRANSB_DATA_N2: 0x00000018 (val 0x18 24) TRANSB_DP_LINK_M1: 0x00000018 (val 0x18 24) TRANSB_DP_LINK_N1: 0x00000018 (val 0x18 24) TRANSB_DP_LINK_M2: 0x00000018 (val 0x18 24) TRANSB_DP_LINK_N2: 0x00000018 (val 0x18 24) TRANS_HTOTAL_C: 0x00000000 (1 active, 1 total) TRANS_HBLANK_C: 0x00000000 (1 start, 1 end) TRANS_HSYNC_C: 0x00000000 (1 start, 1 end) TRANS_VTOTAL_C: 0x00000000 (1 active, 1 total) TRANS_VBLANK_C: 0x00000000 (1 start, 1 end) TRANS_VSYNC_C: 0x00000000 (1 start, 1 end) TRANS_VSYNCSHIFT_C: 0x00000000 TRANSC_DATA_M1: 0x00000000 (TU 1, val 0x0 0) TRANSC_DATA_N1: 0x00000000 (val 0x0 0) TRANSC_DATA_M2: 0x00000000 (TU 1, val 0x0 0) TRANSC_DATA_N2: 0x00000000 (val 0x0 0) TRANSC_DP_LINK_M1: 0x00000000 (val 0x0 0) TRANSC_DP_LINK_N1: 0x00000000 (val 0x0 0) TRANSC_DP_LINK_M2: 0x00000000 (val 0x0 0) TRANSC_DP_LINK_N2: 0x00000000 (val 0x0 0) TRANSACONF: 0x00000018 (disable, inactive, progressive) TRANSBCONF: 0x00000018 (disable, inactive, progressive) TRANSCCONF: 0x00000018 (disable, inactive, progressive) FDI_TXA_CTL: 0x00000000 (disable, train pattern pattern_1, voltage swing 0.4V,pre-emphasis none, port width X1, enhanced framing disable, FDI PLL disable, scrambing enable, master mode disable) FDI_TXB_CTL: 0x00000000 (disable, train pattern pattern_1, voltage swing 0.4V,pre-emphasis none, port width X1, enhanced framing disable, FDI PLL disable, scrambing enable, master mode disable) FDI_TXC_CTL: 0x00000000 (disable, train pattern pattern_1, voltage swing 0.4V,pre-emphasis none, port width X1, enhanced framing disable, FDI PLL disable, scrambing enable, master mode disable) FDI_RXA_CTL: 0x00000018 (disable, train pattern pattern_1, port width X1, 8bpc,link_reverse_strap_overwrite no, dmi_link_reverse no, FDI PLL disable,FS ecc disable, FE ecc disable, FS err report disable, FE err report disable,scrambing enable, enhanced framing disable, PCDClk) FDI_RXB_CTL: 0x00000018 (disable, train pattern pattern_1, port width X1, 8bpc,link_reverse_strap_overwrite no, dmi_link_reverse no, FDI PLL disable,FS ecc disable, FE ecc disable, FS err report disable, FE err report disable,scrambing enable, enhanced framing disable, PCDClk) FDI_RXC_CTL: 0x00000018 (disable, train pattern pattern_1, port width X1, 8bpc,link_reverse_strap_overwrite no, dmi_link_reverse no, FDI PLL disable,FS ecc disable, FE ecc disable, FS err report disable, FE err report disable,scrambing enable, enhanced framing disable, PCDClk) FDI_RXA_MISC: 0x00000018 (FDI Delay 24) FDI_RXB_MISC: 0x00000018 (FDI Delay 24) FDI_RXC_MISC: 0x00000018 (FDI Delay 24) FDI_RXA_TUSIZE1: 0x00000018 FDI_RXA_TUSIZE2: 0x00000018 FDI_RXB_TUSIZE1: 0x00000018 FDI_RXB_TUSIZE2: 0x00000018 FDI_RXC_TUSIZE1: 0x00000018 FDI_RXC_TUSIZE2: 0x00000018 FDI_PLL_CTL_1: 0x00000018 FDI_PLL_CTL_2: 0x00000018 FDI_RXA_IIR: 0x00000018 FDI_RXA_IMR: 0x00000018 FDI_RXB_IIR: 0x00000018 FDI_RXB_IMR: 0x00000018 PCH_ADPA: 0x00000018 (disabled, transcoder A, +hsync, +vsync) HDMIB: 0x00000000 (disabled pipe A 8bpc SDVO DVI audio disabled -vsync -hsync non-detected) HDMIC: 0x00000000 (disabled pipe A 8bpc SDVO DVI audio disabled -vsync -hsync non-detected) HDMID: 0x00000000 (disabled pipe A 8bpc SDVO DVI audio disabled -vsync -hsync non-detected) PCH_LVDS: 0x00000000 (disabled, pipe A, 18 bit, 1 channel) CPU_eDP_A: 0x00000090 PCH_DP_B: 0x00000018 PCH_DP_C: 0x00000018 PCH_DP_D: 0x00000018 TRANS_DP_CTL_A: 0x00000000 (disabled, pipe A, 18 bit, 1 channel) TRANS_DP_CTL_B: 0x00000000 (disabled, pipe A, 18 bit, 1 channel) TRANS_DP_CTL_C: 0x00000000 (disabled, pipe A, 18 bit, 1 channel) BLC_PWM_CPU_CTL2: 0x60000000 BLC_PWM_CPU_CTL: 0x00000000 BLC_PWM_PCH_CTL1: 0x00000000 BLC_PWM_PCH_CTL2: 0x00000000 PCH_PP_STATUS: 0x00000000 (off, not ready, sequencing idle) PCH_PP_CONTROL: 0xabcd0000 (blacklight disabled, do not power down on reset, panel off) PCH_PP_ON_DELAYS: 0x00000000 PCH_PP_OFF_DELAYS: 0x00000000 PCH_PP_DIVISOR: 0x0004af06 PORT_DBG: 0x00000000 (HW DRRS off) RC6_RESIDENCY_TIME: 0x027aa896 RC6p_RESIDENCY_TIME: 0x00000000 RC6pp_RESIDENCY_TIME: 0x00000000 GEN6_RP_CONTROL: 0x00000d92 (enabled) GEN6_RPNSWREQ: 0x28000000 GEN6_RP_DOWN_TIMEOUT: 0x000f4240 GEN6_RP_INTERRUPT_LIMITS: 0x00040000 GEN6_RP_UP_THRESHOLD: 0x0000e808 GEN6_RP_UP_EI: 0x000101d0 GEN6_RP_DOWN_EI: 0x00055730 GEN6_RP_IDLE_HYSTERSIS: 0x0000000a GEN6_RC_STATE: 0x00000000 GEN6_RC_CONTROL: 0x88040000 GEN6_RC1_WAKE_RATE_LIMIT: 0x03e80000 GEN6_RC6_WAKE_RATE_LIMIT: 0x0028001e GEN6_RC_EVALUATION_INTERVAL: 0x0001e848 GEN6_RC_IDLE_HYSTERSIS: 0x00000019 GEN6_RC_SLEEP: 0x00000000 GEN6_RC1e_THRESHOLD: 0x000003e8 GEN6_RC6_THRESHOLD: 0x0000c350 GEN6_RC_VIDEO_FREQ: 0x18000000 GEN6_PMIER: 0x03000076 GEN6_PMIMR: 0x00000000 GEN6_PMINTRMSK: 0x00000000 HSW_PWR_WELL_CTL1: 0xc0000000 HSW_PWR_WELL_CTL2: 0x40000000 HSW_PWR_WELL_CTL3: 0x40000000 HSW_PWR_WELL_CTL4: 0x40000000 HSW_PWR_WELL_CTL5: 0x0004050f HSW_PWR_WELL_CTL6: 0x00000000 PIPE_DDI_FUNC_CTL_A: 0x90030000 PIPE_DDI_FUNC_CTL_B: 0x00005000 PIPE_DDI_FUNC_CTL_C: 0x00030000 PIPE_DDI_FUNC_CTL_EDP: 0x00030000 DP_TP_CTL_A: 0x00000000 DP_TP_CTL_B: 0x00000000 DP_TP_CTL_C: 0x00000000 DP_TP_CTL_D: 0x00000000 DP_TP_CTL_E: 0x00000000 DP_TP_STATUS_A: 0x00000000 DP_TP_STATUS_B: 0x00000000 DP_TP_STATUS_C: 0x00000000 DP_TP_STATUS_D: 0x00000000 DP_TP_STATUS_E: 0x00000000 DDI_BUF_CTL_A: 0x00000090 DDI_BUF_CTL_B: 0x80000000 DDI_BUF_CTL_C: 0x00000000 DDI_BUF_CTL_D: 0x00000000 DDI_BUF_CTL_E: 0x00000000 PIXCLK_GATE: 0x0004af06 SPLL_CTL: 0x00000000 LCPLL_CTL: 0x40000037 WRPLL_CTL1: 0xb0210614 WRPLL_CTL2: 0x30652639 PORT_CLK_SEL_A: 0xe0000000 PORT_CLK_SEL_B: 0x80000000 PORT_CLK_SEL_C: 0xe0000000 PORT_CLK_SEL_D: 0xe0000000 PORT_CLK_SEL_E: 0xe0000000 PIPE_CLK_SEL_A: 0x40000000 PIPE_CLK_SEL_B: 0x00000000 PIPE_CLK_SEL_C: 0x00000000 PIPE_WM_LINETIME_A: 0x00000060 PIPE_WM_LINETIME_B: 0x00000000 PIPE_WM_LINETIME_C: 0x00000000 SFUSE_STRAP: 0x00000006 ubuntu@ubuntu:~$ Many thanks for help. Haswell NUC HD5000. Link to comment Share on other sites More sharing options...
The Real Deal Posted July 22, 2014 Share Posted July 22, 2014 Hi Pike, here's the file you asked for. Thank you in advance for your help on that. link for the tool please ? Link to comment Share on other sites More sharing options...
slayer2333 Posted July 22, 2014 Share Posted July 22, 2014 link for the tool please ? I am using Ubuntu Live CD, downloaded Intel-gpu-tools - 1.7 at https://01.org/linuxgraphics/downloads 1 Link to comment Share on other sites More sharing options...
MiniHack Posted July 22, 2014 Share Posted July 22, 2014 link for the tool please ? Used Ubuntu 12 on a live USB stick. No need for any extra download with that as the intel_reg_dumper is available direct via the terminal using command "sudo intel_reg_dumper". 1 Link to comment Share on other sites More sharing options...
The Real Deal Posted July 22, 2014 Share Posted July 22, 2014 What board/UEFI BIOS (brand/version) do you have? You do know that this is THE solution i.e. that you have to figure out what changes when you change the default port If you really care about the when then at least providing the data that I asked for, so that developers can try to fix this issue. Otherwise nothing can be done, or only at a later date. Hello, Dump freshly extracted (thanks to the fellas who helped me to sort this out). Motherboard is Asus Maximus VII Gene Processor a 4690K UEFI BIOS 1002 (AMI) It's a struggle to make the IGPU works. Chameleon : The IGPU is recognized but only 7 mb VRAM Clover : stuck with a cursor and a black screen before the main boot screen. My AppleIntelFramebufferAzul.kext is edited (for 9 series). The same DSDT patch i used to inject the IGPU in my Z87 DSDT's is not working anymore with Z97. Maybe you can help a bit to figure this. dump.zip Link to comment Share on other sites More sharing options...
BiTRiP Posted July 22, 2014 Share Posted July 22, 2014 Just upgraded to DP4 Same as with DP3, I get crippled screen as soon as Loginwindow loads then it immediately reboots. With AppleIntelFramebufferAzul.kext from DP2 everything is fine! Full QE/CI and detected as HD4600 with 1536MB memory. This is for desktop version (Intel i7 4770K on GA-Z87X-UD5H) 1 Link to comment Share on other sites More sharing options...
jsl Posted July 23, 2014 Share Posted July 23, 2014 Run intel_reg_dumper (Google) and attach your output here, or e-mail me your output (see ssdtPRGen.sh for my e-mail address). I know, but what the (UEFI) BIOS can do… so can we with our boot loaders Here is my dumper.txt G750_dumper.zip Link to comment Share on other sites More sharing options...
Pike R. Alpha Posted July 23, 2014 Share Posted July 23, 2014 My dump: ubuntu@ubuntu:~$ sudo intel_reg_dumper PGETBL_CTL: 0x00000000 GEN6_INSTDONE_1: 0xffdfffff GEN6_INSTDONE_2: 0x00000000 CPU_VGACNTRL: 0x80000000 (disabled) DIGITAL_PORT_HOTPLUG_CNTRL: 0x00000000 RR_HW_CTL: 0x000c0bb8 (low 184, high 11) FDI_PLL_BIOS_0: 0x00000000 FDI_PLL_BIOS_1: 0x00000000 FDI_PLL_BIOS_2: 0x00000000 DISPLAY_PORT_PLL_BIOS_0: 0x00000000 DISPLAY_PORT_PLL_BIOS_1: 0x00000000 DISPLAY_PORT_PLL_BIOS_2: 0x00000000 FDI_PLL_FREQ_CTL: 0x00000000 PIPEACONF: 0xc0000000 (enabled, active, pf-pd, rotate 0, 8bpc) HTOTAL_A: 0x0897077f (1920 active, 2200 total) HBLANK_A: 0x0897077f (1920 start, 2200 end) HSYNC_A: 0x080307d7 (2008 start, 2052 end) VTOTAL_A: 0x04640437 (1080 active, 1125 total) VBLANK_A: 0x04640437 (1080 start, 1125 end) VSYNC_A: 0x0440043b (1084 start, 1089 end) VSYNCSHIFT_A: 0x00000000 PIPEASRC: 0x077f0437 (1920, 1080) PIPEA_DATA_M1: 0x7e3661e0 (TU 64, val 0x3661e0 3564000) PIPEA_DATA_N1: 0x0041eb00 (val 0x41eb00 4320000) PIPEA_DATA_M2: 0x00000000 (TU 1, val 0x0 0) PIPEA_DATA_N2: 0x00000000 (val 0x0 0) PIPEA_LINK_M1: 0x00024414 (val 0x24414 148500) PIPEA_LINK_N1: 0x00041eb0 (val 0x41eb0 270000) PIPEA_LINK_M2: 0x00000000 (val 0x0 0) PIPEA_LINK_N2: 0x00000000 (val 0x0 0) DSPACNTR: 0xd8004400 (enabled) DSPABASE: 0x00000000 DSPASTRIDE: 0x00001e00 (120) DSPASURF: 0x0084d000 DSPATILEOFF: 0x00000000 (0, 0) PIPEBCONF: 0x00000000 (disabled, inactive, pf-pd, rotate 0, 8bpc) HTOTAL_B: 0x031f027f (640 active, 800 total) HBLANK_B: 0x031f027f (640 start, 800 end) HSYNC_B: 0x02ef028f (656 start, 752 end) VTOTAL_B: 0x020c01df (480 active, 525 total) VBLANK_B: 0x020c01df (480 start, 525 end) VSYNC_B: 0x01eb01e9 (490 start, 492 end) VSYNCSHIFT_B: 0x00000000 PIPEBSRC: 0x027f01df (640, 480) PIPEB_DATA_M1: 0x00000000 (TU 1, val 0x0 0) PIPEB_DATA_N1: 0x00000000 (val 0x0 0) PIPEB_DATA_M2: 0x00000000 (TU 1, val 0x0 0) PIPEB_DATA_N2: 0x00000000 (val 0x0 0) PIPEB_LINK_M1: 0x00000000 (val 0x0 0) PIPEB_LINK_N1: 0x00000000 (val 0x0 0) PIPEB_LINK_M2: 0x00000000 (val 0x0 0) PIPEB_LINK_N2: 0x00000000 (val 0x0 0) DSPBCNTR: 0x00004000 (disabled) DSPBBASE: 0x00000000 DSPBSTRIDE: 0x00000500 (20) DSPBSURF: 0x00000000 DSPBTILEOFF: 0x00000000 (0, 0) PIPECCONF: 0x00000000 (disabled, inactive, pf-pd, rotate 0, 8bpc) HTOTAL_C: 0x00000000 (1 active, 1 total) HBLANK_C: 0x00000000 (1 start, 1 end) HSYNC_C: 0x00000000 (1 start, 1 end) VTOTAL_C: 0x00000000 (1 active, 1 total) VBLANK_C: 0x00000000 (1 start, 1 end) VSYNC_C: 0x00000000 (1 start, 1 end) VSYNCSHIFT_C: 0x00000000 PIPECSRC: 0x00000000 (1, 1) PIPEC_DATA_M1: 0x00000000 (TU 1, val 0x0 0) PIPEC_DATA_N1: 0x00000000 (val 0x0 0) PIPEC_DATA_M2: 0x00000000 (TU 1, val 0x0 0) PIPEC_DATA_N2: 0x00000000 (val 0x0 0) PIPEC_LINK_M1: 0x00000000 (val 0x0 0) PIPEC_LINK_N1: 0x00000000 (val 0x0 0) PIPEC_LINK_M2: 0x00000000 (val 0x0 0) PIPEC_LINK_N2: 0x00000000 (val 0x0 0) DSPCCNTR: 0x00004000 (disabled) DSPCBASE: 0x00000000 DSPCSTRIDE: 0x00000000 (0) DSPCSURF: 0x00000000 DSPCTILEOFF: 0x00000000 (0, 0) PFA_CTL_1: 0x00000000 (disable, auto_scale yes, auto_scale_cal no, v_filter enable, vadapt disable, mode least, filter_sel programmed,chroma pre-filter disable, vert3tap auto, v_inter_invert field 1) PFA_CTL_2: 0x00007de4 (vscale 0.983521) PFA_CTL_3: 0x00003ef2 (vscale initial phase 0.491760) PFA_CTL_4: 0x00007c40 (hscale 0.970703) PFA_WIN_POS: 0x00000000 (0, 0) PFA_WIN_SIZE: 0x00000000 (0, 0) PFB_CTL_1: 0x00000000 (disable, auto_scale yes, auto_scale_cal no, v_filter enable, vadapt disable, mode least, filter_sel programmed,chroma pre-filter disable, vert3tap auto, v_inter_invert field 1) PFB_CTL_2: 0x00007de4 (vscale 0.983521) PFB_CTL_3: 0x00003ef2 (vscale initial phase 0.491760) PFB_CTL_4: 0x00007c40 (hscale 0.970703) PFB_WIN_POS: 0x00000000 (0, 0) PFB_WIN_SIZE: 0x00000000 (0, 0) PFC_CTL_1: 0x00000000 (disable, auto_scale yes, auto_scale_cal no, v_filter enable, vadapt disable, mode least, filter_sel programmed,chroma pre-filter disable, vert3tap auto, v_inter_invert field 1) PFC_CTL_2: 0x00007de4 (vscale 0.983521) PFC_CTL_3: 0x00003ef2 (vscale initial phase 0.491760) PFC_CTL_4: 0x00007c40 (hscale 0.970703) PFC_WIN_POS: 0x00000000 (0, 0) PFC_WIN_SIZE: 0x00000000 (0, 0) PCH_DREF_CONTROL: 0x00000000 (cpu source disable, ssc_source disable, nonspread_source disable, superspread_source disable, ssc4_mode downspread, ssc1 disable, ssc4 disable) PCH_RAWCLK_FREQ: 0x00000018 (FDL_TP1 timer 0.5us, FDL_TP2 timer 1.5us, freq 24) PCH_DPLL_TMR_CFG: 0x00000018 PCH_SSC4_PARMS: 0x00000018 PCH_SSC4_AUX_PARMS: 0x00000018 PCH_DPLL_SEL: 0x00000018 (FDL_TP1 timer 0.5us, FDL_TP2 timer 1.5us, freq 24) PCH_DPLL_ANALOG_CTL: 0x00000018 PCH_DPLL_A: 0x00000018 (disable, sdvo high speed no, mode (null), p2 (null), FPA0 P1 0, FPA1 P1 4, refclk default 120Mhz, sdvo/hdmi mul 1) PCH_DPLL_B: 0x00000018 (disable, sdvo high speed no, mode (null), p2 (null), FPA0 P1 0, FPA1 P1 4, refclk default 120Mhz, sdvo/hdmi mul 1) PCH_FPA0: 0x00000018 (n = 0, m1 = 0, m2 = 24) PCH_FPA1: 0x00000018 (n = 0, m1 = 0, m2 = 24) PCH_FPB0: 0x00000018 (n = 0, m1 = 0, m2 = 24) PCH_FPB1: 0x00000018 (n = 0, m1 = 0, m2 = 24) TRANS_HTOTAL_A: 0x00000018 (25 active, 1 total) TRANS_HBLANK_A: 0x00000018 (25 start, 1 end) TRANS_HSYNC_A: 0x00000018 (25 start, 1 end) TRANS_VTOTAL_A: 0x00000018 (25 active, 1 total) TRANS_VBLANK_A: 0x00000018 (25 start, 1 end) TRANS_VSYNC_A: 0x00000018 (25 start, 1 end) TRANS_VSYNCSHIFT_A: 0x00000018 TRANSA_DATA_M1: 0x00000018 (TU 1, val 0x18 24) TRANSA_DATA_N1: 0x00000018 (val 0x18 24) TRANSA_DATA_M2: 0x00000018 (TU 1, val 0x18 24) TRANSA_DATA_N2: 0x00000018 (val 0x18 24) TRANSA_DP_LINK_M1: 0x00000018 (val 0x18 24) TRANSA_DP_LINK_N1: 0x00000018 (val 0x18 24) TRANSA_DP_LINK_M2: 0x00000018 (val 0x18 24) TRANSA_DP_LINK_N2: 0x00000018 (val 0x18 24) TRANS_HTOTAL_B: 0x00000018 (25 active, 1 total) TRANS_HBLANK_B: 0x00000018 (25 start, 1 end) TRANS_HSYNC_B: 0x00000018 (25 start, 1 end) TRANS_VTOTAL_B: 0x00000018 (25 active, 1 total) TRANS_VBLANK_B: 0x00000018 (25 start, 1 end) TRANS_VSYNC_B: 0x00000018 (25 start, 1 end) TRANS_VSYNCSHIFT_B: 0x00000018 TRANSB_DATA_M1: 0x00000018 (TU 1, val 0x18 24) TRANSB_DATA_N1: 0x00000018 (val 0x18 24) TRANSB_DATA_M2: 0x00000018 (TU 1, val 0x18 24) TRANSB_DATA_N2: 0x00000018 (val 0x18 24) TRANSB_DP_LINK_M1: 0x00000018 (val 0x18 24) TRANSB_DP_LINK_N1: 0x00000018 (val 0x18 24) TRANSB_DP_LINK_M2: 0x00000018 (val 0x18 24) TRANSB_DP_LINK_N2: 0x00000018 (val 0x18 24) TRANS_HTOTAL_C: 0x00000000 (1 active, 1 total) TRANS_HBLANK_C: 0x00000000 (1 start, 1 end) TRANS_HSYNC_C: 0x00000000 (1 start, 1 end) TRANS_VTOTAL_C: 0x00000000 (1 active, 1 total) TRANS_VBLANK_C: 0x00000000 (1 start, 1 end) TRANS_VSYNC_C: 0x00000000 (1 start, 1 end) TRANS_VSYNCSHIFT_C: 0x00000000 TRANSC_DATA_M1: 0x00000000 (TU 1, val 0x0 0) TRANSC_DATA_N1: 0x00000000 (val 0x0 0) TRANSC_DATA_M2: 0x00000000 (TU 1, val 0x0 0) TRANSC_DATA_N2: 0x00000000 (val 0x0 0) TRANSC_DP_LINK_M1: 0x00000000 (val 0x0 0) TRANSC_DP_LINK_N1: 0x00000000 (val 0x0 0) TRANSC_DP_LINK_M2: 0x00000000 (val 0x0 0) TRANSC_DP_LINK_N2: 0x00000000 (val 0x0 0) TRANSACONF: 0x00000018 (disable, inactive, progressive) TRANSBCONF: 0x00000018 (disable, inactive, progressive) TRANSCCONF: 0x00000018 (disable, inactive, progressive) FDI_TXA_CTL: 0x00000000 (disable, train pattern pattern_1, voltage swing 0.4V,pre-emphasis none, port width X1, enhanced framing disable, FDI PLL disable, scrambing enable, master mode disable) FDI_TXB_CTL: 0x00000000 (disable, train pattern pattern_1, voltage swing 0.4V,pre-emphasis none, port width X1, enhanced framing disable, FDI PLL disable, scrambing enable, master mode disable) FDI_TXC_CTL: 0x00000000 (disable, train pattern pattern_1, voltage swing 0.4V,pre-emphasis none, port width X1, enhanced framing disable, FDI PLL disable, scrambing enable, master mode disable) FDI_RXA_CTL: 0x00000018 (disable, train pattern pattern_1, port width X1, 8bpc,link_reverse_strap_overwrite no, dmi_link_reverse no, FDI PLL disable,FS ecc disable, FE ecc disable, FS err report disable, FE err report disable,scrambing enable, enhanced framing disable, PCDClk) FDI_RXB_CTL: 0x00000018 (disable, train pattern pattern_1, port width X1, 8bpc,link_reverse_strap_overwrite no, dmi_link_reverse no, FDI PLL disable,FS ecc disable, FE ecc disable, FS err report disable, FE err report disable,scrambing enable, enhanced framing disable, PCDClk) FDI_RXC_CTL: 0x00000018 (disable, train pattern pattern_1, port width X1, 8bpc,link_reverse_strap_overwrite no, dmi_link_reverse no, FDI PLL disable,FS ecc disable, FE ecc disable, FS err report disable, FE err report disable,scrambing enable, enhanced framing disable, PCDClk) FDI_RXA_MISC: 0x00000018 (FDI Delay 24) FDI_RXB_MISC: 0x00000018 (FDI Delay 24) FDI_RXC_MISC: 0x00000018 (FDI Delay 24) FDI_RXA_TUSIZE1: 0x00000018 FDI_RXA_TUSIZE2: 0x00000018 FDI_RXB_TUSIZE1: 0x00000018 FDI_RXB_TUSIZE2: 0x00000018 FDI_RXC_TUSIZE1: 0x00000018 FDI_RXC_TUSIZE2: 0x00000018 FDI_PLL_CTL_1: 0x00000018 FDI_PLL_CTL_2: 0x00000018 FDI_RXA_IIR: 0x00000018 FDI_RXA_IMR: 0x00000018 FDI_RXB_IIR: 0x00000018 FDI_RXB_IMR: 0x00000018 PCH_ADPA: 0x00000018 (disabled, transcoder A, +hsync, +vsync) HDMIB: 0x00000000 (disabled pipe A 8bpc SDVO DVI audio disabled -vsync -hsync non-detected) HDMIC: 0x00000000 (disabled pipe A 8bpc SDVO DVI audio disabled -vsync -hsync non-detected) HDMID: 0x00000000 (disabled pipe A 8bpc SDVO DVI audio disabled -vsync -hsync non-detected) PCH_LVDS: 0x00000000 (disabled, pipe A, 18 bit, 1 channel) CPU_eDP_A: 0x00000090 PCH_DP_B: 0x00000018 PCH_DP_C: 0x00000018 PCH_DP_D: 0x00000018 TRANS_DP_CTL_A: 0x00000000 (disabled, pipe A, 18 bit, 1 channel) TRANS_DP_CTL_B: 0x00000000 (disabled, pipe A, 18 bit, 1 channel) TRANS_DP_CTL_C: 0x00000000 (disabled, pipe A, 18 bit, 1 channel) BLC_PWM_CPU_CTL2: 0x60000000 BLC_PWM_CPU_CTL: 0x00000000 BLC_PWM_PCH_CTL1: 0x00000000 BLC_PWM_PCH_CTL2: 0x00000000 PCH_PP_STATUS: 0x00000000 (off, not ready, sequencing idle) PCH_PP_CONTROL: 0xabcd0000 (blacklight disabled, do not power down on reset, panel off) PCH_PP_ON_DELAYS: 0x00000000 PCH_PP_OFF_DELAYS: 0x00000000 PCH_PP_DIVISOR: 0x0004af06 PORT_DBG: 0x00000000 (HW DRRS off) RC6_RESIDENCY_TIME: 0x027aa896 RC6p_RESIDENCY_TIME: 0x00000000 RC6pp_RESIDENCY_TIME: 0x00000000 GEN6_RP_CONTROL: 0x00000d92 (enabled) GEN6_RPNSWREQ: 0x28000000 GEN6_RP_DOWN_TIMEOUT: 0x000f4240 GEN6_RP_INTERRUPT_LIMITS: 0x00040000 GEN6_RP_UP_THRESHOLD: 0x0000e808 GEN6_RP_UP_EI: 0x000101d0 GEN6_RP_DOWN_EI: 0x00055730 GEN6_RP_IDLE_HYSTERSIS: 0x0000000a GEN6_RC_STATE: 0x00000000 GEN6_RC_CONTROL: 0x88040000 GEN6_RC1_WAKE_RATE_LIMIT: 0x03e80000 GEN6_RC6_WAKE_RATE_LIMIT: 0x0028001e GEN6_RC_EVALUATION_INTERVAL: 0x0001e848 GEN6_RC_IDLE_HYSTERSIS: 0x00000019 GEN6_RC_SLEEP: 0x00000000 GEN6_RC1e_THRESHOLD: 0x000003e8 GEN6_RC6_THRESHOLD: 0x0000c350 GEN6_RC_VIDEO_FREQ: 0x18000000 GEN6_PMIER: 0x03000076 GEN6_PMIMR: 0x00000000 GEN6_PMINTRMSK: 0x00000000 HSW_PWR_WELL_CTL1: 0xc0000000 HSW_PWR_WELL_CTL2: 0x40000000 HSW_PWR_WELL_CTL3: 0x40000000 HSW_PWR_WELL_CTL4: 0x40000000 HSW_PWR_WELL_CTL5: 0x0004050f HSW_PWR_WELL_CTL6: 0x00000000 PIPE_DDI_FUNC_CTL_A: 0x90030000 PIPE_DDI_FUNC_CTL_B: 0x00005000 PIPE_DDI_FUNC_CTL_C: 0x00030000 PIPE_DDI_FUNC_CTL_EDP: 0x00030000 DP_TP_CTL_A: 0x00000000 DP_TP_CTL_B: 0x00000000 DP_TP_CTL_C: 0x00000000 DP_TP_CTL_D: 0x00000000 DP_TP_CTL_E: 0x00000000 DP_TP_STATUS_A: 0x00000000 DP_TP_STATUS_B: 0x00000000 DP_TP_STATUS_C: 0x00000000 DP_TP_STATUS_D: 0x00000000 DP_TP_STATUS_E: 0x00000000 DDI_BUF_CTL_A: 0x00000090 DDI_BUF_CTL_B: 0x80000000 DDI_BUF_CTL_C: 0x00000000 DDI_BUF_CTL_D: 0x00000000 DDI_BUF_CTL_E: 0x00000000 PIXCLK_GATE: 0x0004af06 SPLL_CTL: 0x00000000 LCPLL_CTL: 0x40000037 WRPLL_CTL1: 0xb0210614 WRPLL_CTL2: 0x30652639 PORT_CLK_SEL_A: 0xe0000000 PORT_CLK_SEL_B: 0x80000000 PORT_CLK_SEL_C: 0xe0000000 PORT_CLK_SEL_D: 0xe0000000 PORT_CLK_SEL_E: 0xe0000000 PIPE_CLK_SEL_A: 0x40000000 PIPE_CLK_SEL_B: 0x00000000 PIPE_CLK_SEL_C: 0x00000000 PIPE_WM_LINETIME_A: 0x00000060 PIPE_WM_LINETIME_B: 0x00000000 PIPE_WM_LINETIME_C: 0x00000000 SFUSE_STRAP: 0x00000006 ubuntu@ubuntu:~$ Many thanks for help. Haswell NUC HD5000. Thanks, but could you please do this for both settings in the UEFI BIOS, and let me know which setting was used? Makes things much easier. Oh and thanks everyone else for attaching their dump. No longer required. Link to comment Share on other sites More sharing options...
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