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ErmaC
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3 hours ago, Sherlocks said:

 

i did clean all. and build again. strange. there is another issue.

 

 

Same issue here. Xcode 11.2.1/ Mojave 10.14.6

 

Spoiler

[CC] usbfix
/Users/mathieu/src/CloverBootloader/rEFIt_UEFI/cpp_util/XStringW.cpp:239:3: error: '__builtin_ms_va_start' used in System V ABI function
  VA_START (va, format);
  ^
/Users/mathieu/src/CloverBootloader/MdePkg/Include/Base.h:696:38: note: expanded from macro 'VA_START'
#define VA_START(Marker, Parameter)  __builtin_ms_va_start (Marker, Parameter)
                                     ^
/Users/mathieu/src/CloverBootloader/rEFIt_UEFI/cpp_util/XStringW.cpp:464:3: error: '__builtin_ms_va_start' used in System V ABI function
  VA_START (va, format);
  ^
/Users/mathieu/src/CloverBootloader/MdePkg/Include/Base.h:696:38: note: expanded from macro 'VA_START'
#define VA_START(Marker, Parameter)  __builtin_ms_va_start (Marker, Parameter)
                                     ^
2 errors generated.
make: *** [/Users/mathieu/src/CloverBootloader/Build/Clover/RELEASE_XCODE8/X64/rEFIt_UEFI/refit_cpp/OUTPUT/cpp_util/XStringW.obj] Error 1


build.py...
 : error 7000: Failed to execute command
    make tbuild [/Users/mathieu/src/CloverBootloader/Build/Clover/RELEASE_XCODE8/X64/rEFIt_UEFI/refit_cpp]


build.py...
 : error F002: Failed to build module
    /Users/mathieu/src/CloverBootloader/rEFIt_UEFI/refit_cpp.inf [X64, XCODE8, RELEASE]

- Failed -
Build end time: 09:30:23, Feb.17 2020
Build total time: 00:00:54

 

 

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The windows build script has some errors because changing the other build script but not the windows script. It is pretty easy to correct. Also, the tools_def.txt should just get made from the edk2 one by default. I think maybe you need to look at the config and see if some of that needs changed. Also, you need to build the build tools on windows for the first use:

edksetup.bat Rebuild
edksetup.bat

 

Edited by apianti
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3 minutes ago, Logician said:

Anyone know why I cannot enable SIP?  I have 


<key>csr-active-config</key>
<data>AAAAAA==</data>

and I see


> nvram -p
csr-active-config	g%00%00%00

but when I check, I get


>csrutil status
System Integrity Protection status: disabled.

I don't know what else to check/try.

Because the syntax is wrong

        <key>CsrActiveConfig</key>
        <string>0x3E7</string>
to disable

        <key>CsrActiveConfig</key>
        <string>0</string>
to enable

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2 minutes ago, Slice said:

Because the syntax is wrong

        <key>CsrActiveConfig</key>
        <string>0x3E7</string>
to disable

        <key>CsrActiveConfig</key>
        <string>0</string>
to enable

 

@Logician has delete his post, because he talk about OpenCore settings. 

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maybe is a bit OT here..some of clover's devs are investigating why new AMD TRX40 CPUs fails to boot with a memory allocation error in an early booting process stage?

@apianti and @slice i mean 

thank you

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29 minutes ago, fabiosun said:

maybe is a bit OT here..some of clover's devs are investigating why new AMD TRX40 CPUs fails to boot with a memory allocation error in an early booting process stage?

@apianti and @slice i mean 

thank you

There must be a developer having AMD TRX40 CPU.

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@Slice in the past there where a pretty similar problem with x99 platform  and some highend xeon and you ( the devs) solved that problem with a try and error process creating new aptiomemory driver...

Edited by Guest
Typo
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9 hours ago, fabiosun said:

@Slice in the past there where a pretty similar problem with x99 platform  and some highend xeon and you ( the devs) solved that problem with a try and error process creating new aptiomemory driver...

I have datasheets from Intel and zero from AMD.

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2 minutes ago, Slice said:

@fabiosun

What can I do with this knowledge?

maybe you have the skill to understand why TRX40 chip fails to boot with a memory allocation errors on both main bootloader..i mean clover and acidanthera one :)

 

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8 hours ago, Slice said:

Can you show asm codes for both cases? Where is the difference?

Historically only i++ and --i had a sense because they came from PDP11 assembler where there are instruction like

MOV (R1)+,R2

MOV R3, -(SP)

So C languages is very close to those machine codes.

Intel codes are different.

 

It is inherent in the behavior of the operator. Those CPUs have a special instruction specifically to do that, it is not very common because it is super expensive. No modern CPU has any instruction like this. The most optimized code for an increment would look like these, prefix:

mov rax, [address_of_variable_to_increment]
inc rax
mov [address_of_variable_to_increment], rax

postfix:

mov rax, [address_of_variable_to_increment]
mov rbx, rax
inc rbx
mov [address_of_variable_to_increment], rbx

This is the MOST optimized that either of these operators could be, most likely there is other stuff in registers though so you need to use graph coloring algorithm to determine how to use the registers most efficiently. I've only ever seen the prefix operator come out this optimized.

 

EDIT: I forgot you could do direct memory access, although I doubt the compiler is using these but this will actually make the postfix operator perform even worse compared to the prefix,

prefix:

inc [address_of_variable_to_increment]

postfix still has to operate some way like above.

 

EDIT2: Forgot, that those operators were created in B for convenience not C (C followed B's development at Bell Labs), the PDP-11 just easily supported these because of it's crazy complicated access modes, it didn't even exist yet when those operators were created. Dennis Ritchie even says so:

Quote

People often guess that they were created to use the auto-increment and auto-decrement address modes provided by the DEC PDP-11 on which C and Unix first became popular. This is historically impossible, since there was no PDP-11 when B was developed. 

 

Edited by apianti
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