DSDT Shutdown Nvidia Dells (Not Zero, SLPE trick) Alternate ich8 method

[LatinMcG]

i seem to have found partially why the M1530 Shutdown works with _PTS Store (Zero, SLPE)

HOWEVER it does NOT work for some models with NVIDIA Video like M1330 and Vostro 1500 and inspiron 1420, 1520, 1720 and a few others

 

SLPE is defined as 0x1030 bit 4 normaly 1 .. set 0 to do what ? = SLP_SMI_EN

 

http://www.intel.com/content/dam/doc/datas...8-datasheet.pdf

 

more info on what this is all about for past 2 years.

http://www.insanelymac.com/forum/index.php...t&p=1741624

 

SLP_SMI_EN — R/W.

0 = Disables the generation of SMI# on SLP_EN. Note that this bit must be 0 before

the software attempts to transition the system into a sleep state by writing a 1 to

the SLP_EN bit.(in

1 = A write of 1 to the SLP_EN bit (bit 13 in PM1_CNT register) will generate an SMI#,

and the system will not transition to the sleep state based on that write to the

SLP_EN bit.

==================

 

apparently it confused someone on its function

but we need SLP_TYP 0x07 or 0x7 = 111b ? in bit 10 and 12 ? bit 12:10

then SLP_EN in 0x1004 bit 13 One

 

i want to write proper SystemIO table for PM1A 0x1004 with

SLP_TYP,

SLP_EN,

anything else on the intel ich8 hub doc for it

 

so i can play with shutdown in _PTS or _GTS

 

i believe i have to also set 0 to PME_B0_EN and/or SCI_EN ?

 

PME_B0_STS — R/WC. This bit will be set to 1 by the ICH8 when any internal

device with PCI Power Management capabilities on bus 0 asserts the equivalent of

the PME# signal. Additionally, if the PME_B0_EN bit is set, and the system is in an

S0 state, then the setting of the PME_B0_STS bit will generate an SCI (or SMI# if

SCI_EN is not set). If the PME_B0_STS bit is set, and the system is in an S1–S4

state (or S5 state due to SLP_TYP and SLP_EN), then the setting of the

PME_B0_STS bit will generate a wake event, and an SCI (or SMI# if SCI_EN is not

set) will be generated. If the system is in an S5 state due to power button

override, then the PME_B0_STS bit will not cause a wake event or SCI.

The default for this bit is 0. Writing a 1 to this bit position clears this bit.

Note: On ICH8, HD audio wake events are changed to be reported in this bit.

ME “maskable” wake events are also reported in this bit.

 

i have this so far.. i get NO console with /home unmount fail shutdown Not working (yet).

i think a wake monitor register for gpe is still enabled

 

im sure this is wrong but its a start

    OperationRegion (PM1A, SystemIO, 0x1004, 0x13)
   Field (PM1A, ByteAcc, NoLock, Preserve)
   {
           ,   10, 
       OFFX,   8, 
           ,   12, 
       OFF2,   8, 
           ,   13, 
       OFFD,   1
   }

   OperationRegion (PMRS, SystemIO, 0x1030, One)
   Field (PMRS, ByteAcc, NoLock, Preserve)
   {
           ,   4, 
       SLEN,   1
   }

   Method (_PTS, 1, NotSerialized)
   {
       If (LEqual (Arg0, 0x05))
       {
           SMI (0x8A, 0x05)
           Store (Zero, SLEN)
           Store (0x07, OFF2)
           Store (0x07, OFFX)
           Store (One, OFFD)
           Sleep (0x10)
       }
       Else
       {
           Store (SMI (0x46, Zero), MIS1)
           SMI (0x8A, Arg0)
           Store (One, SMBD)
       }
   }

original_PTS

	Method (_PTS, 1, NotSerialized)
	{
		Store (SMI (0x46, Zero), MIS1)
		SMI (0x8A, Arg0)
	}

 

Progress ! i got restart instead of shutdown with this code order. i believe its missing the AFTERG3_ in the hub 8 doc. or GP0 disable enable issue.

	OperationRegion (PMBS, SystemIO, 0x1000, 0x13)
Field (PMBS, ByteAcc, NoLock, Preserve)
{
			Offset (0x04), 
		,   12, 
	OFF2,   8, 
		,   13, 
	OFFD,   1
}

OperationRegion (PMRS, SystemIO, 0x1030, One)
Field (PMRS, ByteAcc, NoLock, Preserve)
{
		,   4, 
	SLEN,   1
}

Method (_PTS, 1, NotSerialized)
{
	Store (SMI (0x46, Zero), MIS1)
	SMI (0x8A, Arg0)
	Store (One, SMBD)
	If (LGreaterEqual (Arg0, 0x05))
	{
		Store (Zero, SLEN) // SLP_SMI_EN used to be SLPE
		Store (0x07, OFF2) // SLP_TYP 0x07 = 111
		Store (One, OFFD) // DO IT!  (THE REAL SLPE) SLP_EN
		Sleep (0x10) // Time to wait 
	}
}

 

interesting coreboot descriptions of ich hub

@@ -32,6 +42,7 @@

#define PCICMD          0x04
#define PMBASE          0x40
+#define   PMBASE_ADDR	0x0400 // should be 0x1000 for dells
#define ACPI_CNTL       0x44
#define BIOS_CNTL       0x4E
#define GPIO_BASE       0x58
@@ -78,4 +89,75 @@
 */
#define SMBUS_TIMEOUT (100*1000)

-#endif /* I82801DBM_H */
+#define PM1_STS		0x00
+#define   WAK_STS	(1 << 15)
+#define   PCIEXPWAK_STS	(1 << 14)
+#define   PRBTNOR_STS	(1 << 11)
+#define   RTC_STS	(1 << 10)
+#define   PWRBTN_STS	(1 << 8)
+#define   GBL_STS	(1 << 5)
+#define   BM_STS	(1 << 4)
+#define   TMROF_STS	(1 << 0)
+#define PM1_EN		0x02 // heres the stuff we need ich8 hub doc 9.8.3.2
+#define   PCIEXPWAK_DIS	(1 << 14)
+#define   RTC_EN	(1 << 10)
+#define   PWRBTN_EN	(1 << 8)
+#define   GBL_EN	(1 << 5)
+#define   TMROF_EN	(1 << 0)
+#define PM1_CNT		0x04 // heres the stuff we need also details at ich8 hub doc 9.8.3.3
+#define   SLP_EN	(1 << 13) // DO IT! GO TO SLEEP ! but it hasnt yet.
+#define   SLP_TYP	(7 << 10) // ohh it s10 not 12 ? in ich8 hub doc 9.8.3.3 says 12:10 hmm store 0x7 = 111 110 is _S4 aka 0x6
+#define   GBL_RLS	(1 << 2)
+#define   BM_RLD	(1 << 1)
+#define   SCI_EN	(1 << 0)
+#define PM1_TMR		0x08
+#define PROC_CNT	0x10
+#define LV2		0x14
+#define LV3		0x15
+#define LV4		0x16
+#define PM2_CNT		0x20 // mobile only ich8 hub doc 9.8.3.11
+#define GPE0_STS	0x28
+#define   PME_B0_STS	(1 << 13)
+#define   USB3_STS	(1 << 12)
+#define   PME_STS	(1 << 11)
+#define   BATLOW_STS	(1 << 10)
+#define   GST_STS	(1 << 9)
+#define   RI_STS	(1 << 8)
+#define   SMB_WAK_STS	(1 << 7)
+#define   TCOSCI_STS	(1 << 6)
+#define   AC97_STS	(1 << 5)
+#define   USB2_STS	(1 << 4)
+#define   USB1_STS	(1 << 3)
+#define   SWGPE_STS	(1 << 2)
+#define   HOT_PLUG_STS	(1 << 1)
+#define   THRM_STS	(1 << 0)
+#define GPE0_EN		0x2c //ich8 hub doc 9.8.3.13
+#define   PME_B0_EN	(1 << 13)
+#define   PME_EN	(1 << 11)
+#define SMI_EN		0x30
+#define   EL_SMI_EN	 (1 << 25) // Intel Quick Resume Technology
+#define   INTEL_USB2_EN	 (1 << 18) // Intel-Specific USB2 SMI logic
+#define   LEGACY_USB2_EN (1 << 17) // Legacy USB2 SMI logic
+#define   PERIODIC_EN	 (1 << 14) // SMI on PERIODIC_STS in SMI_STS
+#define   TCO_EN	 (1 << 13) // Enable TCO Logic (BIOSWE et al)
+#define   MCSMI_EN	 (1 << 11) // Trap microcontroller range access
+#define   BIOS_RLS	 (1 <<  7) // asserts SCI on bit set
+#define   SWSMI_TMR_EN	 (1 <<  6) // start software smi timer on bit set
+#define   APMC_EN	 (1 <<  5) // Writes to APM_CNT cause SMI#
+#define   SLP_SMI_EN	 (1 <<  4) // Write to SLP_EN in PM1_CNT asserts SMI#.. hey its good ol SLPE, in _PTS
+#define   LEGACY_USB_EN  (1 <<  3) // Legacy USB circuit SMI logic
+#define   BIOS_EN	 (1 <<  2) // Assert SMI# on setting GBL_RLS bit
+#define   EOS		 (1 <<  1) // End of SMI (deassert SMI#)
+#define   GBL_SMI_EN	 (1 <<  0) // SMI# generation at all?
+#define SMI_STS		0x34
+#define ALT_GP_SMI_EN	0x38
+#define ALT_GP_SMI_STS	0x3a
+#define GPE_CNTL	0x42
+#define DEVACT_STS	0x44
+#define SS_CNT		0x50
+#define C3_RES		0x54
+
+#define TCOBASE		0x60 /* TCO Base Address Register */  ich8 hub doc 9.9.6
+#define TCO1_CNT	0x08 /* TCO1 Control Register */
+
+#endif /* I82801DX_H */

 

my dsdt with attempt to shutdown is attached (not working yet .. but soon i hope)

1520nv8600dsdtshutdownNo.aml.zip

[LatinMcG]

Still no shutdown. but restart instead

im geting closer... i can feel it

	OperationRegion (PMBR, SystemIO, 0x1000, 0x40)
Field (PMBR, ByteAcc, NoLock, Preserve)
{
			Offset (0x04), 
	SCIN,   1, 
		,   10, 
	SLPT,   1, 
		,   1, 
	SP12,   1, 
		,   1, 
	SLPE,   1
}

OperationRegion (PMRS, SystemIO, 0x1030, One)
Field (PMRS, ByteAcc, NoLock, Preserve)
{
		,   4, 
	SLEN,   1
}

OperationRegion (LPC0, PCI_Config, 0xA4, 0x02)
Field (LPC0, ByteAcc, NoLock, Preserve)
{
	AG3E,   1
}

Method (_PTS, 1, NotSerialized)
{
	Store (SMI (0x46, Zero), MIS1)
	SMI (0x8A, Arg0)
}

Method (_GTS, 1, NotSerialized)
{
	If (LGreaterEqual (Arg0, 0x05))
	{
		Store (One, AG3E)
		Store (Zero, SLEN)
		Store (0x07, SLPT)
		Store (One, SLPE)
		Sleep (0x10)
	}
}

 

ohh nice i found a vostro 3400 dsdt with better descriptions ( find _PTS in the page seems it has 2 methods for PTS)

https://lists.launchpad.net/hybrid-graphics...x/msg00483.html

		  Device (SBRG)
		{
			Name (_ADR, 0x001F0000)
			Method (SPTS, 1, NotSerialized) // Soft _PTS ?
			{
				Store (One, PS1S)
				Store (One, PS1E)
				Store (One, SLPS)
			}

			Method (SWAK, 1, NotSerialized) //Soft Wake ?
			{
				Store (Zero, SLPS)
				Store (Zero, PS1E)
				If (RTCS) {} // RTC Status. 
				Else
				{
					Notify (PWRB, 0x02)
				}
			}

			OperationRegion (APMP, SystemIO, SMIP, 0x02) // 9.8.2.1 APM_CNT
// Advanced Power Management Control Port.. (Name (SMIP, 0xB2))
			Field (APMP, ByteAcc, NoLock, Preserve)
			{
				APMC,   8, // SMIC in our dsdt in SMIR
				APMS,   8 // SMID
			}

			Field (APMP, ByteAcc, NoLock, Preserve) // part of above APMP
			{
						Offset (0x01),  //Offset 1 of our SMIR in our dsdt
					,   1, 
				BRTC,   1 // ?
			}

			OperationRegion (SMIE, SystemIO, PM30, 0x08) // in our M08 dsdt is 0x1030.
//  in this dsdt defined way up top at dsdt begining   Name (PM30, 0x0430)
			Field (SMIE, ByteAcc, NoLock, Preserve)
			{
					,   4, 
				PS1E,   1, // SPLE in M1530
					,   31, 
				PS1S,   1, // STATUS of SLP_SMI_EN aka SLPE
						Offset (0x08)
			}

			Scope (\_SB)
			{
				Name (SLPS, Zero)
				OperationRegion (PMS0, SystemIO, PMBS, 0x04) //  9.8.3.1 PM1_STS

// in vostro3400 defined at begining as Name (PMBS, 0x0400) ours is 0x1000
				Field (PMS0, ByteAcc, NoLock, Preserve)
				{
						,   10, // bit #
					RTCS,   1, // RTC Status (RTC_STS)
						,   3,  // skip 3 bits
					PEXS,   1, // PCI Express Wake Status (PCIEXPWAK_STS)
					WAKS,   1, // Wake Status (WAK_STS)
							Offset (0x03), 
					PWBT,   1, // not sure 9.8.2.2 APM_STS—APM Status Port Register?
							Offset (0x04)
				}

				Device (SLPB)
				{
					Name (_HID, EisaId ("PNP0C0E"))
					Method (_STA, 0, NotSerialized)
					{
						If (LNotEqual (SUSW, 0xFF))
						{
							Return (0x0F)
						}
						Else
						{
							Return (Zero)
						}
					}

					Method (_PRW, 0, NotSerialized)
					{
						If (LNotEqual (SUSW, 0xFF)) // if SUSW is not enabled 11111111
						{
							Return (Package (0x02)
							{
								SUSW, 
								0x04
							})
						}
						Else
						{
							Return (Package (0x02)
							{
								Zero, 
								Zero
							})
						}
					}
				}
			}

// the _pts 
Name (WOTB, Zero)
Name (WSSB, Zero)
Name (WAXB, Zero)
Method (_PTS, 1, NotSerialized)
{
	Store (Arg0, DBG8)
	If (LAnd (LEqual (Arg0, 0x04), LEqual (OSFL (), 0x02)))
	{
		Sleep (0x0BB8)
	}

	PTS (Arg0)
	Store (Zero, Index (WAKP, Zero))
	Store (Zero, Index (WAKP, One))
	Store (ASSB, WSSB)
	Store (AOTB, WOTB)
	Store (AAXB, WAXB)
	Store (Arg0, ASSB)
	Store (OSFL (), AOTB)
	Store (Zero, AAXB)
	Store (One, \_SB.SLPS)
}

Method (_WAK, 1, NotSerialized)
{
	ShiftLeft (Arg0, 0x04, DBG8)
	WAK (Arg0)
	If (ASSB)
	{
		Store (WSSB, ASSB)
		Store (WOTB, AOTB)
		Store (WAXB, AAXB)
	}

	If (DerefOf (Index (WAKP, Zero)))
	{
		Store (Zero, Index (WAKP, One))
	}
	Else
	{
		Store (Arg0, Index (WAKP, One))
	}

	Return (WAKP)
}

 

woah look at this OPTS .. Look familiar ? reversed.

i think this vostro 3400 holds the key for us to get shutdown reorganized or add a check and continues to final *PTS

	Method (OPTS, 1, NotSerialized)
{
	SMI (0x8A, Arg0)
	Store (SMI (0x46, Zero), MIS1)
}

and Method (SMIE, 0, NotSerialized) is changed along with Method (CESM further down. (adapting this might be our fix.)

 

i wonder if dcdbas would help.

commit 44a214c1611386aa49ce86c70ebcddcad8a7a3f0
Author: Stuart Hayes <stuart_hayes@yahoo.com>
Date:   Wed Mar 2 13:42:05 2011 +0100

dcdbas: force SMI to happen when expected

commit dd65c736d1b5312c80c88a64bf521db4959eded5 upstream.

The dcdbas driver can do an I/O write to cause a SMI to occur.  The SMI handler
looks at certain registers and memory locations, so the SMI needs to happen
immediately.  On some systems I/O writes are posted, though, causing the SMI to
happen well after the "outb" occurred, which causes random failures.  Following
the "outb" with an "inb" forces the write to go through even if it is posted.

Signed-off-by: Stuart Hayes <stuart_hayes@yahoo.com>
Acked-by: Doug Warzecha <douglas_warzecha@dell.com>
Signed-off-by: Jiri Kosina <jkosina@suse.cz>
Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com>

[LatinMcG]

hmm so i got reboot working. why reboot instead of shutdown ??

The monitoring
circuit, often called a Watchdog Timer (WDT), must be able to independently track the
completion of a task within its time limit. It must be able to do so independently of the OS’s state,
the CPU’s state or ability to run the OS, or the state of any other hardware device that might lead
to a system malfunction.
Upon determining that its time limit has been reached, the WDT circuit concludes that an error has
occurred and may take a variety of corrective actions. For example, it may attempt to generate a
non-maskable interrupt, reset the platform, or even force the shut-down of the platform. The WDT
may react in different ways depending on the other factors, such as measured activity from the
CPU or reception of interrupts from peripherals.

so i find this about TCO

 

9.9.7 TCO2_CNT—TCO2 Control Register

I/O Address: TCOBASE +0Ah

Attribute: R/W

Default Value: 0008h

Size: 16-bit

Lockable: No

Power Well: Resume

 

BIT 5:4

OS_POLICY — R/W. OS-based software writes to these bits to select the policy that

the BIOS will use after the platform resets due the WDT. The following convention is

recommended for the BIOS and OS:

00 = Boot normally

01 = Shut down

10 = Don’t load OS. Hold in pre-boot state and use LAN to determine next step

11 = Reserved

NOTE: These are just scratchpad bits. They should not be reset when the TCO logic

resets the platform due to Watchdog Timer.

 

further hunting why agp isnt off or returning status off. i find IOAGPDevice.h hmm destroyAGPSpace

http://developer.apple.com/library/mac/#do...es/IOAGPDevice/

[myrorym]

myrorym cheers on LatinMcG.

damn I thought there was a cheerleading emoticon. Guess I have a lot to learn, maybe this isn't the thread for me to start.

[VMonHeros]

Hi,

 

I've got a try on my M1330 and was unable to reproduce the "reboot" for the shutdown... For sure, I certainly missed something .

 

Can I have some help ?

[LatinMcG]

Hi,

 

I've got a try on my M1330 and was unable to reproduce the "reboot" for the shutdown... For sure, I certainly missed something .

 

Can I have some help ?

 

try post #2 with _GTS