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270-WS-W555 DSDT native power management modifications


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Which mod was it that finally made speedstep work? On my EVGA X58 SLI3 (e767) I have the X58 equivalents of all your mods, plus all the standard ones for Gigabyte X58 boards, and it still doesn't seem to be working. I was using DropSSDT=yes, and GenerateCStates=yes, and I had an ssdt.aml, so I'm dumping those now and I'll report back in a few.

 

Edit:

 

Still not working.

I have C2RC5 r635

In the bios I have S3, HPET 64bit, AHCI, Turbo, C1E, Speedstep on

DSDT has HPET, LPCB, TMR, IPIC, SBUS with BUS0, RTC, cosmetic fixes, and maybe some things I'm forgetting

I've tried DropSSDT y/n, GenerateCStates y/n, GeneratePStates y/n, with or without ssdt.aml

I did the change in fakesmc

I've tried iMac11,1, MacPro4,1, MacPro5,1 (after deleting the TyMCE kext), and PowerMac3,4 with my legacy kext just for fun (My case is a PowerMac3,4 case).

At one point I made a legacy kext, but I think those are only helpful if you can boot without NullCPUPM in the first place, because once I got it right it caused a panic.

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Which mod was it that finally made speedstep work? On my EVGA X58 SLI3 (e767) I have the X58 equivalents of all your mods, plus all the standard ones for Gigabyte X58 boards, and it still doesn't seem to be working. I was using DropSSDT=yes, and GenerateCStates=yes, and I had an ssdt.aml, so I'm dumping those now and I'll report back in a few.

 

Edit:

 

Still not working.

I have C2RC5 r635

In the bios I have S3, HPET 64bit, AHCI, Turbo, C1E, Speedstep on

DSDT has HPET, LPCB, TMR, IPIC, SBUS with BUS0, RTC, cosmetic fixes, and maybe some things I'm forgetting

I've tried DropSSDT y/n, GenerateCStates y/n, GeneratePStates y/n, with or without ssdt.aml

I did the change in fakesmc

I've tried iMac11,1, MacPro4,1, MacPro5,1 (after deleting the TyMCE kext), and PowerMac3,4 with my legacy kext just for fun (My case is a PowerMac3,4 case).

At one point I made a legacy kext, but I think those are only helpful if you can boot without NullCPUPM in the first place, because once I got it right it caused a panic.

For the EVGA SR-2 only an AppleLPC related DSDT modification was needed. Compare the lspci output against your Apple[HPET|LPC|RTC] kexts to make sure your related DSDT modifications are needed and correct.

Assuming those are correct, and the BIOS has HPET and CStates enabled, AppleIntelCPUPowerManagement[|Client] kexts should load and you will have NPM.

If you get a boot panic, that may give clues.

Otherwise kernel.log may have clues.

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Well let's see. lspci says my LPC is 8086:3a16, and in my DSDT I have it patched to 3a18. AppleLPC loads, and in IORegistryExplorer it shows the device id as <18 3a 00 00>, but still shows the IOName as pci8086,3a16. Is that correct? AppleHPET and AppleRTC also load, but I don't know how to identify their output in lspci.

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Well let's see. lspci says my LPC is 8086:3a16, and in my DSDT I have it patched to 3a18. AppleLPC loads, and in IORegistryExplorer it shows the device id as <18 3a 00 00>, but still shows the IOName as pci8086,3a16. Is that correct? AppleHPET and AppleRTC also load, but I don't know how to identify their output in lspci.
That's correct, and AppleHPET and AppleRTC loads so they're good there too.

Clues in panic or kernel.log?

Do the AppleIntelCPUPowerManagement[|Client] kexts load?

In IOService:/AppleACPIPlatformExpert/CPU0@0/AppleACPICPU/ACPI_SMC_PlatformPlugin do you see SpeedStep's CPUPLimit with a value of 0x0, CState's CSTinfo, and the PState's PerformanceStateArray?

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I don't know how to identify clues in the panic, so I've attached a pic.

 

In kernel.log I have these possible clues:

ACPI_SMC_PlatformPlugin::start - waitForService(resourceMatching(AppleIntelCPUPowerManagement) timed out
ACPI_SMC_PlatformPlugin::gatherCStateOverrides - failed to set c-state demotion data: -1

 

AppleIntelCPUPowerManagement loads (seen in ASP, and kextstat), but the Client doesn't.

 

I do have the PerformanceStateArray with 13 values, which I'm pretty sure is correct for the i7 950, but I don't have CPUPLimit nor CSTInfo, and I've never seen them even when I use GenerateCStates or my ssdt.aml. I've checked for them many times during the past few weeks.

post-117-1291855331_thumb.png

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I don't know how to identify clues in the panic, so I've attached a pic.

 

In kernel.log I have these possible clues:

ACPI_SMC_PlatformPlugin::start - waitForService(resourceMatching(AppleIntelCPUPowerManagement) timed out
ACPI_SMC_PlatformPlugin::gatherCStateOverrides - failed to set c-state demotion data: -1

 

AppleIntelCPUPowerManagement loads (seen in ASP, and kextstat), but the Client doesn't.

 

I do have the PerformanceStateArray with 13 values, which I'm pretty sure is correct for the i7 950, but I don't have CPUPLimit nor CSTInfo, and I've never seen them even when I use GenerateCStates or my ssdt.aml. I've checked for them many times during the past few weeks.

The panic on the AppleIntelCPUPowerManagement kext is a `type 13=general protection' fault.

If it had involved HPET there would be a DSDT fix, but the AppleHPET kext loads on your machine.

There's some information on how to debug at;

http://developer.apple.com/library/mac/#te...002/tn2063.html

 

Your kernel.log is typical for when you allow the NullCPUPowerManagement kext to load to prevent the panic, but doing so prevents you from having CStates.

 

I'm holding out hope for a bootloader fix for this and my AppleTyMCEDriver issue.

 

Slice is getting into some low level stuff with his RC5 branch;

http://www.projectosx.com/forum/index.php?showtopic=1106

 

I also want to try returning 0x0501 for my six core CPUs;

http://forge.voodooprojects.org/p/chameleon/issues/49/

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Most of that stuff is a "bit" over my head, (pun intended), but my best guess is that it has something to do with Reserved Bit Checking, page 10-58 in the Intel 64 and IA-32 Architectures Software Developer’s Manual, Volume 3A: System Programming Guide, Part 1. I'll look at it more later today when I have time, and try Slice's latest. I also have the AppleTyMCEDriver issue if I use MacPro4,1 or 5,1.

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Well, I tried Slice's Chameleon, and it didn't make a difference. I tried a couple of other RC5 versions, and then I even went back to RC4. I get the same type 13 panic in all versions. I also tried booting in 32 bit mode, and I still got the panic, but it came slightly later, which I would guess is just because of where the code is located or whatever.

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Well, I tried Slice's Chameleon, and it didn't make a difference. I tried a couple of other RC5 versions, and then I even went back to RC4. I get the same type 13 panic in all versions. I also tried booting in 32 bit mode, and I still got the panic, but it came slightly later, which I would guess is just because of where the code is located or whatever.
That's disappointing.

When I get several hours of free time I'll experiment to see if the extracted DSDT, when booting without one, is different when different settings are changed in the BIOS.

Experiments with the Gigabyte MB showed that changing from S1(POS) to S3(STR) sleep would change the resulting DSDT.

So it's possible that my testing various BIOS options that may have helped, were being masked by my DSDT overriding them.

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I haven't done a whole lot of stuff like that, but I did compare airwalk667's DSDT from his EVGA X58 with the SZ2Z bios to mine, and there really isn't much of anything that I could see, aside from the alignments for the TMR and RTC devices being different. I looked at a DSDT from a UD5 and it had a lot of other little differences that might account for things. I also looked at my FADT extracted from linux, but I don't know much about what's in there.

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I was about to give up on my X58 SLI3 completely, but then I realized that I don't really like the looks of the current Asus or Gigabyte boards that much. I think I'll hold out and see what comes in January (G1 Killer?), or if I get CPUPM loading right on here I'll just keep this. Do you think netkas would have any ideas?

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I'm looking at maybe modding the bios by replacing the evga cpu microcode with Gigabyte's. Do you think that would do it?

 

Check my post here for more details.

AFAIK the microcode comes from Intel, and the MB vendor just adds it to their BIOS.

I'm assuming it's the EVGA difference of the BIOS that causes AICPM and TyMCED issues.

It may be something that's exposed in the DSDT, and therefore can be changed, or a change to the bootloader may help.

You may want to try a BIOS editor to see what changed between versions;

http://www.rebelshavenforum.com/sis-bin/ul...52;t=000004;p=0

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Yeah I've been messing around with some of those already. I noticed the size of the cpumicrocode is like 85k in evga bios version 77, while for the latest gigabyte x58a-ud3r bios it was only 50k. Do you know what parts of the bios I should be looking at? Would it be in the ACPI table?

 

I'm posting on the evga forums to research differences between sz2z and 44, but it's hard to do without being able to say exactly why I want to know. Apparently 44 was really bad and had all kinds of bugs related to changes they made for 32nm/6 core support, and they said it caused a lot of problems for 45nm/4 core chips as well, so maybe it's a lingering bug that hasn't been fixed yet.

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Just for an experiment I just tried to boot with a DSDT from an X58A-UD3R. First I tried with NullCPUPM and the SATA ports weren't working right, so I got waiting for root device errors and stuff. Then I tried with -allowAppleCPUPM and I still got the type 13 panic. I don't know if that tells us anything or not.

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I'm making my EVGA Classified SR-2 270-WS-W555-A1 functionally as close to a dual processor Apple MacPro5,1 as possible.

...

 

 

Thanks d00d for graciously sharing your advice. I hope that you have a most happy New Year and continue to shed your light on all of us.

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So, an update on my X58 SLI3.

 

I got sound working with AppleHDA instead of VoodooHDA using the new ALC8xxHDA.kext from MacMan, which works on ALC892.

 

I've been playing with acpiexec and a full dump from ubuntu, but I don't really understand it. I figured out executing commands in the different tables, but I don't know which tables I should be testing specifically, nor what sort of errors or feedback to expect. I also downloaded a full dump from a MacPro4,1, but again, it's pretty much useless to me until I learn more about how it's all supposed to work.

 

That's all. Seriously considering the ASUS P6T6 Revolution or P6T WS Pro. If Gigabyte redoes the X58 series like they're doing those all black upcoming P67 boards though, then EVGA can kiss my white @ß.

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Thanks d00d for graciously sharing your advice. I hope that you have a most happy New Year and continue to shed your light on all of us.
Thanks, and those are some good numbers!

Any recommendations on the settings to be used for stable overclocking?

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  • 2 weeks later...
Thanks, and those are some good numbers!

Any recommendations on the settings to be used for stable overclocking?

If anyone else has trouble posting to this topic, please PM me.

Thanks.

 

Response from Tutor1;

 

Again, thank you for your insights. My system was at first hobbled like almost everyone else's until I came across your philospy that less is more. I reconfigured my system to be almost exactly like you recommend in post no. 1, except (1) I use the latest bios that allows me to set the un-core frequency to the highest setting, given the memory that I use, (2) I use Profile 1 for my ram chips - which sets the ram voltage to 1.65 and the VVT voltage to 1.4 and (3) that for every step below a processor clock ratio of 25 that I set I get an extra increase in the turbo ratio. Thus, by stepping down my 5680's from a CPU clock ratio of 25 to 20, I get a turbo ratio of 666677 from them. This allows me to use much less voltage for over clocking because my 3.33 GHz chips run at about 2.67 GHz most of the time, except when I put them under load using Cinema 4d , Vue xStream, or Maya. Then with my BCLK set to 170, I get turbo extremes in excess of 4.4 GHz (26x170=4420 and 27x170=4590).

 

Having 20 fans (including one over each of the two banks of 2000 MHz DDR3 ram chips, one directed at each of the two heat sinks near the processors and one over the NB fan) doesn't hurt either. Also, I set my bios controlled fans to run at 60% minimum and at 100% at 60 degrees centigrade. Having all of these fans keeps my system temps very cool. I call my computer a "FrankHacWinTosh" because just like Dr. Frankenstein, I designed my case based on my perceived needs with parts from other computers (horror recycling), including to cool certain components that would be stressed out from over clocking. Actually, my Dremel tools got much hotter when I was making the case than my system ever gets. I gutted a massive case that a good friend in Atlanta made for me in 1992 to house a used Macintosh IIfx mobo and used a hacksaw (ala "Hac") to cut parts from even older cases to meet my design goals. In case you'd like to know, I didn't mind retiring that 18 year old Macintosh IIfx, with that "wicked fast" 40 MHz 68030 processor.

 

Thus, I credit (1) the physical environment of the system as providing the temp control headroom necessary for keeping my system running stable 24/7 and not making me a servant of the power company and (2) you for providing an insight that, although is contrary to the conventional wisdom, is nevertheless the most effective path to follow - less is more especially when it comes to the base CPU clock ratio and more derives from increasing the turbo ratio. Thanks d00d.

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Your using a 5520 chipset so why not find a supermicro equivalent? there are people out there running on 2 cpus I have a SUPERMICRO X8DAL-i 5500 series so cant help with that...

 

but you could help me candykane :)

 

I have the Asus Z8NA-D6 with the 5500 chipset - everything working except sleep. could you send me your dsdt to compare?

 

@d00d - great to see that someone is working seriously with this board. I was thinking about buying an SR-2 almost 6 months ago. there was a guy in some forums that offered me to buy a "special bootloader" only made for this board - otherwise there wouldn´t be any chance to boot it....hahahaaa - so good that I was patient enough

 

mine 5500 is loading the AppleTyMCEDriver.kext with MacPro 4,1 - I know the sr-2 has the 5520 chipset, but could there be any helpful information for your work ?

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  • 1 month later...

I am having problems getting sleep to work with d00d's edited DSDT and NullCPUPowerManagement.kext+SleepEnabler installed.

 

The monitor blanks out when I select sleep/press the power button, but the fans never stop spinning and the system never really shuts down.

 

I set the BIOS settings as instructed and have checked and un-checked the settings in Energy Saver to see if that makes any difference.

 

Anyone have any idea what I am doing wrong?

 

The kexts I am using are:

10.6.2 Apple HDA

HDA Enabler

EvoReboot

NCPM.kext

SleepEnabler

FakeSMC

IOAHCIBlockStorage

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I am having problems getting sleep to work with d00d's edited DSDT and NullCPUPowerManagement.kext+SleepEnabler installed.

 

The monitor blanks out when I select sleep/press the power button, but the fans never stop spinning and the system never really shuts down.

 

I set the BIOS settings as instructed and have checked and un-checked the settings in Energy Saver to see if that makes any difference.

 

Anyone have any idea what I am doing wrong?

 

The kexts I am using are:

10.6.2 Apple HDA

HDA Enabler

EvoReboot

NCPM.kext

SleepEnabler

FakeSMC

IOAHCIBlockStorage

It works for me in 64bit using NullCPUPowerManagement.kext, SleepEnabler.kext from http://code.google.com/p/xnu-sleep-enabler...ues/detail?id=5 comment 24, and my DSDT_SR2-2 with MaLd0n's shutdown fix added.

I'm not sure the shutdown fix helps because I didn't test without it.

You shouldn't need EvoReboot.kext if you are using the C2RC5 bootloader.

 

orig;

   Method (_PTS, 1, NotSerialized)
   {
       Store (Arg0, DBG8)
       PTS (Arg0)
       Store (Zero, Index (WAKP, Zero))
       Store (Zero, Index (WAKP, One))
       If (LAnd (LEqual (Arg0, 0x04), LEqual (OSFL (), 0x02)))
       {
           Sleep (0x0BB8)
       }

       Store (ASSB, WSSB)
       Store (AOTB, WOTB)
       Store (AAXB, WAXB)
       Store (Arg0, ASSB)
       Store (OSFL (), AOTB)
       Store (OSYS (), OSTP)
       Store (Zero, AAXB)
   }

MaLd0n;

   Method (_PTS, 1, NotSerialized)
   {
       If (LEqual (Arg0, 0x05)) {}
       Else
       {
           Store (Arg0, DBG8)
           PTS (Arg0)
           Store (Zero, Index (WAKP, Zero))
           Store (Zero, Index (WAKP, One))
           If (LAnd (LEqual (Arg0, 0x04), LEqual (OSFL (), 0x02)))
           {
               Sleep (0x0BB8)
           }

           Store (ASSB, WSSB)
           Store (AOTB, WOTB)
           Store (AAXB, WAXB)
           Store (Arg0, ASSB)
           Store (OSFL (), AOTB)
           Store (OSYS (), OSTP)
           Store (Zero, AAXB)
       }
   }

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