DSDT fixes for Gigabyte boards

[mitch_de]

If someone can tell where i can configure that stepping (SAVE ! ) that would be of corse better than using extra voodoopower / mark.i.

Hi mitch

what you are talking about - could it be latency timings?

 

Sorry, i mean how can i adjust the AppleIntelCPU stepping up/downs threshoot .

My Pstates are already fully working + correct.

But i want to change the threshoot / make AppleIntelCPU switch faster (on less cpu %) to higher MHZ.

 

And please comment my question about that different Adresses found in the codes above:

_CST part

0x0000000000000414, // i use 414, Address here often found 814 ?

0x0000000000000415, // i use 415, Address here often found815 ?

 

also why in CST_1 part is also

One, // Type: C1

0x9D, // Latency: 157us (values higher than 156 prevent it from entering C2)

0x03E8 // Power: 1000mw

it is only in CST_0 ,

in CST_1 0x9D is One ?!

 

Thats the code belongs to my question above:

  [size=1]
...
           Method ([b]_CST, 0[/b], NotSerialized) // Master Object.
           {
               If (And (PDC0, 0x18)) // Bits 8 & 9 indicate that CST data is available (not true for CPU0).
               {
                    Return (\_PR.CPU1._CST()) // Daisy chaining our Secondary _CST Object.
               }
               Else
               {
                   Return (Package (0x02)
                   {
                       One, // Number of C-State packages: 1
                       Package (0x04)
                       {
                           ResourceTemplate ()
                           {
                               Register (FFixedHW, 
                               0x00,               // Bit Width
                               0x00,               // Bit Offset
                               0x0000000000000000, // Address
                               ,)
                           }, 
                          [color="#FF0000"] One, // Type: C1 [color="#000080"]// why is that code not also used below ???[/color]
                           0x9D, // Latency: 157us (values higher than 156 prevent it from entering C2)
                           0x03E8 // Power: 1000mw[/color]
                       }
                   })
               }
           }
       }
       Processor (CPU1, 0x01, 0x00000410, 0x06)
       {
           Name ([color="#FF0000"]PDC1, 0x80000000[/color]) // Initialized by OSPM – value for CPU1 is different (bit 8 & 9 not set).
           Method (_CST, 0, NotSerialized) // Secondary Object.
           {
              // TODO: Kick ass and demo the C5 & C6 errors!   [color="#000080"] // what does this mean, how to look after CSate errors ?[/color]
                   Return (Package (0x04)
                   {
                       0x03, 
                       Package (0x04)
                       {
                           ResourceTemplate ()
                           {
                               Register (FFixedHW, 
                                   0x01,               // Bit Width
                                   0x02,               // Bit Offset
                                   0x0000000000000000, // Address
                                   0x01,               // Access Size
                                   )
                           },
                         One,    [color="#000080"]// above there was an change of that 157 mS thing, why not here too ?[/color]
                           [color="#FF0000"]  One,[/color]   [color="#000080"]// above is 0x9D ?![/color]
                           0x03E8
                       }, 
                       Package (0x04)
                       {
                           ResourceTemplate ()
                           {
                               Register (SystemIO, 
                                   0x08,               // Bit Width
                                   0x00,               // Bit Offset
                                   0x0000000000000[color="#FF0000"]814[/color], // Address      /[color="#000080"]/in my part here 414 ?![/color]
                                   ,)
                           },
                           0x02,
                           One,
                           0x01F4
                       }, 
                       Package (0x04)
                       {
                           ResourceTemplate ()
                           {
                               Register (SystemIO, 
                                   0x08,               // Bit Width
                                   0x00,               // Bit Offset
                                   0x0000000000000[color="#FF0000"]815[/color], // Address       /[color="#000080"]/in my part here 414 ?![/color]
                                   ,)
                           },
                           0x03,
                           0x11,
                           0xFA
                       }
                   })
           }
       }
.....
       }
   }[/size]

 

Last but not least (thanks for all clearing questions!)

I see you shown for that Cstate CNFG

C1 on : 0x04038302 , my has 0x02038302 , is that wrong ?

[mm67]

Last but not least (thanks for all clearing questions!)

I see you shown for that Cstate CNFG

C1 on : 0x04038302 , my has 0x02038302 , is that wrong ?

 

I think that means number of cores, you have a dual core cpu ?

[Master Chief]

I think that means number of cores, you have a dual core cpu ?

This can easily be verified. Well, it takes a bit of time, but it can be done. First. Do you have a BIOS setting called "Max CPUID Value Limit"? Or something similar? Then please enable this option and boot into Linux, to make a new ACPIdump. That'll do the trick. Or swapping the CPU for a Duo sister

 

If someone can tell where i can configure that stepping (SAVE ! ) that would be ...

First a tip: You save a file, but it ain't safe to go out by night in Baghdad. You get the drill

 

Sorry, i mean how can i adjust the AppleIntelCPU stepping up/downs threshoot . My Pstates are already fully working + correct.

But i want to change the threshoot / make AppleIntelCPU switch faster (on less cpu %) to higher MHZ.

You'll have to change the latency for this. MatthewL can help you with this. Right Matthew?

 

And please comment my question about that different Adresses found in the codes above: _CST part

0x0000000000000414, // i use 414, Address here often found 814 ?

0x0000000000000415, // i use 415, Address here often found815?

Yes, use that when your Processor declaration block looks like this:

Processor (CPUn, 0x0n, 0x00000410, 0x06)

 

also why in CST_1 part is also

One, // Type: C1

0x9D, // Latency: 157us (values higher than 156 prevent it from entering C2)

0x03E8 // Power: 1000mw

it is only in CST_0 ,

in CST_1 0x9D is One ?!

The answer to that question is right on front of you i.e. the first CPU core may not enter C2 – and thus we use a value of 0x9D aka 157 – or your system will get sloppy. see also post #46 in the DSDT - Vanilla Speedstep thread And not entering C2 also means that it won't enter C3, C4 or whatever. Just C1. Which is natively implemented BTW – that is why the address is different.

[mitch_de]

THANKS !!

Yes, i have an C2D E7200. I have C1E enabled , CPUIDMAx disabled, E7300 CPU has only C1 feature for my knowledge .

So i should use Cstate CNFG C1 on : 0x04038302 , and not my 0x02038302 (at least i have no problem )?

Or is that 04 for Quad Intels ?

(For an ACPI dump: is there any live CD with that acpidump available ? I found some life CD but no one with that acpidump too).

How to check if Cstate is used or if changing 020... to 040... does something really ?

Problem is, that Pstates working already and so i dont know how can Cstate (together with Pstate) seen working.

 

"Yes, use that when your Processor declaration block looks like this:

CODE

Processor (CPUn, 0x01, 0x00000410, 0x06)"

 

I already (like all here i think) have that 0410 in the processor(..).

 

I meaned that 000814 / 000815 Adresses later in the CPU/CST Part:

Package (0x04)

{

ResourceTemplate ()

{

Register (SystemIO,

0x08, // Bit Width

0x00, // Bit Offset

0x0000000000000815, // i have 415 ?!

,)

},

...

}

same with 0x0000000000000814, // i have 414 ?!

Why is that (here often posted) 814/815 and not 414 / 415 ?

[mm67]

Yes, use that when your Processor declaration block looks like this:

Processor (CPUn, 0x0n, 0x00000410, 0x06)

 

 

The answer to that question is right on front of you i.e. the first CPU core may not enter C2 – and thus we use a value of 0x9D aka 157 – or your system will get sloppy. And not entering C2 also means that it won't enter C3, C4 or whatever. Just C1. Which is natively implemented BTW – that is why the address is different.

 

Have you somehow verified that the values in CST table actually work, I am now running with a CST table that looks like this and I can't see any difference in temperatures or performance.

        Method (_CST, 0, NotSerialized)
       {
           Return (Package (0x04)
           {
               0x03, 
               Package (0x04) {ResourceTemplate () {Register (FFixedHW, 0x00, 0x02, 0, ,)},0x01,0,0}, 
               Package (0x04) {ResourceTemplate () {Register (FFixedHW, 0x01, 0x02, 0, ,)},0x02,0,0}, 
               Package (0x04) {ResourceTemplate () {Register (FFixedHW, 0x01, 0x02, 0, ,)},0x03,0,0}, 
           })
       }

[Master Chief]

Have you somehow verified that the values in CST table actually work, I am now running with a CST table that looks like this and I can't see any difference in temperatures or performance.

 <snip />

A colleague checked his C-State LED's on his motherboard. It works for him. I personally don't have these LED's so I cannot verify this (not with my own hack) but the core temperature drop of 25 around degrees Celsius should at least tell something doesn't it?

[mm67]

THANKS !!

Yes, i have an C2D E7200. I have C1E enabled , CPUIDMAx disabled, E7300 CPU has only C1 feature for my knowledge .

So i should use Cstate CNFG C1 on : 0x04038302 , and not my 0x02038302 (at least i have no problem )?

Or is that 04 for Quad Intels ?

 

You should use 0x02048302, if you use 0x02038302 your IST tables won't load.

 

 

A colleague checked his C-State LED's on his motherboard. It works for him. I personally don't have these LED's so I can verify this myself, with my P5K PRO hack, but the core temperature drop of 25 degrees Celsius should at least tell something doesn't it?

 

What I mean is that C-states work both ways, giving exactly the same temperatures. If I remove CST totally then I get a 5 degree raise in temperatures.

[asapreta]

Guys, I´m trying to follow your thoughts and have been reading this thread but now I'm sorta lost!

It´s an amazing work, it should be compiled and categorized but sections (USB, P-States, sound, NIC, etc.)

 

Can you guys make a little explanation and summarize what are you doing.

 

I, as far as I can tell, think you are managing to get rid the necessity of running NullCPUPowerManagement.kext and have all the original management working even temperature monitor, if I'm right.

[mitch_de]

You should use 0x02048302, if you use 0x02038302 your IST tables won't load.

 

I now read out my SSDT from ACPI and get those (iwth no dsdt injextion, pure normal bios)

 

Name (CFGD, 0x02030302)

Name (\PDC0, 0x80000000)

Name (\PDC1, 0x80000000)

Name (\PDC2, 0x80000000)

Name (\PDC3, 0x80000000)

 

Should i use this or 0x02048302 ?

 

Also anyone an hint / comment to the adresses 0814 / 0815 ?

Register (SystemIO,

0x08, // Bit Width

0x00, // Bit Offset

0x0000000000000814, // Address i have 414 (and 415 insted of 815)

[mm67]

I now read out my SSDT from ACPI and get those (iwth no dsdt injextion, pure normal bios)

 

Name (CFGD, 0x02030302)

Name (\PDC0, 0x80000000)

Name (\PDC1, 0x80000000)

Name (\PDC2, 0x80000000)

Name (\PDC3, 0x80000000)

 

Should i use this or 0x02048302 ?

 

Also anyone an hint / comment to the adresses 0814 / 0815 ?

Register (SystemIO,

0x08, // Bit Width

0x00, // Bit Offset

0x0000000000000814, // Address i have 414 (and 415 insted of 815)

Have too see an IST table from your acpidump to tell, I don't know if your's are different. Any way it makes no

difference if you are not going to use factory P-states.

[relikwie]

<..>

 

Can you guys make a little explanation and summarize what are you doing.

 

<..>

 

I second this. Have tried to append my ssdt tables yesterday and it failed compiling the dsdt, so I left it (didn't have had the time but plan to sit for it and try to actually grasp what you magicians do). A summary for the noobians on the first page would be superb...

Also have the impression that you guys are hitting this dsdt everywhere, which makes it really hard to follow for me.

 

Anyway, I won't ask you to verify/fix my dsdt as I want to understand it myself, but please guys shed some photons on us at the first page.

 

Appreciate the work people do here, and perplexed by MC's help (not having a GB board and willing to help).

[Master Chief]

Exactly, Chief, that did the job! Defined PDCs 0-3 as external variables, and done!

 

Thanks a million, again!

Phew... finally

 

Guys, I´m trying to follow your thoughts and have been reading this thread but now I'm sorta lost! It´s an amazing work, it should be compiled and categorized but sections (USB, P-States, sound, NIC, etc.)

That would be nice. Maybe later?

 

Can you guys make a little explanation and summarize what are you doing.

It is probably easier to say what we're not trying to do, and that is hack Apple's security measures because then I'm out of here – this due to the legal implication (bye bye job).

 

I, as far as I can tell, think you are managing to get rid the necessity of running NullCPUPowerManagement.kext and have all the original management working even temperature monitor, if I'm right.

I want a hack that "just works" like a real Mac. One with fewer hacks and workarounds, this by patching the DSDT. And for me personally that would be a MacPro3,1.

 

...

Appreciate the work people do here, and perplexed by MC's help (not having a GB board and willing to help).

Ja, ik soms ook van mezelf! Hey I can do Dutch (easy) and many other languages... thanks to Google

[keeza]

Right. Try this one (see attachments).

 

Note: You still need to include the latest patches.

 

MC,

 

Thanks for that, compiled perfectly! And optimisations nice too. Very much appreciated.

 

Everyone,

This dsdt from MC contains some optimisations of code which IMO makes it neater and a bit shorter.

If you use it you will need to change the P-state bit located at the top as its stuck on 8x multiplier, max voltage and temps around 48 degrees.

 

I'm currently investigating how to re-incorporate my boards hard coded P-states without adding a _PSS scope to my dsdt.

 

mm67:

Where are you up to with that?

I would like to investigate the above option as I agree with your earlier comments that if you decide to overclock the p-states are re-calculated automatically as opposed to having to re-enter _PSS data. (the Q9550 is excellent for overclocking apparently, can get 3.4Ghz easily)

I presume with your method you have to use dropdsdt=yes in boot.com.plist?

 

have a great day/night

[asapreta]

Phew... finally

 

That would be nice. Maybe later?

 

It is probably easier to say what we're not trying to do, and that is hack Apple's security measures because then I'm out of here – this due to the legal implication (bye bye job).

 

I want a hack that "just works" like a real Mac. One with fewer hacks and workarounds, this by patching the DSDT. And for me personally that would be a MacPro3,1.

 

 

Ja, ik soms ook van mezelf! Hey I can do Dutch (easy) and many other languages... thanks to Google

 

Please, take your time.

And thanks for answering.

Meanwhile I'll try to catch what you are doing.

As I recently got an GA-EP45-UD3R, just want the same as you, a "perfect" hack!

 

Best Regards.

[xjasx]

Here's mine for GA-EP45-UD3P with all the recommended changes/optimizations (I think)... finally getting lower temps through powermanagement, sleep remains broken unless the setting in energy saver is on... maybe I just made a mistake somewhere and missed something stupid.... recommendations welcome...

dsdt.dsl.zip

[asapreta]

I think it would be interesting that when editing and achieving good results, to post the differences between the "original" DSDT and the modified one. And you all, what do you think?

[yeehaa]

I think it would be interesting that when editing and achieving good results, to post the differences between the "original" DSDT and the modified one. And you all, what do you think?

 

you may wanna try and read the P5k Pro and DSDT _cst threads where it all began

[mm67]

mm67:

Where are you up to with that?

I would like to investigate the above option as I agree with your earlier comments that if you decide to overclock the p-states are re-calculated automatically as opposed to having to re-enter _PSS data. (the Q9550 is excellent for overclocking apparently, can get 3.4Ghz easily)

 

Yes, that works nicely, only problem is that hardcoded PSS table seems to read the max multiplier from CPU. So you can't use for example 8 * 430 because you really end up with 8.5 * 430. 8.5 * 400 or 8.5 * 420 work nicely.

 

I presume with your method you have to use dropdsdt=yes in boot.com.plist?

 

DropSSDT option doesn't matter, I can use yes or no. Only thing important is that you have EIST option enabled in bios, C-states can be turned off or on, makes no difference. Could you post your original SSDT tables, maybe there is some small difference between UD3 and UD3P models.

 

/edit

C-states option makes a lot of difference if you use MC's method of loading Pm table since the tables base address changes on my board if C-states are disabled.

[asapreta]

you may wanna try and read the P5k Pro and DSDT _cst threads where it all began

 

Thanks for the tip, I'll take a look!

[keeza]

Could you post your original SSDT tables, maybe there is some small difference between UD3 and UD3P model

 

I've attached two versions, one based on my previous working P & C States, the other presently doesnt work (no stepping of voltage, multiplier or Mhz) but is a much shorter SSDT version and is the one I would like to get working if poss. I probably need to add _PSS data to the non working version though.

 

Also attached my original Linux SSDT's

SSDT_Tables_UD3P.zip

[Master Chief]

/edit

C-states option makes a lot of difference if you use MC's method of loading Pm table since the tables base address changes on my board if C-states are disabled.

Then we have to make it dynamic... if I only knew where this address is stored. It might be in RSDT/XSDT. Have you checked these for this address change? I mean it can't just change and go up in smoke. ACPI has to know this.

[mm67]

I've attached two versions, one based on my previous working P & C States, the other presently doesnt work (no stepping of voltage, multiplier or Mhz) but is a much shorter SSDT version and is the one I would like to get working if poss. I probably need to add _PSS data to the non working version though.

 

Also attached my original Linux SSDT's

 

That CFGD value should be okay, your SSDT tables are almost identical to mine.

But anyway, I'll show you how to calculate that value by yourself. Let's look

at your IST table and PSS method, looks like this:

        Method (_PSS, 0, NotSerialized)
       {
           If (LEqual (And (CFGD, 0x00060000), 0x00020000))
           {
               Return (SPSS)
           }

           If (LEqual (And (CFGD, 0x00060000), 0x00040000))
           {
               Return (NPSS)
           }

           If (LOr (And (CFGD, 0x4000), And (CFGD, 0x00010000)))
           {
               Return (NPSS)
           }

           Return (SPSS)
       }

 

That first comparison loads SPSS table if bit 17 is set and bit 18 is off, default value of 0x040383F2

has that so SPSS table is loaded, and we don't want that since it has unusable values.

 

If that first comparison failed then next one checks if bit 18 is set and bit 17 is off, 0x040483F2 has that so NPSS is loaded. 0x040583F2 would also do the same.

 

If the second comparison also failed then the last comparison checks for bits 14 and 16, if one or both are set then NPSS table is loaded. So for example 0x040183F2 would be a good value since it has bit 16 set and 0x0400C3F2 for example would have bit 14 set.

 

Then, if even this last comparison failed SPSS is loaded.

 

So there are many choices for CFGD value, you just have to check all places where that value is used so you don't use a value that disables something else.

[mm67]

Then we have to make it dynamic... if I only knew where this address is stored. It might be in RSDT/XSDT. Have you checked these for this address change? I mean it can't just change and go up in smoke. ACPI has to know this.

 

RSDT with C-states off :

 

[024h 0036  4]       ACPI Table Address   0 : DFEE20C0
[028h 0040  4]       ACPI Table Address   1 : DFEE6F80
[02Ch 0044  4]       ACPI Table Address   2 : DFEE7000
[030h 0048  4]       ACPI Table Address   3 : DFEE7040
[034h 0052  4]       ACPI Table Address   4 : DFEE7560
[038h 0056  4]       ACPI Table Address   5 : DFEE6E80
[03Ch 0060  4]       ACPI Table Address   6 : DFEEE6E0

 

RSDT with C-states on:

[024h 0036  4]       ACPI Table Address   0 : DFEE20C0
[028h 0040  4]       ACPI Table Address   1 : DFEE6F80
[02Ch 0044  4]       ACPI Table Address   2 : DFEE7000
[030h 0048  4]       ACPI Table Address   3 : DFEE7040
[034h 0052  4]       ACPI Table Address   4 : DFEE7560
[038h 0056  4]       ACPI Table Address   5 : DFEE6E80
[03Ch 0060  4]       ACPI Table Address   6 : DFEEE6E0
[040h 0064  4]       ACPI Table Address   7 : DFEEE870
[044h 0068  4]       ACPI Table Address   8 : DFEEEA00
[048h 0072  4]       ACPI Table Address   9 : DFEEEB90
[04Ch 0076  4]       ACPI Table Address  10 : DFEEED20

 

On both tables Pm table address is the bottom one.

[Master Chief]

RSDT with C-states off :

...[03Ch 0060  4]	   ACPI Table Address   6 : DFEEE6E0

RSDT with C-states on:

...[04Ch 0076  4]	   ACPI Table Address  10 : DFEEED20

On both tables Pm table address is the bottom one.

Ok. Great work. Thanks! And my (educated) guess would be to use something like this:

LoadTable("SSDT", "PmRef", "CpuPm")

instead of Load(). I am however currently unable to verify this myself. Any takers?

[yeehaa]

Ok. Great work. Thanks! And my (educated) guess would be to use something like this:

LoadTable("SSDT", "PmRef", "CpuPm")

instead of Load(). I am however currently unable to verify this myself. Any takers?

 

Off topic: hey.. there is a new version of GRUB called GRUB2 which has the feature to load any acpi table (not just DSDT) externally. i remember, MC asking for such a bootloader sometime earlier.