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DSDT fixes for Gigabyte boards

iSoprano

By iSoprano,
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sk1nhead
sk1nhead
Posted
Posted
Do you now have method PTS setup like mine, if you do then could you try some shutdowns without OHR.kext.
That's good, I have now been using shutdown without OHR for almost two weeks, haven't seen it fail even once.
unfortunately OSXRestart doesn't work on my board 100%, sometimes it shutdown- sometimes it wont, so Ev0reboot for now.

 

woohoo! mm67 you're a genius, you nailed 2 problems (aluminum kb and shutdown) of mine in one stone! Goodbye ev0 and OHR and finally for the first time i am using OSXRestart by MC..

 

Shutdown is 4 out of 4 already. Thanks Thanks. Excellent job. :)

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kdawg
kdawg
Posted
Posted
Sure, here you go, totally vanilla

DSDT_r1_GBT_GBTUACPI_1000_MSFT_100000C.dsl.zip

 

Just so you know I'm getting temperatures 3-5 degrees cooler with this Scope (_PR):

    Scope (_PR)
   {
	Processor (CPU0, 0x00, 0x00000410, 0x06)
	{
		Method (_PSS, 0, NotSerialized)
		{
			Return (Package(0x03)
			{
				Package (0x06) { 0x00, 0x00, 10, 10, 0x00000822, 0 },
				Package (0x06) { 0x00, 0x00, 10, 10, 0x0000071E, 1 },
				Package (0x06) { 0x00, 0x00, 10, 10, 0x0000061A, 2 }
			})
		}

           Method (_PSD, 0, NotSerialized)
           {
               Return (Package (0x05) {0x05, 0x00, 0x00, 0xFC, 0x04})
           }

		Method (_CST, 0, NotSerialized)
		{
			Return (Package (0x02)
			{
				0x01, 
				Package (0x04) {ResourceTemplate () {Register (FFixedHW, 0x01, 0x02, 0x000, 0x01, )}, 0x01, 0x05A, 0x0384} 
			})
		}
	}

	Processor (CPU1, 0x01, 0x00000410, 0x06)
	{
		Alias (\_PR.CPU0._PSS, _PSS)
                       Alias (\_PR.CPU0._PSD, _PSD)
		Method (_CST, 0, NotSerialized)
		{
			Return (Package (0x04)
			{
				0x03, 
				Package (0x04) {ResourceTemplate () {Register (FFixedHW, 0x01, 0x02, 0x000, ,)}, 0x01, 0x00, 0x0384}, 
				Package (0x04) {ResourceTemplate () {Register (SystemIO, 0x08, 0x00, 0x414, ,)}, 0x02, 0x01, 0x01F4}, 
				Package (0x04) {ResourceTemplate () {Register (SystemIO, 0x08, 0x00, 0x415, ,)}, 0x03, 0x55, 0xFA} 
			})
		}
	}

	Processor (CPU2, 0x02, 0x00000410, 0x06)
	{
		Alias (\_PR.CPU0._PSS, _PSS)
                       Alias (\_PR.CPU0._PSD, _PSD)
		Alias (\_PR.CPU1._CST, _CST)
	}

	Processor (CPU3, 0x03, 0x00000410, 0x06)
	{
		Alias (\_PR.CPU0._PSS, _PSS)
                       Alias (\_PR.CPU0._PSD, _PSD)
		Alias (\_PR.CPU1._CST, _CST)
	}
}

 

Using your interpretation my temps were higher.

    Scope (_PR)
   {
       Processor (CPU0, 0x00, 0x00000410, 0x06) 
       {
		Method (_PSS, 0, NotSerialized)
		{
			Return (Package (0x03)
			{
				Package (0x06) { 0x00, 0x00, 10, 10, 0x00000822, 0 },
				Package (0x06) { 0x00, 0x00, 10, 10, 0x0000071E, 1 },
				Package (0x06) { 0x00, 0x00, 10, 10, 0x0000061A, 2 }
			})
		}
		Method (_CST, 0, NotSerialized)
		{
			Return (Package (0x4)
			{
				0x03, 
				Package (0x04) {ResourceTemplate () {Register (FFixedHW, 0x01, 0x02, 0x000, ,)}, 0x01, 0x00, 0x0384}, 
				Package (0x04) {ResourceTemplate () {Register (SystemIO, 0x08, 0x00, 0x414, ,)}, 0x02, 0x01, 0x01F4}, 
				Package (0x04) {ResourceTemplate () {Register (SystemIO, 0x08, 0x00, 0x415, ,)}, 0x03, 0x55, 0xFA} 
			})
		}
       }
       Processor (CPU1, 0x01, 0x00000410, 0x06) {}
       Processor (CPU2, 0x02, 0x00000410, 0x06) {}
       Processor (CPU3, 0x03, 0x00000410, 0x06) {}
   }

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mm67
mm67
Posted
Posted
Just so you know I'm getting temperatures 3-5 degrees cooler with this Scope (_PR):

 

Yes, I have seen that my self. I'm just not sure if it is a good a idea to use latency value 0 in CST

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Master Chief
Master Chief
Posted
Posted
Just so you know I'm getting temperatures 3-5 degrees cooler with this Scope (_PR) ...

Now move the methods: _PSS, _PSD and _CST out of CPU1 into the _PR scope and use this:

Processor (CPUn, 0x02, 0x00000410, 0x06)
{
Alias (PSS, _PSS)
Alias (PSD, _PSD)
Alias (CST, _CST)
}

For CPU2, CPU3 and CPU4. See how many bytes you get off of dsdt.aml And not only that, because this way it is also faster ;)

 

woohoo! mm67 you're a genius, you nailed 2 problems (aluminum kb and shutdown) of mine in one stone! Goodbye ev0 and OHR and finally for the first time i am using OSXRestart by MC..

 

Shutdown is 4 out of 4 already. Thanks Thanks. Excellent job. :)

I second that!

 

I knew that he was working on getting shutdown fixed, and not only that but he also nailed the Alu Apple keyboard wake. Which is fantastic news for GB users and the like. Again, great job mm67!!!

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kdawg
kdawg
Posted
Posted
Now move the methods: _PSS, _PSD and _CST out of CPU1 into the _PR scope and use this:

Processor (CPUn, 0x02, 0x00000410, 0x06)
{
Alias (PSS, _PSS)
Alias (PSD, _PSD)
Alias (CST, _CST)
}

For CPU2, CPU3 and CPU4. See how many bytes you get off of dsdt.aml And not only that, because this way it is also faster ;)

Worked like a charm. My temps are even a couple degrees lower now. I also took out the zero latency value in my CST.

 

 

I second that!

 

I knew that he was working on getting shutdown fixed, and not only that but he also nailed the Alu Apple keyboard wake. Which is fantastic news for GB users and the like. Again, great job mm67!!!

Yeah I agree. This community is lucky to have a few pioneers (Master Chief and mm67 to name just two) willing to take the time AND share their work.

 

Thanks!

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mm67
mm67
Posted
Posted
Worked like a charm. My temps are even a couple degrees lower now. I also took out the zero latency value in my CST.

 

 

Yeah I agree. This community is lucky to have a few pioneers (Master Chief and mm67 to name just two) willing to take the time AND share their work.

 

Thanks!

 

Tried this style to use a separate CST table for cpu0 and different for other cores. Didn't take long to remember why I got rid of it earlier. When idling everything seems fine and temps are real low. Then I start doing something that causes a light, let's say for example 10 % cpu load, and temps jump up at least 10 degrees. This always happens when I start using for example MPlayer or XBMC. If I use one common CST table for all cores idling temps are a bit higher but temps on a light load are lower so I prefer the 1 CST table solution.

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kdawg
kdawg
Posted
Posted
Tried this style to use a separate CST table for cpu0 and different for other cores. Didn't take long to remember why I got rid of it earlier. When idling everything seems fine and temps are real low. Then I start doing something that causes a light, let's say for example 10 % cpu load, and temps jump up at least 10 degrees. This always happens when I start using for example MPlayer or XBMC. If I use one common CST table for all cores idling temps are a bit higher but temps on a light load are lower so I prefer the 1 CST table solution.

 

Yeah I think I'm going to stick with this. Its seems to run the coolest idle and under load. Thanks guys.

    Scope (_PR)
   {
       Name (PSS, Package (0x03)
       {
           Package (0x06) { Zero, Zero, 10, 10, 0x00000822, Zero },
           Package (0x06) { Zero, Zero, 10, 10, 0x0000071E, One },
           Package (0x06) { Zero, Zero, 10, 10, 0x0000061A, 2 }
       })
       Name (PSD, Package (0x05)
       {
           0x05,Zero,Zero,0xFC,0x04
       })
       Name (CST, Package (0x04)
       {
           0x03,
           Package (0x04){ResourceTemplate (){Register (FFixedHW,0x01,0x02,0x0000000000000000,0x00,)},One,One,0x03E8}, 
           Package (0x04){ResourceTemplate (){Register (SystemIO,0x08,0x00,0x0000000000000414,    ,)},0x02,One,0x01F4}, 
           Package (0x04){ResourceTemplate (){Register (SystemIO,0x08,0x00,0x0000000000000415,    ,)},0x03,0x55,0xFA}
       })
       Processor (CPU0, 0x00, 0x00000410, 0x06)
       {
           Alias (PSS, _PSS)
           Alias (PSD, _PSD)
           Alias (CST, _CST)
       }

       Processor (CPU1, 0x01, 0x00000410, 0x06)
       {
           Alias (PSS, _PSS)
           Alias (PSD, _PSD)
           Alias (CST, _CST)
       }

       Processor (CPU2, 0x02, 0x00000410, 0x06)
       {
           Alias (PSS, _PSS)
           Alias (PSD, _PSD)
           Alias (CST, _CST)
       }

       Processor (CPU3, 0x03, 0x00000410, 0x06)
       {
           Alias (PSS, _PSS)
           Alias (PSD, _PSD)
           Alias (CST, _CST)
       }
   }

 

EDIT

Couple other questions. Why didn't you change the device ID of LPCB to get AppleLPC.kext to load?

				Method (_DSM, 4, NotSerialized)
			{
				Store (Package (0x02)
					{
						"device-id", Buffer (0x04){0x18, 0x3A, 0x00, 0x00}
					}, Local0)
				DTGP (Arg0, Arg1, Arg2, Arg3, RefOf (Local0))
				Return (Local0)
			}

 

And do you think EXPL is necassary? If so why don't they put it with the rest of the devices in Device (PCI0)?

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jamonda
jamonda
Posted
Posted
This is what I am using at the moment:

dsdt.dsl.zip

 

Was already under 900 lines without these EHCI mods ^_^

 

 

Amazing DSDT.dsl, for sure. It would be perfect if you could comment each block, name, method an so on, so that people like me could learn faster what they do and why they are necessary and, of course, try to help the community.

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mm67
mm67
Posted
Posted
Yeah I think I'm going to stick with this. Its seems to run the coolest idle and under load. Thanks guys.

    Scope (_PR)
   {
       Name (PSS, Package (0x03)
       {
           Package (0x06) { Zero, Zero, 10, 10, 0x00000822, Zero },
           Package (0x06) { Zero, Zero, 10, 10, 0x0000071E, One },
           Package (0x06) { Zero, Zero, 10, 10, 0x0000061A, 2 }
       })
       Name (PSD, Package (0x05)
       {
           0x05,Zero,Zero,0xFC,0x04
       })
       Name (CST, Package (0x04)
       {
           0x03,
           Package (0x04){ResourceTemplate (){Register (FFixedHW,0x01,0x02,0x0000000000000000,0x00,)},One,One,0x03E8}, 
           Package (0x04){ResourceTemplate (){Register (SystemIO,0x08,0x00,0x0000000000000414,    ,)},0x02,One,0x01F4}, 
           Package (0x04){ResourceTemplate (){Register (SystemIO,0x08,0x00,0x0000000000000415,    ,)},0x03,0x55,0xFA}
       })
       Processor (CPU0, 0x00, 0x00000410, 0x06)
       {
           Alias (PSS, _PSS)
           Alias (PSD, _PSD)
           Alias (CST, _CST)
       }

       Processor (CPU1, 0x01, 0x00000410, 0x06)
       {
           Alias (PSS, _PSS)
           Alias (PSD, _PSD)
           Alias (CST, _CST)
       }

       Processor (CPU2, 0x02, 0x00000410, 0x06)
       {
           Alias (PSS, _PSS)
           Alias (PSD, _PSD)
           Alias (CST, _CST)
       }

       Processor (CPU3, 0x03, 0x00000410, 0x06)
       {
           Alias (PSS, _PSS)
           Alias (PSD, _PSD)
           Alias (CST, _CST)
       }
   }

 

Yes, exactly the same setup that I am using now. This runs cool also on load.

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kdawg
kdawg
Posted
Posted
Yes, exactly the same setup that I am using now. This runs cool also on load.

 

Couple other questions. Why didn't you change the device ID of LPCB to get AppleLPC.kext to load?

				Method (_DSM, 4, NotSerialized)
			{
				Store (Package (0x02)
					{
						"device-id", Buffer (0x04){0x18, 0x3A, 0x00, 0x00}
					}, Local0)
				DTGP (Arg0, Arg1, Arg2, Arg3, RefOf (Local0))
				Return (Local0)
			}

 

And do you think EXPL is necassary? If so why don't they put it with the rest of the devices in Device (PCI0)?

Sorry you were too quick to answer I had amended my last post.
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mm67
mm67
Posted
Posted
Couple other questions. Why didn't you change the device ID of LPCB to get AppleLPC.kext to load?

				Method (_DSM, 4, NotSerialized)
			{
				Store (Package (0x02)
					{
						"device-id", Buffer (0x04){0x18, 0x3A, 0x00, 0x00}
					}, Local0)
				DTGP (Arg0, Arg1, Arg2, Arg3, RefOf (Local0))
				Return (Local0)
			}

 

I don't need to do that since my board has ICH10, not ICH10R as yours. ICH10 has corrrect device-id as default.

 

And do you think EXPL is necassary? If so why don't they put it with the rest of the devices in Device (PCI0)?

 

I left it there so I would remember to figure out what it is and if it is necessary ^_^

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kdawg
kdawg
Posted
Posted
I don't need to do that since my board has ICH10, not ICH10R as yours. ICH10 has corrrect device-id as default.
Ah ha!

 

I left it there so I would remember to figure out what it is and if it is necessary ;)
Would you agree it'd be safe to move? I don't understand the logic of keeping it isolated from the rest of the devices.

 

Also, I think I had mapped SYSR to MacPro3,1's LDRC device.

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Master Chief
Master Chief
Posted
Posted
Tried this style to use a separate CST table for cpu0 and different for other cores. Didn't take long to remember why I got rid of it earlier. When idling everything seems fine and temps are real low. Then I start doing something that causes a light, let's say for example 10 % cpu load, and temps jump up at least 10 degrees. This always happens when I start using for example MPlayer or XBMC. If I use one common CST table for all cores idling temps are a bit higher but temps on a light load are lower so I prefer the 1 CST table solution.

Interesting. Now read this: "The platform must expose a _CST object for either all or none of its processors.".

 

And this: "_CST eliminates the ACPI 1.0 restriction that all processors must have C State parity. With _CST, each processor can have its own characteristics independent of other processors. For example, processor 0 can support C1, C2 and C3, while processor 1 supports only C1.".

 

And the Intel CPU specification, saying that the first core may not enter any C state higher than 1.

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mm67
mm67
Posted
Posted
Interesting. Now read this: "The platform must expose a _CST object for either all or none of its processors.".

 

And this: "_CST eliminates the ACPI 1.0 restriction that all processors must have C State parity. With _CST, each processor can have its own characteristics independent of other processors. For example, processor 0 can support C1, C2 and C3, while processor 1 supports only C1.".

 

And the Intel CPU specification, saying that the first core may not enter any C state higher than 1.

 

I'm not sure if this refers to only real multi cpu systems or is this information valid also with multicore cpu's. Is this even possible since I seem to recall that only Nehalem's have all cores working independently. On my quad core it looks more like 2 + 2 cores are changing states together.

 

 

 

 

Ah ha!

 

Would you agree it'd be safe to move? I don't understand the logic of keeping it isolated from the rest of the devices.

 

Also, I think I had mapped SYSR to MacPro3,1's LDRC device.

 

Ok, EXPL seems to be pointing to something like this:

http://tldp.org/HOWTO/Plug-and-Play-HOWTO-3.html

 

So in my opinion it should be safe to remove, I will do that now ;)

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Master Chief
Master Chief
Posted
Posted
I'm not sure if this refers to only real multi cpu systems or is this information valid also with multicore cpu's. Is this even possible since I seem to recall that only Nehalem's have all cores working independently. On my quad core it looks more like 2 + 2 cores are changing states together...

I agree that the ACPI specification is a bit blurry sometimes, to put it mildly. And the only reference to a multiprocessing environment in the specification is this one:

 

"In a multiprocessing environment, all CPUs must support the same number of performance states and each processor performance state must have identical performance and power-consumption parameters. Performance objects must be present under each processor object in the system for OSPM to utilize this feature.

Processor performance control objects include the ‘_PCT’ package, ‘_PSS’ package, and the ‘_PPC’ method as detailed below.".

 

Note the bold part, which is why I stick with the aliases ;)

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mm67
mm67
Posted
Posted
I agree that the ACPI specification is a bit blurry sometimes, to put it mildly. And the only reference to a multiprocessing environment in the specification is this one:

 

"In a multiprocessing environment, all CPUs must support the same number of performance states and each processor performance state must have identical performance and power-consumption parameters. Performance objects must be present under each processor object in the system for OSPM to utilize this feature.

Processor performance control objects include the ‘_PCT’ package, ‘_PSS’ package, and the ‘_PPC’ method as detailed below.".

 

Note the bold part, which is why I stick with the aliases :)

 

Yes, there sure is no harm in defining all cores. I just wonder why OS X even accepts a setup that is not fully defined for all cores, if I try to use such a dsdt on Linux it gets refused.

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kdawg
kdawg
Posted
Posted
Ok, EXPL seems to be pointing to something like this:

http://tldp.org/HOWTO/Plug-and-Play-HOWTO-3.html

 

So in my opinion it should be safe to remove, I will do that now :angel:

 

IGBE seems to be useless as well. Doesn't even show up in ioreg.

 

Other than that, the only other one that seems to be useless is PMIO. Which I believe is "Portwell Modules I/O" for handling PCIe or PCI expansion capabilities.

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mm67
mm67
Posted
Posted
IGBE seems to be useless as well. Doesn't even show up in ioreg.

 

Other than that, the only other one that seems to be useless is PMIO. Which I believe is "Portwell Modules I/O" for handling PCIe or PCI expansion capabilities.

 

That name IGBE somehow sounds like Gigabit Ethernet and on Windows side it is shown as a network device. Have to look into that PMIO, address range seems to refer to PMBASE ports. Test what happens if you take those out.

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archie68
archie68
Posted
Posted

Help for a an uber-n00b! I have:

 

Core2Quad

Nvidia 9800 video card

4 GB RAM

ep45-ud3l

 

I have everything working except sound and some speed step issues (CPU temps are high 50's C at idle). The bootloader seems to be working fine now, although it gave me issues in the beginning (forced a reboot unless the original OSX thumbdrive was plugged in)

 

I've downloaded the .dsl and .aml files from the first post of this thread and downloaded DSDTPatcherGUI_1.0 but I have NO CLUE on how to apply these patches, and most guides seem to assume a certain amount of previous experience with DSDT patcher. Is there a very basic beginner's guide for this task? I'm worried my Core2Quad is going to overheat on me!

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kdawg
kdawg
Posted
Posted
That name IGBE somehow sounds like Gigabit Ethernet and on Windows side it is shown as a network device. Have to look into that PMIO, address range seems to refer to PMBASE ports. Test what happens if you take those out.
I've taken both out and see no impact.
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mm67
mm67
Posted
Posted
here's mine for ga-ep45-ud3p with all fixes...

shutdown works... sleep works without setting in energy prefs

 

more can probably be cut...

 

This CST table doesn't look right:

 

            Method (_CST, 0, NotSerialized)
           {
               Return (Package (0x04)
               {
                   0x03, 
                   Package (0x04)
                   {
                       ResourceTemplate ()
                       {
                           Register (FFixedHW, 
                               0x01,               // Bit Width
                               0x02,               // Bit Offset
                               0x0000000000000000, // Address
                               0x01,               // Access Size
                               )
                       }, 

                       One, 
                       One, 
                       0x03E8
                   }, 

                   Package (0x04)
                   {
                       ResourceTemplate ()
                       {
                           Register (SystemIO, 
                               0x08,               // Bit Width
                               0x00,               // Bit Offset
                               0x0000000000000814, // Address
                               ,)
                       }, 

                       0x02, 
                       One, 
                       0x01F4
                   }, 

                   Package (0x04)
                   {
                       ResourceTemplate ()
                       {
                           Register (SystemIO, 
                               0x08,               // Bit Width
                               0x00,               // Bit Offset
                               0x0000000000000815, // Address
                               ,)
                       }, 

                       0x03, 
                       0x11, 
                       0xFA
                   }
               })
           }
       }

 

Your PMBASE address is 0x400 so why are you using 0x814 and 0x815 for C2 and C3. But then again again your CPU is Q6600 which doesn't have C2 and C3 states anyway so how about doing some cutting.

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