DSDT fixes for Gigabyte boards

[mitch_de]

"Speedstep works fine when the PCIB section is like this:"

 

Device (PCIB) // Renamed from HUB0
{
Name (_ADR, 0x001E0000)
Name (_PRT, Package (0x0C)
{
Package (0x04) { 0xFFFF, Zero, Zero, 0x14 }, 
.....
Package (0x04) { 0x0001FFFF, Zero, Zero, 0x13 }, 
.....
Package (0x04) { 0x000[b]7FFFF[/b], Zero, Zero, [b]0x17[/b] },
Package (0x04) { 0x0007FFFF, One, Zero, 0x17 }, 
Package (0x04) { 0x0007FFFF, 0x02, Zero, 0x17 }, 
Package (0x04) { 0x0007FFFF, 0x03, Zero, 0x17 }
})

 

Hmmm, i have insted 7FFFF there 2FFFF, and 0x12, 0x10, 0x14, 0x13 insted of 0x17 ??!!

 

I dont know from whom i got those dsdt sniplet nor i know what that does

 

Anyone can help understand that 7FFFF vs 2FFFF (mine) differences in Device (PCIB) // Renamed from HUB0 ?

Is that Chipset/mainboard specific like the 410/414/415 vs 810/814/815 in PSS/CST or an general thing ?

Thanks

[mm67]

Anyone can help understand that 7FFFF vs 2FFFF (mine) differences in Device (PCIB) // Renamed from HUB0 ?

Is that Chipset/mainboard specific like the 410/414/415 vs 810/814/815 in PSS/CST or an general thing ?

Thanks

 

Interrupt routing is very much motherboard spesific, dont try to use someone else's routing tables.

[SMF]

MasterChief,

 

First - many thanks for your work with DSDT. Truly impressive and I'm trying to learn and benefit from it.

 

I'm starting with some simple mods as I gain knowledge and I have a some questions re your HPET section - you have near the start of version 3.2 or your DSDT

                    Name (CRS, ResourceTemplate ()

 

Why not _CRS?

 

And in your Memory32Fixed you have -

 

                        Memory32Fixed (ReadOnly,
                           0xFED00000,         // Address Base
                           0x00000400,         // Address Length
                           _Y09)

 

And I can't understand the _Y09. I see it in the MacPro3,1 DSDT but reading the ACPI spec doesn't help. I see it referred to in a few lines later in the Method (_CRS code but can't figure it out.

 

I appreciate any insight you can provide.

 

Regards,

SMF

[mitch_de]

Interrupt routing is very much motherboard spesific, dont try to use someone else's routing tables.

Thanks - nice to learn+learn here

 

my orig. part of that HUB0 (PCB) fits with my modded dsdt parts, so all ok here.

[irrational John]

I'm starting with some simple mods as I gain knowledge and I have a some questions re your HPET section - you have near the start

					Name (CRS, ResourceTemplate ()

 

Why not _CRS?

It would help others ... perhaps even help MC ... if you include some form of link back to the post that has the DSL code you're referring to so that it can be seen in context.

 

As for omitting the leading "_", start by looking at section 5.3 ACPI Namespace, the ACPI Specification (the link is to revision 4.0). There it states simply that

"

Names beginning with ‘_’ are reserved by this specification. Definition Blocks can only use names beginning with ‘_’ as defined by this specification.

"

So all the leading underscore means is that the symbol is reserved for a use within the spec. If you leave it off then its just a name and not reserved.

 

So my question is, do you think the reserved name should be used in this context? Why? Or why not?

 

No?

 

-irrational john

[pet1]

Hello everyone.. I am new to the dsdt scene. I have very little knowledge in editing dsdt.aml. I have made some changes to mine with some success. But I get confused when trying to apply the usb hacks. I get compile errors when I'm done. So I must be doing something wrong. I have attached my .dsl hoping one of you kind souls will look at it and help. thanks again.

[SMF]

irrational john,

 

Sorry about that - I was referring to version 3.2 of MasterChief's own DSDT. I wasn't implying that I saw something wrong with what he did but noticed that in this area of his DSDT (and I think in only one other area) he uses Method (CRS .. rather than Method (_CRS and I wanted to try and understand why.

 

Regards,

SMF

[Master Chief]

I'll add three code snippets. Starting with my DSDT V3.2 HPET section:

                Device (HPET)
               {
                   Name (_HID, EisaId ("PNP0103"))
                   Name (CRS, ResourceTemplate ()
                   {
                       IRQNoFlags ()
                           {0}
                       IRQNoFlags ()
                           {8}
                       Memory32Fixed (ReadOnly,
                           0xFED00000,         // Address Base
                           0x00000400,         // Address Length
                           _Y09)
                   })
                   Name (_STA, 0x0F)

                   OperationRegion (^LPCR, SystemMemory, [color="#FF0000"]0xFED1F404[/color], 0x04)
                   Field (LPCR, AnyAcc, NoLock, Preserve)
                   {
                       HPTS,   2, 
                           ,   5, 
                       HPTE,   1, 
                               Offset (0x04)
                   }

                   Method (_CRS, 0, NotSerialized)
                   {
                       CreateDWordField (CRS, \_SB.PCI0.LPCB.HPET._Y09._BAS, HPT)
                       Multiply (HPTS, 0x1000, Local0)
                       Add (Local0, 0xFED00000, HPT)
                       Return (CRS)
                   }
               }

And this is what we're going to use for this session:

                Device (HPET)
               {
                   Name (_HID, EisaId ("PNP0103"))
                   Name (CRS, ResourceTemplate ()
                   {
                       IRQNoFlags ()
                           {0}
                       IRQNoFlags ()
                           {8}
                       Memory32Fixed (ReadOnly,
                           0x00000000,         // Address Base
                           0x00000000,         // Address Length
                           _MC)
                   })
                   Name (_STA, 0x0F)

                   OperationRegion (^LPCR, SystemMemory, [color="#FF0000"]0xFED1F404[/color], 0x04)
                   Field (LPCR, AnyAcc, NoLock, Preserve)
                   {
                       HPTS,   2, 
                           ,   5, 
                       HPTE,   1, 
                               Offset (0x04)
                   }

                   Method (_CRS, 0, NotSerialized)
                   {
                       CreateDWordField (CRS, \_SB.PCI0.LPCB.HPET._MC._BAS, HPTB)
                       Multiply (HPTS, 0x1000, Local0)
                       Add (Local0, 0xFED00000, HPTB)
                       CreateDWordField (CRS, \_SB.PCI0.LPCB.HPET._MC._LEN, HPTL)
                       Store (0x00000400, HPTL)
                       Return (CRS)
                   }
               }

Showing a new name as reference (_MC instead of _Y09) and a zero based base address and length to demo how this works. Yes, you can rename stuff and even zero out the base address. And it doesn't matter because the code in _CRS will modify it for us!

 

Anyway. My vanilla P5K Pro DSDT uses CRS for the resource template, and so did I. No point in renaming stuff, other than maybe to show you that it can be done. And what the lines in _CRS do is to change the base address, this based on a BIOS value. We use HPTS but MacPro3,1 uses HPAS. It's just a name. And looking at the MacPro3,1 DSDT there is can be: 0, 1, 2 or 3. Giving us: 0xFED00000, 0xFED01000, 0xFED02000 and 0xFED03000

 

Mine here is 0 and thus Multiply (HPTS, 0x1000, Local0) stores 0 (Zero) in Local0. The next line Add (Local0, 0xFED00000, HPTB) adds the base address, which is my case is what I use for DSDT V3.3. Here's the stripped variant:

                Device (HPET)
               {
                   Name (_HID, EisaId ("PNP0103"))
                   Name (_CRS, ResourceTemplate ()
                   {
                       IRQNoFlags ()
                           {0}
                       IRQNoFlags ()
                           {8}
                       Memory32Fixed (ReadOnly,
                           0xFED00000,         // Address Base
                           0x00000400,         // Address Length
                           )
                   })
                   Name (_STA, 0x0F)
               }

I hope that this clears things up for people here. No mistake. No error. Thank you.

 

p.s. I think to gave said this before, but I'll add it here once more: Take a look at the value in red (in the long variants) which happen to point to the following code snippet in a real MacPro3,1 DSDT:

    OperationRegion (RCRB, SystemMemory, 0xFED1C000, 0x4000)
   Field (RCRB, DWordAcc, Lock, Preserve)
   {
               Offset (0x1000), 
               Offset (0x3000), 
[color="#008000"]                Offset (0x3404), 
       HPAS,   2, 
           ,   5, 
       HPAE,   1[/color], 
               Offset (0x3418), 
           ,   1, 
       PATD,   1, 
       SATD,   1, 
       SMBD,   1, 
       HDAD,   1, 
       A97D,   1, 
               Offset (0x341A), 
       RP1D,   1, 
       RP2D,   1, 
       RP3D,   1, 
       RP4D,   1, 
       RP5D,   1, 
       RP6D,   1
   }

I mean 0xFED1C000 + 0x3404 = 0xFED1F404 so... someone might be interested in it

[tonymacx86]

Hi everyone- I've managed to read through this thread and apply a few basic DSDT fixes (UHCI/EHCI, HDEF, CMOS reset) for my board, but my question is, do the Speedstep fixes mentioned here and on the speedstep thread apply to P55 based mobos?

 

I have tried the DSDT posted on pg 1 of this thread, and sleep works, but switched back to my own. I'd like to enable vanilla speedstepping and sleep, but I don't want to mess up my system with someone else's DSDT for a totally different mobo. Thanks in advance!

 

EDIT: I got the sleep done! Now for the speedstep...

[Johnny V]

Hello everyone!

 

Could someone point me in the direction on steps building DSDT for my below motherboard?

 

GIGABYTE GA-EX38-DS4 Motherboard

 

North Bridge Intel X38

South Bridge Intel ICH9R

Audio Chipset Realtek ALC889A

LAN Chipset Realtek 8111B

 

How many problems would occur if I used a DSDT from a different Gigabyte motherboard?

 

Thanks,

 

John

[mitch_de]

"How many problems would occur if I used a DSDT from a different Gigabyte motherboard?"

 

None if you use that as Drag&drop parts of like HPET, RTC, AZAL>HDEF into yours.

Those things are similar. AZAL>HDEF maybe not (different Realtech Audio Chip)

But a lot of dsdt heros changed so much to make it more mac like - which make it much harder to adapt it to other MB types!, that you cant use the whole thing on different MB type.

And even you get an 100% same MB dsdt, you may need to edit the PSS part (Pstates), which is CPU/Ghz/FSB depended.

I would make an "search call" for your MB in Post Install 10.5/10.6 forum part if you dont get it here within an week.

[kdawg]

Hi everyone- I've managed to read through this thread and apply a few basic DSDT fixes (UHCI/EHCI, HDEF, CMOS reset) for my board, but my question is, do the Speedstep fixes mentioned here and on the speedstep thread apply to P55 based mobos?

 

I have tried the DSDT posted on pg 1 of this thread, and sleep works, but switched back to my own. I'd like to enable vanilla speedstepping and sleep, but I don't want to mess up my system with someone else's DSDT for a totally different mobo. I attached my DSDT for reference. Thanks in advance!

 

 

Head over to the Vanilla SpeedStepping thread. I'm not actually sure anyone has tried with an i5 processor but I don't see why it wouldn't work.

 

BTW, From your blog I see you're using NVEnabler for your graphics card. You should try and add this via DSDT. Poke around the answer should be easy to find.

[SMF]

MasterChief,

 

Thanks for the reply - looking at what you did and the ACPI spec is making it clearer and is very helpful. Thanks for helping an old dog learn new tricks. I'll keep plugging away.

 

Regards,

SMF

[bonfilio]

A couple people pst'd me to post my DSDT.. here you go - includes .dsl and .aml

 

 

Gigabyte UD3P v1.6.. sleep, clock, USB, etc etc. All the specific GB fixes while remaining as generic as possible (no gfx, no audio, etc).

UD3P_DSDT.zip

[joe2108]

My current DSDT can load IntelAppleCPU..... sleep & wake work

 

EP45-UD3L Bios F8a

Intel C2D e7500 (2930)

GForce 9500GT

 

about P-State...

 

it's seems always work on lower P-state event load huge aplication (see using VoodooMonitor or CPUi)

 

 

 

how I can fix this ... Please Chek my current DSDT if you dont mind

 

 

thank's

dsdtep45ud3l_f8a.zip

[tonymacx86]

Thanks to everyone for their hard work in this thread and the speedstep thread. I've managed to do all of the edits to make sleep work on the GA-P55M-UD2. A few of us over in the P55 Buyers guide thread are starting to make some of the more advanced DSDT edits including enabling sleep and so forth.

 

http://www.insanelymac.com/forum/index.php...6155&st=760

 

So I just wanted to say thanks, and good luck to all!

[SMF]

MasterChief (and others),

 

My next question seeking understanding -

 

I have not yet be able to understand the meaning/importance of the "Alignment" parameter of the IO statement - for example my PIC (now IPIC) code is as follows -

 

                Device (IPIC) //Renamed from: PIC
               {
                   Name (_HID, EisaId ("PNP0000"))
                   Name (_CRS, ResourceTemplate ()
                   {
                       IO (Decode16,
                           0x0020,             // Range Minimum
                           0x0020,             // Range Maximum
                           0x01,               // Alignment
                           0x02,               // Length
                           )
                       IO (Decode16,
                           0x00A0,             // Range Minimum
                           0x00A0,             // Range Maximum
                           0x01,               // Alignment
                           0x02,               // Length
                           )
                       IRQNoFlags ()
                           {2}
                   })
               }

 

Looking at MasterChief's v3.2 DSDT the IPIC section is -

                Device (IPIC) // Renamed from: PIC
               {
                   Name (_HID, EisaId ("PNP0000"))
                   Name (_CRS, ResourceTemplate ()
                   {
                       IO (Decode16,
                           0x0020,             // Range Minimum
                           0x0020,             // Range Maximum
                           0x00,               // Alignment
                           0x02,               // Length
                           )
                       IO (Decode16,
                           0x00A0,             // Range Minimum
                           0x00A0,             // Range Maximum
                           0x00,               // Alignment
                           0x02,               // Length
                           )
                       IO (Decode16,           // Master Controller Edge/Level Triggered Register (ICH9R-316972.pdf / 13.4.10 / page 472)
                           0x04D0,             // Range Minimum
                           0x04D0,             // Range Maximum
                           0x00,               // Alignment
                           0x02,               // Length
                           )
                       IRQNoFlags ()
                           {2}
                   })
               }

 

This is only one example - there are several areas in my DSDT (Gigabyte P35-DQ6) that have an alignment value of "1". I'm interested as I'm trying to understand and correctly apply the changes that MasterChief is suggesting.

 

Regards,

SMF

[irrational John]

I have not yet be able to understand the meaning/importance of the "Alignment" parameter of the IO statement - for example my PIC (now IPIC) code is as follows -

I should start by making it clear that I don't really know what the "Alignment" parameter does. This is just my best guess. I think it's a reasonably good guess, but it's only a guess.

 

There are often addressing restrictions in hardware. While it is convenient to take an abstract view and describe everything as an array of sequentially addressed bytes, this is not necessarily how the hardware will actually work. Sometimes you can only access a resource by specifying an address that is aligned on a 16-bit boundary, or a 32-bit boundary, or a 64-bit boundary, et cetera.

 

I assume the alignment parameter is an attempt to specify this information in an abstract way in ACPI. The excerpt below is on page 608 of Advanced Configuration and Power Interface Specification (rev 4.0).

 

18.5.56 IO (IO Resource Descriptor Macro)

Syntax

IO (Decode, AddressMin, AddressMax, AddressAlignment, RangeLength, DescriptorName) => Buffer

Argument

Decode

describes whether the I/O range uses 10-bit decode (

Decode10

) or 16-bit decode (

Decode16

). The field

DescriptorName

. _DEC is automatically created to refer to this portion of the resource descriptor, where '1' is

Decode16

and '0' is

Decode10

.

AddressMin

evaluates to a 16-bit integer that specifies the minimum acceptable starting address for the I/O range.

It must be an even multiple of

AddressAlignment

. The field

DescriptorName

._MIN is automatically created to refer to this portion of the resource descriptor.

AddressMax

evaluates to a 16-bit integer that specifies the maximum acceptable starting address for the I/O range. It must be an even multiple of

AddressAlignment

. The field

DescriptorName

._MAX is automatically created to refer to this portion of the resource descriptor.

AddressAlignment

evaluates to an 8-bit integer that specifies the alignment granularity for the I/O address assigned. The field

DescriptorName

. _ALN is automatically created to refer to this portion of the resource descriptor.

.....

 

Now as to what is the difference between an alignment of 0 and an alignment of 1 ... beats the heck out of me.

 

The only clue I discovered (in hindsight) is the cryptic (to me) comment that the address must be an even multiple of the value specified for AddressAlignment. What the heck qualifies as an even multiple of 0? Nothing? Everything? Depends on how the IASL compiler handles it, I guess.

 

Specifying "1" feels safer to me than "0", but then again it appears it may not really matter whether you use 0 or 1 here.

[Johnny V]

"How many problems would occur if I used a DSDT from a different Gigabyte motherboard?"

 

None if you use that as Drag&drop parts of like HPET, RTC, AZAL>HDEF into yours.

Those things are similar. AZAL>HDEF maybe not (different Realtech Audio Chip)

But a lot of dsdt heros changed so much to make it more mac like - which make it much harder to adapt it to other MB types!, that you cant use the whole thing on different MB type.

And even you get an 100% same MB dsdt, you may need to edit the PSS part (Pstates), which is CPU/Ghz/FSB depended.

I would make an "search call" for your MB in Post Install 10.5/10.6 forum part if you dont get it here within an week.

 

None if you use that as Drag&drop parts of like HPET, RTC, AZAL>HDEF into yours.

 

Thanks Mitch... could you expand on this as I'm not that clear on what you are suggesting.

 

And even you get an 100% same MB dsdt, you may need to edit the PSS part (Pstates), which is CPU/Ghz/FSB depended.

 

Hmm... If we are getting down to the minutia of CPU/Ghz/FSB with an install, isn't this defeating the purpose of an easy install? I used Kalyway and IPC builds with zero problems for a year and half and never had to worry about overclocking/FSB speed affecting my build.

[Cathul]

And even you get an 100% same MB dsdt, you may need to edit the PSS part (Pstates), which is CPU/Ghz/FSB depended.

 

Hmm... If we are getting down to the minutia of CPU/Ghz/FSB with an install, isn't this defeating the purpose of an easy install? I used Kalyway and IPC builds with zero problems for a year and half and never had to worry about overclocking/FSB speed affecting my build.

 

Well, to my understanding dsdt's cannot really be generic as there are too many possible combinations of mainboards and cpus floating around.

The hints given here and in the speedstep thread are as generic as they can be, but making a dsdt for your own board/cpu combination can be a quite complicated task.

Of course you can copy&paste a lot of things if IDs are identical, but if they are not you have to read through the ACPI specifications for your ICH chip and adapt all changes to your specific mainboard and cpu combination.

 

My advice would be to start with a default DSDT and then start to read about the necessary changes and start modifying one thing after the other with constant testing if things work like they are supposed to do.

 

If that's too much of work for you stay with a generic installation with some more kexts as needed with a heavily modified DSDT.

[Master Chief]

MasterChief (and others),

 

My next question seeking understanding -

 

I have not yet be able to understand the meaning/importance of the "Alignment" parameter of the IO statement - for example my PIC (now IPIC) code is as follows -

 

 ... see post #668

Looking at MasterChief's v3.2 DSDT the IPIC section is -

 ... see post #688

Good question. I didn't knew the answer myself, but I received a reply from Bob (The Intel ACPI developer) which reads:

 

"I believe this is the required alignment within I/O space for the base address that is programmed into the device. Where 0,1 = Byte aligned, 2 = word aligned, 4 = dword aligned, etc."

 

I also found an 8 (0x08) in his grammar.dsl representing a qword. And Apple is also using 0x10 which I believe either represents a double qword or a combination of 2 and 8.

[SMF]

Thanks MasterChief and irrational John,

 

So would you assume that since my PIC/IPIC has an alignment parameter of "1" (which is from my "stock" DSDT as obtained from Linux) that for the Master Controller Edge/Level Triggered Register section I should also use "1" for the alignment parameter? And if I did and it was wrong how would I know/what would be the result/symptom?

 

Thanks again for all your help and time (and my brain must be getting dull reading the specs because I missed that reference (though I'm using version 3.0a as I recall earlier in the thread (or the Asus thread) that MasterChief said that's what the MacPro DSDT is based on. In version 3.0a of the spec perhaps section 17.5.56 and 6.4.2.5 would help. The table 6-28 in 6.4.2.5 discusses "Alignment for minimum base address, increment in 1-byte blocks".

 

Regards,

SMF

[irrational John]

So would you assume that since my PIC/IPIC has an alignment parameter of "1" (which is from my "stock" DSDT as obtained from Linux) that for the Master Controller Edge/Level Triggered Register section I should also use "1" for the alignment parameter? And if I did and it was wrong how would I know/what would be the result/symptom?

I'll yield to whatever Master Chief says since his experience certainly takes precedence here. But FWIW I frankly think it doesn't really matter in this particular case. I'd recommend staying with "1" but mostly because I can't wrap my head around how a non-zero value could be an "even multiple" of 0.

 

But in this case since you are using the same value for both AddressMin and AddressMax, I doubt there is ever any time at which the value in the alignment field is used. That's my wild-ass speculation as to why it might not matter whether you put either "0" or "1" in the alignment field.

 

I'm using version 3.0a as I recall earlier in the thread (or the Asus thread) that MasterChief said that's what the MacPro DSDT is based on.

I took a quick glance at 3.0b and in that version the IO Resource Descriptor Macro was in section 17.5.56. Apparently they added a chapter when going from 3.0 to 4.0. Aside from the location of the section it was in, it looked otherwise unchanged to me.

 

I don't think there are any differences between the spec you referred to and 4.0 that would make a difference in the interpretation/function of this macro.

 

-irrational john

[mitch_de]

After long months of dsdt checking for no sleep problem i found the reason.

DSDT was OK !!!!

Sleepenabled didnt help.

AppleIntelCPUPower.kext wasnt used / loaded (i used voodoomini) was the key !!

Without that (AICP kext) loaded sleep simple NOT WORKING - even if sleepenabler.kext is used.

[blackosx]

After long months of dsdt checking for no sleep problem i found the reason.

DSDT was OK !!!!

Sleepenabled didnt help.

AppleIntelCPUPower.kext wasnt used / loaded (i used voodoomini) was the key !!

Without that (AICP kext) loaded sleep simple NOT WORKING - even if sleepenabler.kext is used.

I remember having a similar quest for sleep when I used 10.5.7. It was a great feeling to have it sorted.

Well done to have finally completed your quest