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DSDT fixes for Gigabyte boards

iSoprano

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Master Chief
Master Chief
Posted
Posted

Another highly optimized DSDT, with a massive code reduction (25%) is now available (as example) in the P5K PRO Snow Leopard Thread.

 

Happy Hacking!

 

Here are lspci's.

Great – I was a little busy the other day, but I will have a look at it, later today.

 

 

At least with the GA-P35-DS3 (not the EP35-DS3!) you don't have a choice. You either enable AHCI for all ICH9-SATA ports or you don't.

Now imagine a smart boot loader, one selecting ACPI mode for your chipset... problem solved – you end up with a blistering fast boot process (no more ACPI nagging at boot time).

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Cathul
Cathul
Posted
Posted
Now imagine a smart boot loader, one selecting ACPI mode for your chipset... problem solved – you end up with a blistering fast boot process (no more ACPI nagging at boot time).

I don't see the problem. BIOS intializes AHCI for SATA ports. The bootloader takes over the responsibility after all ports have been initialized, not?

And with the beta BIOS with AHCI version 1.20something AHCI initialization wasn't such a problem anymore.

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Master Chief
Master Chief
Posted
Posted
I don't see the problem. BIOS intializes AHCI for SATA ports. The bootloader takes over the responsibility after all ports have been initialized, not?

And with the beta BIOS with AHCI version 1.20something AHCI initialization wasn't such a problem anymore.

I'm talking about skipping the BIOS initialization, which slows down the boot process considerably. Just ask William Parker :)

 

Note: I want firmware (BIOS) to load the kernel without any initialization whatsoever, because OS X can handle it... enter Google OS – I am pretty sure that its source code is being read a lot these days. People looking for clues...

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kdawg
kdawg
Posted
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Yes, you can remove these, along with UAR1 and all junk used by it.

 

My UAR1 serial port works. I think for people who might want to use their serial ports, as few as they may be, might want to keep this one. I haven't actually tried my serial port but it's natively recognized by OS X.

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Bansaku
Bansaku
Posted
Posted

Question; is this guide relevant to Gigabyte boards in general or just the P35. I followed every step yet the DSDT will not compile at all. 41 errors all related to SB.PCI0. Maybe the new integrated controller in the new 1156 i5/i7 chips on P55 motherboards has something to do with it? I attached my dsdt.aml with hopes someone can help. :thanks_speechbubble:

dsdt.aml.zip

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William Parker
William Parker
Posted
Posted

@ Master Chief

Still going great guns eh? Pls keep it up.

Skipping Bios Initialization you say? Are you setting up a Motherboard Fab? If you're taking orders I'm in the queue.

But seriously I am looking keenly at Intel DP55KG which appears being capable of scratching my 7 year itch. Sort of civilized quiet boot, intel logo editable, no FDC on board, no PS2 either. Heard the LAN's a bummer though (82578 chip). Will need help for DSDT when I get the board, unless you teach us the magic of booting AHCI on P45 Gigabyte board without initializing the BIOS. The God forsaken ALC889A alone takes 10 seconds.

Loading Kernel from BIOS sounds more like UEFI boot where things are written to NVRAM. Is this on those lines? Boy would I give an arm & a leg for that.

 

 

I'm talking about skipping the BIOS initialization, which slows down the boot process considerably. Just ask William Parker :(

 

Note: I want firmware (BIOS) to load the kernel without any initialization whatsoever, because OS X can handle it... enter Google OS – I am pretty sure that its source code is being read a lot these days. People looking for clues...

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jinnggoff
jinnggoff
Posted
Posted

Hi...

I had to modify my gigabyte mobo dsdt similar imac5, 1..

it can work perfectly ... including shutdown without openhalrestart.

but there is one problem that is annoying ... proccessor into heat when internet sharing is enabled by airport, where the problem does not exist when using the native motherboard dsdt.

anyone knows to solve this problem?

 

here is my custom dsdt

dsdt.zip

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Master Chief
Master Chief
Posted
Posted

I like to remind GigaByte users to include something like this to Method _PTS:

        If (LEqual (Arg0, 0x05))                               // S5 (shutdown).
       {
           Store (One, \_SB.PCI0.LPCB.AG3E)                   // Return to S5 after a power failure
                                                              // Mimic "Start up automatically after power failure" checkbox on Energy Saver (Preferences).
       }

Note: You may need to remove the If clause and just use the Store command.

 

And this code snippet under Device (LPCB) 

                OperationRegion (LPC0, PCI_Config, 0xA0, 0x60) // General PM Configuration 3 Register (ICH9R-316972.pdf / 13.8.1.3 / page 492).
               Field (LPC0, AnyAcc, NoLock, Preserve)
               {
                       ,   10, 
                   XPME,   1,                                 // Bit 10 - BIOS_PCI_EXP_EN.
                           Offset (0x04),                     // General PM Configuration 3 Register (ICH9R-316972.pdf / 13.8.1.3 - / page 492).
                   AG3E,   1,                                 // Bit 0 – AFTERG3_EN.
                           Offset (0x50),                     // Root Complex Base Address Register (ICH9R-316972.pdf / 13.1.35 / page 451).
                   RCBA,   32
               }

I hope that these comments are clear enough :)

 

p.s. And before you say: My board has a ICH10 on board... well. That is irrelevant to the matter.

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MacUser2525
MacUser2525
Posted
Posted
I like to remind GigaByte users to include something like this to Method _PTS:

        If (LEqual (Arg0, 0x05))                               // S5 (shutdown).
       {
           Store (One, \_SB.PCI0.LPCB.AG3E)                   // Return to S5 after a power failure
                                                              // Mimic "Start up automatically after power failure" checkbox on Energy Saver (Preferences).
       }

Note: You may need to remove the If clause and just use the Store command.

 

So with a _PTS like this.

 

	   Method (_PTS, 1, NotSerialized)
   {
	   Or (Arg0, 0xF0, Local0)
	   Store (Local0, DBG1)
	   If (LEqual (Arg0, 0x05))
	   {
		   Store (ESMI, Local0)
		   And (Local0, 0xFB, Local0)
		   Store (Local0, ESMI)
	   }

	   Store (Arg0, \_SB.PCI0.LPCB.EC.ECSS)
	   G3HT ()
	   \_SB.PCI0.SBUS.DISB ()
   }

 

You would change to.

 

	   Method (_PTS, 1, NotSerialized)
   {
	   Or (Arg0, 0xF0, Local0)
	   Store (Local0, DBG1)
	   If (LEqual (Arg0, 0x05))
	   {
		   Store (One, \_SB.PCI0.LPCB.AG3E)
	   }

	   Store (Arg0, \_SB.PCI0.LPCB.EC.ECSS)
	   G3HT ()
	   \_SB.PCI0.SBUS.DISB ()
   }

 

Getting rid of the ESMI.

 

And this code snippet under Device (LPCB) 
                OperationRegion (LPC0, PCI_Config, 0xA0, 0x60) // General PM Configuration 3 Register (ICH9R-316972.pdf / 13.8.1.3 / page 492).
               Field (LPC0, AnyAcc, NoLock, Preserve)
               {
                       ,   10, 
                   XPME,   1,                                 // Bit 10 - BIOS_PCI_EXP_EN.
                           Offset (0x04),                     // General PM Configuration 3 Register (ICH9R-316972.pdf / 13.8.1.3 - / page 492).
                   AG3E,   1,                                 // Bit 0 �" AFTERG3_EN.
                           Offset (0x50),                     // Root Complex Base Address Register (ICH9R-316972.pdf / 13.1.35 / page 451).
                   RCBA,   32
               }

I hope that these comments are clear enough :(

 

p.s. And before you say: My board has a ICH10 on board... well. That is irrelevant to the matter.

 

For this I have

 

   Field (LPC0, AnyAcc, NoLock, Preserve)
			   {
					   ,   10, 
				   XPME,   1, 
						   Offset (0x04), 
				   AG3E,   1, 
						   Offset (0x50), 
				   RAEN,   1, 
					   ,   13, 
				   RCBA,   18
			   }

 

Which would be after your suggested change.

 

   Field (LPC0, AnyAcc, NoLock, Preserve)
			   {
					   ,   10, 
				   XPME,   1, 
						   Offset (0x04), 
				   AG3E,   1, 
						   Offset (0x50), 
				   RCBA,   32
			   }

 

Or would the RAEN part still be in there and does this eliminate the need to have the box checked to "Start up automatically after power failure" as well?

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Master Chief
Master Chief
Posted
Posted
So with a _PTS like this.

 ... see post # 611

You would change to.

 

 ... see post # 611

Getting rid of the ESMI.

 

For this I have

 ... see post # 611

Which would be after your suggested change.

 ... see post # 611

 

Or would the RAEN part still be in there and does this eliminate the need to have the box checked to "Start up automatically after power failure" as well?

The idea is to add Store (One, \_SB.PCI0.LPCB.AG3E) inside the If (LEqual (Arg0, 0x05)) {}

And yes, this will take care of that checkbox for you.

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AudiSport
AudiSport
Posted
Posted

Master Chief,

I added LPCB.AG3E to PTS as well as the LPC0 to LPCB but I am still getting a reboot when waking from sleep when "Start up automatically after power failure" is unchecked. I tried removing the ESMI stuff with no change and I moved LPCB.AG3E outside the if as well and still no change.

 

Attached is my dsdt.dsl.

dsdt.dsl.zip

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mitch_de
mitch_de
Posted
Posted

MC :

  OperationRegion (LPC0, PCI_Config, 0x[b][color="#008000"]A0[/color][/b], 0x[b][color="#008000"]60[/color][/b])[size=1] // General PM Configuration 3 Register (ICH9R-316972.pdf / 13.8.1.3 / page 492).[/size]
               Field (LPC0, AnyAcc, NoLock, Preserve)
               {
                       [size=4][color="#FF0000"][b],[/b][/color][/size]   10, 
                   XPME,   1,                                 /[size=1]/ Bit 10 - BIOS_PCI_EXP_EN.[/size]
                           Offset (0x04),                    [size=1] // General PM Configuration 3 Register (ICH9R-316972.pdf / 13.8.1.3 - / page 492).[/size]
                   AG3E,   1,                                 [size=1]// Bit 0 – AFTERG3_EN.[/size]
                           Offset (0x50),                    [size=1] // Root Complex Base Address Register (ICH9R-316972.pdf / 13.1.35 / page 451).[/size]
                   RCBA,   32
               }

 

 

Does your code qbove is a sniplet , means before the comma , is the old code ?

I ask because that code starts with an comma . If full code i am a bit confused about the comma (marked red in codebox).

Or comes before the comma, that Offset (0x20) (see my Codebox) ?

 

My "orig." LPC code part is much bigger - can i use that code only without mine before the comma ? (dont know if from orig. BIOS Ep35-DS3, or modded x times :) )

 

Also i am a bit confused about that different PCI_Config hex numbers : PCI_Config, 0xA0, 0x60 vs PCI_Config, 0x40, 0xC0) - does it matter (ICH9, ICH9R, ICH10,..) or my PCIConfig hex numbers simle wrong ?

 

  OperationRegion (LPC0, PCI_Config, 0x[b]40[/b], 0x[b]C0[/b])
[size=1]                Field (LPC0, AnyAcc, NoLock, Preserve)
               {
                           [b]Offset (0x20)[/b], 
                   PARC,   8, 
                   PBRC,   8, 
                   PCRC,   8, 
                   PDRC,   8, 
                           Offset (0x28), 
                   PERC,   8, 
                   PFRC,   8, 
                   PGRC,   8, 
                   PHRC,   8, 
                           Offset (0x40), 
                   IOD0,   8, 
                   IOD1,   8, 
                           Offset (0x60), 
                       ,   10, 
                   XPME,   1, 
                           Offset (0x64), 
                   AG3E,   1, 
                           Offset (0xB0), 
                   RAEN,   1, 
                       ,   13, 
                   RCBA,   18
[/size]                }

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blackosx
blackosx
Posted
Posted

Hi mitch

 

My original DSDT didn't have an OperationRegion (LPC0... section.

(My current DSDT now has come a long way since my original DSDT)

 

I have added it exactly as MasterChief has described above. Leave the green numbers as Master Chief has them, as the General PM Configuration 3 Register is at location D31:F0:A4h (intel ICH9 & ICH10 datasheets). This ties in with your Device (LPCB) (used to be PX40) above which will read Name (_ADR, 0x001F0000) (Intel Bus 0:Device 31:Function 0 - LPC Controller)

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Master Chief
Master Chief
Posted
Posted
MC :

 see post #

...

What I do is to skip the unused part by taking 0x40 from the old DSDT and add the value of Offset(0x60) giving me that 0xA0. Enter a new base address of 0xA0. And when you see something like this: 

Field (LPC0, AnyAcc, NoLock, Preserve)
{
	, 10, 
XPME, 1, // Bit 10 - BIOS_PCI_EXP_EN.
...

The lack of a identifier (name) simply means that we skip – are not interested in – the first ten (10) bits. And XPME is bit ten (10) because we start from zero (0) instead of the usual one (1) and thus we skip bit: 0,1,2,3,4,5,6,7,8,9 here. And thus we assign XPME to bit ten (10).

 

And what blackosx said is correct ;)

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Master Chief
Master Chief
Posted
Posted
Master Chief,

I added LPCB.AG3E to PTS as well as the LPC0 to LPCB but I am still getting a reboot when waking from sleep when "Start up automatically after power failure" is unchecked. I tried removing the ESMI stuff with no change and I moved LPCB.AG3E outside the if as well and still no change.

 

Attached is my dsdt.dsl.

dsdt.dsl.zip

Add Store (One, \_SB.PCI0.LPCB.AG3E) to Method _WAK and see how the checkbox changes from unchecked to checked. If not then something is wrong.

 

You can also verify this by entering lspci -nn in a terminal window, to get the device-id (by looking for the ISA bridge) and then to enter lspci -d 8086:2916 -xxxvvv (using the device id) and see how register A5 changes from 38 into 39 and vise versa.

 

p.s. Looking at your DSDT... you still have work to do!

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AudiSport
AudiSport
Posted
Posted
Add Store (One, \_SB.PCI0.LPCB.AG3E) to Method _WAK and see how the checkbox changes from unchecked to checked. If not then something is wrong.
Did that but still no change in behavior on waking from sleep when unchecked.

 

You can also verify this by entering lspci -nn in a terminal window, to get the device-id (by looking for the ISA bridge) and then to enter lspci -d 8086:2916 -xxxvvv (using the device id) and see how register A5 changes from 38 into 39 and vise versa.
I did lspci -d 8086:27b8 -xxxvvv and I do see the A5 register changing when I check and uncheck the preference.

 

p.s. Looking at your DSDT... you still have work to do!
I know and am slowly picking through the posts to figure out and understand what the changes do and how they will be different for my ICH7 board. I know some of my namespaces are different than yours but that is because I am targeting making my hack look like an iMac5,1 or iMac6,1 because they were the the last real Macs that had the ICH7 chipset. The USB naming seems to be the biggest difference. What areas are you referring to that you see need work?

 

Thanks!

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Master Chief
Master Chief
Posted
Posted
Did that but still no change in behavior on waking from sleep when unchecked.

Let's see if I get this right. It works when you tick the checkbox, but it fails when you add it in your DSDT?

 

I know and am slowly picking through the posts to figure out and understand what the changes do and how they will be different for my ICH7 board. I know some of my namespaces are different than yours but that is because I am targeting making my hack look like an iMac5,1 or iMac6,1 because they were the the last real Macs that had the ICH7 chipset. The USB naming seems to be the biggest difference. What areas are you referring to that you see need work?

 

Thanks!

There's a whole lot of things to work on. Here are a few pointers: _STA, _S3D, _PRW, _PRT, MCDP -> MCID, PIRA, PIRB, PIRC, PIRD, PIRE, PIRF, PIRG, PIRG, SLDM, _CRS, SPKR, EXFG, ENFG

 

Yours: 

Method (_PSW, 1, NotSerialized)
{
If (Arg0)
{
	Store (0x03, USBW)
}
Else
{
	Store (Zero, USBW)
}
}

Mine: 

Method (_PSW, 1, NotSerialized)
{
Multiply (0x03, Arg0, USBW)
}

Just look at my DSDT (or another GB one from this thread) and see what we changed. The result will be a much cleaner dsdt.dsl and a smaller dsdt.aml

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mm67
mm67
Posted
Posted
I'll wait for someone to confirm it to work. Or not of course.

 

I can confirm that, and yes, lspci shows that bit changing status when I switch status of Start up automatically... setting. However it doesn't work the other way, if I write to that bit the System preference setting doesn't change.

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AudiSport
AudiSport
Posted
Posted
Let's see if I get this right. It works when you tick the checkbox, but it fails when you add it in your DSDT?
When the checkbox it ticked wakeup from sleep works correctly. When the checkbox is unchecked a wakeup from sleep produces a reboot. I see the same behavior with or without the Store (One, \_SB.PCI0.LPCB.AG3E) DSDT changes. Unless I am misunderstanding but I thought that with the Store (One, \_SB.PCI0.LPCB.AG3E) DSDT changes you mentioned that I could have the checkbox unchecked and wakeup from sleep would work and not reboot.

 

I will get to work on those other fixup. Thanks for the pointers.

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Bansaku
Bansaku
Posted
Posted

After upgrading my DSDT editor to EVO DSTSE things have gone a lot smoother. However, I still get one error when trying to compile; /Library/Application Support/EvOSoftware/DSDT/DSDTFiles/dsdt.dsl 1: ehcify (\_SB.PCI0.PEX2, 0x02) Error 4096 - ^ syntax error, unexpected PARSEOP_NAMESEG, expecting PARSEOP_DEFINITIONBLOCK

 

I am not sure why I am getting this error, seeing how I never touched that part in the DSDT. What the guide had me change posted no errors yet I am stuck one this last snag. I included my latest attempt at USB fix (and my successful HPET fix for MacPro4,1 speedsteping and vanilla AppleCPUPM.kext) with all the changes I have done. Any suggestions?

 

 

 

sry my attachment failed to u/l ><

dsdt.zip

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Acid_Burn
Acid_Burn
Posted
Posted

Hi!

 

I have a G33M-DS2R Board.

- Q6600 Quad

- 4 GB Ram

- 7600 GT

- ALC889A

- ICH9R

 

My Snow works great (Sound, SATA, LAN, USB, VGA, FireWire, Reboot/Shutdown with OHR, orig CPU Powermanagement). But my Sleep don´t work. Gives a DSDT Solution for my Board?

 

Please help me :(

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Master Chief
Master Chief
Posted
Posted
When the checkbox it ticked wakeup from sleep works correctly. When the checkbox is unchecked a wakeup from sleep produces a reboot.

Good to know.

 

I see the same behavior with or without the Store (One, \_SB.PCI0.LPCB.AG3E) DSDT changes. Unless I am misunderstanding but I thought that with the Store (One, \_SB.PCI0.LPCB.AG3E) DSDT changes you mentioned that I could have the checkbox unchecked and wakeup from sleep would work and not reboot.

This is clearly another bug in the GigaByte BIOS since this setting (read LPCB:PCI register 0xA4) controls the state to return to after a power failure. It has nothing to do with sleep, but let's figure out how to solve this. Now. The value of register A4 is 38 for the checked state and 39 for an unchecked state. And the former corresponds with this text in the ICH datasheet:

 

"System will return to S0 state (boot) after power is re-applied.

 

And if that is what you need for resume after sleep, then you must use Store (Zero, \_SB.PCI0.LPCB.AG3E) and use Store (One, \_SB.PCI0.LPCB.AG3E) only for shutdown.

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