DSDT fixes for Gigabyte boards

xjasx · October 24, 2009

How are you guys dropping CPU temps w/ PowerManagement? I have both P-States and C-States working, can confirm Voltage and FSB ratio dropping (x6, x7, x8, x9) etc, but temps are still around 7-10C higher than compared to temps with NullCPUPowerManagement running at full speed/full power at all time....

Matthew L. · October 24, 2009

That is a variant of my scope PR

If I use this:

    Scope (_PR)
   {
       Processor (CPU0, 0x00, 0x00000410, 0x06)
       {
           OperationRegion (PMBL, SystemMemory, 0xDFEE87E0, 0x03AB) 
           Name (PDC0, 0x80000000) 
           Name (HNDL, 0x80000000) 
           Name (TBLD, 0x00000080) 

           Method (_INI, 0, NotSerialized) 
           {
               If (LNot (And (TBLD, One)))
               {
                   Or (TBLD, One, TBLD)
                   Load (PMBL, HNDL)
               }
           }

           Name (_PSS, Package (0x03)
           {
               Package (0x06)
               {
                   0x0D20, 
                   0x000124F8, 
                   0x0A, 
                   0x0A, 
                   0x0820, 
                   0x0820
               }, 

               Package (0x06)
               {
                   0x0B7C, 
                   0xFDE8, 
                   0x0A, 
                   0x0A, 
                   0x071C, 
                   0x071C
               }, 

               Package (0x06)
               {
                   0x09D8, 
                   0xEA60, 
                   0x0A, 
                   0x0A, 
                   0x061A, 
                   0x061A
               }
           })

           Method (_CST, 0, NotSerialized) 
           {
               If (And (PDC0, 0x18)) 
               {
                    Return (\_PR.CPU1._CST()) 
               }
               Else
               {
                   Return (Package (0x02)
                   {
                       One, 
                       Package (0x04)
                       {
                           ResourceTemplate ()
                           {
                               Register (FFixedHW, 
                               0x00,               // Bit Width
                               0x00,               // Bit Offset
                               0x0000000000000000, // Address
                               ,)
                           }, 

                           One, 
                           0x9D, 
                           0x03E8 
                       }
                   })
               }
           }
       }

       Processor (CPU1, 0x01, 0x00000410, 0x06)
       {
           Method (_CST, 0, NotSerialized) 
           {
                   Return (Package (0x04)
                   {
                       0x03, 
                       Package (0x04)
                       {
                           ResourceTemplate ()
                           {
                               Register (FFixedHW, 
                                   0x01,               // Bit Width
                                   0x02,               // Bit Offset
                                   0x0000000000000000, // Address
                                   0x01,               // Access Size
                                   )
                           },
                           One, 
                           One, 
                           0x03E8
                       }, 

                       Package (0x04)
                       {
                           ResourceTemplate ()
                           {
                               Register (SystemIO, 
                                   0x08,               // Bit Width
                                   0x00,               // Bit Offset
                                   0x0000000000000814, // Address
                                   ,)
                           },
                           0x02,
                           One,
                           0x01F4
                       }, 

                       Package (0x04)
                       {
                           ResourceTemplate ()
                           {
                               Register (SystemIO, 
                                   0x08,               // Bit Width
                                   0x00,               // Bit Offset
                                   0x0000000000000815, // Address
                                   ,)
                           },
                           0x03,
                           0x11,
                           0xFA
                       }
                   })
           }
       }

       Processor (CPU2, 0x02, 0x00000410, 0x06)
       {
           Method (_CST, 0, NotSerialized)
           {
               Return (\_PR.CPU1._CST())
           }
       }

       Processor (CPU3, 0x03, 0x00000410, 0x06)
       {
           Method (_CST, 0, NotSerialized)
           {
               Return (\_PR.CPU1._CST())
           }
       }
}

I get PDC related compile errors when (obviously PDc is not defined.)

/Users/Dave/Desktop/dsdt25-10-09.dsl   408:             If (And (PDC1, 0x18))
Error    4063 -                               Object does not exist ^  (PDC1)

If I define PDC in any way it seems to stop my p-states working.

Any ideas?

I've been asking Master Chief for a working PNOT implementation with this type of _PR scope too, so we're going to get a suggestion from him a bit later I think.

milanca · October 24, 2009

@Mathew L., iSoprano,

That's exactly what i am struggling with for the last couple of days. With one method i can get Pstates loaded but then sleep is broken; if i change the method then sleep is working but power management doesn't work properly, like its being blocked from loading.

Master Chief · October 24, 2009

That is a variant of my scope PR. If I use this:

<snip />

I get PDC related compile errors when (obviously PDc is not defined.)
/Users/Dave/Desktop/dsdt25-10-09.dsl   408:			 If (And (PDC1, 0x18))
Error	4063 -							   Object does not exist ^  (PDC1)
If I define PDC in any way it seems to stop my p-states working.

Any ideas?

Not really. I mean I can't see what line 408 is about, which is where the errors appears to be. Have you checked the table, to see if that defines PDCn? What table is that BTW?

FKA · October 24, 2009

Not really. I mean I can't see what line 408 is about, which is where the errors appears to be. Have you checked the table, to see if that defines PDCn? What table is that BTW?

**EDIT** its PNOT

OK I just tried this:

(my working _PR additions in red)

    Scope (_PR)
   {
       Processor (CPU0, 0x00, 0x00000410, 0x06) {}
       Processor (CPU1, 0x01, 0x00000410, 0x06) {}
       Processor (CPU2, 0x02, 0x00000410, 0x06) {}
       Processor (CPU3, 0x03, 0x00000410, 0x06) {}
       Name (CFGD, 0x040383F2)
       Name (PDC0, 0x80000000)
       [b][color="#ff0000"]Name (PDC1, 0x80000000)
       Name (PDC2, 0x80000000)
       Name (PDC3, 0x80000000)[/color][/b]

   }

   Scope (_PR.CPU0)
   {
       Method (_CST, 0, NotSerialized)
       {
           If (LAnd (And (CFGD, 0x01000000), LNot (And (PDC0, 0x10
               ))))
           {
               Return (Package (0x02)
               {
                   One, 
                   Package (0x04)
                   {
                       ResourceTemplate ()
                       {
                           Register (FFixedHW, 
                               0x00,               // Bit Width
                               0x00,               // Bit Offset
                               0x0000000000000000, // Address
                               ,)
                       }, 

                       One, 
                       0x9D, 
                       0x03E8
                   }
               })
           }

           If (And (PDC0, 0x0300))
           {
               If (And (CFGD, 0x20))
               {
                   Return (Package (0x03)
                   {
                       0x02, 
                       Package (0x04)
                       {
                           ResourceTemplate ()
                           {
                               Register (FFixedHW, 
                                   0x01,               // Bit Width
                                   0x02,               // Bit Offset
                                   0x0000000000000000, // Address
                                   ,)
                           }, 

                           One, 
                           One, 
                           0x03E8
                       }, 

                       Package (0x04)
                       {
                           ResourceTemplate ()
                           {
                               Register (FFixedHW, 
                                   0x01,               // Bit Width
                                   0x02,               // Bit Offset
                                   0x0000000000000010, // Address
                                   ,)
                           }, 

                           0x02, 
                           One, 
                           0x01F4
                       }
                   })
               }
           }

           If (And (CFGD, 0x20))
           {
               Return (Package (0x03)
               {
                   0x02, 
                   Package (0x04)
                   {
                       ResourceTemplate ()
                       {
                           Register (FFixedHW, 
                               0x01,               // Bit Width
                               0x02,               // Bit Offset
                               0x0000000000000000, // Address
                               ,)
                       }, 

                       One, 
                       One, 
                       0x03E8
                   }, 

                   Package (0x04)
                   {
                       ResourceTemplate ()
                       {
                           Register (SystemIO, 
                               0x08,               // Bit Width
                               0x00,               // Bit Offset
                               0x0000000000000414, // Address
                               ,)
                       }, 

                       0x02, 
                       One, 
                       0x01F4
                   }
               })
           }

           Return (Package (0x02)
           {
               One, 
               Package (0x04)
               {
                   ResourceTemplate ()
                   {
                       Register (FFixedHW, 
                           0x01,               // Bit Width
                           0x02,               // Bit Offset
                           0x0000000000000000, // Address
                           ,)
                   }, 

                   One, 
                   One, 
                   0x03E8
               }
           })
       }

       Method (_PPC, 0, NotSerialized)
       {
           Return (Zero)
       }

       Method (_PCT, 0, NotSerialized)
       {
           Return (Package (0x02)
           {
               ResourceTemplate ()
               {
                   Register (FFixedHW, 
                       0x10,               // Bit Width
                       0x00,               // Bit Offset
                       0x0000000000000199, // Address
                       ,)
               }, 

               ResourceTemplate ()
               {
                   Register (FFixedHW, 
                       0x10,               // Bit Width
                       0x00,               // Bit Offset
                       0x0000000000000198, // Address
                       ,)
               }
           })
       }

       Method (_PSS, 0, NotSerialized)
       {
           Return (Package (0x03)
           {
               Package (0x06)
               {
                   0x0D20, 
                   0x000124F8, 
                   0x0A, 
                   0x0A, 
                   0x0820, 
                   0x0820
               }, 

               Package (0x06)
               {
                   0x0B7C, 
                   0xFDE8, 
                   0x0A, 
                   0x0A, 
                   0x071C, 
                   0x071C
               }, 

               Package (0x06)
               {
                   0x09D8, 
                   0xEA60, 
                   0x0A, 
                   0x0A, 
                   0x061A, 
                   0x061A
               }
           })
       }
   }

   Scope (_PR.CPU1)
   {
       Method (_CST, 0, NotSerialized)
       {
           Return (^^CPU0._CST ())
       }

       Method (_PPC, 0, NotSerialized)
       {
           Return (Zero)
       }

       Method (_PCT, 0, NotSerialized)
       {
           Return (^^CPU0._PCT ())
       }

       Method (_PSS, 0, NotSerialized)
       {
           Return (^^CPU0._PSS ())
       }
   }

   Scope (_PR.CPU2)
   {
       Method (_CST, 0, NotSerialized)
       {
           Return (^^CPU0._CST ())
       }

       Method (_PPC, 0, NotSerialized)
       {
           Return (Zero)
       }

       Method (_PCT, 0, NotSerialized)
       {
           Return (^^CPU0._PCT ())
       }

       Method (_PSS, 0, NotSerialized)
       {
           Return (^^CPU0._PSS ())
       }
   }

   Scope (_PR.CPU3)
   {
       Method (_CST, 0, NotSerialized)
       {
           Return (^^CPU0._CST ())
       }

       Method (_PPC, 0, NotSerialized)
       {
           Return (Zero)
       }

       Method (_PCT, 0, NotSerialized)
       {
           Return (^^CPU0._PCT ())
       }

       Method (_PSS, 0, NotSerialized)
       {
           Return (^^CPU0._PSS ())
       }
   }

And with this edit to PNOT:

    Method (PNOT, 0, Serialized)
   {
       If (And ([b][color="#ff0000"]\_PR.PDC0[/color][/b], 0x08))
       {
           Notify (\_PR.CPU0, 0x80)
           If (And [b][color="#ff0000"](\_PR.[/color][/b]PDC0, 0x18))
           {
               Sleep (0x64)
               Notify (\_PR.CPU0, 0x81)
           }
       }

       If (And ([b][color="#ff0000"]\_PR.PDC1[/color][/b], 0x08))
       {
           Notify (\_PR.CPU1, 0x80)
           If (And ([b][color="#ff0000"]\_PR.PDC1[/color][/b], 0x18))
           {
               Sleep (0x64)
               Notify (\_PR.CPU1, 0x81)
           }
       }

       If (And ([color="#ff0000"][b]\_PR.PDC2[/b][/color], 0x08))
       {
           Notify (\_PR.CPU2, 0x80)
           If (And ([b][color="#ff0000"]\_PR.PDC2[/color][/b], 0x18))
           {
               Sleep (0x64)
               Notify (\_PR.CPU2, 0x81)
           }
       }

       If (And (\_PR.PDC3, 0x08))
       {
           Notify (\_PR.CPU3, 0x80)
           If (And (\[b][color="#ff0000"]_PR.PDC3[/color][/b], 0x18))
           {
               Sleep (0x64)
               Notify (\_PR.CPU3, 0x81)
           }
       }
   }

Still no p-states

00:00.0 Host bridge: Intel Corporation DRAM Controller (rev 02)
00:01.0 PCI bridge: Intel Corporation PCI Express Root Port (rev 02)
00:1a.0 USB Controller: Intel Corporation USB UHCI Controller #4 (rev 02)
00:1a.1 USB Controller: Intel Corporation USB UHCI Controller #5 (rev 02)
00:1a.2 USB Controller: Intel Corporation USB UHCI Controller #6 (rev 02)
00:1a.7 USB Controller: Intel Corporation USB2 EHCI Controller #2 (rev 02)
00:1b.0 Audio device: Intel Corporation HD Audio Controller (rev 02)
00:1c.0 PCI bridge: Intel Corporation PCI Express Port 1 (rev 02)
00:1c.4 PCI bridge: Intel Corporation PCI Express Port 5 (rev 02)
00:1c.5 PCI bridge: Intel Corporation PCI Express Port 6 (rev 02)
00:1d.0 USB Controller: Intel Corporation USB UHCI Controller #1 (rev 02)
00:1d.1 USB Controller: Intel Corporation USB UHCI Controller #2 (rev 02)
00:1d.2 USB Controller: Intel Corporation USB UHCI Controller #3 (rev 02)
00:1d.7 USB Controller: Intel Corporation USB2 EHCI Controller #1 (rev 02)
00:1e.0 PCI bridge: Intel Corporation 82801 PCI Bridge (rev 92)
00:1f.0 ISA bridge: Intel Corporation LPC Interface Controller (rev 02)
00:1f.2 SATA controller: Intel Corporation 6 port SATA AHCI Controller (rev 02)
00:1f.3 SMBus: Intel Corporation SMBus Controller (rev 02)
01:00.0 VGA compatible controller: nVidia Corporation Unknown device 0640 (rev a1)
04:00.0 Ethernet controller: Realtek Semiconductor Co., Ltd. RTL8111/8168B PCI Express Gigabit Ethernet controller (rev 01)
05:06.0 FireWire (IEEE 1394): Texas Instruments TSB43AB23 IEEE-1394a-2000 Controller (PHY/Link)

DAVIOREG1.zip

dsdt24_10_09.dsl.zip

Master Chief · October 24, 2009

I've been asking Master Chief for a working PNOT implementation with this type of _PR scope too, so we're going to get a suggestion from him a bit later I think.

You already have Method PNOT () and the callers in Method _WAK and _Q80 so what makes you think that it ain't working for you? I might have missed "it" but care to explain this to me?

Edit: You guys need to have the following aliases (this might in fact be "it"):

	// Aliases for the Power Management Notifier. 
Alias (\_PR.CPU0.PDC0, PDC0)
Alias (\_PR.CPU1.PDC1, PDC1)
Alias (\_PR.CPU2.PDC2, PDC2)
Alias (\_PR.CPU3.PDC3, PDC3)

Are these missing?

And here are mine:

	// Aliases for the Power Management Notifier. 
Alias (\_PR.CPU1.TYPE, PDC1)
Alias (\_PR.CPU2.TYPE, PDC2)
Alias (\_PR.CPU3.TYPE, PDC3)
Alias (\_PR.CPU4.TYPE, PDC4)

For people where TYPE is initialized by OSPM with the capabilities.

Note: Your CPU index might start at 0 (CPU0) instead of 1 (CPU1). Also check PDC1.

mm67 · October 24, 2009

**EDIT** its PNOT
OK I just tried this:

(my working _PR additions in red)

Still no p-states

Try like this.

test.dsl.zip

Master Chief · October 24, 2009

Try like this.
test.dsl.zip

I understand that you are trying to help (FormelyKnownAs) which is great, really, but please don't forget that we are trying to make a universal DSDT, and the way you've done it now won't work – we either use the aliases or add the PDCn declarations into the start of the _PR scope (SSDT also want these). This way non-coders can make changes, without having to mess with scope issues.

mm67 · October 24, 2009

I understand that you are trying to help (FormelyKnownAs) which is great, really, but please don't forget that we are trying to make a universal DSDT, and the way you've done it now won't work �€“ we either use the aliases or add the PDCn declarations into the start of the _PR scope (SSDT also want these). This way non-coders can make changes, without having to mess with scope issues.

Ok, maybe this is better then.

test.dsl.zip

/edit

Can't use factory PSS tables if load IST tables like this, handmade PSS tables work.

FKA · October 25, 2009

Ok, maybe this is better then.
test.dsl.zip

Thanks for this - I've added device id's for UHCI and SATA - it works bar p-states !

**EDIT** 3 pstates listed just stuck at multi 8

MC - I've added alias so:

    Scope (_PR)
   {
       Processor (CPU0, 0x00, 0x00000410, 0x06) {}
       Processor (CPU1, 0x01, 0x00000410, 0x06) {}
       Processor (CPU2, 0x02, 0x00000410, 0x06) {}
       Processor (CPU3, 0x03, 0x00000410, 0x06) {}
Name (CFGD, 0x040383F2)
       Name (PDC0, 0x80000000)
       Name (PDC1, 0x80000000)
       Name (PDC2, 0x80000000)
       Name (PDC3, 0x80000000)

   }

   Scope (_PR.CPU0)
   {
       Method (_CST, 0, NotSerialized)
       {
           If (LAnd (And (CFGD, 0x01000000), LNot (And (PDC0, 0x10
               ))))
           {
               Return (Package (0x02)
               {
                   One, 
                   Package (0x04)
                   {
                       ResourceTemplate ()
                       {
                           Register (FFixedHW, 
                               0x00,               // Bit Width
                               0x00,               // Bit Offset
                               0x0000000000000000, // Address
                               ,)
                       }, 

                       One, 
                       0x9D, 
                       0x03E8
                   }
               })
           }

           If (And (PDC0, 0x0300))
           {
               If (And (CFGD, 0x20))
               {
                   Return (Package (0x03)
                   {
                       0x02, 
                       Package (0x04)
                       {
                           ResourceTemplate ()
                           {
                               Register (FFixedHW, 
                                   0x01,               // Bit Width
                                   0x02,               // Bit Offset
                                   0x0000000000000000, // Address
                                   ,)
                           }, 

                           One, 
                           One, 
                           0x03E8
                       }, 

                       Package (0x04)
                       {
                           ResourceTemplate ()
                           {
                               Register (FFixedHW, 
                                   0x01,               // Bit Width
                                   0x02,               // Bit Offset
                                   0x0000000000000010, // Address
                                   ,)
                           }, 

                           0x02, 
                           One, 
                           0x01F4
                       }
                   })
               }
           }

           If (And (CFGD, 0x20))
           {
               Return (Package (0x03)
               {
                   0x02, 
                   Package (0x04)
                   {
                       ResourceTemplate ()
                       {
                           Register (FFixedHW, 
                               0x01,               // Bit Width
                               0x02,               // Bit Offset
                               0x0000000000000000, // Address
                               ,)
                       }, 

                       One, 
                       One, 
                       0x03E8
                   }, 

                   Package (0x04)
                   {
                       ResourceTemplate ()
                       {
                           Register (SystemIO, 
                               0x08,               // Bit Width
                               0x00,               // Bit Offset
                               0x0000000000000414, // Address
                               ,)
                       }, 

                       0x02, 
                       One, 
                       0x01F4
                   }
               })
           }

           Return (Package (0x02)
           {
               One, 
               Package (0x04)
               {
                   ResourceTemplate ()
                   {
                       Register (FFixedHW, 
                           0x01,               // Bit Width
                           0x02,               // Bit Offset
                           0x0000000000000000, // Address
                           ,)
                   }, 

                   One, 
                   One, 
                   0x03E8
               }
           })
       }

       Method (_PPC, 0, NotSerialized)
       {
           Return (Zero)
       }

       Method (_PCT, 0, NotSerialized)
       {
           Return (Package (0x02)
           {
               ResourceTemplate ()
               {
                   Register (FFixedHW, 
                       0x10,               // Bit Width
                       0x00,               // Bit Offset
                       0x0000000000000199, // Address
                       ,)
               }, 

               ResourceTemplate ()
               {
                   Register (FFixedHW, 
                       0x10,               // Bit Width
                       0x00,               // Bit Offset
                       0x0000000000000198, // Address
                       ,)
               }
           })
       }

       Method (_PSS, 0, NotSerialized)
       {
           Return (Package (0x03)
           {
               Package (0x06)
               {
                   0x0D20, 
                   0x000124F8, 
                   0x0A, 
                   0x0A, 
                   0x0820, 
                   0x0820
               }, 

               Package (0x06)
               {
                   0x0B7C, 
                   0xFDE8, 
                   0x0A, 
                   0x0A, 
                   0x071C, 
                   0x071C
               }, 

               Package (0x06)
               {
                   0x09D8, 
                   0xEA60, 
                   0x0A, 
                   0x0A, 
                   0x061A, 
                   0x061A
               }
           })
       }
   }

   Scope (_PR.CPU1)
   {
       Method (_CST, 0, NotSerialized)
       {
           Return (^^CPU0._CST ())
       }

       Method (_PPC, 0, NotSerialized)
       {
           Return (Zero)
       }

       Method (_PCT, 0, NotSerialized)
       {
           Return (^^CPU0._PCT ())
       }

       Method (_PSS, 0, NotSerialized)
       {
           Return (^^CPU0._PSS ())
       }
   }

   Scope (_PR.CPU2)
   {
       Method (_CST, 0, NotSerialized)
       {
           Return (^^CPU0._CST ())
       }

       Method (_PPC, 0, NotSerialized)
       {
           Return (Zero)
       }

       Method (_PCT, 0, NotSerialized)
       {
           Return (^^CPU0._PCT ())
       }

       Method (_PSS, 0, NotSerialized)
       {
           Return (^^CPU0._PSS ())
       }
   }

   Scope (_PR.CPU3)
   {
       Method (_CST, 0, NotSerialized)
       {
           Return (^^CPU0._CST ())
       }

       Method (_PPC, 0, NotSerialized)
       {
           Return (Zero)
       }

       Method (_PCT, 0, NotSerialized)
       {
           Return (^^CPU0._PCT ())
       }

       Method (_PSS, 0, NotSerialized)
       {
           Return (^^CPU0._PSS ())
       }
   }

   Name (_S0, Package (0x04)
   {
       Zero, 
       Zero, 
       Zero, 
       Zero
   })
   Name (SS1, Package (0x04)
   {
       One, 
       Zero, 
       Zero, 
       Zero
   })
   Name (_S3, Package (0x04)
   {
       0x05, 
       Zero, 
       Zero, 
       Zero
   })
   Name (_S4, Package (0x04)
   {
       0x06, 
       Zero, 
       Zero, 
       Zero
   })
   Name (_S5, Package (0x04)
   {
       0x07, 
       Zero, 
       Zero, 
       Zero
   })
   Name (FLAG, Zero)
   Name (STAT, Zero)
   OperationRegion (SMOD, SystemMemory, 0x000FF840, One)
   Field (SMOD, ByteAcc, NoLock, Preserve)
   {
           ,   7, 
       SUSF,   1
   }

   OperationRegion (DEBG, SystemIO, 0x80, One)
   Field (DEBG, ByteAcc, NoLock, Preserve)
   {
       DBG1,   8
   }

   OperationRegion (RCRB, SystemMemory, 0xFED1C000, 0x4000)
   Field (RCRB, DWordAcc, Lock, Preserve)
   {
               Offset (0x3404), 
           ,   7, 
       HPTF,   1
   }

   OperationRegion (ELKM, SystemMemory, 0x000FFFEA, One)
   Field (ELKM, ByteAcc, NoLock, Preserve)
   {
           ,   1, 
           ,   1, 
       ELSO,   1, 
           ,   1, 
           ,   1, 
           ,   1, 
           ,   1
   }

   OperationRegion (EXTM, SystemMemory, 0x000FF830, 0x10)
   Field (EXTM, WordAcc, NoLock, Preserve)
   {
       ROM1,   16, 
       RMS1,   16, 
       ROM2,   16, 
       RMS2,   16, 
       ROM3,   16, 
       RMS3,   16, 
       AMEM,   32
   }

   OperationRegion (GP2C, SystemIO, 0x042C, 0x02)
   Field (GP2C, ByteAcc, NoLock, Preserve)
   {
       G2C1,   8, 
       G2C2,   8
   }

   OperationRegion (GBLE, SystemIO, 0x0421, One)
   Field (GBLE, ByteAcc, NoLock, Preserve)
   {
       ESMI,   8
   }

   OperationRegion (AGPS, SystemIO, 0x0438, 0x04)
   Field (AGPS, ByteAcc, NoLock, Preserve)
   {
       GPSE,   16, 
       GPSS,   16
   }

   OperationRegion (GPCN, SystemIO, 0x0442, One)
   Field (GPCN, ByteAcc, NoLock, Preserve)
   {
           ,   1, 
       SWGC,   1, 
               Offset (0x01)
   }

   OperationRegion (INFO, SystemMemory, 0x000FF840, One)
   Field (INFO, ByteAcc, NoLock, Preserve)
   {
       KBDI,   1, 
       RTCW,   1, 
       PS2F,   1, 
       IRFL,   2, 
       DISE,   1, 
       SSHU,   1
   }

   OperationRegion (GPIO, SystemIO, 0x0500, 0x41)
   Field (GPIO, ByteAcc, NoLock, Preserve)
   {
       GU00,   8, 
       GU01,   8, 
       GU02,   8, 
       GU03,   8, 
       GIO0,   8, 
       GIO1,   8, 
       GIO2,   8, 
       GIO3,   8, 
               Offset (0x0C), 
       GL00,   8, 
       GL01,   8, 
       GL02,   8, 
       GL03,   8, 
               Offset (0x18), 
       GB00,   8, 
       GB01,   8, 
       GB02,   8, 
       GB03,   8, 
               Offset (0x2C), 
       GIV0,   8, 
       GIV1,   7, 
       GI15,   1, 
       GIV2,   8, 
       GIV3,   8, 
       GU04,   8, 
       GU05,   8, 
       GU06,   8, 
       GU07,   8, 
       GIO4,   8, 
       GIO5,   8, 
       GIO6,   8, 
       GIO7,   8, 
       GL04,   8, 
       GL05,   8, 
       GL06,   8, 
       GL07,   8, 
       GO01,   8, 
       GO02,   8, 
       GO03,   8, 
       GO04,   8, 
       GO05,   8
   }

   OperationRegion (BSKU, SystemMemory, 0xFFBC0100, One)
   Field (BSKU, ByteAcc, NoLock, Preserve)
   {
           ,   1, 
       BPHP,   3, 
               Offset (0x01)
   }

   OperationRegion (GPE0, SystemIO, 0x042C, 0x04)
   Field (GPE0, ByteAcc, NoLock, Preserve)
   {
           ,   1, 
       GPEH,   1, 
           ,   7, 
       PEEN,   1, 
           ,   1, 
       PMEE,   1, 
               Offset (0x03), 
       PCIX,   1, 
               Offset (0x04)
   }

   OperationRegion (PMIO, SystemIO, 0x0400, 0x80)
   Field (PMIO, ByteAcc, NoLock, Preserve)
   {
               Offset (0x02), 
           ,   10, 
       RTEE,   1, 
               Offset (0x04), 
               Offset (0x20), 
           ,   2, 
       SPST,   1, 
           ,   28, 
       GPF,    1, 
               Offset (0x42), 
           ,   1, 
       GPEC,   1
   }

   [b][color="#ff0000"]Alias (\_PR.CPU1.PDC0, PDC0)
   Alias (\_PR.CPU2.PDC1, PDC1)
   Alias (\_PR.CPU3.PDC2, PDC2)
   Alias (\_PR.CPU4.PDC3, PDC3)
[/color][/b]
     Method (G3HT, 0, NotSerialized)
   {
       If (LOr (LEqual (RTEE, One), LEqual (\_SB.PCI0.LPCB.AG3E, Zero)))
       {
           Store (Zero, \_SB.PCI0.LPCB.EC.G3HT)
       }
       Else
       {
           Store (One, \_SB.PCI0.LPCB.EC.G3HT)
       }
   }

   Method (PNOT, 0, Serialized)
   {
       If (And (\_PR.PDC0, 0x08))
       {
           Notify (\_PR.CPU0, 0x80)
           If (And (\_PR.PDC0, 0x18))
           {
               Sleep (0x64)
               Notify (\_PR.CPU0, 0x81)
           }
       }

       If (And (\_PR.PDC1, 0x08))
       {
           Notify (\_PR.CPU1, 0x80)

and get

/Users/Dave/Desktop/dsdt24-10-09.dsl   506:     Alias (\_PR.CPU0.PDC0, PDC0)
Error    4064 -       Object not found or not accessible from scope ^  (PDC0)

keeza · October 25, 2009

Sorry to have to ask help here but stuck on 1 compilation error after adding SMBus to my dsdt.

Its probably very simple to fix but I cant find the error.

Could someone have a look for me - I've clearly annotated my changes/additions.

Thank you, then I can move on.

SBUS_DSDT.zip

Master Chief · October 25, 2009

Thanks for this - I've added device id's for UHCI and SATA - it works bar p-states !

**EDIT** 3 pstates listed just stuck at multi 8

MC - I've added alias so:

    Scope (_PR)
   {
       Processor (CPU0, 0x00, 0x00000410, 0x06) {}
       Processor (CPU1, 0x01, 0x00000410, 0x06) {}
       Processor (CPU2, 0x02, 0x00000410, 0x06) {}
       Processor (CPU3, 0x03, 0x00000410, 0x06) {}
Name (CFGD, 0x040383F2)
       Name (PDC0, 0x80000000)
       Name (PDC1, 0x80000000)
       Name (PDC2, 0x80000000)
       Name (PDC3, 0x80000000)

   }

and get

/Users/Dave/Desktop/dsdt24-10-09.dsl   506:	 Alias (\_PR.CPU0.PDC0, PDC0)
Error	4064 -	   Object not found or not accessible from scope ^  (PDC0)

Scope issue! And this is also why I want this to be as simple as possible. Anyway. You first had PDC0 defined inside Processor definition block CPU0 – which is also a scope, and that was why I said to use:

Alias (\_PR.CPU0.PDC0, PDC0)

But now you moved it out of this scope again, and into _PR. Which is also a scope, but a different one. Now you'll have to use this instead:

Alias (\_PR.PDC0, PDC0)

Sorry to have to ask help here but stuck on 1 compilation error after adding SMBus to my dsdt.

Its probably very simple to fix but I cant find the error.

Could someone have a look for me - I've clearly annotated my changes/additions.

Thank you, then I can move on.

I'll give it a quick look. Before going to bed early for a change. And I did! But there's too much stuff in there that should first be removed (please don't copy parts from your SSDT into your DSDT).

mitch_de · October 25, 2009

  [size=1]Scope (_PR)
   {
       Name (CFGD, 0x040483F2)
       Processor (CPU0, 0x00, 0x00000410, 0x06)
       {
           OperationRegion (PMBL, SystemMemory, 0xDFEEED20, 0x03AB) // CpuPm SSDT table's location and length.
           Name ([color="#FF0000"]PDC0, 0x80000000[/color]) // Initialized by OSPM – [color="#FF0000"]value for CPU1 is different (bit 8 & 9 not set)[/color]. 
[color="#000080"]// ALL PCDx have same 0x80000000 , so i cant see different bit 8 & 9 !!!![/color]
           Name (HNDL, 0x80000000) // Mandatory handle – not used after initialization.
           Name (TBLD, 0x00000080) // Keeps track of Load() – only load PM table once.

           Method (_INI, 0, NotSerialized) // CpuPm table loader.
           {
               If (LNot (And (TBLD, One)))
               {
                   Or (TBLD, One, TBLD)
                   Load (PMBL, HNDL)
               }
           }
           Method (_CST, 0, NotSerialized) // Master Object.
           {
               If (And (PDC0, 0x18)) // Bits 8 & 9 indicate that CST data is available (not true for CPU0).
               {
                    Return (\_PR.CPU1._CST()) // Daisy chaining our Secondary _CST Object.
               }
               Else
               {
                   Return (Package (0x02)
                   {
                       One, // Number of C-State packages: 1
                       Package (0x04)
                       {
                           ResourceTemplate ()
                           {
                               Register (FFixedHW, 
                               0x00,               // Bit Width
                               0x00,               // Bit Offset
                               0x0000000000000000, // Address
                               ,)
                           }, 
                          [color="#FF0000"] One, // Type: C1 [color="#000080"]// why is that code not also used below ???[/color]
                           0x9D, // Latency: 157us (values higher than 156 prevent it from entering C2)
                           0x03E8 // Power: 1000mw[/color]
                       }
                   })
               }
           }
       }
       Processor (CPU1, 0x01, 0x00000410, 0x06)
       {
           Name ([color="#FF0000"]PDC1, 0x80000000[/color]) // Initialized by OSPM – value for CPU1 is different (bit 8 & 9 not set).
           Method (_CST, 0, NotSerialized) // Secondary Object.
           {
              // TODO: Kick ass and demo the C5 & C6 errors!   [color="#000080"] // what does this mean, how to look after CSate errors ?[/color]
                   Return (Package (0x04)
                   {
                       0x03, 
                       Package (0x04)
                       {
                           ResourceTemplate ()
                           {
                               Register (FFixedHW, 
                                   0x01,               // Bit Width
                                   0x02,               // Bit Offset
                                   0x0000000000000000, // Address
                                   0x01,               // Access Size
                                   )
                           },
                         One,    [color="#000080"]// above there was an change of that 157 mS thing, why not here too ?[/color]
                           [color="#FF0000"]  One,[/color]   [color="#000080"]// above is 0x9D ?![/color]
                           0x03E8
                       }, 
                       Package (0x04)
                       {
                           ResourceTemplate ()
                           {
                               Register (SystemIO, 
                                   0x08,               // Bit Width
                                   0x00,               // Bit Offset
                                   0x0000000000000[color="#FF0000"]814[/color], // Address      /[color="#000080"]/in my part here 414 ?![/color]
                                   ,)
                           },
                           0x02,
                           One,
                           0x01F4
                       }, 
                       Package (0x04)
                       {
                           ResourceTemplate ()
                           {
                               Register (SystemIO, 
                                   0x08,               // Bit Width
                                   0x00,               // Bit Offset
                                   0x0000000000000[color="#FF0000"]815[/color], // Address       /[color="#000080"]/in my part here 414 ?![/color]
                                   ,)
                           },
                           0x03,
                           0x11,
                           0xFA
                       }
                   })
           }
       }
       Processor (CPU2, 0x02, 0x00000410, 0x06)
       {
           Name ([color="#FF0000"]PDC2, 0x80000000[/color]) // Initialized by OSPM – value for CPU1 is different (bit 8 & 9 not set).
           Method (_CST, 0, NotSerialized)
           {
               Return (\_PR.CPU1._CST())
           }
       }
       Processor (CPU3, 0x03, 0x00000410, 0x06)
       {
           Name ([color="#FF0000"]PDC3, 0x80000000[/color]) // Initialized by OSPM – value for CPU1 is different (bit 8 & 9 not set).
           Method (_CST, 0, NotSerialized)
           {
               Return (\_PR.CPU1._CST())
           }
       }
   }[/size]

I always try to understand changes or comment of found dsdt parts here

So i have some question about that code above, posted new last day.

Question parts marked RED, my questions marked BLUE.

Until now i didnt have Cstate handling in usage by not loading AppleIntelCPU.kext.

please correct me if i am right with that, that CState handling is made by AppleIntelCPU.kext.

But my Pstates working as they should (C2D).

CState questions:

1. I remember that an other .kext (platformplugin ?) also has to do with CState management beside AppleIntelCPU.kext

And that platformplugin , so i remember is very hard to configure (trottling Ctstates, throttling gpu,....) for fitting Mac Modell, i have iMac5,1, because my C2D fitting better to that than on XEON CPU.

Has someone here using other MacModel that MacPro ?

Final question:

Is it really worth to do CState things if Pstates are working already ?

I cant see any benefits adding CState to already working Pstates.

Thanks

William Parker · October 25, 2009

Sorry to have to ask help here but stuck on 1 compilation error after adding SMBus to my dsdt.

Its probably very simple to fix but I cant find the error.

Could someone have a look for me - I've clearly annotated my changes/additions.

Thank you, then I can move on.

Hi keeza

Checked this one too.

First please remove devices you do not use - Floppy, UART (serial ports), Parallel Ports inc. ECP etc., PS2K keyboard, PS2K mouse. The DSDT is too big & a real Mac don't have any of these.

Now on line#6551 you renamed IOCM from PCI0.EXPL, but what is the same device doing there on line #6855 as PCI0.EXPL again? I believe we should have only one.

Still hunting for the 1 last error. Post the DSDT if you succeed in compiling please.

Thanks.

Great to have you back sloshing in the pond.

keeza · October 25, 2009

Scope issue! And this is also why I want this to be as simple as possible. Anyway. You first had PDC0 defined inside Processor definition block CPU0 �" which is also a scope, and that was why I said to use:
Alias (\_PR.CPU0.PDC0, PDC0)
But now you moved it out of this scope again, and into _PR. Which is also a scope, but a different one. Now you'll have to use this instead:
Alias (\_PR.PDC0, PDC0)
I'll give it a quick look. Before going to bed early for a change. And I did! But there's too much stuff in there that should first be removed (please don't copy parts from your SSDT into your DSDT).

Thanks MC,

I've chopped out a fair bit and used your (and mm67) most recent dsdt as a guide so comparison should be easy.

I still have the one error somewhere "unexpected end".

Thanks William for having a look, I've chopped out a lot with this version but the error is still lurking there somewhere

Its good to be back, had some relatives stay the last couple of days, she commandeered the study so couldn't get to my hack!! (gone now)

Thank you.

dsdt_with_SMBus.dsl.zip

mm67 · October 25, 2009

Until now i didnt have Cstate handling in usage by not loading AppleIntelCPU.kext.
please correct me if i am right with that, that CState handling is made by AppleIntelCPU.kext.

But my Pstates working as they should (C2D).

CState questions:

1. I remember that an other .kext (platformplugin ?) also has to do with CState management beside AppleIntelCPU.kext

And that platformplugin , so i remember is very hard to configure (trottling Ctstates, throttling gpu,....) for fitting Mac Modell, i have iMac5,1, because my C2D fitting better to that than on XEON CPU.

Has someone here using other MacModel that MacPro ?

Final question:

Is it really worth to do CState things if Pstates are working already ?

I cant see any benefits adding CState to already working Pstates.

Thanks

Using C-states alone result in almost same temperatures as using P - states & C - states. Using P-states alone make CPU run about 5 degrees warmer for me.

mitch_de · October 25, 2009

So, i took that questioned part of cpu0... (my post above) and changed a bit .

I have C2D E7300, OC by FSB 333 MHZ, but lowered Multi from 10 to 9.

That gives 4 Pstates (CPU has 5, but must be limited to 4 because only 6-9 are madeable, let 10* availbale would give to much OC=KP). I extracted the SSDT part of MY! BIOS and changed the Psates with Pstates Calulator to my CPU needs.

That worked already with voodoopwoer and Mark-i.

Now i tried to do that steppings without voodoopower / Mark-i and use insted AppleIntelCPU.kext with changes in IOPlatformFamily/ACPI Plugin. In that plugin there are all things configured which are: C-States, Pstates + GPU States. Main thing is, that the ModelName does

configure that ! I used iMac5,1 and added / changed all to that for my need. (Used some MacPro keys, some iMac keys).

I believe DSDT changes alone without looking for that configuartion of that plugin .plist with fitting Modelname/fitting CPU type maybe

an risk / not recommended. Also using Pstate (SSDT) dsdt of others without any changes is very risky !

Differences marked RED / commenst BLUE.

Pstates works with that way (AppleIntelCPU + IOPlatformFamlily / Acpi... config) without voodoopower or Mark-i now.

I dont know how can i also check if C-States are used to.

CON:

I can see that the way of AppleIntelCPU trottles the Pstates is a bit more for powersaving.

Voodoopower or Mark-i does same but can be configured that the systems stays fast (Finder / Window movings). I feel with that way a bit slower response, because AppleIntelCPU speeds later up, means needs more cpu load % to switch to higher Mhz. AppleIntelCPU does wait around for 35%+ load to switch to more MHz. For me a bit too late.

Also i cant see any benefit by that "slowing down" in cpu temp. Ist really same temp as with voodoo / mark-i - sure also using same pstate, but faster switching to more MHZ.

Conclusion:

I would say that getting Pstates working with AppleIIntelCU should not be the main thing here. "More Mac like" can be worst than

using voodoopower or Mark-i. Both are doing same but not with the side effect of a bit to much powersaving (slower MHz up).

If someone can tell where i can configure that stepping (SAVE ! ) that would be of corse better than using extra voodoopower / mark.i.

I attatched the .plist of the IO...

Looks now:

[size=1]{
   Scope (_PR)
   {
       Processor (CPU0, 0x00, 0x00000410, 0x06) {}
       Processor (CPU1, 0x01, 0x00000410, 0x06) {}
       Processor (CPU2, 0x02, 0x00000410, 0x06) {}
       Processor (CPU3, 0x03, 0x00000410, 0x06) {}
   }
   Scope (\)
   {
       Name (SSDT, Package (0x18)
       {
           "CPU0IST ",      
           0xDFEE7F00, 
           0x026C, 
           "CPU1IST ", 
           0xDFEE83C0, 
           0x0152, 
           "CPU0CST ", 
           Zero, 
           0xF000E816, 
           "CPU1CST ", 
           Zero, 
           0xF000E816, 
           "CPU2IST ", 
           Zero, 
           0xF000E816, 
           "CPU3IST ", 
           Zero, 
           0xF000E816, 
           "CPU2CST ", 
           Zero, 
           0xF000E816, 
           "CPU3CST ", 
           Zero, 
           0xF000E816
       })
       Name (CFGD, 0x02030302)
       Name (PDC0, 0x80000000)
       Name (PDC1, 0x80000000)
       Name (PDC2, 0x80000000)
       Name (PDC3, 0x80000000)
   }
   Scope (_PR.CPU0)
   {
       Name (HI0, Zero)
       Name (HC0, Zero)
       Name (TLD0, Zero)
       Method (_PDC, 1, NotSerialized)
       {
           If (LEqual (TLD0, Zero))
           {
               CreateDWordField (Arg0, 0x08, CAP0)
               Store (CAP0, PDC0)
               If (LEqual (And (PDC0, 0x09), 0x09))
               {
                   If (And (CFGD, 0x02))
                   {
                       OperationRegion (IST0, SystemMemory, DerefOf (Index (SSDT, One)), DerefOf (Index (SSDT, 0x02
                           )))
                       Load (IST0, HI0)
                   }

                   Store (One, TLD0)
               }
           }
       }
       Name (_PSS, Package (0x04)   [color="#000080"]// my C2D is limited to 4 Pstates, multi 6 to 9 (10 must be disabled by my FSB OC!)[/color]
       {
           Package (0x06)
           {
               0x0BB5, 
               0x00013A97,  [color="#000080"]// 2997 MHZ = 9 * 333[/color]
               0x0A, 
               0x0A, 
               0x0921,  [color="#000080"]// Pstate 0=multi 9*  , VID 21=1239mV[/color]
               0x0921
           }, 

           Package (0x06)
           {
               0x0A68, 
               0x00010A18, [color="#000080"]// 2667 MHz[/color]
               0x0A, 
               0x0A, 
               0x081D,  [color="#000080"]//  Pstate 1=multi 8*,  VID 1D=1179mV[/color]
               0x081D
           }, 
           Package (0x06)
           {
               0x091B, 
               0xDCFB,   [color="#000080"]//2331 MHz[/color]
               0x0A, 
               0x0A, 
               0x071A,  [color="#000080"]//  Pstate 2=multi 7*, VID 1D=1119mV[/color]
               0x071A
           }, 

           Package (0x06)
           {
               0x07CE, 
               0xB341,  [color="#000080"] //1998 MHz  [/color]
               0x0A, 
               0x0A, 
               0x0616, [color="#000080"]//  Pstate 3=multi 6*, VID 1D=1059mV[/color]
               0x0616  
           }
       })
       Method (_CST, 0, NotSerialized)
       {
           If (And (PDC0, 0x18))
           {
               Return (^^CPU1._CST ())
           }
           Else
           {
               Return (Package (0x02)
               {
                   One, 
                   Package (0x04)
                   {
                       ResourceTemplate ()
                       {
                           Register (FFixedHW, 
                               0x00,               // Bit Width
                               0x00,               // Bit Offset
                               0x0000000000000000, // Address
                               ,)
                       }, 

                       One, // Type: C1 
                           0x9D, // Latency: 157us (values higher than 156 prevent it from entering C2)
                           0x03E8 // Power: 1000mw
                   }
               })
           }
       }
   }
   Scope (_PR.CPU1)
   {
       Name (HI1, Zero)
       Name (HC1, Zero)
       Name (TLD1, Zero)
       Method (_PDC, 1, NotSerialized)
       {
           If (LEqual (TLD1, Zero))
           {
               CreateDWordField (Arg0, 0x08, CAP1)
               Store (CAP1, PDC1)
               If (LEqual (And (PDC1, 0x09), 0x09))
               {
                   If (And (CFGD, 0x02))
                   {
                       OperationRegion (IST1, SystemMemory, DerefOf (Index (SSDT, 0x04)), DerefOf (Index (SSDT, 0x05
                           )))
                       Load (IST1, HI1)
                   }

                   Store (One, TLD1)
               }
           }
       }
       Method (_CST, 0, NotSerialized)
       {
           Return (Package (0x04)
           {
               0x03, 
               Package (0x04)
               {
                   ResourceTemplate ()
                   {
                       Register (FFixedHW, 
                           0x01,               // Bit Width
                           0x02,               // Bit Offset
                           0x0000000000000000, // Address
                           0x01,               // Access Size
                           )
                   }, 

                [color="#FF0000"]  One, // Type: C1 
                           0x9D, // Latency: 157us (values higher than 156 prevent it from entering C2)
                           0x03E8 // Power: 1000mw[/color]
               }, 

               Package (0x04)
               {
                   ResourceTemplate ()
                   {
                       Register (SystemIO, 
                           0x08,               // Bit Width
                           0x00,               // Bit Offset
                           0x0000000000000[color="#FF0000"]414[/color], // Address
                           ,)
                   }, 

                   0x02, 
                   One, 
                   0x01F4
               }, 

               Package (0x04)
               {
                   ResourceTemplate ()
                   {
                       Register (SystemIO, 
                           0x08,               // Bit Width
                           0x00,               // Bit Offset
                           0x0000000000000[color="#FF0000"]415[/color], // Address
                           ,)
                   }, 

                   0x03, 
                   0x55, 
                   0xFA
               }
           })
       }
   }

   Scope (_PR.CPU2)
   {
       Name (HI2, Zero)
       Name (HC2, Zero)
       Name (TLD2, Zero)
       Method (_PDC, 1, NotSerialized)
       {
           If (LEqual (TLD2, Zero))
           {
               CreateDWordField (Arg0, 0x08, CAP2)
               Store (CAP2, PDC2)
               If (LEqual (And (PDC2, 0x09), 0x09))
               {
                   If (And (CFGD, 0x02))
                   {
                       OperationRegion (IST2, SystemMemory, DerefOf (Index (SSDT, 0x0D)), DerefOf (Index (SSDT, 0x0E
                           )))
                       Load (IST2, HI2)
                   }

                   Store (One, TLD2)
               }
           }
       }

       Method (_CST, 0, NotSerialized)
       {
           Return (^^CPU1._CST ())
       }
   }

   Scope (_PR.CPU3)
   {
       Name (HI3, Zero)
       Name (HC3, Zero)
       Name (TLD3, Zero)
       Method (_PDC, 1, NotSerialized)
       {
           CreateDWordField (Arg0, 0x08, CAP3)
           Store (CAP3, PDC3)
           If (LEqual (TLD3, Zero))
           {
               If (LEqual (And (PDC3, 0x09), 0x09))
               {
                   If (And (CFGD, 0x02))
                   {
                       OperationRegion (IST3, SystemMemory, DerefOf (Index (SSDT, 0x10)), DerefOf (Index (SSDT, 0x11
                           )))
                       Load (IST3, HI3)
                   }

                   Store (One, TLD3)
               }
           }
       }

       Method (_CST, 0, NotSerialized)
       {
           Return (^^CPU1._CST ())
       }
   }[/size]

Info.plist.zip

Matthew L. · October 25, 2009

You already have Method PNOT () and the callers in Method _WAK and _Q80 so what makes you think that it ain't working for you? I might have missed "it" but care to explain this to me?
[...]

So, the problem starts at PDCs. You said I've turned my _PR scope into a worse one, from my 'most perfect' one. (See your post #141 in this thread.) Then if I want to change it back to the good one, I have to add 3 more PDCs, namely PDC1, PDC2 and PDC3 (which aren't defined, because you defined only one when writing that 'most perfect' _PR scope for me, PDC0), because PNOT checks 4 PDCs, not only 1. So that's where the question starts: just remove all other PDC statements in PNOT, or remove the PNOT method itself, or what is the solution in this case? (I've sent you my wild guess in a PM.)

FKA · October 25, 2009

p-state still stuck at max multi with cpu Alias added !

Also noticed PCI devices are no longer listed in system profiler with SBUS device added?

Sorry to be awkward!

D

If someone can tell where i can configure that stepping (SAVE ! ) that would be of corse better than using extra voodoopower / mark.i.

Hi mitch

what you are talking about - could it be latency timings?

Name (_PSS, Package (0x03)
       {
           Package (0x06)// P-State 0
           {
               3104, // f in MHz
               75000, // P in mW
               10, // Transition latency in us
               10, // Bus Master latency in us
               0x00000820, // value written to PERF_CTL; fid=8, vid=32
               0x00000820// value of PERF_STATE after successful transition; fid=8, vid=32
           },

D.

Master Chief · October 25, 2009

Thanks MC,

I've chopped out a fair bit and used your (and mm67) most recent dsdt as a guide so comparison should be easy.

I still have the one error somewhere "unexpected end"....

Its good to be back, had some relatives stay the last couple of days, she commandeered the study so couldn't get to my hack!! (gone now)

Thank you.

Right. Try this one (see attachments).

Note: You still need to include the latest patches.

<snip />

Question parts marked RED, my questions marked BLUE.

I am going to take a shortcut here – I have to – and point you to the DSDT Vanilla Speedstep thread. The reasons for this is simple, all answers can be found there already, and I am not willing to waste my time by reiterating each and every bit of info here again.

p.s. TODO is mine, as in a reminder to do something at a later stage.

So, the problem starts at PDCs. You said I've turned my _PR scope into a worse one, from my 'most perfect' one. (See your post #141 in this thread.) Then if I want to change it back to the good one, I have to add 3 more PDCs, namely PDC1, PDC2 and PDC3 (which aren't defined, because you defined only one when writing that 'most perfect' _PR scope for me, PDC0), because PNOT checks 4 PDCs, not only 1. So that's where the question starts: just remove all other PDC statements in PNOT, or remove the PNOT method itself, or what is the solution in this case? (I've sent you my wild guess in a PM.)

Ah. But I used TYPE remember? That's why you had to add an alias. However. CpuPm already declares PDC[0-3] so there is not need for it. Let's change your DSDT a bit to fix this. Here's what you have now (I think):

DefinitionBlock ("dsdt.aml", "DSDT", 1, "GBT   ", "GBTUACPI", 0x00001000)
{
Scope (_PR)
{
	Processor (CPU0, 0x00, 0x00000410, 0x06)
	{
		OperationRegion (PMBL, SystemMemory, 0x7FEE85A0, 0x03AB) // CpuPm SSDT table's location and length.
		[color="#FF0000"]Name (PDC0, 0x80000000) // Initialized by OSPM – value for CPU1 is different (bit 8 & 9 not set).[/color]
		Name (HNDL, 0x80000000) // Mandatory handle – not used after initialization.
		Name (TBLD, 0x00000080) // Keeps track of Load() – only load PM table once.

And I want you to change this into:

DefinitionBlock ("dsdt.aml", "DSDT", 1, "GBT   ", "GBTUACPI", 0x00001000)
{
[color="#FF0000"]External (PDC0)[/color]

Scope (_PR)
{
	Processor (CPU0, 0x00, 0x00000410, 0x06)
	{
		OperationRegion (PMBL, SystemMemory, 0x7FEE85A0, 0x03AB) // CpuPm SSDT table's location and length.
		Name (HNDL, 0x80000000) // Mandatory handle – not used after initialization.
		Name (TBLD, 0x00000080) // Keeps track of Load() – only load PM table once.

This way we are using the externally declared PDC0 – the one from CpuPm declared in the global namespace Scope (\) – which will be properly initialized by OSPM.

p-state still stuck at max multi with cpu Alias added !

I need to know what your CpuPm table includes (please attach it for me) since it might be different to what MatthewL's board et all are having.

Attachment for keeza below:

dsdtSMBus.dsl.zip

FKA · October 25, 2009

I need to know what your CpuPm table includes (please attach it for me) since it might be different to what MatthewL's board et all are having.

SSDT_r1_PmRef_CpuPm_3000_INTL_20040311.dsl.zip

pour favour!

is it possible that there is some other difference between GA EP35 DS4 and EP35 DS3 and EP45 DSDT's that would effect CPU PM? (I cant see any difference between EP35 DS3 and EP35 DS4!)

D.

Master Chief · October 25, 2009

SSDT_r1_PmRef_CpuPm_3000_INTL_20040311.dsl.zip
pour favour!

is it possible that there is some other difference between GA EP35 DS4 and EP35 DS3 and EP45 DSDT's that would effect CPU PM? (I cant see any difference between EP35 DS3 and EP35 DS4!)

D.

Merci. Formidable. Almost the same except for Name (CFGD, 0x04030302) versus Name (CFGD, 0x02030302) in MatthewL's copy. Seems like you guys can share the same PR scope, but fix that PDC0 issue by adding External (PDC0) at the top. Keep me posted.

mm67 · October 25, 2009

Merci. Formidable. Almost the same except for Name (CFGD, 0x04030302) versus Name (CFGD, 0x02030302) in MatthewL's copy. Seems like you guys can share the same PR scope, but fix that PDC0 issue by adding External (PDC0) at the top. Keep me posted.

Value of CFGD depends on C-state settings in bios.

C1 on : 0x04038302

C1 & C2 : 0x04038332

C1 & C2 & C4: 0x040383F2

C-states off : 0x04038302, but the Pm table gets a new base address.

Master Chief · October 25, 2009

Value of CFGD depends on C-state settings in bios.
C1 on : 0x04038302

C1 & C2 : 0x04038332

C1 & C2 & C4: 0x040383F2

C-states off : 0x04038302, but the Pm table gets a new base address.

Yes. The CFGD value depends on the C-State setting(s) in the BIOS, but I didn't knew that the table address also changed. Thanks.

Matthew L. · October 25, 2009

[...] CpuPm already declares PDC[0-3] so there is not need for it. Let's change your DSDT a bit to fix this. [...]

Exactly, Chief, that did the job! Defined PDCs 0-3 as external variables, and done!

Thanks a million, again! :unsure:

DSDT fixes for Gigabyte boards

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