Master Chief's P5K PRO ACPI Warfare

[kdawg]

Unfortunately not no (Asus is tight lip about it) but I do know that it is doing the same as what I did with:

Store (Sleep_State, SLPT)
Store (One, SLPE)

The other parts are most likely related to either fan control, power management, or both.

 

So you don't necessarily think this is the "key" to shutdown/restart? I'd like to try and simulate the patch on my Gigabyte board. I've posted your patch on the Gigabyte board so we'll see what happens. Unfortunately I'm art work right now because I think this is a big milestone. I want to give it a whirl.

[DB1]

Ok. Time for another update. Try this:

Method (_PTS, 1, NotSerialized) // Prepare To Sleep.
{
	\_SB.PCI0.LPCB.SPTS (Arg0)
	Store (Arg0, ASSB)

	If (LGreaterEqual (Arg0, 0x05))
	{
		Store (One, \_SB.PCI0.LPCB.AG3E)
	}

	\_SB.PCI0.SBUS.DISB ()
}

Next would be the one I am using. And while you're at it, remove this:

	Method (RRIO, 4, NotSerialized)
{
	Store ("RRIO", Debug)
}

Method (RDMA, 3, NotSerialized)
{
	Store ("rDMA", Debug)
}

And change this:

			Method (^BN00, 0, NotSerialized) // Can't we just return Zero?
		{
			Return (Zero)
		}

		Method (_BBN, 0, NotSerialized) // PCI bus number setup by the BIOS.
		{
			Return (BN00 ())
		}

into:

			Method (_BBN, 0, NotSerialized) // PCI bus number setup by the BIOS.
		{
			Return (Zero)
		}

These will also be gone in DSDT V3.2 along with 13K unused code.

 

OK, these work fine for me. Like the instantaneous shutdown!

 

I'll try your latest PTS now and report back.

 

	Method (_PTS, 1, NotSerialized)		  // Prepare To Sleep.
{
	If (LEqual (Arg0, 0x05))			 // S5 (shutdown).
	{
		Store (One, \_SB.PCI0.LPCB.AG3E) // Return to S5 after power failure.
	}
	Else								 // S1, S3 or S4 (S2 is not supported).
	{
		\_SB.PCI0.SBUS.DISB ()
		\_SB.PCI0.LPCB.SPTS ()
		Store (Arg0, ASSB)
	}
}

 

And this works for me fine also. Got the Too few arguments error on compile so changed the "Method (SPTS" to 0 from 1 and hey presto good to go & working sweet.

 

Thanks.

[Master Chief]

OK, these work fine for me. Like the instantaneous shutdown!

 

I'll try your latest PTS now and report back.

 

	... see post #404

 

And this works for me fine also. Got the Too few arguments error on compile so changed the "Method (SPTS" to 0 from 1 and hey presto good to go & working sweet.

 

Thanks.

Great. Now you are in par for the next set of changes

[DB1]

Great. Now you are in par for the next set of changes

 

Go for it

[THe KiNG]

According to my debug card, when shutdown stalls I get code: 05=S5

Tried to implement SPTS/SWAK on Apple DSDT but leads to not working shutdown

If I delete from SPTS Store (One, PS1S) and Store (One, PS1E) shutdown is fine...

 

Another weird stuff with original DSDT my debug card say that OS is in APIC mode(code AA) with Apple DSDT is in PIC mode(code AC)

I noticed that Restart after power fail feature is gone in 10.6.2, is the same on you guys or is just on me(removed something from DSDT)?

BTW Master Chief you didn't said what is with that server feature on power options.

[Master Chief]

So you don't necessarily think this is the "key" to shutdown/restart? I'd like to try and simulate the patch on my Gigabyte board. I've posted your patch on the Gigabyte board so we'll see what happens. Unfortunately I'm art work right now because I think this is a big milestone. I want to give it a whirl.

This isn't related to any kind of restart fix. Unfortunately not. Shutdown only. And most likely for Asus boards only.

 

BTW: I am still waiting for someone with a GB board to test the Asus BIOS table address, minus one, to see if that points to Sleep State bits, so please give it a go for me

[DB1]

I noticed that Restart after power fail feature is gone in 10.6.2, is the same on you guys or is just on me(removed something from DSDT)?

 

Can confirm this feature still in energy saver preferences for P5K VM 10.6.2.

[Master Chief]

According to my debug card, when shutdown stalls I get code: 05=S5

Nice. Might this be a post test card? Link?

 

Edit: Never mind. Found it. This is the Asus test card supplied by Asus with certain motherboards.

 

Tried to implement SPTS/SWAK on Apple DSDT but leads to not working shutdown If I delete from SPTS Store (One, PS1S) and Store (One, PS1E) shutdown is fine...

That means that Apple is doing things differently. Let me check this after my reply.

 

Another weird stuff with original DSDT my debug card say that OS is in APIC mode(code AA) with Apple DSDT is in PIC mode(code AC)

The card might be looking for something under a different name. There's nothing in the manual about it? They don't have a support forum for this card? I mean maybe you can ask it there.

 

I noticed that Restart after power fail feature is gone in 10.6.2, is the same on you guys or is just on me(removed something from DSDT)?

Not if you are talking about the: "Start up after a power failure" because that is still part of my Energy Saver panel.

 

BTW Master Chief you didn't said what is with that server feature on power options.

Oh right. Sorry. I copied SystemVersion.plist to ServerVersion.plist because I tried to install OS X 10.6 in VMware Fusion (which is what I use for EFI hacking) which works now with a simple script.

 

Edit: The upgrade to 10.6.2 completed without a hitch. Another swell Apple upgrade.

[THe KiNG]

That debug card comes with my board(P6T6 WS Revolution) is a TPM module.

 

About that codes AA/AC they come from _PIC method on original DSDT

 

Something is weird with P8XH method hmn...

[Master Chief]

That debug card comes with my board(P6T6 WS Revolution) is a TPM module.

 

About that codes AA/AC they come from _PIC method on original DSDT

 

Something is weird with P8XH method hmn...

I wouldn't be surprised when the Asus card simply reads PICM, especially since Method _PIC returns nothing, and this is Asus. You could add the one used in your Asus DSTD – which I presume is PICM – and see if that helps.

[Phoenix Wright]

Great. Now you are in par for the next set of changes

It works fine for me too, thanks

p.s. Please add a signature (My Control) because I don't know what hardware you are using, only after downloading the attached DSDT, which makes things a little more complicated for me. Thank you!

Done, sorry

[Master Chief]

It works fine for me too, thanks

 

Done, sorry

It is good to hear that other people are using it, and that it works for them... thank you for the confirmation and the newly added signature, but it is taking up quite a bit of vertical space. You may want to change it into 3-5 long lines. I mean think about the poor notebook users. Not to mention that I have to concentrate real hard before I can even read the green parts. Pretty distracting right now. Or are my old eyes losing it?

[Master Chief]

Here's the first part of the Asus BIOS table:

OperationRegion (BIOS, SystemMemory, 0xCFF8E064, 0xFF)
   Field (BIOS, ByteAcc, NoLock, Preserve)
   {
       SS1,    1,                                  // 0xCFF8E064 : bit 0 – Sleep State 1     (       0x1)
       SS2,    1,                                  // 0xCFF8E064 : bit 1 – Sleep State 2     (       0x0)
       SS3,    1,                                  // 0xCFF8E064 : bit 2 – Sleep State 3     (       0x1)
       SS4,    1,                                  // 0xCFF8E064 : bit 3 – Sleep State 4     (       0x1)
               Offset (0x01), 
       IOST,   16,                                 // 0xCFF8E065 : IO STate                  (    0x1400)
       TOPM,   32,                                 // 0xCFF8E067 : TOP of Memory             (0xD0000000)
       ROMS,   32,                                 // 0xCFF8E06B : ROM Space                 (0xFFF00000)
       MG1B,   32,                                 // 0xCFF8E06F : Memory Gap 1 Base Address (0x000D0000)
       MG1L,   32,                                 // 0xCFF8E073 : Length of Gap 1           (0x00010000)
       MG2B,   32,                                 // 0xCFF8E077 : Memory Gap 2 Base Address (0xD0000000)
       MG2L,   32,

This is my own, personal interpretation. Not officially documented information, and thus I might be wrong. We also no longer include TOPM and ROMS (wasn't used anyway) but IOST will also be gone in DSDT V3.2

 

The P5K Pro BIOS has one sleep setting, and the table below shows you how the sleep bits change, when you select one of the options:

 

1001 S1 (POS) only

1100 S3 only

1101 Auto

 

Next up: The IOST one, which is the only one I am uncertain about. Testing... doesn't seem to change. Is used in Device (FDC) and Device (UAR1) both connected via the Winbond Super IO Chip. Whatever. I removed these for the next update so who cares.

 

Note: I used reggie_se to get the values (for my board and BIOS settings).

[Master Chief]

Someone asked me why I use this:

Multiply (0x01FF, Arg0, URE2)

Instead of the old:

If (LEqual (Arg0, Zero))
{
Store (Zero, URE2) // Clear all bits.
}

If (LEqual (Arg0, One))
{
Store (0x01FF, URE2) // Set bits 0-8
}

And:

Alias (\_PR.CPU1._CST, _CST)

instead of:

Method (_CST, 0, NotSerialized)
{
Return (\_PR.CPU1._CST)
}

Which I think was a good question and thus here goes:

 

It isn't only shorter in terms of lines numbers, but also saves a few extra bytes in your dsdt.aml due to the fact that my code is highly optimized. The first one reduced the AML code by 15 bytes, and the latter by 4. And that for each time this was used! And thus I thought this to be worth the trouble.

[Volcacius]

Note: I used reggie_se to get the values (for my board and BIOS settings).

 

Hi Master Chief,

How did you got these values with reggie_se?

[Master Chief]

Hi Master Chief,

How did you got these values with reggie_se?

That was actually part of a previous post (#378) but here's the one to get the sleep byte:

 

sudo reggie_se -D PhysAddr -r -a 0xCFF8E064 -B 8

 

Note: Most other values in the BIOS table are 32 bit wide so you have to change the 8 in 32. And change the address of course

[BlackCH]

Got the Too few arguments error on compile so changed the "Method (SPTS" to 0 from 1 and hey presto good to go & working sweet.

 

do you mean like this?

 

 

Method (SPTS, 1, NotSerialized)

{

Store (Zero, PS1S) // Clear bit (by writing an 1 to it).

Store (Zero, PS1E) // Writes to the APMC register to cause an SMI#

}

[DB1]

do you mean like this?

 

 

Method (SPTS, 1, NotSerialized)

{

Store (Zero, PS1S) // Clear bit (by writing an 1 to it).

Store (Zero, PS1E) // Writes to the APMC register to cause an SMI#

}

 

No.

 

From

 Method (SPTS, 1, NotSerialized)

to

 Method (SPTS, 0, NotSerialized)

[Master Chief]

I am going to waste spent some time today trying to change this code snippet:

    Name (PRWP, Package (0x02)
   {
       Zero, 
       Zero
   })
   Method (GPRW, 2, NotSerialized)
   {
       Store (Arg0, Index (PRWP, Zero))
       Store (ShiftLeft (SS1, One), Local0)
       [color="#FF0000"]Or (Local0, ShiftLeft (SS2, 0x02), Local0)[/color]
       Or (Local0, ShiftLeft (SS3, 0x03), Local0)
       Or (Local0, ShiftLeft (SS4, 0x04), Local0)

       If (And (ShiftLeft (One, Arg1), Local0))
       {
           Store (Arg1, Index (PRWP, One))
       }
       Else
       {
           ShiftRight (Local0, One, Local0)
           FindSetLeftBit (Local0, Index (PRWP, One))
       }

       Return (PRWP)
   }

One of the reasons is that I looked at it a couple of times, and I keep wondering about the red line. I mean S2 isn't even supported on our Asus board so what is it doing there? Why add something when you, as developer, know that it is useless? A contractor getting payed by the line maybe?

 

Not to mention that this code is called up to 16 times at boot time (UHC[1-6], P0P[2-9], PCIB, EHCI and UHCI). 14 times minimum (without EHCI and UHCI). And all this bit shifting can be done with one single line. I think. What if I make it static? I mean it sure isn't going to change at run time. Does it? Nah. No way. Yeah. Let me give it a try. I like to burn my fingers on other peoples code...

 

This should work:

    Field (BIOS, ByteAcc, NoLock, Preserve)
   {
       SLPM,   8,
   }

   Name (SLPS, Zero)
   Name (PRWP, Package (0x02)
   {
       Zero, 
       Zero
   })

   Method (GPRW, 2, NotSerialized)
   {
       Store (Arg0, Index (PRWP, Zero))

       If (And (ShiftLeft (One, Arg1), SLPS))
       {
           Store (Arg1, Index (PRWP, One))
       }
       Else
       {
           FindSetLeftBit (SLPM, Index (PRWP, One)) 
       }

       Return (PRWP)
   }

At least it compiles. ACPI CA Debugger started... Oops. I forgot to add ShiftLeft (SLPM, One, SLPS) Method _PIC is my temporarily target for it. And now it works. I think. Testing... Done. It works.

 

Uhg. A mere four bytes smaller. Not exactly what I hoped for, but it wasn't my main concern. Boot speed is

 

And the names might change. Probably. Already done. BTW: The new Field (BIOS... should be put under your current one. Do not replace it with the new one! It's an addition to the current one, to get the byte value of the sleep state bits.

 

Note: This is an Asus specific change. Do not add Method (GPRW) when you don't already have one. However, every BIOS with Power Management (and sleep) settings should have something like this.

 

This change will also be part of DSDT V3.2

 

Right. Kids are home from school so daddy is going to have some quality time now. Later folks.

 

And as always... Happy Hacking!

[DB1]

And now it works. I think. Testing... Done. It works.

 

Works ok for me, thanks. V3.2 must be near.

 

Enjoy the QT.

[Master Chief]

Works ok for me, thanks. V3.2 must be near.

 

Enjoy the QT.

Thanks, and you are right. We're going to release DSDT V3.2 Saturday (in a few hours).

[Master Chief]

DSDT V3.2 has been released today – see attachments in post #3

 

The size of our previous update was:

dsdt.dsl 111.179 bytes

dsdt.aml 10.690 bytes

 

And todays update:

dsdt.dsl 95.260 bytes

dsdt.aml 7.957 bytes

 

A massive 25% off. Which makes it a rather significant update. With lots of new comments. Making the code reduction of dsdt.dsl even more impressive, since I have been adding so much spaces/text. Let's have a look at a few examples:

            Device (UHC1)                                      // Renamed from: USB0
           {
               Name (_ADR, 0x001D0000)
               Name (_PRW, Package (0x02)                     // Power Resources for Wake (ACPIspec30a.pdf / 7.2.10 / page 259).
               {
                   0x03, 
                   0x04
               })
               Name (_S3D, 0x02)                              // S3 Device State (ACPIspec30a.pdf / 7.2.15 / page 262).

               OperationRegion (BAR0, PCI_Config, 0xC4, One)  // Newly added: USB_RES—USB Resume Enable Register (ICH9R-3169722.pdf /16.1.24 / page 642).
               Field (BAR0, ByteAcc, NoLock, Preserve)
               {
                   USBW,   2, Offset (0x01)
               }

               Method (_PSW, 1, NotSerialized)                // Power State Wake (ACPIspec30a.pdf / 7.2.11 / page 260).
               {
                   Multiply (0x03, Arg0, USBW)                // Set bit 0-1 based on Arg0 (0 disable- or 1 enable wake capabilities).
               }

               Method (_DSM, 4, NotSerialized)                // Device Specific Method (ACPIspec30a.pdf / 9.15.1 / page 321).
               {
                   Return (MCID (Arg2, 0x3A34))
               }
           }

And this one:

            Device (P0P4)                                      // PCI Express Port 1
           {
               Name (_ADR, 0x001C0000)
               Name (_PRT, Package (0x04)                     // PCI Routing Table AR04 (ACPIspec30a.pdf / 6.2.11 / page 204).
               {
                   Package (0x04) { 0xFFFF, Zero, Zero, 0x10 },
                   Package (0x04) { 0xFFFF,  One, Zero, 0x11 },
                   Package (0x04) { 0xFFFF, 0x02, Zero, 0x12 },
                   Package (0x04) { 0xFFFF, 0x03, Zero, 0x13 }
               })
               Name (_PRW, Package (0x02)                     // Power Resources for Wake (ACPIspec30a.pdf / 7.2.10 / page 259).
               {
                   0x09, 
                   0x04
               })
           }

Again highly optimized – without going back in terms of readability – to squeeze out even the very last byte. And not a single change was done by 'trial and error' but after doing a lot more, additional, reading of the ACPI specification. Quite a few hours to be honest – I don't go change anything anymore without first knowing what it does / how it works.

 

And while I was working on code reduction of GPRW, which I have eliminated with this update, I realized to have made an error. That is why I moved the buffers out of Methods MCID and MCBN into the global name space, because this way we reduce the memory footprint. Yup. Learned something new again.

 

I also know that this update might be a little too much for some. A judgment error. Which is entirely my fault. And if DB1 hadn't mentioned a new release... it might have been Christmas by now. Yeah, I should have released an update earlier, but I didn't realize what I had done since V3.1. Well, just hang in, and feel free to ask for help. As long as it's you doing most of the work

 

Well. I think this covers it. And as always; Happy Hacking!

 

@julia24 & blackosx: Thank you!

[julia24]

Thank you!!!

[blackosx]

DSDT V3.2 has been released today – see attachments in post #3

Thanks MasterChief. I always use your latest DSDT's for reference to help with my learning

[BlackCH]

DSDT V3.2 has been released today �€“ see attachments in post #3

 

Thanks man!; I apreciate the work you're doing!

I brought my P5K-VM dsdt to match yours; everything seems to work good for me, except sleep-wake-restart sequence (which hangs at the point you should see the BIOS boot screen).

I got a question about:

 Method (_QCD, 0, NotSerialized) // Event CD.
				{
					If (CDIN)
					{
						Notify (\_SB.PCI0.SATA.PRT2, 0x81)
					}
					Else
					{
						Notify (\_SB.PCI0.SATA.PRT2, 0x82)
					}
				}

 

As I understand, this is to be able to auto-sleep your CD-DVD drive, isnt it? If so, would be possible to use the same kind of code to work in a drive hooked to the Jmicron IDE connector (present on the P5K-VM)?

 

I've tryed something like this:

Notify (\_SB.PCI0.P0P4.JMB0.IDE0, 0x81)

But didnt work so far...

 

 

A note for the P5K-VM:

One could delete the code for P0P devices addressed at 0x001C0001-3 as they dont appear in the IOReg, and probably they dont exist phisically either:

Nope, dont do it

 

 

Thanks again Chief. Awesome work!