Master Chief's P5K PRO ACPI Warfare

[Master Chief]

My motherboard is a P5Q pro so an ICH10

I add this code with the new methods ( MCID, MCBN and MCDP )

In My smbios.plist, it's better to used MacPro 4.1 or 3.1 ?

 

Barnum

Anything without a Nehalem CPU => Either MacPro3,1 or iMac9,1

 

And I know that you have a ICH10 on-board, but that doesn't matter. It's just to fix the yellow drive icons (without a kext). Hmm. Now that I think about it, that might in fact not (yet) work with your motherboard.

[barnum]

Ok thanks Chief,

 

it was just to be sure, I will let my smbios.plist with the macpro 3.1 information

 

Barnum

[bobby_rocks]

Hi Chief, or is it Master, both i suspect.

 

Many thanks for all you efforts, i've been reading for a while and finally decided to take the plunge......got most of it going with your dsdt and kexts but i'm one of those guys still running IDE DVD drives and i gave your dsdt patch a try.

 

Device (PATA) // Newly added PATA Device.

{

Name (_ADR, Zero)

 

Device (PRID) // CHN0 (default).

{

Name (_ADR, Zero)

}

 

Device (SECD) // CHN1 (default).

{

Name (_ADR, One)

}

}

needless to say, excellent work again and ioreg gives me this

 

| | +-o P0P8@1C,4 <class IOPCIDevice, id 0x10000016e, registered, matche$

| | | +-o IOPCI2PCIBridge <class IOPCI2PCIBridge, id 0x1000001b4, regist$

| | | +-o PATA@0 <class IOPCIDevice, id 0x10000016f, registered, match$

 

 

But thats as far as it goes and for the life of me i can't get any devices recognized, no matter what AppleVIAATA i manage to download, mangle or generally fudge up.

 

Did you manage to get it any PATA DVD drives working with this kext or only the LS120? and if so can you post the kext please?

[Master Chief]

Hi Chief, or is it Master, both i suspect.

 

Many thanks for all you efforts, i've been reading for a while and finally decided to take the plunge......got most of it going with your dsdt and kexts but i'm one of those guys still running IDE DVD drives and i gave your dsdt patch a try.

 

needless to say, excellent work again and ioreg gives me this

 

| | +-o P0P8@1C,4 <class IOPCIDevice, id 0x10000016e, registered, matche$

| | | +-o IOPCI2PCIBridge <class IOPCI2PCIBridge, id 0x1000001b4, regist$

| | | +-o PATA@0 <class IOPCIDevice, id 0x10000016f, registered, match$

 

 

But thats as far as it goes and for the life of me i can't get any devices recognized, no matter what AppleVIAATA i manage to download, mangle or generally fudge up.

 

Did you manage to get it any PATA DVD drives working with this kext or only the LS120? and if so can you post the kext please?

Just Chief is fine.

 

And I don't have a PATA DVD, but the link to the darwin-aka I used is now available in my other post. And the ioreg output you've added doesn't show any attached drives (no matching device-id in the kexts?) so there's indeed some more work to do on your side.

 

Edit: One of the reasons for adding the Device (PATA) was that I liked to know what the other P0Pn devices where used for. Another was to be able to change the device-id. Which I did, so that the original IOATAFamily.kext would load. And it did, but crashes at boot time. I might however get around it using a modified kext – I am using 4GB in my hack, and somehow remembered that to be a possible problem. Might need a (slightly) modified kext I think.

 

p.s. I hope to do some testing later today. Hopefully.

[ZGT]

Hi Master Chief

 

Do you have a plan to fix "FireWire runtime power conservation disabled. (2)"

[Master Chief]

Just to let you know: I am planning to add something like this for our next update:

    // New Method V1.3 – By Master Chief.
   Method (MCID, 2, NotSerialized)
   {
       If (Arg1) // Either a device-id like 0x2693 or a 32-bit combo like 0x269e8086 with both a device-id and a vendor-id.
       {
           Name (BUF0, Buffer (0x04) { Zero, Zero, Zero, Zero } )
           Store (And (Arg1, 0xFF), Index (BUF0, Zero))                         // 0x9e => BUF0 is now 0x9e 0x00 0x00 0x00
           Store (ShiftRight (And (Arg1, 0xFF00), 0x08), Index (BUF0, One))     // 0x2600 => 0x26 => BUF0 is now 0x9e 0x26 0x00 0x00

           If (LEqual (And (Arg1, 0xFFFF0000), Zero))
           {
               Store (Package (0x02)
               {
                   "device-id",
                   BUF0                                                         // 0x9e 0x26 0x00 0x00
               }, Local0)
           }
           Else
           {
               Name (BUF1, Buffer (0x04) { Zero, Zero, Zero, Zero } )           // BUF0 is now 0x86 0x80 0x00 0x00
               ShiftRight (Arg1, 0x10, Arg1)                                    // 0x269e0000 => 0x269e
               Store (And (Arg1, 0xFF), Index (BUF1, Zero))                     // 0x9e => BUF1 is now 0x9e 0x00 0x00 0x00
               Store (ShiftRight (And (Arg1, 0xFF00), 0x08), Index (BUF1, One)) // 0x2600 => 0x26 => BUF1 is now 0x9e 0x26 0x00 0x00
               Store (Package (0x04)
               {
                   "vendor-id",
                   BUF0,                                                        // 0x86 0x80 0x00 0x00
                   "device-id",
                   BUF1                                                         // 0x9e 0x26 0x00 0x00
               }, Local0)
           }

           MCDP (Arg0, RefOf (Local0))
           Return (Local0)
       }

       Return (Zero)
   }

With the usual (educational) comments. But I have yet to debug it in ACPICAexec (Intel developers environment used by Apple).

 

Hi Master Chief

 

Do you have a plan to fix "FireWire runtime power conservation disabled. (2)"

Right. I completely forgot about it. Sorry. I should make a TODO list with stuff I need to look at (at a later time).

[kdawg]

Hi Master Chief

 

Do you have a plan to fix "FireWire runtime power conservation disabled. (2)"

 

Perhaps I can help here. Under Scope (_GPE) I added:

		Method (_L1A, 0, NotSerialized) // <-- Added for firewire
	{
		Notify (\_SB.PCI0.PCIB.FRWR, 0x00)
		Notify (\_SB.PWRB, 0x02)
	}

 

Within the Device (PCIB) I added another device:

				Device (FRWR) // <--Firewire
			{
				Name (_ADR, 0x00070000)
				Name (_GPE, 0x1A)
				Method (_DSM, 4, NotSerialized)
				{
					Store (Package (0x02)
						{
							"fwhub", 
							Buffer (0x04)
							{
								0x00, 0x00, 0x00, 0x00
							}
						}, Local0)
					DTGP (Arg0, Arg1, Arg2, Arg3, RefOf (Local0))
					Return (Local0)
				}
			}

 

Keep in mind I have a Gigabyte board but I believe you can fix the problem using this exact method, the boards seem similar enough. Just verify the _ADR space in the FRWR Device. I've altered MC DSDT JUST AS AN EXAMPLE! I have no way of testing this so take it as a suggestion.

MC_dsdt_3.0.dsl.zip

[bobby_rocks]

Chief,

 

What a journey, tried pretty much everything (been learning hoe to mod kexts, didn't think you'd appreciate such a noob question)

 

Anywho, after much trial and error and error i got something working, unstable but working.

 

However, i found this forum topic AppleVIAATA over 4GB RAm solved on my travels and a new kext has been released SUPERVIAATA that deals with the 4GB mem issue and it works!! with the MArvell controller on our boards

 

Seems to to stable for now (i binned all the sata entries and just left the stuff for our board

 

<key>IOPCIPrimaryMatch</key>

<string>0x610111ab</string>

 

See what you think chief

[Master Chief]

Chief,

 

What a journey, tried pretty much everything (been learning hoe to mod kexts, didn't think you'd appreciate such a noob question)

 

Anywho, after much trial and error and error i got something working, unstable but working.

 

However, i found this forum topic AppleVIAATA over 4GB RAm solved on my travels and a new kext has been released SUPERVIAATA that deals with the 4GB mem issue and it works!! with the MArvell controller on our boards

 

Seems to to stable for now (i binned all the sata entries and just left the stuff for our board

 

<key>IOPCIPrimaryMatch</key>

<string>0x610111ab</string>

 

See what you think chief

Hi Bobby,

 

I had no trouble using the one linked to in post # 247 and went on trying to use a stock Apple kext by changing the device-id. And if it works for you, fine. I personally don't need it, but it sure is nice to see people having success from time to time. This instead of me talking all the time

[Master Chief]

Perhaps I can help here. Under Scope (_GPE) I added:

 

...

 

Keep in mind I have a Gigabyte board but I believe you can fix the problem using this exact method, the boards seem similar enough. Just verify the _ADR space in the FRWR Device. I've altered MC DSDT JUST AS AN EXAMPLE! I have no way of testing this so take it as a suggestion.

Correct. This is exactly what a Apple is using, and this is what I have:

			Method (_L18, 0, NotSerialized) // Newly added for FireWire support.
		{
			Notify (\_SB.PCI0.PCIB.FRWR, 0x00)
		}

In combination with the following code for my Asus P5K Pro:

                Device (FRWR) // Newly added device
               {
                   Name (_ADR, 0x00030000)
                   Name (_GPE, 0x18)

                   Method (_DSM, 4, NotSerialized)
                   {
                       Store (Package (0x02)
                       {
                           "fwhub",
                           Buffer (0x02)
                           {
                               0x00, 0x00, 0x00, 0x00
                           }
                       }, Local0)

                       MCDP (Arg2, RefOf (Local0))
                       Return (Local0)
                   }
               }

Starting with the new MCDP Method (less arguments) and a different address.

 

Note: Sometime people amaze me. I mean I may drop dead on the floor right now, if I haven't worked on this yesterday! I was however unable to locate the address of it, but now simply replaced the 7 with a 3 – knowing that it should be like that – et voila!

 

p.s. The FireWire device on a P5K Pro is normally represented by pci1106,3044@3 in ioreg / IORegistryExplorer and will change into FRWR@3 with the provided code.

 

Edit: I guess all that rest now is to see what is connected to P0P[4/5/6 and 7].

[kdawg]

Note: Sometime people amaze me. I mean I may drop dead on the floor right now, if I haven't worked on this yesterday! I was however unable to locate the address of it, but now simply replaced the 7 with a 3 – knowing that it should be like that – et voila!

 

p.s. The FireWire device on a P5K Pro is normally represented by pci1106,3044@3 in ioreg / IORegistryExplorer and will change into FRWR@3 with the provided code.

 

Edit: I guess all that rest now is to see what is connected to P0P[4/5/6 and 7].

 

Using lscpi.kext or something like the dated OSX86 tools app you can run LSCPI and get something like the following.

 

00:00.0 Host bridge [0600]: Intel Corporation Eaglelake DRAM Controller [8086:2e20] (rev 03)
00:01.0 PCI bridge [0604]: Intel Corporation Eaglelake PCI Express Root Port [8086:2e21] (rev 03)
00:06.0 PCI bridge [0604]: Intel Corporation Unknown device [8086:2e29] (rev 03)
00:1a.0 USB Controller [0c03]: Intel Corporation 82801JI (ICH10 Family) USB UHCI Controller #4 [8086:3a37]
00:1a.1 USB Controller [0c03]: Intel Corporation 82801JI (ICH10 Family) USB UHCI Controller #5 [8086:3a38]
00:1a.2 USB Controller [0c03]: Intel Corporation 82801JI (ICH10 Family) USB UHCI Controller #6 [8086:3a39]
00:1a.7 USB Controller [0c03]: Intel Corporation 82801JI (ICH10 Family) USB2 EHCI Controller #2 [8086:3a3c]
00:1b.0 Audio device [0403]: Intel Corporation 82801JI (ICH10 Family) HD Audio Controller [8086:3a3e]
00:1c.0 PCI bridge [0604]: Intel Corporation 82801JI (ICH10 Family) PCI Express Port 1 [8086:3a40]
00:1c.3 PCI bridge [0604]: Intel Corporation 82801JI (ICH10 Family) PCI Express Port 4 [8086:3a46]
00:1c.4 PCI bridge [0604]: Intel Corporation 82801JI (ICH10 Family) PCI Express Port 5 [8086:3a48]
00:1c.5 PCI bridge [0604]: Intel Corporation 82801JI (ICH10 Family) PCI Express Port 6 [8086:3a4a]
00:1d.0 USB Controller [0c03]: Intel Corporation 82801JI (ICH10 Family) USB UHCI Controller #1 [8086:3a34]
00:1d.1 USB Controller [0c03]: Intel Corporation 82801JI (ICH10 Family) USB UHCI Controller #2 [8086:3a35]
00:1d.2 USB Controller [0c03]: Intel Corporation 82801JI (ICH10 Family) USB UHCI Controller #3 [8086:3a36]
00:1d.7 USB Controller [0c03]: Intel Corporation 82801JI (ICH10 Family) USB2 EHCI Controller #1 [8086:3a3a]
00:1e.0 PCI bridge [0604]: Intel Corporation 82801 PCI Bridge [8086:244e] (rev 90)
00:1f.0 ISA bridge [0601]: Intel Corporation 82801JIR (ICH10R) LPC Interface Controller [8086:3a16]
00:1f.2 SATA controller [0106]: Intel Corporation 82801JI (ICH10 Family) SATA AHCI Controller [8086:3a22]
00:1f.3 SMBus [0c05]: Intel Corporation 82801JI (ICH10 Family) SMBus Controller [8086:3a30]
01:00.0 VGA compatible controller [0300]: nVidia Corporation GeForce 8800 GT [10de:0611] (rev a2)
02:00.0 VGA compatible controller [0300]: nVidia Corporation GeForce 8500 GT [10de:0421] (rev a1)
04:00.0 SATA controller [0106]: JMicron Technologies, Inc. JMicron 20360/20363 AHCI Controller [197b:2363] (rev 02)
04:00.1 IDE interface [0101]: JMicron Technologies, Inc. JMicron 20360/20363 AHCI Controller [197b:2363] (rev 02)
05:00.0 Ethernet controller [0200]: Realtek Semiconductor Co., Ltd. RTL8111/8168B PCI Express Gigabit Ethernet controller [10ec:8168] (rev 02)
06:00.0 Ethernet controller [0200]: Realtek Semiconductor Co., Ltd. RTL8111/8168B PCI Express Gigabit Ethernet controller [10ec:8168] (rev 02)
07:00.0 Network controller [0280]: Atheros Communications Inc. AR5416 802.11abgn Wireless PCI Adapter [168c:0023] (rev 01)
[b]07:07.0 FireWire (IEEE 1394) [0c00]: Texas Instruments TSB43AB23 IEEE-1394a-2000 Controller (PHY/Link) [104c:8024][/b]

 

Last entry is the Firewire. The _ADR is the middle entry of 07:07.0.

Anything else on POP 4-7 or any add on cards will be clearly visible. As you can see I also have two GFX cards and an airport card.

[bobby_rocks]

Chief,

 

It's been bugging me.......my bad, i was booting in 64bit mode and hence i needed the SUPERVIAATA 64bit compiled kext. In 32Bit mode, the one you linked to works, no problem. ahhhhh.

 

Still on to the DLINK DWA 547 card now. thanks for your help man even if i am a bit slow.

 

cheers

[Master Chief]

Using lscpi.kext or something like the dated OSX86 tools app you can run LSCPI and get something like the following.

 

...

 

Last entry is the Firewire. The _ADR is the middle entry of 07:07.0.

Anything else on POP 4-7 or any add on cards will be clearly visible. As you can see I also have two GFX cards and an airport card.

Thanks. I know about lspci -nn but the dumped info is static as it doesn't show the changed addresses – it probably reads the name instead of the ID itself. Yeah, that might actually be it. Let me check that for my changed SATA (now 2681).

 

I also got used to using IORegistryExplorer, this despite the persist problem, because I know that @3 equals 0x00030000. The thing is that I copied that block from my good old Mac Pro 3,1 DSDT and put it right outside of the PCIB scope, right over over the closing } of it. That was why it didn't work the other day. I happen to learn a lot from my own failures you know

 

And the note about the P0Pn ports was for other people, since I don't really use my hack for anything but fun.

 

@bobby_rocks: Thanks for the heads up and good luck with the DLINK.

[ZGT]

thanks a lot !

I will test it !

[bobby_rocks]

Chief,

 

DLINK DWA-547 flawless in 32bit.

 

However, I have added another SATA HDD to my rig and i can see it is OSX when booted but can not see it with Standard Chameleon RC3. I'd like to install Sl on it.

 

Running Disk Utility from SL Retail Install it just beachballs! . I have created custom P5K Pro boot Cd with my dsdt and kexts but still no luck.

 

I remember you saying that you has issues with Chameleon and a HDD you were using, what was the possible cause and or solution?

 

HDD is Maxtor 6B200M0 (it is SATA but 150 not 300) possible issue?

 

 

Bobby

[ZGT]

Correct. This is exactly what a Apple is using, and this is what I have:

			Method (_L18, 0, NotSerialized) // Newly added for FireWire support.
		{
			Notify (\_SB.PCI0.PCIB.FRWR, 0x00)
		}

In combination with the following code for my Asus P5K Pro:

                Device (FRWR) // Newly added device
               {
                   Name (_ADR, 0x00030000)
                   Name (_GPE, 0x18)

                   Method (_DSM, 4, NotSerialized)
                   {
                       Store (Package (0x02)
                       {
                           "fwhub",
                           Buffer (0x02)
                           {
                               0x00, 0x00, 0x00, 0x00
                           }
                       }, Local0)

                       MCDP (Arg2, RefOf (Local0))
                       Return (Local0)
                   }
               }

Starting with the new MCDP Method (less arguments) and a different address.

 

Note: Sometime people amaze me. I mean I may drop dead on the floor right now, if I haven't worked on this yesterday! I was however unable to locate the address of it, but now simply replaced the 7 with a 3 – knowing that it should be like that – et voila!

 

p.s. The FireWire device on a P5K Pro is normally represented by pci1106,3044@3 in ioreg / IORegistryExplorer and will change into FRWR@3 with the provided code.

 

Edit: I guess all that rest now is to see what is connected to P0P[4/5/6 and 7].

 

 

"MCDP" is not exist,I can not production the *.aml.(in dsdt.aml 3.0)

 

Iike "DTGP (Arg0, Arg1, Arg2, Arg3, RefOf (Local0))"

I get dsdt.aml,(Compilation complete. 0 Errors, 0 Warnings, 0 Remarks, 97 Optimizations.),BUT the "FireWire runtime power conservation disabled. (2)" still.............

 

Sorry,My level is limited。

[DB1]

"MCDP" is not exist,I can not production the *.aml.(in dsdt.aml 3.0)

 

Iike "DTGP (Arg0, Arg1, Arg2, Arg3, RefOf (Local0))"

I get dsdt.aml,(Compilation complete. 0 Errors, 0 Warnings, 0 Remarks, 97 Optimizations.),BUT the "FireWire runtime power conservation disabled. (2)" still.............

 

Sorry,My level is limited。

 

Need to read post 214 and others just prior where it explains DTGP replacement by the MCDP method. This is a post V3.0 refinement that will likely appear in V3.1.

 

General note for newcomers to the thread is that you must read through rather than just pick a fix and drop in your own dsdt as invariably it wont work.

 

@MasterChief - maybe were ready for V3.1?

[kdawg]

"MCDP" is not exist,I can not production the *.aml.(in dsdt.aml 3.0)

 

Iike "DTGP (Arg0, Arg1, Arg2, Arg3, RefOf (Local0))"

I get dsdt.aml,(Compilation complete. 0 Errors, 0 Warnings, 0 Remarks, 97 Optimizations.),BUT the "FireWire runtime power conservation disabled. (2)" still.............

 

Sorry,My level is limited。

 

MCDP is Master Chief's own homebrew method thats why it doesnt work for you have have to add it. If you want to use DTGP then it would look like so

 

Add this into the _GPE method:

		Method (_L18, 0, NotSerialized) // <-- Added for firewire
	{
		Notify (\_SB.PCI0.PCIB.FRWR, 0x00)
	}

 

 

Add this into the PCIB device

				Device (FRWR) // <--Firewire
			{
				Name (_ADR, 0x00030000) //<-- MC revisions
				Name (_GPE, 0x18)
				Method (_DSM, 4, NotSerialized)
				{
					Store (Package (0x02)
						{
							"fwhub", 
							Buffer (0x04)
							{
								0x00, 0x00, 0x00, 0x00
							}
						}, Local0)
					DTGP (Arg0, Arg1, Arg2, Arg3, RefOf (Local0))
					Return (Local0)
				}
			}

Need to read post 214 and others just prior where it explains DTGP replacement by the MCDP method. This is a post V3.0 refinement that will likely appear in V3.1.

 

General note for newcomers to the thread is that you must read through rather than just pick a fix and drop in your own dsdt as invariably it wont work.

 

@MasterChief - maybe were ready for V3.1?

DB1 is right users need to do a bit more research before asking otherwise you'll have no idea what you're doing. Someone should write a DSDT (ACPI) tutorial for dummies. For those interested in the spec this is worth having in your library.

ACPISpec4.0

[ZGT]

MCDP is Master Chief's own homebrew method thats why it doesnt work for you have have to add it. If you want to use DTGP then it would look like so

 

Add this into the _GPE method:

		Method (_L18, 0, NotSerialized) // <-- Added for firewire
	{
		Notify (\_SB.PCI0.PCIB.FRWR, 0x00)
	}

 

 

Add this into the PCIB device

				Device (FRWR) // <--Firewire
			{
				Name (_ADR, 0x00030000) //<-- MC revisions
				Name (_GPE, 0x18)
				Method (_DSM, 4, NotSerialized)
				{
					Store (Package (0x02)
						{
							"fwhub", 
							Buffer (0x04)
							{
								0x00, 0x00, 0x00, 0x00
							}
						}, Local0)
					DTGP (Arg0, Arg1, Arg2, Arg3, RefOf (Local0))
					Return (Local0)
				}
			}

 

DB1 is right users need to do a bit more research before asking otherwise you'll have no idea what you're doing. Someone should write a DSDT (ACPI) tutorial for dummies. For those interested in the spec this is worth having in your library.

ACPISpec4.0

 

 

 

Thanks you to be able to pay attention to this question and your reply.I already do it such you said.But it still.

 

Need to read post 214 and others just prior where it explains DTGP replacement by the MCDP method. This is a post V3.0 refinement that will likely appear in V3.1.

 

General note for newcomers to the thread is that you must read through rather than just pick a fix and drop in your own dsdt as invariably it wont work.

 

@MasterChief - maybe were ready for V3.1?

 

I always cannot complete it..........

[Master Chief]

DSDT V3.1 Has Been Released Today – see attachments in post#3

 

Time for another update. Time for DSDT V3.1 So what have you been doing for this release Chief? Well. Let's see:

 

1) Stripped Device (SATA) to a bare minimum.

2) Added Device (PATA) for IDE hardware.

3) Added Device (FRWR) for FireWire hardware.

4) New Method (MCID) added.

5) New Method (MCBN) added.

6) New Method (MCDP) added.

7) Removed Method (DTGP)

- replaced with the new Method (MCDP) which uses fewer arguments.

8) Added Device (GFX0)

- a placeholder for graphics cards.

9) The UHCn devices are now using MCID to change the device-id.

- Broken in previous version(s) due to my use of a hacked com.apple.Boot.plist

10) And as usual, a lot new comments – hopefully to help you understand things better.

 

Notes: People who do happen to use Method MCID already, should check if they are using the latest version (Version 1.3) which now supports device-id with MCID (Arg2, 0x2681) as well as both device-id and vendor-id by using MCID (Arg2, 0x26818086).

 

P5K Pro users can simple use the provided dsdt.dsl as their starting point. Simply copy your HDEF/GFX Devices into the provided dsdt.dsl and compile it. There's really no need to re-invent the wheel, other than maybe trying to learn something new.

 

@DB1: I think this covers it

 

Happy Hacking!

[DB1]

DSDT V3.1 Has Been Released Today

 

Time for another update. Time for DSDT V3.1 So what have you been doing for this release Chief? Well. Let's see:

 

1) Stripped Device (SATA) to a bare minimum.

2) Added Device (PATA) for IDE hardware.

3) Added Device (FRWR) for FireWire hardware.

4) New Method (MCID) added.

5) New Method (MCBN) added.

6) New Method (MCDP) added.

7) Removed Method (DTGP)

- replaced with the new Method (MCDP) which uses fewer arguments.

8) Added Device (GFX0)

- a placeholder for graphics cards.

9) The UHCn devices are now using MCID to change the device-id.

- Broken in previous version(s) due to my use of a hacked com.apple.Boot.plist

10) And as usual, a lot new comments – hopefully to help you understand things better.

 

Notes: People who do happen to use Method MCID already, should check if they are using the latest version (Version 1.3) which now supports device-id with MCID (Arg2, 0x2681) as well as both device-id and vendor-id by using MCID (Arg2, 0x26818086).

 

@DB1: I think this covers it

 

And some! Many thanks, up and running well on P5k VM - except sleep not solved yet, but I'm working on it Sleep solved, just restart to sort :-)

[Master Chief]

Blimey. I guess that adding Device (SBUS) wasn't such a bad idea after all. I mean the great n00b caller – pardon the pun – now also recommends it. Well well. I guess someone noticed that there was at least one error less at boot time. No word about thanks, but whatever. I'm too big for little stuff like this. Let's move forward in a positive way and provide him a bit of useful info, because that's what I am. A nice guy:

            Device (SBUS)                                              // Newly added Device.
           {
               Name (_ADR, 0x001F0003)

               Method (_DSM, 4, NotSerialized)                        // Change device-id from pci8086,2930 to pci8086,3a30
               {
                   Store (Package (0x04)
                   {
                       "name",
                       "pci8086,3a30",

                       "device-id", 
                       Buffer (0x04)
                       {
                           0x30, 0x3a, 0x00, 0x00
                       }
                   }, Local0)
                   MCDP (Arg2, RefOf (Local0))
                   Return (Local0)
               }

               OperationRegion (SMBP, PCI_Config, 0x40, 0xC0)         // Host Configuration Register (ICH9R-316972.pdf / 19.1.16 / page 757).
               Field (SMBP, DWordAcc, NoLock, Preserve)
               {
                       ,   2, 
                   I2CE,   1
               }

               OperationRegion (SMBE, PCI_Config, 0x04, 0x02)         // PCI Command Register (ICH9R-316972.pdf / 19.1.3 / page 752).
               Field (SMBE, AnyAcc, NoLock, Preserve)
               {
                   IOSE,   1
               }

               OperationRegion (SMBI, SystemIO, 0x4000, 0x10)         // SMBus I/O and Memory Mapped I/O Registers (ICH9R-316972.pdf / 19.2 / page 758).
               Field (SMBI, ByteAcc, NoLock, Preserve)
               {
                   HSTS,   8,                                         // Host Status.
                           Offset (0x02), 
                   HCON,   8,                                         // Host Control.
                   HCOM,   8,                                         // Host Command.
                   TXSA,   8,                                         // Transmit Slave Address.
                   DAT0,   8,                                         // Host Data 0.
                   DAT1,   8,                                         // Host Data 1.
                   HBDR,   8,                                         // Host Block Data Register (Byte).
                   PECR,   8,                                         // Packet Error Check Register.
                   RXSA,   8,                                         // Receive Slave Address.
                   SDAT,   16                                         // Receive Slave Data.
               }

               Name (SBOK, 0x00)
               Method (ENAB, 0, NotSerialized)
               {
                   Store (One, IOSE)                                  // Enabled to communicate with I2C devices.
                   Store (One, SBOK)                                  // Activated.
               }

               Method (DISB, 0, NotSerialized)
               {
                   Store (Zero, SBOK)                                 // Disabled.
               }

               Method (SSXB, 2, Serialized)                           // ASUS Method (SBYT)
               {
                   If (STRT ())                                       // Ready?
                   {
                       Store (Zero, I2CE)                             // 
                       Store (0xBF, HSTS)                             // Clear Host Status Register, with the exception of bit-6 (INUSE_STS).
                       Store (Arg0, TXSA)                             // This is a write command (bit 1-7 is the address of the targeted device).
                       Store (Arg1, HCOM)                             // Forward Command.
                       Store (0x48, HCON)                             // Bit-6 (40) represents the start bit and bits 4:2 the command type:
[color="#FF0000"]                                                                       // 0x40 = 01000000 - Quick.
                                                                      // 0x44 = 01000100 - Byte.
                                                                      // 0x48 = 01001000 - Byte Data.
                                                                      // 0x4C = 01001100 - Word Data.
                                                                      // 0x50 = 01000000 - Process Call.
                                                                      // 0x54 = 01010100 - Block.
                                                                      // 0x58 = 01011000 - I2C Read.
                                                                      // 0x5C = 01011100 - Block Process.[/color]
                       If (COMP ())                                   // Error checking – Successful completion of command?
                       {
                           Or (HSTS, 0xFF, HSTS)                      // Clear Host Status Register.
                           Return (One)                               // Return success status.
                       }
                   }

                   Return (Zero)                                      // Return error status – no (all) bytes sent.
               }

               Method (SRXB, 1, Serialized)                           // ASUS Method (RSBT)
               {
                   If (STRT ())                                       // Ready?
                   {
                       Store (Zero, I2CE)
                       Store (0xBF, HSTS)                             // Clear Host Status Register, with the exception of bit-6 (INUSE_STS).
                       Store (Or (Arg0, 0x01), TXSA)                  // This is a Read Command (bit 1-7 is the address of the targeted device).
                       Store (0x44, HCON)                             // Start Byte Read Command.

                       If (COMP ())                                   // Error checking – Successful completion of command?
                       {
                           Or (HSTS, 0xFF, HSTS)                      // Clear Host Status Register.
                           Return (DAT0)                              // Return Read Data.
                       }
                   }

                   Return (0xFFFF)                                    // Return byte read command error status (65535).
               }

               Method (SWRB, 3, Serialized)                           // ASUS Method (WBYT)
               {
                   If (STRT ())                                       // Ready?
                   {
                       Store (Zero, I2CE)                             // 
                       Store (0xBF, HSTS)                             // Clear Host Status Register, with the exception of bit-6 (INUSE_STS).
                       Store (Arg0, TXSA)                             // This is a write command (bit 1-7 is the address of the targeted device).
                       Store (Arg1, HCOM)                             // Forward Command.
                       Store (Arg2, DAT0)                             // Forward Data Byte.
                       Store (0x48, HCON)                             // Start Byte Data Command.

                       If (COMP ())                                   // Error checking – Successful completion of command?
                       {
                           Or (HSTS, 0xFF, HSTS)                      // Clear Host Status Register.
                           Return (One)                               // Success (one byte sent).
                       }
                   }

                   Return (Zero)                                      // Return error status (no byte sent).
               }

               Method (SRDB, 2, Serialized)                           // ASUS Method (RBYT)
               {
                   If (STRT ())                                       // Ready?
                   {
                       Store (Zero, I2CE)                             // 
                       Store (0xBF, HSTS)                             // Clear Host Status Register, with the exception of bit-6 (INUSE_STS).
                       Store (Or (Arg0, One), TXSA)                   // This is a Read Command (bit 1-7 is the address of the targeted device).
                       Store (Arg1, HCOM)                             // 
                       Store (0x48, HCON)                             // Start Byte Data Command.

                       If (COMP ())                                   // Error checking – Successful completion of command?
                       {
                          Or (HSTS, 0xFF, HSTS)                       // Clear Host Status Register.
                          Return (DAT0)                               // Return Read Data.
                       }
                   }

                   Return (0xFFFF)                                    // Return data byte read command error status (65535).
               }

               Method (SBLW, 4, Serialized)                           // ASUS Method (WBLK)
               {
                   If (STRT ())                                       // Ready?
                   {
                       Store (Arg3, I2CE)                             // 
                       Store (0xBF, HSTS)                             // Clear Host Status Register, with the exception of bit-6 (INUSE_STS).
                       Store (Arg0, TXSA)                             // 
                       Store (Arg1, HCOM)                             // Forward Command.
                       Store (SizeOf (Arg2), DAT0)                    // Forward buffer length for transmission.
                       Store (Zero, Local1)                           // Buffer index of transmitted bytes.
                       Store (DerefOf (Index (Arg2, Zero)), HBDR)     // Forward first data byte.
                       Store (0x54, HCON)                             // Start Block Write Command.

                       While (LGreater (SizeOf (Arg2), Local1))       // Loop until all bytes are successfully transmitted.
                       {
                           Store (0x0FA0, Local0)                     // 0x0FA = 4000 (timeout counter).
                                                                      // Wait for the command to complete by checking bit-7 (Byte Done Status) – up to 4000 times.
                           While (LAnd (LNot (And (HSTS, 0x80)), Local0))
                           {
                               Decrement (Local0)                     // 3999, 3998, 3997…
                               Stall (0x32)                           // Delay execution for at least 50 microseconds.
                           }

                           If (LNot (Local0))                         // Error checking – If Local0 is Zero then something went wrong.
                           {
                               KILL ()                                // Abort command.
                               Return (Zero)                          // Error Status.
                           }

                           Store (0x80, HSTS)                         // Byte Done Status (DS) — Clear bit 'byte transmission completed'. 
                           Increment (Local1)                         // Increase index.
                           If (LGreater (SizeOf (Arg2), Local1))      // Forward nth byte (if we have one left).
                           {
                               Store (DerefOf (Index (Arg2, Local1)), HBDR)
                           }
                       }

                       If (COMP ())                                   // Error checking – Successful completion of command?
                       {
                           Or (HSTS, 0xFF, HSTS)                      // Clear Host Status Register.
                           Return (One)                               // Success Status.
                       }
                   }

                   Return (Zero)                                      // Return error status – not (all) bytes sent.
               }

               Method (SBLR, 3, Serialized)                           // ASUS Method (RBLK)
               {
                   If (STRT ())                                       // Ready?
                   {
                       Name (TBUF, Buffer (0x0100) {})                // Create buffer (256 bytes).
                       Store (Arg2, I2CE)                             // 
                       Store (0xBF, HSTS)                             // Clear Host Status Register, with the exception of bit-6 (INUSE_STS).
                       Store (Or (Arg0, One), TXSA)                   // This is a Read Command (bit 1-7 is the address of the targeted device).
                       Store (Arg1, HCOM)                             // Forward Command.
                       Store (0x54, HCON)                             // Start Block Read Command.
                       Store (0x0FA0, Local0)                         // Counter (4000).

                       While (LAnd (LNot (And (HSTS, 0x80)), Local0)) // 
                       {
                           Decrement (Local0)                         // 
                           Stall (0x32)                               // Delay execution for at least 50 microseconds.
                       }

                       If (LNot (Local0))                             // 
                       {
                           KILL ()                                    // Abort.
                           Return (Zero)                              // Return error status.
                       }

                       Store (DAT0, Index (TBUF, Zero))               // 
                       Store (0x80, HSTS)                             // Byte Done Status (DS) — Host controller received a byte.
                       Store (One, Local1)

                       While (LLess (Local1, DerefOf (Index (TBUF, Zero))))
                       {
                           Store (0x0FA0, Local0)                     // Counter (4000).

                           While (LAnd (LNot (And (HSTS, 0x80)), Local0))
                           {
                               Decrement (Local0)                     // 3999, 3998, 3997...
                               Stall (0x32)                           // Delay execution for at least 50 microseconds.
                           }

                           If (LNot (Local0))                         // 
                           {
                               KILL ()                                // Abort.
                               Return (Zero)                          // Return error status.
                           }

                           Store (HBDR, Index (TBUF, Local1))         // Store byte in buffer.
                           Store (0x80, HSTS)                         // Byte Done Status (DS) — Host controller received a byte.
                           Increment (Local1)                         // Increase byte buffer index.
                       }

                       If (COMP ())                                   // Error checking – Successful completion of command?
                       {
                           Or (HSTS, 0xFF, HSTS)                      // Clear Host Status Register.
                           Return (TBUF)                              // Return buffer.
                       }
                   }

                   Return (Zero)                                      // Return error status.
               }

               Method (STRT, 0, Serialized)
               {
                   Store (0xC8, Local0)                               // Counter (200).
                   While (Local0)                                     // Loop until Zero.
                   {
                       If (And (HSTS, 0x40))                          // Check bit-6 (INUSE_STS) – In use?
                       {
                           Decrement (Local0)                         // 199, 198, 197…
                           Sleep (0x01)                               // Delay execution for at least 1 microsecond.
                           If (LEqual (Local0, Zero))                 // Have we reached Zero, then something might be wrong. 
                           {
                               Return (Zero)                          // Return Busy status.
                           }
                       }
                       Else
                       {
                           Store (Zero, Local0)                       // Break (not in use).
                       }
                   }

                   Store (0x0FA0, Local0)                             // Counter (4000).
                   While (Local0)                                     // Loop until Zero.
                   {
                       If (And (HSTS, One))                           // Check bit-0 (HOST_BUSY) – Running command from the host interface?
                       {
                           Decrement (Local0)                         // 3999, 3998, 3997...
                           Stall (0x32)                               // Delay execution for at least 50 microseconds.
                           If (LEqual (Local0, Zero))                 // Have we reached Zero, then something must be wrong.
                           {
                               KILL ()                                // Abort.
                           }
                       }
                       Else
                       {
                           Return (One)                               // Return ready status.
                       }
                   }

                   Return (Zero)                                      // Return error status.
               }

               Method (COMP, 0, Serialized)
               {
                   Store (0x0FA0, Local0)                             // Counter 0x0FA0 (4000). 
                   While (Local0)                                     // Loop until Zero.
                   {
                       If (And (HSTS, 0x02))                          // INTR – Successful completion of last command?
                       {
                           Return (One)                               // Return transmission success ended.
                       }
                       Else
                       {
                           Decrement (Local0)                         // 3999, 3998, 3997...
                           Stall (0x32)                               // Delay execution for at least 50 microseconds.
                           If (LEqual (Local0, Zero))                 // Error.
                           {
                               KILL ()                                // Abort transmission.
                           }
                       }
                   }

                   Return (Zero)                                      // Return error status.
               }

               Method (KILL, 0, Serialized)
               {
                   Or (HCON, 0x02, HCON)                              // Set bit-1 – Abort current host transaction.
                   Or (HSTS, 0xFF, HSTS)                              // Clear Host Status Register.
               }

               Device (BUS0)
               {

Have fun with part one while I rewrite it. Oh and get Debug() working man, that helps a lot. Good luck with it.

 

p.s. I was not allowed to comment in your thread so I've put it here in good spirit

[ƃuıʞ ǝɥʇ]

What I do recommend in that post is the usage of:

            Device (SBUS)
           {
               Name (_ADR, 0x001F0003)
               Device (BUS0)
               {
                   Name (_CID, "smbus")
                   Name (_ADR, Zero)
                   Device (DVL0)
                   {
                       Name (_ADR, 0x57)
                       Name (_CID, "diagsvault")
                   }
               }
           }

But only for those who get that error on boot, also to show that it has the same effect with full apple copy/paste.

No need for thanks since this was discovered long time before you started to play with DSDT.

I always remarked when you have a good idea, like was with _INI method(also recommended by a friend), and the _PRT stuff is interesting...

 

I'm also happy to see that you started to add back stuff from SIOR in the place where they belong SBUS, waiting for the day when you will remove EC device since is useless...

 

I totally disagree with your new methods, you are going, like other ODM/OEM's who dosen't fallow ACPI specs, to create more confusion then clearing something. IMHO DSM is good enough for what we use, and also almost all knows what it does, what you will do create new methods for other stuff we have to inject?

Try to keep stuff in the known area(and as they are defined in specs)...you already got negative results/reports on this.

[barnum]

DSDT V3.1 Has Been Released Today �" see attachments in post#3

 

 

Happy Hacking!

Hi Master chief,

I see that you add this method in the cpu declaration :

            Method (_PSD, 0, NotSerialized)
           {
               Return (Package (0x05)
               {
                   0x05,
                   0x00,
                   0x00,
                   0xFC,
                   0x04
               })
           }

is it specific to your cpu ?

 

Barnum

[Pene]

Hi Master Chief,

 

As already reported, when using the SBUS patch, it tries to load the kexts com.apple.driver.AppleMikeyDriver and com.apple.driver.AppleMikeyHIDDriver.

 

These are not needed and report an error when they load, yet they remain loaded.

 

Is it possible to disable loading them when using SMBUS (which would also disable the logged error)?

 

Thanks!