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DSDT - Vanilla Speedstep - Generic Scope (_PR)

FKA

By FKA,
in Power Management

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kizwan
kizwan
Posted
Posted

I believe there is a simpler way to get proper speedstep. seeker_moc & error-idiot @ NBR forum introduced me BIOS Implementation Test Suite (BITS) . This tool basically can check your computer BIOS & make necessary correction to processor P-States, where you can dump the modified SSDT table & reintegrate it into your DSDT. Check it out!

 

And that's what PStateChanger returns:

pstatechangerdnjm.png

 

But the VID is the FID...

 

So does anyone know what's going wrong?

This is because Nehalem processors have locked VID & FID. Probably Intel change the register to read VID & FID on Nehalem processors.

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JBraddock
JBraddock
Posted
Posted
I believe there is a simpler way to get proper speedstep. seeker_moc & error-idiot @ NBR forum introduced me BIOS Implementation Test Suite (BITS) . This tool basically can check your computer BIOS & make necessary correction to processor P-States, where you can dump the modified SSDT table & reintegrate it into your DSDT. Check it out!.

Hi Kizwan, it's been a long time ;) I hope you are all well.

 

Does it make permanent changes to Bios (P-States etc.)? If so, can I assume that I will not need to edit my DSDT file as I am using AnVaL to generate P and C states based on my SSDT tables? Or does it just show me the corrections and allow me to dump those newly generated tables for later use?

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kizwan
kizwan
Posted
Posted
Does it make permanent changes to Bios (P-States etc.)? If so, can I assume that I will not need to edit my DSDT file as I am using AnVaL to generate P and C states based on my SSDT tables? Or does it just show me the corrections and allow me to dump those newly generated tables for later use?

It doesn't change the existing BIOS. BITS test the BIOS initialization of Intel processors, hardware, and technologies against Intel recommendations. BITS also includes Intel's official reference code, which you can use to override your BIOS's hardware initialization with a known-good configuration, and then boot an OS. Just read all about it @ http://biosbits.org/

 

If you don't want to use BITS as intermediate boot loader, you can dump the fixed SSDT table & integrate it in the DSDT. This way you won't need to use boot loader to generate P & C states for you.

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JBraddock
JBraddock
Posted
Posted
It doesn't change the existing BIOS. BITS test the BIOS initialization of Intel processors, hardware, and technologies against Intel recommendations. BITS also includes Intel's official reference code, which you can use to override your BIOS's hardware initialization with a known-good configuration, and then boot an OS. Just read all about it @ http://biosbits.org/

 

If you don't want to use BITS as intermediate boot loader, you can dump the fixed SSDT table & integrate it in the DSDT. This way you won't need to use boot loader to generate P & C states for you.

Say, I run the test and it made corrections for my SSDT tables. But later, in order to dump all those fixed SSDT tables I need to boot into Linux right? Since I don't have Windows installed, that seems the only choice. But the problem is, looking at the screen shots at that website, there are only two options; Boot first drive MBR and boot second drive MBR.

 

Does this mean that after making the corrections I can't use a Linux live Cd to boot into Linux? In my case, what would be the best option, if any, to dump the fixed SSDT tables? Do I need a separate hard drive on which Windows or Linux installed to dump all those SSDT tables?

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kizwan
kizwan
Posted
Posted
Say, I run the test and it made corrections for my SSDT tables. But later, in order to dump all those fixed SSDT tables I need to boot into Linux right? Since I don't have Windows installed, that seems the only choice. But the problem is, looking at the screen shots at that website, there are only two options; Boot first drive MBR and boot second drive MBR.

 

Does this mean that after making the corrections I can't use a Linux live Cd to boot into Linux? In my case, what would be the best option, if any, to dump the fixed SSDT tables? Do I need a separate hard drive on which Windows or Linux installed to dump all those SSDT tables?

I only tested it with windows but it should work with linux too. After you have choose which configuration you want in "Configure Menu", boot to linux by choosing "Boot first drive MBR" or "boot second drive MBR", depend on where linux is installed. Then dump SSDT table in linux.

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JBraddock
JBraddock
Posted
Posted
I only tested it with windows but it should work with linux too. After you have choose which configuration you want in "Configure Menu", boot to linux by choosing "Boot first drive MBR" or "boot second drive MBR", depend on where linux is installed. Then dump SSDT table in linux.

I see. I think I'll try to find external hard drive to install Windows. But at this point, theoretically speaking, once I've run the test and chosen to boot into my first HDD on which Snow Leopard is installed, Chemeleon should be able to generate P and C States according to the fixed SSDT tables. Am I right?

 

Also in your case, did you see any improvement in your temp values or the way that CPU is being utilised by OS.

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kizwan
kizwan
Posted
Posted
I see. I think I'll try to find external hard drive to install Windows. But at this point, theoretically speaking, once I've run the test and chosen to boot into my first HDD on which Snow Leopard is installed, Chemeleon should be able to generate P and C States according to the fixed SSDT tables. Am I right?

 

Also in your case, did you see any improvement in your temp values or the way that CPU is being utilised by OS.

Yeah, theoretically speaking, it should work with Snow Leopard too. After you have chosen your desired configuration & boot into first HDD on which Snow Leopard is installed, your Snow Leopard will get new SSDT with fixed P-States. You don't need to tell Chameleon to generate P & C states anymore because that would be redundant. I'm unable to test this on my notebooks because P & C states are properly detected without telling Chameleon to generate P & C states for me.

 

I only tested this with windows but I didn't see or feel any improvements. When running the test, everything is OK on my notebook. The only error it found is one C state failed "demotion" routine. I don't know what that's for though (didn't bother to google it ;) ). The BITS ability to generate correct SSDT with fixed P States will definitely help who ever have problem with P States on their computer with OS X.

 

Thanks kizwan for your reply, but this doesn't solve my problem.

 

I mean the VID and FID have to be there and there has to be a solution to read them out, actually I hope...

Yeah, you're right. I though it have similar issue with mobile nehalem processors. I spent too long at notebook forum. Nehalem mobile processors; i3, i5 & i7 have locked VID. Can't even monitor it, let alone control it for e.g. undervolting. In your issue, it is best look directly in the _PSS control method in SSDT table.

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MatzeOS86
MatzeOS86
Posted
Posted

I've now dumped the SSDT with Everest under Windows, but the _PSS Method looks a bit strange to me.

And I guess that I won't get the VID/mV out of the table, right?

 

Thats what the method looks like:

Method (_PSS, 0, NotSerialized)

{

If (LAnd (LNot (And (CFGD, 0x4000)), LEqual (And (PDC0,

0x09), 0x09)))

{

Return (NPSS)

}

 

Return (SPSS)

}

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kizwan
kizwan
Posted
Posted
I've now dumped the SSDT with Everest under Windows, but the _PSS Method looks a bit strange to me.

And I guess that I won't get the VID/mV out of the table, right?

 

Thats what the method looks like:

Is there any SPSS or NPSS control method? Sometime it can be found in those control method. Try use BITS to fix your SSDT table.

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MatzeOS86
MatzeOS86
Posted
Posted

Yes, they are there.

 

Name (SPSS, Package (0x0A)
	{
		Package (0x06)
		{
			0x00000AF0, 
			0x00023E38, 
			0x000000A0, 
			0x0000000A, 
			0x00000015, 
			0x00000015
		}, 

		Package (0x06)
		{
			0x00000A6B, 
			0x0001FBD0, 
			0x000000A0, 
			0x0000000A, 
			0x00000014, 
			0x00000014
		}, 

		Package (0x06)
		{
			0x000009E5, 
			0x0001BD50, 
			0x000000A0, 
			0x0000000A, 
			0x00000013, 
			0x00000013
		}, 

		Package (0x06)
		{
			0x00000960, 
			0x000186A0, 
			0x000000A0, 
			0x0000000A, 
			0x00000012, 
			0x00000012
		}, 

		Package (0x06)
		{
			0x000008DB, 
			0x000153D8, 
			0x000000A0, 
			0x0000000A, 
			0x00000011, 
			0x00000011
		}, 

		Package (0x06)
		{
			0x00000855, 
			0x000128E0, 
			0x000000A0, 
			0x0000000A, 
			0x00000010, 
			0x00000010
		}, 

		Package (0x06)
		{
			0x000007D0, 
			0x000101D0, 
			0x000000A0, 
			0x0000000A, 
			0x0000000F, 
			0x0000000F
		}, 

		Package (0x06)
		{
			0x0000074B, 
			0x0000DEA8, 
			0x000000A0, 
			0x0000000A, 
			0x0000000E, 
			0x0000000E
		}, 

		Package (0x06)
		{
			0x000006C5, 
			0x0000C350, 
			0x000000A0, 
			0x0000000A, 
			0x0000000D, 
			0x0000000D
		}, 

		Package (0x06)
		{
			0x00000640, 
			0x0000A7F8, 
			0x000000A0, 
			0x0000000A, 
			0x0000000C, 
			0x0000000C
		}
	}

 

Name (NPSS, Package (0x0A)
	{
		Package (0x06)
		{
			0x00000A6C, 
			0x00023E38, 
			0x0000000A, 
			0x0000000A, 
			0x00000015, 
			0x00000015
		}, 

		Package (0x06)
		{
			0x00000A6B, 
			0x0001FBD0, 
			0x0000000A, 
			0x0000000A, 
			0x00000014, 
			0x00000014
		}, 

		Package (0x06)
		{
			0x000009E5, 
			0x0001BD50, 
			0x0000000A, 
			0x0000000A, 
			0x00000013, 
			0x00000013
		}, 

		Package (0x06)
		{
			0x00000960, 
			0x000186A0, 
			0x0000000A, 
			0x0000000A, 
			0x00000012, 
			0x00000012
		}, 

		Package (0x06)
		{
			0x000008DB, 
			0x000153D8, 
			0x0000000A, 
			0x0000000A, 
			0x00000011, 
			0x00000011
		}, 

		Package (0x06)
		{
			0x00000855, 
			0x000128E0, 
			0x0000000A, 
			0x0000000A, 
			0x00000010, 
			0x00000010
		}, 

		Package (0x06)
		{
			0x000007D0, 
			0x000101D0, 
			0x0000000A, 
			0x0000000A, 
			0x0000000F, 
			0x0000000F
		}, 

		Package (0x06)
		{
			0x0000074B, 
			0x0000DEA8, 
			0x0000000A, 
			0x0000000A, 
			0x0000000E, 
			0x0000000E
		}, 

		Package (0x06)
		{
			0x000006C5, 
			0x0000C350, 
			0x0000000A, 
			0x0000000A, 
			0x0000000D, 
			0x0000000D
		}, 

		Package (0x06)
		{
			0x00000640, 
			0x0000A7F8, 
			0x0000000A, 
			0x0000000A, 
			0x0000000C, 
			0x0000000C
		}
	}

 

But I don't know where the VID is hiding. :P

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kdtt
kdtt
Posted
Posted

I updated my bios and i found that my ssdt table has been changed. old bios has method_csd . and new one does not have that method.

can you tell me what that method is for?

the only difference between the two bioses is that latter has turbo performance option which gives 22 multiplier.

evga x58 e760 i7 920 

Method (_CSD, 0, NotSerialized)
	{
		If (And (TYPE, 0x00000040))
		{
			Return (Package (0x01)
			{
				Package (0x06)
				{
					0x06, 
					0x00, 
					0x00000000, 
					0x000000FE, 
					0x00000002, 
					0x00000001
				}
			})
		}

		Return (Zero)

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kizwan
kizwan
Posted
Posted

It is a C-State Dependency.

 

(Source: Advanced Configuration and Power Interface Specification - 4.0a)

8.4.2.2 _CSD (C-State Dependency)

This optional object provides C-state control cross logical processor dependency information to OSPM. The _CSD object evaluates to a packaged list of information that correlates with the C-state information returned by the _CST object. Each packaged list entry identifies the C-state for which the dependency is being specified (as an index into the _CST object list), a dependency domain number for that C-state, the coordination type for that C-state and the number of logical processors belonging to the domain for the particular C-state. It is possible that a particular C-state may belong to multiple domains. That is, it is possible to have multiple entries in the _CSD list with the same CStateIndex value.

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kdtt
kdtt
Posted
Posted

Thanks for your reply. when i use old bios i get turbo set 1112 in log but in bios there's no option for 22 multiply.

so msr tools show only 105% 21 multi. when i use new bios , eventhough i get all kexts loaded, i don't get turbo 1112 message , and i can't get x22 in msr tools.

Do you think it has something to do with csd method? In windows i get 22 multiply.

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kizwan
kizwan
Posted
Posted
Thanks for your reply. when i use old bios i get turbo set 1112 in log but in bios there's no option for 22 multiply.

so msr tools show only 105% 21 multi. when i use new bios , eventhough i get all kexts loaded, i don't get turbo 1112 message , and i can't get x22 in msr tools.

Do you think it has something to do with csd method? In windows i get 22 multiply.

I think you'll need to fix the P-States (_PSS). You can check & fixed it with BITS though.

 

So, i7-920 has Turbo 1/1/1/2:-

  • First number is multiple with 133.33 MHz when four cores are active.
  • The second number is multiple with 133.33 MHz for three cores.
  • The third number is multiple with 133.33 for two cores.
  • The fourth number is multiple with 133.33 for one active core.

Normal operating frequency is 2.67 GHz = ~2666 MHz

  • With 2 or 3 or 4 cores active: to 2.8 GHz —————> ~2666 + 1 x 133.33 = ~2666 + 133.33 = ~2799.33
  • With only 1 core active: to 2.93 GHz —————–> ~2666 + 2 x 133.33 = ~2666 + 266.66 = ~2932.66

 

It's a very short Turbo Boost, so it should be easily achieved. i7-920 maximum non-turbo multiplier is x20 while the x22 multi is fall under Turbo Boost. So, I think you'll need to fix the P-States.

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kdtt
kdtt
Posted
Posted

I ran a bits test, and i got quite a lot failures.

smrr test 6 passed 0 failed

pstate ratios 10 passed 0 failed

smi latency 0 passed 1 failed

msr consistency 8166 passed 2 failed(2 different values)

cstate residency 2 passed 2 failed (error need 2 arguments:msr_number value

powermanagement test suit 6 passed 5 failed

post-772374-1303046205_thumb.jpg

 

is this possible to fix with modifying dsdt?

 

thanks

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  • 2 weeks later...
mackyreddy
mackyreddy
Posted
Posted

hey guys can any one help me got one error am almost done with my ssdt

 

Intel ACPI Component Architecture

 

 

 

ASL Optimizing Compiler version 20110413-32 [Apr 13 2011]

 

 

 

Copyright © 2000 - 2011 Intel Corporation

 

 

 

dsdt.dsl 898: }000000B3, // Address

 

 

 

Error 4096 - ^ parse error, expecting `

 

 

 

ASL Input: dsdt.dsl - 8596 lines, 278263 bytes, 150 keywords

 

 

 

Compilation complete. 1 Errors, 0 Warnings, 0 Remarks, 66 Optimizations

 

 

 

[Completed]

 

dsdt.txt

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  • 3 weeks later...
StuMcBill
StuMcBill
Posted
Posted

Hi, I have followed this guide and got my FID & VID values in my DSDT as below:

 

 Scope (_PR)
   {
       Processor (CPU0, 0x00, 0x00000410, 0x06) {}
       Processor (CPU1, 0x01, 0x00000410, 0x06) {}
       Processor (CPU2, 0x02, 0x00000410, 0x06) {}
       Processor (CPU3, 0x03, 0x00000410, 0x06) {}
   }

   Scope (_PR.CPU0)
   {
       Method (_PSS, 0, NotSerialized)
       {
           Return (Package (0x04)
           {
               Package (0x06)
               {
                   Zero, 
                   Zero, 
                   0x10, 
                   0x10, 
                   0x0922, 
                   Zero
               }, 

               Package (0x06)
               {
                   Zero, 
                   Zero, 
                   0x10, 
                   0x10, 
                   0x081F, 
                   One
               }, 

               Package (0x06)
               {
                   Zero, 
                   Zero, 
                   0x10, 
                   0x10, 
                   0x071B, 
                   0x02
               }, 

               Package (0x06)
               {
                   Zero, 
                   Zero, 
                   0x10, 
                   0x10, 
                   0x0617, 
                   0x03
               }
           })
       }

       Method (_PSD, 0, NotSerialized)
       {
           Return (Package (0x05)
           {
               0x05, 
               Zero, 
               Zero, 
               0xFC, 
               0x04
           })
       }

       Method (_CST, 0, NotSerialized)
       {
           Return (Package (0x02)
           {
               One, 
               Package (0x04)
               {
                   ResourceTemplate ()
                   {
                       Register (FFixedHW, 
                           0x01,               // Bit Width
                           0x02,               // Bit Offset
                           0x0000000000000000, // Address
                           0x01,               // Access Size
                           )
                   }, 

                   One, 
                   0x9D, 
                   0x03E8
               }
           })
       }
   }

   Scope (_PR.CPU1)
   {
       Method (_PSS, 0, NotSerialized)
       {
           Return (^^CPU0._PSS ())
       }

       Method (_PSD, 0, NotSerialized)
       {
           Return (^^CPU0._PSD ())
       }

       Method (_CST, 0, NotSerialized)
       {
           Return (Package (0x04)
           {
               0x03, 
               Package (0x04)
               {
                   ResourceTemplate ()
                   {
                       Register (FFixedHW, 
                           0x01,               // Bit Width
                           0x02,               // Bit Offset
                           0x0000000000000000, // Address
                           ,)
                   }, 

                   One, 
                   Zero, 
                   0x03E8
               }, 

               Package (0x04)
               {
                   ResourceTemplate ()
                   {
                       Register (FFixedHW, 
                           0x08,               // Bit Width
                           0x00,               // Bit Offset
                           0x0000000000000414, // Address
                           ,)
                   }, 

                   0x02, 
                   One, 
                   0x01F4
               }, 

               Package (0x04)
               {
                   ResourceTemplate ()
                   {
                       Register (FFixedHW, 
                           0x08,               // Bit Width
                           0x00,               // Bit Offset
                           0x0000000000000415, // Address
                           ,)
                   }, 

                   0x03, 
                   0x55, 
                   0xFA
               }
           })
       }
   }

 

And I have got my Device info from lspci, and adapted my DSDT accordingly to match a value which was contained in the info.plist file in AppleLPC.kext as below:

Device (LPCB)
           {
               Name (_ADR, 0x001F0000)
               Method (_DSM, 4, NotSerialized)
               {
                   Store (Package (0x02)
                       {
                           "device-id", 
                           Buffer (0x04)
                           {
                               0x16, 0x29, 0x00, 0x00
                           }
                       }, Local0)
                   DTGP (Arg0, Arg1, Arg2, Arg3, RefOf (Local0))
                   Return (Local0)
               }

 

This compiles and installs fine, however, I still don't seem to have any SpeedStep functionality?

 

When I insert the following (from the first post) underneath the above code, I get compilation errors?

OperationRegion (PREV, PCI_Config, 0x08, One)
			Scope (\)
			{
				Field (\_SB.PCI0.LPCB.PREV, ByteAcc, NoLock, Preserve)
				{
					REV0,   8
				}
			}

			OperationRegion (PIRQ, PCI_Config, 0x60, 0x04)
			Scope (\)
			{

 

The compilation error is this:

Users/stewart/Library/Application Support/EvOSoftware/DSDT/DSDTFiles/dsdt.dsl  7856: [*** iASL: Read error on source code temp file /Users/stewart/Library/Application Support/EvOSoftware/DSDT/DSDTFiles/dsdt.src ***]
Error	4096 -										syntax error, unexpected $end ^

 

And the contents of my smbios.plist file is this:

<?xml version="1.0" encoding="UTF-8"?>
<!DOCTYPE plist PUBLIC "-//Apple//DTD PLIST 1.0//EN" "http://www.apple.com/DTDs/PropertyList-1.0.dtd">
<plist version="1.0">
<dict>
<key>SMfamily</key>
<string>MacBook Pro</string>
<key>SMproductname</key>
<string>MacBookPro8,1</string>
<key>SMboardproduct</key>
<string>Mac-94245B3640C91C81</string>
<key>SMserial</key>
<string>C02F93FQDH2G</string>
<key>SMbiosversion</key>
<string>[url=&quot;http://www.insanelymac.com/forum/topic/279450-why-insanelymac-does-not-support-tonymacx86/&quot;]#####[/url].tonymacx86.com</string>
</dict>
</plist>

 

I have tried changing it to different ones, but I keep getting Kernel Panics on startup.

 

Could anyone offer me any pointers?

 

Stew

 

Hi, I have followed this guide and got my FID & VID values in my DSDT as below:

 

 Scope (_PR)
   {
       Processor (CPU0, 0x00, 0x00000410, 0x06) {}
       Processor (CPU1, 0x01, 0x00000410, 0x06) {}
       Processor (CPU2, 0x02, 0x00000410, 0x06) {}
       Processor (CPU3, 0x03, 0x00000410, 0x06) {}
   }

   Scope (_PR.CPU0)
   {
       Method (_PSS, 0, NotSerialized)
       {
           Return (Package (0x04)
           {
               Package (0x06)
               {
                   Zero, 
                   Zero, 
                   0x10, 
                   0x10, 
                   0x0922, 
                   Zero
               }, 

               Package (0x06)
               {
                   Zero, 
                   Zero, 
                   0x10, 
                   0x10, 
                   0x081F, 
                   One
               }, 

               Package (0x06)
               {
                   Zero, 
                   Zero, 
                   0x10, 
                   0x10, 
                   0x071B, 
                   0x02
               }, 

               Package (0x06)
               {
                   Zero, 
                   Zero, 
                   0x10, 
                   0x10, 
                   0x0617, 
                   0x03
               }
           })
       }

       Method (_PSD, 0, NotSerialized)
       {
           Return (Package (0x05)
           {
               0x05, 
               Zero, 
               Zero, 
               0xFC, 
               0x04
           })
       }

       Method (_CST, 0, NotSerialized)
       {
           Return (Package (0x02)
           {
               One, 
               Package (0x04)
               {
                   ResourceTemplate ()
                   {
                       Register (FFixedHW, 
                           0x01,               // Bit Width
                           0x02,               // Bit Offset
                           0x0000000000000000, // Address
                           0x01,               // Access Size
                           )
                   }, 

                   One, 
                   0x9D, 
                   0x03E8
               }
           })
       }
   }

   Scope (_PR.CPU1)
   {
       Method (_PSS, 0, NotSerialized)
       {
           Return (^^CPU0._PSS ())
       }

       Method (_PSD, 0, NotSerialized)
       {
           Return (^^CPU0._PSD ())
       }

       Method (_CST, 0, NotSerialized)
       {
           Return (Package (0x04)
           {
               0x03, 
               Package (0x04)
               {
                   ResourceTemplate ()
                   {
                       Register (FFixedHW, 
                           0x01,               // Bit Width
                           0x02,               // Bit Offset
                           0x0000000000000000, // Address
                           ,)
                   }, 

                   One, 
                   Zero, 
                   0x03E8
               }, 

               Package (0x04)
               {
                   ResourceTemplate ()
                   {
                       Register (FFixedHW, 
                           0x08,               // Bit Width
                           0x00,               // Bit Offset
                           0x0000000000000414, // Address
                           ,)
                   }, 

                   0x02, 
                   One, 
                   0x01F4
               }, 

               Package (0x04)
               {
                   ResourceTemplate ()
                   {
                       Register (FFixedHW, 
                           0x08,               // Bit Width
                           0x00,               // Bit Offset
                           0x0000000000000415, // Address
                           ,)
                   }, 

                   0x03, 
                   0x55, 
                   0xFA
               }
           })
       }
   }

 

And I have got my Device info from lspci, and adapted my DSDT accordingly to match a value which was contained in the info.plist file in AppleLPC.kext as below:

Device (LPCB)
           {
               Name (_ADR, 0x001F0000)
               Method (_DSM, 4, NotSerialized)
               {
                   Store (Package (0x02)
                       {
                           "device-id", 
                           Buffer (0x04)
                           {
                               0x16, 0x29, 0x00, 0x00
                           }
                       }, Local0)
                   DTGP (Arg0, Arg1, Arg2, Arg3, RefOf (Local0))
                   Return (Local0)
               }

 

This compiles and installs fine, however, I still don't seem to have any SpeedStep functionality?

 

When I insert the following (from the first post) underneath the above code, I get compilation errors?

OperationRegion (PREV, PCI_Config, 0x08, One)
			Scope (\)
			{
				Field (\_SB.PCI0.LPCB.PREV, ByteAcc, NoLock, Preserve)
				{
					REV0,   8
				}
			}

			OperationRegion (PIRQ, PCI_Config, 0x60, 0x04)
			Scope (\)
			{

 

The compilation error is this:

Users/stewart/Library/Application Support/EvOSoftware/DSDT/DSDTFiles/dsdt.dsl  7856: [*** iASL: Read error on source code temp file /Users/stewart/Library/Application Support/EvOSoftware/DSDT/DSDTFiles/dsdt.src ***]
Error	4096 -										syntax error, unexpected $end ^

 

And the contents of my smbios.plist file is this:

<?xml version="1.0" encoding="UTF-8"?>
<!DOCTYPE plist PUBLIC "-//Apple//DTD PLIST 1.0//EN" "http://www.apple.com/DTDs/PropertyList-1.0.dtd">
<plist version="1.0">
<dict>
<key>SMfamily</key>
<string>MacBook Pro</string>
<key>SMproductname</key>
<string>MacBookPro8,1</string>
<key>SMboardproduct</key>
<string>Mac-94245B3640C91C81</string>
<key>SMserial</key>
<string>C02F93FQDH2G</string>
<key>SMbiosversion</key>
<string>[url=&quot;http://www.insanelymac.com/forum/topic/279450-why-insanelymac-does-not-support-tonymacx86/&quot;]#####[/url].tonymacx86.com</string>
</dict>
</plist>

 

I have tried changing it to different ones, but I keep getting Kernel Panics on startup.

 

Could anyone offer me any pointers?

 

Stew

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