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DSDT - Vanilla Speedstep - Generic Scope (_PR)

FKA

By FKA,
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mitch_de
mitch_de
Posted
Posted
Name (PSD, Package (0x05)

{

0x05,Zero,Zero,0xFC,0x04

})

Yep thats right, page 328 and 329 of ACPI specs, that value relates to the number of processors

 

But does that make really sense ?

Most of us with core2duo (2 Cores) will have such an begin of DSDT in _PR, even be use an 2 core CPU. 4 Cores are defined in PR.

 

Scope (_PR)

{

Processor (CPU0, 0x00, 0x00000410, 0x06) {}

Processor (CPU1, 0x01, 0x00000410, 0x06) {}

Processor (CPU2, 0x02, 0x00000410, 0x06) {}

Processor (CPU3, 0x03, 0x00000410, 0x06) {}

}

 

So why should PSD (....04) should be changed in PSD (.....02 ) ?

 

I think that that DSDT content must have at least as many entrys (Processors , PSD ( num) als cpu cores but may have more without any problem.

I believe that unused _PR CPU2+CPU3 entrys doesnt matter and so also that PSD (...04) . I have an C2D with _PR for 4 Cores and also an PSD with (....04) running without any problem.

Lat but mot least: If someone shrink that down to 2 CPUs in _PR and 02 in PSD an switch to an Quad CPU may run in major problems. If the user didnt remeber that shwinking or used an dsdt of someone else (shrinked) he will have trouble to finde the reason.

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keeza
keeza
Posted
Posted
But does that make really sense ?

Most of us with core2duo (2 Cores) will have such an begin of DSDT in _PR, even be use an 2 core CPU. 4 Cores are defined in PR.

 

Scope (_PR)

{

Processor (CPU0, 0x00, 0x00000410, 0x06) {}

Processor (CPU1, 0x01, 0x00000410, 0x06) {}

Processor (CPU2, 0x02, 0x00000410, 0x06) {}

Processor (CPU3, 0x03, 0x00000410, 0x06) {}

}

 

So why should PSD (....04) should be changed in PSD (.....02 ) ?

 

I think that that DSDT content must have at least as many entrys (Processors , PSD ( num) als cpu cores but may have more without any problem.

I believe that unused _PR CPU2+CPU3 entrys doesnt matter and so also that PSD (...04) . I have an C2D with _PR for 4 Cores and also an PSD with (....04) running without any problem.

Lat but mot least: If someone shrink that down to 2 CPUs in _PR and 02 in PSD an switch to an Quad CPU may run in major problems. If the user didnt remeber that shwinking or used an dsdt of someone else (shrinked) he will have trouble to finde the reason.

I merely quoted the ACPI specs in my response.

 

If you declare four cpu's and have a core2duo and have no issues then maybe it doesn't matter but unless you are certain I would stick with the ACPI specs.

 

As for changing dsdt, dont forget if you change your processor you more than likely will need to change _PSS valus too. That can be easily solved by adding a note in your DSDT such as // Change to suit processor, for _PR and _PSS.

 

Thats why I annotate my dsdt to death!! :D

 

P.S. I have added _CDC and _PTC objects to my DSDT and saw for the first time temps drop to 33-39 degrees (before 37-42).

I'll keep monitoring to see if it has really made a difference.

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mitch_de
mitch_de
Posted
Posted

"If you declare four cpu's and have a core2duo and have no issues then maybe it doesn't matter but unless you are certain I would stick with the ACPI specs."

 

In all orig. BIOS DSDT there are 4 CPUs declared for my knowledge. So that not an special OS X thing.

I would leave 4 cpus if in orig. DSDT (of the BIOS) also 4 cpus are listed.

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keeza
keeza
Posted
Posted
"If you declare four cpu's and have a core2duo and have no issues then maybe it doesn't matter but unless you are certain I would stick with the ACPI specs."

 

In all orig. BIOS DSDT there are 4 CPUs declared for my knowledge. So that not an special OS X thing.

I would leave 4 cpus if in orig. DSDT (of the BIOS) also 4 cpus are listed.

 

So if I have a C2Quad and dump my SSDT I get 4 processors.

If I have a C2Duo and dump my SSDT I get 4 processors or 2??

 

@All,

I'm working on a theory as to why my Cstates dont fully work and need to know if all cores of a quad core processor support all cstates by default.

BTW I won't ask this again :D

 

keeza

 

You can remove PSD from DSDT, in OSX it doesn't matter.

Thanks,

BTW my dsdt additions mentioned in my previous post are not added to my sig as of yet.

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marionez
marionez
Posted
Posted

I'm trying to work this out on a P5Q with E8400 cpu.

I run DSDT_Patcher1.0.1e and I obtain this:

dsdt.dsl.zip

 

This is not working, OSx hang on mac logo.

Do you have any suggestion?

 

PSTEP FID and VID values are right, there's something wrong maybe in the Processor declaration.

 

There's something interesting about E8400 here: http://www.insanelymac.com/forum/index.php...t&p=1264427

but nothing want work here...

As in that post I've got an old dsdt.dsl where the dsdt-CPU part is just:

DefinitionBlock ("dsdt.aml", "DSDT", 1, "A0993", "A0993001", 0x00000001)
{
Scope (_PR)
{
	Processor (P001, 0x01, 0x00000810, 0x06) {}
	Processor (P002, 0x02, 0x00000000, 0x00) {}
	Processor (P003, 0x03, 0x00000000, 0x00) {}
	Processor (P004, 0x04, 0x00000000, 0x00) {}
}

this will boot but everything about CPU is missing and it's not speedstepping.

 

Anyone success with an E8400?

Can you post the code and/or dsdt.dsl ?

 

This compile with errors and boot, but doesn't really speedstep in a proper way, it changes between 2GHz and 3GHz!

dsdt.dsl.zip

 

thanks

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Detrich
Detrich
Posted
Posted

marionez,

 

I think, your CPU should have more then 4 performance states(PSS), my C2D E4600, for example, have 7 p-states.

 

First, put DSDT without PSS(P5Q DSDT_noPSS.zip) in Extra folder. Install VoodooPState.kext, after reboot, run PStateChanger to get correct p-states values for your CPU(FID/VID only). Then open another DSDT(P5Q DSDT.zip) and write these values(FID/VID) under _PSS scop. Now u should have an working DSDT with native shutdown, sleep/autosleep, SATA orange icons fix and other fixes. ;)

P5Q_Fixes.zip

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marionez
marionez
Posted
Posted

Great, thanks! I can boot with your dsdt, mine was not even booting. Fixes are perfects (ICH10 becomes Intel ES82 AHCI... ? ), my E8400 is the problem actually...

 

This is about P-states of my E8400:

post-303759-1265823240_thumb.png

 

And so this is how I edited your dsdt.aml:

DSDT.dsl.zip

 

Now this is booting, but it's not stepping, it's locked on lower pstep.

 

Mmm maybe I'm wrong... wait, it's stepping

=====

UPDATE, ok this above is solved, read down...

 

Ok, now it steps with this!

DSDT.P5Q.E8400.zip

Is this ok?

 

		Processor (CPU0, 0x01, 0x00000810, 0x06)
	{
		Alias (CST, _CST)
		Alias (PSS, _PSS)
	}

	Processor (CPU1, 0x02, 0x00000000, 0x00)
	{
		Alias (CST, _CST)
		Alias (PSS, _PSS)
	}

 

CPU1 goes with zeroes...

 

Man really thank you, I think there's some other work to do on it, but this is a good point to start... :)

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Detrich
Detrich
Posted
Posted

marionez

 

CPU1 should be 06, ur 2d core is not recognized correctly, I think, the problem is not here, but in BIOS. Also please upload IORegistry dump with this DSDT, remember I have P5K board.

 

ICH10 becomes Intel ES82 AHCI... ?

 

This isn't just cosmetic, but natively solves other big problems like orange icons, HDD slow speed, shutdown(sometimes), SATA power management and others. Now u don't need to fix with 3rd part kexts.

 

I want to know, what a kexts are you using, also, why ur SL is MBR and not GUID, !?

 

PS: don't forget, to delete Voodoo kexts from the system.

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marionez
marionez
Posted
Posted

I'm on MBR because I needed winXP... :D

 

This is my "clean" dsdt from Everest:

acpi_dsdt.dsl.zip

 

What I did: I started from scratch patching this attached, USBE/EHC1 USB0/UHC1, speedstep as on DSDT.P5Q.E8400 etc, but it won't work properly.

 

Actually my goal is to reach the sleep function (not really needed, but it would be nice), that I can't have with voodoopowermini method...

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haxzion
haxzion
Posted
Posted

Hello OSX junkies i have a speedstep question..

In my case i get 2 steps same in Windows 7 and i was wondering if i can get more than 2 cause in ubuntu i can.

The only way i could get speedstep working was this..

 

    Scope (_PR)
   {
       Processor (CPU0, 0x00, 0x00000410, 0x06)
       {
           OperationRegion (PMBL, SystemMemory, 0x7FEE85A0, 0x03AB)
           Name (PDC0, 0x80000000)
           Name (HNDL, 0x80000000)
           Name (TBLD, 0x80)
           Method (_INI, 0, NotSerialized)
           {
               If (LNot (And (TBLD, One)))
               {
                   Or (TBLD, One, TBLD)
                   Load (PMBL, HNDL)
               }
           }

           Method (_CST, 0, NotSerialized)
           {
               If (And (PDC0, 0x18))
               {
                   Return (^^CPU1._CST ())
               }
               Else
               {
                   Return (Package (0x02)
                   {
                       One, 
                       Package (0x04)
                       {
                           ResourceTemplate ()
                           {
                               Register (FFixedHW, 
                                   0x00,               // Bit Width
                                   0x00,               // Bit Offset
                                   0x0000000000000000, // Address
                                   ,)
                           }, 

                           One, 
                           0x9D, 
                           0x03E8
                       }
                   })
               }
           }
       }

       Processor (CPU1, 0x01, 0x00000410, 0x06)
       {
           Method (_CST, 0, NotSerialized)
           {
               Return (Package (0x04)
               {
                   0x03, 
                   Package (0x04)
                   {
                       ResourceTemplate ()
                       {
                           Register (FFixedHW, 
                               0x01,               // Bit Width
                               0x02,               // Bit Offset
                               0x0000000000000000, // Address
                               0x01,               // Access Size
                               )
                       }, 

                       One, 
                       One, 
                       0x03E8
                   }, 

                   Package (0x04)
                   {
                       ResourceTemplate ()
                       {
                           Register (SystemIO, 
                               0x08,               // Bit Width
                               0x00,               // Bit Offset
                               0x0000000000000814, // Address
                               ,)
                       }, 

                       0x02, 
                       One, 
                       0x01F4
                   }, 

                   Package (0x04)
                   {
                       ResourceTemplate ()
                       {
                           Register (SystemIO, 
                               0x08,               // Bit Width
                               0x00,               // Bit Offset
                               0x0000000000000815, // Address
                               ,)
                       }, 

                       0x03, 
                       0x11, 
                       0xFA
                   }
               })
           }
       }
   }

 

 

i don't know how this way works but at least it gives me 2 states.

1)3059Mzh x11.5 multiplier 1.276v and 2) 1596Mhz 6x 1.052v

I'm going to include my full dsdt plus my ssdt in case someone wants to check it out

 

DSDT_SSDT.zip

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Detrich
Detrich
Posted
Posted

marionez

 

I also have XP with SL(GUID), but on different HDDs. I've tested on same HDD and all works just fine.

 

To get correct p-states for your CPU you'll need firs to delete VoodooPowerMini and VoodooMonitor from SL Extensions folder, you'll not need these anymore and 2nd core will work correctly with 06.

 

PS: sleep/autosleep/hybernate are already fixed, see my DSDT above.

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iFx
iFx
Posted
Posted

Please, help me to fix my PR section to make ss works! I spent all night to do it and get nothing) maybe thats because i'm noob.

I have e6550 - only 2 states. Everest and CPU-Z, CPU-i and pStateChanger tells me different values of voltage and freq so I cant understand how to do it.

Please, help. My DSTD (thanks to osik for most part of it):

dsdt.aml.zip

Screenshot of pstatechanger (besides, with it's kext voodoopstate SS works) and CPU-i:

post-566789-1265985348_thumb.png

p.s. I told to SMbios.plist that I am iMac7,1

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Master Chief
Master Chief
Posted
Posted
Hello OSX junkies i have a speedstep question..

In my case i get 2 steps same in Windows 7 and i was wondering if i can get more than 2 cause in ubuntu i can.

The only way i could get speedstep working was this..

...see post #1315

i don't know how this way works but at least it gives me 2 states.

1)3059Mzh x11.5 multiplier 1.276v and 2) 1596Mhz 6x 1.052v

I'm going to include my full dsdt plus my ssdt in case someone wants to check it out

You also need a _PSS object with four P-States in it because the factory one (in the SSDT) I presume has only two.

 

p.s. I see that some people here are still using my _PR scope. Interesting news.

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haxzion
haxzion
Posted
Posted

Chief your PR scope works for me even if i don't understand it.But if i add PSS obj with P States my CPU will stick with the lowest one at 1.6 GHZ.Same thing happens with other PR scopes.Maybe VoodooMonitor is giving me wrong values?

 

post-32317-1266023295_thumb.jpg post-32317-1266023330_thumb.jpg

 

2)Nvm i tried some stuff and i still get the same speedstep.

If i don't insert all 12 of my pstates the cpu will stick with the lowest frequency if i insert all 12 of them i get the same results as without PSS object..the same sppedstep i get in windows 7.

I was trying to get custom pstates but your PR scope somehow picks the defaults.Cool huh?

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Drfrag
Drfrag
Posted
Posted

Still getting hight temps with Vanilla SpeedStep Enabled. Don't know why.

Intelcpupowermanagement loaded fine so does applelpc. My CPU keep going 57ºC. (WaterCooled)

With NullCpuPowerManagement CPU I get 42ºC.

I'm currently using openhaltrestart.kext, Legacyhda.kext fakesmc.kext and platformuuid.kext on extra/extensions and RealtekR100SL.kext on S/L/E.

I'm putting my dmesg, ioreg and dsdt.dsl.

If someone could help me, it would be much appreciated.

 

Thanks

ioreg.txt.zip

dsdt.dsl.zip

dmesg.txt.zip

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gatsu_1981
gatsu_1981
Posted
Posted

 

 

Scope (_PR)
   {
       Processor (CPU0, 0x00, 0x00001010, 0x06) {}
       Processor (CPU1, 0x01, 0x00001010, 0x06) {}
   }

   Scope (_PR.CPU0)
   {
       Method (_PSS, 0, NotSerialized)
        {
           Return (Package (0x05)
           {
               Package (0x06)
               {
                   Zero, 
                   Zero, 
                   0x10, 
                   0x10, 
                   0x0A25, 
                   Zero
               }, 

               Package (0x06)
               {
                   Zero, 
                   Zero, 
                   0x10, 
                   0x10, 
                   0x0921, 
                   One
               },

	 Package (0x06)
               {
                   Zero, 
                   Zero, 
                   0x10, 
                   0x10, 
                   0x081C, 
                   0x02
               },

	 Package (0x06)
               {
                   Zero, 
                   Zero, 
                   0x10, 
                   0x10, 
                   0x0718, 
                   0x03
               },

         Package (0x06)
               {
                   Zero, 
                   Zero, 
                   0x10, 
                   0x10, 
                   0x0613, 
                   0x04
               }
           })
       }

       Method (_PSD, 0, NotSerialized)
       {
           Return (Package (0x05)
           {
               0x05, 
               Zero, 
               Zero, 
               0xFC,
               0x04
           })
       }

       Method (_CST, 0, NotSerialized)
       {
           Return (Package (0x02)
           {
               One, 
               Package (0x04)
               {
                   ResourceTemplate ()
                   {
                       Register (FFixedHW, 
                           0x01,               // Bit Width
                           0x02,               // Bit Offset
                           0x0000000000000000, // Address
                           0x01,               // Access Size
                           )
                   }, 

                   One, 
                   0x9D, 
                   0x03E8
               }
           })
       }
   }
   Scope (_PR.CPU1)
   {
       Method (_PSS, 0, NotSerialized)
       {
           Return (^^CPU0._PSS ())
       }

       Method (_PSD, 0, NotSerialized)
       {
           Return (^^CPU0._PSD ())
       }

       Method (_CST, 0, NotSerialized)
       {
           Return (Package (0x04)
           {
               0x03, 
               Package (0x04)
               {
                   ResourceTemplate ()
                   {
                       Register (FFixedHW, 
                           0x01,               // Bit Width
                           0x02,               // Bit Offset
                           0x0000000000000000, // Address
                           ,)
                   }, 
                   One, 
                   Zero, 
                   0x03E8
               }, 

               Package (0x04)
               {
                   ResourceTemplate ()
                   {
                       Register (FFixedHW, 
                           0x08,               // Bit Width
                           0x00,               // Bit Offset
                           0x0000000000000414, // Address
                           ,)
                   }, 

                   0x02, 
                   One, 
                   0x01F4
               }, 

               Package (0x04)
               {
                   ResourceTemplate ()
                   {
                       Register (FFixedHW, 
                           0x08,               // Bit Width
                           0x00,               // Bit Offset
                           0x0000000000000415, // Address
                           ,)
                   }, 

                   0x03, 
                   0x55, 
                   0xFA
               }
           })
       }
   }

 

 

 

The above fix on my Pavilion DV9000, T5500 with 5 pstates, give me the compiler error:

 

Error    4096 -                                       syntax error, unexpected PARSEOP_EXTERNAL ^

 

I'm using EvO DSDTse to compile and to edit code, is that a problem?

 

Regards.

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Silencers
Silencers
Posted
Posted

Epic thread! Thanks to everyone who participated, I've gone through it all and managed to get vanilla SpeedStep working on my ThinkPad T60p. But still I need some help. The full story is right below, and then some questions for gurus.

 

I have T60p with T7600 which is very-very close to MacBookPro2,1 configuration. The same CPU, the same chipset (ICH7-M) and video is very close (FireGL V5200 vs. Mobility X1600 - almost the same thing). But when I use MacBookPro2,1 as a model in my SMBIOS.plist, I get CPUPLimit=0x04 in my IOReg, and SpeedStep is not working and neither do C-states.

 

I've then created fake model MacBookPro2,3, copied MBP2,1 info from ACPI_SMC plugin and put it into legacy kext with some additions like PLimit=0. After that I got SpeedStep working, but no C-states.

 

I've extracted all my SSDT tables in Windows using Everest Lavalys, and tried to use _CST object in my _PR section in DSDT. The problem is that I have 3 different definitions of C-states in my SSDT, and each of those ways has different combinations - 1, 2 or 3 C-states (with 3 C-states it's either C1, C2 and C3 or C1, C2 and C4). I've tried almost every combination, but most of the time I got _CST error during boot and no CSTInfo in IOReg. A couple of times I managed to put 3 C-states and got CSTInfo and no errors during boot, but sound was stuttering and animations were very very slow. IRQ fix didn't work there.

 

I've then used _CST object from MacPro3,1 with single C1 defined there, and it worked! I got no sound problems, lower CPU temps (by 10 degrees) and working SpeedStep. Close to perfection, but not quite there.

 

So, the questions:

 

1) If I have virtually the same hardware as MBP2,1, why can't I use it as model in SMBIOS.plist? I've checked IOregs from real macs, and MBP2,1 has CPUPlimit=0x00, so where's my problem? Why do I get 0x04 there?

 

2) In my SSDT tables I have 5 P-states defined. But in VoodooMonitor I see 8 P-states. If I try to override _PSS in my DSDT, I get no SpeedStep at all. I would like to have more control there, since the plan is to play with undervoltage to reduce power consumption, but so far I didn't manage to use custom _PSS definition. Basically, if I put anything besides _CST object in the _PR section, I get no SpeedStep.

 

3) I'm currently using heavily modified DSDT.aml, SpeedStep is enabled in BIOS and I don't use DropSSDT=y. Should I put all SSDT tables into SSDT-x.aml files in /Extra, or should I append them in the bottom of DSDT or should I leave as it is now? What is the best option here? I would like to have a really bulletproof solution.

 

4) No matter what I do I cannot get Sleep working. This really kills me, 'cause I've tried pretty much everything. I have 100% vanilla /S/L/E, I use no disablers, AppleLPC, AppleHPET and AppleIntelCPUPowerManager are all loading fine. I've tried to debug, but _PST method is not even called when I try to go to Sleep. Hard drives stop spinning, Wi-Fi gets disabled, system seems to be sleeping, but the screen stays on and fan is spinning. In logs I see Sleep - AC - Success. Can this be related to CPU power management somehow? I would appreciate any help here, since it's driving me crazy.

 

Thanks in advance.

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Silencers
Silencers
Posted
Posted

Ok, in addition to everything I've written above I've tried the following:

1) Appended DSDT with SSDT tables at the bottom (removed only SATA tables, gave me compilation errors).

2) Edited _PSS tables and kept only two P-states - maximum and minimum ones.

3) Edited _CST tables to always use 3 C-states - C1, C2 and C4.

4) Disabled EIST in BIOS.

5) Booted with DropSSDT=y and checked that no SSDT tables are present in IOReg.

 

And after all those steps I still get the following picture:

post-391812-1266271821_thumb.png

 

PerformanceStateArray has only two values, but VoodooMonitor has 9 P-states! WTF?! MSR Tools show similar picture, frequency changes between 0.9GHz and 2.3Ghz in very fine steps, but should only be maximum and minimum, right?

 

I've also attached my DSDT, I has all the original SSDT parts, I've just commented out a lot of them (steps 2 and 3 from above).

dsdt.dsl.zip

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mitch_de
mitch_de
Posted
Posted
Ok, in addition to everything I've written above I've tried the following:

1) Appended DSDT with SSDT tables at the bottom (removed only SATA tables, gave me compilation errors).

2) Edited _PSS tables and kept only two P-states - maximum and minimum ones.

3) Edited _CST tables to always use 3 C-states - C1, C2 and C4.

4) Disabled EIST in BIOS.

5) Booted with DropSSDT=y and checked that no SSDT tables are present in IOReg.

 

And after all those steps I still get the following picture:

Screen_shot_2010_02_16_at_12.04.48_AM.png

 

PerformanceStateArray has only two values, but VoodooMonitor has 9 P-states! WTF?! MSR Tools show similar picture, frequency changes between 0.9GHz and 2.3Ghz in very fine steps, but should only be maximum and minimum, right?

 

I've also attached my DSDT, I has all the original SSDT parts, I've just commented out a lot of them (steps 2 and 3 from above).

dsdt.dsl.zip

 

 

If you comment out content in packages you must also check if you edited the counter for the count of packadge down !

 

I believe that your whole PR_CPU parts at the end of your dsdt are much to complex to handle . I would shrink down=make it easier much less items like mm67 or others didt it.

I dont have any SSDT from orig. BIOS included , didnt use dropssdt=Y ( i am not sure but it can be case sensitive = Y needed!) and i use EIST in BIOS enabled.

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