DSDT - Vanilla Speedstep - Generic Scope (_PR)

[polkaholga]

I've still no 100% understanding about the whole thing and try to figure this out myself.

Through the help of mm67 & FKA and reading this thread a couple of times i was lucky enough

to get this working.

Still a lot to learn for me especially when it comes to translate ACPI specs language for my

old synapses to understand...

 

 

I confirmed I have the bit but what do I do next?

Then you should have it working.

 

 

 

Anyway what did you change in your SSDT dump exactly? Once you made that change I'm guessing you used anval bootloader to boot the edits SSDT right? Dont think asereBLN can boot edited SSDT's.

 

correct me if I'm wrong.

I didn't change SSDT. I transfered the data to DSDT, and i'm not using AnVal ( see sig ! )

[Noodle09]

Hi All,

 

I'm trying to make speedstep work on my hackintosh.

 

My motherboard is: ABit IB9 (ICH8 chipset), Q6600 CPU.

 

I tried to add following into the DSDT:

 

	Scope (\_PR)
{
	Processor (\_PR.CPU0, 0x00, 0x00000410, 0x06) 
	{
		Name (_PSS, Package (0x04)
		{
			Package (0x06) { 2403, 64260, 32, 32, 0x928, 0x000 }, // Q6600 4 steps
			Package (0x06) { 2136, 55669, 32, 32, 0x826, 0x001 },
			Package (0x06) { 1869, 46806, 32, 32, 0x722, 0x002 },
			Package (0x06) { 1602, 38488, 32, 32, 0x61E, 0x003 }
		})

		  Name (_PSD, Package (0x05)
		{
			0x05,Zero,Zero,0xFC,0x04 // The last value should equal the number of CPU
		})

		Name (_CST, Package (0x02) // 1 cstate
		{
			One,
			Package (0x04) {ResourceTemplate () {Register (FFixedHW, 1, 2, 0x000)}, 1, 1, 0x03E8}
		})
	}

	Processor (\_PR.CPU1, 0x01, 0x00000410, 0x06)
	{
		Alias (\_PR.CPU0._PSS, _PSS)
		Alias (\_PR.CPU0._PSD, _PSD)
		Alias (\_PR.CPU0._CST, _CST)
	}

	Processor (\_PR.CPU2, 0x02, 0x00000410, 0x06)
	{
		Alias (\_PR.CPU0._PSS, _PSS)
		Alias (\_PR.CPU0._PSD, _PSD)
		Alias (\_PR.CPU0._CST, _CST)
	}

	Processor (\_PR.CPU3, 0x03, 0x00000410, 0x06)
	{
		Alias (\_PR.CPU0._PSS, _PSS)
		Alias (\_PR.CPU0._PSD, _PSD)
		Alias (\_PR.CPU0._CST, _CST)
	}
}

 

I also removed NullCPUPowerManage, SleepEnabler and so on. I made sure LPC kext loadded:

   58	0 0xffffff7f80f32000 0x3000	 0x3000	 com.apple.driver.AppleLPC (1.4.12) <9 5 4 3>

But still, I got KP like:

CPU 1 has no HPET assigned to it

or

CPU 2 has no HPET assigned to it

 

I attached my DSDT file, and hope somebody can help me to take a look. BTW, I'm running 10.6.4, MacPro3,1.

 

Thanks a lot

 

Noodle

DSDT.zip

[ovof]

Hi all,

 

i've got an P5LD2-VM SE with E4600

 

I put code in DSDT with 7 pstates, and add device to get LPC working.

 

Since i put the code, VoodooMonitor crash at start now, so i cant see if vanilla speedstep is working !!! How can i check this ? THanks (i tried CPUX - no fred update)

 

Thanks

 

 

 

 

 

Exception Type: EXC_CRASH (SIGABRT)

Exception Codes: 0x0000000000000000, 0x0000000000000000

Crashed Thread: 0 Dispatch queue: com.apple.main-thread

 

Application Specific Information:

abort() called

*** Terminating app due to uncaught exception 'NSInvalidArgumentException', reason: '-[NSCFArray size]: unrecognized selector sent to instance 0x100212040'

*** Call stack at first throw:

(

0 CoreFoundation 0x00007fff878e0d24 __exceptionPreprocess + 180

1 libobjc.A.dylib 0x00007fff857210f3 objc_exception_throw + 45

2 CoreFoundation 0x00007fff8793a160 +[NSObject(NSObject) doesNotRecognizeSelector:] + 0

3 CoreFoundation 0x00007fff878b2d3f ___forwarding___ + 751

4 CoreFoundation 0x00007fff878aee88 _CF_forwarding_prep_0 + 232

5 AppKit 0x00007fff846f0b14 -[NSApplication _setApplicationIconImage:setDockImage:] + 51

6 VoodooMonitor 0x0000000100001c36 -[statusController updateEvent:] + 523

7 VoodooMonitor 0x0000000100001212 -[statusController awakeFromNib] + 105

8 CoreFoundation 0x00007fff8788f4dd -[NSSet makeObjectsPerformSelector:] + 205

9 AppKit 0x00007fff84571227 -[NSIBObjectData nibInstantiateWithOwner:topLevelObjects:] + 1445

10 AppKit 0x00007fff8456f45d loadNib + 226

11 AppKit 0x00007fff8456e96d +[NSBundle(NSNibLoading) _loadNibFile:nameTable:withZone:ownerBundle:] + 248

12 AppKit 0x00007fff8456e7a5 +[NSBundle(NSNibLoading) loadNibNamed:owner:] + 326

13 AppKit 0x00007fff8456bd27 NSApplicationMain + 279

[kdawg]

For those willing to live on the cutting edge. There's a version of Chameleon with built in C and P state support. It's still being actively developed but if you want to give it a try it's in the SVN repository.

 

https://www.assembla.com/code/fakesmc/subve...ameleon?rev=345

[FKA]

For those willing to live on the cutting edge. There's a version of Chameleon with built in C and P state support. It's still being actively developed but if you want to give it a try it's in the SVN repository.

 

http://www.assembla.com/code/fakesmc/

 

Hay kdawg,

 

Bad link mate ..

 

https://www.assembla.com/code/fakesmc/subve...ameleon?rev=345

 

D.

[kdawg]

Hay kdawg,

 

Bad link mate...

Thanks I updated my post. That's what I get trying to post stuff with my iPhone.

[FKA]

Thanks I updated my post. That's what I get trying to post stuff with my iPhone.

 

LOL - unfortunately my company don't deem an iphone as necessary and I'm not convinced enough to buy one, yet!

 

Great news that speedstep is being integrated into chameleon. It's about time this thread died!

 

D

[kiwonks]

In general: Why is it that people here keep skipping mighty important topics at hand... like having SBUS in DSDT. I simply don't get it.

 

I did add the missing SBUS to my dsdt.dsl last week, and I tell you this: reading the "Intel I/O Controller Hug 9 (ICH9) Family" was a real eye opener. No. I don't like to copy/paste stuff info my dsdt.dsl Not without knowing what it does. Even if it takes me four hours of reading to grasp the meaning of it. At least now I understand what it does. That's the beauty of reading.

 

SBUS Goodies

I'm not going into much detail right now, but let's look at what adding SBUS in DSDT does (using kextstat):

 

Without SMBUS it loads the following extra kexts:

 

com.apple.driver.AppleIntelMeromProfile

com.apple.driver.AppleIntelNehalemProfile

com.apple.driver.AppleIntelYonahProfile

 

com.apple.driver.AppleTyMCEDriver

com.apple.driver.AppleMCEDriver

com.apple.driver.AppleFileSystemDriver

com.apple.driver.AppleHDAPlatformDriver

 

With SMBUS it loads the following extra kexts - not the kexts mentioned above:

 

com.apple.driver.AppleSMBusPCI

com.apple.iokit.IOSMBusFamily

com.apple.driver.AppleSMBusController

 

com.apple.driver.AppleMikeyDriver

com.apple.driver.AppleMikeyHIDDriver

 

The first three kexts should be clear, but the latter two might not be needed – giving me two sound assertions – though I have yet to check this myself.

 

In other words: It now knows what kext to load for the processor. It won't have to load all four kexts anymore. Just com.apple.driver.AppleIntelPenrynProfile for my hack. But more importantly... enter MacPro4,1 without using a disabler for AppleTyMCEDriver.kext or the need to remove it without a Nehalem CPU.

 

i've no SMBUS in lspci, when i add sbus in dsdt, it not working.

 

bash-3.2$ lspci -nn

00:00.0 Host bridge [0600]: Intel Corporation Mobile 4 Series Chipset Memory Controller Hub [8086:2a40] (rev 07)

00:01.0 PCI bridge [0604]: Intel Corporation Mobile 4 Series Chipset PCI Express Graphics Port [8086:2a41] (rev 07)

00:1a.0 USB Controller [0c03]: Intel Corporation 82801I (ICH9 Family) USB UHCI Controller #4 [8086:2937] (rev 03)

00:1a.1 USB Controller [0c03]: Intel Corporation 82801I (ICH9 Family) USB UHCI Controller #5 [8086:2938] (rev 03)

00:1a.2 USB Controller [0c03]: Intel Corporation 82801I (ICH9 Family) USB UHCI Controller #6 [8086:2939] (rev 03)

00:1a.7 USB Controller [0c03]: Intel Corporation 82801I (ICH9 Family) USB2 EHCI Controller #2 [8086:293c] (rev 03)

00:1b.0 Audio device [0403]: Intel Corporation 82801I (ICH9 Family) HD Audio Controller [8086:293e] (rev 03)

00:1c.0 PCI bridge [0604]: Intel Corporation 82801I (ICH9 Family) PCI Express Port 1 [8086:2940] (rev 03)

00:1c.1 PCI bridge [0604]: Intel Corporation 82801I (ICH9 Family) PCI Express Port 2 [8086:2942] (rev 03)

00:1c.2 PCI bridge [0604]: Intel Corporation 82801I (ICH9 Family) PCI Express Port 3 [8086:2944] (rev 03)

00:1c.5 PCI bridge [0604]: Intel Corporation 82801I (ICH9 Family) PCI Express Port 6 [8086:294a] (rev 03)

00:1d.0 USB Controller [0c03]: Intel Corporation 82801I (ICH9 Family) USB UHCI Controller #1 [8086:2934] (rev 03)

00:1d.1 USB Controller [0c03]: Intel Corporation 82801I (ICH9 Family) USB UHCI Controller #2 [8086:2935] (rev 03)

00:1d.2 USB Controller [0c03]: Intel Corporation 82801I (ICH9 Family) USB UHCI Controller #3 [8086:2936] (rev 03)

00:1d.7 USB Controller [0c03]: Intel Corporation 82801I (ICH9 Family) USB2 EHCI Controller #1 [8086:293a] (rev 03)

00:1e.0 PCI bridge [0604]: Intel Corporation 82801 Mobile PCI Bridge [8086:2448] (rev 93)

00:1f.0 ISA bridge [0601]: Intel Corporation ICH9M-E LPC Interface Controller [8086:2917] (rev 03)

00:1f.2 IDE interface [0101]: Intel Corporation ICH9M/M-E 2 port SATA IDE Controller [8086:2928] (rev 03)

00:1f.5 IDE interface [0101]: Intel Corporation ICH9M/M-E 2 port SATA IDE Controller [8086:292d] (rev 03)

01:00.0 VGA compatible controller [0300]: nVidia Corporation G94 [GeForce 9800M GS] [10de:062b] (rev a1)

03:00.0 Network controller [0280]: Intel Corporation Wireless WiFi Link 5100 [8086:4232]

06:00.0 Ethernet controller [0200]: Realtek Semiconductor Co., Ltd. RTL8111/8168B PCI Express Gigabit Ethernet controller [10ec:8168] (rev 02)

07:01.0 FireWire (IEEE 1394) [0c00]: Ricoh Co Ltd R5C832 IEEE 1394 Controller [1180:0832] (rev 05)

07:01.1 SD Host controller [0805]: Ricoh Co Ltd R5C822 SD/SDIO/MMC/MS/MSPro Host Adapter [1180:0822] (rev 22)

07:01.2 System peripheral [0880]: Ricoh Co Ltd R5C843 MMC Host Controller [1180:0843] (rev 12)

07:01.3 System peripheral [0880]: Ricoh Co Ltd R5C592 Memory Stick Bus Host Adapter [1180:0592] (rev 12)

07:01.4 System peripheral [0880]: Ricoh Co Ltd xD-Picture Card Controller [1180:0852] (rev 12)

 

but in Win 7 x64 it shown:

 

[ Intel 82801IB ICH9 - SMBus Controller [A-3] ]

 

Device Properties:

Device Description Intel 82801IB ICH9 - SMBus Controller [A-3]

Bus Type PCI

Bus / Device / Function 0 / 31 / 3

Device ID 8086-2930

Subsystem ID 1043-19A7

Device Class 0C05 (SMBus Controller)

Revision 03

Fast Back-to-Back Transactions Supported, Disabled

 

[MacKonsti]

Good morning to all. I purchased the Gigabyte GA-P55M-UD4 with a Core i7-860 processor running at nominal 2.80GHz and I am looking around the DSDT code for speed-stepping, just like you guys helped with my current mobo for the Q9550 processor. I really want to remove NullCPUPowerManagement.kext!

 

I tried installing VoodooMonitor.kext and it causes a KP. This proggie helped me some time ago to get the values for the DSDT section (_PSS) for my Q9550.

 

Can anyone with a stable, working solution post the whole Scope (\_PR) for this Core i7-860 processor? (no overclocking)

 

Many thanks in advance.

 

EDIT: I plan to set smbios.plist as iMac11,1 obviously...

[iFIRE]

Hello ,I have one problem with my Native Speedstep, is impossible what work for me, I use Smbios iMac 11.1 of the [url="http://www.insanelymac.com/forum/topic/279450-why-insanelymac-does-not-support-tonymacx86/"]#####[/url], DSDT.aml P55 UD6 F10 and this not work for me, please some look my zip and you have more information for this problem, i no use any disabler kext, and AppleIntelCPUPowerManagement.kext I Have KP, I not understand why this not work for me. Please look my zip, have my extra and kexts and others screenshots.

 

 

Thanks

 

 

http://cl.ly/03a6b1eff146a76a3965

[sirbow2]

i have a AMD Phenom II X6 1055T how do i enable APPLELPC via DSDT. i have tried the "Device ID" trick but it doesnt work. i have done DSDT mods so im not a total DSDT noob.

how do i check what my cpu is currently running at, like in Ghz

 

what do i do to enable correct temperature readings of the mobo, cpu etc via DSDT

 

i ve searched for these things but i havent found anything to help

 

LSPCI output:

00:00.0 Host bridge [0600]: Advanced Micro Devices [AMD] RS780 Host Bridge Alternate [1022:9601]
00:02.0 PCI bridge [0604]: Advanced Micro Devices [AMD] RS780 PCI to PCI bridge (ext gfx port 0) [1022:9603]
00:05.0 PCI bridge [0604]: Advanced Micro Devices [AMD] RS780 PCI to PCI bridge (PCIE port 1) [1022:9605]
00:0a.0 PCI bridge [0604]: Advanced Micro Devices [AMD] RS780 PCI to PCI bridge (PCIE port 5) [1022:9609]
00:11.0 SATA controller [0106]: ATI Technologies Inc SB700/SB800 SATA Controller [AHCI mode] [1002:4391] (rev 40)
00:12.0 USB Controller [0c03]: ATI Technologies Inc SB700/SB800 USB OHCI0 Controller [1002:4397]
00:12.2 USB Controller [0c03]: ATI Technologies Inc SB700/SB800 USB EHCI Controller [1002:4396]
00:13.0 USB Controller [0c03]: ATI Technologies Inc SB700/SB800 USB OHCI0 Controller [1002:4397]
00:13.2 USB Controller [0c03]: ATI Technologies Inc SB700/SB800 USB EHCI Controller [1002:4396]
00:14.0 SMBus [0c05]: ATI Technologies Inc SBx00 SMBus Controller [1002:4385] (rev 41)
00:14.2 Audio device [0403]: ATI Technologies Inc SBx00 Azalia (Intel HDA) [1002:4383] (rev 40)
00:14.3 ISA bridge [0601]: ATI Technologies Inc SB700/SB800 LPC host controller [1002:439d] (rev 40)
00:14.4 PCI bridge [0604]: ATI Technologies Inc SBx00 PCI to PCI Bridge [1002:4384] (rev 40)
00:14.5 USB Controller [0c03]: ATI Technologies Inc SB700/SB800 USB OHCI2 Controller [1002:4399]
00:15.0 PCI bridge [0604]: ATI Technologies Inc Unknown device [1002:43a0]
00:16.0 USB Controller [0c03]: ATI Technologies Inc SB700/SB800 USB OHCI0 Controller [1002:4397]
00:16.2 USB Controller [0c03]: ATI Technologies Inc SB700/SB800 USB EHCI Controller [1002:4396]
00:18.0 Host bridge [0600]: Advanced Micro Devices [AMD] Family 10h [Opteron, Athlon64, Sempron] HyperTransport Configuration [1022:1200]
00:18.1 Host bridge [0600]: Advanced Micro Devices [AMD] Family 10h [Opteron, Athlon64, Sempron] Address Map [1022:1201]
00:18.2 Host bridge [0600]: Advanced Micro Devices [AMD] Family 10h [Opteron, Athlon64, Sempron] DRAM Controller [1022:1202]
00:18.3 Host bridge [0600]: Advanced Micro Devices [AMD] Family 10h [Opteron, Athlon64, Sempron] Miscellaneous Control [1022:1203]
00:18.4 Host bridge [0600]: Advanced Micro Devices [AMD] Family 10h [Opteron, Athlon64, Sempron] Link Control [1022:1204]
01:00.0 VGA compatible controller [0300]: ATI Technologies Inc Unknown device [1002:6899]
01:00.1 Audio device [0403]: ATI Technologies Inc Unknown device [1002:aa50]
02:00.0 USB Controller [0c03]: NEC Corporation Unknown device [1033:0194] (rev 03)
03:00.0 Ethernet controller [0200]: Realtek Semiconductor Co., Ltd. RTL8111/8168B PCI Express Gigabit Ethernet controller [10ec:8168] (rev 03)
04:0e.0 FireWire (IEEE 1394) [0c00]: Texas Instruments TSB43AB23 IEEE-1394a-2000 Controller (PHY/Link) [104c:8024]
05:00.0 SATA controller [0106]: JMicron Technologies, Inc. JMicron 20360/20363 AHCI Controller [197b:2363] (rev 02)
05:00.1 IDE interface [0101]: JMicron Technologies, Inc. JMicron 20360/20363 AHCI Controller [197b:2363] (rev 02)

[Gringo Vermelho]

how do i enable APPLELPC via DSDT.

how do i check what my cpu is currently running at, like in Ghz

what do i do to enable correct temperature readings of the mobo, cpu etc via DSDT

 

You need Intel CPU+motherboard chipset to do that on OS X. This thread is not called 'Intel Speedstep' for nothing.

 

Ladies and Gentlemen, the future has arrived.

 

Today I got native P- and C-states *perfectly working* with Chameleon 2.0 RC5 rev 318:

http://www.insanelymac.com/forum/index.php...t&p=1525596

 

I put back the CPU scope from my vanilla DSDT and took out all the speedstepping code that I've painstakingly worked on for hours and hours. Hours of reading this thread and many other DSDT threads, tinkering with C-state latencies, calculating voltages.. losing hair.. ..going insane..

 

It's amazing.. it just..works.. w000t dudes, look at that Hackintosh go!!

[anibalin]

Guys, regarding AppleSMBusPCI.kext, I dont see it loaded when I do a kextstat

 

lspci -nn pops:

00:1f.3 SMBus [0c05]: Intel Corporation Ibex Peak SMBus Controller [8086:3b30] (rev 05)

 

my dsdt has:

			Device (SBUS)
		{
			Name (_ADR, 0x001F0003)
			Method (_DSM, 4, NotSerialized)
			{
				Store (Package (0x02)
					{
						"device-id", 
						Buffer (0x04)
						{
							0x30, 0x3B, 0x00, 0x00
						}
					}, Local0)
				DTGP (Arg0, Arg1, Arg2, Arg3, RefOf (Local0))
				Return (Local0)
			}
		}

 

AppleSMBusPCI presents this IONameMatch

			<array>
			<string>pci10de,aa2</string>
			<string>pci10de,d79</string>
			<string>pci8086,3a30</string>
			<string>pci8086,3b30</string>
		</array>

 

Therefore I dont see why im not getting it loaded?

dp55wb / core i5 650

ChameleonRC5 318 / imac 11.1 /10.6.4

 

Thanks for any hint.

 

edit:

With this:

			Device (SBUS)
		{
			Name (_ADR, 0x001F0003)
			Device (BUS0)
			{
				Name (_CID, "smbus")
				Name (_ADR, Zero)
				Device (DVL0)
				{
					Name (_ADR, 0x57)
					Name (_CID, "diagsvault")
				}
			}
		}

 

I get it loaded:

   46	0 0xffffff7f807dc000 0x2000	 0x2000	 com.apple.driver.AppleSMBusPCI (1.0.8d0) <9 5 4 3>

[Eisofen]

Can anyone with a stable, working solution post the whole Scope (\_PR) for this Core i7-860 processor? (no overclocking)

 

Many thanks in advance.

 

EDIT: I plan to set smbios.plist as iMac11,1 obviously...

 

I'm using iMac11,1 in my smbios.plist an I got Speedstep w/o any DSDT-editing. I see speed changing in K-Stat-i (with new fakesmc) under load. I tried it over the weekend, but gave up since I couldn't tackle the stuttering sound with Speedstep in DSDT. And when I've fixed it USB gave me headaches. So I left it alone, removed AppleIntelCPUPowermanagement, rebooted, bingo!

Board used: GA-P35-DS3P Bios F12. May iMac11,1 reads out the SSDTs just fine?

Temp goes up to 40°C max. when Overclocked.

[FKA]

I'm using iMac11,1 in my smbios.plist an I got Speedstep w/o any DSDT-editing. I see speed changing in K-Stat-i (with new fakesmc) under load. I tried it over the weekend, but gave up since I couldn't tackle the stuttering sound with Speedstep in DSDT. And when I've fixed it USB gave me headaches. So I left it alone, removed AppleIntelCPUPowermanagement, rebooted, bingo!

Board used: GA-P35-DS3P Bios F12. May iMac11,1 reads out the SSDTs just fine?

Temp goes up to 40°C max. when Overclocked.

 

If you want speedstep use chameleon2 pre5

[sirbow2]

i know this is a INTEL thread but it just a quick question for my AMD

 

i know speed stepping/ throttling isn't available for AMD CPU's but could i some how set My cpu to run a certain speed all the time instead of running a full speed, because i dont need my hexa core cranking at 2.8Ghz (times six cores) all the time. my lowest stepping is 800MHZ this would be a great permanent speed!

[MacUser2525]

i know this is a INTEL thread but it just a quick question for my AMD

 

i know speed stepping/ throttling isn't available for AMD CPU's but could i some how set My cpu to run a certain speed all the time instead of running a full speed, because i dont need my hexa core cranking at 2.8Ghz (times six cores) all the time. my lowest stepping is 800MHZ this would be a great permanent speed!

 

So go into your BIOS and lower one or both of the multiplier and FSB to get the result you want, while your at it you may as well see how low the voltage will go while still being stable it's called underclocking.

[sirbow2]

i know what "underclocking" is, i just dont want to change that every time i want to go into windows

[cybercap]

Hello guys,

 

you can easily apply this patch to your DSDT using this editor.

 

Here is the patch in the automated patcher format

SpeedStep.zip

Choose cpu0-3 if your DSDT has CPU0, CPU1, CPU2 and CPU3

 

Choose cpu1-4 if your DSDT has CPU1, CPU2, CPU3 and CPU4

 

There are files with 3 and 4 P-states, you just have to fill the FID and VID values for each state. If you add more states, remember to fix the package size.

 

Here for the Q6600 CPU

Q6600.zip

And here the LPC device-id patch, if you need it

LPC.txt.zip

Hope it helps the less experienced with DSDT patching.

 

Regards.

Hello

 

just arrived in this thread

 

I have a Q6600 overclocked to 3,0ghz . I've noticed that whatever the cpu vcore i set in bios, when SL boots it overrides my setting

here is what pstatechanger reads.

I'm running 48° with a noctua u12 heatsink

 

what modifications should i make (dsdt, kext loading) to enjoy the benefit of best speedstep (and power when i need it)

all in bios is set to enabled regarding C1E and all that stuff

 

thank you

[psychonautuk]

Hi, could someone help me out with my compiling for a GA-P35-DS4 with an E8200 chip?

 

When I do the first part of the coding, copying and pasting the code in following the instructions I get the following error

 

/Users/fran/Library/Application Support/EvOSoftware/DSDT/DSDTFiles/dsdt.dsl 69: Name (_S0, Package (0x04)

Error 4096 - syntax error, unexpected PARSEOP_NAME ^

 

/Users/fran/Library/Application Support/EvOSoftware/DSDT/DSDTFiles/dsdt.dsl 5838: [*** iASL: Read error on source code temp file /Users/fran/Library/Application Support/EvOSoftware/DSDT/DSDTFiles/dsdt.src ***]

Error 4096 - syntax error, unexpected $end ^

 

I cant for the life of me figure out why this is.

 

I have attached the offending code if some one could have a look? Thanks

 

 

    Scope (_PR)
   {
       Processor (CPU0, 0x00, 0x00000410, 0x06) {}
       Processor (CPU1, 0x01, 0x00000410, 0x06) {}
       Processor (CPU2, 0x02, 0x00000410, 0x06) {}
       Processor (CPU3, 0x03, 0x00000410, 0x06) {}
   }
   Scope (_PR.CPU0)

   {

       Method (_PSS, 0, NotSerialized)

       {

           Return (Package (0x03)

           {

               Package (0x06)

               {

                   Zero, 

                   Zero, 

                   0x10, 

                   0x10, 

                   0x0820, 

                   Zero

               }, 



               Package (0x06)

               {

                   Zero, 

                   Zero, 

                   0x10, 

                   0x10, 

                   0x071D, 

                   One

               }, 



               Package (0x06)

               {

                   Zero, 

                   Zero, 

                   0x10, 

                   0x10, 

                   0x061A, 

                   0x02

               }

           })

       }



       Method (_PSD, 0, NotSerialized)

       {

           Return (Package (0x05)

           {

               0x05, 

               Zero, 

               Zero, 

               0xFC, 

               0x04

           })

       }



       Method (_CST, 0, NotSerialized)

       {

           Return (Package (0x02)

           {

               One, 

               Package (0x04)

               {

                   ResourceTemplate ()

                   {

                       Register (FFixedHW, 

                           0x01,               // Bit Width

                           0x02,               // Bit Offset

                           0x0000000000000000, // Address

                           0x01,               // Access Size

                           )

                   }, 



                   One, 

                   0x9D, 

                   0x03E8

               }

           })

       }

   }
}
   Scope (_PR.CPU1)

   {

       Method (_PSS, 0, NotSerialized)

       {

           Return (^^CPU0._PSS ())

       }



       Method (_PSD, 0, NotSerialized)

       {

           Return (^^CPU0._PSD ())

       }



       Method (_CST, 0, NotSerialized)

       {

           Return (Package (0x04)

           {

               0x03, 

               Package (0x04)

               {

                   ResourceTemplate ()

                   {

                       Register (FFixedHW, 

                           0x01,               // Bit Width

                           0x02,               // Bit Offset

                           0x0000000000000000, // Address

                           ,)

                   }, 



                   One, 

                   Zero, 

                   0x03E8

               }, 



               Package (0x04)

               {

                   ResourceTemplate ()

                   {

                       Register (FFixedHW, 

                           0x08,               // Bit Width

                           0x00,               // Bit Offset

                           0x0000000000000414, // Address

                           ,)

                   }, 



                   0x02, 

                   One, 

                   0x01F4

               }, 



               Package (0x04)

               {

                   ResourceTemplate ()

                   {

                       Register (FFixedHW, 

                           0x08,               // Bit Width

                           0x00,               // Bit Offset

                           0x0000000000000415, // Address

                           ,)

                   }, 



                   0x03, 

                   0x55, 

                   0xFA

               }

           })

       }

   }

   Name (_S0, Package (0x04)
   {
       Zero, 
       Zero, 
       Zero, 
       Zero
   })

 

Thanks

[polkaholga]

I cant for the life of me figure out why this is.

 

I have attached the offending code if some one could have a look? Thanks

 

 

Type manually, don't copy and paste b/c often you get hidden characters inside.

 

Try something like this...

Scope (_PR)
{
   Processor (CPU0,0x00,0x00000410,0x06)
   {
        Name (_PSS, Package (0x06) →→ according to your # of P-States !
        {
              Your Packages !
         })
         Name (_PSD, Package (0x05){0x05,Zero,Zero,0xFC,0x04})
         Name (_CST, Package (0x04) →→ according to your # of  C-States !
         {
                Your Packages !
          })
    }

    Processor (CPU1, 0x01,0x00000410,0x06)
    {
         Alias (∧CPU0._PSS,_PSS)
         Alias (∧CPU0._PSD,_PSD)
         Alias (∧CPU0._CST,_CST)
    }

    Repeat last section for CPU2 and CPU3  
}

Name (_S0, Package (0x04)
{
    etc….
    etc….

[EnzoFX]

I think this stuff is over my head =P but looks like great progress. I will have to read more of these posts...

 

but it seems like I should be using the DropSSDT=Y, even though hack is functional without it, and not simply disable EIST because I also use Windows...

[Gringo Vermelho]

If you want native P- and C-states these days the odds are very good that you can leave your DSDT alone and just install the latest revision of Chameleon 2.0 RC5, add a few lines to com.apple.Boot.plist and off you go.

 

It doesn't matter what C-state or P-state settings you enable or disable in the BIOS because you can have Chameleon override this by loading SSDT tables.

 

More information in the Chameleon 2.0 RC5 thread in the new releases forum.

[derpuma]

Can anybody show me a solution for a working speedstep with my T7500 C2D M CPU?

I got a HP 6710b Notebook and everything works so far except speedstep!

I tried the legacy Speed Step Kext from here LINK which is not working.

Using NullCPUPowerManagement.kext does not do a good job too!

I would like to see a DSDT Fix for the T7500 CPU, nut I do not have any idea how to fix it.

Any help?

[Time2Retire]

I was wondering if anyone can help me with something. Shouldn't I also include Method (_PCT) in my DSDT since it is also included in the Mac ACPI tables? I understand that Mac's can run Windows/Linux as well, so maybe we don't need it? How can you tell? Here's mine:

        Method (_PCT, 0, NotSerialized)
       {
           If (LAnd ([color="#2E8B57"][b]And (CFGD, One[/b][/color]), [color="#FF0000"][b]And (PDC0, One)[/b][/color]))
           {
               Return (Package (0x02)
               {
                   ResourceTemplate ()
                   {
                       Register (FFixedHW, 
                           0x00,               // Bit Width
                           0x00,               // Bit Offset
                           0x0000000000000000, // Address
                           ,)
                   }, 

                   ResourceTemplate ()
                   {
                       Register (FFixedHW, 
                           0x00,               // Bit Width
                           0x00,               // Bit Offset
                           0x0000000000000000, // Address
                           ,)
                   }
               })
           }

           Return (Package (0x02)
           {
               ResourceTemplate ()
               {
                   Register (SystemIO, 
                       0x10,               // Bit Width
                       0x00,               // Bit Offset
                       0x0000000000000800, // Address
                       ,)
               }, 

               ResourceTemplate ()
               {
                   Register (SystemIO, 
                       0x08,               // Bit Width
                       0x00,               // Bit Offset
                       0x00000000000000B3, // Address
                       ,)
               }
           })
       }

Also. I found this table in post #71 which reads:

 

"If set, OSPM is capable of direct access to Performance State MSR's"

 

But I don't know what "Performance State MSR's" are. Where can I find info about it? Is that supported on my Intel i3-350m?

 

Anyone?

Edit: The Intel i3 datasheet reveals that it is used. Seems I need this, but it is not included with any of the examples here. Error?