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DSDT - Vanilla Speedstep - Generic Scope (_PR)

FKA

By FKA,
in Power Management

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Silencers
Silencers
Posted
Posted
If you comment out content in packages you must also check if you edited the counter for the count of packadge down !

 

I believe that your whole PR_CPU parts at the end of your dsdt are much to complex to handle . I would shrink down=make it easier much less items like mm67 or others didt it.

I dont have any SSDT from orig. BIOS included , didnt use dropssdt=Y ( i am not sure but it can be case sensitive = Y needed!) and i use EIST in BIOS enabled.

 

Well, I believe I did change the counter (is it in _PSD method?), the problem is that I can't understand where those 9 P-states I see in VoodooMonitor are coming from, even before edit my SSDT had only 5.

 

_PR parts in the end are mostly either commented out or they have Name() objects defined which are not used (just kept them for easy of experimenting). I tried to use short examples from this thread and SpeedStep stopped working.

 

I also have other stuff there, which I don't know what for, like _TSS and _TSD methods. They are probably related to throttling, but I'm not sure how important they are for the whole vanilla speedstep in my setup.

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peakymonster
peakymonster
Posted
Posted

I appear to have vanilla speedstep working on my fujitsu siemens AMILO XI 3650.

 

I appears to be shifting through the p-states and c-states are also working

 

I have changed the model in smbios.plist to MacBookPro5,1 and also changed lpc kext to the proper id to

get lpc kext to load.

 

Everything works great but one problem it just seems to randomly freeze could be 10min could be 30 seconds

 

Cant figure out whats causing it . according to coolbook the correct steps and voltages are being used

 

The macbookpro 5,1 has the same cpu which is a p8600 2.4ghz

 

Is it a cpu issue or could it be the gpu which is a geforce 9600m gt cant see its temp in osx

 

could it be overheating , anybody know whats causing the random freezing ?

 

 

 

 

System spec

 

cpu intel core2duo P8600 2.4 ghz

memory 4gb dd3 1066mhz memory

Hd 2x 500gb scorpio blue 5400rpm

geforce 9600m gt + intel 4 series graphics Hybrid

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anibalin
anibalin
Posted
Posted

I have been fighting this since yesterday. Cannt understand why it isnt working. GB 965P-DS3 / ICH8.

Tweaked the dsdt with usual fixes.

All its ok -But I cannot make the system to work without the use NullCPUPowerManagement.

If I took it away I get this beautiful KP.

speedstep.jpg

 

This are my settings:

Screen%20shot%202010-02-24%20at%207.41.27%20PM.png

 

dsdt file http://dl.dropbox.com/u/363153/965/dsdt.aml

Thanks for any hint guys. Im puzzled.

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MacUser2525
MacUser2525
Posted
Posted
I have been fighting this since yesterday. Cannt understand why it isnt working. GB 965P-DS3 / ICH8.

Tweaked the dsdt with usual fixes.

All its ok -But I cannot make the system to work without the use NullCPUPowerManagement.

If I took it away I get this beautiful KP.

 

dsdt file http://dl.dropbox.com/u/363153/965/dsdt.aml

Thanks for any hint guys. Im puzzled.

 

You have not fixed your HPET device and while your at it since you have Gigabyte board check the Length of the RTC it should be the 0x02 to prevent the CMOS reset bug oh and you will be better of posting the .dsl file so people don't have to decompile before reading it...

 

				Device (HPET)
			{
				Name (_HID, EisaId ("PNP0103"))
				Name (ATT3, ResourceTemplate ()
				{
					IRQNoFlags ()
						{0}
					IRQNoFlags ()
						{8}
					Memory32Fixed (ReadWrite,
						0xFED00000,		 // Address Base
						0x00000400,		 // Address Length
						)
				})
				Method (_STA, 0, NotSerialized)
				{
					Return (0x0F)
				}

				Method (_CRS, 0, NotSerialized)
				{
					Return (ATT3)
				}
			}

			Device (RTC)
			{
				Name (_HID, EisaId ("PNP0B00"))
				Name (_CRS, ResourceTemplate ()
				{
					IO (Decode16,
						0x0070,			 // Range Minimum
						0x0070,			 // Range Maximum
						0x00,			   // Alignment
						0x02,			   // Length
						)
				})
			}

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gatsu_1981
gatsu_1981
Posted
Posted

I have gotten my speedstep to work, i corrected LPC, I inserted SBUS, I got correct reading and everything.

 

Two thing, one was my problem: I have to write inside _CST method this way, otherwise DSDTSE won't compile and will spit out error.

 

Register (FFixedHW, 0x01, 0x02, 0x0000000000000000, 0x01)

 

No text after "//", no useless "," inside, and everything will compile good.

 

The second, BIG thing is... My hackintosh now has really slowed down!

Expose, dock and pressing space bar on icons is not smooth as before... It's not smooth at all!

PStates are working good, I monitored during normal usage with voodoomonitor and the cores change states very smoothly, no problem, and during benchmark my CPU will top to 100%.

 

I've got an overclocked Q6600 @ 3000 Mhz.

 

I noticed that before fixing my speedstep, Voodoo monitor won't load very well. Usually it loaded very slowly, and crash 8 time on 10!

Now it starts as soon as I click on the icon.

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gatsu_1981
gatsu_1981
Posted
Posted

Fixed this way:

 

"If you get audio stuttering or audio glitches with this fix, then You have also to remove the IRQ to

Device (TMR)/(TIMR) and Device (PIC)/(IPIC)"

 

This advice was in DSDTSE inside the SBRG/LPCB Fix text.

 

Removing IRQ bringed back my old smoothness :)

 

Now I am really happy, not half happy ;)

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anibalin
anibalin
Posted
Posted
You have not fixed your HPET device and while your at it since you have Gigabyte board check the Length of the RTC it should be the 0x02 to prevent the CMOS reset bug oh and you will be better of posting the .dsl file so people don't have to decompile before reading it...

 

				Device (HPET)
			{
				Name (_HID, EisaId ("PNP0103"))
				Name (ATT3, ResourceTemplate ()
				{
					IRQNoFlags ()
						{0}
					IRQNoFlags ()
						{8}
					Memory32Fixed (ReadWrite,
						0xFED00000,		 // Address Base
						0x00000400,		 // Address Length
						)
				})
				Method (_STA, 0, NotSerialized)
				{
					Return (0x0F)
				}

				Method (_CRS, 0, NotSerialized)
				{
					Return (ATT3)
				}
			}

			Device (RTC)
			{
				Name (_HID, EisaId ("PNP0B00"))
				Name (_CRS, ResourceTemplate ()
				{
					IO (Decode16,
						0x0070,			 // Range Minimum
						0x0070,			 // Range Maximum
						0x00,			   // Alignment
						0x02,			   // Length
						)
				})
			}

 

 

Hi mate, I dont get I, I sure do have HPET fixed (and the RTC too) in the dsdt:

Screen%20shot%202010-02-26%20at%207.50.43%20AM.png

Screen%20shot%202010-02-26%20at%207.51.36%20AM.png

 

(And it does compile without errors/warnings of course)

.dsl http://dl.dropbox.com/u/363153/965/dsdt.dsl

Thanks for your time mate.

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Master Chief
Master Chief
Posted
Posted
...I dont get I, I sure do have HPET fixed (and the RTC too) in the dsdt

You want something like this: 

                Device (HPET)
               {
                   Name (_HID, EisaId ("PNP0103"))
                   Name (_STA, 0x0F)
                   Name (_CRS, ResourceTemplate ()
                   {
                       IRQNoFlags ()
                           {0}
                       IRQNoFlags ()
                           {8}
                       Memory32Fixed (ReadOnly,
                           0xFED00000,         // Address Base
                           0x00000400,         // Address Length
                           )
                   })
               }

               Device (RTC)
               {
                   Name (_HID, EisaId ("PNP0B00"))
                   Name (_CRS, ResourceTemplate ()
                   {
                       IO (Decode16,
                           0x0070,             // Range Minimum
                           0x0070,             // Range Maximum
                           0x01,               // Alignment
                           0x02,               // Length
                           )
                   })

Nothing else.

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mikefred
mikefred
Posted
Posted

Alright, I am trying to apply this to my i7-965 but have a few questions. I already tried it and restarted my computer but my benchmarks cut in half so something must have been wrong. I have AppleLPC working in ioreg using the method from the guide.

 

1. Obviously I am running a quad core. But, my DSDT shows 8 of them (see below). Is this correct? I mean my SSDT dump (attached) also shows this.

 

2. I just took the "Return (Package (0x0E)" section from my ubuntu SSDT dump and pasted it into my DSDT in the " Scope (_PR.CPU0)" section. Is this okay or no?

 

 

Any help is appreciated...

 

 

 

 

Here is what I am doing right now in my DSDT:

 

Scope (_PR)
{
	Processor (CPU0, 0x00, 0x00000000, 0x00) {}
	Processor (CPU1, 0x01, 0x00000000, 0x00) {}
	Processor (CPU2, 0x02, 0x00000000, 0x00) {}
	Processor (CPU3, 0x03, 0x00000000, 0x00) {}
	Processor (CPU4, 0x04, 0x00000000, 0x00) {}
	Processor (CPU5, 0x05, 0x00000000, 0x00) {}
	Processor (CPU6, 0x06, 0x00000000, 0x00) {}
	Processor (CPU7, 0x07, 0x00000000, 0x00) {}


}

	Scope (_PR.CPU0)
{
	Method (_PSS, 0, NotSerialized)
	{
		Return (Package (0x0E)
			{
				Package (0x06)
				{
					0x00000CFD, 
					0x003DFF18, 
					0x0000000A, 
					0x0000000A, 
					0x00000019, 
					0x00000019
				}, 

				Package (0x06)
				{
					0x00000C78, 
					0x003DFF18, 
					0x0000000A, 
					0x0000000A, 
					0x00000018, 
					0x00000018
				}, 

				Package (0x06)
				{
					0x00000BF3, 
					0x00326658, 
					0x0000000A, 
					0x0000000A, 
					0x00000017, 
					0x00000017
				}, 

				Package (0x06)
				{
					0x00000B6E, 
					0x002D2E68, 
					0x0000000A, 
					0x0000000A, 
					0x00000016, 
					0x00000016
				}, 

				Package (0x06)
				{
					0x00000AE9, 
					0x00285820, 
					0x0000000A, 
					0x0000000A, 
					0x00000015, 
					0x00000015
				}, 

				Package (0x06)
				{
					0x00000A64, 
					0x0023DF98, 
					0x0000000A, 
					0x0000000A, 
					0x00000014, 
					0x00000014
				}, 

				Package (0x06)
				{
					0x000009DF, 
					0x001BEC70, 
					0x0000000A, 
					0x0000000A, 
					0x00000013, 
					0x00000013
				}, 

				Package (0x06)
				{
					0x0000095A, 
					0x001871D0, 
					0x0000000A, 
					0x0000000A, 
					0x00000012, 
					0x00000012
				}, 

				Package (0x06)
				{
					0x000008D5, 
					0x00154168, 
					0x0000000A, 
					0x0000000A, 
					0x00000011, 
					0x00000011
				}, 

				Package (0x06)
				{
					0x00000850, 
					0x00125B38, 
					0x0000000A, 
					0x0000000A, 
					0x00000010, 
					0x00000010
				}, 

				Package (0x06)
				{
					0x000007CB, 
					0x000D61C8, 
					0x0000000A, 
					0x0000000A, 
					0x0000000F, 
					0x0000000F
				}, 

				Package (0x06)
				{
					0x00000746, 
					0x000B46B8, 
					0x0000000A, 
					0x0000000A, 
					0x0000000E, 
					0x0000000E
				}, 

				Package (0x06)
				{
					0x000006C1, 
					0x00096640, 
					0x0000000A, 
					0x0000000A, 
					0x0000000D, 
					0x0000000D
				}, 

				Package (0x06)
				{
					0x0000063C, 
					0x0007BC78, 
					0x0000000A, 
					0x0000000A, 
					0x0000000C, 
					0x0000000C
				}
			})
	}

	Method (_PSD, 0, NotSerialized)
	{
		Return (Package (0x05)
		{
			0x05, 
			Zero, 
			Zero, 
			0xFC, 
			0x04
		})
	}

	Method (_CST, 0, NotSerialized)
	{
		Return (Package (0x02)
		{
			One, 
			Package (0x04)
			{
				ResourceTemplate ()
				{
					Register (FFixedHW, 
						0x01,			   // Bit Width
						0x02,			   // Bit Offset
						0x0000000000000000, // Address
						0x01,			   // Access Size
						)
				}, 

				One, 
				0x9D, 
				0x03E8
			}
		})
	}
}

Scope (_PR.CPU1)
{
	Method (_PSS, 0, NotSerialized)
	{
		Return (^^CPU0._PSS ())
	}

	Method (_PSD, 0, NotSerialized)
	{
		Return (^^CPU0._PSD ())
	}

	Method (_CST, 0, NotSerialized)
	{
		 Return (Package (0x04)
			{
				0x03, 
				Package (0x04)
				{
					ResourceTemplate ()
					{
						Register (FFixedHW, 
							0x01,			   // Bit Width
							0x02,			   // Bit Offset
							0x0000000000000000, // Address
							,)
					}, 

					One, 
					Zero, 
					0x03E8
				}, 

				Package (0x04)
				{
					ResourceTemplate ()
					{
						Register (FFixedHW, 
							0x08,			   // Bit Width
							0x00,			   // Bit Offset
							0x0000000000000414, // Address
							,)
					}, 

					0x02, 
					One, 
					0x01F4
				}, 

				Package (0x04)
				{
					ResourceTemplate ()
					{
						Register (FFixedHW, 
							0x08,			   // Bit Width
							0x00,			   // Bit Offset
							0x0000000000000415, // Address
							,)
					}, 

					0x03, 
					0x55, 
					0xFA
				}
			})
	}
}

Scope (_PR.CPU2)
{
	Method (_PSS, 0, NotSerialized)
	{
		Return (^^CPU0._PSS ())
	}

	Method (_PSD, 0, NotSerialized)
	{
		Return (^^CPU0._PSD ())
	}

	Method (_CST, 0, NotSerialized)
	{
		Return (^^CPU1._CST ())
	}
}

Scope (_PR.CPU3)
{
	Method (_PSS, 0, NotSerialized)
	{
		Return (^^CPU0._PSS ())
	}

	Method (_PSD, 0, NotSerialized)
	{
		Return (^^CPU0._PSD ())
	}

	Method (_CST, 0, NotSerialized)
	{
		Return (^^CPU1._CST ())
	}
}

Scope (_PR.CPU4)
{
	Method (_PSS, 0, NotSerialized)
	{
		Return (^^CPU0._PSS ())
	}

	Method (_PSD, 0, NotSerialized)
	{
		Return (^^CPU0._PSD ())
	}

	Method (_CST, 0, NotSerialized)
	{
		Return (^^CPU1._CST ())
	}
}
Scope (_PR.CPU5)
{
	Method (_PSS, 0, NotSerialized)
	{
		Return (^^CPU0._PSS ())
	}

	Method (_PSD, 0, NotSerialized)
	{
		Return (^^CPU0._PSD ())
	}

	Method (_CST, 0, NotSerialized)
	{
		Return (^^CPU1._CST ())
	}
}
Scope (_PR.CPU6)
{
	Method (_PSS, 0, NotSerialized)
	{
		Return (^^CPU0._PSS ())
	}

	Method (_PSD, 0, NotSerialized)
	{
		Return (^^CPU0._PSD ())
	}

	Method (_CST, 0, NotSerialized)
	{
		Return (^^CPU1._CST ())
	}
}
Scope (_PR.CPU7)
{
	Method (_PSS, 0, NotSerialized)
	{
		Return (^^CPU0._PSS ())
	}

	Method (_PSD, 0, NotSerialized)
	{
		Return (^^CPU0._PSD ())
	}

	Method (_CST, 0, NotSerialized)
	{
		Return (^^CPU1._CST ())
	}
}

SSDT.dsl.zip

ioreg.txt.zip

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  • 2 weeks later...
marionez
marionez
Posted
Posted

Anyone with a patched P5Q dsdt?

I've got no time for this in this period, I tried a lot but I can't get it working correctely.

 

This is the original .dsl coming from the P5Q with an E8400.

dsdtP5Qoriginal.zip

I think it's more simple starting from scratch (file attached) then correcting my mistaken dsl.

 

- CPU: E8400, core duo 2

- Speedstep: post-303759-1268757523_thumb.png

- SATA Controller: ICH10

 

I even tried with all those fixes about EHCI, USB ports etc...

 

Any help would really be appreciated.

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gatsu_1981
gatsu_1981
Posted
Posted
Anyone with a patched P5Q dsdt?

I've got no time for this in this period, I tried a lot but I can't get it working correctely.

 

This is the original .dsl coming from the P5Q with an E8400.

dsdtP5Qoriginal.zip

I think it's more simple starting from scratch (file attached) then correcting my mistaken dsl.

 

- CPU: E8400, core duo 2

- Speedstep: post-303759-1268757523_thumb.png

- SATA Controller: ICH10

 

I even tried with all those fixes about EHCI, USB ports etc...

 

Any help would really be appreciated.

 

Here it is mine, i'm on a P5Q with a Q6600, your work should be a lot less than editing the original file :)

q6600_p5q_dsdt.zip

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FKA
FKA
Posted
  • Author
Posted
Alright, I am trying to apply this to my i7-965 but have a few questions. I already tried it and restarted my computer but my benchmarks cut in half so something must have been wrong. I have AppleLPC working in ioreg using the method from the guide.

 

1. Obviously I am running a quad core. But, my DSDT shows 8 of them (see below). Is this correct? I mean my SSDT dump (attached) also shows this.

 

2. I just took the "Return (Package (0x0E)" section from my ubuntu SSDT dump and pasted it into my DSDT in the " Scope (_PR.CPU0)" section. Is this okay or no?

 

You only need to add values for your 4 cores CPU 0 through 3.

 

D.

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valv
valv
Posted
Posted

thanx to all u for this nice evolution on the way to the perfect mac-like

 

have trying too many ways from too many people over here, just to realize I could not get this on my own.

It would be cool if someone could take a look into this and tell where the trouble comes from.

 

I have C-states showing on IORegExplorer as u ca see

post-498884-1268906633_thumb.png

 

msrtools shows that speed-step is on

post-498884-1268906760_thumb.png

 

The thing is even if my cpu temp gets between 31~46C, the cpu doesn't seem to throttle. looking into coolbook, I see the lowest P-State

post-498884-1268907560_thumb.png

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valv
valv
Posted
Posted

 

thank u for replying,

the thing is I was already using MacBookPro5,4 without success; on my legacy acpi_smc_plugin however I used a fake model (as Silencer suggested on one of his guides)

 

and those are kexts I use from E/E/:

AppleAcpiPs2Nub

Fakesmc

Cpuinjector

VoodooPs2Controller

Voodoobattery

 

though I will try it your way and tell u :rolleyes:

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valv
valv
Posted
Posted

oh, forgot to explain my self, my cpu is p8700 core2duo with 2,533Ghz that's why I chose Mbp5,4 as it has same pross.

I remade my config as u suggested and now am running into same trouble

post-498884-1268925937_thumb.png

 

and it gets even warmer as it now hangs on first p-state.

post-498884-1268925976_thumb.png

 

one more question what is the CPUPLimit and how to modify it

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valv
valv
Posted
Posted

the only diff I can see is the _PR declaration, for Formerly it looks like this

 

Processor (CPU0, 0x00, 0x00000410, 0x06) {}

Processor (CPU1, 0x01, 0x00000410, 0x06) {}

Processor (CPU2, 0x02, 0x00000410, 0x06) {}

Processor (CPU3, 0x03, 0x00000410, 0x06) {}

 

this is the same as the one from mbp5,4 but for me it looks so

 

Processor (CPU0, 0x01, 0x00000410, 0x06) {}

Processor (CPU1, 0x02, 0x00000410, 0x06) {}

Processor (CPU2, 0x03, 0x00000410, 0x06) {}

Processor (CPU3, 0x04, 0x00000410, 0x06) {}

 

I know Tea has got the same KP when he was trying to change the values on projecosx, but then how can I get this the way macOs likes it to be?

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leslieking
leslieking
Posted
Posted

I'm trying to obtain the FID/VID values for the Q6600 CPU. There is a problem. PStatenChanger shows the same VID (28, 28, 28, 28). Please check the attached image.

 

I have NullCPUPowerManagement and Sleepenabler enabled, but I'm unable to boot OS X without NullCPUPowerManagement.

 

Any idea how can I solve this problem ? Thanks!

post-66455-1268948525_thumb.png

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FKA
FKA
Posted
  • Author
Posted
I'm trying to obtain the FID/VID values for the Q6600 CPU. There is a problem. PStatenChanger shows the same VID (28, 28, 28, 28). Please check the attached image.

 

I have NullCPUPowerManagement and Sleepenabler enabled, but I'm unable to boot OS X without NullCPUPowerManagement.

 

Any idea how can I solve this problem ? Thanks!

 

zoliky - you need to removed NullCPUPM kext and sleepenabler and use voodoopowerstate kext instead.

This will give you you fid and vid values in p-statechanger. Edit DSDT with values then removed voodoopowerstate kext .

Please read the 1st post again.

 

D

 

the only diff I can see is the _PR declaration, for Formerly it looks like this

 

Processor (CPU0, 0x00, 0x00000410, 0x06) {}

Processor (CPU1, 0x01, 0x00000410, 0x06) {}

Processor (CPU2, 0x02, 0x00000410, 0x06) {}

Processor (CPU3, 0x03, 0x00000410, 0x06) {}

 

this is the same as the one from mbp5,4 but for me it looks so

 

Processor (CPU0, 0x01, 0x00000410, 0x06) {}

Processor (CPU1, 0x02, 0x00000410, 0x06) {}

Processor (CPU2, 0x03, 0x00000410, 0x06) {}

Processor (CPU3, 0x04, 0x00000410, 0x06) {}

 

I know Tea has got the same KP when he was trying to change the values on projecosx, but then how can I get this the way macOs likes it to be?

 

you should keep the values native to your DSDT !

 

D

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Beerkex'd
Beerkex'd
Posted
Posted

Where did you get "418" for your third C-state package? If that's C3, it should be 415, C4 is 416.

 

You can find the right code for your C-states in your SSDT tables - extract them with Everest under Windows like this:

http://www.projectosx.com/forum/index.php?...post&p=1343

 

Not sure what kind of problems (if any) having this value wrong could cause though.

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