DSDT - Vanilla Speedstep - Generic Scope (_PR)

[Signal64]

Register with all zeros means C1, register with 0x1,0x2,0x00 means C1E. And defining C1 is pointless since all cpu's support it anyway.

 

Defining it in that case would be to just get rid of the LPC CST error on boot unless there is a better way.

 

In regards to the 8.4.2.1 _CST description if you look in FACP and you see latency values for C2 C3 don't you have support for C1-C3 anyway? Just being done through P_BLK P_LVLx values and P_LVLx_LAT from FADT instead of the "optional" _CST method.

 

[05Fh 0095  1]				 _CST Support : 00
[060h 0096  2]				   C2 Latency : 0065
[062h 0098  2]				   C3 Latency : 03E9

 

If that's true then your not just limted to C1 and should be able to safely define _CST for C2 and C3 right?

[mm67]

Defining it in that case would be to just get rid of the LPC CST error on boot unless there is a better way.

 

In regards to the 8.4.2.1 _CST description if you look in FACP and you see latency values for C2 C3 don't you have support for C1-C3 anyway? Just being done through P_BLK P_LVLx values and P_LVLx_LAT from FADT instead of the "optional" _CST method.

 

[05Fh 0095  1]				 _CST Support : 00
[060h 0096  2]				   C2 Latency : 0065
[062h 0098  2]				   C3 Latency : 03E9

 

If that's true then your not just limted to C1 and should be able to safely define _CST for C2 and C3 right?

 

Those 65 and 3E9 values mean that C2 and C3 are not supported, look at Acpispec40, page 120. But it doesn't seem to matter what values you use there, I can make C-states work only with CST object.

[Signal64]

Those 65 and 3E9 values mean that C2 and C3 are not supported, look at Acpispec40, page 120.

 

Alright, bad example then.

 

On the Gigabyte EP45-UD3P with an E6850 we have C2=0x5A and C3=0x384 which would indicate it being supported.

 

Getting the same values on the EP45-DS4P with Q9550.

 

Point being on these boards where you don't get CST tables (like all three of the gigabytes in my sig) it doesn't appear your just stuck with C1 (if C2 < 100 [0x64] and C3 < 1000 [0x3E8] )

[mm67]

Alright, bad example then.

 

On the Gigabyte EP45-UD3P with an E6850 we have C2=0x5A and C3=0x384 which would indicate it being supported.

 

Getting the same values on the EP45-DS4P with Q9550.

 

Point being on these boards where you don't get CST tables (like all three of the gigabytes in my sig) it doesn't appear your just stuck with C1 (if C2 < 100 [0x64] and C3 < 1000 [0x3E8] )

 

Both your boards do support deeper C-states, but you also have to look at CPU datasheets, your E6850 for example seems to support only C1 and C2.

[MacKonsti]

This document will tell you the meaning of register values: http://download.intel.com/technology/IAPC/...ds/30222305.pdf

 

Register with all zeros means C1, register with 0x1,0x2,0x00 means C1E. And defining C1 is pointless since all cpu's support it anyway.

That is a great find, dear mm67. And makes sense, in a way; using these values lowers the temperature considerably, even below 40C sometimes. In page 12, there's mention of "Native C State Instruction (beyond halt)" so you think this is C1E?

 

Can I please make a couple of newbie® questions as to clarify the issue?

 

(1) if there's no mention of C2, C3 and even C4 in the BIOS screen of my system (Shuttle SG31G2V2) does that completely exclude C2/3/4 support altogether? My BIOS only has C1E Enabled/Auto option...

 

(2) what is the best way to detect if the SnowLeo system is indeed making use of C-States? With VoodooMonitor I can only see the voltage and multipliers changing. There's no command cstatesinfo, etc. unless you're referring to Ubuntu.

 

By the way, when I tried the LiveCD method to obtain SSDTs, I got an empty (null) file. Does that say anything?

 

Finally, I think that the line:

 

Name (_CST, Package (0x02)
{
0x01,  // Only C1E available, below
Package (0x04) {ResourceTemplate () {Register (FFixedHW, 0x01, 0x02, 0x0000,,)}, 0x01, 0x01, 0x03E8},
})

is the one working for me. However, Temperature Monitor.app does not always read a temperature out of the 4 cores of my Q9550 (displaying dashes ---) despite using the latest FakeSMC 2.5 from netkas.org. Any thoughts on that one, too?

[mm67]

That is a great find, dear mm67. And makes sense, in a way; using these values lowers the temperature considerably, even below 40C sometimes. Can you please post the page number? Tried to find it...

 

Can I please make a couple of newbie® questions as to clarify the issue?

 

(1) if there's no mention of C2, C3 and even C4 in the BIOS screen of my system (Shuttle SG31G2V2) does that completely exclude C2/3/4 support altogether? My BIOS only has C1E Enabled/Auto option...

 

(2) what is the best way to detect if the SnowLeo system is indeed making use of C-States? With VoodooMonitor I can only see the voltage and multipliers changing. There's no command cstatesinfo, etc. unless you're referring to Ubuntu.

 

By the way, when I tried the LiveCD method to obtain SSDTs, I got an empty (null) file. Does that say anything?

 

Finally, I think that the line:

 

Name (_CST, Package (0x02)
{
	0x01,  // Only C1E available, below
	Package (0x04) {ResourceTemplate () {Register (FFixedHW, 0x01, 0x02, 0x0000,,)}, 0x01, 0x01, 0x03E8},
})

is the one working for me. However, Temperature Monitor.app does not always read a temperature out of the 4 cores of my Q9550 (displaying dashes ---) despite using the latest FakeSMC 2.5 from netkas.org. Any thoughts on that one, too?

 

Page 12, table 4 is the interesting part. As you can see 0x1, 0x2 is used to call native C state instructions.

 

That Shuttle is using G31 chipset ? Then you have to look for that datasheet and see what it says, but I do think that it is very much likely that it supports only C1E as P35 seems to do. Best tool for OS X seems to be mark-i if you have a supported Super-I/O chip on your board. I use iStat menus, no problems with temperature readings.

[MacKonsti]

That Shuttle is using G31 chipset ? Then you have to look for that datasheet and see what it says, but I do think that it is very much likely that it supports only C1E as P35 seems to do.

 

Best tool for OS X seems to be mark-i if you have a supported Super-I/O chip on your board. I use iStat menus, no problems with temperature readings.

Yes, the Shuttle SG31G2V2 uses the G31 ICH7 chipset, and performs adequately (as MacPro3,1). Its BIOS reports only C1E and thus I will use only one C1 code in my DSDT. For my Q9550 I get idle temps at 41C (for first core) and around 38-39 for the other cores.

 

Furthermore, for all of us, a note: the fact that the temperature reading is there, doesn't mean that it's polling continuously. It waits for a new value to update, even if it takes too long. I also use iStat Menus which are great; they report the same values as Temperature Monitor, but refresh less often. However, e.g. core 3 and core 4 are at idle 38C and that reading doesn't change on iStat Menus, it just stays there while in Temperature Monitor there's no reading (dashes) for some time. So this prompts me to believe that iStat Menus just waits for the next info and if there's none, it still keeps the previous temperature value displayed. I urge you to also test Temperature Monitor here to see this behaviour (unless Temperature Monitor's sucks!)

[mm67]

Yes, the Shuttle SG31G2V2 uses the G31 ICH7 chipset, and performs adequately (as MacPro3,1). Its BIOS reports only C1E and thus I will use only one C1 code in my DSDT. For my Q9550 I get idle temps at 41C (for first core) and around 38-39 for the other cores.

 

Furthermore, for all of us, a note: the fact that the temperature reading is there, doesn't mean that it's polling continuously. It waits for a new value to update, even if it takes too long. I also use iStat Menus which are great; they report the same values as Temperature Monitor, but refresh less often. However, e.g. core 3 and core 4 are at idle 38C and that reading doesn't change on iStat Menus, it just stays there while in Temperature Monitor there's no reading (dashes) for some time. So this prompts me to believe that iStat Menus just waits for the next info and if there's none, it still keeps the previous temperature value displayed. I urge you to also test Temperature Monitor here to see this behaviour (unless Temperature Monitor's sucks!)

 

This is from ICH7 datasheet: ACPI-defined power states (C1, S1, S3–S5 for Desktop and C1–C4, S1, S3–S5 for Mobile/Ultra Mobile)

 

I think you should stick to C1E only.

[mitch_de]

"I think you should stick to C1E only."

I think also.

But there seems to be two different C1E only posted here:

Name (_CST, Package (0x02)

{

0x01, // Only C1E available, below

Package (0x04) {ResourceTemplate () {Register (FFixedHW, 0x01, 0x02, 0x0000,,)}, 0x01, 0x01, 0x03E8},

})

 

and

Name (_CST, Package (0x02)

{

0x1,

Package (0x4){ResourceTemplate (){Register (FFixedHW,0x01,0x02,0x00,,)},One,0x9D,0x3E8}

})

 

Only difference is that 0x9D vs 0x01.

[MacKonsti]

mitch_de, as I mentioned earlier, with the find by mm67, the line (for ICH7 and Q9950):

 

Package (0x04) {ResourceTemplate () {Register (FFixedHW, 0x01, 0x02, 0x0000,,)}, 0x01, 0x01, 0x03E8},

 

seems to be the proper for C1E. Now please can anyone tell me if:

 

1. there's a way to confirm supported C-states or if they are working, from within Snow Leopard? A special command/tool? Or Ubuntu Live CD?

 

2. Can you also please test Temperature Monitor (freeware) and let us know if you also detect an absence of core temperatures measurement, at times, over a period of a few minutes? It has an interesting temperature graph, too...

[westwaerts]

1. there's a way to confirm supported C-states or if they are working, from within Snow Leopard? A special command/tool? Or Ubuntu Live CD?

 

2. Can you also please test Temperature Monitor (freeware) and let us know if you also detect an absence of core temperatures measurement, at times, over a period of a few minutes? It has an interesting temperature graph, too...

 

1. mark-i is a little russian app, that afaik monitors speedstep, without speedstepping.

( besides that monitors cpu temp)

2. istat monitors various system temp, activity, etc ( with fakeSMC 2.5) it reads out cpu-temp

( temperaturmonitor is not designed to run on hacks, was the reply from the author about a year ago,

when this question appeared )

[mitch_de]

mitch_de, as I mentioned earlier, with the find by mm67, the line (for ICH7 and Q9950):

Package (0x04) {ResourceTemplate () {Register (FFixedHW, 0x01, 0x02, 0x0000,,)}, 0x01, 0x01, 0x03E8},

 

seems to be the proper for C1E. Now please can anyone tell me if:

 

Hi, thanks for information. In my case (C2D E7300@ 3.0 GHz OC (2.0-3.0 GHz), GAEP35) i get same low temps with 0x01 and 0x9D. So seems doesnt matter.

32/34 degrees Celsius in both cases running OS X desktop with no mosue move / apps running and in slowest Pstate 2.0 GHZ (from max=3.0 GHz)

(I dont stay outside in ALSAKA - room temp for those 32/34 Celsius is 20 Celsius )

[keeza]

Register with all zeros means C1, register with 0x1,0x2,0x00 means C1E. And defining C1 is pointless since all cpu's support it anyway.

Does that mean that C2E and C4E have different FfixedHW values or are these C-states only available by IO addresses?

 

And is it possible that OSX doesn't support Enhanced CState i.e. C2E & C4E not supported?

[mm67]

Does that mean that C2E and C4E have different FfixedHW values or are these C-states only available by IO addresses?

 

And is it possible that OSX doesn't support Enhanced CState i.e. C2E & C4E not supported?

 

That Intel document says that 0x1,0x2 means native C state instruction, next value is defined as Hints and this is what that document says about Hints and native C states:

 

The Native C State encoding supports processors that support the MWAIT instruction and MWAIT Extensions if applicable. MWAIT Hints correspond to the value passed via the EAX register when executing the MWAIT instruction

 

To me it looks like OS X supports only this method of using C - states, at least using SystemIO addressing never gets that C-state deeper than C2 bit set. OS X surely supports deeper C - states, just take a look at MacPro4,1 SSDT, it has C-states going down to C7.

[keeza]

OS X surely supports deeper C - states, just take a look at MacPro4,1 SSDT, it has C-states going down to C7.

I meant does OSX support enhanced C2E, C4E not C2 and C4.

 

Also, regarding a single quad core processor such as the Q9550, I read somewhere that CPU0 doesn't go any deeper than C1, whereas CPU1-3 can go to all C-States - is that correct?

[Goron]

Maybe a dumb question, but may someone be so kind to clarify?

 

How can i tell if vanilla speedstep REALLY works by itself? I do not really understand, how Voodoopstate works .... does it only read the current frequency, or is it a "driver" that forces the cpu to throttle, or speed up?

 

Which program(s) do you use to read your actual cpu frequencies, or even monitor them????????

 

 

Cheers

 

Goron

[mitch_de]

Voodomonitor and Mark-i show Pstate usage (MHZ up/down) - but do no thottling.

Vanialla Pstates (using AppleIntelCPU...) and Vodoopower trottle.

[jvolkman]

I'm slightly confused about p-states. I have an i7-920, and VoodooPower is reporting 10 p-states: bus * 12-21. The default bus speed for this processor is 133, so the top p-state is 2793mhz. I'm running a slight overclock with the bus at 160mhz. Should I update the p-state table and multiply each multiplier by 160 instead of 133? If so, do I need to worry about the power (wattage) element?

 

My current table:

Package (0x06) { 2793, 130000, 10, 10, 21, 21 },

Package (0x06) { 2664, 130000, 10, 10, 20, 20 },

Package (0x06) { 2527, 109000, 10, 10, 19, 19 },

Package (0x06) { 2394, 100000, 10, 10, 18, 18 },

Package (0x06) { 2261, 83000, 10, 10, 17, 17 },

Package (0x06) { 2128, 76000, 10, 10, 16, 16 },

Package (0x06) { 1995, 63000, 10, 10, 15, 15 },

Package (0x06) { 1862, 57000, 10, 10, 14, 14 },

Package (0x06) { 1729, 47000, 10, 10, 13, 13 },

Package (0x06) { 1596, 43000, 10, 10, 12, 12 }

[mitch_de]

Yep, for my knowledge the WATTs in Pstates are cosmetic. Values of mVolts and Pstate Nr. are the only really needed / dangerous.

 

But your PSS is a bit worng!

Package (0x06) { 2793, 130000, 10, 10, 21, 21 },

Package (0x06) { 2664, 130000, 10, 10, 20, 20 },

...

mine

Package (0x06)

{

0x0BB5, // MHZ in hex, can be in dez also

0x00013A97, // Watts in hex, can be in dez also

0x0A, // ? (all same for me, = 10 dez)

0x0A, // ? (all same for me, = 10 dez)

0x0922, // 09(hex)= multiplier (*FSB), 22(hex!) VID (mVolts)

0x0922 // 09(hex)= multiplier (*FSB), 22(hex!) VID (mVolts) SAME, used as check

},

 

So your last two entrys are wrong (multiplier + mVolts VID) in each line!

[keeza]

Anyone have an apple macpro3,1 SSDT available?

[VCH888]

Anyone have an apple macpro3,1 SSDT available?

 

Got from another forum.

 

MP31.zip

[jvolkman]

mine

Package (0x06)

{

0x0BB5, // MHZ in hex, can be in dez also

0x00013A97, // Watts in hex, can be in dez also

0x0A, // ? (all same for me, = 10 dez)

0x0A, // ? (all same for me, = 10 dez)

0x0922, // 09(hex)= multiplier (*FSB), 22(hex!) VID (mVolts)

0x0922 // 09(hex)= multiplier (*FSB), 22(hex!) VID (mVolts) SAME, used as check

},

 

So your last two entrys are wrong (multiplier + mVolts VID) in each line!

 

Where does that definition for that field come from? According to ACPIspec40.pdf, those fields are:

 

The last two fields are what we're talking about. The spec is pretty general about them, and they don't appear to contain any useful data other than being opaque identifiers. I might be wrong, but if so is there somewhere that describes them as something more important?

 

Got from another forum.

 

MP31.zip

 

Do you have MacPro4,1 as well?

[mitch_de]

Yep-. That ACPI definitions of the PSS are very basic. The 5. value is that what controls FSB multiplier and mVolts.

Last for my knowledge can be used for an compare (after change?) if pstate switch was OK. Normally same as 5. for compareadge.

Perhhaps someone finde an detailed part of the definitions of 5.(major) and 6.(only for compare/checks) values.

[leslieking]

I'm trying to add vanilla speedstep to the Intel Core 2 E5200 CPU. It has 14 p-states:

 

Scope (_PR)
{
   Name (PSS, Package (0x0E) // 14 p-states
   {
       Package (0x06) { Zero, Zero, 10, 10, 0x4C24, Zero }, 
       Package (0x06) { Zero, Zero, 10, 10, 0x0C23, One },
       Package (0x06) { Zero, Zero, 10, 10, 0x4B22, 2 },
       Package (0x06) { Zero, Zero, 10, 10, 0x0B21, 3 },
       Package (0x06) { Zero, Zero, 10, 10, 0x4A20, 4 },
       Package (0x06) { Zero, Zero, 10, 10, 0x0A1F, 5 },
       Package (0x06) { Zero, Zero, 10, 10, 0x491E, 6 },
       Package (0x06) { Zero, Zero, 10, 10, 0x091D, 7 },
       Package (0x06) { Zero, Zero, 10, 10, 0x481C, 8 },
       Package (0x06) { Zero, Zero, 10, 10, 0x081B, 9 },
       Package (0x06) { Zero, Zero, 10, 10, 0x471A, 10 },
       Package (0x06) { Zero, Zero, 10, 10, 0x0719, 11 },
       Package (0x06) { Zero, Zero, 10, 10, 0x4618, 12 },
       Package (0x06) { Zero, Zero, 10, 10, 0x0616, 13 }
   })

   Name (PSD, Package (0x05)
   {
       0x05,Zero,Zero,0xFC,0x04
   })

   Name (CST, Package (0x04) // 3 c-states
   {
       0x03,
       Package (0x04){ResourceTemplate (){Register (FFixedHW,0x01,0x02,0x000,0x00,)},One,One,0x03E8},
       Package (0x04){ResourceTemplate (){Register (SystemIO,0x08,0x00,0x0000000000000414, ,)},0x02,One,0x01F4},
       Package (0x04){ResourceTemplate (){Register (SystemIO,0x08,0x00,0x0000000000000415, ,)},0x03,0x55,0xFA}
   })

   Processor (CPU0, 0x00, 0x00000410, 0x06)
   {
       Alias (PSS, _PSS)
       Alias (PSD, _PSD)
       Alias (CST, _CST)
   }

   Processor (CPU1, 0x01, 0x00000410, 0x06)
   {
       Alias (PSS, _PSS)
       Alias (PSD, _PSD)
       Alias (CST, _CST)
   }
}

 

Just one question: I need to replace 0x04 with 0x02 in PSD : ?

 

Name (PSD, Package (0x05)
{
0x05,Zero,Zero,0xFC,0x04   <--- 0x02 instead of 0x04 ??
})

 

I would be grateful for any help!

[keeza]

Name (PSD, Package (0x05)
  {
   0x05,Zero,Zero,0xFC,0x04   <--- 0x02 instead of 0x04 ??
  })

 

I would be grateful for any help!

 

Yep thats right, page 328 and 329 of ACPI specs, that value relates to the number of processors

 

Also, regarding a single quad core processor such as the Q9550, I read somewhere that CPU0 doesn't go any deeper than C1, whereas CPU1-3 can go to all C-States - is that correct?

 

Anyone know the answer to this?