DSDT - Vanilla Speedstep - Generic Scope (_PR)

[mitch_de]

It might just have been VoodooPower – known to block restart – but it can be verified by removing AppleIntelCPUPowerManagement.kext or to use a disabler kext.

 

Sleep here works without AppleIntelCPUPowerManagement.kext !

For me sleep only works with AppleIntelCPU loaded. (Sure i can load it )

WIthout AICP no sleep on 10.5.8 I havent tried SL.

I have no Voodoopower loaded, only sleepenabler (i dont have any Powermanagement .kext loaded as default).

But doenst matter - it works now

[msm5]

Aargh-a-Knot:

 

Glad to hear you're running well. The credit for the DSDT goes to big brains in this thread.

 

For VoodooMonitor, I put VoodooMonitor.kext in my Extra/Extensions folder. After a reboot, you should be able to run the app without a problem. P-state changer is similar, you just have to make sure you're using the correct kext for 10.6. I understand P-state changer is more resource intense, so I uninstalled it after getting the values. They didn't jive with some of the other methods and I ended up settling with p-state calculator. I've attached a comparison of some of the values I obtained while running a generic DSDT with no speedstepping.

 

 

pstate_calculator.rtf

[snackole]

Hey msm5, could you post your dsdt for your ep35-ds3r. I have the same board and would like to compare them. Thank you.

[Aargh-a-Knot]

Hey msm5, could you post your dsdt for your ep35-ds3r. I have the same board and would like to compare them. Thank you.

 

He posted them earlier in this post, apparently in response to my request for his original UD3P DSDT... I would ask him for it again, but I don't want to become bothersome...

[snackole]

Okay thanks.

[msm5]

He posted them earlier in this post, apparently in response to my request for his original UD3P DSDT... I would ask him for it again, but I don't want to become bothersome...

 

Sorry, it's really no bother at all, it just slipped my mind. This hobby gets last dibs on my time after work, kids, dogs, etc. This DSDT file has mainly the basic fixes applied when using ACPI Patcher to include video and LAN. Are you planning on starting from scratch?

 

EP45UD3PorigDSDT.dsl.zip

[kdawg]

For me sleep only works with AppleIntelCPU loaded. (Sure i can load it )

WIthout AICP no sleep on 10.5.8 I havent tried SL.

I have no Voodoopower loaded, only sleepenabler (i dont have any Powermanagement .kext loaded as default).

But doenst matter - it works now

 

My GA-EP35-DS4 restart and sleep worked without the help of OpenHaltRestart, EvOreboot, sleepenabler or any of those in 10.5.8 too. Unfortunately, I haven't been able to replicate that on my GA-EP45-UD3P in Snow Leopard. But that was also a while ago and didn't have all the latest DSDT modifications. It did have speed stepping though.

[Aargh-a-Knot]

Sorry, it's really no bother at all, it just slipped my mind. This hobby gets last dibs on my time after work, kids, dogs, etc. This DSDT file has mainly the basic fixes applied when using ACPI Patcher to include video and LAN. Are you planning on starting from scratch?

 

EP45UD3PorigDSDT.dsl.zip

 

Hey, thanks. Not really starting from scratch, but I wanted to compare your original with my original, to see if there were any differences. I know we have the same board and BIOS, but I wanted to rule out the possibility that there were any subtle differences due to revision# or something. I want to be able to look at any of the values in the new DSDT and see what it was before you changed it.

 

So, the above isn't your original unmodified DSDT dump? No worries, I'll just assume we started with at least close to the same thing. When I first asked, I hadn't tried the one you posted yet, and I wanted to be prepared to compare if anything was awry. But, it's working great!

 

BTW, thanks for the reassurance with VoodooMonitor. I installed the kext into E/E again and rebooted, and this time it worked instead of making a kernel panic upon boot. I can now watch speedstepping in action. I have no idea why I was getting KP the last time and not now I do have slightly different values showing than you posted earlier for Voltage and Control. I wonder why? Are these values set by the CPU, the BIOS, and/or the DSDT tables? Is it possible to change any of these values to make it run cooler at the lowest step?

 

I have a lot more to learn about this, but instead of kids/dogs/work, I have wife/nursing school/web design business taking up my time. This sure is more fun than studying for finals though!

[msm5]

I do have slightly different values showing than you posted earlier for Voltage and Control. I wonder why? Are these values set by the CPU, the BIOS, and/or the DSDT tables? Is it possible to change any of these values to make it run cooler at the lowest step?

 

I've also wondered about this voltage thing and according to what I've read on this and the Gigabyte DSDT thread a generic or non-speedstepping CPU should be used to get the initial values. It's my understanding that they're dependent not only on CPU, but also frontside bus. I went with p-state calculator values mainly because they seemed to give the lowest values and most "even" spread of values. Really, though, Master Chief mentioned in his P5K PRO thread that it's what he used. So much to learn.

[relikwie]

Happy i could help you

 

 

Oh, you have OC'ed your CPU? Wonder if that could be harmful for my stock speed CPU.

Temps are OK (but have an insane cooler) around 30/32 Celsius.

 

Can anyone see if these values are correct?

	Scope (_PR) // Processor scope (namespace).
{
	Processor (CPU0, 0x00, 0x00000410, 0x06)
	{
		Name (_PSS, Package (0x08)
		{
			// Processor scope (namespace).
			Package (0x06) { 0x0ED8, 0, 10, 10, 0x4922, 0 },
			Package (0x06) { 0x0E10, 0, 10, 10, 0x0920, 1 },
			Package (0x06) { 0x0D48, 0, 10, 10, 0x481F, 2 },
			Package (0x06) { 0x0C80, 0, 10, 10, 0x081D, 3 },
			Package (0x06) { 0x0BB8, 0, 10, 10, 0x471C, 4 },
			Package (0x06) { 0x0AF0, 0, 10, 10, 0x071A, 5 },
			Package (0x06) { 0x0A28, 0, 10, 10, 0x4619, 6 },
			Package (0x06) { 0x0960, 0, 10, 10, 0x0617, 7 }
		})

		Name (_PSD, Package (0x05) {0x05, Zero, Zero, 0xFC, 0x04})
		Name (_CST, Package (0x04) 
			 {0x03,
			 Package (0x04) {ResourceTemplate () {Register (FFixedHW, 1, 2, 0x000)},1,1,0x03E8},
			 Package (0x04) {ResourceTemplate () {Register (SystemIO, 8, 0, 0x414)},2,1,0x01F4},
			 Package (0x04) {ResourceTemplate () {Register (SystemIO, 8, 0, 0x415)},3,17,0x0FA}
		})
	}

	Processor (CPU1, 0x01, 0x00000410, 0x06)
	{
		Alias (\_PR.CPU0._PSS, _PSS)
		Alias (\_PR.CPU0._PSD, _PSD)
		Alias (\_PR.CPU0._CST, _CST)
	}

	Processor (CPU2, 0x02, 0x00000410, 0x06)
	{
		Alias (\_PR.CPU0._PSS, _PSS)
		Alias (\_PR.CPU0._PSD, _PSD)
		Alias (\_PR.CPU0._CST, _CST)
	}

	Processor (CPU3, 0x03, 0x00000410, 0x06)
	{
		Alias (\_PR.CPU0._PSS, _PSS)
		Alias (\_PR.CPU0._PSD, _PSD)
		Alias (\_PR.CPU0._CST, _CST)
	}
}

[Aargh-a-Knot]

I've also wondered about this voltage thing and according to what I've read on this and the Gigabyte DSDT thread a generic or non-speedstepping CPU should be used to get the initial values. It's my understanding that they're dependent not only on CPU, but also frontside bus. I went with p-state calculator values mainly because they seemed to give the lowest values and most "even" spread of values. Really, though, Master Chief mentioned in his P5K PRO thread that it's what he used. So much to learn.

 

Interesting thing is, my voltage for the x6 multiplier is the same as your voltage for the x9 multiplier. And the frequency etc is the same. What do you have your voltage set for in BIOS? I just have mine set on "Auto".

 

What kind of idle temps do you have?

 

 

[MacUser2525]

Interesting thing is, my voltage for the x6 multiplier is the same as your voltage for the x9 multiplier. And the frequency etc is the same. What do you have your voltage set for in BIOS? I just have mine set on "Auto".

 

I believe what you are seeing there with respect to the different voltages has to do with the default VID of the chip itself. Every chip has a different VID my Q6600 for instance has this set to 1.2125 which is what it is when set to Auto in BIOS. Now I think when using these tools to get the VID's we are putting in this is reflected in the results ie higher default VID chip gets higher VID's to put in than someone who has lower value for instance my 6x is 1.068v @2100mhz for my overclock yours at stock is 1.26v.

 

What kind of idle temps do you have?

 

Depending on which you believe iStat menu with a tjmax of 90 in fakesmc.kext is 34,35,30,30 Voodoo Monitor says 10C higher, the iStat agrees with my BIOS so I go with that.

[Aargh-a-Knot]

@msm5

 

I got some advice about the c-states that you have in your dsdt, and learned alot more about it in the process. (thanks mm67!)

 

Anyway, the q6600 only has 1 c-state, and you had 3 defined. Also, you have some stuff defined twice. I just got some insight from one of Master Chiefs recent posts, and I moved PSS, PSD, and CST out of the CPU blocks and just used aliases for all the cores. Looks much more elegant.

 

I spent the last two days building a new dsdt, using mm67's dsdt as an example. I compared his original with mine, and went in and made all the changes for the UD3P/Q6600, adding HDEF sound etc.

 

Try this one out:

 

Aargh_dsdt_v2.0

 

[mtrr]

@msm5

 

I got some advice about the c-states that you have in your dsdt, and learned alot more about it in the process. (thanks mm67!)

 

Anyway, the q6600 only has 1 c-state, and you had 3 defined. Also, you have some stuff defined twice. I just got some insight from one of Master Chiefs recent posts, and I moved PSS, PSD, and CST out of the CPU blocks and just used aliases for all the cores. Looks much more elegant.

 

I spent the last two days building a new dsdt, using mm67's dsdt as an example. I compared his original with mine, and went in and made all the changes for the UD3P/Q6600, adding HDEF sound etc.

 

Try this one out:

 

Aargh_dsdt_v2.0

 

 

I'd also like to take a peek at this one as it would match my cpu, unfortunately I'm unable to register there because I can't receive the confirmation email (UCE blocker on my mail provider side, which I cannot turn off)

 

could you attach it here? or upload it somewhere else like mediafire?

 

thx

 

mtrr

[Aargh-a-Knot]

oops, I didn't realize you would need to be logged in on that site to dl that.

 

I just found a bug with this dsdt, that makes it think its the year 2026 for a minute after waking up from sleep. I am going to try and fix that, and then I will repost another version of the dsdt, from a link that works.

[mtrr]

oops, I didn't realize you would need to be logged in on that site to dl that.

 

I just found a bug with this dsdt, that makes it think its the year 2026 for a minute after waking up from sleep. I am going to try and fix that, and then I will repost another version of the dsdt, from a link that works.

 

 

sounds good to me.

 

take care

 

mtrr

[msm5]

@msm5

 

I got some advice about the c-states that you have in your dsdt, and learned alot more about it in the process. (thanks mm67!)

 

Anyway, the q6600 only has 1 c-state, and you had 3 defined. Also, you have some stuff defined twice. I just got some insight from one of Master Chiefs recent posts, and I moved PSS, PSD, and CST out of the CPU blocks and just used aliases for all the cores. Looks much more elegant.

 

I spent the last two days building a new dsdt, using mm67's dsdt as an example. I compared his original with mine, and went in and made all the changes for the UD3P/Q6600, adding HDEF sound etc.

 

Try this one out:

 

Aargh_dsdt_v2.0

 

 

I'm right with you buddy, I've been doing the same. I also caught that post about the c-states of the q6600, which I had completely overlooked. I've attached the DSDT version that I'm currently using. Speedstepping is definitely working. I also added in audio and PATA, and adjusted the LPCB for the ICH10R. There's no graphics or LAN since they get injected at boot by netkas 10.5. This is still a work in progress, but I have found my system much more stable. The only curious thing is that sleep only works manually now. I don't know why.

 

I've attached the file below, looking forward to comparing it with yours!

 

 

msm5_EP45UD3P_Q6600.dsl.zip

[Aargh-a-Knot]

I'm right with you buddy, I've been doing the same. I also caught that post about the c-states of the q6600, which I had completely overlooked. I've attached the DSDT version that I'm currently using. Speedstepping is definitely working. I also added in audio and PATA, and adjusted the LPCB for the ICH10R. There's no graphics or LAN since they get injected at boot by netkas 10.5. This is still a work in progress, but I have found my system much more stable. The only curious thing is that sleep only works manually now. I don't know why.

 

I've attached the file below, looking forward to comparing it with yours!

 

 

msm5_EP45UD3P_Q6600.dsl.zip

 

 

OK, here ya go. Everything's working perfectly!

 

I cleaned it up all purty-like...

 

I am going to research the devices some more in the ACPI specs and add some annotations, but here is what I got now:

 

Aargh's dsdt v3.1

 

EDIT: New version, fixed P-States, and added a few details specific to my board that I had missed.

 

DSDT v4.0

 

EDIT #2: OK, this might be as far as I go with this dsdt:

 

Aargh's DSDT v4.2

 

Just over 500 lines

[msm5]

OK, here ya go. Everything's working perfectly!

 

I cleaned it up all purty-like...

 

I am going to research the devices some more in the ACPI specs and add some annotations, but here is what I got now:

 

Aargh's dsdt v3.1

 

866 lines!

Nice job, I'll comb through it today. I just reread your post from earlier in the week about idle temps. Mine are about low to mid 30's and my voltage is also set to auto. On Voodoo Monitor, while I see the temps and speed change, but the voltage is usually below the lowest pstate. I'll report back with my results with your DSDT.

[JrCs]

Hi all,

 

i have all my speedstep, AppleLPC, etc.. running and working well using your tutorial.

 

The problem is i have overclock my mobo, and i need a 1,468 voltage for my CPU to be stable.

So i put (0x0930 in VID for my Q6600 65nm CPU) but under MSR Tools it seems that the current voltage cant go futher than 1.292v. So sometime the graphic freeze and i can only hard reboot my hack.

I think it's a limitation that have been put in the kext to not overcome the specs of Intel. But did some know how to overcome this limitation ?

 

Thanks in advance for any answer that can help me.

[helob]

Yep. For my knowledge something changed from 10.5.7 > 10.5.8 how sleep worked (with kernel, AppleIntelCpu,...).

 

My dsdt is only for GA-EP35-DS3 (non P, non L) + C2D 7300 @ 3.00 (333FSB * 9) , Nvidia 8800GTX without changings. Its an miy of the known basic fixes, also includes Nvidia 8880 and some SATA / USB things.

But not!! "all you can modd" I dont like that. Less is sometimes more

 

mitch,

Thanks for sharing your dsdt.

What is non P, non L?

Also you mention using C2D 7300, just curious why you have CPU2 & CPU3 in

Scope (_PR)

Processor (CPU0.......){}

Processor (CPU1.......){}

Processor (CPU2.......){}

Processor (CPU3.......){}

TQ

[mitch_de]

My information GA-EP35-DS3 (no P , no L) means ist not an DS3L or DS3P mainboard version (they hafe little differnt hardware/bios).

The 4 CPUus are normal / default for all Mainboards , even you use an C2D and not Quad CPU- also orig. BIOS uses 4 CPU items in dsdt. Only the real available Cores are enabled (by the system OS) at runtime. YOu can see that with -v bootflag , at beginning you see some CPU0 / CPU1 enabled, CPU2/3 disabled informations by darwin.

[msm5]

OK, here ya go. Everything's working perfectly!

 

Hi Aargh-a-Knot,

 

Your DSDT is great, I fixed a few things on mine from yours that I missed. Boot time is faster, speedstepping is great. I'm still baffled why this broke autosleep for me. Thanks for posting your file and looking forward to the next revision!

[Aargh-a-Knot]

Hi Aargh-a-Knot,

 

Your DSDT is great, I fixed a few things on mine from yours that I missed. Boot time is faster, speedstepping is great. I'm still baffled why this broke autosleep for me. Thanks for posting your file and looking forward to the next revision!

 

 

Well, maybe "perfectly" was not the right word.

 

I just realized that my P-States are in fact only half working. If I watch the Status in VoodooMonitor, I can see my Frequency, Multiplier, and Temperature all changing in response to activity. Then I thought, well what about Voltage? Shouldn't it be changing also? I mean, why else is there a different Voltage defined for each step in the P-States tab?

 

I started looking into it, as I did not even know if this was an expected behavior of P-States, and I found this post by AsereBLN:

 

_PCT stands for Performance Control (ACPI spec chapter 8.4.4.1)and declares an interface that allows OSPM to transition to a specific performance state. I know to methods: one uses directly the CPU Performance Control Register (FFixedHW, 0x199) and the other one uses SystemIO to configure the P-State. I tried both methods on my system. Both are able to change the frequency, but only the direct method using the PERF_CTRL register could also change the voltage (checked with CPU-I).

 

But this object is in the SSDT, not the DSDT. I'm still pretty new to this, so I have these questions:

 

1) Is it possible to properly define this object in the DSDT, like say adding it into Scope (_PR) along with PSS, PSD, and CST?

2) If not, then how to make this work? Do we need to make and edit an entire SSDT the way we do with the DSDT?

 

From reading the ACPI Specs and AsereBLN's unfinished guide on the matter, I believe it should look like this:

 

Method (_PCT, 0, NotSerialized)

{

Return (Package (0x02)

{

ResourceTemplate () { Register (FFixedHW, 0x00, 0x00, 0x0000000000000000, ,) }, // PERF_CTRL

ResourceTemplate () { Register (FFixedHW, 0x00, 0x00, 0x0000000000000000, ,) } // PERF_STATUS

})

}

 

But where to get the red values from?

 

Also, from the ACPI specs (8.4.4), "The platform must supply all three objects if processor performance control is implemented"..."Processor performance control objects include the ‘_PCT’ package, ‘_PSS’ package, and the ‘_PPC’ method"

 

So, we would need to also include PPC?

 

If my assumptions about the Voltage changing along with the Multiplier are wrong someone please correct me.

[helob]

My information GA-EP35-DS3 (no P , no L) means ist not an DS3L or DS3P mainboard version (they hafe little differnt hardware/bios).

The 4 CPUus are normal / default for all Mainboards , even you use an C2D and not Quad CPU- also orig. BIOS uses 4 CPU items in dsdt. Only the real available Cores are enabled (by the system OS) at runtime. YOu can see that with -v bootflag , at beginning you see some CPU0 / CPU1 enabled, CPU2/3 disabled informations by darwin.

mitch,

Thanks for prompt reply. I have a GA-P35-DS3 (ICH9 chipset) motherboard and E8400 C2D CPU.

I have been following the excellent installation guide by blackosx.

He is excellent in keeping us informed on the latest changes he made on SL.

The latest is on speedstep .

However with speedstep, my CPU is running at 51 deg C which is on the high side and no auto sleep.

I have played around with only CPU0 & CPU1 only and that is why I asked you the question.

Following blackosx DSDT installation, I have 3C states even though my BIOS has only CPU EIST & C1E available only.

Changing to only 1C state in fact made it worst ( CPU temp rises to 54 deg C )

Not sure whether there is anything more I can do to bring down the CPU temp.

TQ and have a nice day