relikwie Posted November 27, 2009 Share Posted November 27, 2009 IIRC AppleLPC was needed to get the temperature down too. btw: did a test with nullcpu and voodoomini (keeping dsdt) VS dsdt speedstepping and geekbench results are way way better with dsdt speedstepping. I tought with voodomini I had a score of 2300 and with dsdt 3300 Link to comment Share on other sites More sharing options...
FKA Posted November 27, 2009 Author Share Posted November 27, 2009 IIRC AppleLPC was needed to get the temperature down too. Exactly ! Link to comment Share on other sites More sharing options...
MacKonsti Posted November 27, 2009 Share Posted November 27, 2009 Dear mm67 and FormerlyKnownAs, after I extracted my DSDT from the binary BIOS (via hex tool as per the guide from the makers of evosx.es) it was all zeros for the CPU; you reckon I should leave it with the zeros, for all four cores? What about the added code for Speedstepping? In _CST code there's a big value 0x0000000000000414 and 415 (Address) in CPU1. Should we also make them zeros, or are these irrelevant to the CPU declaration in the beginning? Dear friends, can really no-one reply to my question regarding the values in the DSDT for CPUs? Should we stick to what our BIOS holds as CPU parameters, or modify it as per post #1 instructions? Link to comment Share on other sites More sharing options...
mm67 Posted November 27, 2009 Share Posted November 27, 2009 Dear friends, can really no-one reply to my question regarding the values in the DSDT for CPUs? Should we stick to what our BIOS holds as CPU parameters, or modify it as per post #1 instructions? It is PMBASE + 14h(ACPI P_BLK+4) and PMBASE +15h(ACPI P_BLK+5), ICH10 datasheet, page 469. On this line:Processor (CPU0, 0x00, 0x00000410, 0x06) ACPI P_BLK is 410 so I use 414 for C2, 415 for C3 and 416 for C4 Link to comment Share on other sites More sharing options...
FKA Posted November 27, 2009 Author Share Posted November 27, 2009 It is PMBASE + 14h(ACPI P_BLK+4) and PMBASE +15h(ACPI P_BLK+5), ICH10 datasheet, page 469. On this line:Processor (CPU0, 0x00, 0x00000410, 0x06) ACPI P_BLK is 410 so I use 414 for C2, 415 for C3 and 416 for C4 So you can also use 810 for P_BLK and 814 C2, 815 C3 etc etc .. EDIT still doesn't answer his question though! - What do you see in you FACP table MacKonsti? [038h 0056 4] PM1A Event Block Address : 00000400 <<here? Link to comment Share on other sites More sharing options...
mm67 Posted November 27, 2009 Share Posted November 27, 2009 So you can also use 810 for P_BLK and 814 C2, 815 C3 etc etc .. No, you have to check FACP table for PMBASE, everything else is based on that Link to comment Share on other sites More sharing options...
FKA Posted November 27, 2009 Author Share Posted November 27, 2009 No, you have to check FACP table for PMBASE, everything else is based on that See edited post ! Link to comment Share on other sites More sharing options...
mm67 Posted November 27, 2009 Share Posted November 27, 2009 See edited post ! You can also use FFH interfaces like this: Return (Package (0x04) { 0x03, Package (0x04) { ResourceTemplate () { Register (FFixedHW, 0x01, // Bit Width 0x02, // Bit Offset 0x0000000000000000, // Address 0x01, // Access Size ) }, 0x01, 0x01, 0x03E8 }, Package (0x04) { ResourceTemplate () { Register (FFixedHW, 0x01, // Bit Width 0x02, // Bit Offset 0x0000000000000010, // Address 0x01, // Access Size ) }, 0x02, 0x01, 0x01F4 }, Package (0x04) { ResourceTemplate () { Register (FFixedHW, 0x01, // Bit Width 0x02, // Bit Offset 0x0000000000000030, // Address 0x03, // Access Size ) }, 0x03, 0x39, 0x64 } }) This example from my MSI board has C1, C2 and C4 states Link to comment Share on other sites More sharing options...
FKA Posted November 27, 2009 Author Share Posted November 27, 2009 You can also use FFH interfaces like this: Return (Package (0x04) { 0x03, Package (0x04) { ResourceTemplate () { Register (FFixedHW, 0x01, // Bit Width 0x02, // Bit Offset 0x0000000000000000, // Address 0x01, // Access Size ) }, 0x01, 0x01, 0x03E8 }, Package (0x04) { ResourceTemplate () { Register (FFixedHW, 0x01, // Bit Width 0x02, // Bit Offset 0x0000000000000010, // Address 0x01, // Access Size ) }, 0x02, 0x01, 0x01F4 }, Package (0x04) { ResourceTemplate () { Register (FFixedHW, 0x01, // Bit Width 0x02, // Bit Offset 0x0000000000000030, // Address 0x03, // Access Size ) }, 0x03, 0x39, 0x64 } }) This example from my MSI board has C1, C2 and C4 states I was going to ask that:- So if MacKonski turns out to have a PM1A Event Block Address = 00000000 You can edit the cst as above?! D. Link to comment Share on other sites More sharing options...
mastershredder Posted November 27, 2009 Share Posted November 27, 2009 No luck with removing the IRQ entries the two devices mentioned when i did this it caused a kernel panic of which i have no idea as it doesnt know what caused it or what thread it coresponded to. I have however noticed in the last second last page of the thread FormelyKnownAs you were talking about Phase LEDs on the gigabyte motherboard now they usually are working unitl post has finished and then go off and never come back on unitl reboot. I have just installed dynamic energy saver advanced the advanced version allows this app to work on custom overclock settings as the original version does not and voltage and core frequency needs to be set to default which is obviously useless. it is under utilities for your motherboard on gigabyte website however if it only has the original version not the advanced version i suggest u manually download the advanced version from ga-ep45-ds4 or whatever that uses it. my motherboard GA-X48-DS4 again have not mentioned that the advanced version works with my motherboard yet it does and now the phase leds work even in snow leopard. Link to comment Share on other sites More sharing options...
mm67 Posted November 27, 2009 Share Posted November 27, 2009 I was going to ask that:- So if MacKonski turns out to have a PM1A Event Block Address = 00000000 You can edit the cst as above?! D. Yes, but this is using Functional Fixed Hardware interfaces. See Intel Processor Vendor-Specific ACPI document. This one would give you C1, C2 and C3: Return (Package (0x04) { 0x03, Package (0x04) { ResourceTemplate () { Register (FFixedHW, 0x01, // Bit Width 0x02, // Bit Offset 0x0000000000000000, // Address 0x01, // Access Size ) }, 0x01, 0x01, 0x03E8 }, Package (0x04) { ResourceTemplate () { Register (FFixedHW, 0x01, // Bit Width 0x02, // Bit Offset 0x0000000000000010, // Address 0x01, // Access Size ) }, 0x02, 0x01, 0x01F4 }, Package (0x04) { ResourceTemplate () { Register (FFixedHW, 0x01, // Bit Width 0x02, // Bit Offset 0x0000000000000020, // Address 0x03, // Access Size ) }, 0x03, 0x11, 0xFA } }) Link to comment Share on other sites More sharing options...
italy4ever Posted November 27, 2009 Share Posted November 27, 2009 no one can help me? i spent a lot of time on dsdt editing to have speedstep and sleep working(thanks to zhell's trick) but only speedstep is working at the moment any suggestions? Link to comment Share on other sites More sharing options...
mastershredder Posted November 28, 2009 Share Posted November 28, 2009 right finally got past the kernel panic i was having after i removed the IRQ entries from the two devices PIC and TMR i beleive you need to look at your own extracted FACP table and under the entries you should see something similar :- [05Fh 095 1] _CST Support : 00 [060h 096 2] C2 Latency : 0065 //values may vary here just substitute mine for yours [062h 098 2] C3 Latency : 03E9 you need to use these entries for c2 and c3 in the dsdt if you have used the template provided by FormelyKnownAs you need to put these hex values here under the CST methods for CPU0 and CPU1:- Method (_CST, 0, NotSerialized) { Return (Package (0x02) { One, Package (0x04) { ResourceTemplate () { Register (FFixedHW, 0x01, // Bit Width 0x02, // Bit Offset 0x0000000000000000, // Address 0x01, // Access Size ) }, One, 0x9D, // C2 Latency - replace with what values are in your FACP table. 0x03E8 //C3 Latency - replace thes values with what is in your FACP table Example of mine for CPU0 _CST method Method (_CST, 0, NotSerialized) { Return (Package (0x02) { One, Package (0x04) { ResourceTemplate () { Register (FFixedHW, 0x01, // Bit Width 0x02, // Bit Offset 0x0000000000000000, // Address 0x01, // Access Size ) }, One, 0x65, // C2 latency - replace with what values are in your FACP table. 0x03E9 // C3 latency - replace with what values are in your FACP table. also this is the cst method for CPU0 you need to do it for CPU1 CST Method as well that would look like this :- Method (_CST, 0, NotSerialized) { Return (Package (0x04) { 0x03, Package (0x04) { ResourceTemplate () { Register (FFixedHW, 0x01, // Bit Width 0x02, // Bit Offset 0x0000000000000000, // Address ,) }, One, Zero, 0x03E9 // only change this value do not change the one named Zero i havent tried setting it as anything else and it works. do not modify the values that are at the end of the CST method in CPU1 they look like this leave them as they are: - Package (0x04) { ResourceTemplate () { Register (FFixedHW, 0x08, // Bit Width 0x00, // Bit Offset 0x0000000000000414, // Address ,) }, 0x02, One, //Do not modify 0x01F4 //Do not modify }, Package (0x04) { ResourceTemplate () { Register (FFixedHW, 0x08, // Bit Width 0x00, // Bit Offset 0x0000000000000415, // Address ,) }, 0x03, //Do not modify 0x55, //Do not modify 0xFA //Do not modify } }) } Link to comment Share on other sites More sharing options...
Shaj Posted November 28, 2009 Share Posted November 28, 2009 Hey mastershredder, I'm currently using FormerlyKnownAs' Generic scope. What and how much of a difference will the above changes make? And does it mean I currently don't have the c-states working the way they should (if not at all)? Link to comment Share on other sites More sharing options...
mastershredder Posted November 28, 2009 Share Posted November 28, 2009 hey Shaj lf you go through the last 5 pages or so of this thread i have posted various messages about the status of my speedstepping it took many hours of fiddling about to get just a couple of pstates working correctly however that was all worth it as i now have all 4 pstates for my cpu even windows doesnt use 4. My original DSDT which was extracted using everest ultimate in windows shows only 2 pstates for my cpu one for the highest multiplier and one for the lowest now as far as the cst method goes i was getting very strange results when those methods were included in the dsdt when loading on the apple screen at boot the little grey wheel that spins was lagging and then the desktop felt a little sluggish compared to when they werent in the dsdt. I figured something must be wrong. The CST tables were working as i had an even further reduction in temps and the errors had gone from kernel.log but itunes was laso lagging when playing mp3's which was obviously unacceptable. I did the method mentioned by FormelyKnownAs which is on page 16 which was to delete the IRQ references in the following Devices in DSDT (PIC) and (TMR) this howeveer resulted in even more strange behaviour starting with kernel panic on first boot then susquent boots did strange things like it never got to the desktop but when the blue screen shows it looked as if it was stuck in a loop of continually reloading that section. Again this was unnaceptable so i tried one more time taking specific care to look at my FACP dump from everest is shows the latency timings for the C States one of which was ever so slightlt different from the one written in the generic scope. After doing this and the included IRQ method from above it bootedfine no wierd lagg problem no stability problem no CST errors in kernel.log and temps have had the extra 5 C shaved off compared with just using pStates. Also my motherboard GA-X48-DS4 has never been able to sleep regardless of operating system i have spoken to various gigabyte techs who were unable to resolve and suggested an RMA which i didnt want to do so i lived with it but since doing this DSDT modification sleep works 100% on mac now which is great. Also geekbench now shows 6400 on mac and 5300 on windows 7 which i thought was lol. attached is my current DSDT which for me has everything working. Also a nice pic to show Temps as of this morning its slightly colder than it shud be because im freezing my ass off this morning they are usually about 28C or so which is impressive as before pstates were included they were about 40C with pstates they were about 33 -35 C and now with Cstates 28-30C. Now finally all i have to tackle in my system is the dreaded Alc889a audio which i have working but a few irratating things like front panel doesnt work and stupid sound assertion errors in kernel.log then thats it for me no more errors in my log when booting. One final note for anyone who is still struggling make sure your smbios.plist is using macpro 3.1 i found out last night if i removed all entries relating to model identier board etc system profiler shows as mac pro 2.1 which i though was great because app like geekbench and ibench show up as macpro however pstates then do not work this is dues the the plist entries in the ACPI_SMC_PlatformPlugin.kext if you look at the plists in there the one for macpro 2.1 has a lot less power saving techniques and this was causing all pstates to fail. this is unfortunate as when setting model to macpro 3.1 in smbios.plist ibench and geekbench now show hackintosh as model which is a shame. Attached also is my smbios.plist just remeber to change any settings regarding FSB and memory to your own or it will change your current configuration in about this mac. DSDT.dsl.zip smbios.plist.zip Link to comment Share on other sites More sharing options...
FKA Posted November 28, 2009 Author Share Posted November 28, 2009 Thanks Shaj I'll add finding correct CST latencies to post#1 and should also lay out the removal of IRQ's . D. Link to comment Share on other sites More sharing options...
mastershredder Posted November 28, 2009 Share Posted November 28, 2009 Thanks Shaj I'll add finding correct CST latencies to post#1 and should also lay out the removal of IRQ's . D. Thanks Shaj? I hope this was just a typo Link to comment Share on other sites More sharing options...
FKA Posted November 28, 2009 Author Share Posted November 28, 2009 Thanks Shaj? I hope this was just a typo trying to do too many things at once --- sorry MrShrededer Link to comment Share on other sites More sharing options...
cvad Posted November 28, 2009 Share Posted November 28, 2009 ... Method (_CST, 0, NotSerialized) { Return (Package (0x02) { One, Package (0x04) {ResourceTemplate () {Register (FFixedHW, 0x01, 0x02, 0x0000000000000000, 0x01,)}, One, [color="#FF0000"][b][s]0x9D[/s][/b][/color], // [s]C2 Latency - replace with what values are in your FACP table.[/s] // [color="#FF0000"][b]C1 Latency (0x00)[/b][/color] [color="#0000FF"][b]0x03E8[/b][/color] //[s]C3 Latency - replace thes values with what is in your FACP table[/s] // [color="#0000FF"][b]Power[/b][/color] } } } ... It seems to me, more truly, will be so: 8.4.2.1 _CST (C States) // ACPIspec30b.pdf... CState: Package (Register, Type, Latency, Power) Where: Register: RegisterTerm A register that OSPM reads to place the processor in the corresponding C state. Type: ByteConst The C State type (for example, 1=C1, 2=C2, 3=C3). This field conveys the semantics to be used by OSPM when entering/exiting the C state. Zero is not a valid value Latency: WordConst The worst-case latency in microseconds to enter and exit the C State. There are no latency restrictions. Power: DWordConst The average power consumption in milliwatts of the processor when in the corresponding C State. Link to comment Share on other sites More sharing options...
mastershredder Posted November 28, 2009 Share Posted November 28, 2009 It seems to me, more truly, will be so: I have just really started to scratch the surface of the importance of these tables and the values they contain tbh i really didnt know what these valeus were only they were very similar to the one listed in my FACP table and they showed they were the C2 and C3 latencies whether this is actually the case doesnt really matter to me as i have it working now by using the values used from my extracted FACP table as before using the values that were in the generic scope was casuing very strange behaviour in Mac Link to comment Share on other sites More sharing options...
cvad Posted November 28, 2009 Share Posted November 28, 2009 Updated 12.07.09: My FASP table: [000h 0000 4] Signature : "FACP" /* Fixed ACPI Description Table */ [004h 0004 4] Table Length : 000000F4 [008h 0008 1] Revision : 03 [009h 0009 1] Checksum : 30 [00Ah 0010 6] Oem ID : "MSTEST" [010h 0016 8] Oem Table ID : "OEMFACP " [018h 0024 4] Oem Revision : 09000830 [01Ch 0028 4] Asl Compiler ID : "MSFT" [020h 0032 4] Asl Compiler Revision : 00000097 [024h 0036 4] FACS Address : BFF9E000 [028h 0040 4] DSDT Address : 00B8D000 [02Ch 0044 1] Model : 01 [02Dh 0045 1] PM Profile : 01 (Desktop) [02Eh 0046 2] SCI Interrupt : 0009 [030h 0048 4] SMI Command Port : 000000B2 [034h 0052 1] ACPI Enable Value : E1 [035h 0053 1] ACPI Disable Value : 1E [036h 0054 1] S4BIOS Command : 00 [037h 0055 1] P-State Control : E2 [038h 0056 4] [b]PM1A Event Block Address : 00000800[/b] [03Ch 0060 4] PM1B Event Block Address : 00000000 [040h 0064 4] PM1A Control Block Address : 00000804 [044h 0068 4] PM1B Control Block Address : 00000000 [048h 0072 4] PM2 Control Block Address : 00000000 [04Ch 0076 4] PM Timer Block Address : 00000808 [050h 0080 4] GPE0 Block Address : 00000828 [054h 0084 4] GPE1 Block Address : 00000000 [058h 0088 1] PM1 Event Block Length : 04 [059h 0089 1] PM1 Control Block Length : 02 [05Ah 0090 1] PM2 Control Block Length : 00 [05Bh 0091 1] PM Timer Block Length : 04 [05Ch 0092 1] GPE0 Block Length : 08 [05Dh 0093 1] GPE1 Block Length : 00 [05Eh 0094 1] GPE1 Base Offset : 00 [05Fh 0095 1] _CST Support : E3 [060h 0096 2] [b]C2 Latency : [color="#FF0000"]0065[/color][/b] -->> If this value >100 then C2-State tune off. [062h 0098 2] [b]C3 Latency : [color="#0000FF"]03E9[/color][/b] -->> If this value >1000 then C3-State tune off. [064h 0100 2] CPU Cache Size : 0400 [066h 0102 2] Cache Flush Stride : 0010 [068h 0104 1] Duty Cycle Offset : 01 [069h 0105 1] Duty Cycle Width : 00 [06Ah 0106 1] RTC Day Alarm Index : 0D [06Bh 0107 1] RTC Month Alarm Index : 00 [06Ch 0108 1] RTC Century Index : 32 [06Dh 0109 2] Boot Flags (decoded below) : 0003 Legacy Devices Supported (V2) : 1 8042 Present on ports 60/64 (V2) : 1 VGA Not Present (V4) : 0 MSI Not Supported (V4) : 0 PCIe ASPM Not Supported (V4) : 0 [06Fh 0111 1] Reserved : 00 [070h 0112 4] Flags (decoded below) : 000000A5 WBINVD instruction is operational (V1) : 1 WBINVD flushes all caches (V1) : 0 All CPUs support C1 (V1) : 1 C2 works on MP system (V1) : 0 Control Method Power Button (V1) : 0 Control Method Sleep Button (V1) : 1 RTC wake not in fixed reg space (V1) : 0 RTC can wake system from S4 (V1) : 1 32-bit PM Timer (V1) : 0 Docking Supported (V1) : 0 Reset Register Supported (V2) : 0 Sealed Case (V3) : 0 Headless - No Video (V3) : 0 Use native instr after SLP_TYPx (V3) : 0 PCIEXP_WAK Bits Supported (V4) : 0 Use Platform Timer (V4) : 0 RTC_STS valid on S4 wake (V4) : 0 Remote Power-on capable (V4) : 0 Use APIC Cluster Model (V4) : 0 Use APIC Physical Destination Mode (V4) : 0 [074h 0116 12] Reset Register : <Generic Address Structure> [074h 0116 1] Space ID : 01 (SystemIO) [075h 0117 1] Bit Width : 08 [076h 0118 1] Bit Offset : 00 [077h 0119 1] Access Width : 00 [078h 0120 8] Address : 0000000000000CF9 [080h 0128 1] Value to cause reset : 06 [081h 0129 3] Reserved : 000000 [084h 0132 8] FACS Address : 00000000BFF9E000 [08Ch 0140 8] DSDT Address : 0000000000B8D000 [094h 0148 12] PM1A Event Block : <Generic Address Structure> [094h 0148 1] Space ID : 01 (SystemIO) [095h 0149 1] Bit Width : 20 [096h 0150 1] Bit Offset : 00 [097h 0151 1] Access Width : 00 [098h 0152 8] Address : 0000000000000800 [0A0h 0160 12] PM1B Event Block : <Generic Address Structure> [0A0h 0160 1] Space ID : 01 (SystemIO) [0A1h 0161 1] Bit Width : 20 [0A2h 0162 1] Bit Offset : 00 [0A3h 0163 1] Access Width : 00 [0A4h 0164 8] Address : 0000000000000000 [0ACh 0172 12] PM1A Control Block : <Generic Address Structure> [0ACh 0172 1] Space ID : 01 (SystemIO) [0ADh 0173 1] Bit Width : 10 [0AEh 0174 1] Bit Offset : 00 [0AFh 0175 1] Access Width : 00 [0B0h 0176 8] Address : 0000000000000804 [0B8h 0184 12] PM1B Control Block : <Generic Address Structure> [0B8h 0184 1] Space ID : 00 (SystemMemory) [0B9h 0185 1] Bit Width : 00 [0BAh 0186 1] Bit Offset : 00 [0BBh 0187 1] Access Width : 00 [0BCh 0188 8] Address : 0000000000000000 [0C4h 0196 12] PM2 Control Block : <Generic Address Structure> [0C4h 0196 1] Space ID : 00 (SystemMemory) [0C5h 0197 1] Bit Width : 00 [0C6h 0198 1] Bit Offset : 00 [0C7h 0199 1] Access Width : 00 [0C8h 0200 8] Address : 0000000000000000 [0D0h 0208 12] PM Timer Block : <Generic Address Structure> [0D0h 0208 1] Space ID : 01 (SystemIO) [0D1h 0209 1] Bit Width : 20 [0D2h 0210 1] Bit Offset : 00 [0D3h 0211 1] Access Width : 00 [0D4h 0212 8] Address : 0000000000000808 [0DCh 0220 12] GPE0 Block : <Generic Address Structure> [0DCh 0220 1] Space ID : 01 (SystemIO) [0DDh 0221 1] Bit Width : 40 [0DEh 0222 1] Bit Offset : 00 [0DFh 0223 1] Access Width : 00 [0E0h 0224 8] Address : 0000000000000828 [0E8h 0232 12] GPE1 Block : <Generic Address Structure> [0E8h 0232 1] Space ID : 01 (SystemIO) [0E9h 0233 1] Bit Width : 20 [0EAh 0234 1] Bit Offset : 00 [0EBh 0235 1] Access Width : 00 [0ECh 0236 8] Address : 0000000000000000 I use following values: Method (_CST, 0, NotSerialized) { Return (Package () { 0x03, // 0x03 Number of C-State packages: 3 (C1, C2 and C3). Package (0x04) {ResourceTemplate () {Register (FFixedHW, 0x01, 0x02, 0x000, 0x00,)}, One, [b][color="#9932CC"]One[/color][/b], 0x03E8}, // [b][color="#9932CC"]C1[/color][/b] Latency Package (0x04) {ResourceTemplate () {Register (SystemIO, 0x08, 0x00, 0x814, ,)}, 0x02, [b][color="#FF0000"]One[/color][/b], 0x01F4}, // [b][color="#FF0000"]C2[/color][/b] Latency (no more than 100) Package (0x04) {ResourceTemplate () {Register (SystemIO, 0x08, 0x00, 0x815, ,)}, 0x03, [b][color="#0000FF"]0x55[/color][/b], 0xFA} // [b][color="#0000FF"]C3[/color][/b] Latency (no more than 1000) }) } Link to comment Share on other sites More sharing options...
FKA Posted November 28, 2009 Author Share Posted November 28, 2009 I have just really started to scratch the surface of the importance of these tables and the values they contain tbh i really didnt know what these valeus were only they were very similar to the one listed in my FACP table and they showed they were the C2 and C3 latencies whether this is actually the case doesnt really matter to me as i have it working now by using the values used from my extracted FACP table as before using the values that were in the generic scope was casuing very strange behaviour in Mac OK Guys -- For the record !! Package (0x04) { ResourceTemplate () { Register (FFixedHW, 0x08, // Bit Width 0x00, // Bit Offset 0x0000000000000414, // Address ,) }, 0x02, //interger >type ... in this case 2 > C2 One, // interger > latency .... 0x01F4 //Power ... in this case 500 - as previously discussed this appears to be a % value }, shredder - what you are seeing in the FACP table listed as C2 latency C3 latency, in my FACP appears to be power - 1000%, 500% etc ... etc .. Thye only value you may need to change in the _cst table is the address: 0x08, // Bit Width 0x00, // Bit Offset 0x00000000000[b][color="#ff0000"]00414[/color][/b], // Address ,) }, this will (as pointed out by mm67) depend upon the PMBASE value from the FACP table: [038h 0056 4] PM1A Event Block Address : 00000[color="#ff0000"]400[/color] < here Values seen here generally are 0000400 or 0000800 if its 400 then your C-state addresses will be 0x0000000000000414 for C2 > 0x0000000000000415 for C3 etc If its 800 then C-state address will be 0x0000000000000814 for C2 > 0x0000000000000815 for C3 etc etc .. I will add this to post#1 when i get a chance. D. Method (_CST, 0, NotSerialized) { Return (Package () { 0x03, // 0x03 Number of C-State packages: 3 (C1, C2 and C3). Package (0x04) {ResourceTemplate () {Register (FFixedHW, 0x01, 0x02, 0x000, 0x00,)}, One, [b][color="#9932cc"]One[/color][/b], 0x03E8}, // [b][color="#9932cc"]C1[/color][/b] Latency Package (0x04) {ResourceTemplate () {Register (SystemIO, 0x08, 0x00, 0x814, ,)}, 0x02, [b][color="#ff0000"]0x64[/color][/b], 0x01F4}, // [b][color="#ff0000"]C2[/color][/b] Latency (no more than 100) Package (0x04) {ResourceTemplate () {Register (SystemIO, 0x08, 0x00, 0x815, ,)}, 0x03, [b][color="#0000ff"]0x03E8[/color][/b], 0xFA} // [b][color="#0000ff"]C3[/color][/b] Latency (no more than 1000) }) } a latency of 1000 > doesn't seem right?! I have the exact same values for C2 and C3 Latency in my FACP... Looking at MP3,1 cst table > Method (_CST, 0, NotSerialized) { If (LAnd (And (CFGD, 0x01000000), LNot (And (PDC0, 0x10 )))) { Return (Package (0x02) { 0x01, Package (0x04) { ResourceTemplate () { Register (FFixedHW, 0x00, // Bit Width 0x00, // Bit Offset 0x0000000000000000, // Address ,) }, 0x01, 0x9D, 0x03E8 } }) } If (And (PDC0, 0x0300)) { If (And (CFGD, 0x20)) { Return (Package (0x03) { 0x02, Package (0x04) { ResourceTemplate () { Register (FFixedHW, 0x01, // Bit Width 0x02, // Bit Offset 0x0000000000000000, // Address ,) }, 0x01, 0x01, 0x03E8 }, Package (0x04) { ResourceTemplate () { Register (FFixedHW, 0x01, // Bit Width 0x02, // Bit Offset 0x0000000000000010, // Address ,) }, 0x02, 0x01, 0x01F4 } }) } } If (And (CFGD, 0x20)) { Return (Package (0x03) { 0x02, Package (0x04) { ResourceTemplate () { Register (FFixedHW, 0x01, // Bit Width 0x02, // Bit Offset 0x0000000000000000, // Address ,) }, 0x01, 0x01, 0x03E8 }, Package (0x04) { ResourceTemplate () { Register (SystemIO, 0x08, // Bit Width 0x00, // Bit Offset 0x000000000000000C, // Address ,) }, 0x02, 0x01, 0x01F4 } }) } Return (Package (0x02) { 0x01, Package (0x04) { ResourceTemplate () { Register (FFixedHW, 0x01, // Bit Width 0x02, // Bit Offset 0x0000000000000000, // Address ,) }, 0x01, 0x01, 0x03E8 } }) } } Latency is never more than 1! Any body have a native GigaByte or Asus cst table we can look at? EDIT ### Ok in ACPI spec it is stated as "worst case" latency - so such high values don't seem to strainge! Anybody ? Bueller ? Anybody ? Link to comment Share on other sites More sharing options...
mm67 Posted November 28, 2009 Share Posted November 28, 2009 Latency is never more than 1! Any body have a native GigaByte or Asus cst table we can look at? Here you go, Gigabyte original CST Scope (\_PR.CPU0) { Method (_CST, 0, NotSerialized) { If (And (CFGD, 0x80)) { Return (Package (0x04) { 0x03, Package (0x04) { ResourceTemplate () { Register (FFixedHW, 0x00, // Bit Width 0x00, // Bit Offset 0x0000000000000000, // Address ,) }, 0x01, 0x01, 0x03E8 }, Package (0x04) { ResourceTemplate () { Register (SystemIO, 0x08, // Bit Width 0x00, // Bit Offset 0x0000000000000414, // Address ,) }, 0x02, 0x01, 0x01F4 }, Package (0x04) { ResourceTemplate () { Register (SystemIO, 0x08, // Bit Width 0x00, // Bit Offset 0x0000000000000416, // Address ,) }, 0x03, 0x96, 0x64 } }) } If (And (CFGD, 0x40)) { Return (Package (0x04) { 0x03, Package (0x04) { ResourceTemplate () { Register (FFixedHW, 0x00, // Bit Width 0x00, // Bit Offset 0x0000000000000000, // Address ,) }, 0x01, 0x01, 0x03E8 }, Package (0x04) { ResourceTemplate () { Register (SystemIO, 0x08, // Bit Width 0x00, // Bit Offset 0x0000000000000414, // Address ,) }, 0x02, 0x01, 0x01F4 }, Package (0x04) { ResourceTemplate () { Register (SystemIO, 0x08, // Bit Width 0x00, // Bit Offset 0x0000000000000415, // Address ,) }, 0x03, 0x55, 0xFA } }) } If (And (CFGD, 0x20)) { Return (Package (0x03) { 0x02, Package (0x04) { ResourceTemplate () { Register (FFixedHW, 0x00, // Bit Width 0x00, // Bit Offset 0x0000000000000000, // Address ,) }, 0x01, 0x01, 0x03E8 }, Package (0x04) { ResourceTemplate () { Register (SystemIO, 0x08, // Bit Width 0x00, // Bit Offset 0x0000000000000414, // Address ,) }, 0x02, 0x01, 0x01F4 } }) } Return (Package (0x02) { 0x01, Package (0x04) { ResourceTemplate () { Register (FFixedHW, 0x00, // Bit Width 0x00, // Bit Offset 0x0000000000000000, // Address ,) }, 0x01, 0x01, 0x03E8 } }) } } And one from MSI Scope (\_PR.P001) { Method (_CST, 0, NotSerialized) { If (LAnd (LGreater (NCPU, 0x01), LNot (And (PDC0, 0x10)))) { Return (Package (0x02) { 0x01, Package (0x04) { ResourceTemplate () { Register (FFixedHW, 0x00, // Bit Width 0x00, // Bit Offset 0x0000000000000000, // Address ,) }, 0x01, 0x9D, 0x03E8 } }) } If (LAnd (And (CFGD, 0x00200000), And (PDC0, 0x0200))) { If (And (CFGD, 0x80)) { Return (Package (0x04) { 0x03, Package (0x04) { ResourceTemplate () { Register (FFixedHW, 0x01, // Bit Width 0x02, // Bit Offset 0x0000000000000000, // Address 0x01, // Access Size ) }, 0x01, 0x01, 0x03E8 }, Package (0x04) { ResourceTemplate () { Register (FFixedHW, 0x01, // Bit Width 0x02, // Bit Offset 0x0000000000000010, // Address 0x01, // Access Size ) }, 0x02, 0x01, 0x01F4 }, Package (0x04) { ResourceTemplate () { Register (FFixedHW, 0x01, // Bit Width 0x02, // Bit Offset 0x0000000000000030, // Address 0x03, // Access Size ) }, 0x03, 0x39, 0x64 } }) } If (LAnd (LNot (And (CFGD, 0x80)), And (CFGD, 0x40 ))) { Return (Package (0x04) { 0x03, Package (0x04) { ResourceTemplate () { Register (FFixedHW, 0x01, // Bit Width 0x02, // Bit Offset 0x0000000000000000, // Address 0x01, // Access Size ) }, 0x01, 0x01, 0x03E8 }, Package (0x04) { ResourceTemplate () { Register (FFixedHW, 0x01, // Bit Width 0x02, // Bit Offset 0x0000000000000010, // Address 0x01, // Access Size ) }, 0x02, 0x01, 0x01F4 }, Package (0x04) { ResourceTemplate () { Register (FFixedHW, 0x01, // Bit Width 0x02, // Bit Offset 0x0000000000000020, // Address 0x03, // Access Size ) }, 0x03, 0x11, 0xFA } }) } If (And (CFGD, 0x20)) { Return (Package (0x03) { 0x02, Package (0x04) { ResourceTemplate () { Register (FFixedHW, 0x01, // Bit Width 0x02, // Bit Offset 0x0000000000000000, // Address 0x01, // Access Size ) }, 0x01, 0x01, 0x03E8 }, Package (0x04) { ResourceTemplate () { Register (FFixedHW, 0x01, // Bit Width 0x02, // Bit Offset 0x0000000000000010, // Address 0x01, // Access Size ) }, 0x02, 0x01, 0x01F4 } }) } Return (Package (0x02) { 0x01, Package (0x04) { ResourceTemplate () { Register (FFixedHW, 0x01, // Bit Width 0x02, // Bit Offset 0x0000000000000000, // Address 0x01, // Access Size ) }, 0x01, 0x01, 0x03E8 } }) } If (LAnd (And (CFGD, 0x00200000), And (PDC0, 0x0100))) { If (And (CFGD, 0x80)) { Return (Package (0x04) { 0x03, Package (0x04) { ResourceTemplate () { Register (FFixedHW, 0x01, // Bit Width 0x02, // Bit Offset 0x0000000000000000, // Address 0x01, // Access Size ) }, 0x01, 0x01, 0x03E8 }, Package (0x04) { ResourceTemplate () { Register (SystemIO, 0x08, // Bit Width 0x00, // Bit Offset 0x0000000000000814, // Address ,) }, 0x02, 0x01, 0x01F4 }, Package (0x04) { ResourceTemplate () { Register (SystemIO, 0x08, // Bit Width 0x00, // Bit Offset 0x0000000000000816, // Address ,) }, 0x03, 0x39, 0x64 } }) } If (LAnd (LNot (And (CFGD, 0x80)), And (CFGD, 0x40 ))) { Return (Package (0x04) { 0x03, Package (0x04) { ResourceTemplate () { Register (FFixedHW, 0x01, // Bit Width 0x02, // Bit Offset 0x0000000000000000, // Address 0x01, // Access Size ) }, 0x01, 0x01, 0x03E8 }, Package (0x04) { ResourceTemplate () { Register (SystemIO, 0x08, // Bit Width 0x00, // Bit Offset 0x0000000000000814, // Address ,) }, 0x02, 0x01, 0x01F4 }, Package (0x04) { ResourceTemplate () { Register (SystemIO, 0x08, // Bit Width 0x00, // Bit Offset 0x0000000000000815, // Address ,) }, 0x03, 0x11, 0xFA } }) } If (And (CFGD, 0x20)) { Return (Package (0x03) { 0x02, Package (0x04) { ResourceTemplate () { Register (FFixedHW, 0x01, // Bit Width 0x02, // Bit Offset 0x0000000000000000, // Address 0x01, // Access Size ) }, 0x01, 0x01, 0x03E8 }, Package (0x04) { ResourceTemplate () { Register (SystemIO, 0x08, // Bit Width 0x00, // Bit Offset 0x0000000000000814, // Address ,) }, 0x02, 0x01, 0x01F4 } }) } Return (Package (0x02) { 0x01, Package (0x04) { ResourceTemplate () { Register (FFixedHW, 0x01, // Bit Width 0x02, // Bit Offset 0x0000000000000000, // Address 0x01, // Access Size ) }, 0x01, 0x01, 0x03E8 } }) } If (And (CFGD, 0x80)) { Return (Package (0x04) { 0x03, Package (0x04) { ResourceTemplate () { Register (FFixedHW, 0x00, // Bit Width 0x00, // Bit Offset 0x0000000000000000, // Address ,) }, 0x01, 0x01, 0x03E8 }, Package (0x04) { ResourceTemplate () { Register (SystemIO, 0x08, // Bit Width 0x00, // Bit Offset 0x0000000000000814, // Address ,) }, 0x02, 0x01, 0x01F4 }, Package (0x04) { ResourceTemplate () { Register (SystemIO, 0x08, // Bit Width 0x00, // Bit Offset 0x0000000000000816, // Address ,) }, 0x03, 0x39, 0x64 } }) } If (LAnd (LNot (And (CFGD, 0x80)), And (CFGD, 0x40 ))) { Return (Package (0x04) { 0x03, Package (0x04) { ResourceTemplate () { Register (FFixedHW, 0x00, // Bit Width 0x00, // Bit Offset 0x0000000000000000, // Address ,) }, 0x01, 0x01, 0x03E8 }, Package (0x04) { ResourceTemplate () { Register (SystemIO, 0x08, // Bit Width 0x00, // Bit Offset 0x0000000000000814, // Address ,) }, 0x02, 0x01, 0x01F4 }, Package (0x04) { ResourceTemplate () { Register (SystemIO, 0x08, // Bit Width 0x00, // Bit Offset 0x0000000000000815, // Address ,) }, 0x03, 0x11, 0x64 } }) } If (And (CFGD, 0x20)) { Return (Package (0x03) { 0x02, Package (0x04) { ResourceTemplate () { Register (FFixedHW, 0x00, // Bit Width 0x00, // Bit Offset 0x0000000000000000, // Address ,) }, 0x01, 0x01, 0x03E8 }, Package (0x04) { ResourceTemplate () { Register (SystemIO, 0x08, // Bit Width 0x00, // Bit Offset 0x0000000000000814, // Address ,) }, 0x02, 0x01, 0x01F4 } }) } Return (Package (0x02) { 0x01, Package (0x04) { ResourceTemplate () { Register (FFixedHW, 0x00, // Bit Width 0x00, // Bit Offset 0x0000000000000000, // Address ,) }, 0x01, 0x01, 0x03E8 } }) } } Link to comment Share on other sites More sharing options...
MacUser2525 Posted November 28, 2009 Share Posted November 28, 2009 Any body have a native GigaByte or Asus cst table we can look at? I have all the dumps I did under Debian in the attached archive perhaps they can help. One thing though using masteshreder's idea for C2 & C3 I have finally seen a voltage lower than my default lowest pstate so it appears to enter a cstate using that in my test machine. Linux_Dumps.zip Link to comment Share on other sites More sharing options...
FKA Posted November 28, 2009 Author Share Posted November 28, 2009 I have all the dumps I did under Debian in the attached archive perhaps they can help. One thing though using masteshreder's idea for C2 & C3 I have finally seen a voltage lower than my default lowest pstate so it appears to enter a cstate using that in my test machine. Thanks, Stuck at work ATM - I'll try with my max latency values from FACP later on and report back! Thinking about it it does make sence 'worst case latency to enter and exit c-state' If it's too short a time it could lead to flip flopping in and out of states or simply never entering them .. D. Link to comment Share on other sites More sharing options...
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