DSDT - Vanilla Speedstep - Generic Scope (_PR)

blackosx · November 25, 2009

I think we discovered that 410 was for quad core and 810 for dual (please someone correct if wrong.)

If that's correct then I will change my data. I have been using 410 so far with my core2duo. My original DSDT also used 410 so I carried on using it. Thanks

FKA · November 25, 2009

If that's correct then I will change my data. I have been using 410 so far with my core2duo. My original DSDT also used 410 so I carried on using it. Thanks

I must be wrong then - stick with original.

D.

mitch_de · November 25, 2009

If that's correct then I will change my data. I have been using 410 so far with my core2duo. My original DSDT also used 410 so I carried on using it. Thanks

Same to me (GA-EP35_DS3) orig. DSDT has 100% 410 (+414/415 later in dsdt) using my C2D cpu. So i use that.

I would never ever change that until i find other DSDT info when i switch cpu and readout again orig. DSDT.

So again: If user posting DSDT content it is absolutly needed to post also mainboard + cpu type to be sure to use it as seen or edit it befpre using.

PS: The 410 / 810 is not only found in the CPU part , also later in CST (?) as 414/415 or 814/815 !!!!

Be sure to use ALL right.

mm67 · November 25, 2009

I must be wrong then - stick with original.
D.

Take a look at your FACP table:

Gigabyte

[038h 0056 4] PM1A Event Block Address : 00000400

Msi

[038h 0056 4] PM1A Event Block Address : 00000800

Now you see where those 410,810 etc addresses come from...

blackosx · November 25, 2009

Take a look at your FACP table:
Gigabyte

[038h 0056 4] PM1A Event Block Address : 00000400

Msi

[038h 0056 4] PM1A Event Block Address : 00000800

Now you see where those 410,810 etc addresses come from...

Ah ha... Thanks mm67. Yes, I see it now in my FACP.

I have not really studied the other files from my ACPIdump, apart from SSDT and DSDT. I have so much more to try to understand now.

mastershredder · November 25, 2009

Right finally made some headway i have speedstepping working by using the values in my dumped SSDT table which shows my cpu only has 2 steps one for x9 multiplier and one for x6 multiplier when using voodoopstate.kext it shows 4 pstates x9 x8 x7 x6 when using the values shown in pstatechanger app it fails to work it just stays at the lowest pstate which is x6. However even tho i have the speed stepping working i am still getting the laggy performance on the desktop and playing mp3s shows a slight decrease in the speed at which they are played does anyone know why this is occuring and what i would need to alter to fix this behaviour?

thanks for any response and also thanks FormelyKnownAs for your reply again

attached is the working DSDT.dsl

DSDT.dsl.zip

emp_% · November 25, 2009

Your vCore does not change because you have entered the same VId value (28) for each p-state.

I think there was a bug in pstatechanger after another reboot it showed me correct vids:

After I entered the generic scope I got a Kernel panic for hpet missing.

Attaching dsdtnospeedstep and dsdtwithit.

dsdts.zip

[Edit] Maybe I found the error in the check regarding OSFX:

My dsdt

 
                              Device (HPET)
               {
                   Name (_HID, EisaId ("PNP0103"))
                   Name (ATT3, ResourceTemplate ()
                   {
                       IRQNoFlags ()
                           {0}
                       IRQNoFlags ()
                           {8}
                       Memory32Fixed (ReadWrite,
                           0xFED00000,         // Address Base
                           0x00000400,         // Address Length
                           )
                   })
                   Name (ATT4, ResourceTemplate ()
                   {
                   })
                   Method (_STA, 0, NotSerialized)
                   {
                       If (LGreaterEqual (OSFX, 0x03))
                       {
                           If (HPTF)
                           { 
                               Return (0x0F)
                           }
                           Else
                           {
                               Return (Zero)
                           }
                       }
                       Else
                       {
                           Return (Zero)
                       }
                   }

                   Method (_CRS, 0, NotSerialized)
                   {
                       If (LGreaterEqual (OSFX, 0x03))
                       {
                           If (HPTF)
                           {
                               Return (ATT3)
                           }
                           Else
                           {
                               Return (ATT4)
                           }
                       }
                       Else
                       {
                           Return (ATT4)
                       }
                   }
               }

Your dsdt:

               Device (HPET)
               {
                   Name (_HID, EisaId ("PNP0103"))
                   Name (ATT3, ResourceTemplate ()
                   {
                       IRQNoFlags ()
                           {0}
                       IRQNoFlags ()
                           {8}
                       Memory32Fixed (ReadWrite,
                           0xFED00000,         // Address Base
                           0x00000400,         // Address Length
                           )
                   })
                   Name (ATT4, ResourceTemplate ()
                   {
                   })
                   Method (_STA, 0, NotSerialized)
                   {
                       Return (0x0F)
                   }

                   Method (_CRS, 0, NotSerialized)
                   {
                       Return (ATT3)
                   }
               }

Changed the code removing the check for OSFX and no kernel panic

FormerlyKnownAs you are my new hero.

DSDTwithSpeedstep.dsl.zip

MacKonsti · November 25, 2009

Take a look at your FACP table:
Gigabyte

[038h 0056 4] PM1A Event Block Address : 00000400

Msi

[038h 0056 4] PM1A Event Block Address : 00000800

Now you see where those 410,810 etc addresses come from...

Dear mm67 and FormerlyKnownAs, after I extracted my DSDT from the binary BIOS (via hex tool as per the guide from the makers of evosx.es) it was all zeros for the CPU; you reckon I should leave it with the zeros, for all four cores?

What about the added code for Speedstepping? In _CST code there's a big value 0x0000000000000414 and 415 (Address) in CPU1. Should we also make them zeros, or are these irrelevant to the CPU declaration in the beginning?

Shaj · November 25, 2009

Hey FormerlyKnownAs, thanks for the fantastic thread.

I followed your generic scope guide and got vanilla speedstep working.

I also dumped my SSDT table (with both Linux & Everest) to try and get my c-states. Problem is that I don't know what to do with them

I've attached my DSDT and am posting my SSDT table below. Could you please help me with getting the c-states in my DSDT. Would really appreciate it.

P.S. I'm running an E8400 on an EP45-UD3R

/*
* Intel ACPI Component Architecture
* AML Disassembler version 20090730
*
* Disassembly of ./dsdt.aml, Thu Nov 26 02:51:40 2009
*
*
* Original Table Header:
*	 Signature		"SSDT"
*	 Length		   0x000003AB (939)
*	 Revision		 0x01
*	 Checksum		 0x13
*	 OEM ID		   "PmRef"
*	 OEM Table ID	 "CpuPm"
*	 OEM Revision	 0x00003000 (12288)
*	 Compiler ID	  "INTL"
*	 Compiler Version 0x20040311 (537133841)
*/
DefinitionBlock ("./dsdt.aml", "SSDT", 1, "PmRef", "CpuPm", 0x00003000)
{
External (\_PR_.CPU3, DeviceObj)
External (\_PR_.CPU2, DeviceObj)
External (\_PR_.CPU1, DeviceObj)
External (\_PR_.CPU0, DeviceObj)

Scope (\)
{
	Name (SSDT, Package (0x18)
	{
		"CPU0IST ", 
		0xDFEEDE00, 
		0x0000022A, 
		"CPU1IST ", 
		0xDFEEE2C0, 
		0x00000152, 
		"CPU0CST ", 
		0xDFEEE420, 
		0x0000018A, 
		"CPU1CST ", 
		0xDFEEE5B0, 
		0x0000018A, 
		"CPU2IST ", 
		0x00000000, 
		0xF000E816, 
		"CPU3IST ", 
		0x00000000, 
		0xF000E816, 
		"CPU2CST ", 
		0xDFEEE740, 
		0x0000018A, 
		"CPU3CST ", 
		0xDFEEE8D0, 
		0x0000018A
	})
	Name (CFGD, 0x02038332)
	Name (\PDC0, 0x80000000)
	Name (\PDC1, 0x80000000)
	Name (\PDC2, 0x80000000)
	Name (\PDC3, 0x80000000)
}

Scope (\_PR.CPU0)
{
	Name (HI0, 0x00)
	Name (HC0, 0x00)
	Name (TLD0, 0x00)
	Method (_PDC, 1, NotSerialized)
	{
		CreateDWordField (Arg0, 0x08, CAP0)
		Store (CAP0, PDC0)
		If (LEqual (TLD0, 0x00))
		{
			If (LEqual (And (PDC0, 0x0A), 0x0A))
			{
				If (And (CFGD, 0x02))
				{
					OperationRegion (IST0, SystemMemory, DerefOf (Index (SSDT, 0x01)), DerefOf (Index (SSDT, 0x02
						)))
					Load (IST0, HI0)
				}

				Store (0x01, TLD0)
			}
		}
	}
}

Scope (\_PR.CPU1)
{
	Name (HI1, 0x00)
	Name (HC1, 0x00)
	Name (TLD1, 0x00)
	Method (_PDC, 1, NotSerialized)
	{
		CreateDWordField (Arg0, 0x08, CAP1)
		Store (CAP1, PDC1)
		If (LEqual (TLD1, 0x00))
		{
			If (LEqual (And (PDC1, 0x0A), 0x0A))
			{
				If (And (CFGD, 0x02))
				{
					OperationRegion (IST1, SystemMemory, DerefOf (Index (SSDT, 0x04)), DerefOf (Index (SSDT, 0x05
						)))
					Load (IST1, HI1)
				}

				If (And (CFGD, 0x10))
				{
					OperationRegion (CST1, SystemMemory, DerefOf (Index (SSDT, 0x0A)), DerefOf (Index (SSDT, 0x0B
						)))
					Load (CST1, HC1)
				}

				Store (0x01, TLD1)
			}
		}
	}
}

Scope (\_PR.CPU2)
{
	Name (HI2, 0x00)
	Name (HC2, 0x00)
	Name (TLD2, 0x00)
	Method (_PDC, 1, NotSerialized)
	{
		CreateDWordField (Arg0, 0x08, CAP2)
		Store (CAP2, PDC2)
		If (LEqual (TLD2, 0x00))
		{
			If (LEqual (And (PDC2, 0x0A), 0x0A))
			{
				If (And (CFGD, 0x02))
				{
					OperationRegion (IST2, SystemMemory, DerefOf (Index (SSDT, 0x0D)), DerefOf (Index (SSDT, 0x0E
						)))
					Load (IST2, HI2)
				}

				If (And (CFGD, 0x10))
				{
					OperationRegion (CST2, SystemMemory, DerefOf (Index (SSDT, 0x13)), DerefOf (Index (SSDT, 0x14
						)))
					Load (CST2, HC2)
				}

				Store (0x01, TLD2)
			}
		}
	}
}

Scope (\_PR.CPU3)
{
	Name (HI3, 0x00)
	Name (HC3, 0x00)
	Name (TLD3, 0x00)
	Method (_PDC, 1, NotSerialized)
	{
		CreateDWordField (Arg0, 0x08, CAP3)
		Store (CAP3, PDC3)
		If (LEqual (TLD3, 0x00))
		{
			If (LEqual (And (PDC3, 0x0A), 0x0A))
			{
				If (And (CFGD, 0x02))
				{
					OperationRegion (IST3, SystemMemory, DerefOf (Index (SSDT, 0x10)), DerefOf (Index (SSDT, 0x11
						)))
					Load (IST3, HI3)
				}

				If (And (CFGD, 0x10))
				{
					OperationRegion (CST3, SystemMemory, DerefOf (Index (SSDT, 0x16)), DerefOf (Index (SSDT, 0x17
						)))
					Load (CST3, HC3)
				}

				Store (0x01, TLD3)
			}
		}
	}
}
}

dsdt.aml.zip

FKA · November 26, 2009

Hey FormerlyKnownAs, thanks for the fantastic thread.

I followed your generic scope guide and got vanilla speedstep working.

I also dumped my SSDT table (with both Linux & Everest) to try and get my c-states. Problem is that I don't know what to do with them

I've attached my DSDT and am posting my SSDT table below. Could you please help me with getting the c-states in my DSDT. Would really appreciate it.

P.S. I'm running an E8400 on an EP45-UD3R

Hi

The CST tables that are already in the generic code should give you c-states.

D.

Shaj · November 26, 2009

Hi
The CST tables that are already in the generic code should give you c-states.

D.

Really?? I thought c-states were specific to the processor?

Is there any way I could verify that they are working?

FKA · November 26, 2009

Really?? I thought c-states were specific to the processor?

Is there any way I could verify that they are working?

You should notice lower temps.

Also if you have phase LED on MB should indicate CPU states.

don't think there is a specific App that will show c-states.

blackosx · November 26, 2009

Also if you have phase LED on MB should indicate CPU states.

I have just realised I have Phase LED on my mobo. I will have to try it out when I get a chance.

mastershredder · November 26, 2009

Hi has anyone else also had the lagging problem occur with the speedstepping working i would love to get this working where its the same performance as when speedstepping isnt working as if i dont i will have to abandon the vanilla speedstepping and just go for plain performance BTW there was a significant reduction in temps after i altered my code to get it working my q6600 is water cooled and without the speedstepping it was idle at about 39 -40 and when i have it working with my modified DSDT it is 28 -30 idle. posted is my DSDT if anyone would kindly have a look to see if there are any errors i have not picked up on.

Thanks for everyones hard work in this thread peace out.

DSDT.dsl.zip

FKA · November 26, 2009

Hi has anyone else also had the lagging problem occur with the speedstepping working i would love to get this working where its the same performance as when speedstepping isnt working as if i dont i will have to abandon the vanilla speedstepping and just go for plain performance BTW there was a significant reduction in temps after i altered my code to get it working my q6600 is water cooled and without the speedstepping it was idle at about 39 -40 and when i have it working with my modified DSDT it is 28 -30 idle. posted is my DSDT if anyone would kindly have a look to see if there are any errors i have not picked up on.

Thanks for everyones hard work in this thread peace out.

If your talking about mouse lag and audio stutter then you need to remove IRQ's from DSDT. There is more detailed info somewhere around page 8 of this thread.

I'll have to add this part to post#1 at some point.

D.

Shaj · November 26, 2009

You should notice lower temps.
Also if you have phase LED on MB should indicate CPU states.

don't think there is a specific App that will show c-states.

I'm having almost exactly the same temps as I was when using NullCPUpowerManagement.kext & VoodooPowerMini.kext combo.

I guess that means it's working?

My MB does have the phase LED. What should I be noticing? Sorry my first time

FKA · November 26, 2009

I'm having almost exactly the same temps as I was when using NullCPUpowerManagement.kext & VoodooPowerMini.kext combo.

I guess that means it's working?

My MB does have the phase LED. What should I be noticing? Sorry my first time

Sounds like it's working - some have reported lower temps than when using nullcpupm - personally my temps are the same as when using nullcpupm.

Check your MB's manual it may tell you what they mean. Unfortunatly this is all it says in my GigaByte manual:PHASE LED

The number of lighted LEDs indicates the CPU loading. The higher the CPU loading, the more the number of lighted LEDs.

Im sure if you scratched a little deeper you can find out more .

D.

italy4ever · November 26, 2009

i'm here again there is a problem in fact after i entered the right cst table gently offered by mm67 i lost sleep someone can help me? here my dsdt.dsl dsdt.dsl.zip

mastershredder · November 26, 2009

If your talking about mouse lag and audio stutter then you need to remove IRQ's from DSDT. There is more detailed info somewhere around page 8 of this thread.

I'll have to add this part to post#1 at some point.

D.

Thanks for the reply FormerlyKnownAs i have looked through the first 10 pages of this thread to find any information regarding removing IRQs from the dsdt i was unable to find any posts regarding this other than just removing the cst method from DSDT. I have got the stepping working without reduced performance and audio issues by removing the _cst methods however temps have increased to about 33-35 from about 28-30 when the CST method was included in DSDT and also am now obviously getting the cst error at boot.

Shaj · November 26, 2009

Sounds like it's working - some have reported lower temps than when using nullcpupm - personally my temps are the same as when using nullcpupm.

Check your MB's manual it may tell you what they mean. Unfortunatly this is all it says in my GigaByte manual:PHASE LED

The number of lighted LEDs indicates the CPU loading. The higher the CPU loading, the more the number of lighted LEDs.

Im sure if you scratched a little deeper you can find out more .

D.

Thanks mate. A few more questions please.

I use a stock cooler (I really need to upgrade) and idle temps for me are about 45C

However, with full load, it jumps up to 80C!!!

1) Is that too high a jump?

2) Is that possibly a sign of p-state or c-state not working the way it should be?

3) How will these temps negatively affect my processor?

mastershredder · November 26, 2009

Another interesting point to mention is that my motherboard GA-X48-DS4 really doesnt seem to have a lot of support from gigabyte regarding bios updates they seem to be lazy updating bios and spend more time on the more expensive X48-DQ6 line of boards and about a year ago when i was just starting the vanilla revolution i realized sleep never worked properly and thought it was a configuration problem with leopard a few weeks later i realized this was regardless of operating system an would also occurein windows. What occurs is when S3 sleep is enabled in bios is the computer would go to sleep everything turned off but when you tried to wake it it would start then 5 seconds later shut off and then start again and be in an endless cycle of starting and shutting down and the only cure was to pull the power cord out and wait a few seconds for the board to loose all power before turning it back on. Needless to say this was very annoying as this is a powerful computer and not only would sleep reduce power consumption causing lower electricity bills it would prolong the life of all the components in the computer. around that time a year ago i had a series of correspondances with a technician from gigabyte who went through various settings i could try to make it work all of these failed and his suggestion was to RMA the board back. which i didnt and couldnt be bothered to do. The board itself is a great board it overclocks my q6600 like stonk and is super stable never had BSOD's in windows that werent instigated by me through undervolting etc... There is a whole bunch off people pissed off about various gigabyte motherboards with various chipsets complaining of the same problem ranging from p35 chipset all the way to core i7's x58 chipset most people have either never found a solution or have recieved a bios update that cures it. as i said at the beginning of this post gigabyte dont seem to be bothering pursuing the bios updates of this particular board as the last update was a beta bios in march or so which just updated the achi code for faster detection of drives.

however to the point.

Since doing this DSDT modifications and getting pstates working properly snow leopard is consistently waking from sleep on this board now which has baffled me. i am now going to try compiling the dsdt into the bios and flashing which should also cure the sleep issue in windows.

one question has anyone tried flashing there bios with the modified DSDT fixes and does it cause any problems on the windows side of things ?

paulicat · November 27, 2009

Incredible work!

Just wanted to say thanks to all who contributed!!

Works perfectly on my Gigabyte G31M-S2L/E6300 with 10 P-States.

Just curious, AppleLPC is not loading for me, what exactly is AppleLPC for?

blackosx · November 27, 2009

Thanks for the reply FormerlyKnownAs i have looked through the first 10 pages of this thread to find any information regarding removing IRQs from the dsdt i was unable to find any posts regarding this....

Have a look a few more pages in... on page 16.

http://www.insanelymac.com/forum/index.php...t&p=1283137

FKA · November 27, 2009

one question has anyone tried flashing there bios with the modified DSDT fixes and does it cause any problems on the windows side of things ?

Not recomended - and not much point when the custom DSDT.aml can be loaded by the bootloader!

Incredible work!
Just wanted to say thanks to all who contributed!!

Works perfectly on my Gigabyte G31M-S2L/E6300 with 10 P-States.

Just curious, AppleLPC is not loading for me, what exactly is AppleLPC for?

AppleLPC.kext will give you the 'Automatic restart after power failure' option in power savings. This option needs to be checked for sleep!

It's also needed for vanilla speedstep!

D.

paulicat · November 27, 2009

Just FYI, vanilla speedstep and sleep are working flawlessly (for me) without AppleLPC loaded.

As for the Automatic restart after power failure, I don't really need that either.

Thanks again for all the hard work.

DSDT - Vanilla Speedstep - Generic Scope (_PR)

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