DSDT - Vanilla Speedstep - Generic Scope (_PR)

keeza · October 13, 2009

First my heartfelt gratitude goes out to all the forum members here, whose help has been invaluable, especially Master Chief & FormerlyKnownAs.
I have attached here 3 variants of DSDT mods. The first one was done following FormerlyKnownAs first post here. I had no CST evaluation errors to start with & my ACPI dumps yielded 5 SSDTs of which 4 were CPUcXst and the fifth one was CpuPm. I also had the FACP table with _CST support : 00 & C2 Latency : 005A & C3 Latency : 0384.

Frankly the high temps were bothering me 60 deg. C on load. I could see stepping in CPU-i. So that was some relief. After a second read through I understood that I needed to enter the latencies from the FACP into the SPSS part. Which is what I did in the Second mod. which brought temps down to 40 on idle and about 50 on load.

But I had seen members on this thread getting temps in their 30s. I preferred not to replace ROISOFT's MacPro 3,1 code into my DSDT but I tried just to see and it works with idle temps down to about 34.

Am I doing anything wrong by replacing my obtained SSDT tables with these?

I see FormerlyKnownAs DSDT attached in the first post have "Method (_PPC, 0, NotSerialized)". Can it be ignored because it returns Zero?

Also it has Method (_PCT, 0, NotSerialized) which I don't. Should it be there?

And among other things I will be very grateful if someone could point errors in the Speed stepping and related parts, and how to set them right.

My sincerest thanks to all who have shared their knowledge here.

Check out my previous post #335. I used my own dumps with Macpro3,1 additions where I have mentioned. I wanted to keep my dsdt additions relating to speedstep and CST as close to my original dumps as poss.

My idles are around 35 degrees and seems to run fine.

Also, do you have AppleLPC loading - run kextstat in terminal to find out. There is a previous post from member Beerkexd relating to this. There doesnt seem to be a device id fix in your dsdt for your LPC device (you may have addressed this using another method). My understanding is that AppleLPC kext needs to load in order for C-States to work.

...and by the way line 3307 and 3316 of your dsdt need to have the same value for the cmos fix for SL

William Parker · October 13, 2009

@keeza

Thanks friend. I will look at your dsdt and see what I have mucked up in mine, and try set it right including cmos fix. But I too am idling around 34 no problems. As for the LPC I have edited it's plist because I was unaware of the dsdt patch for it. I will do it soon.

Another thing - 2 days earlier on moofspeak irc I met mojodojo and he said that his CPU-i app works in 64 bit kernel & also provided a link on applelife russian site for it. I somehow lost the link. It was a version much greater than 1.0.3. Any clues? Coolbook does not work, shows all freq as 0. I simply use temperature monitor to guess what's happening.

Thanks a ton

(Edit)

Your SPSS Package should have the latency values from your FACP table which are presently A0 & 0A. This was input by fromerlyKA because he did not have meaningful latency values. Probably you do (almost my MB). Your comments?

FKA · October 13, 2009

This way I can get P-states and C-states working even if EIST and C-states are disabled in bios.

This P-state table is for Q9550.

    Scope (_PR)
   {
       Processor (CPU0, 0x00, 0x00000410, 0x06) {}
       Processor (CPU1, 0x01, 0x00000410, 0x06) {}
       Processor (CPU2, 0x02, 0x00000410, 0x06) {}
       Processor (CPU3, 0x03, 0x00000410, 0x06) {}
       Name (CFGD, 0x040383F2)
       Name (PDC0, 0x80000000)
   }

   Scope (_PR.CPU0)
   {
       Method (_CST, 0, NotSerialized)
       {
           If (LAnd (And (CFGD, 0x01000000), LNot (And (PDC0, 0x10
               ))))
           {
               Return (Package (0x02)
               {
                   One, 
                   Package (0x04)
                   {
                       ResourceTemplate ()
                       {
                           Register (FFixedHW, 
                               0x00,               // Bit Width
                               0x00,               // Bit Offset
                               0x0000000000000000, // Address
                               ,)
                       },
                       One, 
                       0x9D, 
                       0x03E8
                   }
               })
           }
           If (And (PDC0, 0x0300))
           {
               If (And (CFGD, 0x20))
               {
                   Return (Package (0x03)
                   {
                       0x02, 
                       Package (0x04)
                       {
                           ResourceTemplate ()
                           {
                               Register (FFixedHW, 
                                   0x01,               // Bit Width
                                   0x02,               // Bit Offset
                                   0x0000000000000000, // Address
                                   ,)
                           }, 

                           One, 
                           One, 
                           0x03E8
                       }, 

                       Package (0x04)
                       {
                           ResourceTemplate ()
                           {
                               Register (FFixedHW, 
                                   0x01,               // Bit Width
                                   0x02,               // Bit Offset
                                   0x0000000000000010, // Address
                                   ,)
                           }, 

                           0x02, 
                           One, 
                           0x01F4
                       }
                   })
               }
           }
           If (And (CFGD, 0x20))
           {
               Return (Package (0x03)
               {
                   0x02, 
                   Package (0x04)
                   {
                       ResourceTemplate ()
                       {
                           Register (FFixedHW, 
                               0x01,               // Bit Width
                               0x02,               // Bit Offset
                               0x0000000000000000, // Address
                               ,)
                       }, 

                       One, 
                       One, 
                       0x03E8
                   }, 

                   Package (0x04)
                   {
                       ResourceTemplate ()
                       {
                           Register (SystemIO, 
                               0x08,               // Bit Width
                               0x00,               // Bit Offset
                               0x0000000000000414, // Address
                               ,)
                       }, 

                       0x02, 
                       One, 
                       0x01F4
                   }
               })
           }

           Return (Package (0x02)
           {
               One, 
               Package (0x04)
               {
                   ResourceTemplate ()
                   {
                       Register (FFixedHW, 
                           0x01,               // Bit Width
                           0x02,               // Bit Offset
                           0x0000000000000000, // Address
                           ,)
                   }, 

                   One, 
                   One, 
                   0x03E8
               }
           })
       }
       Method (_PPC, 0, NotSerialized)
       {
           Return (Zero)
       }

       Method (_PCT, 0, NotSerialized)
       {
         Return (Package (0x02)
         {
           ResourceTemplate ()
           {
               Register (FFixedHW, 
                   0x10,
                   0x00,
                   0x0000000000000199,
                   ,)
           }, 

           ResourceTemplate ()
           {
               Register (FFixedHW, 
                   0x10,
                   0x00,
                   0x0000000000000198,
                   ,)
           }
         })
       }
       Method (_PSS, 0, NotSerialized)
       {
         Return (Package (0x06)
          {
           Package (0x06)
           {
               0xB0F, 
               Zero, 
               0xA, 
               0xA, 
               0x4820, 
               0x4820
           }, 

           Package (0x06)
           {
               0xA68, 
               Zero, 
               0xA, 
               0xA, 
               0x81E, 
               0x81E
           }, 

           Package (0x06)
           {
               0x9C2, 
               Zero, 
               0xA, 
               0xA, 
               0x471C, 
               0x471C
           }, 

           Package (0x06)
           {
               0x91B, 
               Zero, 
               0xA, 
               0xA, 
               0x71A, 
               0x71A
           }, 

           Package (0x06)
           {
               0x875, 
               Zero, 
               0xA, 
               0xA, 
               0x4618, 
               0x4618
           }, 

           Package (0x06)
           {
               0x7CE, 
               Zero, 
               0xA, 
               0xA, 
               0x616, 
               0x616
           }
       })
     }
   }

   Scope (_PR.CPU1)
   {
       Method (_CST, 0, NotSerialized)
       {
           Return (^^CPU0._CST ())
       }

       Method (_PPC, 0, NotSerialized)
       {
           Return (Zero)
       }

       Method (_PCT, 0, NotSerialized)
       {
           Return (^^CPU0._PCT ())
       }

       Method (_PSS, 0, NotSerialized)
       {
           Return (^^CPU0._PSS ())
       }
   }

   Scope (_PR.CPU2)
   {
       Method (_CST, 0, NotSerialized)
       {
           Return (^^CPU0._CST ())
       }

       Method (_PPC, 0, NotSerialized)
       {
           Return (Zero)
       }

       Method (_PCT, 0, NotSerialized)
       {
           Return (^^CPU0._PCT ())
       }

       Method (_PSS, 0, NotSerialized)
       {
           Return (^^CPU0._PSS ())
       }
   }

   Scope (_PR.CPU3)
   {
       Method (_CST, 0, NotSerialized)
       {
           Return (^^CPU0._CST ())
       }

       Method (_PPC, 0, NotSerialized)
       {
           Return (Zero)
       }

       Method (_PCT, 0, NotSerialized)
       {
           Return (^^CPU0._PCT ())
       }

       Method (_PSS, 0, NotSerialized)
       {
           Return (^^CPU0._PSS ())
       }
   }

With EIST and C-states disabled Windows makes cpu run hot (idling around 50) but in OSX cpu is idling around 35 degrees.

I get same temperatures when I am using CST tables from my own bios. If I use MP 3,1 CST tables temps go down to 35 and IOrRegistryExplorer has CSTInfo key which is missing when using my own tables.

Hi mm67

I've adapted your code with MP3,1 _cst for my Q9450 with 3 steps. I works just fine and is much tidier than the code I was using. Still no c-states for me although I still have cst info in ioreg.

{
Processor (CPU0, 0x00, 0x00000410, 0x06) {}
Processor (CPU1, 0x01, 0x00000410, 0x06) {}
Processor (CPU2, 0x02, 0x00000410, 0x06) {}
Processor (CPU3, 0x03, 0x00000410, 0x06) {}
Name (CFGD, 0x040383F2)
Name (PDC0, 0x80000000)
}

Scope (_PR.CPU0)
{
Method (_CST, 0, NotSerialized)
{
If (LAnd (And (CFGD, 0x01000000), LNot (And (PDC0, 0x10
))))
{
Return (Package (0x02)
{
One,
Package (0x04)
{
ResourceTemplate ()
{
Register (FFixedHW,
0x00, // Bit Width
0x00, // Bit Offset
0x0000000000000000, // Address
,)
},
One,
0x9D,
0x03E8
}
})
}
If (And (PDC0, 0x0300))
{
If (And (CFGD, 0x20))
{
Return (Package (0x03)
{
0x02,
Package (0x04)
{
ResourceTemplate ()
{
Register (FFixedHW,
0x01, // Bit Width
0x02, // Bit Offset
0x0000000000000000, // Address
,)
},

One,
One,
0x03E8
},

Package (0x04)
{
ResourceTemplate ()
{
Register (FFixedHW,
0x01, // Bit Width
0x02, // Bit Offset
0x0000000000000010, // Address
,)
},

0x02,
One,
0x01F4
}
})
}
}
If (And (CFGD, 0x20))
{
Return (Package (0x03)
{
0x02,
Package (0x04)
{
ResourceTemplate ()
{
Register (FFixedHW,
0x01, // Bit Width
0x02, // Bit Offset
0x0000000000000000, // Address
,)
},

One,
One,
0x03E8
},

Package (0x04)
{
ResourceTemplate ()
{
Register (SystemIO,
0x08, // Bit Width
0x00, // Bit Offset
0x0000000000000414, // Address
,)
},

0x02,
One,
0x01F4
}
})
}

Return (Package (0x02)
{
One,
Package (0x04)
{
ResourceTemplate ()
{
Register (FFixedHW,
0x01, // Bit Width
0x02, // Bit Offset
0x0000000000000000, // Address
,)
},

One,
One,
0x03E8
}
})
}
Method (_PPC, 0, NotSerialized)
{
Return (Zero)
}

Method (_PCT, 0, NotSerialized)
{
Return (Package (0x02)
{
ResourceTemplate ()
{
Register (FFixedHW,
0x10,
0x00,
0x0000000000000199,
,)
},

ResourceTemplate ()
{
Register (FFixedHW,
0x10,
0x00,
0x0000000000000198,
,)
}
})
}
Method (_PSS, 0, NotSerialized)
{
Return (Package (0x03)
{
           Package (0x06)
           {
               0x0C20, 
               0x000124F8, 
               0xA0, 
               0x0A, 
               0x0820, 
               0x0820
           }, 

           Package (0x06)
           {
               0x0A9C, 
               0xFDE8, 
               0xA0, 
               0x0A, 
               0x071C, 
               0x071C
           }, 

           Package (0x06)
           {
               0x0918, 
               0xEA60, 
               0xA0, 
               0x0A, 
               0x061A, 
               0x061A
           }
})
}
}

Scope (_PR.CPU1)
{
Method (_CST, 0, NotSerialized)
{
Return (^^CPU0._CST ())
}

Method (_PPC, 0, NotSerialized)
{
Return (Zero)
}

Method (_PCT, 0, NotSerialized)
{
Return (^^CPU0._PCT ())
}

Method (_PSS, 0, NotSerialized)
{
Return (^^CPU0._PSS ())
}
}

Scope (_PR.CPU2)
{
Method (_CST, 0, NotSerialized)
{
Return (^^CPU0._CST ())
}

Method (_PPC, 0, NotSerialized)
{
Return (Zero)
}

Method (_PCT, 0, NotSerialized)
{
Return (^^CPU0._PCT ())
}

Method (_PSS, 0, NotSerialized)
{
Return (^^CPU0._PSS ())
}
}

Scope (_PR.CPU3)
{
Method (_CST, 0, NotSerialized)
{
Return (^^CPU0._CST ())
}

Method (_PPC, 0, NotSerialized)
{
Return (Zero)
}

Method (_PCT, 0, NotSerialized)
{
Return (^^CPU0._PCT ())
}

Method (_PSS, 0, NotSerialized)
{
Return (^^CPU0._PSS ())
}
}

D

mm67 · October 13, 2009

Hi mm67

I've adapted your code with MP3,1 _cst for my Q9450 with 3 steps. I works just fine and is much tidier than the code I was using. Still no c-states for me although I still have cst info in ioreg.

How does one know if C-states are working or not. Is there some tool for OSX that shows it ?

I verified that this gives working C-states by loading this to Ubuntu and running cat /proc/acpi/processor/CPU0/power but I have no idea how to check this in OSX.

FKA · October 13, 2009

How does one know if C-states are working or not. Is there some tool for OSX that shows it ?
I verified that this gives working C-states by loading this to Ubuntu and running cat /proc/acpi/processor/CPU0/power but I have no idea how to check this in OSX.

Firstly - I have no cst tables and FACP states cst support - 0 so don't expect to get c-states working even uisng ab__73's method to find the hard coded memory addresses for cst.

using mark-i I'd expect if I entered a C1 or 2 state, to see any of the following - a voltage drop, cpu fan speed drop or CPU temp drop - beyond the level of my lowest P state multi.

It's not too scientific and I'd like a better method if anybody has one!

D.

mm67 · October 13, 2009

Firstly - I have no cst tables and FACP states cst support - 0 so don't expect to get c-states working even uisng ab__73's method to find the hard coded memory addresses for cst.

using mark-i I'd expect if I entered a C1 or 2 state, to see any of the following - a voltage drop, cpu fan speed drop or CPU temp drop - beyond the level of my lowest P state multi.

It's not too scientific and I'd like a better method if anybody has one!

D.

Only difference that I can see is that temps drop from 40 to 35 degrees when cst is working.

yeehaa · October 13, 2009

Another thing - 2 days earlier on moofspeak irc I met mojodojo and he said that his CPU-i app works in 64 bit kernel & also provided a link on applelife russian site for it. I somehow lost the link. It was a version much greater than 1.0.3. Any clues? Coolbook does not work, shows all freq as 0. I simply use temperature monitor to guess what's happening.
Thanks a ton

cpu-i is now called voodoomonitor and is on version 1.0.7 now. head over to applelife n do a search there..

mm67 · October 13, 2009

Firstly - I have no cst tables and FACP states cst support - 0 so don't expect to get c-states working even uisng ab__73's method to find the hard coded memory addresses for cst.

using mark-i I'd expect if I entered a C1 or 2 state, to see any of the following - a voltage drop, cpu fan speed drop or CPU temp drop - beyond the level of my lowest P state multi.

It's not too scientific and I'd like a better method if anybody has one!

D.

You mean your FACP looks like this ?

[000h 0000  4]                    Signature : "FACP"    /* Fixed ACPI Description Table */
[004h 0004  4]                 Table Length : 00000074
[008h 0008  1]                     Revision : 01
[009h 0009  1]                     Checksum : 1B
[00Ah 0010  6]                       Oem ID : "GBT   "
[010h 0016  8]                 Oem Table ID : "GBTUACPI"
[018h 0024  4]                 Oem Revision : 42302E31
[01Ch 0028  4]              Asl Compiler ID : "GBTU"
[020h 0032  4]        Asl Compiler Revision : 01010101

[024h 0036  4]                 FACS Address : DFEE0000
[028h 0040  4]                 DSDT Address : DFEE2180
[02Ch 0044  1]                        Model : 01
[02Dh 0045  1]                   PM Profile : 01 (Desktop)
[02Eh 0046  2]                SCI Interrupt : 0009
[030h 0048  4]             SMI Command Port : 000000B2
[034h 0052  1]            ACPI Enable Value : A1
[035h 0053  1]           ACPI Disable Value : A0
[036h 0054  1]               S4BIOS Command : 00
[037h 0055  1]              P-State Control : 34
[038h 0056  4]     PM1A Event Block Address : 00000400
[03Ch 0060  4]     PM1B Event Block Address : 00000000
[040h 0064  4]   PM1A Control Block Address : 00000404
[044h 0068  4]   PM1B Control Block Address : 00000000
[048h 0072  4]    PM2 Control Block Address : 00000450
[04Ch 0076  4]       PM Timer Block Address : 00000408
[050h 0080  4]           GPE0 Block Address : 00000420
[054h 0084  4]           GPE1 Block Address : 00000000
[058h 0088  1]       PM1 Event Block Length : 04
[059h 0089  1]     PM1 Control Block Length : 02
[05Ah 0090  1]     PM2 Control Block Length : 01
[05Bh 0091  1]        PM Timer Block Length : 04
[05Ch 0092  1]            GPE0 Block Length : 10
[05Dh 0093  1]            GPE1 Block Length : 00
[05Eh 0094  1]             GPE1 Base Offset : 00
[05Fh 0095  1]                 _CST Support : 00
[060h 0096  2]                   C2 Latency : 005A
[062h 0098  2]                   C3 Latency : 0384
[064h 0100  2]               CPU Cache Size : 0000
[066h 0102  2]           Cache Flush Stride : 0000
[068h 0104  1]            Duty Cycle Offset : 01
[069h 0105  1]             Duty Cycle Width : 03
[06Ah 0106  1]          RTC Day Alarm Index : 0D
[06Bh 0107  1]        RTC Month Alarm Index : 00
[06Ch 0108  1]            RTC Century Index : 00
[06Dh 0109  2]   Boot Flags (decoded below) : 0010
             Legacy Devices Supported (V2) : 0
          8042 Present on ports 60/64 (V2) : 0
                      VGA Not Present (V4) : 0
                    MSI Not Supported (V4) : 0
              PCIe ASPM Not Supported (V4) : 1
[06Fh 0111  1]                     Reserved : 00
[070h 0112  4]        Flags (decoded below) : 000004A5
    WBINVD instruction is operational (V1) : 1
            WBINVD flushes all caches (V1) : 0
                  All CPUs support C1 (V1) : 1
                C2 works on MP system (V1) : 0
          Control Method Power Button (V1) : 0
          Control Method Sleep Button (V1) : 1
      RTC wake not in fixed reg space (V1) : 0
          RTC can wake system from S4 (V1) : 1
                      32-bit PM Timer (V1) : 0
                    Docking Supported (V1) : 0
             Reset Register Supported (V2) : 1
                          Sealed Case (V3) : 0
                  Headless - No Video (V3) : 0
      Use native instr after SLP_TYPx (V3) : 0
            PCIEXP_WAK Bits Supported (V4) : 0
                   Use Platform Timer (V4) : 0
             RTC_STS valid on S4 wake (V4) : 0
              Remote Power-on capable (V4) : 0
               Use APIC Cluster Model (V4) : 0
   Use APIC Physical Destination Mode (V4) : 0

I get this when I disable C-states from bios, but cst works anyway using dsdt.aml, both in OSX and Linux.

/edit

Checked again, FACP table stays the same when disabling cst from bios but RSDT looses SSDT table addresses.

FKA · October 13, 2009

You mean your FACP looks like this ?

[000h 0000  4]                    Signature : "FACP"    /* Fixed ACPI Description Table */
[004h 0004  4]                 Table Length : 00000074
[008h 0008  1]                     Revision : 01
[009h 0009  1]                     Checksum : 1B
[00Ah 0010  6]                       Oem ID : "GBT   "
[010h 0016  8]                 Oem Table ID : "GBTUACPI"
[018h 0024  4]                 Oem Revision : 42302E31
[01Ch 0028  4]              Asl Compiler ID : "GBTU"
[020h 0032  4]        Asl Compiler Revision : 01010101

[024h 0036  4]                 FACS Address : DFEE0000
[028h 0040  4]                 DSDT Address : DFEE2180
[02Ch 0044  1]                        Model : 01
[02Dh 0045  1]                   PM Profile : 01 (Desktop)
[02Eh 0046  2]                SCI Interrupt : 0009
[030h 0048  4]             SMI Command Port : 000000B2
[034h 0052  1]            ACPI Enable Value : A1
[035h 0053  1]           ACPI Disable Value : A0
[036h 0054  1]               S4BIOS Command : 00
[037h 0055  1]              P-State Control : 34
[038h 0056  4]     PM1A Event Block Address : 00000400
[03Ch 0060  4]     PM1B Event Block Address : 00000000
[040h 0064  4]   PM1A Control Block Address : 00000404
[044h 0068  4]   PM1B Control Block Address : 00000000
[048h 0072  4]    PM2 Control Block Address : 00000450
[04Ch 0076  4]       PM Timer Block Address : 00000408
[050h 0080  4]           GPE0 Block Address : 00000420
[054h 0084  4]           GPE1 Block Address : 00000000
[058h 0088  1]       PM1 Event Block Length : 04
[059h 0089  1]     PM1 Control Block Length : 02
[05Ah 0090  1]     PM2 Control Block Length : 01
[05Bh 0091  1]        PM Timer Block Length : 04
[05Ch 0092  1]            GPE0 Block Length : 10
[05Dh 0093  1]            GPE1 Block Length : 00
[05Eh 0094  1]             GPE1 Base Offset : 00
[05Fh 0095  1]                 _CST Support : 00
[060h 0096  2]                   C2 Latency : 005A
[062h 0098  2]                   C3 Latency : 0384
[064h 0100  2]               CPU Cache Size : 0000
[066h 0102  2]           Cache Flush Stride : 0000
[068h 0104  1]            Duty Cycle Offset : 01
[069h 0105  1]             Duty Cycle Width : 03
[06Ah 0106  1]          RTC Day Alarm Index : 0D
[06Bh 0107  1]        RTC Month Alarm Index : 00
[06Ch 0108  1]            RTC Century Index : 00
[06Dh 0109  2]   Boot Flags (decoded below) : 0010
             Legacy Devices Supported (V2) : 0
          8042 Present on ports 60/64 (V2) : 0
                      VGA Not Present (V4) : 0
                    MSI Not Supported (V4) : 0
              PCIe ASPM Not Supported (V4) : 1
[06Fh 0111  1]                     Reserved : 00
[070h 0112  4]        Flags (decoded below) : 000004A5
    WBINVD instruction is operational (V1) : 1
            WBINVD flushes all caches (V1) : 0
                  All CPUs support C1 (V1) : 1
                C2 works on MP system (V1) : 0
          Control Method Power Button (V1) : 0
          Control Method Sleep Button (V1) : 1
      RTC wake not in fixed reg space (V1) : 0
          RTC can wake system from S4 (V1) : 1
                      32-bit PM Timer (V1) : 0
                    Docking Supported (V1) : 0
             Reset Register Supported (V2) : 1
                          Sealed Case (V3) : 0
                  Headless - No Video (V3) : 0
      Use native instr after SLP_TYPx (V3) : 0
            PCIEXP_WAK Bits Supported (V4) : 0
                   Use Platform Timer (V4) : 0
             RTC_STS valid on S4 wake (V4) : 0
              Remote Power-on capable (V4) : 0
               Use APIC Cluster Model (V4) : 0
   Use APIC Physical Destination Mode (V4) : 0

I get this when I disable C-states from bios, but cst works anyway using dsdt.aml, both in OSX and Linux.

/edit

Checked again, FACP table stays the same when disabling cst from bios but RSDT looses SSDT table addresses.

Something along those lines - but I have no cst tables in SSDT (hence borrowing from MP3,1) and the only option in BIOS is for C1E ..

Only difference that I can see is that temps drop from 40 to 35 degrees when cst is working.

I've never got below 40 degrees - so a deffinate sign you've entered a c-state if your getting 35.C

EDIT## do you notice any cst entry present/ not present under ACPI_SMC in ioreg when you change cst tables from your own to MP3,1 in DSDT and switch between 40.C and 35.C idle??

D

mm67 · October 13, 2009

Something along those lines - but I have no cst tables in SSDT (hence borrowing from MP3,1) and the only option in BIOS is for C1E ..

I've never got below 40 degrees - so a deffinate sign you've entered a c-state if your getting 35.C

EDIT## do you notice any cst entry present/ not present under ACPI_SMC in ioreg when you change cst tables from your own to MP3,1 in DSDT and switch between 40.C and 35.C idle??

D

I get the CSTInfo key only with MP3.1 cst, if I try to use my own tables then I have no cst entries.

FKA · October 13, 2009

I get the CSTInfo key only with MP3.1 cst, if I try to use my own tables then I have no cst entries.

A Guess - if you found the hard coded memory addresses using your own cst I presume they'd work for you also!

mark-i custom labels - very nice toy SL only

mark_i_custom.w.kext.zip

mark_i.force_nehalem.zip - Still testing

curt' - mark @the project

http://www.insanelymac.com/forum/index.php...p;#entry1287585

Master Chief · October 13, 2009

Give me some time and I'll add part two, showing C-States working, lowering the CPU temperature by almost 25 degrees centigrade!

I get the CSTInfo key only with MP3.1 cst, if I try to use my own tables then I have no cst entries.

ACPI_SMC_PlatformPlugin.kext adds this property after evaluating your _CST object i.e. it has to be properly formatted and valid before this shows up.

keeza · October 13, 2009

(Edit)
Your SPSS Package should have the latency values from your FACP table which are presently A0 & 0A. This was input by fromerlyKA because he did not have meaningful latency values. Probably you do (almost my MB). Your comments?

Interesting. Would you happen to know the post number from FKA that you refer to?

Speedstepping and CStates seem to be working perfectly for me at the moment.

Beerkex'd · October 14, 2009

Here's what I got with LegacyAGPM.kext, LegacyACPI_SMC_PP.kext + adding the SBUS device to my DSDT. And of course the C/P-states. I'm still using iMac9,1 as model identifier - And so Snow Leopard thinks my E8500 is a Penryn CPU, which, being the mobile version of Wolfdale, is reasonably close.

/EDIT - It was discussed earlier in this thread but for those who missed it, you need to insert the device ID of your video card in LegacyAGPM.kext for it to work.

The motherboard SBUS device must match the device ID in LegacyACPI_SMC_PP.kext - if it doesn't, you have to patch it in the DSDT - see Master Chief's P5K Pro thread.

I use iMac9,1 as model identifier, so I've replaced P5K Pro with iMac9,1 in the two kexts.

Thanks Master Chief, for all your awesome work and research.

I still have some testing to do to see if it really works. So far P-States and S3 sleep/wake from USB/PWRB is still working.

I have a rarely occurring issue where the 9800 GTX+ fan will spin up to full speed, followed by instant reboot.

I want to see if that still happens but I haven't figured out how to trigger it (EDIT - yay, it seems to be gone for good)

btw if you keep the SPKR device in the DSDT, Parallels will use it when it boots a virtual machine! I guess they must have left the code in from the PC version.

I didn't have to patch the device ID of the SBUS device.

Here's my DSDT if you want to see how it works on ASUS P5Q-E.

(/EDIT - removed - go here: http://www.insanelymac.com/forum/index.php...t&p=1299409 )

/EDIT 24/10 (fixed some stupid mistakes) - Here are my modified LegacyAGPM.kext and LegacyACPI_SMC_PP.kexts, I've changed model identifier to iMac9,1 in both and in LegacyAGPM.kext I've replaced device ID of the Geforce 9400 (used in iMac9,1) with 0x612 of my 9800GTX+.

Both load from /EFI/Extra/Extensions.mkext.

iMac9_1_GF9800GTX_LegacyKexts.zip

William Parker · October 14, 2009

Interesting. Would you happen to know the post number from FKA that you refer to?

Speedstepping and CStates seem to be working perfectly for me at the moment.

Sorry, My bad. The post #83 is by Master Chief

Thanks

barnum · October 14, 2009

Hi Beerkex'd,

I've look your P-states and I see only 4 on you DSDT :

Package (0x06) { 0x0C5E, 0x00015BA8, 0x0A, 0x0A, 0x4922, 0x4922},

Package (0x06) { 0x0A6E, 0x00012CC8, 0x0A, 0x0A, 0x081E, 0x081E},

Package (0x06) { 0x0920, 0x000101D0, 0x0A, 0x0A, 0x071A, 0x071A},

Package (0x06) { 0x07D3, 0xDEA8, 0x0A, 0x0A, 0x0616, 0x0616}

In you screenshot you have 8 ?

Can you explain to me how you have this 8 p-states

regards,

William Parker · October 14, 2009

Hi,

An essential tool which was quite hard to track down - Voodoo Monitor / VoodooMonitor version 1.0.7. As yeeha pointed out it is the latest iteration of CPU-i by mojodojo. It works nicely in the 64 bit kernel and is quite responsive. Thought I'd share..

VoodooMonitor.zip

Master Chief · October 14, 2009

Here's what I got with LegacyAGPMEnabler and the Legacy SMBUS kext + adding the SBUS device to my DSDT. And of course the P-states. I'm still using iMac9,1 as model identifier - And so Snow Leopard thinks my E8500 is a Penryn CPU.

Thanks Master Chief, for all your awesome work and research.

Thanks man!

I have a rarely occurring issue where the 9800 GTX+ fan will spin up to full speed, followed by instant reboot. I want to see if that still happens but I haven't figured out how to trigger it.

Interesting. Let me know when you found out what it was

btw if you keep the SPKR device in the DSDT, Parallels will use it when it boots a virtual machine! I guess they must have left the code in from the PC version.

I do have Parallels 4.something but I didn't knew this. Let me check later today.

I didn't have to patch the device ID of the SBUS device. Here's my DSDT if you want to see how it works on ASUS P5Q-E.

Looks awesome.

I didn't rip out all the SIOR stuff, I can't figure out which parts are safe to remove.

Start by modifying your _PTS and _WAK objects first. Look at my code, then rip out the underlaying code.

I see that you was smart enough not to RIP _PDC and _OSC because I tell you these are mighty important. I know that some people here (and there) make you believe that these are not important. Well... let's see what they mean to your system:

_PDC (Processor Driver Capabilities)

_OSC (Operating System Capabilities)

Now read that, and think for a moment. Do I want to fry another CPU? No thanks. Next.

There's also stuff in your dsdt.dsl that should NOT be there. The following targets are most likely inserted by you after reading stuff here, but please, please remove these again:

_PPC, _PCT, _PSD, _PSS, SPSS, NPSS,

The reasons for this is that your DSDT already loads these object with the following statements:

Load (GV00, HI[0/1])

I mean all these code duplications make my head spin. This is about global name space pollution (Google it) I guess that you are not a developer, which is fine of course, but we developers are hammered with bugs due to this. Have a look at DSDT V2.7 and note that DSDT V2.8 will be released later today with stuff you want to fix this. In short: Do not pollute the global/_PR name space with unrelated objects. It screams for BUGS.

Note: You only need _PSS when you want/need to modify or expand the P-State values!

And there's one big fat plus in it for you... Yep. because you won't need to search for related code. All nice and tidy in one block. Hand in hand. As it supposed to be

p.s. They have got to fix these F'ing database errors once and for all.... I am getting so sick of thenm (I was not even able to fix by type due to these DBF error! Grrrr!

Master Chief · October 14, 2009

Give me some time and I'll add part two, showing C-States working, lowering the CPU temperature by almost 25 degrees centigrade!

And this my friends is the stunning result....

With _CST (no errors in kernel.log) but without _PDC object:

With _PDC and _CST objects:

Well... what else can I say....

Beerkex'd · October 14, 2009

I've look your P-states and I see only 4 on you DSDT :
In you screenshot you have 8 ?

Can you explain to me how you have this 8 p-states

Um...by luck?

(I seriously don't know, Ask Master Chief).

I guess that you are not a developer

Hell no, I'm a musician. Hackintoshing is a hobby. I don't even use my "iMac" for anything serious, I mostly just tweak and marvel at it

I am old enough to have typed in game listings from magazines on my ZX Spectrum in the early 80's. I remember having at least as much fun debugging and changing things in the code as i did actually playing the games. But I never got into assembler, and then later came the music.

I will wait for your 2.8 and then compare DSDTs again, while ripping out NPSS and friends in the meantime.

/edit - removed them - all 8 p-states are still working, idle temp hovers at the same comfy 37-39 degrees.

The reason why it's placed all neatly at the end of my DSDT like that is that I used FormerlyKnownAs' original DSDT from the first post as "inspiration". All the code there is from my own ACPI dumps (posted earlier in the thread as you know) though. But thanks for the compliment, I'm a little embarassed because (surprise ) I don't really know what I'm doing, so I try to mix logic with instinct and follow the code the best I can.

Master Chief · October 14, 2009

Um...by luck?

(I seriously don't know, Ask Master Chief).

Your CPU supports eight P-States (as displayed) but you might have only four listed under Status in CPU-i due to your _PSS object. You can use this information and make them all work by expanding your _PSS object.

Hell no, I'm a musician. Hackintoshing is a hobby.
I am old enough to have typed in game listings from magazines on my ZX Spectrum back in 1982. I remember having at least as much fun debugging and changing things in the code as actually playing the games. But I never got into assembler, and then later came the music.

Hm. Sounds like we're pretty close age wise. I myself joined the Commodore community in 1986.

I will wait for your 2.8 and then compare DSDTs again, while ripping out NPSS and friends in the meantime.

It's already available from post #3 there. Still have to announce it though.

The reason why it's placed all neatly at the end of my DSDT like that is that I used FormerlyKnownAs' original DSDT from the first post as "inspiration". All the code there is from my own ACPI dumps (posted earlier in the thread as you know) though. But thanks for the compliment, I'm a little embarassed because (surprise ) I don't really know what I'm doing, I see the general outline of things and try to follow the logic.

And I'm not much of a musician, so there is really no need to be embarrassed. You are doing a great job. And we're all here for fun... and ultimately to get the job done.

Cheers my friend!

verdant · October 14, 2009

And this my friends is the stunning result....

With _CST (no errors in kernel.log) but without _PDC object:

With _PDC and _CST objects:

Well... what else can I say....

Hi Master Chief, I hope this is not off-topic but on my 650i nForce chipset MOBO with the current BIOS settings (I will get to my specific question at the end)......

CPU Internal Thermal Control [AUTO]

Limit CPUID MaxVal [DISABLED]

Enhanced C1 (C1E) [DISABLED]

Execute Disable Bit [ENABLED]

Virtualization Technology [DISABLED]

Enhanced Intel Speedstep Technology [DISABLED]

VoodooMonitor v1.0.7 shows, with changing temps.....

VoodooMonitor1.tiff VoodooMonitor2.tiff VoodooMonitor3.tiff

compared with FanSpeed temps in Vista of

Core 0 48°C

Core 1 46°C

Core 2 42°C

Core 3 46°C

Now my Ubuntu Linux ACPI Table dump using

sudo mkdir ACPI && dmesg | perl -we '$n=0; while (<>) { if  (($t,$a,$l,$o) = (/^[^a-zA-Z]*ACPI: ([-._A-Z0-9]{4,4})  +([0-9A-F]{8,8}), ([0-9A-F]{4,4})+(?:\s*\(([^)]+))?/)) { $o &&  $o=~s/[^-._a-zA-Z0-9]+/-/g; ($cmd="acpidump -a $a -l $l >  \"ACPI/${t}".($o?"_$o":"").".aml\""); print "Running command:  \"$cmd\"\n"; system($cmd); ++$n; } } die("No match") unless $n;'  && zip -r ACPI-Tables.zip ACPI

which I believe should dump SSDT tables (including C-states), produced

ACPITables.tiff

with my FACP table showing:

/*
* Intel ACPI Component Architecture
* AML Disassembler version 20090730
*
* Disassembly of ./dsdt.aml, Wed Oct 14 20:54:33 2009
*
* ACPI Data Table [FACP]
*
* Format: [HexOffset DecimalOffset ByteLength]  FieldName : FieldValue
*/

[000h 0000  4]                    Signature : "FACP"    /* Fixed ACPI Description Table */
[004h 0004  4]                 Table Length : 000000F4
[008h 0008  1]                     Revision : 03
[009h 0009  1]                     Checksum : 3D
[00Ah 0010  6]                       Oem ID : "Nvidia"
[010h 0016  8]                 Oem Table ID : "ASUSACPI"
[018h 0024  4]                 Oem Revision : 42302E31
[01Ch 0028  4]              Asl Compiler ID : "AWRD"
[020h 0032  4]        Asl Compiler Revision : 00000000

[024h 0036  4]                 FACS Address : CFEF0000
[028h 0040  4]                 DSDT Address : CFEF3240
[02Ch 0044  1]                        Model : 00
[02Dh 0045  1]                   PM Profile : 01 (Desktop)
[02Eh 0046  2]                SCI Interrupt : 0009
[030h 0048  4]             SMI Command Port : 0000142E
[034h 0052  1]            ACPI Enable Value : A1
[035h 0053  1]           ACPI Disable Value : A0
[036h 0054  1]               S4BIOS Command : 00
[037h 0055  1]              P-State Control : 34
[038h 0056  4]     PM1A Event Block Address : 00001000
[03Ch 0060  4]     PM1B Event Block Address : 00000000
[040h 0064  4]   PM1A Control Block Address : 00001004
[044h 0068  4]   PM1B Control Block Address : 00000000
[048h 0072  4]    PM2 Control Block Address : 0000101C
[04Ch 0076  4]       PM Timer Block Address : 00001008
[050h 0080  4]           GPE0 Block Address : 00001020
[054h 0084  4]           GPE1 Block Address : 000014A0
[058h 0088  1]       PM1 Event Block Length : 04
[059h 0089  1]     PM1 Control Block Length : 02
[05Ah 0090  1]     PM2 Control Block Length : 01
[05Bh 0091  1]        PM Timer Block Length : 04
[05Ch 0092  1]            GPE0 Block Length : 08
[05Dh 0093  1]            GPE1 Block Length : 10
[05Eh 0094  1]             GPE1 Base Offset : 20
[05Fh 0095  1]                 _CST Support : 00
[060h 0096  2]                   C2 Latency : 0065
[062h 0098  2]                   C3 Latency : 03E9
[064h 0100  2]               CPU Cache Size : 0000
[066h 0102  2]           Cache Flush Stride : 0000
[068h 0104  1]            Duty Cycle Offset : 01
[069h 0105  1]             Duty Cycle Width : 03
[06Ah 0106  1]          RTC Day Alarm Index : 7D
[06Bh 0107  1]        RTC Month Alarm Index : 7E
[06Ch 0108  1]            RTC Century Index : 32
[06Dh 0109  2]   Boot Flags (decoded below) : 0000
             Legacy Devices Supported (V2) : 0
          8042 Present on ports 60/64 (V2) : 0
                      VGA Not Present (V4) : 0
                    MSI Not Supported (V4) : 0
              PCIe ASPM Not Supported (V4) : 0
[06Fh 0111  1]                     Reserved : 00
[070h 0112  4]        Flags (decoded below) : 000004A5
    WBINVD instruction is operational (V1) : 1
            WBINVD flushes all caches (V1) : 0
                  All CPUs support C1 (V1) : 1
                C2 works on MP system (V1) : 0
          Control Method Power Button (V1) : 0
          Control Method Sleep Button (V1) : 1
      RTC wake not in fixed reg space (V1) : 0
          RTC can wake system from S4 (V1) : 1
                      32-bit PM Timer (V1) : 0
                    Docking Supported (V1) : 0
             Reset Register Supported (V2) : 1
                          Sealed Case (V3) : 0
                  Headless - No Video (V3) : 0
      Use native instr after SLP_TYPx (V3) : 0
            PCIEXP_WAK Bits Supported (V4) : 0
                   Use Platform Timer (V4) : 0
             RTC_STS valid on S4 wake (V4) : 0
              Remote Power-on capable (V4) : 0
               Use APIC Cluster Model (V4) : 0
   Use APIC Physical Destination Mode (V4) : 0

[074h 0116 12]               Reset Register : 
[074h 0116  1]                     Space ID : 01 (SystemIO)
[075h 0117  1]                    Bit Width : 08
[076h 0118  1]                   Bit Offset : 00
[077h 0119  1]                 Access Width : 00
[078h 0120  8]                      Address : 0000000000000CF9

[080h 0128  1]         Value to cause reset : 06
[081h 0129  3]                     Reserved : 000000
[084h 0132  8]                 FACS Address : 00000000CFEF0000
[08Ch 0140  8]                 DSDT Address : 00000000CFEF3240
[094h 0148 12]             PM1A Event Block : 
[094h 0148  1]                     Space ID : 01 (SystemIO)
[095h 0149  1]                    Bit Width : 08
[096h 0150  1]                   Bit Offset : 00
[097h 0151  1]                 Access Width : 00
[098h 0152  8]                      Address : 0000000000001000

[0A0h 0160 12]             PM1B Event Block : 
[0A0h 0160  1]                     Space ID : 01 (SystemIO)
[0A1h 0161  1]                    Bit Width : 08
[0A2h 0162  1]                   Bit Offset : 00
[0A3h 0163  1]                 Access Width : 00
[0A4h 0164  8]                      Address : 0000000000000000

[0ACh 0172 12]           PM1A Control Block : 
[0ACh 0172  1]                     Space ID : 01 (SystemIO)
[0ADh 0173  1]                    Bit Width : 08
[0AEh 0174  1]                   Bit Offset : 00
[0AFh 0175  1]                 Access Width : 00
[0B0h 0176  8]                      Address : 0000000000001004

[0B8h 0184 12]           PM1B Control Block : 
[0B8h 0184  1]                     Space ID : 01 (SystemIO)
[0B9h 0185  1]                    Bit Width : 08
[0BAh 0186  1]                   Bit Offset : 00
[0BBh 0187  1]                 Access Width : 00
[0BCh 0188  8]                      Address : 0000000000000000

[0C4h 0196 12]            PM2 Control Block : 
[0C4h 0196  1]                     Space ID : 01 (SystemIO)
[0C5h 0197  1]                    Bit Width : 08
[0C6h 0198  1]                   Bit Offset : 00
[0C7h 0199  1]                 Access Width : 00
[0C8h 0200  8]                      Address : 000000000000101C

[0D0h 0208 12]               PM Timer Block : 
[0D0h 0208  1]                     Space ID : 01 (SystemIO)
[0D1h 0209  1]                    Bit Width : 08
[0D2h 0210  1]                   Bit Offset : 00
[0D3h 0211  1]                 Access Width : 00
[0D4h 0212  8]                      Address : 0000000000001008

[0DCh 0220 12]                   GPE0 Block : 
[0DCh 0220  1]                     Space ID : 01 (SystemIO)
[0DDh 0221  1]                    Bit Width : 08
[0DEh 0222  1]                   Bit Offset : 00
[0DFh 0223  1]                 Access Width : 00
[0E0h 0224  8]                      Address : 0000000000001020

[0E8h 0232 12]                   GPE1 Block : 
[0E8h 0232  1]                     Space ID : 01 (SystemIO)
[0E9h 0233  1]                    Bit Width : 08
[0EAh 0234  1]                   Bit Offset : 00
[0EBh 0235  1]                 Access Width : 00
[0ECh 0236  8]                      Address : 00000000000014A0


Raw Table Data

 0000: 46 41 43 50 F4 00 00 00 03 3D 4E 76 69 64 69 61  FACP.....=Nvidia
 0010: 41 53 55 53 41 43 50 49 31 2E 30 42 41 57 52 44  ASUSACPI1.0BAWRD
 0020: 00 00 00 00 00 00 EF CF 40 32 EF CF 00 01 09 00  ........@2......
 0030: 2E 14 00 00 A1 A0 00 34 00 10 00 00 00 00 00 00  .......4........
 0040: 04 10 00 00 00 00 00 00 1C 10 00 00 08 10 00 00  ................
 0050: 20 10 00 00 A0 14 00 00 04 02 01 04 08 10 20 00   ............. .
 0060: 65 00 E9 03 00 00 00 00 01 03 7D 7E 32 00 00 00  e.........}~2...
 0070: A5 04 00 00 01 08 00 00 F9 0C 00 00 00 00 00 00  ................
 0080: 06 00 00 00 00 00 EF CF 00 00 00 00 40 32 EF CF  ............@2..
 0090: 00 00 00 00 01 08 00 00 00 10 00 00 00 00 00 00  ................
 00A0: 01 08 00 00 00 00 00 00 00 00 00 00 01 08 00 00  ................
 00B0: 04 10 00 00 00 00 00 00 01 08 00 00 00 00 00 00  ................
 00C0: 00 00 00 00 01 08 00 00 1C 10 00 00 00 00 00 00  ................
 00D0: 01 08 00 00 08 10 00 00 00 00 00 00 01 08 00 00  ................
 00E0: 20 10 00 00 00 00 00 00 01 08 00 00 A0 14 00 00   ...............
 00F0: 00 00 00 00                                      ....

so my question is, based on the above information, do I have the possibility of setting up vanilla Speedstep for OS X (Leopard and Snow Leopard) so that I can enable Enhanced C1 (C1E) and Enhanced Intel Speedstep Technology in BIOS to allow their use with Windows/Linux....and hence drop my core temps for all OS's.....?

BTW OS X versions 10.5.7, 10.5.8 and 10.6.0, 10.6.1 will not sleep properly (previous versions from 10.5.1 to 10.5.6 have all had fully functioning sleep)......

When I select Sleep, the display goes black but the PC fans stay on and then the display cannot be woken up.......I need to reboot to get the display back......

Master Chief · October 14, 2009

Hi Master Chief, I hope this is not off-topic but on my 650i nForce chipset MOBO with the current BIOS settings (I will get to my specific question at the end)......

<snip />

so my question is, based on the above information, do I have the possibility of setting up vanilla Speedstep for OS X (Leopard and Snow Leopard) so that I can enable Enhanced C1 (C1E) and Enhanced Intel Speedstep Technology in BIOS to allow their use with Windows/Linux....and hence drop my core temps for all OS's.....?

How's this for an answer: I'm quite surprised that you haven't enabled them already. Yes, by all means; do enable them in your BIOS to lower the core temperatures. And I hope that P-State stepping works for you, because all I see is the 6 and 9 multiplier in your screen shot.

BTW OS X versions 10.5.7, 10.5.8 and 10.6.0, 10.6.1 will not sleep properly (previous versions from 10.5.1 to 10.5.6 have all had fully functioning sleep)......

When I select Sleep, the display goes black but the PC fans stay on and then the display cannot be woken up.......I need to reboot to get the display back......

OT: You can fix this by modifying your DSDT with help of the info available in the P5K PRO Snow Leopard thread.

BTW: Your FACP table tells me that your BIOS does not include C-State data and thus you'll have to add it yourself – getting C1 to work should be a piece of a cake.

verdant · October 14, 2009

How's this for an answer: I'm quite surprised that you haven't enabled them already. Yes, by all means; do enable them in your BIOS to lower the core temperatures. And I hope that P-State stepping works for you, because all I see is the 6 and 9 multiplier in your screen shot.

OT: You can fix this by modifying your DSDT with help of the info available in the P5K PRO Snow Leopard thread.

BTW: Your FACP table tells me that your BIOS does not include C-State data and thus you'll have to add it yourself �" getting C1 to work should be a piece of a cake.

Thanks for your very helpful answer.......

I had not enabled them previously because with Leopard I have to use the Voodoo 9.5.0 kernel (the Leopard vanilla kernels always cause random KPs....) and CPU-i showed/shows no P-states running the Voodoo kernel.....

With Enhanced C1 (C1E) and Enhanced Intel Speedstep Technology now enabled in BIOS, I get under OS X 10.6.1.....

versus when disabled......

but no meaningful drop in core temps despite the apparent drop in core frequency, change in multiplier with voltages and temps changing in real time......seems DSDT modding is required......

mm67 · October 15, 2009

Anyone want to take a look at these dumps. These are from MSI P43-Neo, P-states and C-states work out of the box, USB works out of the box, ICH10 works out of the box(no fixes in dsdt and silver HD icons). Only problem is that shutdown or restart doesn't work anymore after system has gone to sleep even once.Maybe we can learn something from these.

ACPI_Tables.zip

MSI_P43.ioreg.zip

DSDT - Vanilla Speedstep - Generic Scope (_PR)

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