kdawg Posted August 19, 2009 Share Posted August 19, 2009 This technique works like a charm on my desktop rig. Using Voodoo speedstepping works on the Mini but it's performance feels choppy. This DSDT patch basically cuts my performance in half. Anyone? Here it is: Scope (_PR) { Processor (CPU0, 0x00, 0x00001010, 0x06){ Name (_PPC, 0x00) Name (_PCT, Package (0x02) { ResourceTemplate () { Register (FFixedHW, // PERF_CTL 0x10, // Bit Width 0x00, // Bit Offset 0x0000000000000199, // Address ,) }, ResourceTemplate () { Register (FFixedHW, // PERF_STATUS 0x10, // Bit Width 0x00, // Bit Offset 0x0000000000000198, // Address ,) } }) Name (_PSS, Package (0x04) { Package (0x06)// P-State 0 { 1596, // f in MHz 2000, // P in mW 10, // Transition latency in us 10, // Bus Master latency in us 0x00000C20, // value written to PERF_CTL; fid=12, vid=32 0x00000C20 // value of PERF_STATE after successful transition; fid=12, vid=32 }, Package (0x06)// P-State 1 { 1330, // f in MHz 1500, // P in mW 10, // Transition latency in us 10, // Bus Master latency in us 0x00000A1A, // value written to PERF_CTL; fid=10, vid=26 0x00000A1A // value of PERF_STATE after successful transition; fid=10, vid=26 }, Package (0x06)// P-State 2 { 1064, // f in MHz 1000, // P in mW 10, // Transition latency in us 10, // Bus Master latency in us 0x00000812, // value written to PERF_CTL; fid=8, vid=18 0x00000812 // value of PERF_STATE after successful transition; fid=8, vid=18 }, Package (0x06)// P-State 3 { 798, // f in MHz 600, // P in mW 10, // Transition latency in us 10, // Bus Master latency in us 0x0000060A, // value written to PERF_CTL; fid=6, vid=10 0x0000060A // value of PERF_STATE after successful transition; fid=6, vid=10 }, }) } Processor (CPU1, 0x01, 0x00001010, 0x06){ Name (_PPC, 0x00) Name (_PCT, Package (0x02) { ResourceTemplate () { Register (FFixedHW, // PERF_CTL 0x10, // Bit Width 0x00, // Bit Offset 0x0000000000000199, // Address ,) }, ResourceTemplate () { Register (FFixedHW, // PERF_STATUS 0x10, // Bit Width 0x00, // Bit Offset 0x0000000000000198, // Address ,) } }) Name (_PSS, Package (0x04) { Package (0x06)// P-State 0 { 1596, // f in MHz 2000, // P in mW 10, // Transition latency in us 10, // Bus Master latency in us 0x00000C20, // value written to PERF_CTL; fid=12, vid=32 0x00000C20 // value of PERF_STATE after successful transition; fid=12, vid=32 }, Package (0x06)// P-State 1 { 1330, // f in MHz 1500, // P in mW 10, // Transition latency in us 10, // Bus Master latency in us 0x00000A1A, // value written to PERF_CTL; fid=10, vid=26 0x00000A1A // value of PERF_STATE after successful transition; fid=10, vid=26 }, Package (0x06)// P-State 2 { 1064, // f in MHz 1000, // P in mW 10, // Transition latency in us 10, // Bus Master latency in us 0x00000812, // value written to PERF_CTL; fid=8, vid=18 0x00000812 // value of PERF_STATE after successful transition; fid=8, vid=18 }, Package (0x06)// P-State 3 { 798, // f in MHz 600, // P in mW 10, // Transition latency in us 10, // Bus Master latency in us 0x0000060A, // value written to PERF_CTL; fid=6, vid=10 0x0000060A // value of PERF_STATE after successful transition; fid=6, vid=10 }, }) } } Here is my complete DSDT. dsdt_r3_Speedstep.dsl.zip Link to comment Share on other sites More sharing options...
waldo_pepperjack Posted December 30, 2009 Share Posted December 30, 2009 kdawg, I know this is an older post, and that since you wrote it, NBI has been released (several versions) ... I have the voodoo processor stepping kext in my Mini10v. It does help the battery life somewhat, but I'd always like to get a bit more out of the battery as well. Did you make any progress on this? I am curious, because I had just worked out a dsdt solution for my HackPro (Gigabyte GA-EP45-UD3L mobo) and I really like the idea of putting all the fixes in the dsdt.aml, rather than all those kexts. I'm wondering if meklort, mechdrew & the others @ mydellmini have moved the as many fixes to the dsdt as is possible, and truly minimized the number of kexts needed. Link to comment Share on other sites More sharing options...
kdawg Posted December 30, 2009 Author Share Posted December 30, 2009 kdawg, I know this is an older post, and that since you wrote it, NBI has been released (several versions) ... I have the voodoo processor stepping kext in my Mini10v. It does help the battery life somewhat, but I'd always like to get a bit more out of the battery as well. Did you make any progress on this? I am curious, because I had just worked out a dsdt solution for my HackPro (Gigabyte GA-EP45-UD3L mobo) and I really like the idea of putting all the fixes in the dsdt.aml, rather than all those kexts. I'm wondering if meklort, mechdrew & the others @ mydellmini have moved the as many fixes to the dsdt as is possible, and truly minimized the number of kexts needed. I didn't honestly see a lot of DSDT patching in their netbook installer. I tried going the manaul route with as much DSDT as possible but there was too much else going on in the Mini that made it difficult to debug. I have since decided to sell my Mini for that reason. I'll take a peek at what I had done and where it might be improved if I get some time. Link to comment Share on other sites More sharing options...
18seven Posted January 7, 2010 Share Posted January 7, 2010 Native Speedstepping on Atom N270 is not possible in 10.6. This requires the ability to load AppleIntelCPUPowermanagment. However, if you are using 10.5.8 it works like a charm. The processor cap issue can be fixed by grabbing the states from SSDT's and adding DropSSDT=Yes bootflag. AFAIR an issue with OSC causes that (left 10.5 a while ago). Anyone who tries this must NOT have sleepEnabler loaded since AppleCPUPM will deliver the needed calls. You may need to tidy up HPET as well. Have fun... Link to comment Share on other sites More sharing options...
XPbIM3 Posted January 23, 2010 Share Posted January 23, 2010 we already havea binpatched kernel for atom. Anybody to help with binpatching CPUPM? )) or ability to fake CPUID? Link to comment Share on other sites More sharing options...
zcream Posted July 7, 2012 Share Posted July 7, 2012 Ive been trying to get native PM workign on a Dell mini 9 N270 on 10.6.8 as NBI does not support it.. Just wondering if anyone managed to get this via native ApplePM ? This is what I have so far under Scope (_PR) Processor (CPU0, 0x00, 0x00001010, 0x06){ Name (_PPC, 0x00) Name (_PCT, Package (0x02) { ResourceTemplate () { Register (FFixedHW, // PERF_CTL 0x10, // Bit Width 0x00, // Bit Offset 0x0000000000000199, // Address ,) }, ResourceTemplate () { Register (FFixedHW, // PERF_STATUS 0x10, // Bit Width 0x00, // Bit Offset 0x0000000000000198, // Address ,) } }) Name (_PSS, Package (0x04) { Package (0x06)// P-State 0 { 1596, // f in MHz 2000, // P in mW 10, // Transition latency in us 10, // Bus Master latency in us 0x00000C20, // value written to PERF_CTL; fid=12, vid=32 0x00000C20 // value of PERF_STATE after successful transition; fid=12, vid=32 }, Package (0x06)// P-State 1 { 1330, // f in MHz 1500, // P in mW 10, // Transition latency in us 10, // Bus Master latency in us 0x00000A1A, // value written to PERF_CTL; fid=10, vid=26 0x00000A1A // value of PERF_STATE after successful transition; fid=10, vid=26 }, Package (0x06)// P-State 2 { 1064, // f in MHz 1000, // P in mW 10, // Transition latency in us 10, // Bus Master latency in us 0x00000812, // value written to PERF_CTL; fid=8, vid=18 0x00000812 // value of PERF_STATE after successful transition; fid=8, vid=18 }, Package (0x06)// P-State 3 { 798, // f in MHz 600, // P in mW 10, // Transition latency in us 10, // Bus Master latency in us 0x0000060A, // value written to PERF_CTL; fid=6, vid=10 0x0000060A // value of PERF_STATE after successful transition; fid=6, vid=10 }, }) } we already havea binpatched kernel for atom. Anybody to help with binpatching CPUPM? )) or ability to fake CPUID? Link to comment Share on other sites More sharing options...
Recommended Posts