[Guide] Using DSDT with the Gigabyte GA-EP45-DS3L

[PSUlion01]

blackosx: Is speedstep enabled in v5? I can't seem to find the pss parts to edit for my cpu?

 

Per my PMs with him, I don't believe any of the stepping code exists in the v5 DSDT. I believe you need to follow his instuctions here http://www.insanelymac.com/forum/index.php...p;#entry1334977

 

From what I can follow, the stepping code needs to be added to the DSDT file right after the line that reads:

 

DefinitionBlock ("/Volumes......../dsdt.aml", "DSDT", 1, "GBT ", "GBTUACPI", 0x00001000)

{

 

 

Does that seem right? I haven't tried this yet but am planning on doing it this weekend.

 

I tried various fixes, but always ended up getting KPs. So i bought a bigger sata drive

 

Interesting... My system seems pretty solid right now, but I've got about 400gb worth of IDE drives that I'd hate to lose, and am really trying to get away from using enclosures. Any idea if I can install one of the IDE drives and use it for a Windows 7 drive? Windows and OSX would be completely separate physical drives, so there shouldn't be any issues, right? Or would the mere presence of the drive in my tower cause OSX to go haywire?

 

Thanks for your feedback.

[DieBuche]

It only KP'ed when spotlight indexing the drive/other heavy i/o. If u fstab ur drive, i think it would work.

[sw170]

Can someone point me to the right thread/post that discusses enabling IDE drive support in 10.6 with the board I have, or an equivalent Gigabyte board?

 

Thanks,

Mike

Hi Mike

try to use ATAPortInjector.kext from this pack, not sure about UD3L but it works on GA-EP45-UD3R, another solution is to use SATA to PATA converter, check it here, I use them on 3 of my drives without issues.

good luck

s

[kdawg]

Sorry if this has been covered, but most of the time the InsanelyMac search gives me an error, and when it does work I don't get the right hits.

....

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[blackosx]

I've got my system almost perfect thanks to blackosx's guides and help, but I'm trying to add support for my older IDE hard drives, and would prefer to have them in my tower vs. in external USB enclosures as they are today.

 

Can someone point me to the right thread/post that discusses enabling IDE drive support in 10.6 with the board I have, or an equivalent Gigabyte board?

Hi Mike

 

The DSDT I now use here is based on mm67's excellent stripped out DSDT. Stripped out because anything that a Mac doesn't use is gone. For instance support for IDE and PS/2 devices.

 

Today I pointed Marby, from my 10.6 thread, towards the Gigabyte DSDT fix thread to ask mm67 what he needs to do to add these devices back in and this is mm67's reply.

 

EDIT: Then when the DSDT had the IDE devices back in, you can try the kexts that swavek has kindly posted a link to.

 

EDIT: I have had a go at adding back in the PS/2 and IDE devices that mm67 referred to. There is no guarantee that it will work and this untested as I don't use them on my hack but would you be kind enough to check it out and report back?

 

I have added it to the current Generic v5 DSDT and you will still need to add kexts for PS/2 and IDE devices for them to work.

GA_EP45_DS3L_DSDT_Generic_v5_PS2_IDE.zip

 

 

blackosx: Is speedstep enabled in v5? I can't seem to find the pss parts to edit for my cpu?

Hi DieBuche

 

No, speedstep is not enabled in the v5 DSDT.

As Mike (PSUlion01) kindly mentioned, you will need to follow the steps I posted here.

 

If you have have already done this before and you have the require data etc. then you can add your revised Scope (_PR) section to the DSDT v5. Here's the .dsl for v5

dsdt.dsl.zip

 

All you need to do is replace this section at the top of the DSDT

Scope (_PR)
   {
       Processor (CPU0, 0x00, 0x00000410, 0x06) {}
       Processor (CPU1, 0x01, 0x00000410, 0x06) {}
       Processor (CPU2, 0x02, 0x00000410, 0x06) {}
       Processor (CPU3, 0x03, 0x00000410, 0x06) {}
   }

 

with your Scope (_PR) which might look something like this (which is mine for my E7300 CPU)

Scope (_PR)
   {
       Name (PSS, Package (0x05) // For Intel Core 2 Duo E7300 @ 2.66Ghz
       {
           Package (0x06) { 2670, 0, 10, 10, 0x0A1D, 0 },
           Package (0x06) { 2403, 0, 10, 10, 0x091D, 1 },
           Package (0x06) { 2136, 0, 10, 10, 0x081C, 2 },
           Package (0x06) { 1869, 0, 10, 10, 0x071B, 3 },
           Package (0x06) { 1602, 0, 10, 10, 0x061A, 4 }
       })

       Name (PSD, Package (0x05)
       {
           0x05,
           0x00,
           0x00,
           0xFC, // Double-checked the 0xFC value with ACPISpec v4.0 pdf
           0x02  // Number of Processors - If you have a Quad core CPU then this value should read 0x04
       })

       Name (CST, Package (0x04)
       {
           0x03, 
           Package (0x04) {ResourceTemplate () {Register (FFixedHW, 1, 2, 0x000,)},0x01,0x01,0x03E8},
           Package (0x04) {ResourceTemplate () {Register (FFixedHW, 1, 2, 0x010,)},0x02,0x01,0x01F4},
           Package (0x04) {ResourceTemplate () {Register (FFixedHW, 1, 2, 0x030,)},0x04,0x39,0x064}
       })

       Processor (CPU0, 0x0, 0x00000410, 0x06)
       {
           Alias (PSS, _PSS)
           Alias (PSD, _PSD)
           Alias (CST, _CST)
       }

       Processor (CPU1, 0x01, 0x00000410, 0x06)
       {
           Alias (PSS, _PSS)
           Alias (PSD, _PSD)
           Alias (CST, _CST)
       }
   }

 

For those looking for a better InsanelyMac search tool install the Firefox plugin, for OSX and Windows, from my signature. Works in IE7 too you just have to select it manually in the upper right search dropdown.

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Good job

[spacr]

Thanks again Blackosx for another great guide.

 

I have 2 questions.

Do I need to enter my own cstate info or can I use yours (I have a core2duo e8400)

 

Also when I compile I get 2 errors but have no idea how to read them. I followed the code exactly:

 

/Volumes/timemachine/dsdt/dsdt.dsl 31: Zero,

Error 4096 - ^ syntax error, unexpected PARSEOP_ZERO

 

/Volumes/timemachine/dsdt/dsdt.dsl 1335: [*** iASL: Read error on source code temp file /Volumes/timemachine/dsdt/Sessions/2010-01-25-010449/dsdt.src ***]

Error 4096 - ^ syntax error, unexpected $end

 

Thanks!

dsdt.zip

[blackosx]

Thanks again Blackosx for another great guide.

 

I have 2 questions.

Do I need to enter my own cstate info or can I use yours (I have a core2duo e8400)

 

Also when I compile I get 2 errors but have no idea how to read them. I followed the code exactly:

 

 

 

Thanks!

Hi spacr

 

I am not sure what motherboard you have. Can you create a signature detailing this please.. (Click on the cog icon above your login name in the blue bar near the top of the screen, then in the next windows, click 'Edit Signature' for the left edge).

 

But in the mean time I have fixed the problem with your DSDT failing to compile and changed the style of your Scope (_PR) section to match mine. And attached it here for you. dsdt.dsl.zip

With regard to C-states, I have replaced you code with mine which will hopefully work for you. But you will need to find put how many C-States your CPU supports. You can find out everything you need to know in FormerlyKnownAs' vanilla SpeedStep thread. You can also have a look in the Gigabyte DSDT fix thread . I know they're long threads but look for some of the work done later on in the threads by mm67.

[spacr]

Hi spacr

 

I am not sure what motherboard you have. Can you create a signature detailing this please.. (Click on the cog icon above your login name in the blue bar near the top of the screen, then in the next windows, click 'Edit Signature' for the left edge).

 

But in the mean time I have fixed the problem with your DSDT failing to compile and changed the style of your Scope (_PR) section to match mine. And attached it here for you. dsdt.dsl.zip

With regard to C-states, I have replaced you code with mine which will hopefully work for you. But you will need to find put how many C-States your CPU supports. You can find out everything you need to know in FormerlyKnownAs' vanilla SpeedStep thread. You can also have a look in the Gigabyte DSDT fix thread . I know they're long threads but look for some of the work done later on in the threads by mm67.

 

Works great. Thank you very much. I don't see any performance boost unfortunately (stays around 5600 in GeekBench) but at least I get to remove another kext. I will read up on the C-states even though it gets really confusing....

[sw170]

...

But in the mean time I have fixed the problem with your DSDT failing to compile and changed the style of your Scope (_PR) section to match mine. And attached it here for you. dsdt.dsl.zip

Hi Blackosx,

sstep section in above dsdt looks exactly like mine(sstates,pstates cooked myself based on FKA guide, cstates ta to mm67) and I also have E8400 oc'd to 3600, exactly but not those two sections (in red):

            Package (0x04)
           {
               ResourceTemplate ()
               {
                   Register (FFixedHW, 
                       0x01,               // Bit Width
                       0x02,               // Bit Offset
                       0x0000000000000010, // Address
                       [color="#FF0000"][b]0x01[/b][/color],               // Access Size
                       )
               }, 

               0x02, 
               One, 
               0x01F4
           }, 

           Package (0x04)
           {
               ResourceTemplate ()
               {
                   Register (FFixedHW, 
                       0x01,               // Bit Width
                       0x02,               // Bit Offset
                       0x0000000000000030, // Address
                       [b][color="#FF0000"]0x03[/color][/b],               // Access Size
                       )
               }, 

               0x04, 
               0x39, 
               0x64

any chance you know what for they are ?

thank you

regards

s

 

ps. idle temps on med case fan blow - 38C / min and quiet - 41C / max and loud! 34C

what your temps spacr ?

[spacr]

ps. idle temps on med case fan blow - 38C / min and quiet - 41C / max and loud! 34C

what your temps spacr ?

 

I idle at 30C and hit about 43C under max load

[helob]

I idle at 30C and hit about 43C under max load

 

Excellent result with so low temp.

I am using GA-EP45-UD3L with Intel E8400 like yours.

However I am seeing an idle temp of 51C and 60C at max load.

I would like to try out your DSDT.

Would appreciate if you can upload it here.

TQ

[spacr]

Excellent result with so low temp.

I am using GA-EP45-UD3L with Intel E8400 like yours.

However I am seeing an idle temp of 51C and 60C at max load.

I would like to try out your DSDT.

Would appreciate if you can upload it here.

TQ

 

I also have a really good aftermarket cpu cooler. You can try my dsdt, Blackosx posted it above. It wont work if you dont have the same overclocking settings though. So be careful you dont mess up your system

[Johnny V]

I also have a really good aftermarket cpu cooler. You can try my dsdt, Blackosx posted it above. It wont work if you dont have the same overclocking settings though. So be careful you dont mess up your system

 

Also note the ambient temp of your computer room. I thought my computer was running hot at 51C degrees until I was in the bios recently and the temp readings were only about 4 degrees cooler. So temps are in the ball park. My office is in the basement by the furnace so it does get toastie while doing computer work.

[blackosx]

Hi Blackosx,

sstep section in above dsdt looks exactly like mine(sstates,pstates cooked myself based on FKA guide, cstates ta to mm67) and I also have E8400 oc'd to 3600, exactly but not those two sections (in

... /snip/ ....

any chance you know what for they are ?

Hi swavek

 

No, I am not sure. I can tell you is when I look at my SSDT (Cst) files generated from an ACPIdump in Linux, they contain a blank field for those supposed values that you mention... for example.

  Package (0x04)
                   {
                       ResourceTemplate ()
                       {
                           Register (FFixedHW, 
                               0x00,               // Bit Width
                               0x00,               // Bit Offset
                               0x0000000000000000, // Address
                               ,)
                       }, 

                       0x01, 
                       0x01, 
                       0x03E8
                   }, 

 

You can more about the FFixedHW in Superhai's post here and the ACPI spec PDF.

[helob]

I also have a really good aftermarket cpu cooler. You can try my dsdt, Blackosx posted it above. It wont work if you dont have the same overclocking settings though. So be careful you dont mess up your system

 

Hi,

I have tried Blackosx dsdt with modified PState for E8400 CPU.

Since you are using E8400, I like to know what PState data you are using based on PStateChanger.

TQ

[spacr]

Hi,

I have tried Blackosx dsdt with modified PState for E8400 CPU.

Since you are using E8400, I like to know what PState data you are using based on PStateChanger.

TQ

[helob]

Hi Spacr,

Thanks for providing Pstates table for yout E8400.

Since I am not using OC, I can't used those values.

Thank you anyway

[fanfan22]

since this topic sticks to GA-EP45-DS3L, it is good idea to provide a .aml file directly for those who didn't want to spend time on building his own aml file. very happy there is a aml file provided. And want to see on how to use the file, for example what other additional kext are need after install this aml file?

[blackosx]

And want to see on how to use the file, for example what other additional kext are need after install this aml file?

A good place to start would be at my 10.6 install thread.

[helob]

Hi blaclosx,

I am looking for your last DSDT which has speedstep included as your latest below does not have speedstep.

 

"LATEST - Credit to mm67 for this DSDT.

Attached File GA_EP45_DS3L_DSDT_Generic_v5.zip ( 2.85K ) Number of downloads: 167

Last updated 17th January 2009 - 20:27"

 

Would apprecaite if you can direct me or upload your latest DSDT which has speed step.

 

TQ & have a nice day.

[Marby]

Blackosx,

You can change the pci root value in the DSDT by changing Name (_UID, One) to Name (_UID, Zero)

 

 

 

Change this:

 

Device (PCI0)

{

Name (_HID, EisaId ("PNP0A03"))

Name (_ADR, Zero)

Name (_UID, One)

Name (_BBN, Zero)

Name (_STA, 0x0F)

Method (_CRS, 0, NotSerialized)

 

To this:

 

Device (PCI0)

{

Name (_HID, EisaId ("PNP0A03"))

Name (_ADR, Zero)

Name (_UID, Zero)

Name (_BBN, Zero)

Name (_STA, 0x0F)

Method (_CRS, 0, NotSerialized)

 

After doing so you can set pciroot to 0 in com.apple.Boot.plist

[blackosx]

Hi blaclosx,

I am looking for your last DSDT which has speedstep included as your latest below does not have speedstep.

 

"LATEST - Credit to mm67 for this DSDT.

Attached File GA_EP45_DS3L_DSDT_Generic_v5.zip ( 2.85K ) Number of downloads: 167

Last updated 17th January 2009 - 20:27"

 

Would apprecaite if you can direct me or upload your latest DSDT which has speed step.

 

TQ & have a nice day.

Hi Helob

 

The Generic DSDT is as the name suggests, generic, so anyone with the qualifying motherboard can use it. You can then add your own CPU data is you choose.

 

Here's the latest one I am using right now which includes CPU data for my E7300 @ 2.66Ghz so don't use it exactly unless you have the same. dsdt.dsl.zip

You will find my CPU data added under Scope (_SB). This is because a while back MasterChief identified that it doesn't have to be under Scope (_PR).

 

Blackosx,

You can change the pci root value in the DSDT by changing Name (_UID, One) to Name (_UID, Zero)

Hi Marby

 

Yes this has been discussed before somewhere in this thread and it is no longer necessary to do this as the new bootloaders support auto PCIroot detection. Try having a go with the latest Chameleon RC5 pre-release v8 and you'll find you don't need to touch this. Dr Hurt has put together an installer for the current pre-release. Run it and point it at your Cham partition.

[helob]

Hi Helob

 

The Generic DSDT is as the name suggests, generic, so anyone with the qualifying motherboard can use it. You can then add your own CPU data is you choose.

 

Here's the latest one I am using right now which includes CPU data for my E7300 @ 2.66Ghz so don't use it exactly unless you have the same. dsdt.dsl.zip

You will find my CPU data added under Scope (_SB). This is because a while back MasterChief identified that it doesn't have to be under Scope (_PR).

 

Hi blackosx,

TQ for sharing with me your latest dsdt with speedstep.

 

I noticed that under Scope (_SB)

 

Name (CST, Package (0x04)

{

0x03,

Package (0x04) {ResourceTemplate () {Register (FFixedHW, 1, 2, 0x000,)},0x01,0x01,0x03E8},

Package (0x04) {ResourceTemplate () {Register (FFixedHW, 1, 2, 0x010,)},0x02,0x01,0x01F4},

Package (0x04) {ResourceTemplate () {Register (FFixedHW, 1, 2, 0x030,)},0x04,0x39,0x064}

})

 

You don't used SystemIO for ResourceTemplate anymore for C2 & C4 state under Register. Instead you use FFixedHW. Any reason?

 

Based on my ssdt_cp0cst.dsl dump, I have

Scope (\_PR.CPU0)

{

Method (_CST, 0, NotSerialized)

{

If (And (CFGD, 0x80))

{

Return (Package (0x04)

{

0x03,

Package (0x04)

{

ResourceTemplate ()

{

Register (FFixedHW,

0x00, // Bit Width

0x00, // Bit Offset

0x0000000000000000, // Address

,)

},

 

0x01,

0x01,

0x03E8

},

 

Package (0x04)

{

ResourceTemplate ()

{

Register (SystemIO,

0x08, // Bit Width

0x00, // Bit Offset

0x0000000000000414, // Address

,)

},

 

0x02,

0x01,

0x01F4

},

 

Package (0x04)

{

ResourceTemplate ()

{

Register (SystemIO,

0x08, // Bit Width

0x00, // Bit Offset

0x0000000000000416, // Address

,)

},

 

0x03,

0x96,

0x64

}

})

}

 

Should I change "Package (0x04) {ResourceTemplate () {Register (FFixedHW, 1, 2, 0x030,)},0x04,0x39,0x064}" for C4 to

Package (0x04) {ResourceTemplate () {Register (FFixedHW, 1, 2, 0x030,)},0x03,0x96,0x064}?

 

TQ & Have a nice day

ssdt_cpu0cst.txt

[blackosx]

I noticed that under Scope (_SB)

 

Name (CST, Package (0x04)

{

0x03,

Package (0x04) {ResourceTemplate () {Register (FFixedHW, 1, 2, 0x000,)},0x01,0x01,0x03E8},

Package (0x04) {ResourceTemplate () {Register (FFixedHW, 1, 2, 0x010,)},0x02,0x01,0x01F4},

Package (0x04) {ResourceTemplate () {Register (FFixedHW, 1, 2, 0x030,)},0x04,0x39,0x064}

})

 

You don't used SystemIO for ResourceTemplate anymore for C2 & C4 state under Register. Instead you use FFixedHW. Any reason?

Hi helob

 

mm67 did some research on C-States and posted some code which that I now use. Have a look here.

[helob]

Hi helob

 

mm67 did some research on C-States and posted some code which that I now use. Have a look here.

 

Tks for the pointer.

However running the setpci -s 0:1f.0 0xa6.b command returned 00 with

Package (0x4){ResourceTemplate (){Register (FFixedHW,0x01,0x02,0x000,0x0,)},One,One,0x3E8},

Package (0x4){ResourceTemplate (){Register (FFixedHW,0x01,0x02,0x010,0x1,)},0x2,One,0x1F4},

Package (0x4){ResourceTemplate (){Register (FFixedHW,0x01,0x02,0x030,0x3,)},0x4,0x39,0x064} or Package (0x04) {ResourceTemplate (){Register (FFixedHW,0x01,0x02,0x030,0x3,)},0x4,0x96,0x064}

So my C4 state is not working.