tuxianer Posted September 2, 2009 Share Posted September 2, 2009 Oh sorry I have misunderstood the totorial and inserted my device-ids correctly. But I have to fake them. The problem is that I have 8 devices in ioregestry Explorer. So I have to change: 1A: 2937 ----> 3A37 1D: 2934 ----> 3A34 1D,1: 2935 --> 3A35 1D,2: 2936 --> 3A36 1A,1: 2938 --> 3A38 1A,2: 2939 --> 3A39 Thes ones are not named in the first post so tried this but they don't work. USB Bus is regcognized correct as integrated. But the USB High Speed Bus is still expansion slot.: 1D,7: 293A --> 3A3A 1A,7: 293C --> 3A3C And is 10.5.7 really necessary?I have attached my DSDT for USB and the fixed one. USB.rtf USB_Patched.rtf Link to comment Share on other sites More sharing options...
ApexDE Posted September 2, 2009 Share Posted September 2, 2009 @ P35 Mainboard Users It seems that P35 Users need to patch the USB-Device-IDs too (see first post in this thread). If you have issues with the EHCI Sleep-Fix, check if you patched the USB Device-IDs too. P45 Users just need the EHCI-Fix as they already have the correct USB Device-IDs. Wake with USB Mouse should work for P35 Users too, after applying the USB Device-ID Patches. Good Luck, and report back here! EDIT: Combining both Patches (device-id and ehci fix) is a bit tricky, so i post the USBE and USE2 sections here: USBE: Device (USBE) { Name (_ADR, 0x001D0007) Method (_S3D, 0, NotSerialized) { If (LEqual (OSFL, 0x02)) { Return (0x02) } Return (0x03) } Name (_PRW, Package (0x02) { 0x0D, One }) Method (_DSM, 4, NotSerialized) { Store (Package (0x06) { "device-id", Buffer (0x04) { 0x3A, 0x3A, 0x00, 0x00 }, "AAPL,clock-id", Buffer (0x01) { 0x01 }, "device_type", Buffer (0x05) { "EHCI" } }, Local0) DTGP (Arg0, Arg1, Arg2, Arg3, RefOf (Local0)) Return (Local0) } } USE2: Device (USE2) { Name (_ADR, 0x001A0007) Method (_S3D, 0, NotSerialized) { If (LEqual (OSFL, 0x02)) { Return (0x02) } Return (0x03) } Name (_PRW, Package (0x02) { 0x0D, One }) Method (_DSM, 4, NotSerialized) { Store (Package (0x06) { "device-id", Buffer (0x04) { 0x3C, 0x3A, 0x00, 0x00 }, "AAPL,clock-id", Buffer (0x01) { 0x02 }, "device_type", Buffer (0x05) { "EHCI" } }, Local0) DTGP (Arg0, Arg1, Arg2, Arg3, RefOf (Local0)) Return (Local0) } } Untested, as i have no EP35 Board Someone test and report back. Link to comment Share on other sites More sharing options...
Cathul Posted September 2, 2009 Share Posted September 2, 2009 @ P35 Mainboard Users It seems that P35 Users need to patch the USB-Device-IDs too (see first post in this thread). If you have issues with the EHCI Sleep-Fix, check if you patched the USB Device-IDs too. P45 Users just need the EHCI-Fix as they already have the correct USB Device-IDs. Wake with USB Mouse should work for P35 Users too, after applying the USB Device-ID Patches. Good Luck, and report back here! I have a Gigabyte GA-P35-DS3 Rev. 1.0 with a patched DSDT.aml. All USB ports are reported as internal, but i think i have to switch on the bios flag for wake up by mouse. Will test it as soon as i'm back home again from work. edit: nope, didn't work with my USB mouse and keyboard. Link to comment Share on other sites More sharing options...
tuxianer Posted September 2, 2009 Share Posted September 2, 2009 what is the advantage in patching the sata ports in dsdt? Link to comment Share on other sites More sharing options...
FKA Posted September 2, 2009 Share Posted September 2, 2009 Hi i want to add my P-States into my dsdt.dsl , not in an extra ssdt-x. aml. The changes(adds) in the DSDT cpu part are no problem, but i have a few questions around adding P-State tables in the CPU part of dsdt.dsl. my extracted ssdt-0 (only one ssdt in my bios!). Hi mitch_de Firstly I think you will find 4 other SSDT tables if you extract in Windows using Everest or in linux with acpidump (apologies if you have already done this.) There are two ways to add the p-states to DSDT. You can add them to PR part of DSDT like so: /* * Intel ACPI Component Architecture * AML Disassembler version 20080926 * * Disassembly of /Users/Dave/Documents/EP35DS4 OSX Install Files/DSDT Files/DSDT.aml, * * * Original Table Header: * Signature "DSDT" * Length 0x00004D8D (19853) * Revision 0x01 **** ACPI 1.0, no 64-bit math support * Checksum 0x1D * OEM ID "GBT " * OEM Table ID "GBTUACPI" * OEM Revision 0x00001000 (4096) * Compiler ID "INTL" * Compiler Version 0x20080926 (537397542) */ DefinitionBlock ("/UX Install Files/DSDT Files/DSDT.aml", "DSDT", 1, "GBT ", "GBTUACPI", 0x00001000) { Scope (_PR) { Processor (CPU0, 0x00, 0x00000410, 0x06) { Name (_PPC, Zero) Name (_PCT, Package (0x02) { ResourceTemplate () { Register (FFixedHW, 0x10, // Bit Width 0x00, // Bit Offset 0x0000000000000199, // Address ,) }, ResourceTemplate () { Register (FFixedHW, 0x10, // Bit Width 0x00, // Bit Offset 0x0000000000000198, // Address ,) } }) Name (_PSS, Package (0x03) { Package (0x06) { 0x0C20, 0x000124F8, 0x0A, 0x0A, 0x0820, 0x0820 }, Package (0x06) { 0x0A9C, 0xFDE8, 0x0A, 0x0A, 0x071C, 0x071C }, Package (0x06) { 0x0918, 0xEA60, 0x0A, 0x0A, 0x061A, 0x061A } }) } etc........ Or if you find PSS in SSDT tables (the 4 i believe you are missing.) you can add all 5 SSDT tables to the end of DSDT as described here then amend NPSS and SPSS values to suite you. I went with the second method because I wanted to add CST tables from MP3,1 SSDT and for the life of me I couldn't manage to incorporate the MP3,1 CST and get the DSDT.dsl to compile with my PSS values at the beginning of my DSDT. I have to addmit I don't know where to see p-state info in ioreg. Here are two DSDT examples Just p-state data added to DSDT DSDT_P_state_only.dsl.zip SSDT appended to end of DSDT DSDT01_09_09.dsl.zip I hope this helps. **EDIT** Here are my SSDT tables: GA_EP35_DS4_SSDT.zip D. Link to comment Share on other sites More sharing options...
kdawg Posted September 2, 2009 Share Posted September 2, 2009 Hi mitch_de Firstly I think you will find 4 other SSDT tables if you extract in Windows using Everest or in linux with acpidump (apologies if you have already done this.) There are two ways to add the p-states to DSDT. You can add them to PR part of DSDT like so: /* * Intel ACPI Component Architecture * AML Disassembler version 20080926 * * Disassembly of /Users/Dave/Documents/EP35DS4 OSX Install Files/DSDT Files/DSDT.aml, * * * Original Table Header: * Signature "DSDT" * Length 0x00004D8D (19853) * Revision 0x01 **** ACPI 1.0, no 64-bit math support * Checksum 0x1D * OEM ID "GBT " * OEM Table ID "GBTUACPI" * OEM Revision 0x00001000 (4096) * Compiler ID "INTL" * Compiler Version 0x20080926 (537397542) */ DefinitionBlock ("/UX Install Files/DSDT Files/DSDT.aml", "DSDT", 1, "GBT ", "GBTUACPI", 0x00001000) { Scope (_PR) { Processor (CPU0, 0x00, 0x00000410, 0x06) { Name (_PPC, Zero) Name (_PCT, Package (0x02) { ResourceTemplate () { Register (FFixedHW, 0x10, // Bit Width 0x00, // Bit Offset 0x0000000000000199, // Address ,) }, ResourceTemplate () { Register (FFixedHW, 0x10, // Bit Width 0x00, // Bit Offset 0x0000000000000198, // Address ,) } }) Name (_PSS, Package (0x03) { Package (0x06) { 0x0C20, 0x000124F8, 0x0A, 0x0A, 0x0820, 0x0820 }, Package (0x06) { 0x0A9C, 0xFDE8, 0x0A, 0x0A, 0x071C, 0x071C }, Package (0x06) { 0x0918, 0xEA60, 0x0A, 0x0A, 0x061A, 0x061A } }) } etc........ Or if you find PSS in SSDT tables (the 4 i believe you are missing.) you can add all 5 SSDT tables to the end of DSDT as described here then amend NPSS and SPSS values to suite you. I went with the second method because I wanted to add CST tables from MP3,1 SSDT and for the life of me I couldn't manage to incorporate the MP3,1 CST and get the DSDT.dsl to compile with my PSS values at the beginning of my DSDT. I have to addmit I don't know where to see p-state info in ioreg. Here are two DSDT examples Just p-state data added to DSDT DSDT_P_state_only.dsl.zip SSDT appended to end of DSDT DSDT01_09_09.dsl.zip I hope this helps. **EDIT** Here are my SSDT tables: GA_EP35_DS4_SSDT.zip D. In case anyone was interested where the DSDT SSDT info lives in the ioreg. Link to comment Share on other sites More sharing options...
tuxianer Posted September 2, 2009 Share Posted September 2, 2009 does anyone has a working wake up by keyboard with a P35 board? Link to comment Share on other sites More sharing options...
ApexDE Posted September 2, 2009 Share Posted September 2, 2009 OK, the "EHCI-controller-unload" fix does work on P35 Boards, if the device-ids of the UHCI Devices are patched to ICH10, check post #1. Sleep and Wake via Mouse does work (Mouse directly on Mainboard USB Port) Confirmed and working on a P35 Board NOCHMAL: If you are using a P35 Board: the UHCI Devices MUST be patched using the method described in post #1. Then change the USBE and USE2 like this http://www.insanelymac.com/forum/index.php...t&p=1247462 If you have a P45 Board, you just need the USBE and USE2 Fixes WITHOUT device-id injection. Link to comment Share on other sites More sharing options...
tuxianer Posted September 2, 2009 Share Posted September 2, 2009 OK, the "EHCI-controller-unload" fix does work on P35 Boards, if the device-ids of the UHCI Devices are patched to ICH10, check post #1. Sleep and Wake via Mouse does work (Mouse directly on Mainboard USB Port) Confirmed and working on a P35 Board NOCHMAL: If you are using a P35 Board: the UHCI Devices MUST be patched using the method described in post #1. Then change the USBE and USE2 like this http://www.insanelymac.com/forum/index.php...t&p=1247462 If you have a P45 Board, you just need the USBE and USE2 Fixes WITHOUT device-id injection. Wake up via mous or keyboard doesn't work for me. When the pc turns into sleep the mous led switches out and when I click it turns on again. But no wake up. Link to comment Share on other sites More sharing options...
FKA Posted September 2, 2009 Share Posted September 2, 2009 Wake up via mous or keyboard doesn't work for me. When the pc turns into sleep the mous led switches out and when I click it turns on again. But no wake up. Hi Apex Many thanks for this. It does get rid of the AppleUSBEHCI[0x6838800]::CheckSleepCapability - controller will be unloaded across sleep message but I still need slice's USB kext for deep sleep. D Link to comment Share on other sites More sharing options...
mitch_de Posted September 3, 2009 Share Posted September 3, 2009 Hi, i now made my PSTATES for GA-EP35-DS3 with C2D 7300/2.66 @ 3 GHZ (333 *9 insted 266*10). The problem with that GA is, that there are no P-States in the SSDT part of the bios - most other GA boards seems to have them. So you must use the override mode of voodoopower to get that worked. With that dsdt its possible not use that override mode of voodoopwoer, because now vp get the p_state tables from the dsdt patch. I used an tool which can compute the right values for each step. PstatesCalulator (OS X) Here my starting part of DSDT (dont use that 1:1 / you MUST use your own number of states (very cpu depended). Scope (_PR) { Processor ([b]CPU0[/b], 0x00, 0x00000410, 0x06) { Name (_PPC, 0x00) Name (_PCT, Package (0x02) { ResourceTemplate () { Register (FFixedHW, // PERF_CTL 0x10, // Bit Width 0x00, // Bit Offset 0x0000000000000199, // Address ,) }, ResourceTemplate () { Register (FFixedHW, // PERF_STATUS 0x10, // Bit Width 0x00, // Bit Offset 0x0000000000000198, // Address ,) } }) Name (_PSS, Package (0x[b]04[/b]) // [b]4[/b] Pstates [b]6-9[/b] fsb muilt * 333 FSB, E7300-2660 GHZ-266*10 { /* multi 10 OFF Package (0x06) { 3330, 93816, 10, 10, 0xA25, 0xA25 } */ Package (0x06) { 2997, 80535, 10, 10, 0x921, 0x921 }, // [b]2997 MHZ = 9* 333[/b] Package (0x06) { 2664, 68120, 10, 10, 0x81D, 0x81D }, Package (0x06) { 2331, 56571, 10, 10, 0x71A, 0x71A }, Package (0x06) { 1998, 45889, 10, 10, 0x616, 0x616 } }) } // end CPU0 Processor (CPU1, 0x0[b]1[/b], 0x00000410, 0x06) { Name (_PPC, 0x00) Name (_PCT, Package (0x02) { ResourceTemplate () { Register (FFixedHW, // PERF_CTL 0x10, // Bit Width 0x00, // Bit Offset 0x0000000000000199, // Address ,) }, ResourceTemplate () { Register (FFixedHW, // PERF_STATUS 0x10, // Bit Width 0x00, // Bit Offset 0x0000000000000198, // Address ,) } }) Name (_PSS, Package (0x04) // 4 Pstates 6-9 fsb muilt { /* multi 10 OFF Package (0x06) { 3330, 93816, 10, 10, 0xA25, 0xA25 } */ Package (0x06) { 2997, 80535, 10, 10, 0x921, 0x921 }, // 2997 MHZ = 9* 333 Package (0x06) { 2664, 68120, 10, 10, 0x81D, 0x81D }, Package (0x06) { 2331, 56571, 10, 10, 0x71A, 0x71A }, Package (0x06) { 1998, 45889, 10, 10, 0x616, 0x616 } }) } // end CPU1 Processor (CPU2, 0x02, 0x00000410, 0x06) { } // end CPU2 Processor (CPU3, 0x03, 0x00000410, 0x06) { } // end CPU3 } i also included SSDT-0 unchanged!! for later editing (i only have one SSDT Table with GA-EP35-DS3) at the end of the dsdt.dsl I dont know really whats that stuff , but i believe they are the C-States. ......... Device (PCI0.EXPL) { Name (_HID, EisaId ("PNP0C02")) Name (_UID, 0x04) Method (_CRS, 0, NotSerialized) { Name (BUF0, ResourceTemplate () { Memory32Fixed (ReadWrite, 0xF0000000, // Address Base 0x04000000, // Address Length ) }) Return (BUF0) } } } [b]// NEW in dsdt[/b] Scope (\) { Name (SSDT, Package (0x18) { "CPU0IST ", 0xDFEE7F00, 0x026C, "CPU1IST ", 0xDFEE83C0, 0x0152, "CPU0CST ", Zero, 0xF000E816, "CPU1CST ", // 10 Zero, 0xF000E816, "CPU2IST ", Zero, 0xF000E816, "CPU3IST ", Zero, 0xF000E816, "CPU2CST ", Zero, // 20 0xF000E816, "CPU3CST ", Zero, 0xF000E816 }) Name (CFGD, 0x02030302) Name (\PDC0, 0x80000000) Name (\PDC1, 0x80000000) Name (\PDC2, 0x80000000) Name (\PDC3, 0x80000000) } Scope (\_PR.CPU0) { Name (HI0, Zero) Name (HC0, Zero) Name (TLD0, Zero) Method (_PDC, 1, NotSerialized) { CreateDWordField (Arg0, 0x08, CAP0) Store (CAP0, PDC0) If (LEqual (TLD0, Zero)) { If (LEqual (And (PDC0, 0x0A), 0x0A)) { If (And (CFGD, 0x02)) { OperationRegion (IST0, SystemMemory, DerefOf (Index (SSDT, One)), DerefOf (Index (SSDT, 0x02 ))) Load (IST0, HI0) } If (And (CFGD, 0x10)) { OperationRegion (CST0, SystemMemory, DerefOf (Index (SSDT, 0x07)), DerefOf (Index (SSDT, 0x08 ))) Load (CST0, HC0) } Store (One, TLD0) } } } } Scope (\_PR.CPU1) { Name (HI1, Zero) Name (HC1, Zero) Name (TLD1, Zero) Method (_PDC, 1, NotSerialized) { CreateDWordField (Arg0, 0x08, CAP1) Store (CAP1, PDC1) If (LEqual (TLD1, Zero)) { If (LEqual (And (PDC1, 0x0A), 0x0A)) { If (And (CFGD, 0x02)) { OperationRegion (IST1, SystemMemory, DerefOf (Index (SSDT, 0x04)), DerefOf (Index (SSDT, 0x05 ))) Load (IST1, HI1) } If (And (CFGD, 0x10)) { OperationRegion (CST1, SystemMemory, DerefOf (Index (SSDT, 0x0A)), DerefOf (Index (SSDT, 0x0B ))) Load (CST1, HC1) } Store (One, TLD1) } } } } Scope (\_PR.CPU2) { Name (HI2, Zero) Name (HC2, Zero) Name (TLD2, Zero) Method (_PDC, 1, NotSerialized) { CreateDWordField (Arg0, 0x08, CAP2) Store (CAP2, PDC2) If (LEqual (TLD2, Zero)) { If (LEqual (And (PDC2, 0x0A), 0x0A)) { If (And (CFGD, 0x02)) { OperationRegion (IST2, SystemMemory, DerefOf (Index (SSDT, 0x0D)), DerefOf (Index (SSDT, 0x0E ))) Load (IST2, HI2) } If (And (CFGD, 0x10)) { OperationRegion (CST2, SystemMemory, DerefOf (Index (SSDT, 0x13)), DerefOf (Index (SSDT, 0x14 ))) Load (CST2, HC2) } Store (One, TLD2) } } } } Scope (\_PR.CPU3) { Name (HI3, Zero) Name (HC3, Zero) Name (TLD3, Zero) Method (_PDC, 1, NotSerialized) { CreateDWordField (Arg0, 0x08, CAP3) Store (CAP3, PDC3) If (LEqual (TLD3, Zero)) { If (LEqual (And (PDC3, 0x0A), 0x0A)) { If (And (CFGD, 0x02)) { OperationRegion (IST3, SystemMemory, DerefOf (Index (SSDT, 0x10)), DerefOf (Index (SSDT, 0x11 ))) Load (IST3, HI3) } If (And (CFGD, 0x10)) { OperationRegion (CST3, SystemMemory, DerefOf (Index (SSDT, 0x16)), DerefOf (Index (SSDT, 0x17 ))) Load (CST3, HC3) } Store (One, TLD3) } } } } } // end of dsl Last but not least the part of USB looks like for my GA-Ep35-DS3 (F4 Bios) Device ([b]USB0[/b]) { Name (_ADR, 0x001D0000) Method (_S3D, 0, NotSerialized) { If (LEqual (OSFL, 0x02)) { Return (0x02) } Return (0x03) } Method (_DSM, 4, NotSerialized) { Store (Package (0x02) { "device-id", Buffer (0x04) { 0x34, 0x29, 0x00, 0x00 } }, Local0) DTGP (Arg0, Arg1, Arg2, Arg3, RefOf (Local0)) Return (Local0) } Name (_PRW, Package (0x02) { 0x03, 0x03 }) } Device (USB1) { Name (_ADR, 0x001D0001) Method (_S3D, 0, NotSerialized) { If (LEqual (OSFL, 0x02)) { Return (0x02) } Return (0x03) } Method (_DSM, 4, NotSerialized) { Store (Package (0x02) { "device-id", Buffer (0x04) { 0x35, 0x29, 0x00, 0x00 } }, Local0) DTGP (Arg0, Arg1, Arg2, Arg3, RefOf (Local0)) Return (Local0) } Name (_PRW, Package (0x02) { 0x04, 0x03 }) } Device (USB2) { Name (_ADR, 0x001D0002) Method (_S3D, 0, NotSerialized) { If (LEqual (OSFL, 0x02)) { Return (0x02) } Return (0x03) } Method (_DSM, 4, NotSerialized) { Store (Package (0x02) { "device-id", Buffer (0x04) { 0x36, 0x29, 0x00, 0x00 } }, Local0) DTGP (Arg0, Arg1, Arg2, Arg3, RefOf (Local0)) Return (Local0) } Name (_PRW, Package (0x02) { 0x0C, 0x03 }) } Device (US31) { Name (_ADR, 0x001D0003) Method (_S3D, 0, NotSerialized) { If (LEqual (OSFL, 0x02)) { Return (0x02) } Return (0x03) } Name (_PRW, Package (0x02) { 0x0E, 0x03 }) } Device (USB3) { Name (_ADR, 0x001A0000) Method (_S3D, 0, NotSerialized) { If (LEqual (OSFL, 0x02)) { Return (0x02) } Return (0x03) } Method (_DSM, 4, NotSerialized) { Store (Package (0x02) { "device-id", Buffer (0x04) { 0x37, 0x29, 0x00, 0x00 } }, Local0) DTGP (Arg0, Arg1, Arg2, Arg3, RefOf (Local0)) Return (Local0) } Name (_PRW, Package (0x02) { 0x0E, 0x03 }) } Device (USB4) { Name (_ADR, 0x001A0001) Method (_S3D, 0, NotSerialized) { If (LEqual (OSFL, 0x02)) { Return (0x02) } Return (0x03) } Method (_DSM, 4, NotSerialized) { Store (Package (0x02) { "device-id", Buffer (0x04) { 0x38, 0x29, 0x00, 0x00 } }, Local0) DTGP (Arg0, Arg1, Arg2, Arg3, RefOf (Local0)) Return (Local0) } Name (_PRW, Package (0x02) { 0x05, 0x03 }) } Device (USB5) { Name (_ADR, 0x001A0002) Method (_S3D, 0, NotSerialized) { If (LEqual (OSFL, 0x02)) { Return (0x02) } Return (0x03) } Method (_DSM, 4, NotSerialized) { Store (Package (0x02) { "device-id", Buffer (0x04) { 0x39, 0x29, 0x00, 0x00 } }, Local0) DTGP (Arg0, Arg1, Arg2, Arg3, RefOf (Local0)) Return (Local0) } Name (_PRW, Package (0x02) { 0x20, 0x03 }) } Device ([b]EHC1[/b]) { Name (_ADR, 0x001D0007) Method (_S3D, 0, NotSerialized) { If (LEqual (OSFL, 0x02)) { Return (0x02) } Return (0x03) } Method (_DSM, 4, NotSerialized) { Store (Package (0x06) { "AAPL,clock-id", Buffer (One) { 0x01 }, "device_type", Buffer (0x05) { "EHCI" }, "device-id", Buffer (0x04) { 0x3A, 0x29, 0x00, 0x00 } }, Local0) DTGP (Arg0, Arg1, Arg2, Arg3, RefOf (Local0)) Return (Local0) } Name (_PRW, Package (0x02) { 0x0D, 0x03 }) } Device ([b]EHC2[/b]) //name changed is cosmetic like HDEF also changed that notify.... { Name (_ADR, 0x001A0007) Method (_S3D, 0, NotSerialized) { If (LEqual (OSFL, 0x02)) { Return (0x02) } Return (0x03) } Method (_DSM, 4, NotSerialized) { Store (Package (0x06) { "AAPL,clock-id", Buffer (One) { 0x02 }, "device_type", Buffer (0x05) { "EHCI" }, "device-id", Buffer (0x04) { 0x3C, 0x29, 0x00, 0x00 } }, Local0) DTGP (Arg0, Arg1, Arg2, Arg3, RefOf (Local0)) Return (Local0) } Name (_PRW, Package (0x02) { 0x0D, 0x03 }) } P_States_Calculator.zip Link to comment Share on other sites More sharing options...
tuxianer Posted September 3, 2009 Share Posted September 3, 2009 @mitch_de does your computer wake up via keyboard or mouse? Link to comment Share on other sites More sharing options...
FKA Posted September 3, 2009 Share Posted September 3, 2009 Hi,i now made my PSTATES for GA-EP35-DS3 with C2D 7300/2.66 @ 3 GHZ (333 *9 insted 266*10). The problem with that GA is, that there are no P-States in the SSDT part of the bios - most other GA boards seems to have them. So you must use the override mode of voodoopower to get that worked. With that dsdt its possible not use that override mode of voodoopwoer, because now vp get the p_state tables from the dsdt patch. i also included SSDT-0 unchanged!! for later editing (i only have one SSDT Table with GA-EP35-DS3) at the end of the dsdt.dsl I dont know really whats that stuff , but i believe they are the C-States. ......... Device (PCI0.EXPL) { Name (_HID, EisaId ("PNP0C02")) Name (_UID, 0x04) Method (_CRS, 0, NotSerialized) { Name (BUF0, ResourceTemplate () { Memory32Fixed (ReadWrite, 0xF0000000, // Address Base 0x04000000, // Address Length ) }) Return (BUF0) } } } [b]// NEW in dsdt[/b] Scope (\) { Name (SSDT, Package (0x18) { "CPU0IST ", 0xDFEE7F00, 0x026C, "CPU1IST ", 0xDFEE83C0, 0x0152, "CPU0CST ", Zero, 0xF000E816, "CPU1CST ", // 10 Zero, 0xF000E816, "CPU2IST ", Zero, 0xF000E816, "CPU3IST ", Zero, 0xF000E816, "CPU2CST ", Zero, // 20 0xF000E816, "CPU3CST ", Zero, 0xF000E816 }) Name (CFGD, 0x02030302) Name (\PDC0, 0x80000000) Name (\PDC1, 0x80000000) Name (\PDC2, 0x80000000) Name (\PDC3, 0x80000000) } Scope (\_PR.CPU0) { Name (HI0, Zero) Name (HC0, Zero) Name (TLD0, Zero) Method (_PDC, 1, NotSerialized) { CreateDWordField (Arg0, 0x08, CAP0) Store (CAP0, PDC0) If (LEqual (TLD0, Zero)) { If (LEqual (And (PDC0, 0x0A), 0x0A)) { If (And (CFGD, 0x02)) { OperationRegion (IST0, SystemMemory, DerefOf (Index (SSDT, One)), DerefOf (Index (SSDT, 0x02 ))) Load (IST0, HI0) } If (And (CFGD, 0x10)) { OperationRegion (CST0, SystemMemory, DerefOf (Index (SSDT, 0x07)), DerefOf (Index (SSDT, 0x08 ))) Load (CST0, HC0) } Store (One, TLD0) } } } } Scope (\_PR.CPU1) { Name (HI1, Zero) Name (HC1, Zero) Name (TLD1, Zero) Method (_PDC, 1, NotSerialized) { CreateDWordField (Arg0, 0x08, CAP1) Store (CAP1, PDC1) If (LEqual (TLD1, Zero)) { If (LEqual (And (PDC1, 0x0A), 0x0A)) { If (And (CFGD, 0x02)) { OperationRegion (IST1, SystemMemory, DerefOf (Index (SSDT, 0x04)), DerefOf (Index (SSDT, 0x05 ))) Load (IST1, HI1) } If (And (CFGD, 0x10)) { OperationRegion (CST1, SystemMemory, DerefOf (Index (SSDT, 0x0A)), DerefOf (Index (SSDT, 0x0B ))) Load (CST1, HC1) } Store (One, TLD1) } } } } Scope (\_PR.CPU2) { Name (HI2, Zero) Name (HC2, Zero) Name (TLD2, Zero) Method (_PDC, 1, NotSerialized) { CreateDWordField (Arg0, 0x08, CAP2) Store (CAP2, PDC2) If (LEqual (TLD2, Zero)) { If (LEqual (And (PDC2, 0x0A), 0x0A)) { If (And (CFGD, 0x02)) { OperationRegion (IST2, SystemMemory, DerefOf (Index (SSDT, 0x0D)), DerefOf (Index (SSDT, 0x0E ))) Load (IST2, HI2) } If (And (CFGD, 0x10)) { OperationRegion (CST2, SystemMemory, DerefOf (Index (SSDT, 0x13)), DerefOf (Index (SSDT, 0x14 ))) Load (CST2, HC2) } Store (One, TLD2) } } } } Scope (\_PR.CPU3) { Name (HI3, Zero) Name (HC3, Zero) Name (TLD3, Zero) Method (_PDC, 1, NotSerialized) { CreateDWordField (Arg0, 0x08, CAP3) Store (CAP3, PDC3) If (LEqual (TLD3, Zero)) { If (LEqual (And (PDC3, 0x0A), 0x0A)) { If (And (CFGD, 0x02)) { OperationRegion (IST3, SystemMemory, DerefOf (Index (SSDT, 0x10)), DerefOf (Index (SSDT, 0x11 ))) Load (IST3, HI3) } If (And (CFGD, 0x10)) { OperationRegion (CST3, SystemMemory, DerefOf (Index (SSDT, 0x16)), DerefOf (Index (SSDT, 0x17 ))) Load (CST3, HC3) } Store (One, TLD3) } } } } } // end of dsl NIce one mitch - I like the way you've added p-states as roisoft has posted before - it looks a lot tidier ! Any ideas about c-states? - I've kind of given up here! D. @mitch_de does your computer wake up via keyboard or mouse? Are you USB or PS2 keyboard and mouse? Link to comment Share on other sites More sharing options...
tuxianer Posted September 3, 2009 Share Posted September 3, 2009 I have a Logitech USB mouse for USB1 and the apple alu keyboard which uses USB2. Link to comment Share on other sites More sharing options...
FKA Posted September 3, 2009 Share Posted September 3, 2009 I have a Logitech USB mouse for USB1 and the apple alu keyboard which uses USB2. Ok silly question but do you have USB keyboard and Mouse support enabled in BIOS? I know this shouldn't make any difference (LAN related) but also try enabling PME Event wake up. EDit - also even using the latest DSDT USB patch, I'm still having to use slice's USBFamily kext to achieve deep sleep - have you tried that yet? D. Link to comment Share on other sites More sharing options...
mitch_de Posted September 3, 2009 Share Posted September 3, 2009 @mitch_de does your computer wake up via keyboard or mouse? No my system cant sleep - fans stay on , all running. Only HDs go to sleep & the monitor. Sleep had never worked on my GA_EP35-DS3 (without DSDT/with DSDT. OpenHaltRestart / SLeepenabler,...). May be an problem of SATA Pioinieer DVD or something other hardware else. But doenst matter for me. So i dont use sleep and have also no problem for wakeup Link to comment Share on other sites More sharing options...
tuxianer Posted September 3, 2009 Share Posted September 3, 2009 Ok silly question but do you have USB keyboard and Mouse support enabled in BIOS? I know this shouldn't make any difference (LAN related) but also try enabling PME Event wake up. EDit - also even using the latest DSDT USB patch, I'm still having to use slice's USBFamily kext to achieve deep sleep - have you tried that yet? D. All 3 settings are enabled. The USB kext I didn't tried yet. I am running 10.5.6 could this the problem? Link to comment Share on other sites More sharing options...
FKA Posted September 3, 2009 Share Posted September 3, 2009 All 3 settings are enabled. The USB kext I didn't tried yet. I am running 10.5.6 could this the problem? Try slice's kext but it looks like mitch_de has problem with the same MB. I can deep sleep and wake up with USB mouse and keyboard but monitor doesn't power up, although I think this is a problem with my GPU rather than anything else. 10.5.6 shouldn't be a problem as a lot of people who had sleep have lost it since upgrade to 10.5.8 D. Link to comment Share on other sites More sharing options...
tuxianer Posted September 3, 2009 Share Posted September 3, 2009 Try slice's kext but it looks like mitch_de has problem with the same MB. I can deep sleep and wake up with USB mouse and keyboard but monitor doesn't power up, although I think this is a problem with my GPU rather than anything else. 10.5.6 shouldn't be a problem as a lot of people who had sleep have lost it since upgrade to 10.5.8 D. I tried the USB kext without success. But I think sleep with your mainboard should be possible. Which kexts do you have installed? Link to comment Share on other sites More sharing options...
alborto Posted September 4, 2009 Share Posted September 4, 2009 Hi, I tried the method on a P5K-se (P35 ICH9) who didn't want to wake after sleep but now with the fix it wakes immediatly after sleep and restart doesn't work anymore. I tried this metod and work great for me the only problem is the restart that take me on black screen for about one minute. Anyone have a solution for it? I use openhaltrestart just right now. Thanks in advance. Link to comment Share on other sites More sharing options...
tuxianer Posted September 4, 2009 Share Posted September 4, 2009 Hi, I have got a working wake up by mouse. The problem is the following: You have to change this Name (_PRW, Package (0x02) { 0x0D, One }) to this Name (_PRW, Package (0x02) { 0x0D, 0x03 }) But this works only with USB1 Devices. I can't wake up with my USB2 Keyboard. Link to comment Share on other sites More sharing options...
tuxianer Posted September 4, 2009 Share Posted September 4, 2009 And when I inject my SATA IDs is there no IOATAFamily.kext necessary to boot without ahci? Link to comment Share on other sites More sharing options...
FKA Posted September 5, 2009 Share Posted September 5, 2009 Here's ICH10 SATA part of DSDT, working on my ICH9-R. Should also work ICH9. Note: my SATA ports where previously listed as IDE in DSDT and IOReg, this was taken from DSE and ICH10 id from this thread thanks to rx782p. Device (SATA) { Name (_ADR, 0x001F0002) Name (_SUN, One) Device (PRT0) { Name (_ADR, Zero) Method (_GTF, 0, NotSerialized) { Name (PIB0, Buffer (0x07) { 0x00, 0x00, 0x00, 0x00, 0x00, 0xA0, 0xF5 }) Return (PIB0) } Method (_DSM, 4, NotSerialized) { Store (Package (0x02) { "io-device-location", Buffer (0x06) { "Bay 1" } }, Local0) DTGP (Arg0, Arg1, Arg2, Arg3, RefOf (Local0)) Return (Local0) } } Device (PRT1) { Name (_ADR, One) Method (_GTF, 0, NotSerialized) { Name (PIB1, Buffer (0x07) { 0x00, 0x00, 0x00, 0x00, 0x00, 0xB0, 0xF5 }) Return (PIB1) } Method (_DSM, 4, NotSerialized) { Store (Package (0x02) { "io-device-location", Buffer (0x06) { "Bay 2" } }, Local0) DTGP (Arg0, Arg1, Arg2, Arg3, RefOf (Local0)) Return (Local0) } } Device (PRT2) { Name (_ADR, 0x02) Method (_GTF, 0, NotSerialized) { Name (PIB2, Buffer (0x07) { 0x00, 0x00, 0x00, 0x00, 0x00, 0xA0, 0xF5 }) Return (PIB2) } Method (_DSM, 4, NotSerialized) { Store (Package (0x02) { "io-device-location", Buffer (0x06) { "Bay 3" } }, Local0) DTGP (Arg0, Arg1, Arg2, Arg3, RefOf (Local0)) Return (Local0) } } Device (PRT3) { Name (_ADR, 0x03) Method (_GTF, 0, NotSerialized) { Name (PIB3, Buffer (0x07) { 0x00, 0x00, 0x00, 0x00, 0x00, 0xB0, 0xF5 }) Return (PIB3) } Method (_DSM, 4, NotSerialized) { Store (Package (0x02) { "io-device-location", Buffer (0x06) { "Bay 4" } }, Local0) DTGP (Arg0, Arg1, Arg2, Arg3, RefOf (Local0)) Return (Local0) } } Device (PRT4) { Name (_ADR, 0x04) Method (_GTF, 0, NotSerialized) { Name (PIB4, Buffer (0x07) { 0x00, 0x00, 0x00, 0x00, 0x00, 0xA0, 0xF5 }) Return (PIB4) } Method (_DSM, 4, NotSerialized) { Store (Package (0x02) { "io-device-location", Buffer (0x06) { "Bay 5" } }, Local0) DTGP (Arg0, Arg1, Arg2, Arg3, RefOf (Local0)) Return (Local0) } } Device (PRT5) { Name (_ADR, 0x05) Method (_GTF, 0, NotSerialized) { Name (PIB5, Buffer (0x07) { 0x00, 0x00, 0x00, 0x00, 0x00, 0xB0, 0xF5 }) Return (PIB5) } Method (_DSM, 4, NotSerialized) { Store (Package (0x02) { "io-device-location", Buffer (0x06) { "Bay 6" } }, Local0) DTGP (Arg0, Arg1, Arg2, Arg3, RefOf (Local0)) Return (Local0) } } Method (_DSM, 4, NotSerialized) { Store (Package (0x02) { "device-id", Buffer (0x04) { 0x22, 0x3A, 0x00, 0x00 } }, Local0) DTGP (Arg0, Arg1, Arg2, Arg3, RefOf (Local0)) Return (Local0) } } No need for AHCIPortinjector. Is it possible to state HDD's are internal with DSDT? D. Link to comment Share on other sites More sharing options...
kdawg Posted September 5, 2009 Share Posted September 5, 2009 Here's ICH10 SATA part of DSDT, working on my ICH9-R. Should also work ICH9. Note: my SATA ports where previously listed as IDE in DSDT and IOReg, this was taken from DSE and ICH10 id from this thread thanks to rx782p. Device (SATA) { Name (_ADR, 0x001F0002) Name (_SUN, One) Device (PRT0) { Name (_ADR, Zero) Method (_GTF, 0, NotSerialized) { Name (PIB0, Buffer (0x07) { 0x00, 0x00, 0x00, 0x00, 0x00, 0xA0, 0xF5 }) Return (PIB0) } Method (_DSM, 4, NotSerialized) { Store (Package (0x02) { "io-device-location", Buffer (0x06) { "Bay 1" } }, Local0) DTGP (Arg0, Arg1, Arg2, Arg3, RefOf (Local0)) Return (Local0) } } Device (PRT1) { Name (_ADR, One) Method (_GTF, 0, NotSerialized) { Name (PIB1, Buffer (0x07) { 0x00, 0x00, 0x00, 0x00, 0x00, 0xB0, 0xF5 }) Return (PIB1) } Method (_DSM, 4, NotSerialized) { Store (Package (0x02) { "io-device-location", Buffer (0x06) { "Bay 2" } }, Local0) DTGP (Arg0, Arg1, Arg2, Arg3, RefOf (Local0)) Return (Local0) } } Device (PRT2) { Name (_ADR, 0x02) Method (_GTF, 0, NotSerialized) { Name (PIB2, Buffer (0x07) { 0x00, 0x00, 0x00, 0x00, 0x00, 0xA0, 0xF5 }) Return (PIB2) } Method (_DSM, 4, NotSerialized) { Store (Package (0x02) { "io-device-location", Buffer (0x06) { "Bay 3" } }, Local0) DTGP (Arg0, Arg1, Arg2, Arg3, RefOf (Local0)) Return (Local0) } } Device (PRT3) { Name (_ADR, 0x03) Method (_GTF, 0, NotSerialized) { Name (PIB3, Buffer (0x07) { 0x00, 0x00, 0x00, 0x00, 0x00, 0xB0, 0xF5 }) Return (PIB3) } Method (_DSM, 4, NotSerialized) { Store (Package (0x02) { "io-device-location", Buffer (0x06) { "Bay 4" } }, Local0) DTGP (Arg0, Arg1, Arg2, Arg3, RefOf (Local0)) Return (Local0) } } Device (PRT4) { Name (_ADR, 0x04) Method (_GTF, 0, NotSerialized) { Name (PIB4, Buffer (0x07) { 0x00, 0x00, 0x00, 0x00, 0x00, 0xA0, 0xF5 }) Return (PIB4) } Method (_DSM, 4, NotSerialized) { Store (Package (0x02) { "io-device-location", Buffer (0x06) { "Bay 5" } }, Local0) DTGP (Arg0, Arg1, Arg2, Arg3, RefOf (Local0)) Return (Local0) } } Device (PRT5) { Name (_ADR, 0x05) Method (_GTF, 0, NotSerialized) { Name (PIB5, Buffer (0x07) { 0x00, 0x00, 0x00, 0x00, 0x00, 0xB0, 0xF5 }) Return (PIB5) } Method (_DSM, 4, NotSerialized) { Store (Package (0x02) { "io-device-location", Buffer (0x06) { "Bay 6" } }, Local0) DTGP (Arg0, Arg1, Arg2, Arg3, RefOf (Local0)) Return (Local0) } } Method (_DSM, 4, NotSerialized) { Store (Package (0x02) { "device-id", Buffer (0x04) { 0x22, 0x3A, 0x00, 0x00 } }, Local0) DTGP (Arg0, Arg1, Arg2, Arg3, RefOf (Local0)) Return (Local0) } } No need for AHCIPortinjector. Is it possible to state HDD's are internal with DSDT? D. I've been trying to do exactly that for days now! You would think IOAHCIBlockStorageInjector.kext would be any easy one to get rid of, but I haven't had any luck. I've download the IOStorageFamily opensource files from Apple and poured through the code. I've found the key (IOPropertyPhysicalInterconnectTypeSerialATA = 0x01) that needs to be tripped but I can't do it through DSDT. I've even tried to force the Physical Interconnect/Location properties but no luck: Device (PRT2) { Name (_ADR, 0x02) Method (_DSM, 4, NotSerialized) { Store (Package (0x08) { "Physical Interconnect", "SATA", "Physical Interconnect Location", "Internal", Buffer (0x01) { 0x00 } }, Local0) DTGP (Arg0, Arg1, Arg2, Arg3, RefOf (Local0)) Return (Local0) } } Anyone else want to chime in on this one? ApexDE? BTW I chatted with ApexDE and he was able to find the EHCI fix by looking at the opensource code. The developers had commented plain as day what needed to appear for EHCI to display as internal. I was hoping I could do the same with IOStorageFamily. This is a great tip for anyone wanting to learn more about DSDT editing. http://www.opensource.apple.com/ Link to comment Share on other sites More sharing options...
ApexDE Posted September 5, 2009 Share Posted September 5, 2009 Hi! Buffer (0x01) { 0x00 } But i guess this should be 0x01 then, not 0x00? (True/False) Link to comment Share on other sites More sharing options...
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