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Chameleon bootloader with SSDT and DSDT override


ab___73
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I have tried the patcher and I only get 2 files; SSDT-0 and SSDT-1.

Also, as trauma has pointed out, the bootloader does NOT support /Extra folder. I just found out the hard way.

I haven't tried loading the SSDT yet because I have to put the kexts in the extensions folder first.

 

My SSDT is attached below for anyone interested.

SSDT_GA_945GCM_S2L.zip

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I have tried the patcher and I only get 2 files; SSDT-0 and SSDT-1.

Also, as trauma has pointed out, the bootloader does NOT support /Extra folder. I just found out the hard way.

I haven't tried loading the SSDT yet because I have to put the kexts in the extensions folder first.

 

My SSDT is attached below for anyone interested.

 

@Dr Hurt

 

Could you post your DSDT file, it might help me fix a lot of dual core problems.

 

Once I've tidied up my code i'll post the source so that Netkas can implement it in the next netkas release.

I'm planning on doing this tomorrow.

 

Thanks in advance.

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Thanks very much for the dumps.

 

How did you extract the ssdt from the MP3.1?

It seems to be very different from normal i.e. 20 tables?

This dump even contains the cst (cstates) and ist (pstates) that are usually hard coded into the memory of the BIOS?

I would be very interested in the dsdt from the MP3.1, could you provide this also?

 

Thanks for your help. Great work (as always :) )!!

 

--

AB

Other MBP SSDT table have 2 cores support (0,1).

This one has 8 cores support (0,1,2,3,4,5,6,7).

Since there is 2 table for each CPU, there is lot of table and it's normal.

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ab___73

 

My dream will be to have bootloader that supports all the latest features: DSDT override, SSDT override, Extra folder (so I will not have to mix additional kexts with system ones) and of course the most important for me SMBIOS override. I think it could be an universal bootloader for everyone.

 

SMBIOS override is so critical to me because I do not like AppleSMBIOSEFI or other injectors as they inject info they find somewhere and I want the ability to modify it (to write the right type and speed for my memory, add a serial, inject hardware vendors info and of course name my hack "MacPro 3,1")

 

See if you can try to do this or simply add these options to your bootloader.

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ab___73

 

My dream will be to have bootloader that supports all the latest features: DSDT override, SSDT override, Extra folder (so I will not have to mix additional kexts with system ones) and of course the most important for me SMBIOS override. I think it could be an universal bootloader for everyone.

 

SMBIOS override is so critical to me because I do not like AppleSMBIOSEFI or other injectors as they inject info they find somewhere and I want the ability to modify it (to write the right type and speed for my memory, add a serial, inject hardware vendors info and of course name my hack "MacPro 3,1")

 

See if you can try to do this or simply add these options to your bootloader.

 

I share your dream, and will look into this...

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New version uploaded, see start of topic.

Thanks, we test the new version.

 

I wonder if anyone knows anything about the boot filesize restriction?

This restriction seems to it's possible to bypass, someone already wrote about it, probably david elliot?

It is very a pity that other gurus do not support the joint project. For a common cause!

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Thanks, we test the new version.

 

 

This restriction seems to it's possible to bypass, someone already wrote about it, probably david elliot?

It is very a pity that other gurus do not support the joint project. For a common cause!

 

Thanks for the hint:

 

articles/time-to-grow-up

 

Hmm, this could be possible!!

;)

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with new version 5 files SSDT is out and they are loaded properly!

iDQ965GFdsdt_ssdt_v2.zip

Have a question. My e6300 processor supports only two pstates speedstep. min-max multiplier 6x/7x. It makes sense to do SSDT?

I tried genericcpupowerman.

When playing a movie(mpeg4), with frequency in few seconds jump voltage,and it lasts about an hour and a half). This is to display in the utility. I do not know how it is harmful to health and the normal functioning of the processor, the constant switching power surges.

and yet I have errors, which I do not know how to fix(

 sudo dmesg | grep ACPI
ACPI_SMC_PlatformPlugin::pushCPU_CSTData - _CST evaluation failed
ACPI_SMC_PlatformPlugin::registerLPCDriver - WARNING - LPC device initialization failed: C-state power management not initialized
ACPI_SMC_PlatformPlugin::pushCPU_CSTData - _CST evaluation failed

Thx

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I did load a SSDT-1.aml (C-States control) from a Macbook and changed it to SSDT-3 (Where my Vaio has it´s C-States) , first time it loaded, it complained as the user 1 post ago:

 

Jan 14 17:59:53 Pere-osx kernel[0]: ACPI_SMC_PlatformPlugin::pushCPU_CSTData - _CST evaluation failed

Jan 14 17:59:53 Pere-osx kernel[0]: ACPI_SMC_PlatformPlugin::registerLPCDriver - WARNING - LPC device initialization failed: C-state power management not initialized

 

I opened the .dsl from the macbook and changed this:

 

"CPU0IST ",

0xBEEC9A98,

0x000002FE,

"CPU1IST ",

0xBEEC8F18,

0x000000C8,

"CPU0CST ",

0xBEEC7C98,

0x00000222,

"CPU1CST ",

0xBEEC7F18,

0x00000085

 

Into my real information:

 

"CPU0IST ",

0x7FED95F4,

0x00000238,

"CPU1IST ",

0x7FED982C,

0x000000C8,

"CPU0CST ",

0x7FED90D7,

0x00000498,

"CPU1CST ",

0x7FED956F,

0x00000085

 

And it worked perfectly for my C-States...

 

I will keep porting the Macbook SSDT to my Sony Vaio SSDT and see what can i get.

I did use the debug version so i could see the messages.

 

EDIT: I did compare all tables and found all of them are Equal from Macbook to Sony Vaio Cr11Z, the only differences i found:

 

SSDT-0 : Vaio table includes two AHCI ports, Macbook, just one

SSDT-1 (Vaio) SSDT-3 (Macbook), CPU C-States registers were different (as different processors must be).

 

So no solution to shutdown for Sony Vaio on SSDT tables, just an improvement on C-States.

 

I have attached al SSDT tables from Macbook...

 

Looking forward for next version. :)

 

Thanks ab____73.

SSDT_Macbook.zip

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with new version 5 files SSDT is out and they are loaded properly!

iDQ965GFdsdt_ssdt_v2.zip

Have a question. My e6300 processor supports only two pstates speedstep. min-max multiplier 6x/7x. It makes sense to do SSDT?

I tried genericcpupowerman.

When playing a movie(mpeg4), with frequency in few seconds jump voltage,and it lasts about an hour and a half). This is to display in the utility. I do not know how it is harmful to health and the normal functioning of the processor, the constant switching power surges.

and yet I have errors, which I do not know how to fix(

 sudo dmesg | grep ACPI
ACPI_SMC_PlatformPlugin::pushCPU_CSTData - _CST evaluation failed
ACPI_SMC_PlatformPlugin::registerLPCDriver - WARNING - LPC device initialization failed: C-state power management not initialized
ACPI_SMC_PlatformPlugin::pushCPU_CSTData - _CST evaluation failed

Thx

 

I've looked at your dumps (thanks), I found no cst tables in them.

 

When I dump the SSDT tables from my Laptop (HP530) I find CStates in the SSDT tables.

When I dump the SSDT tables from my Desktop (Gigabyte P45) I find no CStates.

That might explain the lack of CStates on your motherboard.

 

the constant switching power surges

 

GenericCPUPM has a latency setting that can be changed. This setting changes the frequency between PState (SpeedStep) changes. If you are worried i would set this according to your requirements. Although a greater latency might give degrade the performance of your processor, since it will take longer to detect the CPU load.

 

I'm working on another version of the bootloader that allows other modified BIOS tables to get loaded. I've found an entry in the FACP table which might explain CState Problems:

 

[000h 000  4]                    Signature : "FACP"    /* Fixed ACPI Description Table */
[004h 004  4]                 Table Length : 000000F4
[008h 008  1]                     Revision : 04
[009h 009  1]                     Checksum : E8     /* Incorrect checksum, should be E6 */
[00Ah 010  6]                       Oem ID : "APPLE "
[010h 016  8]                 Oem Table ID : "Apple00 "
[018h 024  4]                 Oem Revision : 0000005C
[01Ch 028  4]              Asl Compiler ID : "Loki"
[020h 032  4]        Asl Compiler Revision : 0000005F

[024h 036  4]                 FACS Address : 7FAC5000
[028h 040  4]                 DSDT Address : 7FBAE000
[02Ch 044  1]                        Model : 00
[02Dh 045  1]                   PM Profile : 03
[02Eh 046  2]                SCI Interrupt : 0009
[030h 048  4]             SMI Command Port : 000000B2
[034h 052  1]            ACPI Enable Value : A0
[035h 053  1]           ACPI Disable Value : A1
[036h 054  1]               S4BIOS Command : 00
[037h 055  1]              P-State Control : 00
[038h 056  4]     PM1A Event Block Address : 00000400
[03Ch 060  4]     PM1B Event Block Address : 00000000
[040h 064  4]   PM1A Control Block Address : 00000404
[044h 068  4]   PM1B Control Block Address : 00000000
[048h 072  4]    PM2 Control Block Address : 00000000
[04Ch 076  4]       PM Timer Block Address : 00000408
[050h 080  4]           GPE0 Block Address : 00000428
[054h 084  4]           GPE1 Block Address : 00000000
[058h 088  1]       PM1 Event Block Length : 04
[059h 089  1]     PM1 Control Block Length : 02
[05Ah 090  1]     PM2 Control Block Length : 00
[05Bh 091  1]        PM Timer Block Length : 04
[05Ch 092  1]            GPE0 Block Length : 08
[05Dh 093  1]            GPE1 Block Length : 00
[05Eh 094  1]             GPE1 Base Offset : 20
[05Fh 095  1]                 _CST Support : 00
[060h 096  2]                   C2 Latency : 0065
[062h 098  2]                   C3 Latency : 03E9
[064h 100  2]               CPU Cache Size : 0000
[066h 102  2]           Cache Flush Stride : 0000
[068h 104  1]            Duty Cycle Offset : 01
[069h 105  1]             Duty Cycle Width : 00
[06Ah 106  1]          RTC Day Alarm Index : 0D
[06Bh 107  1]        RTC Month Alarm Index : 00
[06Ch 108  1]            RTC Century Index : 32
[06Dh 109  2]      Boot Architecture Flags : 0000
[06Fh 111  1]                     Reserved : 00
[070h 112  4]        Flags (decoded below) : 000004A5
                    WBINVD is operational : 1
               WBINVD does not invalidate : 0
                      All CPUs support C1 : 1
                    C2 works on MP system : 0
                  Power button is generic : 0
                  Sleep button is generic : 1
                     RTC wakeup not fixed : 0
               RTC wakeup/S4 not possible : 1
                          32-bit PM Timer : 0
                        Docking Supported : 0
                 Reset Register Supported : 1
                              Sealed Case : 0
                      Headless - No Video : 0
               Native instr after SLP_TYP : 0
                     PCIEXP_WAK Supported : 0
                       Use Platform Timer : 0
                   RTC_STS valid after S4 : 0
                  Remote Power-on capable : 0
                       APIC Cluster Model : 0
                  APIC Physical Dest Mode : 0

 

Hope this helps!

 

AB

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the constant switching power surges

 

GenericCPUPM has a latency setting that can be changed. This setting changes the frequency between PState (SpeedStep) changes. If you are worried i would set this according to your requirements. Although a greater latency might give degrade the performance of your processor, since it will take longer to detect the CPU load.

Thanks. Now, in normal operation my desktop burn stone to 42 C, and keeping 48C when i'm coding videosource

 

I'm working on another version of the bootloader that allows other modified BIOS tables to get loaded. I've found an entry in the FACP table which might explain CState Problems:

from my mb FACP table

FACP.zip

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